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r44641 Wednesday 3rd February, 2016 at 04:08:33 UTC by Brandon Munger
r9751: Fix offset switching and enable write mask logging

[src/mame/drivers]

r9751.cpp

trunk/src/mame/drivers/r9751.cpp

r253152	r253153
156	156	READ32_MEMBER( r9751_state::r9751_mmio_5ff_r )
157	157	{
158	158	UINT32 data;
159		UINT32 address = offset * 4 + 0x5FF00000;
160	159
161		switch(address)
	160	switch(offset << 2)
162	161	{
163	162	/* PDC HDD region (0x24, device 9) */
164		case 0x5FF00824: /* HDD Command result code */
	163	case 0x0824: /* HDD Command result code */
165	164	return 0x10;
166		case 0x5FF03024: /* HDD SCSI command completed successfully */
	165	case 0x3024: /* HDD SCSI command completed successfully */
167	166	data = 0x1;
168		if(TRACE_HDC) logerror("SCSI HDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
	167	if(TRACE_HDC) logerror("SCSI HDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
169	168	return data;
170	169	/* SMIOC region (0x98, device 26) */
171		case 0x5FF00898: /* Serial status or DMA status */
	170	case 0x0898: /* Serial status or DMA status */
172	171	return 0x40;
173	172	/* PDC FDD region (0xB0, device 44 */
174		case 0x5FF008B0: /* FDD Command result code */
	173	case 0x08B0: /* FDD Command result code */
175	174	return 0x10;
176		case 0x5FF010B0: /* Clear 5FF030B0 ?? */
	175	case 0x10B0: /* Clear 5FF030B0 ?? */
177	176	if(TRACE_FDC) logerror("--- FDD 0x5FF010B0 READ (0)\n");
178	177	return 0;
179		case 0x5FF030B0: /* FDD command completion status */
	178	case 0x30B0: /* FDD command completion status */
180	179	data = (m_pdc->reg_p5 << 8) + m_pdc->reg_p4;
181		if(TRACE_FDC) logerror("--- SCSI FDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
	180	if(TRACE_FDC) logerror("--- SCSI FDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
182	181	return data;
183	182	default:
184		if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, 0, mem_mask);
	183	if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000, 0, mem_mask);
185	184	return 0;
186	185	}
187	186	}
r253152	r253153
189	188	WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
190	189	{
191	190	UINT8 data_b0, data_b1;
192		UINT32 address = offset * 4 + 0x5FF00000;
	191	/* Unknown mask */
	192	if (mem_mask != 0xFFFFFFFF)
	193	logerror("Mask found: %08X Register: %08X PC: %08X\n", mem_mask, offset << 2 | 0x5FF00000, space.machine().firstcpu->pc());
193	194
194		switch(address)
	195	switch(offset << 2)
195	196	{
196	197	/* PDC HDD region (0x24, device 9 */
197		case 0x5FF00224: /* HDD SCSI read command */
198		if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
	198	case 0x0224: /* HDD SCSI read command */
	199	if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
199	200	break;
200		case 0x5FF08024: /* HDD SCSI read command */
201		if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
	201	case 0x8024: /* HDD SCSI read command */
	202	if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
202	203	break;
203		case 0x5FF0C024: /* HDD SCSI read command */
204		if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
	204	case 0xC024: /* HDD SCSI read command */
	205	if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
205	206	break;
206	207	/* SMIOC region (0x98, device 26) */
207		case 0x5FF04098: /* Serial DMA Command */
	208	case 0x4098: /* Serial DMA Command */
208	209	switch(data)
209	210	{
210	211	case 0x4100: /* Send byte to serial */
r253152	r253153
215	216	if(TRACE_SMIOC) logerror("Uknown serial DMA command: %X\n", data);
216	217	}
217	218	break;
218		case 0x5FF0C098: /* Serial DMA output address */
	219	case 0xC098: /* Serial DMA output address */
219	220	//smioc_out_addr = data * 2;
220	221	smioc_out_addr = (smioc_dma_bank & 0x7FFFF800) | ((data&0x3FF)<<1);
221	222	if(TRACE_SMIOC) logerror("Serial output address: %08X PC: %08X\n", smioc_out_addr, space.machine().firstcpu->pc());
222	223	break;
223	224	/* PDC FDD region (0xB0, device 44 */
224		case 0x5FF001B0: /* FDD SCSI read command */
225		if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
	225	case 0x01B0: /* FDD SCSI read command */
	226	if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
226	227	break;
227		case 0x5FF002B0: /* FDD SCSI read command */
228		if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
	228	case 0x02B0: /* FDD SCSI read command */
	229	if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
229	230	break;
230		case 0x5FF004B0: /* FDD RESET PDC */
	231	case 0x04B0: /* FDD RESET PDC */
231	232	if(TRACE_FDC) logerror("PDC RESET, PC: %08X\n", space.machine().firstcpu->pc());
232	233	m_pdc->reset();
233	234	break;
234		case 0x5FF008B0: /* FDD SCSI read command */
235		if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
	235	case 0x08B0: /* FDD SCSI read command */
	236	if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
236	237	break;
237		case 0x5FF041B0: /* Unknown - Probably old style commands */
238		if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
	238	case 0x41B0: /* Unknown - Probably old style commands */
	239	if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
239	240
240	241	/* Clear FDD Command completion status 0x5FF030B0 (PDC 0x4, 0x5) */
241	242	m_pdc->reg_p4 = 0;
r253152	r253153
248	249	m_pdc->reg_p38 |= 0x2; /* Set bit 1 on port 38 register, PDC polls this port looking for a command */
249	250	if(TRACE_FDC) logerror("--- FDD Old Command: %02X and %02X\n", data_b0, data_b1);
250	251	break;
251		case 0x5FF080B0: /* fdd_dest_address register */
	252	case 0x80B0: /* fdd_dest_address register */
252	253	fdd_dest_address = data << 1;
253	254	if(TRACE_FDC) logerror("--- FDD destination address: %08X\n", fdd_dest_address);
254	255	data_b0 = data & 0xFF;
r253152	r253153
256	257	m_pdc->reg_p6 = data_b0;
257	258	m_pdc->reg_p7 = data_b1;
258	259	break;
259		case 0x5FF0C0B0:
260		case 0x5FF0C1B0: /* FDD command address register */
	260	case 0xC0B0:
	261	case 0xC1B0: /* FDD command address register */
261	262	UINT32 fdd_scsi_command;
262	263	UINT32 fdd_scsi_command2;
263	264	unsigned char c_fdd_scsi_command[8]; // Array for SCSI command
r253152	r253153
296	297	break;
297	298
298	299	default:
299		if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
	300	if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000, data, mem_mask);
300	301	}
301	302	}
302	303
r253152	r253153
306	307	READ32_MEMBER( r9751_state::r9751_mmio_ff01_r )
307	308	{
308	309	//UINT32 data;
309		UINT32 address = offset * 4 + 0xFF010000;
310	310
311		switch(address)
	311	switch(offset << 2)
312	312	{
313	313	default:
314	314	//return data;
r253152	r253153
318	318
319	319	WRITE32_MEMBER( r9751_state::r9751_mmio_ff01_w )
320	320	{
321		UINT32 address = offset * 4 + 0xFF010000;
	321	/* Unknown mask */
	322	if (mem_mask != 0xFFFFFFFF)
	323	logerror("Mask found: %08X Register: %08X PC: %08X\n", mem_mask, offset << 2 | 0xFF010000, space.machine().firstcpu->pc());
322	324
323		switch(address)
	325	switch(offset << 2)
324	326	{
325		case 0xFF01000C: /* FDD DMA Offset */
	327	case 0x000C: /* FDD DMA Offset */
326	328	fdd_dma_bank = data;
327	329	return;
328		case 0xFF010010: /* SMIOC DMA Offset */
	330	case 0x0010: /* SMIOC DMA Offset */
329	331	smioc_dma_bank = data;
330	332	return;
331	333	default:
r253152	r253153
336	338	READ32_MEMBER( r9751_state::r9751_mmio_ff05_r )
337	339	{
338	340	UINT32 data;
339		UINT32 address = offset * 4 + 0xFF050000;
340	341
341		switch(address)
	342	switch(offset << 2)
342	343	{
343		case 0xFF050004:
	344	case 0x0004:
344	345	return reg_ff050004;
345		case 0xFF050300:
	346	case 0x0300:
346	347	return 0x1B | (1<<0x14);
347		case 0xFF050320: /* Some type of counter */
	348	case 0x0320: /* Some type of counter */
348	349	return (machine().time() - timer_32khz_last).as_ticks(32768) & 0xFFFF;
349		case 0xFF050584:
	350	case 0x0584:
350	351	return 0;
351		case 0xFF050610:
	352	case 0x0610:
352	353	return 0xabacabac;
353		case 0xFF060014:
	354	case 0x0014:
354	355	return 0x80;
355	356	default:
356	357	data = 0;
357		if(TRACE_CPU_REG) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
	358	if(TRACE_CPU_REG) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0xFF050000, data, mem_mask);
358	359	return data;
359	360	}
360	361	}
361	362
362	363	WRITE32_MEMBER( r9751_state::r9751_mmio_ff05_w )
363	364	{
364		UINT32 address = offset * 4 + 0xFF050000;
	365	/* Unknown mask */
	366	if (mem_mask != 0xFFFFFFFF)
	367	logerror("Mask found: %08X Register: %08X PC: %08X\n", mem_mask, offset << 2 | 0xFF050000, space.machine().firstcpu->pc());
365	368
366		switch(address)
	369	switch(offset << 2)
367	370	{
368		case 0xFF050004:
	371	case 0x0004:
369	372	reg_ff050004 = data;
370	373	return;
371		case 0xFF05000C: /* CPU LED hex display indicator */
	374	case 0x000C: /* CPU LED hex display indicator */
372	375	if(TRACE_LED) logerror("\n*** LED: %02x, Instruction: %08x ***\n\n", data, space.machine().firstcpu->pc());
373	376	return;
374		case 0xFF050320:
	377	case 0x0320:
375	378	timer_32khz_last = machine().time();
376	379	default:
377		if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
	380	if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0xFF050000, data, mem_mask);
378	381	return;
379	382	}
380	383	}
381	384
382	385	READ32_MEMBER( r9751_state::r9751_mmio_fff8_r )
383	386	{
384		UINT32 data;
385		UINT32 address = offset * 4 + 0xFFF80000;
	387	UINT32 data;
386	388
387		switch(address)
	389	switch(offset << 2)
388	390	{
389		case 0xFFF80040:
	391	case 0x0040:
390	392	return reg_fff80040;
391	393	default:
392	394	data = 0;
393		if(TRACE_CPU_REG) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
	395	if(TRACE_CPU_REG) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0xFFF80000, data, mem_mask);
394	396	return data;
395	397	}
396	398	}
397	399
398	400	WRITE32_MEMBER( r9751_state::r9751_mmio_fff8_w )
399	401	{
400		UINT32 address = offset * 4 + 0xFFF80000;
	402	/* Unknown mask */
	403	if (mem_mask != 0xFFFFFFFF)
	404	logerror("Mask found: %08X Register: %08X PC: %08X\n", mem_mask, offset << 2 | 0xFFF80000, space.machine().firstcpu->pc());
401	405
402		switch(address)
	406	switch(offset << 2)
403	407	{
404		case 0xFFF80040:
	408	case 0x0040:
405	409	reg_fff80040 = data;
406	410	return;
407	411	default:
408		if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
	412	if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0xFFF80000, data, mem_mask);
409	413	}
410	414	}
411	415

https://github.com/mamedev/mame/commit/7f6b42536e6fbcd6b0f18414a6584116fd75e83b

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