MAME SVN History

199869 Revisions

r44642 Wednesday 3rd February, 2016 at 04:15:36 UTC by Vasantha Crabb
Merge pull request #601 from bmunger/r9751 r9751: Added more dma registers for serial and floppy

[/trunk]	makefile
[scripts/src]	3rdparty.lua
[scripts/target/mame]	mess.lua
[src/devices/bus/a2bus]	a2pic.cpp
[src/devices/bus/centronics]	epson_lx810l.cpp
[src/devices/machine]	i8271.cpp i8271.h k033906.cpp k033906.h
[src/devices/video]	vooddefs.h voodoo.cpp voodoo.h voodoo_pci.cpp
[src/emu]	emuopts.cpp
[src/mame]	arcade.lst mess.lst
[src/mame/drivers]	arkanoid.cpp esd16.cpp fidelz80.cpp funkball.cpp gticlub.cpp hornet.cpp kaneko16.cpp ladyfrog.cpp magictg.cpp nibble.cpp nwk-tr.cpp overdriv.cpp pc9801.cpp savquest.cpp seattle.cpp stv.cpp tispeak.cpp vc4000.cpp vegas.cpp viper.cpp
[src/mame/includes]	arkanoid.h chihiro.h overdriv.h
[src/mame/machine]	315-5838_317-0229_comp.cpp 315-5838_317-0229_comp.h arkanoid.cpp pc9801_cd.cpp* pc9801_cd.h* pc9801_kbd.cpp pc9801_kbd.h
[src/mame/video]	chihiro.cpp

trunk/makefile
r253153	r253154
1267	1267	$(SILENT)$(PYTHON) scripts/build/file2str.py $< $@ layout_$(basename $(notdir $<))
1268	1268
1269	1269	$(SRC)/devices/cpu/m68000/m68kops.cpp: $(SRC)/devices/cpu/m68000/m68k_in.cpp $(SRC)/devices/cpu/m68000/m68kmake.cpp
	1270	ifeq ($(TARGETOS),asmjs)
	1271	$(SILENT) $(MAKE) -C $(SRC)/devices/cpu/m68000
	1272	else
1270	1273	$(SILENT) $(MAKE) -C $(SRC)/devices/cpu/m68000 CC=$(CC) CXX=$(CXX)
	1274	endif
1271	1275
1272	1276	#-------------------------------------------------
1273	1277	# Regression tests

trunk/scripts/src/3rdparty.lua
r253153	r253154
967	967	"/wd4210", -- warning C4210: nonstandard extension used : function given file scope
968	968	"/wd4701", -- warning C4701: potentially uninitialized local variable 'xxx' used
969	969	"/wd4703", -- warning C4703: potentially uninitialized local pointer variable 'xxx' used
	970	"/wd4477", -- warning C4477: '<function>' : format string '<format-string>' requires an argument of type '<type>', but variadic argument <position> has type '<type>'
970	971	}
971	972
972	973	configuration { }

trunk/scripts/target/mame/mess.lua
r253153	r253154
2090	2090	MAME_DIR .. "src/mame/machine/pc9801_cbus.h",
2091	2091	MAME_DIR .. "src/mame/machine/pc9801_kbd.cpp",
2092	2092	MAME_DIR .. "src/mame/machine/pc9801_kbd.h",
	2093	MAME_DIR .. "src/mame/machine/pc9801_cd.cpp",
	2094	MAME_DIR .. "src/mame/machine/pc9801_cd.h",
2093	2095	MAME_DIR .. "src/mame/drivers/tk80bs.cpp",
2094	2096	MAME_DIR .. "src/mame/drivers/hh_ucom4.cpp",
2095	2097	MAME_DIR .. "src/mame/includes/hh_ucom4.h",

trunk/src/devices/bus/a2bus/a2pic.cpp
r253153	r253154
49	49	PORT_DIPSETTING( 0x06, "13 microseconds" )
50	50	PORT_DIPSETTING( 0x07, "15 microseconds" )
51	51
52		PORT_DIPNAME( 0x08, 0x00, "Strobe polarity (SW4)" )
	52	PORT_DIPNAME( 0x08, 0x08, "Strobe polarity (SW4)" )
53	53	PORT_DIPSETTING( 0x00, "Positive" )
54	54	PORT_DIPSETTING( 0x08, "Negative" )
55	55
56		PORT_DIPNAME( 0x10, 0x00, "Acknowledge polarity (SW5)" )
	56	PORT_DIPNAME( 0x10, 0x10, "Acknowledge polarity (SW5)" )
57	57	PORT_DIPSETTING( 0x00, "Positive" )
58	58	PORT_DIPSETTING( 0x10, "Negative" )
59	59
r253153	r253154
181	181
182	182	UINT8 a2bus_pic_device::read_c0nx(address_space &space, UINT8 offset)
183	183	{
	184	UINT8 rv = 0;
	185
184	186	switch (offset)
185	187	{
186	188	case 3:
187	189	return m_ctx_data_in->read();
188	190
189	191	case 4:
190		r~~eturn~~ m_ack;
	192	rv = m_ack;
191	193
	194	// clear flip-flop
	195	if (m_dsw1->read() & 0x10) // negative polarity
	196	{
	197	m_ack \|= 0x80;
	198	}
	199	else
	200	{
	201	m_ack &= ~0x80;
	202	}
	203
	204	return rv;
	205
192	206	case 6: // does reading this really work?
193	207	m_irqenable = true;
194	208	break;

trunk/src/devices/bus/centronics/epson_lx810l.cpp
r253153	r253154
26	26	*/
27	27
28	28	#include "epson_lx810l.h"
29		extern const char layout_lx800[]; /* use layout from lx800 */
	29	//extern const char layout_lx800[]; /* use layout from lx800 */
30	30
31	31	//#define LX810LDEBUG
32	32	#ifdef LX810LDEBUG
r253153	r253154
132	132	MCFG_UPD7810_CO0(WRITELINE(epson_lx810l_t, co0_w))
133	133	MCFG_UPD7810_CO1(WRITELINE(epson_lx810l_t, co1_w))
134	134
135		MCFG_DEFAULT_LAYOUT(layout_lx800)
	135	// MCFG_DEFAULT_LAYOUT(layout_lx800)
136	136
137	137	/* video hardware (simulates paper) */
138	138	MCFG_SCREEN_ADD("screen", RASTER)

trunk/src/devices/machine/i8271.cpp
r253153	r253154
88	88	flopi[i].live = false;
89	89	flopi[i].ready = get_ready(i);
90	90	}
	91	hdl_cb(false);
91	92	set_irq(false);
92	93	set_drq(false);
93	94	command_pos = 0;
r253153	r253154
887	888	{
888	889	logerror("%s: command done (%s) - %02x\n", tag(), data_completion ? "data" : "seek", rr);
889	890	fi.main_state = fi.sub_state = IDLE;
	891	idle_icnt = 0;
890	892	main_phase = PHASE_RESULT;
891	893	set_irq(true);
892	894	}
r253153	r253154
981	983	void i8271_device::read_data_start(floppy_info &fi)
982	984	{
983	985	fi.main_state = READ_DATA;
	986	hdl_cb(true);
984	987	fi.sub_state = HEAD_LOAD_DONE;
985	988
986	989	logerror("%s: command read%s data%s cmd=%02x crn=(%d, %d, %d) len=%02x rate=%d\n",
r253153	r253154
1010	1013	void i8271_device::scan_start(floppy_info &fi)
1011	1014	{
1012	1015	fi.main_state = SCAN_DATA;
	1016	hdl_cb(true);
1013	1017	fi.sub_state = HEAD_LOAD_DONE;
1014	1018
1015	1019	logerror("%s: command scan%s data%s cmd=%02x crn=(%d, %d, %d) len=%02x rate=%d\n",
r253153	r253154
1041	1045	void i8271_device::verify_data_start(floppy_info &fi)
1042	1046	{
1043	1047	fi.main_state = VERIFY_DATA;
	1048	hdl_cb(true);
1044	1049	fi.sub_state = HEAD_LOAD_DONE;
1045	1050
1046	1051	logerror("%s: command verify%s data%s cmd=%02x crn=(%d, %d, %d) len=%02x rate=%d\n",
r253153	r253154
1098	1103	return;
1099	1104
1100	1105	case SEEK_WAIT_STEP_TIME_DONE:
	1106	hdl_cb(true);
1101	1107	do {
1102	1108	if(fi.pcn > command[1])
1103	1109	fi.pcn--;
r253153	r253154
1181	1187	void i8271_device::write_data_start(floppy_info &fi)
1182	1188	{
1183	1189	fi.main_state = WRITE_DATA;
	1190	hdl_cb(true);
1184	1191	fi.sub_state = HEAD_LOAD_DONE;
	1192
1185	1193	logerror("%s: command write%s data%s cmd=%02x crn=(%d, %d, %d) len=%02x rate=%d\n",
1186	1194	tag(),
1187	1195	command[0] & 0x04 ? " deleted" : "",
r253153	r253154
1238	1246	return;
1239	1247
1240	1248	case SEEK_WAIT_STEP_TIME_DONE:
	1249	hdl_cb(true);
1241	1250	do {
1242	1251	if(fi.pcn > command[1])
1243	1252	fi.pcn--;
r253153	r253154
1311	1320	void i8271_device::format_track_start(floppy_info &fi)
1312	1321	{
1313	1322	fi.main_state = FORMAT_TRACK;
	1323	hdl_cb(true);
1314	1324	fi.sub_state = HEAD_LOAD_DONE;
1315	1325
1316	1326	logerror("%s: command format track c=%02x n=%02x sc=%02x gap3=%02x gap5=%02x gap1=%02x\n",
r253153	r253154
1364	1374	return;
1365	1375
1366	1376	case SEEK_WAIT_STEP_TIME_DONE:
	1377	hdl_cb(true);
1367	1378	do {
1368	1379	if(fi.pcn > command[1])
1369	1380	fi.pcn--;
r253153	r253154
1402	1413	void i8271_device::read_id_start(floppy_info &fi)
1403	1414	{
1404	1415	fi.main_state = READ_ID;
	1416	hdl_cb(true);
1405	1417	fi.sub_state = HEAD_LOAD_DONE;
1406	1418
1407	1419	logerror("%s: command read id, rate=%d\n",
r253153	r253154
1457	1469	return;
1458	1470
1459	1471	case SEEK_WAIT_STEP_TIME_DONE:
	1472	hdl_cb(true);
1460	1473	do {
1461	1474	if(fi.pcn > command[1])
1462	1475	fi.pcn--;
r253153	r253154
1553	1566	continue;
1554	1567	}
1555	1568
	1569	if (fi.main_state == IDLE) {
	1570	idle_icnt++;
	1571	if (icnt != 0x0f && idle_icnt >= icnt) {
	1572	hdl_cb(false);
	1573	}
	1574	}
	1575
1556	1576	switch(fi.sub_state) {
1557	1577	case IDLE:
1558	1578	case SEEK_MOVE:

trunk/src/devices/machine/i8271.h
r253153	r253154
215	215	UINT8 srate, hset, icnt, hload;
216	216	int sector_size;
217	217	int cur_rate;
	218	int idle_icnt;
218	219
219	220	static std::string tts(attotime t);
220	221	std::string ttsn();

trunk/src/devices/machine/k033906.cpp
r253153	r253154
33	33
34	34	void k033906_device::device_start()
35	35	{
36		m_voodoo = machine().device(m_voodoo_tag);
	36	m_voodoo = (voodoo_device*)machine().device(m_voodoo_tag);
37	37
38	38	m_reg_set = 0;
39	39
r253153	r253154
95	95
96	96	case 0x10: // initEnable
97	97	{
98		voodoo_set_init_enable(~~m_voodoo,~~ data);
	98	m_voodoo->voodoo_set_init_enable(data);
99	99	break;
100	100	}
101	101

trunk/src/devices/machine/k033906.h
r253153	r253154
12	12	#define __K033906_H__
13	13
14	14	#include "emu.h"
	15	#include "video/voodoo.h"
15	16
16	17
17
18	18	/***************************************************************************
19	19	DEVICE CONFIGURATION MACROS
20	20	***************************************************************************/
r253153	r253154
58	58	int m_reg_set; // 1 = access reg / 0 = access ram
59	59
60	60	const char *m_voodoo_tag;
61		device_t *m_voodoo;
	61	voodoo_device *m_voodoo;
62	62
63	63	UINT32 m_reg[256];
64	64	UINT32 m_ram[32768];

trunk/src/devices/video/vooddefs.h
r253153	r253154
9	9	***************************************************************************/
10	10
11	11
12		/*************************************
13		*
14		* Misc. constants
15		*
16		*************************************/
17	12
18		/* enumeration describing reasons we might be stalled */
19		enum
20		{
21		NOT_STALLED = 0,
22		STALLED_UNTIL_FIFO_LWM,
23		STALLED_UNTIL_FIFO_EMPTY
24		};
25	13
26
27
28		// Use old table lookup versus straight double divide
29		#define USE_FAST_RECIP 0
30
31		/* maximum number of TMUs */
32		#define MAX_TMU 2
33
34		/* accumulate operations less than this number of clocks */
35		#define ACCUMULATE_THRESHOLD 0
36
37		/* number of clocks to set up a triangle (just a guess) */
38		#define TRIANGLE_SETUP_CLOCKS 100
39
40		/* maximum number of rasterizers */
41		#define MAX_RASTERIZERS 1024
42
43		/* size of the rasterizer hash table */
44		#define RASTER_HASH_SIZE 97
45
46		/* flags for LFB writes */
47		#define LFB_RGB_PRESENT 1
48		#define LFB_ALPHA_PRESENT 2
49		#define LFB_DEPTH_PRESENT 4
50		#define LFB_DEPTH_PRESENT_MSW 8
51
52		/* flags for the register access array */
53		#define REGISTER_READ 0x01 /* reads are allowed */
54		#define REGISTER_WRITE 0x02 /* writes are allowed */
55		#define REGISTER_PIPELINED 0x04 /* writes are pipelined */
56		#define REGISTER_FIFO 0x08 /* writes go to FIFO */
57		#define REGISTER_WRITETHRU 0x10 /* writes are valid even for CMDFIFO */
58
59		/* shorter combinations to make the table smaller */
60		#define REG_R (REGISTER_READ)
61		#define REG_W (REGISTER_WRITE)
62		#define REG_WT (REGISTER_WRITE \| REGISTER_WRITETHRU)
63		#define REG_RW (REGISTER_READ \| REGISTER_WRITE)
64		#define REG_RWT (REGISTER_READ \| REGISTER_WRITE \| REGISTER_WRITETHRU)
65		#define REG_RP (REGISTER_READ \| REGISTER_PIPELINED)
66		#define REG_WP (REGISTER_WRITE \| REGISTER_PIPELINED)
67		#define REG_RWP (REGISTER_READ \| REGISTER_WRITE \| REGISTER_PIPELINED)
68		#define REG_RWPT (REGISTER_READ \| REGISTER_WRITE \| REGISTER_PIPELINED \| REGISTER_WRITETHRU)
69		#define REG_RF (REGISTER_READ \| REGISTER_FIFO)
70		#define REG_WF (REGISTER_WRITE \| REGISTER_FIFO)
71		#define REG_RWF (REGISTER_READ \| REGISTER_WRITE \| REGISTER_FIFO)
72		#define REG_RPF (REGISTER_READ \| REGISTER_PIPELINED \| REGISTER_FIFO)
73		#define REG_WPF (REGISTER_WRITE \| REGISTER_PIPELINED \| REGISTER_FIFO)
74		#define REG_RWPF (REGISTER_READ \| REGISTER_WRITE \| REGISTER_PIPELINED \| REGISTER_FIFO)
75
76		/* lookup bits is the log2 of the size of the reciprocal/log table */
77		#define RECIPLOG_LOOKUP_BITS 9
78
79		/* input precision is how many fraction bits the input value has; this is a 64-bit number */
80		#define RECIPLOG_INPUT_PREC 32
81
82		/* lookup precision is how many fraction bits each table entry contains */
83		#define RECIPLOG_LOOKUP_PREC 22
84
85		/* output precision is how many fraction bits the result should have */
86		#define RECIP_OUTPUT_PREC 15
87		#define LOG_OUTPUT_PREC 8
88
89
90
91	14	/*************************************
92	15	*
93		* Register constants
94		*
95		*************************************/
96
97		/* Codes to the right:
98		R = readable
99		W = writeable
100		P = pipelined
101		F = goes to FIFO
102		*/
103
104		/* 0x000 */
105		#define status (0x000/4) /* R P */
106		#define intrCtrl (0x004/4) /* RW P -- Voodoo2/Banshee only */
107		#define vertexAx (0x008/4) /* W PF */
108		#define vertexAy (0x00c/4) /* W PF */
109		#define vertexBx (0x010/4) /* W PF */
110		#define vertexBy (0x014/4) /* W PF */
111		#define vertexCx (0x018/4) /* W PF */
112		#define vertexCy (0x01c/4) /* W PF */
113		#define startR (0x020/4) /* W PF */
114		#define startG (0x024/4) /* W PF */
115		#define startB (0x028/4) /* W PF */
116		#define startZ (0x02c/4) /* W PF */
117		#define startA (0x030/4) /* W PF */
118		#define startS (0x034/4) /* W PF */
119		#define startT (0x038/4) /* W PF */
120		#define startW (0x03c/4) /* W PF */
121
122		/* 0x040 */
123		#define dRdX (0x040/4) /* W PF */
124		#define dGdX (0x044/4) /* W PF */
125		#define dBdX (0x048/4) /* W PF */
126		#define dZdX (0x04c/4) /* W PF */
127		#define dAdX (0x050/4) /* W PF */
128		#define dSdX (0x054/4) /* W PF */
129		#define dTdX (0x058/4) /* W PF */
130		#define dWdX (0x05c/4) /* W PF */
131		#define dRdY (0x060/4) /* W PF */
132		#define dGdY (0x064/4) /* W PF */
133		#define dBdY (0x068/4) /* W PF */
134		#define dZdY (0x06c/4) /* W PF */
135		#define dAdY (0x070/4) /* W PF */
136		#define dSdY (0x074/4) /* W PF */
137		#define dTdY (0x078/4) /* W PF */
138		#define dWdY (0x07c/4) /* W PF */
139
140		/* 0x080 */
141		#define triangleCMD (0x080/4) /* W PF */
142		#define fvertexAx (0x088/4) /* W PF */
143		#define fvertexAy (0x08c/4) /* W PF */
144		#define fvertexBx (0x090/4) /* W PF */
145		#define fvertexBy (0x094/4) /* W PF */
146		#define fvertexCx (0x098/4) /* W PF */
147		#define fvertexCy (0x09c/4) /* W PF */
148		#define fstartR (0x0a0/4) /* W PF */
149		#define fstartG (0x0a4/4) /* W PF */
150		#define fstartB (0x0a8/4) /* W PF */
151		#define fstartZ (0x0ac/4) /* W PF */
152		#define fstartA (0x0b0/4) /* W PF */
153		#define fstartS (0x0b4/4) /* W PF */
154		#define fstartT (0x0b8/4) /* W PF */
155		#define fstartW (0x0bc/4) /* W PF */
156
157		/* 0x0c0 */
158		#define fdRdX (0x0c0/4) /* W PF */
159		#define fdGdX (0x0c4/4) /* W PF */
160		#define fdBdX (0x0c8/4) /* W PF */
161		#define fdZdX (0x0cc/4) /* W PF */
162		#define fdAdX (0x0d0/4) /* W PF */
163		#define fdSdX (0x0d4/4) /* W PF */
164		#define fdTdX (0x0d8/4) /* W PF */
165		#define fdWdX (0x0dc/4) /* W PF */
166		#define fdRdY (0x0e0/4) /* W PF */
167		#define fdGdY (0x0e4/4) /* W PF */
168		#define fdBdY (0x0e8/4) /* W PF */
169		#define fdZdY (0x0ec/4) /* W PF */
170		#define fdAdY (0x0f0/4) /* W PF */
171		#define fdSdY (0x0f4/4) /* W PF */
172		#define fdTdY (0x0f8/4) /* W PF */
173		#define fdWdY (0x0fc/4) /* W PF */
174
175		/* 0x100 */
176		#define ftriangleCMD (0x100/4) /* W PF */
177		#define fbzColorPath (0x104/4) /* RW PF */
178		#define fogMode (0x108/4) /* RW PF */
179		#define alphaMode (0x10c/4) /* RW PF */
180		#define fbzMode (0x110/4) /* RW F */
181		#define lfbMode (0x114/4) /* RW F */
182		#define clipLeftRight (0x118/4) /* RW F */
183		#define clipLowYHighY (0x11c/4) /* RW F */
184		#define nopCMD (0x120/4) /* W F */
185		#define fastfillCMD (0x124/4) /* W F */
186		#define swapbufferCMD (0x128/4) /* W F */
187		#define fogColor (0x12c/4) /* W F */
188		#define zaColor (0x130/4) /* W F */
189		#define chromaKey (0x134/4) /* W F */
190		#define chromaRange (0x138/4) /* W F -- Voodoo2/Banshee only */
191		#define userIntrCMD (0x13c/4) /* W F -- Voodoo2/Banshee only */
192
193		/* 0x140 */
194		#define stipple (0x140/4) /* RW F */
195		#define color0 (0x144/4) /* RW F */
196		#define color1 (0x148/4) /* RW F */
197		#define fbiPixelsIn (0x14c/4) /* R */
198		#define fbiChromaFail (0x150/4) /* R */
199		#define fbiZfuncFail (0x154/4) /* R */
200		#define fbiAfuncFail (0x158/4) /* R */
201		#define fbiPixelsOut (0x15c/4) /* R */
202		#define fogTable (0x160/4) /* W F */
203
204		/* 0x1c0 */
205		#define cmdFifoBaseAddr (0x1e0/4) /* RW -- Voodoo2 only */
206		#define cmdFifoBump (0x1e4/4) /* RW -- Voodoo2 only */
207		#define cmdFifoRdPtr (0x1e8/4) /* RW -- Voodoo2 only */
208		#define cmdFifoAMin (0x1ec/4) /* RW -- Voodoo2 only */
209		#define colBufferAddr (0x1ec/4) /* RW -- Banshee only */
210		#define cmdFifoAMax (0x1f0/4) /* RW -- Voodoo2 only */
211		#define colBufferStride (0x1f0/4) /* RW -- Banshee only */
212		#define cmdFifoDepth (0x1f4/4) /* RW -- Voodoo2 only */
213		#define auxBufferAddr (0x1f4/4) /* RW -- Banshee only */
214		#define cmdFifoHoles (0x1f8/4) /* RW -- Voodoo2 only */
215		#define auxBufferStride (0x1f8/4) /* RW -- Banshee only */
216
217		/* 0x200 */
218		#define fbiInit4 (0x200/4) /* RW -- Voodoo/Voodoo2 only */
219		#define clipLeftRight1 (0x200/4) /* RW -- Banshee only */
220		#define vRetrace (0x204/4) /* R -- Voodoo/Voodoo2 only */
221		#define clipTopBottom1 (0x204/4) /* RW -- Banshee only */
222		#define backPorch (0x208/4) /* RW -- Voodoo/Voodoo2 only */
223		#define videoDimensions (0x20c/4) /* RW -- Voodoo/Voodoo2 only */
224		#define fbiInit0 (0x210/4) /* RW -- Voodoo/Voodoo2 only */
225		#define fbiInit1 (0x214/4) /* RW -- Voodoo/Voodoo2 only */
226		#define fbiInit2 (0x218/4) /* RW -- Voodoo/Voodoo2 only */
227		#define fbiInit3 (0x21c/4) /* RW -- Voodoo/Voodoo2 only */
228		#define hSync (0x220/4) /* W -- Voodoo/Voodoo2 only */
229		#define vSync (0x224/4) /* W -- Voodoo/Voodoo2 only */
230		#define clutData (0x228/4) /* W F -- Voodoo/Voodoo2 only */
231		#define dacData (0x22c/4) /* W -- Voodoo/Voodoo2 only */
232		#define maxRgbDelta (0x230/4) /* W -- Voodoo/Voodoo2 only */
233		#define hBorder (0x234/4) /* W -- Voodoo2 only */
234		#define vBorder (0x238/4) /* W -- Voodoo2 only */
235		#define borderColor (0x23c/4) /* W -- Voodoo2 only */
236
237		/* 0x240 */
238		#define hvRetrace (0x240/4) /* R -- Voodoo2 only */
239		#define fbiInit5 (0x244/4) /* RW -- Voodoo2 only */
240		#define fbiInit6 (0x248/4) /* RW -- Voodoo2 only */
241		#define fbiInit7 (0x24c/4) /* RW -- Voodoo2 only */
242		#define swapPending (0x24c/4) /* W -- Banshee only */
243		#define leftOverlayBuf (0x250/4) /* W -- Banshee only */
244		#define rightOverlayBuf (0x254/4) /* W -- Banshee only */
245		#define fbiSwapHistory (0x258/4) /* R -- Voodoo2/Banshee only */
246		#define fbiTrianglesOut (0x25c/4) /* R -- Voodoo2/Banshee only */
247		#define sSetupMode (0x260/4) /* W PF -- Voodoo2/Banshee only */
248		#define sVx (0x264/4) /* W PF -- Voodoo2/Banshee only */
249		#define sVy (0x268/4) /* W PF -- Voodoo2/Banshee only */
250		#define sARGB (0x26c/4) /* W PF -- Voodoo2/Banshee only */
251		#define sRed (0x270/4) /* W PF -- Voodoo2/Banshee only */
252		#define sGreen (0x274/4) /* W PF -- Voodoo2/Banshee only */
253		#define sBlue (0x278/4) /* W PF -- Voodoo2/Banshee only */
254		#define sAlpha (0x27c/4) /* W PF -- Voodoo2/Banshee only */
255
256		/* 0x280 */
257		#define sVz (0x280/4) /* W PF -- Voodoo2/Banshee only */
258		#define sWb (0x284/4) /* W PF -- Voodoo2/Banshee only */
259		#define sWtmu0 (0x288/4) /* W PF -- Voodoo2/Banshee only */
260		#define sS_W0 (0x28c/4) /* W PF -- Voodoo2/Banshee only */
261		#define sT_W0 (0x290/4) /* W PF -- Voodoo2/Banshee only */
262		#define sWtmu1 (0x294/4) /* W PF -- Voodoo2/Banshee only */
263		#define sS_Wtmu1 (0x298/4) /* W PF -- Voodoo2/Banshee only */
264		#define sT_Wtmu1 (0x29c/4) /* W PF -- Voodoo2/Banshee only */
265		#define sDrawTriCMD (0x2a0/4) /* W PF -- Voodoo2/Banshee only */
266		#define sBeginTriCMD (0x2a4/4) /* W PF -- Voodoo2/Banshee only */
267
268		/* 0x2c0 */
269		#define bltSrcBaseAddr (0x2c0/4) /* RW PF -- Voodoo2 only */
270		#define bltDstBaseAddr (0x2c4/4) /* RW PF -- Voodoo2 only */
271		#define bltXYStrides (0x2c8/4) /* RW PF -- Voodoo2 only */
272		#define bltSrcChromaRange (0x2cc/4) /* RW PF -- Voodoo2 only */
273		#define bltDstChromaRange (0x2d0/4) /* RW PF -- Voodoo2 only */
274		#define bltClipX (0x2d4/4) /* RW PF -- Voodoo2 only */
275		#define bltClipY (0x2d8/4) /* RW PF -- Voodoo2 only */
276		#define bltSrcXY (0x2e0/4) /* RW PF -- Voodoo2 only */
277		#define bltDstXY (0x2e4/4) /* RW PF -- Voodoo2 only */
278		#define bltSize (0x2e8/4) /* RW PF -- Voodoo2 only */
279		#define bltRop (0x2ec/4) /* RW PF -- Voodoo2 only */
280		#define bltColor (0x2f0/4) /* RW PF -- Voodoo2 only */
281		#define bltCommand (0x2f8/4) /* RW PF -- Voodoo2 only */
282		#define bltData (0x2fc/4) /* W PF -- Voodoo2 only */
283
284		/* 0x300 */
285		#define textureMode (0x300/4) /* W PF */
286		#define tLOD (0x304/4) /* W PF */
287		#define tDetail (0x308/4) /* W PF */
288		#define texBaseAddr (0x30c/4) /* W PF */
289		#define texBaseAddr_1 (0x310/4) /* W PF */
290		#define texBaseAddr_2 (0x314/4) /* W PF */
291		#define texBaseAddr_3_8 (0x318/4) /* W PF */
292		#define trexInit0 (0x31c/4) /* W F -- Voodoo/Voodoo2 only */
293		#define trexInit1 (0x320/4) /* W F */
294		#define nccTable (0x324/4) /* W F */
295
296
297
298		// 2D registers
299		#define banshee2D_clip0Min (0x008/4)
300		#define banshee2D_clip0Max (0x00c/4)
301		#define banshee2D_dstBaseAddr (0x010/4)
302		#define banshee2D_dstFormat (0x014/4)
303		#define banshee2D_srcColorkeyMin (0x018/4)
304		#define banshee2D_srcColorkeyMax (0x01c/4)
305		#define banshee2D_dstColorkeyMin (0x020/4)
306		#define banshee2D_dstColorkeyMax (0x024/4)
307		#define banshee2D_bresError0 (0x028/4)
308		#define banshee2D_bresError1 (0x02c/4)
309		#define banshee2D_rop (0x030/4)
310		#define banshee2D_srcBaseAddr (0x034/4)
311		#define banshee2D_commandExtra (0x038/4)
312		#define banshee2D_lineStipple (0x03c/4)
313		#define banshee2D_lineStyle (0x040/4)
314		#define banshee2D_pattern0Alias (0x044/4)
315		#define banshee2D_pattern1Alias (0x048/4)
316		#define banshee2D_clip1Min (0x04c/4)
317		#define banshee2D_clip1Max (0x050/4)
318		#define banshee2D_srcFormat (0x054/4)
319		#define banshee2D_srcSize (0x058/4)
320		#define banshee2D_srcXY (0x05c/4)
321		#define banshee2D_colorBack (0x060/4)
322		#define banshee2D_colorFore (0x064/4)
323		#define banshee2D_dstSize (0x068/4)
324		#define banshee2D_dstXY (0x06c/4)
325		#define banshee2D_command (0x070/4)
326
327
328		/*************************************
329		*
330		* Alias map of the first 64
331		* registers when remapped
332		*
333		*************************************/
334
335		static const UINT8 register_alias_map[0x40] =
336		{
337		status, 0x004/4, vertexAx, vertexAy,
338		vertexBx, vertexBy, vertexCx, vertexCy,
339		startR, dRdX, dRdY, startG,
340		dGdX, dGdY, startB, dBdX,
341		dBdY, startZ, dZdX, dZdY,
342		startA, dAdX, dAdY, startS,
343		dSdX, dSdY, startT, dTdX,
344		dTdY, startW, dWdX, dWdY,
345
346		triangleCMD,0x084/4, fvertexAx, fvertexAy,
347		fvertexBx, fvertexBy, fvertexCx, fvertexCy,
348		fstartR, fdRdX, fdRdY, fstartG,
349		fdGdX, fdGdY, fstartB, fdBdX,
350		fdBdY, fstartZ, fdZdX, fdZdY,
351		fstartA, fdAdX, fdAdY, fstartS,
352		fdSdX, fdSdY, fstartT, fdTdX,
353		fdTdY, fstartW, fdWdX, fdWdY
354		};
355
356
357
358		/*************************************
359		*
360		* Table of per-register access rights
361		*
362		*************************************/
363
364		static const UINT8 voodoo_register_access[0x100] =
365		{
366		/* 0x000 */
367		REG_RP, 0, REG_WPF, REG_WPF,
368		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
369		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
370		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
371
372		/* 0x040 */
373		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
374		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
375		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
376		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
377
378		/* 0x080 */
379		REG_WPF, 0, REG_WPF, REG_WPF,
380		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
381		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
382		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
383
384		/* 0x0c0 */
385		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
386		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
387		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
388		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
389
390		/* 0x100 */
391		REG_WPF, REG_RWPF, REG_RWPF, REG_RWPF,
392		REG_RWF, REG_RWF, REG_RWF, REG_RWF,
393		REG_WF, REG_WF, REG_WF, REG_WF,
394		REG_WF, REG_WF, 0, 0,
395
396		/* 0x140 */
397		REG_RWF, REG_RWF, REG_RWF, REG_R,
398		REG_R, REG_R, REG_R, REG_R,
399		REG_WF, REG_WF, REG_WF, REG_WF,
400		REG_WF, REG_WF, REG_WF, REG_WF,
401
402		/* 0x180 */
403		REG_WF, REG_WF, REG_WF, REG_WF,
404		REG_WF, REG_WF, REG_WF, REG_WF,
405		REG_WF, REG_WF, REG_WF, REG_WF,
406		REG_WF, REG_WF, REG_WF, REG_WF,
407
408		/* 0x1c0 */
409		REG_WF, REG_WF, REG_WF, REG_WF,
410		REG_WF, REG_WF, REG_WF, REG_WF,
411		0, 0, 0, 0,
412		0, 0, 0, 0,
413
414		/* 0x200 */
415		REG_RW, REG_R, REG_RW, REG_RW,
416		REG_RW, REG_RW, REG_RW, REG_RW,
417		REG_W, REG_W, REG_W, REG_W,
418		REG_W, 0, 0, 0,
419
420		/* 0x240 */
421		0, 0, 0, 0,
422		0, 0, 0, 0,
423		0, 0, 0, 0,
424		0, 0, 0, 0,
425
426		/* 0x280 */
427		0, 0, 0, 0,
428		0, 0, 0, 0,
429		0, 0, 0, 0,
430		0, 0, 0, 0,
431
432		/* 0x2c0 */
433		0, 0, 0, 0,
434		0, 0, 0, 0,
435		0, 0, 0, 0,
436		0, 0, 0, 0,
437
438		/* 0x300 */
439		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
440		REG_WPF, REG_WPF, REG_WPF, REG_WF,
441		REG_WF, REG_WF, REG_WF, REG_WF,
442		REG_WF, REG_WF, REG_WF, REG_WF,
443
444		/* 0x340 */
445		REG_WF, REG_WF, REG_WF, REG_WF,
446		REG_WF, REG_WF, REG_WF, REG_WF,
447		REG_WF, REG_WF, REG_WF, REG_WF,
448		REG_WF, REG_WF, REG_WF, REG_WF,
449
450		/* 0x380 */
451		REG_WF
452		};
453
454
455		static const UINT8 voodoo2_register_access[0x100] =
456		{
457		/* 0x000 */
458		REG_RP, REG_RWPT, REG_WPF, REG_WPF,
459		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
460		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
461		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
462
463		/* 0x040 */
464		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
465		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
466		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
467		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
468
469		/* 0x080 */
470		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
471		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
472		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
473		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
474
475		/* 0x0c0 */
476		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
477		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
478		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
479		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
480
481		/* 0x100 */
482		REG_WPF, REG_RWPF, REG_RWPF, REG_RWPF,
483		REG_RWF, REG_RWF, REG_RWF, REG_RWF,
484		REG_WF, REG_WF, REG_WF, REG_WF,
485		REG_WF, REG_WF, REG_WF, REG_WF,
486
487		/* 0x140 */
488		REG_RWF, REG_RWF, REG_RWF, REG_R,
489		REG_R, REG_R, REG_R, REG_R,
490		REG_WF, REG_WF, REG_WF, REG_WF,
491		REG_WF, REG_WF, REG_WF, REG_WF,
492
493		/* 0x180 */
494		REG_WF, REG_WF, REG_WF, REG_WF,
495		REG_WF, REG_WF, REG_WF, REG_WF,
496		REG_WF, REG_WF, REG_WF, REG_WF,
497		REG_WF, REG_WF, REG_WF, REG_WF,
498
499		/* 0x1c0 */
500		REG_WF, REG_WF, REG_WF, REG_WF,
501		REG_WF, REG_WF, REG_WF, REG_WF,
502		REG_RWT, REG_RWT, REG_RWT, REG_RWT,
503		REG_RWT, REG_RWT, REG_RWT, REG_RW,
504
505		/* 0x200 */
506		REG_RWT, REG_R, REG_RWT, REG_RWT,
507		REG_RWT, REG_RWT, REG_RWT, REG_RWT,
508		REG_WT, REG_WT, REG_WF, REG_WT,
509		REG_WT, REG_WT, REG_WT, REG_WT,
510
511		/* 0x240 */
512		REG_R, REG_RWT, REG_RWT, REG_RWT,
513		0, 0, REG_R, REG_R,
514		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
515		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
516
517		/* 0x280 */
518		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
519		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
520		REG_WPF, REG_WPF, 0, 0,
521		0, 0, 0, 0,
522
523		/* 0x2c0 */
524		REG_RWPF, REG_RWPF, REG_RWPF, REG_RWPF,
525		REG_RWPF, REG_RWPF, REG_RWPF, REG_RWPF,
526		REG_RWPF, REG_RWPF, REG_RWPF, REG_RWPF,
527		REG_RWPF, REG_RWPF, REG_RWPF, REG_WPF,
528
529		/* 0x300 */
530		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
531		REG_WPF, REG_WPF, REG_WPF, REG_WF,
532		REG_WF, REG_WF, REG_WF, REG_WF,
533		REG_WF, REG_WF, REG_WF, REG_WF,
534
535		/* 0x340 */
536		REG_WF, REG_WF, REG_WF, REG_WF,
537		REG_WF, REG_WF, REG_WF, REG_WF,
538		REG_WF, REG_WF, REG_WF, REG_WF,
539		REG_WF, REG_WF, REG_WF, REG_WF,
540
541		/* 0x380 */
542		REG_WF
543		};
544
545
546		static const UINT8 banshee_register_access[0x100] =
547		{
548		/* 0x000 */
549		REG_RP, REG_RWPT, REG_WPF, REG_WPF,
550		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
551		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
552		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
553
554		/* 0x040 */
555		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
556		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
557		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
558		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
559
560		/* 0x080 */
561		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
562		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
563		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
564		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
565
566		/* 0x0c0 */
567		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
568		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
569		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
570		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
571
572		/* 0x100 */
573		REG_WPF, REG_RWPF, REG_RWPF, REG_RWPF,
574		REG_RWF, REG_RWF, REG_RWF, REG_RWF,
575		REG_WF, REG_WF, REG_WF, REG_WF,
576		REG_WF, REG_WF, REG_WF, REG_WF,
577
578		/* 0x140 */
579		REG_RWF, REG_RWF, REG_RWF, REG_R,
580		REG_R, REG_R, REG_R, REG_R,
581		REG_WF, REG_WF, REG_WF, REG_WF,
582		REG_WF, REG_WF, REG_WF, REG_WF,
583
584		/* 0x180 */
585		REG_WF, REG_WF, REG_WF, REG_WF,
586		REG_WF, REG_WF, REG_WF, REG_WF,
587		REG_WF, REG_WF, REG_WF, REG_WF,
588		REG_WF, REG_WF, REG_WF, REG_WF,
589
590		/* 0x1c0 */
591		REG_WF, REG_WF, REG_WF, REG_WF,
592		REG_WF, REG_WF, REG_WF, REG_WF,
593		0, 0, 0, REG_RWF,
594		REG_RWF, REG_RWF, REG_RWF, 0,
595
596		/* 0x200 */
597		REG_RWF, REG_RWF, 0, 0,
598		0, 0, 0, 0,
599		0, 0, 0, 0,
600		0, 0, 0, 0,
601
602		/* 0x240 */
603		0, 0, 0, REG_WT,
604		REG_RWF, REG_RWF, REG_WPF, REG_WPF,
605		REG_WPF, REG_WPF, REG_R, REG_R,
606		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
607
608		/* 0x280 */
609		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
610		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
611		REG_WPF, REG_WPF, 0, 0,
612		0, 0, 0, 0,
613
614		/* 0x2c0 */
615		0, 0, 0, 0,
616		0, 0, 0, 0,
617		0, 0, 0, 0,
618		0, 0, 0, 0,
619
620		/* 0x300 */
621		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
622		REG_WPF, REG_WPF, REG_WPF, 0,
623		REG_WF, REG_WF, REG_WF, REG_WF,
624		REG_WF, REG_WF, REG_WF, REG_WF,
625
626		/* 0x340 */
627		REG_WF, REG_WF, REG_WF, REG_WF,
628		REG_WF, REG_WF, REG_WF, REG_WF,
629		REG_WF, REG_WF, REG_WF, REG_WF,
630		REG_WF, REG_WF, REG_WF, REG_WF,
631
632		/* 0x380 */
633		REG_WF
634		};
635
636
637
638		/*************************************
639		*
640		* Register string table for debug
641		*
642		*************************************/
643
644		static const char *const voodoo_reg_name[] =
645		{
646		/* 0x000 */
647		"status", "{intrCtrl}", "vertexAx", "vertexAy",
648		"vertexBx", "vertexBy", "vertexCx", "vertexCy",
649		"startR", "startG", "startB", "startZ",
650		"startA", "startS", "startT", "startW",
651		/* 0x040 */
652		"dRdX", "dGdX", "dBdX", "dZdX",
653		"dAdX", "dSdX", "dTdX", "dWdX",
654		"dRdY", "dGdY", "dBdY", "dZdY",
655		"dAdY", "dSdY", "dTdY", "dWdY",
656		/* 0x080 */
657		"triangleCMD", "reserved084", "fvertexAx", "fvertexAy",
658		"fvertexBx", "fvertexBy", "fvertexCx", "fvertexCy",
659		"fstartR", "fstartG", "fstartB", "fstartZ",
660		"fstartA", "fstartS", "fstartT", "fstartW",
661		/* 0x0c0 */
662		"fdRdX", "fdGdX", "fdBdX", "fdZdX",
663		"fdAdX", "fdSdX", "fdTdX", "fdWdX",
664		"fdRdY", "fdGdY", "fdBdY", "fdZdY",
665		"fdAdY", "fdSdY", "fdTdY", "fdWdY",
666		/* 0x100 */
667		"ftriangleCMD", "fbzColorPath", "fogMode", "alphaMode",
668		"fbzMode", "lfbMode", "clipLeftRight","clipLowYHighY",
669		"nopCMD", "fastfillCMD", "swapbufferCMD","fogColor",
670		"zaColor", "chromaKey", "{chromaRange}","{userIntrCMD}",
671		/* 0x140 */
672		"stipple", "color0", "color1", "fbiPixelsIn",
673		"fbiChromaFail","fbiZfuncFail", "fbiAfuncFail", "fbiPixelsOut",
674		"fogTable160", "fogTable164", "fogTable168", "fogTable16c",
675		"fogTable170", "fogTable174", "fogTable178", "fogTable17c",
676		/* 0x180 */
677		"fogTable180", "fogTable184", "fogTable188", "fogTable18c",
678		"fogTable190", "fogTable194", "fogTable198", "fogTable19c",
679		"fogTable1a0", "fogTable1a4", "fogTable1a8", "fogTable1ac",
680		"fogTable1b0", "fogTable1b4", "fogTable1b8", "fogTable1bc",
681		/* 0x1c0 */
682		"fogTable1c0", "fogTable1c4", "fogTable1c8", "fogTable1cc",
683		"fogTable1d0", "fogTable1d4", "fogTable1d8", "fogTable1dc",
684		"{cmdFifoBaseAddr}","{cmdFifoBump}","{cmdFifoRdPtr}","{cmdFifoAMin}",
685		"{cmdFifoAMax}","{cmdFifoDepth}","{cmdFifoHoles}","reserved1fc",
686		/* 0x200 */
687		"fbiInit4", "vRetrace", "backPorch", "videoDimensions",
688		"fbiInit0", "fbiInit1", "fbiInit2", "fbiInit3",
689		"hSync", "vSync", "clutData", "dacData",
690		"maxRgbDelta", "{hBorder}", "{vBorder}", "{borderColor}",
691		/* 0x240 */
692		"{hvRetrace}", "{fbiInit5}", "{fbiInit6}", "{fbiInit7}",
693		"reserved250", "reserved254", "{fbiSwapHistory}","{fbiTrianglesOut}",
694		"{sSetupMode}", "{sVx}", "{sVy}", "{sARGB}",
695		"{sRed}", "{sGreen}", "{sBlue}", "{sAlpha}",
696		/* 0x280 */
697		"{sVz}", "{sWb}", "{sWtmu0}", "{sS/Wtmu0}",
698		"{sT/Wtmu0}", "{sWtmu1}", "{sS/Wtmu1}", "{sT/Wtmu1}",
699		"{sDrawTriCMD}","{sBeginTriCMD}","reserved2a8", "reserved2ac",
700		"reserved2b0", "reserved2b4", "reserved2b8", "reserved2bc",
701		/* 0x2c0 */
702		"{bltSrcBaseAddr}","{bltDstBaseAddr}","{bltXYStrides}","{bltSrcChromaRange}",
703		"{bltDstChromaRange}","{bltClipX}","{bltClipY}","reserved2dc",
704		"{bltSrcXY}", "{bltDstXY}", "{bltSize}", "{bltRop}",
705		"{bltColor}", "reserved2f4", "{bltCommand}", "{bltData}",
706		/* 0x300 */
707		"textureMode", "tLOD", "tDetail", "texBaseAddr",
708		"texBaseAddr_1","texBaseAddr_2","texBaseAddr_3_8","trexInit0",
709		"trexInit1", "nccTable0.0", "nccTable0.1", "nccTable0.2",
710		"nccTable0.3", "nccTable0.4", "nccTable0.5", "nccTable0.6",
711		/* 0x340 */
712		"nccTable0.7", "nccTable0.8", "nccTable0.9", "nccTable0.A",
713		"nccTable0.B", "nccTable1.0", "nccTable1.1", "nccTable1.2",
714		"nccTable1.3", "nccTable1.4", "nccTable1.5", "nccTable1.6",
715		"nccTable1.7", "nccTable1.8", "nccTable1.9", "nccTable1.A",
716		/* 0x380 */
717		"nccTable1.B"
718		};
719
720
721		static const char *const banshee_reg_name[] =
722		{
723		/* 0x000 */
724		"status", "intrCtrl", "vertexAx", "vertexAy",
725		"vertexBx", "vertexBy", "vertexCx", "vertexCy",
726		"startR", "startG", "startB", "startZ",
727		"startA", "startS", "startT", "startW",
728		/* 0x040 */
729		"dRdX", "dGdX", "dBdX", "dZdX",
730		"dAdX", "dSdX", "dTdX", "dWdX",
731		"dRdY", "dGdY", "dBdY", "dZdY",
732		"dAdY", "dSdY", "dTdY", "dWdY",
733		/* 0x080 */
734		"triangleCMD", "reserved084", "fvertexAx", "fvertexAy",
735		"fvertexBx", "fvertexBy", "fvertexCx", "fvertexCy",
736		"fstartR", "fstartG", "fstartB", "fstartZ",
737		"fstartA", "fstartS", "fstartT", "fstartW",
738		/* 0x0c0 */
739		"fdRdX", "fdGdX", "fdBdX", "fdZdX",
740		"fdAdX", "fdSdX", "fdTdX", "fdWdX",
741		"fdRdY", "fdGdY", "fdBdY", "fdZdY",
742		"fdAdY", "fdSdY", "fdTdY", "fdWdY",
743		/* 0x100 */
744		"ftriangleCMD", "fbzColorPath", "fogMode", "alphaMode",
745		"fbzMode", "lfbMode", "clipLeftRight","clipLowYHighY",
746		"nopCMD", "fastfillCMD", "swapbufferCMD","fogColor",
747		"zaColor", "chromaKey", "chromaRange", "userIntrCMD",
748		/* 0x140 */
749		"stipple", "color0", "color1", "fbiPixelsIn",
750		"fbiChromaFail","fbiZfuncFail", "fbiAfuncFail", "fbiPixelsOut",
751		"fogTable160", "fogTable164", "fogTable168", "fogTable16c",
752		"fogTable170", "fogTable174", "fogTable178", "fogTable17c",
753		/* 0x180 */
754		"fogTable180", "fogTable184", "fogTable188", "fogTable18c",
755		"fogTable190", "fogTable194", "fogTable198", "fogTable19c",
756		"fogTable1a0", "fogTable1a4", "fogTable1a8", "fogTable1ac",
757		"fogTable1b0", "fogTable1b4", "fogTable1b8", "fogTable1bc",
758		/* 0x1c0 */
759		"fogTable1c0", "fogTable1c4", "fogTable1c8", "fogTable1cc",
760		"fogTable1d0", "fogTable1d4", "fogTable1d8", "fogTable1dc",
761		"reserved1e0", "reserved1e4", "reserved1e8", "colBufferAddr",
762		"colBufferStride","auxBufferAddr","auxBufferStride","reserved1fc",
763		/* 0x200 */
764		"clipLeftRight1","clipTopBottom1","reserved208","reserved20c",
765		"reserved210", "reserved214", "reserved218", "reserved21c",
766		"reserved220", "reserved224", "reserved228", "reserved22c",
767		"reserved230", "reserved234", "reserved238", "reserved23c",
768		/* 0x240 */
769		"reserved240", "reserved244", "reserved248", "swapPending",
770		"leftOverlayBuf","rightOverlayBuf","fbiSwapHistory","fbiTrianglesOut",
771		"sSetupMode", "sVx", "sVy", "sARGB",
772		"sRed", "sGreen", "sBlue", "sAlpha",
773		/* 0x280 */
774		"sVz", "sWb", "sWtmu0", "sS/Wtmu0",
775		"sT/Wtmu0", "sWtmu1", "sS/Wtmu1", "sT/Wtmu1",
776		"sDrawTriCMD", "sBeginTriCMD", "reserved2a8", "reserved2ac",
777		"reserved2b0", "reserved2b4", "reserved2b8", "reserved2bc",
778		/* 0x2c0 */
779		"reserved2c0", "reserved2c4", "reserved2c8", "reserved2cc",
780		"reserved2d0", "reserved2d4", "reserved2d8", "reserved2dc",
781		"reserved2e0", "reserved2e4", "reserved2e8", "reserved2ec",
782		"reserved2f0", "reserved2f4", "reserved2f8", "reserved2fc",
783		/* 0x300 */
784		"textureMode", "tLOD", "tDetail", "texBaseAddr",
785		"texBaseAddr_1","texBaseAddr_2","texBaseAddr_3_8","reserved31c",
786		"trexInit1", "nccTable0.0", "nccTable0.1", "nccTable0.2",
787		"nccTable0.3", "nccTable0.4", "nccTable0.5", "nccTable0.6",
788		/* 0x340 */
789		"nccTable0.7", "nccTable0.8", "nccTable0.9", "nccTable0.A",
790		"nccTable0.B", "nccTable1.0", "nccTable1.1", "nccTable1.2",
791		"nccTable1.3", "nccTable1.4", "nccTable1.5", "nccTable1.6",
792		"nccTable1.7", "nccTable1.8", "nccTable1.9", "nccTable1.A",
793		/* 0x380 */
794		"nccTable1.B"
795		};
796
797
798
799		/*************************************
800		*
801		* Voodoo Banshee I/O space registers
802		*
803		*************************************/
804
805		/* 0x000 */
806		#define io_status (0x000/4) /* */
807		#define io_pciInit0 (0x004/4) /* */
808		#define io_sipMonitor (0x008/4) /* */
809		#define io_lfbMemoryConfig (0x00c/4) /* */
810		#define io_miscInit0 (0x010/4) /* */
811		#define io_miscInit1 (0x014/4) /* */
812		#define io_dramInit0 (0x018/4) /* */
813		#define io_dramInit1 (0x01c/4) /* */
814		#define io_agpInit (0x020/4) /* */
815		#define io_tmuGbeInit (0x024/4) /* */
816		#define io_vgaInit0 (0x028/4) /* */
817		#define io_vgaInit1 (0x02c/4) /* */
818		#define io_dramCommand (0x030/4) /* */
819		#define io_dramData (0x034/4) /* */
820
821		/* 0x040 */
822		#define io_pllCtrl0 (0x040/4) /* */
823		#define io_pllCtrl1 (0x044/4) /* */
824		#define io_pllCtrl2 (0x048/4) /* */
825		#define io_dacMode (0x04c/4) /* */
826		#define io_dacAddr (0x050/4) /* */
827		#define io_dacData (0x054/4) /* */
828		#define io_rgbMaxDelta (0x058/4) /* */
829		#define io_vidProcCfg (0x05c/4) /* */
830		#define io_hwCurPatAddr (0x060/4) /* */
831		#define io_hwCurLoc (0x064/4) /* */
832		#define io_hwCurC0 (0x068/4) /* */
833		#define io_hwCurC1 (0x06c/4) /* */
834		#define io_vidInFormat (0x070/4) /* */
835		#define io_vidInStatus (0x074/4) /* */
836		#define io_vidSerialParallelPort (0x078/4) /* */
837		#define io_vidInXDecimDeltas (0x07c/4) /* */
838
839		/* 0x080 */
840		#define io_vidInDecimInitErrs (0x080/4) /* */
841		#define io_vidInYDecimDeltas (0x084/4) /* */
842		#define io_vidPixelBufThold (0x088/4) /* */
843		#define io_vidChromaMin (0x08c/4) /* */
844		#define io_vidChromaMax (0x090/4) /* */
845		#define io_vidCurrentLine (0x094/4) /* */
846		#define io_vidScreenSize (0x098/4) /* */
847		#define io_vidOverlayStartCoords (0x09c/4) /* */
848		#define io_vidOverlayEndScreenCoord (0x0a0/4) /* */
849		#define io_vidOverlayDudx (0x0a4/4) /* */
850		#define io_vidOverlayDudxOffsetSrcWidth (0x0a8/4) /* */
851		#define io_vidOverlayDvdy (0x0ac/4) /* */
852		#define io_vgab0 (0x0b0/4) /* */
853		#define io_vgab4 (0x0b4/4) /* */
854		#define io_vgab8 (0x0b8/4) /* */
855		#define io_vgabc (0x0bc/4) /* */
856
857		/* 0x0c0 */
858		#define io_vgac0 (0x0c0/4) /* */
859		#define io_vgac4 (0x0c4/4) /* */
860		#define io_vgac8 (0x0c8/4) /* */
861		#define io_vgacc (0x0cc/4) /* */
862		#define io_vgad0 (0x0d0/4) /* */
863		#define io_vgad4 (0x0d4/4) /* */
864		#define io_vgad8 (0x0d8/4) /* */
865		#define io_vgadc (0x0dc/4) /* */
866		#define io_vidOverlayDvdyOffset (0x0e0/4) /* */
867		#define io_vidDesktopStartAddr (0x0e4/4) /* */
868		#define io_vidDesktopOverlayStride (0x0e8/4) /* */
869		#define io_vidInAddr0 (0x0ec/4) /* */
870		#define io_vidInAddr1 (0x0f0/4) /* */
871		#define io_vidInAddr2 (0x0f4/4) /* */
872		#define io_vidInStride (0x0f8/4) /* */
873		#define io_vidCurrOverlayStartAddr (0x0fc/4) /* */
874
875
876
877		/*************************************
878		*
879		* Register string table for debug
880		*
881		*************************************/
882
883		static const char *const banshee_io_reg_name[] =
884		{
885		/* 0x000 */
886		"status", "pciInit0", "sipMonitor", "lfbMemoryConfig",
887		"miscInit0", "miscInit1", "dramInit0", "dramInit1",
888		"agpInit", "tmuGbeInit", "vgaInit0", "vgaInit1",
889		"dramCommand", "dramData", "reserved38", "reserved3c",
890
891		/* 0x040 */
892		"pllCtrl0", "pllCtrl1", "pllCtrl2", "dacMode",
893		"dacAddr", "dacData", "rgbMaxDelta", "vidProcCfg",
894		"hwCurPatAddr", "hwCurLoc", "hwCurC0", "hwCurC1",
895		"vidInFormat", "vidInStatus", "vidSerialParallelPort","vidInXDecimDeltas",
896
897		/* 0x080 */
898		"vidInDecimInitErrs","vidInYDecimDeltas","vidPixelBufThold","vidChromaMin",
899		"vidChromaMax", "vidCurrentLine","vidScreenSize","vidOverlayStartCoords",
900		"vidOverlayEndScreenCoord","vidOverlayDudx","vidOverlayDudxOffsetSrcWidth","vidOverlayDvdy",
901		"vga[b0]", "vga[b4]", "vga[b8]", "vga[bc]",
902
903		/* 0x0c0 */
904		"vga[c0]", "vga[c4]", "vga[c8]", "vga[cc]",
905		"vga[d0]", "vga[d4]", "vga[d8]", "vga[dc]",
906		"vidOverlayDvdyOffset","vidDesktopStartAddr","vidDesktopOverlayStride","vidInAddr0",
907		"vidInAddr1", "vidInAddr2", "vidInStride", "vidCurrOverlayStartAddr"
908		};
909
910
911
912		/*************************************
913		*
914		* Voodoo Banshee AGP space registers
915		*
916		*************************************/
917
918		/* 0x000 */
919		#define agpReqSize (0x000/4) /* */
920		#define agpHostAddressLow (0x004/4) /* */
921		#define agpHostAddressHigh (0x008/4) /* */
922		#define agpGraphicsAddress (0x00c/4) /* */
923		#define agpGraphicsStride (0x010/4) /* */
924		#define agpMoveCMD (0x014/4) /* */
925		#define cmdBaseAddr0 (0x020/4) /* */
926		#define cmdBaseSize0 (0x024/4) /* */
927		#define cmdBump0 (0x028/4) /* */
928		#define cmdRdPtrL0 (0x02c/4) /* */
929		#define cmdRdPtrH0 (0x030/4) /* */
930		#define cmdAMin0 (0x034/4) /* */
931		#define cmdAMax0 (0x03c/4) /* */
932
933		/* 0x040 */
934		#define cmdFifoDepth0 (0x044/4) /* */
935		#define cmdHoleCnt0 (0x048/4) /* */
936		#define cmdBaseAddr1 (0x050/4) /* */
937		#define cmdBaseSize1 (0x054/4) /* */
938		#define cmdBump1 (0x058/4) /* */
939		#define cmdRdPtrL1 (0x05c/4) /* */
940		#define cmdRdPtrH1 (0x060/4) /* */
941		#define cmdAMin1 (0x064/4) /* */
942		#define cmdAMax1 (0x06c/4) /* */
943		#define cmdFifoDepth1 (0x074/4) /* */
944		#define cmdHoleCnt1 (0x078/4) /* */
945
946		/* 0x080 */
947		#define cmdFifoThresh (0x080/4) /* */
948		#define cmdHoleInt (0x084/4) /* */
949
950		/* 0x100 */
951		#define yuvBaseAddress (0x100/4) /* */
952		#define yuvStride (0x104/4) /* */
953		#define crc1 (0x120/4) /* */
954		#define crc2 (0x130/4) /* */
955
956
957
958		/*************************************
959		*
960		* Register string table for debug
961		*
962		*************************************/
963
964		static const char *const banshee_agp_reg_name[] =
965		{
966		/* 0x000 */
967		"agpReqSize", "agpHostAddressLow","agpHostAddressHigh","agpGraphicsAddress",
968		"agpGraphicsStride","agpMoveCMD","reserved18", "reserved1c",
969		"cmdBaseAddr0", "cmdBaseSize0", "cmdBump0", "cmdRdPtrL0",
970		"cmdRdPtrH0", "cmdAMin0", "reserved38", "cmdAMax0",
971
972		/* 0x040 */
973		"reserved40", "cmdFifoDepth0","cmdHoleCnt0", "reserved4c",
974		"cmdBaseAddr1", "cmdBaseSize1", "cmdBump1", "cmdRdPtrL1",
975		"cmdRdPtrH1", "cmdAMin1", "reserved68", "cmdAMax1",
976		"reserved70", "cmdFifoDepth1","cmdHoleCnt1", "reserved7c",
977
978		/* 0x080 */
979		"cmdFifoThresh","cmdHoleInt", "reserved88", "reserved8c",
980		"reserved90", "reserved94", "reserved98", "reserved9c",
981		"reserveda0", "reserveda4", "reserveda8", "reservedac",
982		"reservedb0", "reservedb4", "reservedb8", "reservedbc",
983
984		/* 0x0c0 */
985		"reservedc0", "reservedc4", "reservedc8", "reservedcc",
986		"reservedd0", "reservedd4", "reservedd8", "reserveddc",
987		"reservede0", "reservede4", "reservede8", "reservedec",
988		"reservedf0", "reservedf4", "reservedf8", "reservedfc",
989
990		/* 0x100 */
991		"yuvBaseAddress","yuvStride", "reserved108", "reserved10c",
992		"reserved110", "reserved114", "reserved118", "reserved11c",
993		"crc1", "reserved124", "reserved128", "reserved12c",
994		"crc2", "reserved134", "reserved138", "reserved13c"
995		};
996
997
998
999		/*************************************
1000		*
1001		* Dithering tables
1002		*
1003		*************************************/
1004
1005		static const UINT8 dither_matrix_4x4[16] =
1006		{
1007		0, 8, 2, 10,
1008		12, 4, 14, 6,
1009		3, 11, 1, 9,
1010		15, 7, 13, 5
1011		};
1012
1013		static const UINT8 dither_matrix_2x2[16] =
1014		{
1015		2, 10, 2, 10,
1016		14, 6, 14, 6,
1017		2, 10, 2, 10,
1018		14, 6, 14, 6
1019		};
1020
1021
1022
1023		/*************************************
1024		*
1025		* Macros for extracting pixels
1026		*
1027		*************************************/
1028
1029		#define EXTRACT_565_TO_888(val, a, b, c) \
1030		(a) = (((val) >> 8) & 0xf8) \| (((val) >> 13) & 0x07); \
1031		(b) = (((val) >> 3) & 0xfc) \| (((val) >> 9) & 0x03); \
1032		(c) = (((val) << 3) & 0xf8) \| (((val) >> 2) & 0x07);
1033		#define EXTRACT_x555_TO_888(val, a, b, c) \
1034		(a) = (((val) >> 7) & 0xf8) \| (((val) >> 12) & 0x07); \
1035		(b) = (((val) >> 2) & 0xf8) \| (((val) >> 7) & 0x07); \
1036		(c) = (((val) << 3) & 0xf8) \| (((val) >> 2) & 0x07);
1037		#define EXTRACT_555x_TO_888(val, a, b, c) \
1038		(a) = (((val) >> 8) & 0xf8) \| (((val) >> 13) & 0x07); \
1039		(b) = (((val) >> 3) & 0xf8) \| (((val) >> 8) & 0x07); \
1040		(c) = (((val) << 2) & 0xf8) \| (((val) >> 3) & 0x07);
1041		#define EXTRACT_1555_TO_8888(val, a, b, c, d) \
1042		(a) = ((INT16)(val) >> 15) & 0xff; \
1043		EXTRACT_x555_TO_888(val, b, c, d)
1044		#define EXTRACT_5551_TO_8888(val, a, b, c, d) \
1045		EXTRACT_555x_TO_888(val, a, b, c) \
1046		(d) = ((val) & 0x0001) ? 0xff : 0x00;
1047		#define EXTRACT_x888_TO_888(val, a, b, c) \
1048		(a) = ((val) >> 16) & 0xff; \
1049		(b) = ((val) >> 8) & 0xff; \
1050		(c) = ((val) >> 0) & 0xff;
1051		#define EXTRACT_888x_TO_888(val, a, b, c) \
1052		(a) = ((val) >> 24) & 0xff; \
1053		(b) = ((val) >> 16) & 0xff; \
1054		(c) = ((val) >> 8) & 0xff;
1055		#define EXTRACT_8888_TO_8888(val, a, b, c, d) \
1056		(a) = ((val) >> 24) & 0xff; \
1057		(b) = ((val) >> 16) & 0xff; \
1058		(c) = ((val) >> 8) & 0xff; \
1059		(d) = ((val) >> 0) & 0xff;
1060		#define EXTRACT_4444_TO_8888(val, a, b, c, d) \
1061		(a) = (((val) >> 8) & 0xf0) \| (((val) >> 12) & 0x0f); \
1062		(b) = (((val) >> 4) & 0xf0) \| (((val) >> 8) & 0x0f); \
1063		(c) = (((val) >> 0) & 0xf0) \| (((val) >> 4) & 0x0f); \
1064		(d) = (((val) << 4) & 0xf0) \| (((val) >> 0) & 0x0f);
1065		#define EXTRACT_332_TO_888(val, a, b, c) \
1066		(a) = (((val) >> 0) & 0xe0) \| (((val) >> 3) & 0x1c) \| (((val) >> 6) & 0x03); \
1067		(b) = (((val) << 3) & 0xe0) \| (((val) >> 0) & 0x1c) \| (((val) >> 3) & 0x03); \
1068		(c) = (((val) << 6) & 0xc0) \| (((val) << 4) & 0x30) \| (((val) << 2) & 0x0c) \| (((val) << 0) & 0x03);
1069
1070
1071		/*************************************
1072		*
1073		* Misc. macros
1074		*
1075		*************************************/
1076
1077		/* macro for clamping a value between minimum and maximum values */
1078		#define CLAMP(val,min,max) do { if ((val) < (min)) { (val) = (min); } else if ((val) > (max)) { (val) = (max); } } while (0)
1079
1080		/* macro to compute the base 2 log for LOD calculations */
1081		#define LOGB2(x) (log((double)(x)) / log(2.0))
1082
1083
1084
1085		/*************************************
1086		*
1087		* Macros for extracting bitfields
1088		*
1089		*************************************/
1090
1091		#define INITEN_ENABLE_HW_INIT(val) (((val) >> 0) & 1)
1092		#define INITEN_ENABLE_PCI_FIFO(val) (((val) >> 1) & 1)
1093		#define INITEN_REMAP_INIT_TO_DAC(val) (((val) >> 2) & 1)
1094		#define INITEN_ENABLE_SNOOP0(val) (((val) >> 4) & 1)
1095		#define INITEN_SNOOP0_MEMORY_MATCH(val) (((val) >> 5) & 1)
1096		#define INITEN_SNOOP0_READWRITE_MATCH(val) (((val) >> 6) & 1)
1097		#define INITEN_ENABLE_SNOOP1(val) (((val) >> 7) & 1)
1098		#define INITEN_SNOOP1_MEMORY_MATCH(val) (((val) >> 8) & 1)
1099		#define INITEN_SNOOP1_READWRITE_MATCH(val) (((val) >> 9) & 1)
1100		#define INITEN_SLI_BUS_OWNER(val) (((val) >> 10) & 1)
1101		#define INITEN_SLI_ODD_EVEN(val) (((val) >> 11) & 1)
1102		#define INITEN_SECONDARY_REV_ID(val) (((val) >> 12) & 0xf) /* voodoo 2 only */
1103		#define INITEN_MFCTR_FAB_ID(val) (((val) >> 16) & 0xf) /* voodoo 2 only */
1104		#define INITEN_ENABLE_PCI_INTERRUPT(val) (((val) >> 20) & 1) /* voodoo 2 only */
1105		#define INITEN_PCI_INTERRUPT_TIMEOUT(val) (((val) >> 21) & 1) /* voodoo 2 only */
1106		#define INITEN_ENABLE_NAND_TREE_TEST(val) (((val) >> 22) & 1) /* voodoo 2 only */
1107		#define INITEN_ENABLE_SLI_ADDRESS_SNOOP(val) (((val) >> 23) & 1) /* voodoo 2 only */
1108		#define INITEN_SLI_SNOOP_ADDRESS(val) (((val) >> 24) & 0xff) /* voodoo 2 only */
1109
1110		#define FBZCP_CC_RGBSELECT(val) (((val) >> 0) & 3)
1111		#define FBZCP_CC_ASELECT(val) (((val) >> 2) & 3)
1112		#define FBZCP_CC_LOCALSELECT(val) (((val) >> 4) & 1)
1113		#define FBZCP_CCA_LOCALSELECT(val) (((val) >> 5) & 3)
1114		#define FBZCP_CC_LOCALSELECT_OVERRIDE(val) (((val) >> 7) & 1)
1115		#define FBZCP_CC_ZERO_OTHER(val) (((val) >> 8) & 1)
1116		#define FBZCP_CC_SUB_CLOCAL(val) (((val) >> 9) & 1)
1117		#define FBZCP_CC_MSELECT(val) (((val) >> 10) & 7)
1118		#define FBZCP_CC_REVERSE_BLEND(val) (((val) >> 13) & 1)
1119		#define FBZCP_CC_ADD_ACLOCAL(val) (((val) >> 14) & 3)
1120		#define FBZCP_CC_INVERT_OUTPUT(val) (((val) >> 16) & 1)
1121		#define FBZCP_CCA_ZERO_OTHER(val) (((val) >> 17) & 1)
1122		#define FBZCP_CCA_SUB_CLOCAL(val) (((val) >> 18) & 1)
1123		#define FBZCP_CCA_MSELECT(val) (((val) >> 19) & 7)
1124		#define FBZCP_CCA_REVERSE_BLEND(val) (((val) >> 22) & 1)
1125		#define FBZCP_CCA_ADD_ACLOCAL(val) (((val) >> 23) & 3)
1126		#define FBZCP_CCA_INVERT_OUTPUT(val) (((val) >> 25) & 1)
1127		#define FBZCP_CCA_SUBPIXEL_ADJUST(val) (((val) >> 26) & 1)
1128		#define FBZCP_TEXTURE_ENABLE(val) (((val) >> 27) & 1)
1129		#define FBZCP_RGBZW_CLAMP(val) (((val) >> 28) & 1) /* voodoo 2 only */
1130		#define FBZCP_ANTI_ALIAS(val) (((val) >> 29) & 1) /* voodoo 2 only */
1131
1132		#define ALPHAMODE_ALPHATEST(val) (((val) >> 0) & 1)
1133		#define ALPHAMODE_ALPHAFUNCTION(val) (((val) >> 1) & 7)
1134		#define ALPHAMODE_ALPHABLEND(val) (((val) >> 4) & 1)
1135		#define ALPHAMODE_ANTIALIAS(val) (((val) >> 5) & 1)
1136		#define ALPHAMODE_SRCRGBBLEND(val) (((val) >> 8) & 15)
1137		#define ALPHAMODE_DSTRGBBLEND(val) (((val) >> 12) & 15)
1138		#define ALPHAMODE_SRCALPHABLEND(val) (((val) >> 16) & 15)
1139		#define ALPHAMODE_DSTALPHABLEND(val) (((val) >> 20) & 15)
1140		#define ALPHAMODE_ALPHAREF(val) (((val) >> 24) & 0xff)
1141
1142		#define FOGMODE_ENABLE_FOG(val) (((val) >> 0) & 1)
1143		#define FOGMODE_FOG_ADD(val) (((val) >> 1) & 1)
1144		#define FOGMODE_FOG_MULT(val) (((val) >> 2) & 1)
1145		#define FOGMODE_FOG_ZALPHA(val) (((val) >> 3) & 3)
1146		#define FOGMODE_FOG_CONSTANT(val) (((val) >> 5) & 1)
1147		#define FOGMODE_FOG_DITHER(val) (((val) >> 6) & 1) /* voodoo 2 only */
1148		#define FOGMODE_FOG_ZONES(val) (((val) >> 7) & 1) /* voodoo 2 only */
1149
1150		#define FBZMODE_ENABLE_CLIPPING(val) (((val) >> 0) & 1)
1151		#define FBZMODE_ENABLE_CHROMAKEY(val) (((val) >> 1) & 1)
1152		#define FBZMODE_ENABLE_STIPPLE(val) (((val) >> 2) & 1)
1153		#define FBZMODE_WBUFFER_SELECT(val) (((val) >> 3) & 1)
1154		#define FBZMODE_ENABLE_DEPTHBUF(val) (((val) >> 4) & 1)
1155		#define FBZMODE_DEPTH_FUNCTION(val) (((val) >> 5) & 7)
1156		#define FBZMODE_ENABLE_DITHERING(val) (((val) >> 8) & 1)
1157		#define FBZMODE_RGB_BUFFER_MASK(val) (((val) >> 9) & 1)
1158		#define FBZMODE_AUX_BUFFER_MASK(val) (((val) >> 10) & 1)
1159		#define FBZMODE_DITHER_TYPE(val) (((val) >> 11) & 1)
1160		#define FBZMODE_STIPPLE_PATTERN(val) (((val) >> 12) & 1)
1161		#define FBZMODE_ENABLE_ALPHA_MASK(val) (((val) >> 13) & 1)
1162		#define FBZMODE_DRAW_BUFFER(val) (((val) >> 14) & 3)
1163		#define FBZMODE_ENABLE_DEPTH_BIAS(val) (((val) >> 16) & 1)
1164		#define FBZMODE_Y_ORIGIN(val) (((val) >> 17) & 1)
1165		#define FBZMODE_ENABLE_ALPHA_PLANES(val) (((val) >> 18) & 1)
1166		#define FBZMODE_ALPHA_DITHER_SUBTRACT(val) (((val) >> 19) & 1)
1167		#define FBZMODE_DEPTH_SOURCE_COMPARE(val) (((val) >> 20) & 1)
1168		#define FBZMODE_DEPTH_FLOAT_SELECT(val) (((val) >> 21) & 1) /* voodoo 2 only */
1169
1170		#define LFBMODE_WRITE_FORMAT(val) (((val) >> 0) & 0xf)
1171		#define LFBMODE_WRITE_BUFFER_SELECT(val) (((val) >> 4) & 3)
1172		#define LFBMODE_READ_BUFFER_SELECT(val) (((val) >> 6) & 3)
1173		#define LFBMODE_ENABLE_PIXEL_PIPELINE(val) (((val) >> 8) & 1)
1174		#define LFBMODE_RGBA_LANES(val) (((val) >> 9) & 3)
1175		#define LFBMODE_WORD_SWAP_WRITES(val) (((val) >> 11) & 1)
1176		#define LFBMODE_BYTE_SWIZZLE_WRITES(val) (((val) >> 12) & 1)
1177		#define LFBMODE_Y_ORIGIN(val) (((val) >> 13) & 1)
1178		#define LFBMODE_WRITE_W_SELECT(val) (((val) >> 14) & 1)
1179		#define LFBMODE_WORD_SWAP_READS(val) (((val) >> 15) & 1)
1180		#define LFBMODE_BYTE_SWIZZLE_READS(val) (((val) >> 16) & 1)
1181
1182		#define CHROMARANGE_BLUE_EXCLUSIVE(val) (((val) >> 24) & 1)
1183		#define CHROMARANGE_GREEN_EXCLUSIVE(val) (((val) >> 25) & 1)
1184		#define CHROMARANGE_RED_EXCLUSIVE(val) (((val) >> 26) & 1)
1185		#define CHROMARANGE_UNION_MODE(val) (((val) >> 27) & 1)
1186		#define CHROMARANGE_ENABLE(val) (((val) >> 28) & 1)
1187
1188		#define FBIINIT0_VGA_PASSTHRU(val) (((val) >> 0) & 1)
1189		#define FBIINIT0_GRAPHICS_RESET(val) (((val) >> 1) & 1)
1190		#define FBIINIT0_FIFO_RESET(val) (((val) >> 2) & 1)
1191		#define FBIINIT0_SWIZZLE_REG_WRITES(val) (((val) >> 3) & 1)
1192		#define FBIINIT0_STALL_PCIE_FOR_HWM(val) (((val) >> 4) & 1)
1193		#define FBIINIT0_PCI_FIFO_LWM(val) (((val) >> 6) & 0x1f)
1194		#define FBIINIT0_LFB_TO_MEMORY_FIFO(val) (((val) >> 11) & 1)
1195		#define FBIINIT0_TEXMEM_TO_MEMORY_FIFO(val) (((val) >> 12) & 1)
1196		#define FBIINIT0_ENABLE_MEMORY_FIFO(val) (((val) >> 13) & 1)
1197		#define FBIINIT0_MEMORY_FIFO_HWM(val) (((val) >> 14) & 0x7ff)
1198		#define FBIINIT0_MEMORY_FIFO_BURST(val) (((val) >> 25) & 0x3f)
1199
1200		#define FBIINIT1_PCI_DEV_FUNCTION(val) (((val) >> 0) & 1)
1201		#define FBIINIT1_PCI_WRITE_WAIT_STATES(val) (((val) >> 1) & 1)
1202		#define FBIINIT1_MULTI_SST1(val) (((val) >> 2) & 1) /* not on voodoo 2 */
1203		#define FBIINIT1_ENABLE_LFB(val) (((val) >> 3) & 1)
1204		#define FBIINIT1_X_VIDEO_TILES(val) (((val) >> 4) & 0xf)
1205		#define FBIINIT1_VIDEO_TIMING_RESET(val) (((val) >> 8) & 1)
1206		#define FBIINIT1_SOFTWARE_OVERRIDE(val) (((val) >> 9) & 1)
1207		#define FBIINIT1_SOFTWARE_HSYNC(val) (((val) >> 10) & 1)
1208		#define FBIINIT1_SOFTWARE_VSYNC(val) (((val) >> 11) & 1)
1209		#define FBIINIT1_SOFTWARE_BLANK(val) (((val) >> 12) & 1)
1210		#define FBIINIT1_DRIVE_VIDEO_TIMING(val) (((val) >> 13) & 1)
1211		#define FBIINIT1_DRIVE_VIDEO_BLANK(val) (((val) >> 14) & 1)
1212		#define FBIINIT1_DRIVE_VIDEO_SYNC(val) (((val) >> 15) & 1)
1213		#define FBIINIT1_DRIVE_VIDEO_DCLK(val) (((val) >> 16) & 1)
1214		#define FBIINIT1_VIDEO_TIMING_VCLK(val) (((val) >> 17) & 1)
1215		#define FBIINIT1_VIDEO_CLK_2X_DELAY(val) (((val) >> 18) & 3)
1216		#define FBIINIT1_VIDEO_TIMING_SOURCE(val) (((val) >> 20) & 3)
1217		#define FBIINIT1_ENABLE_24BPP_OUTPUT(val) (((val) >> 22) & 1)
1218		#define FBIINIT1_ENABLE_SLI(val) (((val) >> 23) & 1)
1219		#define FBIINIT1_X_VIDEO_TILES_BIT5(val) (((val) >> 24) & 1) /* voodoo 2 only */
1220		#define FBIINIT1_ENABLE_EDGE_FILTER(val) (((val) >> 25) & 1)
1221		#define FBIINIT1_INVERT_VID_CLK_2X(val) (((val) >> 26) & 1)
1222		#define FBIINIT1_VID_CLK_2X_SEL_DELAY(val) (((val) >> 27) & 3)
1223		#define FBIINIT1_VID_CLK_DELAY(val) (((val) >> 29) & 3)
1224		#define FBIINIT1_DISABLE_FAST_READAHEAD(val) (((val) >> 31) & 1)
1225
1226		#define FBIINIT2_DISABLE_DITHER_SUB(val) (((val) >> 0) & 1)
1227		#define FBIINIT2_DRAM_BANKING(val) (((val) >> 1) & 1)
1228		#define FBIINIT2_ENABLE_TRIPLE_BUF(val) (((val) >> 4) & 1)
1229		#define FBIINIT2_ENABLE_FAST_RAS_READ(val) (((val) >> 5) & 1)
1230		#define FBIINIT2_ENABLE_GEN_DRAM_OE(val) (((val) >> 6) & 1)
1231		#define FBIINIT2_ENABLE_FAST_READWRITE(val) (((val) >> 7) & 1)
1232		#define FBIINIT2_ENABLE_PASSTHRU_DITHER(val) (((val) >> 8) & 1)
1233		#define FBIINIT2_SWAP_BUFFER_ALGORITHM(val) (((val) >> 9) & 3)
1234		#define FBIINIT2_VIDEO_BUFFER_OFFSET(val) (((val) >> 11) & 0x1ff)
1235		#define FBIINIT2_ENABLE_DRAM_BANKING(val) (((val) >> 20) & 1)
1236		#define FBIINIT2_ENABLE_DRAM_READ_FIFO(val) (((val) >> 21) & 1)
1237		#define FBIINIT2_ENABLE_DRAM_REFRESH(val) (((val) >> 22) & 1)
1238		#define FBIINIT2_REFRESH_LOAD_VALUE(val) (((val) >> 23) & 0x1ff)
1239
1240		#define FBIINIT3_TRI_REGISTER_REMAP(val) (((val) >> 0) & 1)
1241		#define FBIINIT3_VIDEO_FIFO_THRESH(val) (((val) >> 1) & 0x1f)
1242		#define FBIINIT3_DISABLE_TMUS(val) (((val) >> 6) & 1)
1243		#define FBIINIT3_FBI_MEMORY_TYPE(val) (((val) >> 8) & 7)
1244		#define FBIINIT3_VGA_PASS_RESET_VAL(val) (((val) >> 11) & 1)
1245		#define FBIINIT3_HARDCODE_PCI_BASE(val) (((val) >> 12) & 1)
1246		#define FBIINIT3_FBI2TREX_DELAY(val) (((val) >> 13) & 0xf)
1247		#define FBIINIT3_TREX2FBI_DELAY(val) (((val) >> 17) & 0x1f)
1248		#define FBIINIT3_YORIGIN_SUBTRACT(val) (((val) >> 22) & 0x3ff)
1249
1250		#define FBIINIT4_PCI_READ_WAITS(val) (((val) >> 0) & 1)
1251		#define FBIINIT4_ENABLE_LFB_READAHEAD(val) (((val) >> 1) & 1)
1252		#define FBIINIT4_MEMORY_FIFO_LWM(val) (((val) >> 2) & 0x3f)
1253		#define FBIINIT4_MEMORY_FIFO_START_ROW(val) (((val) >> 8) & 0x3ff)
1254		#define FBIINIT4_MEMORY_FIFO_STOP_ROW(val) (((val) >> 18) & 0x3ff)
1255		#define FBIINIT4_VIDEO_CLOCKING_DELAY(val) (((val) >> 29) & 7) /* voodoo 2 only */
1256
1257		#define FBIINIT5_DISABLE_PCI_STOP(val) (((val) >> 0) & 1) /* voodoo 2 only */
1258		#define FBIINIT5_PCI_SLAVE_SPEED(val) (((val) >> 1) & 1) /* voodoo 2 only */
1259		#define FBIINIT5_DAC_DATA_OUTPUT_WIDTH(val) (((val) >> 2) & 1) /* voodoo 2 only */
1260		#define FBIINIT5_DAC_DATA_17_OUTPUT(val) (((val) >> 3) & 1) /* voodoo 2 only */
1261		#define FBIINIT5_DAC_DATA_18_OUTPUT(val) (((val) >> 4) & 1) /* voodoo 2 only */
1262		#define FBIINIT5_GENERIC_STRAPPING(val) (((val) >> 5) & 0xf) /* voodoo 2 only */
1263		#define FBIINIT5_BUFFER_ALLOCATION(val) (((val) >> 9) & 3) /* voodoo 2 only */
1264		#define FBIINIT5_DRIVE_VID_CLK_SLAVE(val) (((val) >> 11) & 1) /* voodoo 2 only */
1265		#define FBIINIT5_DRIVE_DAC_DATA_16(val) (((val) >> 12) & 1) /* voodoo 2 only */
1266		#define FBIINIT5_VCLK_INPUT_SELECT(val) (((val) >> 13) & 1) /* voodoo 2 only */
1267		#define FBIINIT5_MULTI_CVG_DETECT(val) (((val) >> 14) & 1) /* voodoo 2 only */
1268		#define FBIINIT5_SYNC_RETRACE_READS(val) (((val) >> 15) & 1) /* voodoo 2 only */
1269		#define FBIINIT5_ENABLE_RHBORDER_COLOR(val) (((val) >> 16) & 1) /* voodoo 2 only */
1270		#define FBIINIT5_ENABLE_LHBORDER_COLOR(val) (((val) >> 17) & 1) /* voodoo 2 only */
1271		#define FBIINIT5_ENABLE_BVBORDER_COLOR(val) (((val) >> 18) & 1) /* voodoo 2 only */
1272		#define FBIINIT5_ENABLE_TVBORDER_COLOR(val) (((val) >> 19) & 1) /* voodoo 2 only */
1273		#define FBIINIT5_DOUBLE_HORIZ(val) (((val) >> 20) & 1) /* voodoo 2 only */
1274		#define FBIINIT5_DOUBLE_VERT(val) (((val) >> 21) & 1) /* voodoo 2 only */
1275		#define FBIINIT5_ENABLE_16BIT_GAMMA(val) (((val) >> 22) & 1) /* voodoo 2 only */
1276		#define FBIINIT5_INVERT_DAC_HSYNC(val) (((val) >> 23) & 1) /* voodoo 2 only */
1277		#define FBIINIT5_INVERT_DAC_VSYNC(val) (((val) >> 24) & 1) /* voodoo 2 only */
1278		#define FBIINIT5_ENABLE_24BIT_DACDATA(val) (((val) >> 25) & 1) /* voodoo 2 only */
1279		#define FBIINIT5_ENABLE_INTERLACING(val) (((val) >> 26) & 1) /* voodoo 2 only */
1280		#define FBIINIT5_DAC_DATA_18_CONTROL(val) (((val) >> 27) & 1) /* voodoo 2 only */
1281		#define FBIINIT5_RASTERIZER_UNIT_MODE(val) (((val) >> 30) & 3) /* voodoo 2 only */
1282
1283		#define FBIINIT6_WINDOW_ACTIVE_COUNTER(val) (((val) >> 0) & 7) /* voodoo 2 only */
1284		#define FBIINIT6_WINDOW_DRAG_COUNTER(val) (((val) >> 3) & 0x1f) /* voodoo 2 only */
1285		#define FBIINIT6_SLI_SYNC_MASTER(val) (((val) >> 8) & 1) /* voodoo 2 only */
1286		#define FBIINIT6_DAC_DATA_22_OUTPUT(val) (((val) >> 9) & 3) /* voodoo 2 only */
1287		#define FBIINIT6_DAC_DATA_23_OUTPUT(val) (((val) >> 11) & 3) /* voodoo 2 only */
1288		#define FBIINIT6_SLI_SYNCIN_OUTPUT(val) (((val) >> 13) & 3) /* voodoo 2 only */
1289		#define FBIINIT6_SLI_SYNCOUT_OUTPUT(val) (((val) >> 15) & 3) /* voodoo 2 only */
1290		#define FBIINIT6_DAC_RD_OUTPUT(val) (((val) >> 17) & 3) /* voodoo 2 only */
1291		#define FBIINIT6_DAC_WR_OUTPUT(val) (((val) >> 19) & 3) /* voodoo 2 only */
1292		#define FBIINIT6_PCI_FIFO_LWM_RDY(val) (((val) >> 21) & 0x7f) /* voodoo 2 only */
1293		#define FBIINIT6_VGA_PASS_N_OUTPUT(val) (((val) >> 28) & 3) /* voodoo 2 only */
1294		#define FBIINIT6_X_VIDEO_TILES_BIT0(val) (((val) >> 30) & 1) /* voodoo 2 only */
1295
1296		#define FBIINIT7_GENERIC_STRAPPING(val) (((val) >> 0) & 0xff) /* voodoo 2 only */
1297		#define FBIINIT7_CMDFIFO_ENABLE(val) (((val) >> 8) & 1) /* voodoo 2 only */
1298		#define FBIINIT7_CMDFIFO_MEMORY_STORE(val) (((val) >> 9) & 1) /* voodoo 2 only */
1299		#define FBIINIT7_DISABLE_CMDFIFO_HOLES(val) (((val) >> 10) & 1) /* voodoo 2 only */
1300		#define FBIINIT7_CMDFIFO_READ_THRESH(val) (((val) >> 11) & 0x1f) /* voodoo 2 only */
1301		#define FBIINIT7_SYNC_CMDFIFO_WRITES(val) (((val) >> 16) & 1) /* voodoo 2 only */
1302		#define FBIINIT7_SYNC_CMDFIFO_READS(val) (((val) >> 17) & 1) /* voodoo 2 only */
1303		#define FBIINIT7_RESET_PCI_PACKER(val) (((val) >> 18) & 1) /* voodoo 2 only */
1304		#define FBIINIT7_ENABLE_CHROMA_STUFF(val) (((val) >> 19) & 1) /* voodoo 2 only */
1305		#define FBIINIT7_CMDFIFO_PCI_TIMEOUT(val) (((val) >> 20) & 0x7f) /* voodoo 2 only */
1306		#define FBIINIT7_ENABLE_TEXTURE_BURST(val) (((val) >> 27) & 1) /* voodoo 2 only */
1307
1308		#define TEXMODE_ENABLE_PERSPECTIVE(val) (((val) >> 0) & 1)
1309		#define TEXMODE_MINIFICATION_FILTER(val) (((val) >> 1) & 1)
1310		#define TEXMODE_MAGNIFICATION_FILTER(val) (((val) >> 2) & 1)
1311		#define TEXMODE_CLAMP_NEG_W(val) (((val) >> 3) & 1)
1312		#define TEXMODE_ENABLE_LOD_DITHER(val) (((val) >> 4) & 1)
1313		#define TEXMODE_NCC_TABLE_SELECT(val) (((val) >> 5) & 1)
1314		#define TEXMODE_CLAMP_S(val) (((val) >> 6) & 1)
1315		#define TEXMODE_CLAMP_T(val) (((val) >> 7) & 1)
1316		#define TEXMODE_FORMAT(val) (((val) >> 8) & 0xf)
1317		#define TEXMODE_TC_ZERO_OTHER(val) (((val) >> 12) & 1)
1318		#define TEXMODE_TC_SUB_CLOCAL(val) (((val) >> 13) & 1)
1319		#define TEXMODE_TC_MSELECT(val) (((val) >> 14) & 7)
1320		#define TEXMODE_TC_REVERSE_BLEND(val) (((val) >> 17) & 1)
1321		#define TEXMODE_TC_ADD_ACLOCAL(val) (((val) >> 18) & 3)
1322		#define TEXMODE_TC_INVERT_OUTPUT(val) (((val) >> 20) & 1)
1323		#define TEXMODE_TCA_ZERO_OTHER(val) (((val) >> 21) & 1)
1324		#define TEXMODE_TCA_SUB_CLOCAL(val) (((val) >> 22) & 1)
1325		#define TEXMODE_TCA_MSELECT(val) (((val) >> 23) & 7)
1326		#define TEXMODE_TCA_REVERSE_BLEND(val) (((val) >> 26) & 1)
1327		#define TEXMODE_TCA_ADD_ACLOCAL(val) (((val) >> 27) & 3)
1328		#define TEXMODE_TCA_INVERT_OUTPUT(val) (((val) >> 29) & 1)
1329		#define TEXMODE_TRILINEAR(val) (((val) >> 30) & 1)
1330		#define TEXMODE_SEQ_8_DOWNLD(val) (((val) >> 31) & 1)
1331
1332		#define TEXLOD_LODMIN(val) (((val) >> 0) & 0x3f)
1333		#define TEXLOD_LODMAX(val) (((val) >> 6) & 0x3f)
1334		#define TEXLOD_LODBIAS(val) (((val) >> 12) & 0x3f)
1335		#define TEXLOD_LOD_ODD(val) (((val) >> 18) & 1)
1336		#define TEXLOD_LOD_TSPLIT(val) (((val) >> 19) & 1)
1337		#define TEXLOD_LOD_S_IS_WIDER(val) (((val) >> 20) & 1)
1338		#define TEXLOD_LOD_ASPECT(val) (((val) >> 21) & 3)
1339		#define TEXLOD_LOD_ZEROFRAC(val) (((val) >> 23) & 1)
1340		#define TEXLOD_TMULTIBASEADDR(val) (((val) >> 24) & 1)
1341		#define TEXLOD_TDATA_SWIZZLE(val) (((val) >> 25) & 1)
1342		#define TEXLOD_TDATA_SWAP(val) (((val) >> 26) & 1)
1343		#define TEXLOD_TDIRECT_WRITE(val) (((val) >> 27) & 1) /* Voodoo 2 only */
1344
1345		#define TEXDETAIL_DETAIL_MAX(val) (((val) >> 0) & 0xff)
1346		#define TEXDETAIL_DETAIL_BIAS(val) (((val) >> 8) & 0x3f)
1347		#define TEXDETAIL_DETAIL_SCALE(val) (((val) >> 14) & 7)
1348		#define TEXDETAIL_RGB_MIN_FILTER(val) (((val) >> 17) & 1) /* Voodoo 2 only */
1349		#define TEXDETAIL_RGB_MAG_FILTER(val) (((val) >> 18) & 1) /* Voodoo 2 only */
1350		#define TEXDETAIL_ALPHA_MIN_FILTER(val) (((val) >> 19) & 1) /* Voodoo 2 only */
1351		#define TEXDETAIL_ALPHA_MAG_FILTER(val) (((val) >> 20) & 1) /* Voodoo 2 only */
1352		#define TEXDETAIL_SEPARATE_RGBA_FILTER(val) (((val) >> 21) & 1) /* Voodoo 2 only */
1353
1354		#define TREXINIT_SEND_TMU_CONFIG(val) (((val) >> 18) & 1)
1355
1356
1357		/*************************************
1358		*
1359	16	* Core types
1360	17	*
1361	18	*************************************/
r253153	r253154
1364	21	struct poly_extra_data;
1365	22
1366	23
1367		struct rgba
1368		{
1369		#ifdef LSB_FIRST
1370		UINT8 b, g, r, a;
1371		#else
1372		UINT8 a, r, g, b;
1373		#endif
1374		};
1375	24
1376	25
1377		union voodoo_reg
1378		{
1379		INT32 i;
1380		UINT32 u;
1381		float f;
1382		rgba rgb;
1383		};
1384	26
1385
1386		typedef voodoo_reg rgb_union;
1387
1388
1389		struct voodoo_stats
1390		{
1391		UINT8 lastkey; /* last key state */
1392		UINT8 display; /* display stats? */
1393		INT32 swaps; /* total swaps */
1394		INT32 stalls; /* total stalls */
1395		INT32 total_triangles; /* total triangles */
1396		INT32 total_pixels_in; /* total pixels in */
1397		INT32 total_pixels_out; /* total pixels out */
1398		INT32 total_chroma_fail; /* total chroma fail */
1399		INT32 total_zfunc_fail; /* total z func fail */
1400		INT32 total_afunc_fail; /* total a func fail */
1401		INT32 total_clipped; /* total clipped */
1402		INT32 total_stippled; /* total stippled */
1403		INT32 lfb_writes; /* LFB writes */
1404		INT32 lfb_reads; /* LFB reads */
1405		INT32 reg_writes; /* register writes */
1406		INT32 reg_reads; /* register reads */
1407		INT32 tex_writes; /* texture writes */
1408		INT32 texture_mode[16]; /* 16 different texture modes */
1409		UINT8 render_override; /* render override */
1410		char buffer[1024]; /* string */
1411		};
1412
1413
1414		/* note that this structure is an even 64 bytes long */
1415		struct stats_block
1416		{
1417		INT32 pixels_in; /* pixels in statistic */
1418		INT32 pixels_out; /* pixels out statistic */
1419		INT32 chroma_fail; /* chroma test fail statistic */
1420		INT32 zfunc_fail; /* z function test fail statistic */
1421		INT32 afunc_fail; /* alpha function test fail statistic */
1422		INT32 clip_fail; /* clipping fail statistic */
1423		INT32 stipple_count; /* stipple statistic */
1424		INT32 filler[64/4 - 7]; /* pad this structure to 64 bytes */
1425		};
1426
1427
1428		struct fifo_state
1429		{
1430		UINT32 * base; /* base of the FIFO */
1431		INT32 size; /* size of the FIFO */
1432		INT32 in; /* input pointer */
1433		INT32 out; /* output pointer */
1434		};
1435
1436
1437		struct cmdfifo_info
1438		{
1439		UINT8 enable; /* enabled? */
1440		UINT8 count_holes; /* count holes? */
1441		UINT32 base; /* base address in framebuffer RAM */
1442		UINT32 end; /* end address in framebuffer RAM */
1443		UINT32 rdptr; /* current read pointer */
1444		UINT32 amin; /* minimum address */
1445		UINT32 amax; /* maximum address */
1446		UINT32 depth; /* current depth */
1447		UINT32 holes; /* number of holes */
1448		};
1449
1450
1451		struct pci_state
1452		{
1453		fifo_state fifo; /* PCI FIFO */
1454		UINT32 init_enable; /* initEnable value */
1455		UINT8 stall_state; /* state of the system if we're stalled */
1456		UINT8 op_pending; /* true if an operation is pending */
1457		attotime op_end_time; /* time when the pending operation ends */
1458		emu_timer * continue_timer; /* timer to use to continue processing */
1459		UINT32 fifo_mem[642]; / memory backing the PCI FIFO */
1460		};
1461
1462
1463		struct ncc_table
1464		{
1465		UINT8 dirty; /* is the texel lookup dirty? */
1466		voodoo_reg * reg; /* pointer to our registers */
1467		INT32 ir[4], ig[4], ib[4]; /* I values for R,G,B */
1468		INT32 qr[4], qg[4], qb[4]; /* Q values for R,G,B */
1469		INT32 y[16]; /* Y values */
1470		rgb_t * palette; /* pointer to associated RGB palette */
1471		rgb_t * palettea; /* pointer to associated ARGB palette */
1472		rgb_t texel[256]; /* texel lookup */
1473		};
1474
1475
1476		struct tmu_state
1477		{
1478		UINT8 * ram; /* pointer to our RAM */
1479		UINT32 mask; /* mask to apply to pointers */
1480		voodoo_reg * reg; /* pointer to our register base */
1481		UINT32 regdirty; /* true if the LOD/mode/base registers have changed */
1482
1483		UINT32 texaddr_mask; /* mask for texture address */
1484		UINT8 texaddr_shift; /* shift for texture address */
1485
1486		INT64 starts, startt; /* starting S,T (14.18) */
1487		INT64 startw; /* starting W (2.30) */
1488		INT64 dsdx, dtdx; /* delta S,T per X */
1489		INT64 dwdx; /* delta W per X */
1490		INT64 dsdy, dtdy; /* delta S,T per Y */
1491		INT64 dwdy; /* delta W per Y */
1492
1493		INT32 lodmin, lodmax; /* min, max LOD values */
1494		INT32 lodbias; /* LOD bias */
1495		UINT32 lodmask; /* mask of available LODs */
1496		UINT32 lodoffset[9]; /* offset of texture base for each LOD */
1497		INT32 detailmax; /* detail clamp */
1498		INT32 detailbias; /* detail bias */
1499		UINT8 detailscale; /* detail scale */
1500
1501		UINT32 wmask; /* mask for the current texture width */
1502		UINT32 hmask; /* mask for the current texture height */
1503
1504		UINT32 bilinear_mask; /* mask for bilinear resolution (0xf0 for V1, 0xff for V2) */
1505
1506		ncc_table ncc[2]; /* two NCC tables */
1507
1508		rgb_t * lookup; /* currently selected lookup */
1509		rgb_t * texel[16]; /* texel lookups for each format */
1510
1511		rgb_t palette[256]; /* palette lookup table */
1512		rgb_t palettea[256]; /* palette+alpha lookup table */
1513		};
1514
1515
1516		struct tmu_shared_state
1517		{
1518		rgb_t rgb332[256]; /* RGB 3-3-2 lookup table */
1519		rgb_t alpha8[256]; /* alpha 8-bit lookup table */
1520		rgb_t int8[256]; /* intensity 8-bit lookup table */
1521		rgb_t ai44[256]; /* alpha, intensity 4-4 lookup table */
1522
1523		rgb_t rgb565[65536]; /* RGB 5-6-5 lookup table */
1524		rgb_t argb1555[65536]; /* ARGB 1-5-5-5 lookup table */
1525		rgb_t argb4444[65536]; /* ARGB 4-4-4-4 lookup table */
1526		};
1527
1528
1529		struct setup_vertex
1530		{
1531		float x, y; /* X, Y coordinates */
1532		float a, r, g, b; /* A, R, G, B values */
1533		float z, wb; /* Z and broadcast W values */
1534		float w0, s0, t0; /* W, S, T for TMU 0 */
1535		float w1, s1, t1; /* W, S, T for TMU 1 */
1536		};
1537
1538
1539		struct fbi_state
1540		{
1541		UINT8 * ram; /* pointer to frame buffer RAM */
1542		UINT32 mask; /* mask to apply to pointers */
1543		UINT32 rgboffs[3]; /* word offset to 3 RGB buffers */
1544		UINT32 auxoffs; /* word offset to 1 aux buffer */
1545
1546		UINT8 frontbuf; /* front buffer index */
1547		UINT8 backbuf; /* back buffer index */
1548		UINT8 swaps_pending; /* number of pending swaps */
1549		UINT8 video_changed; /* did the frontbuffer video change? */
1550
1551		UINT32 yorigin; /* Y origin subtract value */
1552		UINT32 lfb_base; /* base of LFB in memory */
1553		UINT8 lfb_stride; /* stride of LFB accesses in bits */
1554
1555		UINT32 width; /* width of current frame buffer */
1556		UINT32 height; /* height of current frame buffer */
1557		UINT32 xoffs; /* horizontal offset (back porch) */
1558		UINT32 yoffs; /* vertical offset (back porch) */
1559		UINT32 vsyncscan; /* vertical sync scanline */
1560		UINT32 rowpixels; /* pixels per row */
1561		UINT32 tile_width; /* width of video tiles */
1562		UINT32 tile_height; /* height of video tiles */
1563		UINT32 x_tiles; /* number of tiles in the X direction */
1564
1565		emu_timer * vblank_timer; /* VBLANK timer */
1566		UINT8 vblank; /* VBLANK state */
1567		UINT8 vblank_count; /* number of VBLANKs since last swap */
1568		UINT8 vblank_swap_pending; /* a swap is pending, waiting for a vblank */
1569		UINT8 vblank_swap; /* swap when we hit this count */
1570		UINT8 vblank_dont_swap; /* don't actually swap when we hit this point */
1571
1572		/* triangle setup info */
1573		UINT8 cheating_allowed; /* allow cheating? */
1574		INT32 sign; /* triangle sign */
1575		INT16 ax, ay; /* vertex A x,y (12.4) */
1576		INT16 bx, by; /* vertex B x,y (12.4) */
1577		INT16 cx, cy; /* vertex C x,y (12.4) */
1578		INT32 startr, startg, startb, starta; /* starting R,G,B,A (12.12) */
1579		INT32 startz; /* starting Z (20.12) */
1580		INT64 startw; /* starting W (16.32) */
1581		INT32 drdx, dgdx, dbdx, dadx; /* delta R,G,B,A per X */
1582		INT32 dzdx; /* delta Z per X */
1583		INT64 dwdx; /* delta W per X */
1584		INT32 drdy, dgdy, dbdy, dady; /* delta R,G,B,A per Y */
1585		INT32 dzdy; /* delta Z per Y */
1586		INT64 dwdy; /* delta W per Y */
1587
1588		stats_block lfb_stats; /* LFB-access statistics */
1589
1590		UINT8 sverts; /* number of vertices ready */
1591		setup_vertex svert[3]; /* 3 setup vertices */
1592
1593		fifo_state fifo; /* framebuffer memory fifo */
1594		cmdfifo_info cmdfifo[2]; /* command FIFOs */
1595
1596		UINT8 fogblend[64]; /* 64-entry fog table */
1597		UINT8 fogdelta[64]; /* 64-entry fog table */
1598		UINT8 fogdelta_mask; /* mask for for delta (0xff for V1, 0xfc for V2) */
1599
1600		rgb_t pen[65536]; /* mapping from pixels to pens */
1601		rgb_t clut[512]; /* clut gamma data */
1602		UINT8 clut_dirty; /* do we need to recompute? */
1603		};
1604
1605
1606		struct dac_state
1607		{
1608		UINT8 reg[8]; /* 8 registers */
1609		UINT8 read_result; /* pending read result */
1610		};
1611
1612
1613		struct raster_info
1614		{
1615		raster_info * next; /* pointer to next entry with the same hash */
1616		poly_draw_scanline_func callback; /* callback pointer */
1617		UINT8 is_generic; /* TRUE if this is one of the generic rasterizers */
1618		UINT8 display; /* display index */
1619		UINT32 hits; /* how many hits (pixels) we've used this for */
1620		UINT32 polys; /* how many polys we've used this for */
1621		UINT32 eff_color_path; /* effective fbzColorPath value */
1622		UINT32 eff_alpha_mode; /* effective alphaMode value */
1623		UINT32 eff_fog_mode; /* effective fogMode value */
1624		UINT32 eff_fbz_mode; /* effective fbzMode value */
1625		UINT32 eff_tex_mode_0; /* effective textureMode value for TMU #0 */
1626		UINT32 eff_tex_mode_1; /* effective textureMode value for TMU #1 */
1627		UINT32 hash;
1628		};
1629
1630
1631		struct poly_extra_data
1632		{
1633		voodoo_state * state; /* pointer back to the voodoo state */
1634		raster_info * info; /* pointer to rasterizer information */
1635
1636		INT16 ax, ay; /* vertex A x,y (12.4) */
1637		INT32 startr, startg, startb, starta; /* starting R,G,B,A (12.12) */
1638		INT32 startz; /* starting Z (20.12) */
1639		INT64 startw; /* starting W (16.32) */
1640		INT32 drdx, dgdx, dbdx, dadx; /* delta R,G,B,A per X */
1641		INT32 dzdx; /* delta Z per X */
1642		INT64 dwdx; /* delta W per X */
1643		INT32 drdy, dgdy, dbdy, dady; /* delta R,G,B,A per Y */
1644		INT32 dzdy; /* delta Z per Y */
1645		INT64 dwdy; /* delta W per Y */
1646
1647		INT64 starts0, startt0; /* starting S,T (14.18) */
1648		INT64 startw0; /* starting W (2.30) */
1649		INT64 ds0dx, dt0dx; /* delta S,T per X */
1650		INT64 dw0dx; /* delta W per X */
1651		INT64 ds0dy, dt0dy; /* delta S,T per Y */
1652		INT64 dw0dy; /* delta W per Y */
1653		INT32 lodbase0; /* used during rasterization */
1654
1655		INT64 starts1, startt1; /* starting S,T (14.18) */
1656		INT64 startw1; /* starting W (2.30) */
1657		INT64 ds1dx, dt1dx; /* delta S,T per X */
1658		INT64 dw1dx; /* delta W per X */
1659		INT64 ds1dy, dt1dy; /* delta S,T per Y */
1660		INT64 dw1dy; /* delta W per Y */
1661		INT32 lodbase1; /* used during rasterization */
1662
1663		UINT16 dither[16]; /* dither matrix, for fastfill */
1664		};
1665
1666
1667		struct banshee_info
1668		{
1669		UINT32 io[0x40]; /* I/O registers */
1670		UINT32 agp[0x80]; /* AGP registers */
1671		UINT8 vga[0x20]; /* VGA registers */
1672		UINT8 crtc[0x27]; /* VGA CRTC registers */
1673		UINT8 seq[0x05]; /* VGA sequencer registers */
1674		UINT8 gc[0x05]; /* VGA graphics controller registers */
1675		UINT8 att[0x15]; /* VGA attribute registers */
1676		UINT8 attff; /* VGA attribute flip-flop */
1677
1678		UINT32 blt_regs[0x20]; /* 2D Blitter registers */
1679		UINT32 blt_dst_base;
1680		UINT32 blt_dst_x;
1681		UINT32 blt_dst_y;
1682		UINT32 blt_dst_width;
1683		UINT32 blt_dst_height;
1684		UINT32 blt_dst_stride;
1685		UINT32 blt_dst_bpp;
1686		UINT32 blt_cmd;
1687		UINT32 blt_src_base;
1688		UINT32 blt_src_x;
1689		UINT32 blt_src_y;
1690		UINT32 blt_src_width;
1691		UINT32 blt_src_height;
1692		UINT32 blt_src_stride;
1693		UINT32 blt_src_bpp;
1694		};
1695
1696
1697		struct voodoo_state
1698		{
1699		UINT8 index; /* index of board */
1700		voodoo_device device; / pointer to our containing device */
1701		screen_device screen; / the screen we are acting on */
1702		device_t cpu; / the CPU we interact with */
1703		UINT8 type; /* type of system */
1704		UINT8 chipmask; /* mask for which chips are available */
1705		UINT32 freq; /* operating frequency */
1706		attoseconds_t attoseconds_per_cycle; /* attoseconds per cycle */
1707		UINT32 extra_cycles; /* extra cycles not yet accounted for */
1708		int trigger; /* trigger used for stalling */
1709
1710		voodoo_reg reg[0x400]; /* raw registers */
1711		const UINT8 * regaccess; /* register access array */
1712		const char const regnames; /* register names array */
1713		UINT8 alt_regmap; /* enable alternate register map? */
1714
1715		pci_state pci; /* PCI state */
1716		dac_state dac; /* DAC state */
1717
1718		fbi_state fbi; /* FBI states */
1719		tmu_state tmu[MAX_TMU]; /* TMU states */
1720		tmu_shared_state tmushare; /* TMU shared state */
1721		banshee_info banshee; /* Banshee state */
1722
1723		legacy_poly_manager * poly; /* polygon manager */
1724		stats_block * thread_stats; /* per-thread statistics */
1725
1726		voodoo_stats stats; /* internal statistics */
1727
1728		offs_t last_status_pc; /* PC of last status description (for logging) */
1729		UINT32 last_status_value; /* value of last status read (for logging) */
1730
1731		int next_rasterizer; /* next rasterizer index */
1732		raster_info rasterizer[MAX_RASTERIZERS]; /* array of rasterizers */
1733		raster_info * raster_hash[RASTER_HASH_SIZE]; /* hash table of rasterizers */
1734
1735		bool send_config;
1736		UINT32 tmu_config;
1737		};
1738
1739
1740
1741	27	/*************************************
1742	28	*
1743	29	* Inline FIFO management
r253153	r253154
2345	631	} \
2346	632	while (0)
2347	633
2348		static inline bool ATTR_FORCE_INLINE chromaKeyTest(voodoo_~~stat~~e v, stats_block stats, UINT32 fbzModeReg, rgbaint_t rgbaIntColor)
	634	static inline bool ATTR_FORCE_INLINE chromaKeyTest(voodoo_device vd, stats_block stats, UINT32 fbzModeReg, rgbaint_t rgbaIntColor)
2349	635	{
2350	636	if (FBZMODE_ENABLE_CHROMAKEY(fbzModeReg))
2351	637	{
2352	638	rgb_union color;
2353	639	color.u = (rgbaIntColor.get_a()<<24) \| (rgbaIntColor.get_r()<<16) \| (rgbaIntColor.get_g()<<8) \| rgbaIntColor.get_b();
2354	640	/* non-range version */
2355		if (!CHROMARANGE_ENABLE(v->reg[chromaRange].u))
	641	if (!CHROMARANGE_ENABLE(vd->reg[chromaRange].u))
2356	642	{
2357		if (((color.u ^ v->reg[chromaKey].u) & 0xffffff) == 0)
	643	if (((color.u ^ vd->reg[chromaKey].u) & 0xffffff) == 0)
2358	644	{
2359	645	stats->chroma_fail++;
2360	646	return false;
r253153	r253154
2368	654	int results;
2369	655
2370	656	/* check blue */
2371		low = v->reg[chromaKey].rgb.b;
2372		high = v->reg[chromaRange].rgb.b;
	657	low = vd->reg[chromaKey].rgb.b;
	658	high = vd->reg[chromaRange].rgb.b;
2373	659	test = color.rgb.b;
2374	660	results = (test >= low && test <= high);
2375		results ^= CHROMARANGE_BLUE_EXCLUSIVE(v->reg[chromaRange].u);
	661	results ^= CHROMARANGE_BLUE_EXCLUSIVE(vd->reg[chromaRange].u);
2376	662	results <<= 1;
2377	663
2378	664	/* check green */
2379		low = v->reg[chromaKey].rgb.g;
2380		high = v->reg[chromaRange].rgb.g;
	665	low = vd->reg[chromaKey].rgb.g;
	666	high = vd->reg[chromaRange].rgb.g;
2381	667	test = color.rgb.g;
2382	668	results \|= (test >= low && test <= high);
2383		results ^= CHROMARANGE_GREEN_EXCLUSIVE(v->reg[chromaRange].u);
	669	results ^= CHROMARANGE_GREEN_EXCLUSIVE(vd->reg[chromaRange].u);
2384	670	results <<= 1;
2385	671
2386	672	/* check red */
2387		low = v->reg[chromaKey].rgb.r;
2388		high = v->reg[chromaRange].rgb.r;
	673	low = vd->reg[chromaKey].rgb.r;
	674	high = vd->reg[chromaRange].rgb.r;
2389	675	test = color.rgb.r;
2390	676	results \|= (test >= low && test <= high);
2391		results ^= CHROMARANGE_RED_EXCLUSIVE(v->reg[chromaRange].u);
	677	results ^= CHROMARANGE_RED_EXCLUSIVE(vd->reg[chromaRange].u);
2392	678
2393	679	/* final result */
2394		if (CHROMARANGE_UNION_MODE(v->reg[chromaRange].u))
	680	if (CHROMARANGE_UNION_MODE(vd->reg[chromaRange].u))
2395	681	{
2396	682	if (results != 0)
2397	683	{
r253153	r253154
2520	806	} \
2521	807	while (0)
2522	808
2523		static inline bool ATTR_FORCE_INLINE alphaTest(voodoo_~~stat~~e v, stats_block stats, UINT32 alphaModeReg, UINT8 alpha)
	809	static inline bool ATTR_FORCE_INLINE alphaTest(voodoo_device vd, stats_block stats, UINT32 alphaModeReg, UINT8 alpha)
2524	810	{
2525	811	if (ALPHAMODE_ALPHATEST(alphaModeReg))
2526	812	{
2527		UINT8 alpharef = v->reg[alphaMode].rgb.a;
	813	UINT8 alpharef = vd->reg[alphaMode].rgb.a;
2528	814	switch (ALPHAMODE_ALPHAFUNCTION(alphaModeReg))
2529	815	{
2530	816	case 0: /* alphaOP = never */
r253153	r253154
3067	1353	} \
3068	1354	while (0)
3069	1355
3070		static inline void ATTR_FORCE_INLINE applyFogging(voodoo_~~stat~~e v, UINT32 fogModeReg, UINT32 fbzCpReg, INT32 x, const UINT8 dither4, INT32 fogDepth,
	1356	static inline void ATTR_FORCE_INLINE applyFogging(voodoo_device vd, UINT32 fogModeReg, UINT32 fbzCpReg, INT32 x, const UINT8 dither4, INT32 fogDepth,
3071	1357	rgbaint_t &color, INT32 iterz, INT64 iterw, UINT8 itera)
3072	1358	{
3073	1359	if (FOGMODE_ENABLE_FOG(fogModeReg))
r253153	r253154
3075	1361	UINT32 color_alpha = color.get_a();
3076	1362
3077	1363	/* constant fog bypasses everything else */
3078		rgbaint_t fogColorLocal(v->reg[fogColor].u);
	1364	rgbaint_t fogColorLocal(vd->reg[fogColor].u);
3079	1365
3080	1366	if (FOGMODE_FOG_CONSTANT(fogModeReg))
3081	1367	{
r253153	r253154
3119	1405	{
3120	1406	case 0: /* fog table */
3121	1407	{
3122		INT32 delta = v->fbi.fogdelta[fogDepth >> 10];
	1408	INT32 delta = vd->fbi.fogdelta[fogDepth >> 10];
3123	1409	INT32 deltaval;
3124	1410
3125	1411	/* perform the multiply against lower 8 bits of wfloat */
3126		deltaval = (delta & v->fbi.fogdelta_mask) *
	1412	deltaval = (delta & vd->fbi.fogdelta_mask) *
3127	1413	((fogDepth >> 2) & 0xff);
3128	1414
3129	1415	/* fog zones allow for negating this value */
r253153	r253154
3137	1423	deltaval >>= 4;
3138	1424
3139	1425	/* add to the blending factor */
3140		fogblend = v->fbi.fogblend[fogDepth >> 10] + deltaval;
	1426	fogblend = vd->fbi.fogblend[fogDepth >> 10] + deltaval;
3141	1427	break;
3142	1428	}
3143	1429
r253153	r253154
3542	1828	*
3543	1829	*************************************/
3544	1830
3545		#define PIXEL_PIPELINE_BEGIN(VV, STATS, XX, YY, FBZCOLORPATH, FBZMODE, ITERZ, ITERW) \
	1831	#define PIXEL_PIPELINE_BEGIN(vd, STATS, XX, YY, FBZCOLORPATH, FBZMODE, ITERZ, ITERW) \
3546	1832	do \
3547	1833	{ \
3548	1834	INT32 depthval, wfloat, fogdepth, biasdepth; \
r253153	r253154
3559	1845	/* rotate mode */ \
3560	1846	if (FBZMODE_STIPPLE_PATTERN(FBZMODE) == 0) \
3561	1847	{ \
3562		(VV)->reg[stipple].u = ((VV)->reg[stipple].u << 1) \| ((VV)->reg[stipple].u >> 31);\
3563		if (((VV)->reg[stipple].u & 0x80000000) == 0) \
	1848	vd->reg[stipple].u = (vd->reg[stipple].u << 1) \| (vd->reg[stipple].u >> 31);\
	1849	if ((vd->reg[stipple].u & 0x80000000) == 0) \
3564	1850	{ \
3565		~~(VV)~~->stats.total_stippled++; \
	1851	vd->stats.total_stippled++; \
3566	1852	goto skipdrawdepth; \
3567	1853	} \
3568	1854	} \
r253153	r253154
3571	1857	else \
3572	1858	{ \
3573	1859	int stipple_index = (((YY) & 3) << 3) \| (~(XX) & 7); \
3574		if (((~~(VV)~~->reg[stipple].u >> stipple_index) & 1) == 0) \
	1860	if (((vd->reg[stipple].u >> stipple_index) & 1) == 0) \
3575	1861	{ \
3576		~~(VV)~~->stats.total_stippled++; \
	1862	vd->stats.total_stippled++; \
3577	1863	goto skipdrawdepth; \
3578	1864	} \
3579	1865	} \
r253153	r253154
3597	1883	/* add the bias for fog selection*/ \
3598	1884	if (FBZMODE_ENABLE_DEPTH_BIAS(FBZMODE)) \
3599	1885	{ \
3600		fogdepth += (INT16)~~(VV)~~->reg[zaColor].u; \
	1886	fogdepth += (INT16)vd->reg[zaColor].u; \
3601	1887	CLAMP(fogdepth, 0, 0xffff); \
3602	1888	} \
3603	1889	\
r253153	r253154
3628	1914	biasdepth = depthval; \
3629	1915	if (FBZMODE_ENABLE_DEPTH_BIAS(FBZMODE)) \
3630	1916	{ \
3631		biasdepth += (INT16)~~(VV)~~->reg[zaColor].u; \
	1917	biasdepth += (INT16)vd->reg[zaColor].u; \
3632	1918	CLAMP(biasdepth, 0, 0xffff); \
3633	1919	}
3634	1920
3635	1921
3636		#define DEPTH_TEST(VV, STATS, XX, FBZMODE) \
	1922	#define DEPTH_TEST(vd, STATS, XX, FBZMODE) \
3637	1923	do \
3638	1924	{ \
3639	1925	/* handle depth buffer testing */ \
r253153	r253154
3646	1932	if (FBZMODE_DEPTH_SOURCE_COMPARE(FBZMODE) == 0) \
3647	1933	depthsource = biasdepth; \
3648	1934	else \
3649		depthsource = (UINT16)~~(VV)~~->reg[zaColor].u; \
	1935	depthsource = (UINT16)vd->reg[zaColor].u; \
3650	1936	\
3651	1937	/* test against the depth buffer */ \
3652	1938	switch (FBZMODE_DEPTH_FUNCTION(FBZMODE)) \
r253153	r253154
3786	2072	return true;
3787	2073	}
3788	2074
3789		#define PIXEL_PIPELINE_END(VV, STATS, DITHER, DITHER4, DITHER_LOOKUP, XX, dest, depth, FBZMODE, FBZCOLORPATH, ALPHAMODE, FOGMODE, ITERZ, ITERW, ITERAXXX) \
	2075	#define PIXEL_PIPELINE_END(vd, STATS, DITHER, DITHER4, DITHER_LOOKUP, XX, dest, depth, FBZMODE, FBZCOLORPATH, ALPHAMODE, FOGMODE, ITERZ, ITERW, ITERAXXX) \
3790	2076	\
3791	2077	/* perform fogging */ \
3792	2078	preFog.set(color); \
3793		applyFogging(VV, FOGMODE, FBZCOLORPATH, XX, DITHER4, fogdepth, color, ITERZ, ITERW, ITERAXXX.get_a()); \
	2079	applyFogging(vd, FOGMODE, FBZCOLORPATH, XX, DITHER4, fogdepth, color, ITERZ, ITERW, ITERAXXX.get_a()); \
3794	2080	/* perform alpha blending */ \
3795	2081	alphaBlend(FBZMODE, ALPHAMODE, XX, DITHER, dest[XX], depth, preFog, color); \
3796	2082	a = color.get_a(); r = color.get_r(); g = color.get_g(); b = color.get_b(); \
r253153	r253154
4121	2407	} \
4122	2408	while (0)
4123	2409
4124		static inline bool ATTR_FORCE_INLINE combineColor(voodoo_~~stat~~e VV, stats_block STATS, UINT32 FBZCOLORPATH, UINT32 FBZMODE, UINT32 ALPHAMODE,
	2410	static inline bool ATTR_FORCE_INLINE combineColor(voodoo_device vd, stats_block STATS, UINT32 FBZCOLORPATH, UINT32 FBZMODE, UINT32 ALPHAMODE,
4125	2411	rgbaint_t TEXELARGB, INT32 ITERZ, INT64 ITERW, rgbaint_t &srcColor)
4126	2412	{
4127	2413	rgbaint_t c_other;
r253153	r253154
4139	2425	break;
4140	2426
4141	2427	case 2: /* color1 RGB */
4142		c_other.set(~~(VV)~~->reg[color1].u);
	2428	c_other.set(vd->reg[color1].u);
4143	2429	break;
4144	2430
4145	2431	default: /* reserved - voodoo3 framebufferRGB */
r253153	r253154
4148	2434	}
4149	2435
4150	2436	/* handle chroma key */
4151		if (!chromaKeyTest(VV, STATS, FBZMODE, c_other))
	2437	if (!chromaKeyTest(vd, STATS, FBZMODE, c_other))
4152	2438	return false;
4153		//APPLY_CHROMAKEY(VV, STATS, FBZMODE, c_other);
	2439	//APPLY_CHROMAKEY(vd->m_vds, STATS, FBZMODE, c_other);
4154	2440
4155	2441	/* compute a_other */
4156	2442	switch (FBZCP_CC_ASELECT(FBZCOLORPATH))
r253153	r253154
4164	2450	break;
4165	2451
4166	2452	case 2: /* color1 alpha */
4167		c_other.set_a(~~(VV)~~->reg[color1].rgb.a);
	2453	c_other.set_a(vd->reg[color1].rgb.a);
4168	2454	break;
4169	2455
4170	2456	default: /* reserved */
r253153	r253154
4175	2461	/* handle alpha mask */
4176	2462	if (!alphaMaskTest(STATS, FBZMODE, c_other.get_a()))
4177	2463	return false;
4178		//APPLY_ALPHAMASK(VV, STATS, FBZMODE, c_other.rgb.a);
	2464	//APPLY_ALPHAMASK(vd->m_vds, STATS, FBZMODE, c_other.rgb.a);
4179	2465
4180	2466
4181	2467	/* compute c_local */
r253153	r253154
4184	2470	if (FBZCP_CC_LOCALSELECT(FBZCOLORPATH) == 0) /* iterated RGB */
4185	2471	c_local.set(srcColor);
4186	2472	else /* color0 RGB */
4187		c_local.set(~~(VV)~~->reg[color0].u);
	2473	c_local.set(vd->reg[color0].u);
4188	2474	}
4189	2475	else
4190	2476	{
4191	2477	if (!(TEXELARGB.get_a() & 0x80)) /* iterated RGB */
4192	2478	c_local.set(srcColor);
4193	2479	else /* color0 RGB */
4194		c_local.set(~~(VV)~~->reg[color0].u);
	2480	c_local.set(vd->reg[color0].u);
4195	2481	}
4196	2482
4197	2483	/* compute a_local */
r253153	r253154
4203	2489	break;
4204	2490
4205	2491	case 1: /* color0 alpha */
4206		c_local.set_a(~~(VV)~~->reg[color0].rgb.a);
	2492	c_local.set_a(vd->reg[color0].rgb.a);
4207	2493	break;
4208	2494
4209	2495	case 2: /* clamped iterated Z[27:20] */
r253153	r253154
4355	2641
4356	2642
4357	2643	/* handle alpha test */
4358		if (!alphaTest(VV, STATS, ALPHAMODE, srcColor.get_a()))
	2644	if (!alphaTest(vd, STATS, ALPHAMODE, srcColor.get_a()))
4359	2645	return false;
4360		//APPLY_ALPHATEST(VV, STATS, ALPHAMODE, color.rgb.a);
	2646	//APPLY_ALPHATEST(vd->m_vds, STATS, ALPHAMODE, color.rgb.a);
4361	2647
4362	2648	return true;
4363	2649	}
r253153	r253154
4372	2658
4373	2659	#define RASTERIZER(name, TMUS, FBZCOLORPATH, FBZMODE, ALPHAMODE, FOGMODE, TEXMODE0, TEXMODE1) \
4374	2660	\
4375		~~static~~ void raster_##name(void destbase, INT32 y, const poly_extent extent, const void *extradata, int threadid) \
	2661	void voodoo_device::raster_##name(void destbase, INT32 y, const poly_extent extent, const void *extradata, int threadid) \
4376	2662	{ \
4377	2663	const poly_extra_data extra = (const poly_extra_data )extradata; \
4378		voodoo_state *v = extra->state; \
4379		stats_block *stats = &v->thread_stats[threadid]; \
	2664	voodoo_device *vd = extra->device; \
	2665	stats_block *stats = &vd->thread_stats[threadid]; \
4380	2666	DECLARE_DITHER_POINTERS; \
4381	2667	INT32 startx = extent->startx; \
4382	2668	INT32 stopx = extent->stopx; \
r253153	r253154
4394	2680	/* determine the screen Y */ \
4395	2681	scry = y; \
4396	2682	if (FBZMODE_Y_ORIGIN(FBZMODE)) \
4397		scry = (v->fbi.yorigin - y) & 0x3ff; \
	2683	scry = (vd->fbi.yorigin - y) & 0x3ff; \
4398	2684	\
4399	2685	/* compute dithering */ \
4400	2686	COMPUTE_DITHER_POINTERS(FBZMODE, y); \
r253153	r253154
4405	2691	INT32 tempclip; \
4406	2692	\
4407	2693	/* Y clipping buys us the whole scanline */ \
4408		if (scry < ((v->reg[clipLowYHighY].u >> 16) & 0x3ff) \|\| \
4409		scry >= (v->reg[clipLowYHighY].u & 0x3ff)) \
	2694	if (scry < ((vd->reg[clipLowYHighY].u >> 16) & 0x3ff) \|\| \
	2695	scry >= (vd->reg[clipLowYHighY].u & 0x3ff)) \
4410	2696	{ \
4411	2697	stats->pixels_in += stopx - startx; \
4412	2698	stats->clip_fail += stopx - startx; \
r253153	r253154
4414	2700	} \
4415	2701	\
4416	2702	/* X clipping */ \
4417		tempclip = (v->reg[clipLeftRight].u >> 16) & 0x3ff; \
	2703	tempclip = (vd->reg[clipLeftRight].u >> 16) & 0x3ff; \
4418	2704	if (startx < tempclip) \
4419	2705	{ \
4420	2706	stats->pixels_in += tempclip - startx; \
4421		v->stats.total_clipped += tempclip - startx; \
	2707	vd->stats.total_clipped += tempclip - startx; \
4422	2708	startx = tempclip; \
4423	2709	} \
4424		tempclip = v->reg[clipLeftRight].u & 0x3ff; \
	2710	tempclip = vd->reg[clipLeftRight].u & 0x3ff; \
4425	2711	if (stopx >= tempclip) \
4426	2712	{ \
4427	2713	stats->pixels_in += stopx - tempclip; \
4428		v->stats.total_clipped += stopx - tempclip; \
	2714	vd->stats.total_clipped += stopx - tempclip; \
4429	2715	stopx = tempclip - 1; \
4430	2716	} \
4431	2717	} \
4432	2718	\
4433	2719	/* get pointers to the target buffer and depth buffer */ \
4434		dest = (UINT16 )destbase + scry v->fbi.rowpixels; \
4435		depth = (v->fbi.auxoffs != ~0) ? ((UINT16 )(v->fbi.ram + v->fbi.auxoffs) + scry v->fbi.rowpixels) : NULL; \
	2720	dest = (UINT16 )destbase + scry vd->fbi.rowpixels; \
	2721	depth = (vd->fbi.auxoffs != ~0) ? ((UINT16 )(vd->fbi.ram + vd->fbi.auxoffs) + scry vd->fbi.rowpixels) : NULL; \
4436	2722	\
4437	2723	/* compute the starting parameters */ \
4438	2724	dx = startx - (extra->ax >> 4); \
r253153	r253154
4465	2751	rgbaint_t color, preFog; \
4466	2752	\
4467	2753	/* pixel pipeline part 1 handles depth setup and stippling */ \
4468		PIXEL_PIPELINE_BEGIN(v, stats, x, y, FBZCOLORPATH, FBZMODE, iterz, iterw); \
	2754	PIXEL_PIPELINE_BEGIN(vd, stats, x, y, FBZCOLORPATH, FBZMODE, iterz, iterw); \
4469	2755	/* depth testing */ \
4470		if (!depthTest((UINT16) v->reg[zaColor].u, stats, depth[x], FBZMODE, biasdepth)) \
	2756	if (!depthTest((UINT16) vd->reg[zaColor].u, stats, depth[x], FBZMODE, biasdepth)) \
4471	2757	goto skipdrawdepth; \
4472	2758	\
4473	2759	/* run the texture pipeline on TMU1 to produce a value in texel */ \
4474	2760	/* note that they set LOD min to 8 to "disable" a TMU */ \
4475		if (TMUS >= 2 && v->tmu[1].lodmin < (8 << 8)) { \
	2761	if (TMUS >= 2 && vd->tmu[1].lodmin < (8 << 8)) { \
4476	2762	INT32 tmp; \
4477	2763	const rgbaint_t texelZero(0); \
4478		texel = genTexture(&v->tmu[1], x, dither4, TEXMODE1, v->tmu[1].lookup, extra->lodbase1, \
	2764	texel = genTexture(&vd->tmu[1], x, dither4, TEXMODE1, vd->tmu[1].lookup, extra->lodbase1, \
4479	2765	iters1, itert1, iterw1, tmp); \
4480		texel = combineTexture(&v->tmu[1], TEXMODE1, texel, texelZero, tmp); \
	2766	texel = combineTexture(&vd->tmu[1], TEXMODE1, texel, texelZero, tmp); \
4481	2767	} \
4482	2768	/* run the texture pipeline on TMU0 to produce a final */ \
4483	2769	/* result in texel */ \
4484	2770	/* note that they set LOD min to 8 to "disable" a TMU */ \
4485		if (TMUS >= 1 && v->tmu[0].lodmin < (8 << 8)) \
	2771	if (TMUS >= 1 && vd->tmu[0].lodmin < (8 << 8)) \
4486	2772	{ \
4487		if (!v->send_config) \
	2773	if (!vd->send_config) \
4488	2774	{ \
4489	2775	INT32 lod0; \
4490	2776	rgbaint_t texelT0; \
4491		texelT0 = genTexture(&v->tmu[0], x, dither4, TEXMODE0, v->tmu[0].lookup, extra->lodbase0, \
	2777	texelT0 = genTexture(&vd->tmu[0], x, dither4, TEXMODE0, vd->tmu[0].lookup, extra->lodbase0, \
4492	2778	iters0, itert0, iterw0, lod0); \
4493		texel = combineTexture(&v->tmu[0], TEXMODE0, texelT0, texel, lod0); \
	2779	texel = combineTexture(&vd->tmu[0], TEXMODE0, texelT0, texel, lod0); \
4494	2780	} \
4495	2781	else \
4496	2782	{ \
4497		texel.set(v->tmu_config); \
	2783	texel.set(vd->tmu_config); \
4498	2784	} \
4499	2785	} \
4500	2786	\
4501	2787	/* colorpath pipeline selects source colors and does blending */ \
4502	2788	color = clampARGB(iterargb, FBZCOLORPATH); \
4503		if (!combineColor(v, stats, FBZCOLORPATH, FBZMODE, ALPHAMODE, texel, iterz, iterw, color)) \
	2789	if (!combineColor(vd, stats, FBZCOLORPATH, FBZMODE, ALPHAMODE, texel, iterz, iterw, color)) \
4504	2790	goto skipdrawdepth; \
4505	2791	\
4506	2792	/* pixel pipeline part 2 handles fog, alpha, and final output */ \
4507		PIXEL_PIPELINE_END(v, stats, dither, dither4, dither_lookup, x, dest, depth, \
	2793	PIXEL_PIPELINE_END(vd, stats, dither, dither4, dither_lookup, x, dest, depth, \
4508	2794	FBZMODE, FBZCOLORPATH, ALPHAMODE, FOGMODE, \
4509	2795	iterz, iterw, iterargb); \
4510	2796	\

trunk/src/devices/video/voodoo.cpp
r253153	r253154
143	143
144	144
145	145	#include "emu.h"
146		~~#include "video/polylgcy.h"~~
	146
147	147	#include "video/rgbutil.h"
148	148	#include "voodoo.h"
149	149	#include "vooddefs.h"
r253153	r253154
194	194
195	195
196	196
197		/*************************************
198		*
199		* Prototypes
200		*
201		*************************************/
202	197
203		static void init_fbi(voodoo_state v, fbi_state f, void *memory, int fbmem);
204		static void init_tmu_shared(tmu_shared_state *s);
205		static void init_tmu(voodoo_state v, tmu_state t, voodoo_reg reg, void memory, int tmem);
206		static void soft_reset(voodoo_state *v);
207		static void recompute_video_memory(voodoo_state *v);
208		static void check_stalled_cpu(voodoo_state *v, attotime current_time);
209		static void flush_fifos(voodoo_state *v, attotime current_time);
210		static TIMER_CALLBACK( stall_cpu_callback );
211		static void stall_cpu(voodoo_state *v, int state, attotime current_time);
212		static TIMER_CALLBACK( vblank_callback );
213		static INT32 register_w(voodoo_state *v, offs_t offset, UINT32 data);
214		static INT32 lfb_direct_w(voodoo_state *v, offs_t offset, UINT32 data, UINT32 mem_mask);
215		static INT32 lfb_w(voodoo_state *v, offs_t offset, UINT32 data, UINT32 mem_mask);
216		static INT32 texture_w(voodoo_state *v, offs_t offset, UINT32 data);
217		static INT32 banshee_2d_w(voodoo_state *v, offs_t offset, UINT32 data);
218	198
219		/* command handlers */
220		static INT32 fastfill(voodoo_state *v);
221		static INT32 swapbuffer(voodoo_state *v, UINT32 data);
222		static INT32 triangle(voodoo_state *v);
223		static INT32 begin_triangle(voodoo_state *v);
224		static INT32 draw_triangle(voodoo_state *v);
225
226		/* triangle helpers */
227		static INT32 setup_and_draw_triangle(voodoo_state *v);
228		static INT32 triangle_create_work_item(voodoo_state v, UINT16 drawbuf, int texcount);
229
230		/* rasterizer management */
231		static raster_info add_rasterizer(voodoo_state v, const raster_info *cinfo);
232		static raster_info find_rasterizer(voodoo_state v, int texcount);
233		static void dump_rasterizer_stats(voodoo_state *v);
234
235		/* generic rasterizers */
236		static void raster_fastfill(void dest, INT32 scanline, const poly_extent extent, const void *extradata, int threadid);
237		static void raster_generic_0tmu(void dest, INT32 scanline, const poly_extent extent, const void *extradata, int threadid);
238		static void raster_generic_1tmu(void dest, INT32 scanline, const poly_extent extent, const void *extradata, int threadid);
239		static void raster_generic_2tmu(void dest, INT32 scanline, const poly_extent extent, const void *extradata, int threadid);
240
241
242
243	199	/*************************************
244	200	*
245	201	* Specific rasterizers
r253153	r253154
262	218	*************************************/
263	219
264	220	#define RASTERIZER_ENTRY(fbzcp, alpha, fog, fbz, tex0, tex1) \
265		{ NULL, raster_##fbzcp##_##alpha##_##fog##_##fbz##_##tex0##_##tex1, FALSE, 0, 0, 0, fbzcp, alpha, fog, fbz, tex0, tex1 },
	221	{ NULL, voodoo_device::raster_##fbzcp##_##alpha##_##fog##_##fbz##_##tex0##_##tex1, FALSE, 0, 0, 0, fbzcp, alpha, fog, fbz, tex0, tex1 },
266	222
267	223	static const raster_info predef_raster_table[] =
268	224	{
r253153	r253154
278	234	INLINE FUNCTIONS
279	235	***************************************************************************/
280	236
281		/*-------------------------------------------------
282		get_safe_token - makes sure that the passed
283		in device is, in fact, a voodoo device
284		-------------------------------------------------*/
285
286		static inline voodoo_state get_safe_token(device_t device)
287		{
288		assert(device != nullptr);
289		assert((device->type() == VOODOO_1) \|\| (device->type() == VOODOO_2) \|\| (device->type() == VOODOO_BANSHEE) \|\| (device->type() == VOODOO_3));
290
291		return (voodoo_state )downcast<voodoo_device >(device)->token();
292		}
293
294
295
296	237	/*************************************
297	238	*
298	239	* Video update
299	240	*
300	241	*************************************/
301	242
302		int voodoo_update~~(de~~vice_t *de~~vice,~~ bitmap_rgb32 &bitmap, const rectangle &cliprect)
	243	int voodoo_device::voodoo_update(bitmap_rgb32 &bitmap, const rectangle &cliprect)
303	244	{
304		voodoo_state *v = get_safe_token(device);
305		int changed = v->fbi.video_changed;
306		int drawbuf = v->fbi.frontbuf;
	245	int changed = fbi.video_changed;
	246	int drawbuf = fbi.frontbuf;
307	247	int statskey;
308	248	int x, y;
309	249
310	250	/* reset the video changed flag */
311		~~v->~~fbi.video_changed = FALSE;
	251	fbi.video_changed = FALSE;
312	252
313	253	/* if we are blank, just fill with black */
314		if (v->type <= TYPE_VOODOO_2 && FBIINIT1_SOFTWARE_BLANK(~~v->~~reg[fbiInit1].u))
	254	if (vd_type <= TYPE_VOODOO_2 && FBIINIT1_SOFTWARE_BLANK(reg[fbiInit1].u))
315	255	{
316	256	bitmap.fill(0, cliprect);
317	257	return changed;
318	258	}
319	259
320	260	/* if the CLUT is dirty, recompute the pens array */
321		if (~~v->~~fbi.clut_dirty)
	261	if (fbi.clut_dirty)
322	262	{
323	263	UINT8 rtable[32], gtable[64], btable[32];
324	264
325	265	/* Voodoo/Voodoo-2 have an internal 33-entry CLUT */
326		if (v->type <= TYPE_VOODOO_2)
	266	if (vd_type <= TYPE_VOODOO_2)
327	267	{
328	268	/* kludge: some of the Midway games write 0 to the last entry when they obviously mean FF */
329		if ((v->fbi.clut[32] & 0xffffff) == 0 && (v->fbi.clut[31] & 0xffffff) != 0)
330		v->fbi.clut[32] = 0x20ffffff;
	269	if ((fbi.clut[32] & 0xffffff) == 0 && (fbi.clut[31] & 0xffffff) != 0)
	270	fbi.clut[32] = 0x20ffffff;
331	271
332	272	/* compute the R/G/B pens first */
333	273	for (x = 0; x < 32; x++)
334	274	{
335	275	/* treat X as a 5-bit value, scale up to 8 bits, and linear interpolate for red/blue */
336	276	y = (x << 3) \| (x >> 2);
337		rtable[x] = (v->fbi.clut[y >> 3].r() * (8 - (y & 7)) + v->fbi.clut[(y >> 3) + 1].r() * (y & 7)) >> 3;
338		btable[x] = (v->fbi.clut[y >> 3].b() * (8 - (y & 7)) + v->fbi.clut[(y >> 3) + 1].b() * (y & 7)) >> 3;
	277	rtable[x] = (fbi.clut[y >> 3].r() * (8 - (y & 7)) + fbi.clut[(y >> 3) + 1].r() * (y & 7)) >> 3;
	278	btable[x] = (fbi.clut[y >> 3].b() * (8 - (y & 7)) + fbi.clut[(y >> 3) + 1].b() * (y & 7)) >> 3;
339	279
340	280	/* treat X as a 6-bit value with LSB=0, scale up to 8 bits, and linear interpolate */
341	281	y = (x * 2) + 0;
342	282	y = (y << 2) \| (y >> 4);
343		gtable[x2+0] = (~~v->~~fbi.clut[y >> 3].g() (8 - (y & 7)) + ~~v->~~fbi.clut[(y >> 3) + 1].g() * (y & 7)) >> 3;
	283	gtable[x2+0] = (fbi.clut[y >> 3].g() (8 - (y & 7)) + fbi.clut[(y >> 3) + 1].g() * (y & 7)) >> 3;
344	284
345	285	/* treat X as a 6-bit value with LSB=1, scale up to 8 bits, and linear interpolate */
346	286	y = (x * 2) + 1;
347	287	y = (y << 2) \| (y >> 4);
348		gtable[x2+1] = (~~v->~~fbi.clut[y >> 3].g() (8 - (y & 7)) + ~~v->~~fbi.clut[(y >> 3) + 1].g() * (y & 7)) >> 3;
	288	gtable[x2+1] = (fbi.clut[y >> 3].g() (8 - (y & 7)) + fbi.clut[(y >> 3) + 1].g() * (y & 7)) >> 3;
349	289	}
350	290	}
351	291
352	292	/* Banshee and later have a 512-entry CLUT that can be bypassed */
353	293	else
354	294	{
355		int which = (v->banshee.io[io_vidProcCfg] >> 13) & 1;
356		int bypass = (v->banshee.io[io_vidProcCfg] >> 11) & 1;
	295	int which = (banshee.io[io_vidProcCfg] >> 13) & 1;
	296	int bypass = (banshee.io[io_vidProcCfg] >> 11) & 1;
357	297
358	298	/* compute R/G/B pens first */
359	299	for (x = 0; x < 32; x++)
360	300	{
361	301	/* treat X as a 5-bit value, scale up to 8 bits */
362	302	y = (x << 3) \| (x >> 2);
363		rtable[x] = bypass ? y : v->fbi.clut[which * 256 + y].r();
364		btable[x] = bypass ? y : v->fbi.clut[which * 256 + y].b();
	303	rtable[x] = bypass ? y : fbi.clut[which * 256 + y].r();
	304	btable[x] = bypass ? y : fbi.clut[which * 256 + y].b();
365	305
366	306	/* treat X as a 6-bit value with LSB=0, scale up to 8 bits */
367	307	y = (x * 2) + 0;
368	308	y = (y << 2) \| (y >> 4);
369		gtable[x2+0] = bypass ? y : ~~v->~~fbi.clut[which 256 + y].g();
	309	gtable[x2+0] = bypass ? y : fbi.clut[which 256 + y].g();
370	310
371	311	/* treat X as a 6-bit value with LSB=1, scale up to 8 bits, and linear interpolate */
372	312	y = (x * 2) + 1;
373	313	y = (y << 2) \| (y >> 4);
374		gtable[x2+1] = bypass ? y : ~~v->~~fbi.clut[which 256 + y].g();
	314	gtable[x2+1] = bypass ? y : fbi.clut[which 256 + y].g();
375	315	}
376	316	}
377	317
r253153	r253154
381	321	int r = rtable[(x >> 11) & 0x1f];
382	322	int g = gtable[(x >> 5) & 0x3f];
383	323	int b = btable[x & 0x1f];
384		~~v->~~fbi.pen[x] = rgb_t(r, g, b);
	324	fbi.pen[x] = rgb_t(r, g, b);
385	325	}
386	326
387	327	/* no longer dirty */
388		~~v->~~fbi.clut_dirty = FALSE;
	328	fbi.clut_dirty = FALSE;
389	329	changed = TRUE;
390	330	}
391	331
392	332	/* debugging! */
393		if (device->machine().input().code_pressed(KEYCODE_L))
394		drawbuf = v->fbi.backbuf;
	333	if (machine().input().code_pressed(KEYCODE_L))
	334	drawbuf = fbi.backbuf;
395	335
396	336	/* copy from the current front buffer */
397	337	for (y = cliprect.min_y; y <= cliprect.max_y; y++)
398		if (y >= ~~v->~~fbi.yoffs)
	338	if (y >= fbi.yoffs)
399	339	{
400		UINT16 src = (UINT16 )(~~v->~~fbi.ram + ~~v->~~fbi.rgboffs[drawbuf]) + (y - ~~v->~~fbi.yoffs) * ~~v->~~fbi.rowpixels - ~~v->~~fbi.xoffs;
	340	UINT16 src = (UINT16 )(fbi.ram + fbi.rgboffs[drawbuf]) + (y - fbi.yoffs) * fbi.rowpixels - fbi.xoffs;
401	341	UINT32 *dst = &bitmap.pix32(y);
402	342	for (x = cliprect.min_x; x <= cliprect.max_x; x++)
403		dst[x] = ~~v->~~fbi.pen[src[x]];
	343	dst[x] = fbi.pen[src[x]];
404	344	}
405	345
406	346	/* update stats display */
407		statskey = (device->machine().input().code_pressed(KEYCODE_BACKSLASH) != 0);
408		if (statskey && statskey != v->stats.lastkey)
409		v->stats.display = !v->stats.display;
410		v->stats.lastkey = statskey;
	347	statskey = (machine().input().code_pressed(KEYCODE_BACKSLASH) != 0);
	348	if (statskey && statskey != stats.lastkey)
	349	stats.display = !stats.display;
	350	stats.lastkey = statskey;
411	351
412	352	/* display stats */
413		if (v->stats.display)
414		device->popmessage(v->stats.buffer, 0, 0);
	353	if (stats.display)
	354	popmessage(stats.buffer, 0, 0);
415	355
416	356	/* update render override */
417		v->stats.render_override = device->machine().input().code_pressed(KEYCODE_ENTER);
418		if (DEBUG_DEPTH && v->stats.render_override)
	357	stats.render_override = machine().input().code_pressed(KEYCODE_ENTER);
	358	if (DEBUG_DEPTH && stats.render_override)
419	359	{
420	360	for (y = cliprect.min_y; y <= cliprect.max_y; y++)
421	361	{
422		UINT16 src = (UINT16 )(~~v->~~fbi.ram + ~~v->~~fbi.auxoffs) + (y - ~~v->~~fbi.yoffs) * ~~v->~~fbi.rowpixels - ~~v->~~fbi.xoffs;
	362	UINT16 src = (UINT16 )(fbi.ram + fbi.auxoffs) + (y - fbi.yoffs) * fbi.rowpixels - fbi.xoffs;
423	363	UINT32 *dst = &bitmap.pix32(y);
424	364	for (x = cliprect.min_x; x <= cliprect.max_x; x++)
425	365	dst[x] = ((src[x] << 8) & 0xff0000) \| ((src[x] >> 0) & 0xff00) \| ((src[x] >> 8) & 0xff);
r253153	r253154
436	376	*
437	377	*************************************/
438	378
439		int voodoo_get_type(device_t *device)
	379
	380	int voodoo_device::voodoo_get_type()
440	381	{
441		voodoo_state *v = get_safe_token(device);
442		return v->type;
	382	voodoo_device *vd = this;
	383	return vd->vd_type;
443	384	}
444	385
445	386
446		int voodoo_is_stalled(~~device_t *device~~)
	387	int voodoo_device::voodoo_is_stalled()
447	388	{
448		voodoo_state *v = get_safe_token(device);
449		return (v->pci.stall_state != NOT_STALLED);
	389	voodoo_device *vd = this;
	390	return (vd->pci.stall_state != NOT_STALLED);
450	391	}
451	392
452	393
453		void voodoo_set_init_enable(~~device_t *device,~~ UINT32 newval)
	394	void voodoo_device::voodoo_set_init_enable(UINT32 newval)
454	395	{
455		voodoo_state *v = get_safe_token(device);
456		v->pci.init_enable = newval;
	396	voodoo_device *vd = this;
	397	vd->pci.init_enable = newval;
457	398	if (LOG_REGISTERS)
458		~~device->~~logerror("VOODOO.%d.REG:initEnable write = %08X\n", v->index, newval);
	399	logerror("VOODOO.%d.REG:initEnable write = %08X\n", vd->index, newval);
459	400	}
460	401
461	402
r253153	r253154
466	407	*
467	408	*************************************/
468	409
469		~~static~~ void init_fbi(voodoo_~~stat~~e v, fbi_state f, void *memory, int fbmem)
	410	void voodoo_device::init_fbi(voodoo_device* vd,fbi_state f, void memory, int fbmem)
470	411	{
471	412	int pen;
472	413
r253153	r253154
484	425
485	426	/* init the pens */
486	427	f->clut_dirty = TRUE;
487		if (v->type <= TYPE_VOODOO_2)
	428	if (vd->vd_type <= TYPE_VOODOO_2)
488	429	{
489	430	for (pen = 0; pen < 32; pen++)
490		v->fbi.clut[pen] = rgb_t(pen, pal5bit(pen), pal5bit(pen), pal5bit(pen));
491		v->fbi.clut[32] = rgb_t(32,0xff,0xff,0xff);
	431	vd->fbi.clut[pen] = rgb_t(pen, pal5bit(pen), pal5bit(pen), pal5bit(pen));
	432	vd->fbi.clut[32] = rgb_t(32,0xff,0xff,0xff);
492	433	}
493	434	else
494	435	{
495	436	for (pen = 0; pen < 512; pen++)
496		v->fbi.clut[pen] = rgb_t(pen,pen,pen);
	437	vd->fbi.clut[pen] = rgb_t(pen,pen,pen);
497	438	}
498	439
499	440	/* allocate a VBLANK timer */
500		f->vblank_timer = v->device->machine().scheduler().timer_alloc(FUNC(vblank_callback), v);
	441	f->vblank_timer = vd->device->machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(voodoo_device::vblank_callback),vd), vd);
501	442	f->vblank = FALSE;
502	443
503	444	/* initialize the memory FIFO */
r253153	r253154
505	446	f->fifo.size = f->fifo.in = f->fifo.out = 0;
506	447
507	448	/* set the fog delta mask */
508		f->fogdelta_mask = (v->type < TYPE_VOODOO_2) ? 0xff : 0xfc;
	449	f->fogdelta_mask = (vd->vd_type < TYPE_VOODOO_2) ? 0xff : 0xfc;
509	450	}
510	451
511	452
512		~~static~~ void init_tmu_shared(tmu_shared_state *s)
	453	void voodoo_device::init_tmu_shared(tmu_shared_state *s)
513	454	{
514	455	int val;
515	456
r253153	r253154
554	495	}
555	496
556	497
557		~~static~~ void init_tmu(voodoo_~~stat~~e v, tmu_state t, voodoo_reg reg, void memory, int tmem)
	498	void voodoo_device::init_tmu(voodoo_device* vd, tmu_state t, voodoo_reg reg, void *memory, int tmem)
558	499	{
559	500	/* allocate texture RAM */
560	501	t->ram = (UINT8 *)memory;
561	502	t->mask = tmem - 1;
562	503	t->reg = reg;
563	504	t->regdirty = TRUE;
564		t->bilinear_mask = (v->type >= TYPE_VOODOO_2) ? 0xff : 0xf0;
	505	t->bilinear_mask = (vd->vd_type >= TYPE_VOODOO_2) ? 0xff : 0xf0;
565	506
566	507	/* mark the NCC tables dirty and configure their registers */
567	508	t->ncc[0].dirty = t->ncc[1].dirty = TRUE;
r253153	r253154
569	510	t->ncc[1].reg = &t->reg[nccTable+12];
570	511
571	512	/* create pointers to all the tables */
572		t->texel[0] = v->tmushare.rgb332;
	513	t->texel[0] = vd->tmushare.rgb332;
573	514	t->texel[1] = t->ncc[0].texel;
574		t->texel[2] = v->tmushare.alpha8;
575		t->texel[3] = v->tmushare.int8;
576		t->texel[4] = v->tmushare.ai44;
	515	t->texel[2] = vd->tmushare.alpha8;
	516	t->texel[3] = vd->tmushare.int8;
	517	t->texel[4] = vd->tmushare.ai44;
577	518	t->texel[5] = t->palette;
578		t->texel[6] = (v->type >= TYPE_VOODOO_2) ? t->palettea : nullptr;
	519	t->texel[6] = (vd->vd_type >= TYPE_VOODOO_2) ? t->palettea : nullptr;
579	520	t->texel[7] = nullptr;
580		t->texel[8] = v->tmushare.rgb332;
	521	t->texel[8] = vd->tmushare.rgb332;
581	522	t->texel[9] = t->ncc[0].texel;
582		t->texel[10] = v->tmushare.rgb565;
583		t->texel[11] = v->tmushare.argb1555;
584		t->texel[12] = v->tmushare.argb4444;
585		t->texel[13] = v->tmushare.int8;
	523	t->texel[10] = vd->tmushare.rgb565;
	524	t->texel[11] = vd->tmushare.argb1555;
	525	t->texel[12] = vd->tmushare.argb4444;
	526	t->texel[13] = vd->tmushare.int8;
586	527	t->texel[14] = t->palette;
587	528	t->texel[15] = nullptr;
588	529	t->lookup = t->texel[0];
589	530
590	531	/* attach the palette to NCC table 0 */
591	532	t->ncc[0].palette = t->palette;
592		if (v->type >= TYPE_VOODOO_2)
	533	if (vd->vd_type >= TYPE_VOODOO_2)
593	534	t->ncc[0].palettea = t->palettea;
594	535
595	536	/* set up texture address calculations */
596		if (v->type <= TYPE_VOODOO_2)
	537	if (vd->vd_type <= TYPE_VOODOO_2)
597	538	{
598	539	t->texaddr_mask = 0x0fffff;
599	540	t->texaddr_shift = 3;
r253153	r253154
606	547	}
607	548
608	549
609		~~static~~ void voodoo_postload(voodoo_~~stat~~e *v)
	550	void voodoo_device::voodoo_postload(voodoo_device *vd)
610	551	{
611	552	int index, subindex;
612	553
613		v->fbi.clut_dirty = TRUE;
614		for (index = 0; index < ARRAY_LENGTH(v->tmu); index++)
	554	vd->fbi.clut_dirty = TRUE;
	555	for (index = 0; index < ARRAY_LENGTH(vd->tmu); index++)
615	556	{
616		v->tmu[index].regdirty = TRUE;
617		for (subindex = 0; subindex < ARRAY_LENGTH(v->tmu[index].ncc); subindex++)
618		v->tmu[index].ncc[subindex].dirty = TRUE;
	557	vd->tmu[index].regdirty = TRUE;
	558	for (subindex = 0; subindex < ARRAY_LENGTH(vd->tmu[index].ncc); subindex++)
	559	vd->tmu[index].ncc[subindex].dirty = TRUE;
619	560	}
620	561
621	562	/* recompute video memory to get the FBI FIFO base recomputed */
622		if (v->type <= TYPE_VOODOO_2)
623		recompute_video_memory(v);
	563	if (vd->vd_type <= TYPE_VOODOO_2)
	564	recompute_video_memory(vd);
624	565	}
625	566
626	567
627		static void init_save_state(device_t *dev~~ice~~)
	568	static void init_save_state(voodoo_device *vd)
628	569	{
629		voodoo_state *v = get_safe_token(device);
630	570	int index, subindex;
631	571
632		dev~~ice~~->machine().save().register_postload(save_prepost_delegate(FUNC(voodoo_postload), v));
	572	vd->machine().save().register_postload(save_prepost_delegate(FUNC(voodoo_device::voodoo_postload), vd));
633	573
634	574	/* register states: core */
635		device->save_item(NAME(v->extra_cycles));
636		device->save_pointer(NAME(&v->reg[0].u), ARRAY_LENGTH(v->reg));
637		device->save_item(NAME(v->alt_regmap));
	575	vd->save_item(NAME(vd->extra_cycles));
	576	vd->save_pointer(NAME(&vd->reg[0].u), ARRAY_LENGTH(vd->reg));
	577	vd->save_item(NAME(vd->alt_regmap));
638	578
639	579	/* register states: pci */
640		device->save_item(NAME(v->pci.fifo.in));
641		device->save_item(NAME(v->pci.fifo.out));
642		device->save_item(NAME(v->pci.init_enable));
643		device->save_item(NAME(v->pci.stall_state));
644		device->save_item(NAME(v->pci.op_pending));
645		device->save_item(NAME(v->pci.op_end_time));
646		device->save_item(NAME(v->pci.fifo_mem));
	580	vd->save_item(NAME(vd->pci.fifo.in));
	581	vd->save_item(NAME(vd->pci.fifo.out));
	582	vd->save_item(NAME(vd->pci.init_enable));
	583	vd->save_item(NAME(vd->pci.stall_state));
	584	vd->save_item(NAME(vd->pci.op_pending));
	585	vd->save_item(NAME(vd->pci.op_end_time));
	586	vd->save_item(NAME(vd->pci.fifo_mem));
647	587
648	588	/* register states: dac */
649		device->save_item(NAME(v->dac.reg));
650		device->save_item(NAME(v->dac.read_result));
	589	vd->save_item(NAME(vd->dac.reg));
	590	vd->save_item(NAME(vd->dac.read_result));
651	591
652	592	/* register states: fbi */
653		device->save_pointer(NAME(v->fbi.ram), v->fbi.mask + 1);
654		device->save_item(NAME(v->fbi.rgboffs));
655		device->save_item(NAME(v->fbi.auxoffs));
656		device->save_item(NAME(v->fbi.frontbuf));
657		device->save_item(NAME(v->fbi.backbuf));
658		device->save_item(NAME(v->fbi.swaps_pending));
659		device->save_item(NAME(v->fbi.video_changed));
660		device->save_item(NAME(v->fbi.yorigin));
661		device->save_item(NAME(v->fbi.lfb_base));
662		device->save_item(NAME(v->fbi.lfb_stride));
663		device->save_item(NAME(v->fbi.width));
664		device->save_item(NAME(v->fbi.height));
665		device->save_item(NAME(v->fbi.xoffs));
666		device->save_item(NAME(v->fbi.yoffs));
667		device->save_item(NAME(v->fbi.vsyncscan));
668		device->save_item(NAME(v->fbi.rowpixels));
669		device->save_item(NAME(v->fbi.vblank));
670		device->save_item(NAME(v->fbi.vblank_count));
671		device->save_item(NAME(v->fbi.vblank_swap_pending));
672		device->save_item(NAME(v->fbi.vblank_swap));
673		device->save_item(NAME(v->fbi.vblank_dont_swap));
674		device->save_item(NAME(v->fbi.cheating_allowed));
675		device->save_item(NAME(v->fbi.sign));
676		device->save_item(NAME(v->fbi.ax));
677		device->save_item(NAME(v->fbi.ay));
678		device->save_item(NAME(v->fbi.bx));
679		device->save_item(NAME(v->fbi.by));
680		device->save_item(NAME(v->fbi.cx));
681		device->save_item(NAME(v->fbi.cy));
682		device->save_item(NAME(v->fbi.startr));
683		device->save_item(NAME(v->fbi.startg));
684		device->save_item(NAME(v->fbi.startb));
685		device->save_item(NAME(v->fbi.starta));
686		device->save_item(NAME(v->fbi.startz));
687		device->save_item(NAME(v->fbi.startw));
688		device->save_item(NAME(v->fbi.drdx));
689		device->save_item(NAME(v->fbi.dgdx));
690		device->save_item(NAME(v->fbi.dbdx));
691		device->save_item(NAME(v->fbi.dadx));
692		device->save_item(NAME(v->fbi.dzdx));
693		device->save_item(NAME(v->fbi.dwdx));
694		device->save_item(NAME(v->fbi.drdy));
695		device->save_item(NAME(v->fbi.dgdy));
696		device->save_item(NAME(v->fbi.dbdy));
697		device->save_item(NAME(v->fbi.dady));
698		device->save_item(NAME(v->fbi.dzdy));
699		device->save_item(NAME(v->fbi.dwdy));
700		device->save_item(NAME(v->fbi.lfb_stats.pixels_in));
701		device->save_item(NAME(v->fbi.lfb_stats.pixels_out));
702		device->save_item(NAME(v->fbi.lfb_stats.chroma_fail));
703		device->save_item(NAME(v->fbi.lfb_stats.zfunc_fail));
704		device->save_item(NAME(v->fbi.lfb_stats.afunc_fail));
705		device->save_item(NAME(v->fbi.lfb_stats.clip_fail));
706		device->save_item(NAME(v->fbi.lfb_stats.stipple_count));
707		device->save_item(NAME(v->fbi.sverts));
708		for (index = 0; index < ARRAY_LENGTH(v->fbi.svert); index++)
	593	vd->save_pointer(NAME(vd->fbi.ram), vd->fbi.mask + 1);
	594	vd->save_item(NAME(vd->fbi.rgboffs));
	595	vd->save_item(NAME(vd->fbi.auxoffs));
	596	vd->save_item(NAME(vd->fbi.frontbuf));
	597	vd->save_item(NAME(vd->fbi.backbuf));
	598	vd->save_item(NAME(vd->fbi.swaps_pending));
	599	vd->save_item(NAME(vd->fbi.video_changed));
	600	vd->save_item(NAME(vd->fbi.yorigin));
	601	vd->save_item(NAME(vd->fbi.lfb_base));
	602	vd->save_item(NAME(vd->fbi.lfb_stride));
	603	vd->save_item(NAME(vd->fbi.width));
	604	vd->save_item(NAME(vd->fbi.height));
	605	vd->save_item(NAME(vd->fbi.xoffs));
	606	vd->save_item(NAME(vd->fbi.yoffs));
	607	vd->save_item(NAME(vd->fbi.vsyncscan));
	608	vd->save_item(NAME(vd->fbi.rowpixels));
	609	vd->save_item(NAME(vd->fbi.vblank));
	610	vd->save_item(NAME(vd->fbi.vblank_count));
	611	vd->save_item(NAME(vd->fbi.vblank_swap_pending));
	612	vd->save_item(NAME(vd->fbi.vblank_swap));
	613	vd->save_item(NAME(vd->fbi.vblank_dont_swap));
	614	vd->save_item(NAME(vd->fbi.cheating_allowed));
	615	vd->save_item(NAME(vd->fbi.sign));
	616	vd->save_item(NAME(vd->fbi.ax));
	617	vd->save_item(NAME(vd->fbi.ay));
	618	vd->save_item(NAME(vd->fbi.bx));
	619	vd->save_item(NAME(vd->fbi.by));
	620	vd->save_item(NAME(vd->fbi.cx));
	621	vd->save_item(NAME(vd->fbi.cy));
	622	vd->save_item(NAME(vd->fbi.startr));
	623	vd->save_item(NAME(vd->fbi.startg));
	624	vd->save_item(NAME(vd->fbi.startb));
	625	vd->save_item(NAME(vd->fbi.starta));
	626	vd->save_item(NAME(vd->fbi.startz));
	627	vd->save_item(NAME(vd->fbi.startw));
	628	vd->save_item(NAME(vd->fbi.drdx));
	629	vd->save_item(NAME(vd->fbi.dgdx));
	630	vd->save_item(NAME(vd->fbi.dbdx));
	631	vd->save_item(NAME(vd->fbi.dadx));
	632	vd->save_item(NAME(vd->fbi.dzdx));
	633	vd->save_item(NAME(vd->fbi.dwdx));
	634	vd->save_item(NAME(vd->fbi.drdy));
	635	vd->save_item(NAME(vd->fbi.dgdy));
	636	vd->save_item(NAME(vd->fbi.dbdy));
	637	vd->save_item(NAME(vd->fbi.dady));
	638	vd->save_item(NAME(vd->fbi.dzdy));
	639	vd->save_item(NAME(vd->fbi.dwdy));
	640	vd->save_item(NAME(vd->fbi.lfb_stats.pixels_in));
	641	vd->save_item(NAME(vd->fbi.lfb_stats.pixels_out));
	642	vd->save_item(NAME(vd->fbi.lfb_stats.chroma_fail));
	643	vd->save_item(NAME(vd->fbi.lfb_stats.zfunc_fail));
	644	vd->save_item(NAME(vd->fbi.lfb_stats.afunc_fail));
	645	vd->save_item(NAME(vd->fbi.lfb_stats.clip_fail));
	646	vd->save_item(NAME(vd->fbi.lfb_stats.stipple_count));
	647	vd->save_item(NAME(vd->fbi.sverts));
	648	for (index = 0; index < ARRAY_LENGTH(vd->fbi.svert); index++)
709	649	{
710		device->save_item(NAME(v->fbi.svert[index].x), index);
711		device->save_item(NAME(v->fbi.svert[index].y), index);
712		device->save_item(NAME(v->fbi.svert[index].a), index);
713		device->save_item(NAME(v->fbi.svert[index].r), index);
714		device->save_item(NAME(v->fbi.svert[index].g), index);
715		device->save_item(NAME(v->fbi.svert[index].b), index);
716		device->save_item(NAME(v->fbi.svert[index].z), index);
717		device->save_item(NAME(v->fbi.svert[index].wb), index);
718		device->save_item(NAME(v->fbi.svert[index].w0), index);
719		device->save_item(NAME(v->fbi.svert[index].s0), index);
720		device->save_item(NAME(v->fbi.svert[index].t0), index);
721		device->save_item(NAME(v->fbi.svert[index].w1), index);
722		device->save_item(NAME(v->fbi.svert[index].s1), index);
723		device->save_item(NAME(v->fbi.svert[index].t1), index);
	650	vd->save_item(NAME(vd->fbi.svert[index].x), index);
	651	vd->save_item(NAME(vd->fbi.svert[index].y), index);
	652	vd->save_item(NAME(vd->fbi.svert[index].a), index);
	653	vd->save_item(NAME(vd->fbi.svert[index].r), index);
	654	vd->save_item(NAME(vd->fbi.svert[index].g), index);
	655	vd->save_item(NAME(vd->fbi.svert[index].b), index);
	656	vd->save_item(NAME(vd->fbi.svert[index].z), index);
	657	vd->save_item(NAME(vd->fbi.svert[index].wb), index);
	658	vd->save_item(NAME(vd->fbi.svert[index].w0), index);
	659	vd->save_item(NAME(vd->fbi.svert[index].s0), index);
	660	vd->save_item(NAME(vd->fbi.svert[index].t0), index);
	661	vd->save_item(NAME(vd->fbi.svert[index].w1), index);
	662	vd->save_item(NAME(vd->fbi.svert[index].s1), index);
	663	vd->save_item(NAME(vd->fbi.svert[index].t1), index);
724	664	}
725		device->save_item(NAME(v->fbi.fifo.size));
726		device->save_item(NAME(v->fbi.fifo.in));
727		device->save_item(NAME(v->fbi.fifo.out));
728		for (index = 0; index < ARRAY_LENGTH(v->fbi.cmdfifo); index++)
	665	vd->save_item(NAME(vd->fbi.fifo.size));
	666	vd->save_item(NAME(vd->fbi.fifo.in));
	667	vd->save_item(NAME(vd->fbi.fifo.out));
	668	for (index = 0; index < ARRAY_LENGTH(vd->fbi.cmdfifo); index++)
729	669	{
730		device->save_item(NAME(v->fbi.cmdfifo[index].enable), index);
731		device->save_item(NAME(v->fbi.cmdfifo[index].count_holes), index);
732		device->save_item(NAME(v->fbi.cmdfifo[index].base), index);
733		device->save_item(NAME(v->fbi.cmdfifo[index].end), index);
734		device->save_item(NAME(v->fbi.cmdfifo[index].rdptr), index);
735		device->save_item(NAME(v->fbi.cmdfifo[index].amin), index);
736		device->save_item(NAME(v->fbi.cmdfifo[index].amax), index);
737		device->save_item(NAME(v->fbi.cmdfifo[index].depth), index);
738		device->save_item(NAME(v->fbi.cmdfifo[index].holes), index);
	670	vd->save_item(NAME(vd->fbi.cmdfifo[index].enable), index);
	671	vd->save_item(NAME(vd->fbi.cmdfifo[index].count_holes), index);
	672	vd->save_item(NAME(vd->fbi.cmdfifo[index].base), index);
	673	vd->save_item(NAME(vd->fbi.cmdfifo[index].end), index);
	674	vd->save_item(NAME(vd->fbi.cmdfifo[index].rdptr), index);
	675	vd->save_item(NAME(vd->fbi.cmdfifo[index].amin), index);
	676	vd->save_item(NAME(vd->fbi.cmdfifo[index].amax), index);
	677	vd->save_item(NAME(vd->fbi.cmdfifo[index].depth), index);
	678	vd->save_item(NAME(vd->fbi.cmdfifo[index].holes), index);
739	679	}
740		device->save_item(NAME(v->fbi.fogblend));
741		device->save_item(NAME(v->fbi.fogdelta));
742		device->save_item(NAME(v->fbi.clut));
	680	vd->save_item(NAME(vd->fbi.fogblend));
	681	vd->save_item(NAME(vd->fbi.fogdelta));
	682	vd->save_item(NAME(vd->fbi.clut));
743	683
744	684	/* register states: tmu */
745		for (index = 0; index < ARRAY_LENGTH(v->tmu); index++)
	685	for (index = 0; index < ARRAY_LENGTH(vd->tmu); index++)
746	686	{
747		tmu_state *tmu = &v->tmu[index];
	687	tmu_state *tmu = &vd->tmu[index];
748	688	if (tmu->ram == nullptr)
749	689	continue;
750		if (tmu->ram != v->fbi.ram)
751		device->save_pointer(NAME(tmu->ram), tmu->mask + 1, index);
752		device->save_item(NAME(tmu->starts), index);
753		device->save_item(NAME(tmu->startt), index);
754		device->save_item(NAME(tmu->startw), index);
755		device->save_item(NAME(tmu->dsdx), index);
756		device->save_item(NAME(tmu->dtdx), index);
757		device->save_item(NAME(tmu->dwdx), index);
758		device->save_item(NAME(tmu->dsdy), index);
759		device->save_item(NAME(tmu->dtdy), index);
760		device->save_item(NAME(tmu->dwdy), index);
	690	if (tmu->ram != vd->fbi.ram)
	691	vd->save_pointer(NAME(tmu->ram), tmu->mask + 1, index);
	692	vd->save_item(NAME(tmu->starts), index);
	693	vd->save_item(NAME(tmu->startt), index);
	694	vd->save_item(NAME(tmu->startw), index);
	695	vd->save_item(NAME(tmu->dsdx), index);
	696	vd->save_item(NAME(tmu->dtdx), index);
	697	vd->save_item(NAME(tmu->dwdx), index);
	698	vd->save_item(NAME(tmu->dsdy), index);
	699	vd->save_item(NAME(tmu->dtdy), index);
	700	vd->save_item(NAME(tmu->dwdy), index);
761	701	for (subindex = 0; subindex < ARRAY_LENGTH(tmu->ncc); subindex++)
762	702	{
763		device->save_item(NAME(tmu->ncc[subindex].ir), index * ARRAY_LENGTH(tmu->ncc) + subindex);
764		device->save_item(NAME(tmu->ncc[subindex].ig), index * ARRAY_LENGTH(tmu->ncc) + subindex);
765		device->save_item(NAME(tmu->ncc[subindex].ib), index * ARRAY_LENGTH(tmu->ncc) + subindex);
766		device->save_item(NAME(tmu->ncc[subindex].qr), index * ARRAY_LENGTH(tmu->ncc) + subindex);
767		device->save_item(NAME(tmu->ncc[subindex].qg), index * ARRAY_LENGTH(tmu->ncc) + subindex);
768		device->save_item(NAME(tmu->ncc[subindex].qb), index * ARRAY_LENGTH(tmu->ncc) + subindex);
769		device->save_item(NAME(tmu->ncc[subindex].y), index * ARRAY_LENGTH(tmu->ncc) + subindex);
	703	vd->save_item(NAME(tmu->ncc[subindex].ir), index * ARRAY_LENGTH(tmu->ncc) + subindex);
	704	vd->save_item(NAME(tmu->ncc[subindex].ig), index * ARRAY_LENGTH(tmu->ncc) + subindex);
	705	vd->save_item(NAME(tmu->ncc[subindex].ib), index * ARRAY_LENGTH(tmu->ncc) + subindex);
	706	vd->save_item(NAME(tmu->ncc[subindex].qr), index * ARRAY_LENGTH(tmu->ncc) + subindex);
	707	vd->save_item(NAME(tmu->ncc[subindex].qg), index * ARRAY_LENGTH(tmu->ncc) + subindex);
	708	vd->save_item(NAME(tmu->ncc[subindex].qb), index * ARRAY_LENGTH(tmu->ncc) + subindex);
	709	vd->save_item(NAME(tmu->ncc[subindex].y), index * ARRAY_LENGTH(tmu->ncc) + subindex);
770	710	}
771	711	}
772	712
773	713	/* register states: banshee */
774		if (v->type >= TYPE_VOODOO_BANSHEE)
	714	if (vd->vd_type >= TYPE_VOODOO_BANSHEE)
775	715	{
776		device->save_item(NAME(v->banshee.io));
777		device->save_item(NAME(v->banshee.agp));
778		device->save_item(NAME(v->banshee.vga));
779		device->save_item(NAME(v->banshee.crtc));
780		device->save_item(NAME(v->banshee.seq));
781		device->save_item(NAME(v->banshee.gc));
782		device->save_item(NAME(v->banshee.att));
783		device->save_item(NAME(v->banshee.attff));
	716	vd->save_item(NAME(vd->banshee.io));
	717	vd->save_item(NAME(vd->banshee.agp));
	718	vd->save_item(NAME(vd->banshee.vga));
	719	vd->save_item(NAME(vd->banshee.crtc));
	720	vd->save_item(NAME(vd->banshee.seq));
	721	vd->save_item(NAME(vd->banshee.gc));
	722	vd->save_item(NAME(vd->banshee.att));
	723	vd->save_item(NAME(vd->banshee.attff));
784	724	}
785	725	}
786	726
r253153	r253154
792	732	*
793	733	*************************************/
794	734
795		static void accumulate_statistics(voodoo_~~stat~~e v, const stats_block stats)
	735	static void accumulate_statistics(voodoo_device vd, const stats_block stats)
796	736	{
797	737	/* apply internal voodoo statistics */
798		v->reg[fbiPixelsIn].u += stats->pixels_in;
799		v->reg[fbiPixelsOut].u += stats->pixels_out;
800		v->reg[fbiChromaFail].u += stats->chroma_fail;
801		v->reg[fbiZfuncFail].u += stats->zfunc_fail;
802		v->reg[fbiAfuncFail].u += stats->afunc_fail;
	738	vd->reg[fbiPixelsIn].u += stats->pixels_in;
	739	vd->reg[fbiPixelsOut].u += stats->pixels_out;
	740	vd->reg[fbiChromaFail].u += stats->chroma_fail;
	741	vd->reg[fbiZfuncFail].u += stats->zfunc_fail;
	742	vd->reg[fbiAfuncFail].u += stats->afunc_fail;
803	743
804	744	/* apply emulation statistics */
805		v->stats.total_pixels_in += stats->pixels_in;
806		v->stats.total_pixels_out += stats->pixels_out;
807		v->stats.total_chroma_fail += stats->chroma_fail;
808		v->stats.total_zfunc_fail += stats->zfunc_fail;
809		v->stats.total_afunc_fail += stats->afunc_fail;
810		v->stats.total_clipped += stats->clip_fail;
811		v->stats.total_stippled += stats->stipple_count;
	745	vd->stats.total_pixels_in += stats->pixels_in;
	746	vd->stats.total_pixels_out += stats->pixels_out;
	747	vd->stats.total_chroma_fail += stats->chroma_fail;
	748	vd->stats.total_zfunc_fail += stats->zfunc_fail;
	749	vd->stats.total_afunc_fail += stats->afunc_fail;
	750	vd->stats.total_clipped += stats->clip_fail;
	751	vd->stats.total_stippled += stats->stipple_count;
812	752	}
813	753
814	754
815		static void update_statistics(voodoo_~~stat~~e *v, int accumulate)
	755	static void update_statistics(voodoo_device *vd, int accumulate)
816	756	{
817	757	int threadnum;
818	758
r253153	r253154
820	760	for (threadnum = 0; threadnum < WORK_MAX_THREADS; threadnum++)
821	761	{
822	762	if (accumulate)
823		accumulate_statistics(v, &v->thread_stats[threadnum]);
824		memset(&v->thread_stats[threadnum], 0, sizeof(v->thread_stats[threadnum]));
	763	accumulate_statistics(vd, &vd->thread_stats[threadnum]);
	764	memset(&vd->thread_stats[threadnum], 0, sizeof(vd->thread_stats[threadnum]));
825	765	}
826	766
827	767	/* accumulate/reset statistics from the LFB */
828	768	if (accumulate)
829		accumulate_statistics(v, &v->fbi.lfb_stats);
830		memset(&v->fbi.lfb_stats, 0, sizeof(v->fbi.lfb_stats));
	769	accumulate_statistics(vd, &vd->fbi.lfb_stats);
	770	memset(&vd->fbi.lfb_stats, 0, sizeof(vd->fbi.lfb_stats));
831	771	}
832	772
833	773
r253153	r253154
838	778	*
839	779	*************************************/
840	780
841		~~static~~ void swap_buffers(voodoo_~~stat~~e *v)
	781	void voodoo_device::swap_buffers(voodoo_device *vd)
842	782	{
843	783	int count;
844	784
845		if (LOG_VBLANK_SWAP) v->device->logerror("--- swap_buffers @ %d\n", v->screen->vpos());
	785	if (LOG_VBLANK_SWAP) vd->device->logerror("--- swap_buffers @ %d\n", vd->screen->vpos());
846	786
847	787	/* force a partial update */
848		v->screen->update_partial(v->screen->vpos());
849		v->fbi.video_changed = TRUE;
	788	vd->screen->update_partial(vd->screen->vpos());
	789	vd->fbi.video_changed = TRUE;
850	790
851	791	/* keep a history of swap intervals */
852		count = v->fbi.vblank_count;
	792	count = vd->fbi.vblank_count;
853	793	if (count > 15)
854	794	count = 15;
855		v->reg[fbiSwapHistory].u = (v->reg[fbiSwapHistory].u << 4) \| count;
	795	vd->reg[fbiSwapHistory].u = (vd->reg[fbiSwapHistory].u << 4) \| count;
856	796
857	797	/* rotate the buffers */
858		if (v->type <= TYPE_VOODOO_2)
	798	if (vd->vd_type <= TYPE_VOODOO_2)
859	799	{
860		if (v->type < TYPE_VOODOO_2 \|\| !v->fbi.vblank_dont_swap)
	800	if (vd->vd_type < TYPE_VOODOO_2 \|\| !vd->fbi.vblank_dont_swap)
861	801	{
862		if (v->fbi.rgboffs[2] == ~0)
	802	if (vd->fbi.rgboffs[2] == ~0)
863	803	{
864		v->fbi.frontbuf = 1 - v->fbi.frontbuf;
865		v->fbi.backbuf = 1 - v->fbi.frontbuf;
	804	vd->fbi.frontbuf = 1 - vd->fbi.frontbuf;
	805	vd->fbi.backbuf = 1 - vd->fbi.frontbuf;
866	806	}
867	807	else
868	808	{
869		v->fbi.frontbuf = (v->fbi.frontbuf + 1) % 3;
870		v->fbi.backbuf = (v->fbi.frontbuf + 1) % 3;
	809	vd->fbi.frontbuf = (vd->fbi.frontbuf + 1) % 3;
	810	vd->fbi.backbuf = (vd->fbi.frontbuf + 1) % 3;
871	811	}
872	812	}
873	813	}
874	814	else
875		v->fbi.rgboffs[0] = v->reg[leftOverlayBuf].u & v->fbi.mask & ~0x0f;
	815	vd->fbi.rgboffs[0] = vd->reg[leftOverlayBuf].u & vd->fbi.mask & ~0x0f;
876	816
877	817	/* decrement the pending count and reset our state */
878		if (v->fbi.swaps_pending)
879		v->fbi.swaps_pending--;
880		v->fbi.vblank_count = 0;
881		v->fbi.vblank_swap_pending = FALSE;
	818	if (vd->fbi.swaps_pending)
	819	vd->fbi.swaps_pending--;
	820	vd->fbi.vblank_count = 0;
	821	vd->fbi.vblank_swap_pending = FALSE;
882	822
883	823	/* reset the last_op_time to now and start processing the next command */
884		if (v->pci.op_pending)
	824	if (vd->pci.op_pending)
885	825	{
886		v->pci.op_end_time = v->device->machine().time();
887		flush_fifos(v, v->pci.op_end_time);
	826	vd->pci.op_end_time = vd->device->machine().time();
	827	flush_fifos(vd, vd->pci.op_end_time);
888	828	}
889	829
890	830	/* we may be able to unstall now */
891		if (v->pci.stall_state != NOT_STALLED)
892		check_stalled_cpu(v, v->device->machine().time());
	831	if (vd->pci.stall_state != NOT_STALLED)
	832	check_stalled_cpu(vd, vd->device->machine().time());
893	833
894	834	/* periodically log rasterizer info */
895		v->stats.swaps++;
896		if (LOG_RASTERIZERS && v->stats.swaps % 1000 == 0)
897		dump_rasterizer_stats(v);
	835	vd->stats.swaps++;
	836	if (LOG_RASTERIZERS && vd->stats.swaps % 1000 == 0)
	837	dump_rasterizer_stats(vd);
898	838
899	839	/* update the statistics (debug) */
900		if (v->stats.display)
	840	if (vd->stats.display)
901	841	{
902		const rectangle &visible_area = v->screen->visible_area();
	842	const rectangle &visible_area = vd->screen->visible_area();
903	843	int screen_area = visible_area.width() * visible_area.height();
904		char *statsptr = v->stats.buffer;
	844	char *statsptr = vd->stats.buffer;
905	845	int pixelcount;
906	846	int i;
907	847
908		update_statistics(v, TRUE);
909		pixelcount = v->stats.total_pixels_out;
	848	update_statistics(vd, TRUE);
	849	pixelcount = vd->stats.total_pixels_out;
910	850
911		statsptr += sprintf(statsptr, "Swap:%6d\n", v->stats.swaps);
912		statsptr += sprintf(statsptr, "Hist:%08X\n", v->reg[fbiSwapHistory].u);
913		statsptr += sprintf(statsptr, "Stal:%6d\n", v->stats.stalls);
	851	statsptr += sprintf(statsptr, "Swap:%6d\n", vd->stats.swaps);
	852	statsptr += sprintf(statsptr, "Hist:%08X\n", vd->reg[fbiSwapHistory].u);
	853	statsptr += sprintf(statsptr, "Stal:%6d\n", vd->stats.stalls);
914	854	statsptr += sprintf(statsptr, "Rend:%6d%%\n", pixelcount * 100 / screen_area);
915		statsptr += sprintf(statsptr, "Poly:%6d\n", v->stats.total_triangles);
916		statsptr += sprintf(statsptr, "PxIn:%6d\n", v->stats.total_pixels_in);
917		statsptr += sprintf(statsptr, "POut:%6d\n", v->stats.total_pixels_out);
918		statsptr += sprintf(statsptr, "Clip:%6d\n", v->stats.total_clipped);
919		statsptr += sprintf(statsptr, "Stip:%6d\n", v->stats.total_stippled);
920		statsptr += sprintf(statsptr, "Chro:%6d\n", v->stats.total_chroma_fail);
921		statsptr += sprintf(statsptr, "ZFun:%6d\n", v->stats.total_zfunc_fail);
922		statsptr += sprintf(statsptr, "AFun:%6d\n", v->stats.total_afunc_fail);
923		statsptr += sprintf(statsptr, "RegW:%6d\n", v->stats.reg_writes);
924		statsptr += sprintf(statsptr, "RegR:%6d\n", v->stats.reg_reads);
925		statsptr += sprintf(statsptr, "LFBW:%6d\n", v->stats.lfb_writes);
926		statsptr += sprintf(statsptr, "LFBR:%6d\n", v->stats.lfb_reads);
927		statsptr += sprintf(statsptr, "TexW:%6d\n", v->stats.tex_writes);
	855	statsptr += sprintf(statsptr, "Poly:%6d\n", vd->stats.total_triangles);
	856	statsptr += sprintf(statsptr, "PxIn:%6d\n", vd->stats.total_pixels_in);
	857	statsptr += sprintf(statsptr, "POut:%6d\n", vd->stats.total_pixels_out);
	858	statsptr += sprintf(statsptr, "Clip:%6d\n", vd->stats.total_clipped);
	859	statsptr += sprintf(statsptr, "Stip:%6d\n", vd->stats.total_stippled);
	860	statsptr += sprintf(statsptr, "Chro:%6d\n", vd->stats.total_chroma_fail);
	861	statsptr += sprintf(statsptr, "ZFun:%6d\n", vd->stats.total_zfunc_fail);
	862	statsptr += sprintf(statsptr, "AFun:%6d\n", vd->stats.total_afunc_fail);
	863	statsptr += sprintf(statsptr, "RegW:%6d\n", vd->stats.reg_writes);
	864	statsptr += sprintf(statsptr, "RegR:%6d\n", vd->stats.reg_reads);
	865	statsptr += sprintf(statsptr, "LFBW:%6d\n", vd->stats.lfb_writes);
	866	statsptr += sprintf(statsptr, "LFBR:%6d\n", vd->stats.lfb_reads);
	867	statsptr += sprintf(statsptr, "TexW:%6d\n", vd->stats.tex_writes);
928	868	statsptr += sprintf(statsptr, "TexM:");
929	869	for (i = 0; i < 16; i++)
930		if (v->stats.texture_mode[i])
	870	if (vd->stats.texture_mode[i])
931	871	*statsptr++ = "0123456789ABCDEF"[i];
932	872	*statsptr = 0;
933	873	}
934	874
935	875	/* update statistics */
936		v->stats.stalls = 0;
937		v->stats.total_triangles = 0;
938		v->stats.total_pixels_in = 0;
939		v->stats.total_pixels_out = 0;
940		v->stats.total_chroma_fail = 0;
941		v->stats.total_zfunc_fail = 0;
942		v->stats.total_afunc_fail = 0;
943		v->stats.total_clipped = 0;
944		v->stats.total_stippled = 0;
945		v->stats.reg_writes = 0;
946		v->stats.reg_reads = 0;
947		v->stats.lfb_writes = 0;
948		v->stats.lfb_reads = 0;
949		v->stats.tex_writes = 0;
950		memset(v->stats.texture_mode, 0, sizeof(v->stats.texture_mode));
	876	vd->stats.stalls = 0;
	877	vd->stats.total_triangles = 0;
	878	vd->stats.total_pixels_in = 0;
	879	vd->stats.total_pixels_out = 0;
	880	vd->stats.total_chroma_fail = 0;
	881	vd->stats.total_zfunc_fail = 0;
	882	vd->stats.total_afunc_fail = 0;
	883	vd->stats.total_clipped = 0;
	884	vd->stats.total_stippled = 0;
	885	vd->stats.reg_writes = 0;
	886	vd->stats.reg_reads = 0;
	887	vd->stats.lfb_writes = 0;
	888	vd->stats.lfb_reads = 0;
	889	vd->stats.tex_writes = 0;
	890	memset(vd->stats.texture_mode, 0, sizeof(vd->stats.texture_mode));
951	891	}
952	892
953	893
954		static void adjust_vblank_timer(voodoo_~~stat~~e *v)
	894	static void adjust_vblank_timer(voodoo_device *vd)
955	895	{
956		attotime vblank_period = v->screen->time_until_pos(v->fbi.vsyncscan);
	896	attotime vblank_period = vd->screen->time_until_pos(vd->fbi.vsyncscan);
957	897
958	898	/* if zero, adjust to next frame, otherwise we may get stuck in an infinite loop */
959	899	if (vblank_period == attotime::zero)
960		vblank_period = v->screen->frame_period();
961		v->fbi.vblank_timer->adjust(vblank_period);
	900	vblank_period = vd->screen->frame_period();
	901	vd->fbi.vblank_timer->adjust(vblank_period);
962	902	}
963	903
964	904
965		~~static~~ TIMER_CALLBACK( vblank_off_callback )
	905	TIMER_CALLBACK_MEMBER( voodoo_device::vblank_off_callback )
966	906	{
967		~~voodoo~~_~~state~~ v ~~= (v~~oo~~doo_st~~ate )~~ptr~~;
	907	if (LOG_VBLANK_SWAP) device->logerror("--- vblank end\n");
968	908
969		if (LOG_VBLANK_SWAP) v->device->logerror("--- vblank end\n");
970
971	909	/* set internal state and call the client */
972		~~v->~~fbi.vblank = FALSE;
	910	fbi.vblank = FALSE;
973	911
974	912	// TODO: Vblank IRQ enable is VOODOO3 only?
975		if (v->type >= TYPE_VOODOO_3)
	913	if (vd_type >= TYPE_VOODOO_3)
976	914	{
977		if (~~v->~~reg[intrCtrl].u & 0x8) // call IRQ handler if VSYNC interrupt (falling) is enabled
	915	if (reg[intrCtrl].u & 0x8) // call IRQ handler if VSYNC interrupt (falling) is enabled
978	916	{
979		~~v->~~reg[intrCtrl].u \|= 0x200; // VSYNC int (falling) active
	917	reg[intrCtrl].u \|= 0x200; // VSYNC int (falling) active
980	918
981		if (!v->device->m_vblank.isnull())
982		v->device->m_vblank(FALSE);
	919	if (!device->m_vblank.isnull())
	920	device->m_vblank(FALSE);
983	921
984	922	}
985	923	}
986	924	else
987	925	{
988		if (!v->device->m_vblank.isnull())
989		v->device->m_vblank(FALSE);
	926	if (!device->m_vblank.isnull())
	927	device->m_vblank(FALSE);
990	928	}
991	929
992	930	/* go to the end of the next frame */
993		adjust_vblank_timer(v);
	931	adjust_vblank_timer(this);
994	932	}
995	933
996	934
997		~~static~~ TIMER_CALLBACK( vblank_callback )
	935	TIMER_CALLBACK_MEMBER( voodoo_device::vblank_callback )
998	936	{
999		vo~~odoo_stat~~e v ~~= (voodoo_~~state )~~ptr~~;
	937	if (LOG_VBLANK_SWAP) device->logerror("--- vblank start\n");
1000	938
1001		if (LOG_VBLANK_SWAP) v->device->logerror("--- vblank start\n");
1002
1003	939	/* flush the pipes */
1004		if (~~v->~~pci.op_pending)
	940	if (pci.op_pending)
1005	941	{
1006		if (LOG_VBLANK_SWAP) v->device->logerror("---- vblank flush begin\n");
1007		flush_fifos(v, machine.time());
1008		if (LOG_VBLANK_SWAP) v->device->logerror("---- vblank flush end\n");
	942	if (LOG_VBLANK_SWAP) device->logerror("---- vblank flush begin\n");
	943	flush_fifos(this, machine().time());
	944	if (LOG_VBLANK_SWAP) device->logerror("---- vblank flush end\n");
1009	945	}
1010	946
1011	947	/* increment the count */
1012		v->fbi.vblank_count++;
1013		if (v->fbi.vblank_count > 250)
1014		v->fbi.vblank_count = 250;
1015		if (LOG_VBLANK_SWAP) v->device->logerror("---- vblank count = %d", v->fbi.vblank_count);
1016		if (v->fbi.vblank_swap_pending)
1017		if (LOG_VBLANK_SWAP) v->device->logerror(" (target=%d)", v->fbi.vblank_swap);
1018		if (LOG_VBLANK_SWAP) v->device->logerror("\n");
	948	fbi.vblank_count++;
	949	if (fbi.vblank_count > 250)
	950	fbi.vblank_count = 250;
	951	if (LOG_VBLANK_SWAP) device->logerror("---- vblank count = %d", fbi.vblank_count);
	952	if (fbi.vblank_swap_pending)
	953	if (LOG_VBLANK_SWAP) device->logerror(" (target=%d)", fbi.vblank_swap);
	954	if (LOG_VBLANK_SWAP) device->logerror("\n");
1019	955
1020	956	/* if we're past the swap count, do the swap */
1021		if (v->fbi.vblank_swap_pending && v->fbi.vblank_count >= v->fbi.vblank_swap)
1022		swap_buffers(v);
	957	if (fbi.vblank_swap_pending && fbi.vblank_count >= fbi.vblank_swap)
	958	swap_buffers(this);
1023	959
1024	960	/* set a timer for the next off state */
1025		machine.scheduler().timer_set(~~v->~~screen->time_until_pos(0), FUNC(vblank_off_callback), 0, v);
	961	machine().scheduler().timer_set(screen->time_until_pos(0), timer_expired_delegate(FUNC(voodoo_device::vblank_off_callback),this), 0, this);
1026	962
	963
	964
1027	965	/* set internal state and call the client */
1028		~~v->~~fbi.vblank = TRUE;
	966	fbi.vblank = TRUE;
1029	967
1030	968	// TODO: Vblank IRQ enable is VOODOO3 only?
1031		if (v->type >= TYPE_VOODOO_3)
	969	if (vd_type >= TYPE_VOODOO_3)
1032	970	{
1033		if (~~v->~~reg[intrCtrl].u & 0x4) // call IRQ handler if VSYNC interrupt (rising) is enabled
	971	if (reg[intrCtrl].u & 0x4) // call IRQ handler if VSYNC interrupt (rising) is enabled
1034	972	{
1035		~~v->~~reg[intrCtrl].u \|= 0x100; // VSYNC int (rising) active
	973	reg[intrCtrl].u \|= 0x100; // VSYNC int (rising) active
1036	974
1037		if (!v->device->m_vblank.isnull())
1038		v->device->m_vblank(TRUE);
	975	if (!device->m_vblank.isnull())
	976	device->m_vblank(TRUE);
1039	977	}
1040	978	}
1041	979	else
1042	980	{
1043		if (!v->device->m_vblank.isnull())
1044		v->device->m_vblank(TRUE);
	981	if (!device->m_vblank.isnull())
	982	device->m_vblank(TRUE);
1045	983	}
1046	984	}
1047	985
r253153	r253154
1053	991	*
1054	992	*************************************/
1055	993
1056		static void reset_counters(voodoo_~~stat~~e *v)
	994	static void reset_counters(voodoo_device *vd)
1057	995	{
1058		update_statistics(v, FALSE);
1059		v->reg[fbiPixelsIn].u = 0;
1060		v->reg[fbiChromaFail].u = 0;
1061		v->reg[fbiZfuncFail].u = 0;
1062		v->reg[fbiAfuncFail].u = 0;
1063		v->reg[fbiPixelsOut].u = 0;
	996	update_statistics(vd, FALSE);
	997	vd->reg[fbiPixelsIn].u = 0;
	998	vd->reg[fbiChromaFail].u = 0;
	999	vd->reg[fbiZfuncFail].u = 0;
	1000	vd->reg[fbiAfuncFail].u = 0;
	1001	vd->reg[fbiPixelsOut].u = 0;
1064	1002	}
1065	1003
1066	1004
1067		~~static~~ void soft_reset(voodoo_~~stat~~e *v)
	1005	void voodoo_device::soft_reset(voodoo_device *vd)
1068	1006	{
1069		reset_counters(v);
1070		v->reg[fbiTrianglesOut].u = 0;
1071		fifo_reset(&v->fbi.fifo);
1072		fifo_reset(&v->pci.fifo);
	1007	reset_counters(vd);
	1008	vd->reg[fbiTrianglesOut].u = 0;
	1009	fifo_reset(&vd->fbi.fifo);
	1010	fifo_reset(&vd->pci.fifo);
1073	1011	}
1074	1012
1075	1013
r253153	r253154
1080	1018	*
1081	1019	*************************************/
1082	1020
1083		~~static~~ void recompute_video_memory(voodoo_~~stat~~e *v)
	1021	void voodoo_device::recompute_video_memory(voodoo_device *vd)
1084	1022	{
1085		UINT32 buffer_pages = FBIINIT2_VIDEO_BUFFER_OFFSET(v->reg[fbiInit2].u);
1086		UINT32 fifo_start_page = FBIINIT4_MEMORY_FIFO_START_ROW(v->reg[fbiInit4].u);
1087		UINT32 fifo_last_page = FBIINIT4_MEMORY_FIFO_STOP_ROW(v->reg[fbiInit4].u);
	1023	UINT32 buffer_pages = FBIINIT2_VIDEO_BUFFER_OFFSET(vd->reg[fbiInit2].u);
	1024	UINT32 fifo_start_page = FBIINIT4_MEMORY_FIFO_START_ROW(vd->reg[fbiInit4].u);
	1025	UINT32 fifo_last_page = FBIINIT4_MEMORY_FIFO_STOP_ROW(vd->reg[fbiInit4].u);
1088	1026	UINT32 memory_config;
1089	1027	int buf;
1090	1028
1091	1029	/* memory config is determined differently between V1 and V2 */
1092		memory_config = FBIINIT2_ENABLE_TRIPLE_BUF(v->reg[fbiInit2].u);
1093		if (v->type == TYPE_VOODOO_2 && memory_config == 0)
1094		memory_config = FBIINIT5_BUFFER_ALLOCATION(v->reg[fbiInit5].u);
	1030	memory_config = FBIINIT2_ENABLE_TRIPLE_BUF(vd->reg[fbiInit2].u);
	1031	if (vd->vd_type == TYPE_VOODOO_2 && memory_config == 0)
	1032	memory_config = FBIINIT5_BUFFER_ALLOCATION(vd->reg[fbiInit5].u);
1095	1033
1096	1034	/* tiles are 64x16/32; x_tiles specifies how many half-tiles */
1097		v->fbi.tile_width = (v->type == TYPE_VOODOO_1) ? 64 : 32;
1098		v->fbi.tile_height = (v->type == TYPE_VOODOO_1) ? 16 : 32;
1099		v->fbi.x_tiles = FBIINIT1_X_VIDEO_TILES(v->reg[fbiInit1].u);
1100		if (v->type == TYPE_VOODOO_2)
	1035	vd->fbi.tile_width = (vd->vd_type == TYPE_VOODOO_1) ? 64 : 32;
	1036	vd->fbi.tile_height = (vd->vd_type == TYPE_VOODOO_1) ? 16 : 32;
	1037	vd->fbi.x_tiles = FBIINIT1_X_VIDEO_TILES(vd->reg[fbiInit1].u);
	1038	if (vd->vd_type == TYPE_VOODOO_2)
1101	1039	{
1102		v->fbi.x_tiles = (v->fbi.x_tiles << 1) \|
1103		(FBIINIT1_X_VIDEO_TILES_BIT5(v->reg[fbiInit1].u) << 5) \|
1104		(FBIINIT6_X_VIDEO_TILES_BIT0(v->reg[fbiInit6].u));
	1040	vd->fbi.x_tiles = (vd->fbi.x_tiles << 1) \|
	1041	(FBIINIT1_X_VIDEO_TILES_BIT5(vd->reg[fbiInit1].u) << 5) \|
	1042	(FBIINIT6_X_VIDEO_TILES_BIT0(vd->reg[fbiInit6].u));
1105	1043	}
1106		v->fbi.rowpixels = v->fbi.tile_width * v->fbi.x_tiles;
	1044	vd->fbi.rowpixels = vd->fbi.tile_width * vd->fbi.x_tiles;
1107	1045
1108		// logerror("VOODOO.%d.VIDMEM: buffer_pages=%X fifo=%X-%X tiles=%X rowpix=%d\n", v->index, buffer_pages, fifo_start_page, fifo_last_page, v->fbi.x_tiles, v->fbi.rowpixels);
	1046	// logerror("VOODOO.%d.VIDMEM: buffer_pages=%X fifo=%X-%X tiles=%X rowpix=%d\n", vd->index, buffer_pages, fifo_start_page, fifo_last_page, vd->fbi.x_tiles, vd->fbi.rowpixels);
1109	1047
1110	1048	/* first RGB buffer always starts at 0 */
1111		v->fbi.rgboffs[0] = 0;
	1049	vd->fbi.rgboffs[0] = 0;
1112	1050
1113	1051	/* second RGB buffer starts immediately afterwards */
1114		v->fbi.rgboffs[1] = buffer_pages * 0x1000;
	1052	vd->fbi.rgboffs[1] = buffer_pages * 0x1000;
1115	1053
1116	1054	/* remaining buffers are based on the config */
1117	1055	switch (memory_config)
1118	1056	{
1119	1057	case 3: /* reserved */
1120		v->device->logerror("VOODOO.%d.ERROR:Unexpected memory configuration in recompute_video_memory!\n", v->index);
	1058	vd->device->logerror("VOODOO.%d.ERROR:Unexpected memory configuration in recompute_video_memory!\n", vd->index);
1121	1059
1122	1060	case 0: /* 2 color buffers, 1 aux buffer */
1123		v->fbi.rgboffs[2] = ~0;
1124		v->fbi.auxoffs = 2 * buffer_pages * 0x1000;
	1061	vd->fbi.rgboffs[2] = ~0;
	1062	vd->fbi.auxoffs = 2 * buffer_pages * 0x1000;
1125	1063	break;
1126	1064
1127	1065	case 1: /* 3 color buffers, 0 aux buffers */
1128		v->fbi.rgboffs[2] = 2 * buffer_pages * 0x1000;
1129		v->fbi.auxoffs = ~0;
	1066	vd->fbi.rgboffs[2] = 2 * buffer_pages * 0x1000;
	1067	vd->fbi.auxoffs = ~0;
1130	1068	break;
1131	1069
1132	1070	case 2: /* 3 color buffers, 1 aux buffers */
1133		v->fbi.rgboffs[2] = 2 * buffer_pages * 0x1000;
1134		v->fbi.auxoffs = 3 * buffer_pages * 0x1000;
	1071	vd->fbi.rgboffs[2] = 2 * buffer_pages * 0x1000;
	1072	vd->fbi.auxoffs = 3 * buffer_pages * 0x1000;
1135	1073	break;
1136	1074	}
1137	1075
1138	1076	/* clamp the RGB buffers to video memory */
1139	1077	for (buf = 0; buf < 3; buf++)
1140		if (v->fbi.rgboffs[buf] != ~0 && v->fbi.rgboffs[buf] > v->fbi.mask)
1141		v->fbi.rgboffs[buf] = v->fbi.mask;
	1078	if (vd->fbi.rgboffs[buf] != ~0 && vd->fbi.rgboffs[buf] > vd->fbi.mask)
	1079	vd->fbi.rgboffs[buf] = vd->fbi.mask;
1142	1080
1143	1081	/* clamp the aux buffer to video memory */
1144		if (v->fbi.auxoffs != ~0 && v->fbi.auxoffs > v->fbi.mask)
1145		v->fbi.auxoffs = v->fbi.mask;
	1082	if (vd->fbi.auxoffs != ~0 && vd->fbi.auxoffs > vd->fbi.mask)
	1083	vd->fbi.auxoffs = vd->fbi.mask;
1146	1084
1147	1085	/* osd_printf_debug("rgb[0] = %08X rgb[1] = %08X rgb[2] = %08X aux = %08X\n",
1148		v->fbi.rgboffs[0], v->fbi.rgboffs[1], v->fbi.rgboffs[2], v->fbi.auxoffs);*/
	1086	vd->fbi.rgboffs[0], vd->fbi.rgboffs[1], vd->fbi.rgboffs[2], vd->fbi.auxoffs);*/
1149	1087
1150	1088	/* compute the memory FIFO location and size */
1151		if (fifo_last_page > v->fbi.mask / 0x1000)
1152		fifo_last_page = v->fbi.mask / 0x1000;
	1089	if (fifo_last_page > vd->fbi.mask / 0x1000)
	1090	fifo_last_page = vd->fbi.mask / 0x1000;
1153	1091
1154	1092	/* is it valid and enabled? */
1155		if (fifo_start_page <= fifo_last_page && FBIINIT0_ENABLE_MEMORY_FIFO(v->reg[fbiInit0].u))
	1093	if (fifo_start_page <= fifo_last_page && FBIINIT0_ENABLE_MEMORY_FIFO(vd->reg[fbiInit0].u))
1156	1094	{
1157		v->fbi.fifo.base = (UINT32 )(v->fbi.ram + fifo_start_page 0x1000);
1158		v->fbi.fifo.size = (fifo_last_page + 1 - fifo_start_page) * 0x1000 / 4;
1159		if (v->fbi.fifo.size > 65536*2)
1160		v->fbi.fifo.size = 65536*2;
	1095	vd->fbi.fifo.base = (UINT32 )(vd->fbi.ram + fifo_start_page 0x1000);
	1096	vd->fbi.fifo.size = (fifo_last_page + 1 - fifo_start_page) * 0x1000 / 4;
	1097	if (vd->fbi.fifo.size > 65536*2)
	1098	vd->fbi.fifo.size = 65536*2;
1161	1099	}
1162	1100
1163	1101	/* if not, disable the FIFO */
1164	1102	else
1165	1103	{
1166		v->fbi.fifo.base = nullptr;
1167		v->fbi.fifo.size = 0;
	1104	vd->fbi.fifo.base = nullptr;
	1105	vd->fbi.fifo.size = 0;
1168	1106	}
1169	1107
1170	1108	/* reset the FIFO */
1171		fifo_reset(&v->fbi.fifo);
	1109	fifo_reset(&vd->fbi.fifo);
1172	1110
1173	1111	/* reset our front/back buffers if they are out of range */
1174		if (v->fbi.rgboffs[2] == ~0)
	1112	if (vd->fbi.rgboffs[2] == ~0)
1175	1113	{
1176		if (v->fbi.frontbuf == 2)
1177		v->fbi.frontbuf = 0;
1178		if (v->fbi.backbuf == 2)
1179		v->fbi.backbuf = 0;
	1114	if (vd->fbi.frontbuf == 2)
	1115	vd->fbi.frontbuf = 0;
	1116	if (vd->fbi.backbuf == 2)
	1117	vd->fbi.backbuf = 0;
1180	1118	}
1181	1119	}
1182	1120
r253153	r253154
1476	1414	*
1477	1415	*************************************/
1478	1416
1479		static int cmdfifo_compute_expected_depth(voodoo_~~stat~~e v, cmdfifo_info f)
	1417	static int cmdfifo_compute_expected_depth(voodoo_device vd, cmdfifo_info f)
1480	1418	{
1481		UINT32 fifobase = (UINT32 )v->fbi.ram;
	1419	UINT32 fifobase = (UINT32 )vd->fbi.ram;
1482	1420	UINT32 readptr = f->rdptr;
1483	1421	UINT32 command = fifobase[readptr / 4];
1484	1422	int i, count = 0;
r253153	r253154
1616	1554	*
1617	1555	*************************************/
1618	1556
1619		~~static~~ UINT32 cmdfifo_execute(voodoo_~~stat~~e v, cmdfifo_info f)
	1557	UINT32 voodoo_device::cmdfifo_execute(voodoo_device vd, cmdfifo_info f)
1620	1558	{
1621		UINT32 fifobase = (UINT32 )v->fbi.ram;
	1559	UINT32 fifobase = (UINT32 )vd->fbi.ram;
1622	1560	UINT32 readptr = f->rdptr;
1623	1561	UINT32 *src = &fifobase[readptr / 4];
1624	1562	UINT32 command = *src++;
r253153	r253154
1649	1587	switch ((command >> 3) & 7)
1650	1588	{
1651	1589	case 0: /* NOP */
1652		if (LOG_CMDFIFO) v->device->logerror(" NOP\n");
	1590	if (LOG_CMDFIFO) vd->device->logerror(" NOP\n");
1653	1591	break;
1654	1592
1655	1593	case 1: /* JSR */
1656		if (LOG_CMDFIFO) v->device->logerror(" JSR $%06X\n", target);
	1594	if (LOG_CMDFIFO) vd->device->logerror(" JSR $%06X\n", target);
1657	1595	osd_printf_debug("JSR in CMDFIFO!\n");
1658	1596	src = &fifobase[target / 4];
1659	1597	break;
1660	1598
1661	1599	case 2: /* RET */
1662		if (LOG_CMDFIFO) v->device->logerror(" RET $%06X\n", target);
	1600	if (LOG_CMDFIFO) vd->device->logerror(" RET $%06X\n", target);
1663	1601	fatalerror("RET in CMDFIFO!\n");
1664	1602
1665	1603	case 3: /* JMP LOCAL FRAME BUFFER */
1666		if (LOG_CMDFIFO) v->device->logerror(" JMP LOCAL FRAMEBUF $%06X\n", target);
	1604	if (LOG_CMDFIFO) vd->device->logerror(" JMP LOCAL FRAMEBUF $%06X\n", target);
1667	1605	src = &fifobase[target / 4];
1668	1606	break;
1669	1607
1670	1608	case 4: /* JMP AGP */
1671		if (LOG_CMDFIFO) v->device->logerror(" JMP AGP $%06X\n", target);
	1609	if (LOG_CMDFIFO) vd->device->logerror(" JMP AGP $%06X\n", target);
1672	1610	fatalerror("JMP AGP in CMDFIFO!\n");
1673	1611	src = &fifobase[target / 4];
1674	1612	break;
r253153	r253154
1696	1634	inc = (command >> 15) & 1;
1697	1635	target = (command >> 3) & 0xfff;
1698	1636
1699		if (LOG_CMDFIFO) v->device->logerror(" PACKET TYPE 1: count=%d inc=%d reg=%04X\n", count, inc, target);
	1637	if (LOG_CMDFIFO) vd->device->logerror(" PACKET TYPE 1: count=%d inc=%d reg=%04X\n", count, inc, target);
1700	1638
1701		if (v->type >= TYPE_VOODOO_BANSHEE && (target & 0x800))
	1639	if (vd->vd_type >= TYPE_VOODOO_BANSHEE && (target & 0x800))
1702	1640	{
1703	1641	// Banshee/Voodoo3 2D register writes
1704	1642
1705	1643	/* loop over all registers and write them one at a time */
1706	1644	for (i = 0; i < count; i++, target += inc)
1707	1645	{
1708		cycles += banshee_2d_w(v, target & 0xff, *src);
	1646	cycles += banshee_2d_w(vd, target & 0xff, *src);
1709	1647	//logerror(" 2d reg: %03x = %08X\n", target & 0x7ff, *src);
1710	1648	src++;
1711	1649	}
r253153	r253154
1714	1652	{
1715	1653	/* loop over all registers and write them one at a time */
1716	1654	for (i = 0; i < count; i++, target += inc)
1717		cycles += register_w(v, target, *src++);
	1655	cycles += register_w(vd, target, *src++);
1718	1656	}
1719	1657	break;
1720	1658
r253153	r253154
1727	1665	1 31:0 = Data word
1728	1666	*/
1729	1667	case 2:
1730		if (LOG_CMDFIFO) v->device->logerror(" PACKET TYPE 2: mask=%X\n", (command >> 3) & 0x1ffffff);
	1668	if (LOG_CMDFIFO) vd->device->logerror(" PACKET TYPE 2: mask=%X\n", (command >> 3) & 0x1ffffff);
1731	1669
1732	1670	/* loop over all registers and write them one at a time */
1733	1671	for (i = 3; i <= 31; i++)
1734	1672	if (command & (1 << i))
1735		cycles += register_w(v, banshee2D_clip0Min + (i - 3), *src++);
	1673	cycles += register_w(vd, banshee2D_clip0Min + (i - 3), *src++);
1736	1674	break;
1737	1675
1738	1676	/*
r253153	r253154
1764	1702	count = (command >> 6) & 15;
1765	1703	code = (command >> 3) & 7;
1766	1704
1767		if (LOG_CMDFIFO) v->device->logerror(" PACKET TYPE 3: count=%d code=%d mask=%03X smode=%02X pc=%d\n", count, code, (command >> 10) & 0xfff, (command >> 22) & 0x3f, (command >> 28) & 1);
	1705	if (LOG_CMDFIFO) vd->device->logerror(" PACKET TYPE 3: count=%d code=%d mask=%03X smode=%02X pc=%d\n", count, code, (command >> 10) & 0xfff, (command >> 22) & 0x3f, (command >> 28) & 1);
1768	1706
1769	1707	/* copy relevant bits into the setup mode register */
1770		v->reg[sSetupMode].u = ((command >> 10) & 0xff) \| ((command >> 6) & 0xf0000);
	1708	vd->reg[sSetupMode].u = ((command >> 10) & 0xff) \| ((command >> 6) & 0xf0000);
1771	1709
1772	1710	/* loop over triangles */
1773	1711	for (i = 0; i < count; i++)
r253153	r253154
1834	1772	/* for a series of individual triangles, initialize all the verts */
1835	1773	if ((code == 1 && i == 0) \|\| (code == 0 && i % 3 == 0))
1836	1774	{
1837		v->fbi.sverts = 1;
1838		v->fbi.svert[0] = v->fbi.svert[1] = v->fbi.svert[2] = svert;
	1775	vd->fbi.sverts = 1;
	1776	vd->fbi.svert[0] = vd->fbi.svert[1] = vd->fbi.svert[2] = svert;
1839	1777	}
1840	1778
1841	1779	/* otherwise, add this to the list */
r253153	r253154
1843	1781	{
1844	1782	/* for strip mode, shuffle vertex 1 down to 0 */
1845	1783	if (!(command & (1 << 22)))
1846		v->fbi.svert[0] = v->fbi.svert[1];
	1784	vd->fbi.svert[0] = vd->fbi.svert[1];
1847	1785
1848	1786	/* copy 2 down to 1 and add our new one regardless */
1849		v->fbi.svert[1] = v->fbi.svert[2];
1850		v->fbi.svert[2] = svert;
	1787	vd->fbi.svert[1] = vd->fbi.svert[2];
	1788	vd->fbi.svert[2] = svert;
1851	1789
1852	1790	/* if we have enough, draw */
1853		if (++v->fbi.sverts >= 3)
1854		cycles += setup_and_draw_triangle(v);
	1791	if (++vd->fbi.sverts >= 3)
	1792	cycles += setup_and_draw_triangle(vd);
1855	1793	}
1856	1794	}
1857	1795
r253153	r253154
1874	1812	/* extract parameters */
1875	1813	target = (command >> 3) & 0xfff;
1876	1814
1877		if (LOG_CMDFIFO) v->device->logerror(" PACKET TYPE 4: mask=%X reg=%04X pad=%d\n", (command >> 15) & 0x3fff, target, command >> 29);
	1815	if (LOG_CMDFIFO) vd->device->logerror(" PACKET TYPE 4: mask=%X reg=%04X pad=%d\n", (command >> 15) & 0x3fff, target, command >> 29);
1878	1816
1879		if (v->type >= TYPE_VOODOO_BANSHEE && (target & 0x800))
	1817	if (vd->vd_type >= TYPE_VOODOO_BANSHEE && (target & 0x800))
1880	1818	{
1881	1819	// Banshee/Voodoo3 2D register writes
1882	1820
r253153	r253154
1886	1824	{
1887	1825	if (command & (1 << i))
1888	1826	{
1889		cycles += banshee_2d_w(v, target + (i - 15), *src);
	1827	cycles += banshee_2d_w(vd, target + (i - 15), *src);
1890	1828	//logerror(" 2d reg: %03x = %08X\n", target & 0x7ff, *src);
1891	1829	src++;
1892	1830	}
r253153	r253154
1897	1835	/* loop over all registers and write them one at a time */
1898	1836	for (i = 15; i <= 28; i++)
1899	1837	if (command & (1 << i))
1900		cycles += register_w(v, target + (i - 15), *src++);
	1838	cycles += register_w(vd, target + (i - 15), *src++);
1901	1839	}
1902	1840
1903	1841	/* account for the extra dummy words */
r253153	r253154
1928	1866	{
1929	1867	case 0: // Linear FB
1930	1868	{
1931		if (LOG_CMDFIFO) v->device->logerror(" PACKET TYPE 5: FB count=%d dest=%08X bd2=%X bdN=%X\n", count, target, (command >> 26) & 15, (command >> 22) & 15);
	1869	if (LOG_CMDFIFO) vd->device->logerror(" PACKET TYPE 5: FB count=%d dest=%08X bd2=%X bdN=%X\n", count, target, (command >> 26) & 15, (command >> 22) & 15);
1932	1870
1933	1871	UINT32 addr = target * 4;
1934	1872	for (i=0; i < count; i++)
1935	1873	{
1936	1874	UINT32 data = *src++;
1937	1875
1938		v->fbi.ram[BYTE_XOR_LE(addr + 0)] = (UINT8)(data);
1939		v->fbi.ram[BYTE_XOR_LE(addr + 1)] = (UINT8)(data >> 8);
1940		v->fbi.ram[BYTE_XOR_LE(addr + 2)] = (UINT8)(data >> 16);
1941		v->fbi.ram[BYTE_XOR_LE(addr + 3)] = (UINT8)(data >> 24);
	1876	vd->fbi.ram[BYTE_XOR_LE(addr + 0)] = (UINT8)(data);
	1877	vd->fbi.ram[BYTE_XOR_LE(addr + 1)] = (UINT8)(data >> 8);
	1878	vd->fbi.ram[BYTE_XOR_LE(addr + 2)] = (UINT8)(data >> 16);
	1879	vd->fbi.ram[BYTE_XOR_LE(addr + 3)] = (UINT8)(data >> 24);
1942	1880
1943	1881	addr += 4;
1944	1882	}
r253153	r253154
1946	1884	}
1947	1885	case 2: // 3D LFB
1948	1886	{
1949		if (LOG_CMDFIFO) v->device->logerror(" PACKET TYPE 5: 3D LFB count=%d dest=%08X bd2=%X bdN=%X\n", count, target, (command >> 26) & 15, (command >> 22) & 15);
	1887	if (LOG_CMDFIFO) vd->device->logerror(" PACKET TYPE 5: 3D LFB count=%d dest=%08X bd2=%X bdN=%X\n", count, target, (command >> 26) & 15, (command >> 22) & 15);
1950	1888
1951	1889	/* loop over words */
1952	1890	for (i = 0; i < count; i++)
1953		cycles += lfb_w(v, target++, *src++, 0xffffffff);
	1891	cycles += lfb_w(vd, target++, *src++, 0xffffffff);
1954	1892
1955	1893	break;
1956	1894	}
r253153	r253154
1971	1909
1972	1910	case 3: // Texture Port
1973	1911	{
1974		if (LOG_CMDFIFO) v->device->logerror(" PACKET TYPE 5: textureRAM count=%d dest=%08X bd2=%X bdN=%X\n", count, target, (command >> 26) & 15, (command >> 22) & 15);
	1912	if (LOG_CMDFIFO) vd->device->logerror(" PACKET TYPE 5: textureRAM count=%d dest=%08X bd2=%X bdN=%X\n", count, target, (command >> 26) & 15, (command >> 22) & 15);
1975	1913
1976	1914	/* loop over words */
1977	1915	for (i = 0; i < count; i++)
1978		cycles += texture_w(v, target++, *src++);
	1916	cycles += texture_w(vd, target++, *src++);
1979	1917
1980	1918	break;
1981	1919	}
r253153	r253154
2001	1939	*
2002	1940	*************************************/
2003	1941
2004		~~static~~ INT32 cmdfifo_execute_if_ready(voodoo_~~stat~~e v, cmdfifo_info f)
	1942	INT32 voodoo_device::cmdfifo_execute_if_ready(voodoo_device* vd, cmdfifo_info *f)
2005	1943	{
2006	1944	int needed_depth;
2007	1945	int cycles;
r253153	r253154
2011	1949	return -1;
2012	1950
2013	1951	/* see if we have enough for the current command */
2014		needed_depth = cmdfifo_compute_expected_depth(v, f);
	1952	needed_depth = cmdfifo_compute_expected_depth(vd, f);
2015	1953	if (f->depth < needed_depth)
2016	1954	return -1;
2017	1955
2018	1956	/* execute */
2019		cycles = cmdfifo_execute(v, f);
	1957	cycles = cmdfifo_execute(vd, f);
2020	1958	f->depth -= needed_depth;
2021	1959	return cycles;
2022	1960	}
r253153	r253154
2029	1967	*
2030	1968	*************************************/
2031	1969
2032		~~static~~ void cmdfifo_w(voodoo_~~stat~~e v, cmdfifo_info f, offs_t offset, UINT32 data)
	1970	void voodoo_device::cmdfifo_w(voodoo_device vd, cmdfifo_info f, offs_t offset, UINT32 data)
2033	1971	{
2034	1972	UINT32 addr = f->base + offset * 4;
2035		UINT32 fifobase = (UINT32 )v->fbi.ram;
	1973	UINT32 fifobase = (UINT32 )vd->fbi.ram;
2036	1974
2037		if (LOG_CMDFIFO_VERBOSE) v->device->logerror("CMDFIFO_w(%04X) = %08X\n", offset, data);
	1975	if (LOG_CMDFIFO_VERBOSE) vd->device->logerror("CMDFIFO_w(%04X) = %08X\n", offset, data);
2038	1976
2039	1977	/* write the data */
2040	1978	if (addr < f->end)
r253153	r253154
2054	1992	else if (addr < f->amin)
2055	1993	{
2056	1994	if (f->holes != 0)
2057		v->device->logerror("Unexpected CMDFIFO: AMin=%08X AMax=%08X Holes=%d WroteTo:%08X\n",
	1995	vd->device->logerror("Unexpected CMDFIFO: AMin=%08X AMax=%08X Holes=%d WroteTo:%08X\n",
2058	1996	f->amin, f->amax, f->holes, addr);
2059	1997	//f->amin = f->amax = addr;
2060	1998	f->holes += (addr - f->base) / 4;
r253153	r253154
2084	2022	}
2085	2023
2086	2024	/* execute if we can */
2087		if (!v->pci.op_pending)
	2025	if (!vd->pci.op_pending)
2088	2026	{
2089		INT32 cycles = cmdfifo_execute_if_ready(v, f);
	2027	INT32 cycles = cmdfifo_execute_if_ready(vd, f);
2090	2028	if (cycles > 0)
2091	2029	{
2092		v->pci.op_pending = TRUE;
2093		v->pci.op_end_time = v->device->machine().time() + attotime(0, (attoseconds_t)cycles * v->attoseconds_per_cycle);
	2030	vd->pci.op_pending = TRUE;
	2031	vd->pci.op_end_time = vd->device->machine().time() + attotime(0, (attoseconds_t)cycles * vd->attoseconds_per_cycle);
2094	2032
2095		if (LOG_FIFO_VERBOSE) v->device->logerror("VOODOO.%d.FIFO:direct write start at %d.%08X%08X end at %d.%08X%08X\n", v->index,
2096		v->device->machine().time().seconds(), (UINT32)(v->device->machine().time().attoseconds() >> 32), (UINT32)v->device->machine().time().attoseconds(),
2097		v->pci.op_end_time.seconds(), (UINT32)(v->pci.op_end_time.attoseconds() >> 32), (UINT32)v->pci.op_end_time.attoseconds());
	2033	if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:direct write start at %d.%08X%08X end at %d.%08X%08X\n", vd->index,
	2034	vd->device->machine().time().seconds(), (UINT32)(vd->device->machine().time().attoseconds() >> 32), (UINT32)vd->device->machine().time().attoseconds(),
	2035	vd->pci.op_end_time.seconds(), (UINT32)(vd->pci.op_end_time.attoseconds() >> 32), (UINT32)vd->pci.op_end_time.attoseconds());
2098	2036	}
2099	2037	}
2100	2038	}
r253153	r253154
2108	2046	*
2109	2047	*************************************/
2110	2048
2111		~~static~~ TIMER_CALLBACK( stall_cpu_callback )
	2049	TIMER_CALLBACK_MEMBER( voodoo_device::stall_cpu_callback )
2112	2050	{
2113		check_stalled_cpu(~~(voodoo_s~~t~~ate *)ptr~~, machine.time());
	2051	check_stalled_cpu(this, machine().time());
2114	2052	}
2115	2053
2116	2054
2117		~~static~~ void check_stalled_cpu(voodoo_~~stat~~e *v, attotime current_time)
	2055	void voodoo_device::check_stalled_cpu(voodoo_device* vd, attotime current_time)
2118	2056	{
2119	2057	int resume = FALSE;
2120	2058
2121	2059	/* flush anything we can */
2122		if (v->pci.op_pending)
2123		flush_fifos(v, current_time);
	2060	if (vd->pci.op_pending)
	2061	flush_fifos(vd, current_time);
2124	2062
2125	2063	/* if we're just stalled until the LWM is passed, see if we're ok now */
2126		if (v->pci.stall_state == STALLED_UNTIL_FIFO_LWM)
	2064	if (vd->pci.stall_state == STALLED_UNTIL_FIFO_LWM)
2127	2065	{
2128	2066	/* if there's room in the memory FIFO now, we can proceed */
2129		if (FBIINIT0_ENABLE_MEMORY_FIFO(v->reg[fbiInit0].u))
	2067	if (FBIINIT0_ENABLE_MEMORY_FIFO(vd->reg[fbiInit0].u))
2130	2068	{
2131		if (fifo_items(&v->fbi.fifo) < 2 * 32 * FBIINIT0_MEMORY_FIFO_HWM(v->reg[fbiInit0].u))
	2069	if (fifo_items(&vd->fbi.fifo) < 2 * 32 * FBIINIT0_MEMORY_FIFO_HWM(vd->reg[fbiInit0].u))
2132	2070	resume = TRUE;
2133	2071	}
2134		else if (fifo_space(&v->pci.fifo) > 2 * FBIINIT0_PCI_FIFO_LWM(v->reg[fbiInit0].u))
	2072	else if (fifo_space(&vd->pci.fifo) > 2 * FBIINIT0_PCI_FIFO_LWM(vd->reg[fbiInit0].u))
2135	2073	resume = TRUE;
2136	2074	}
2137	2075
2138	2076	/* if we're stalled until the FIFOs are empty, check now */
2139		else if (v->pci.stall_state == STALLED_UNTIL_FIFO_EMPTY)
	2077	else if (vd->pci.stall_state == STALLED_UNTIL_FIFO_EMPTY)
2140	2078	{
2141		if (FBIINIT0_ENABLE_MEMORY_FIFO(v->reg[fbiInit0].u))
	2079	if (FBIINIT0_ENABLE_MEMORY_FIFO(vd->reg[fbiInit0].u))
2142	2080	{
2143		if (fifo_empty(&v->fbi.fifo) && fifo_empty(&v->pci.fifo))
	2081	if (fifo_empty(&vd->fbi.fifo) && fifo_empty(&vd->pci.fifo))
2144	2082	resume = TRUE;
2145	2083	}
2146		else if (fifo_empty(&v->pci.fifo))
	2084	else if (fifo_empty(&vd->pci.fifo))
2147	2085	resume = TRUE;
2148	2086	}
2149	2087
2150	2088	/* resume if necessary */
2151		if (resume \|\| !v->pci.op_pending)
	2089	if (resume \|\| !vd->pci.op_pending)
2152	2090	{
2153		if (LOG_FIFO) v->device->logerror("VOODOO.%d.FIFO:Stall condition cleared; resuming\n", v->index);
2154		v->pci.stall_state = NOT_STALLED;
	2091	if (LOG_FIFO) vd->device->logerror("VOODOO.%d.FIFO:Stall condition cleared; resuming\n", vd->index);
	2092	vd->pci.stall_state = NOT_STALLED;
2155	2093
2156	2094	/* either call the callback, or trigger the trigger */
2157		if (!v->device->m_stall.isnull())
2158		v->device->m_stall(FALSE);
	2095	if (!vd->device->m_stall.isnull())
	2096	vd->device->m_stall(FALSE);
2159	2097	else
2160		v->device->machine().scheduler().trigger(v->trigger);
	2098	vd->device->machine().scheduler().trigger(vd->trigger);
2161	2099	}
2162	2100
2163	2101	/* if not, set a timer for the next one */
2164	2102	else
2165	2103	{
2166		v->pci.continue_timer->adjust(v->pci.op_end_time - current_time);
	2104	vd->pci.continue_timer->adjust(vd->pci.op_end_time - current_time);
2167	2105	}
2168	2106	}
2169	2107
2170	2108
2171		~~static~~ void stall_cpu(voodoo_~~stat~~e *v, int state, attotime current_time)
	2109	void voodoo_device::stall_cpu(voodoo_device *vd, int state, attotime current_time)
2172	2110	{
2173	2111	/* sanity check */
2174		if (!v->pci.op_pending) fatalerror("FIFOs not empty, no op pending!\n");
	2112	if (!vd->pci.op_pending) fatalerror("FIFOs not empty, no op pending!\n");
2175	2113
2176	2114	/* set the state and update statistics */
2177		v->pci.stall_state = state;
2178		v->stats.stalls++;
	2115	vd->pci.stall_state = state;
	2116	vd->stats.stalls++;
2179	2117
2180	2118	/* either call the callback, or spin the CPU */
2181		if (!v->device->m_stall.isnull())
2182		v->device->m_stall(TRUE);
	2119	if (!vd->device->m_stall.isnull())
	2120	vd->device->m_stall(TRUE);
2183	2121	else
2184		v->cpu->execute().spin_until_trigger(v->trigger);
	2122	vd->cpu->execute().spin_until_trigger(vd->trigger);
2185	2123
2186	2124	/* set a timer to clear the stall */
2187		v->pci.continue_timer->adjust(v->pci.op_end_time - current_time);
	2125	vd->pci.continue_timer->adjust(vd->pci.op_end_time - current_time);
2188	2126	}
2189	2127
2190	2128
r253153	r253154
2195	2133	*
2196	2134	*************************************/
2197	2135
2198		~~static~~ INT32 register_w(voodoo_~~stat~~e *v, offs_t offset, UINT32 data)
	2136	INT32 voodoo_device::register_w(voodoo_device *vd, offs_t offset, UINT32 data)
2199	2137	{
2200	2138	UINT32 origdata = data;
2201	2139	INT32 cycles = 0;
r253153	r253154
2204	2142	UINT8 chips;
2205	2143
2206	2144	/* statistics */
2207		v->stats.reg_writes++;
	2145	vd->stats.reg_writes++;
2208	2146
2209	2147	/* determine which chips we are addressing */
2210	2148	chips = (offset >> 8) & 0xf;
2211	2149	if (chips == 0)
2212	2150	chips = 0xf;
2213		chips &= v->chipmask;
	2151	chips &= vd->chipmask;
2214	2152
2215	2153	/* the first 64 registers can be aliased differently */
2216		if ((offset & 0x800c0) == 0x80000 && v->alt_regmap)
	2154	if ((offset & 0x800c0) == 0x80000 && vd->alt_regmap)
2217	2155	regnum = register_alias_map[offset & 0x3f];
2218	2156	else
2219	2157	regnum = offset & 0xff;
2220	2158
2221	2159	/* first make sure this register is readable */
2222		if (!(v->regaccess[regnum] & REGISTER_WRITE))
	2160	if (!(vd->regaccess[regnum] & REGISTER_WRITE))
2223	2161	{
2224		v->device->logerror("VOODOO.%d.ERROR:Invalid attempt to write %s\n", v->index, v->regnames[regnum]);
	2162	vd->device->logerror("VOODOO.%d.ERROR:Invalid attempt to write %s\n", vd->index, vd->regnames[regnum]);
2225	2163	return 0;
2226	2164	}
2227	2165
r253153	r253154
2232	2170	case fvertexAx:
2233	2171	data = float_to_int32(data, 4);
2234	2172	case vertexAx:
2235		if (chips & 1) v->fbi.ax = (INT16)data;
	2173	if (chips & 1) vd->fbi.ax = (INT16)data;
2236	2174	break;
2237	2175
2238	2176	case fvertexAy:
2239	2177	data = float_to_int32(data, 4);
2240	2178	case vertexAy:
2241		if (chips & 1) v->fbi.ay = (INT16)data;
	2179	if (chips & 1) vd->fbi.ay = (INT16)data;
2242	2180	break;
2243	2181
2244	2182	case fvertexBx:
2245	2183	data = float_to_int32(data, 4);
2246	2184	case vertexBx:
2247		if (chips & 1) v->fbi.bx = (INT16)data;
	2185	if (chips & 1) vd->fbi.bx = (INT16)data;
2248	2186	break;
2249	2187
2250	2188	case fvertexBy:
2251	2189	data = float_to_int32(data, 4);
2252	2190	case vertexBy:
2253		if (chips & 1) v->fbi.by = (INT16)data;
	2191	if (chips & 1) vd->fbi.by = (INT16)data;
2254	2192	break;
2255	2193
2256	2194	case fvertexCx:
2257	2195	data = float_to_int32(data, 4);
2258	2196	case vertexCx:
2259		if (chips & 1) v->fbi.cx = (INT16)data;
	2197	if (chips & 1) vd->fbi.cx = (INT16)data;
2260	2198	break;
2261	2199
2262	2200	case fvertexCy:
2263	2201	data = float_to_int32(data, 4);
2264	2202	case vertexCy:
2265		if (chips & 1) v->fbi.cy = (INT16)data;
	2203	if (chips & 1) vd->fbi.cy = (INT16)data;
2266	2204	break;
2267	2205
2268	2206	/* RGB data is 12.12 formatted fixed point */
2269	2207	case fstartR:
2270	2208	data = float_to_int32(data, 12);
2271	2209	case startR:
2272		if (chips & 1) v->fbi.startr = (INT32)(data << 8) >> 8;
	2210	if (chips & 1) vd->fbi.startr = (INT32)(data << 8) >> 8;
2273	2211	break;
2274	2212
2275	2213	case fstartG:
2276	2214	data = float_to_int32(data, 12);
2277	2215	case startG:
2278		if (chips & 1) v->fbi.startg = (INT32)(data << 8) >> 8;
	2216	if (chips & 1) vd->fbi.startg = (INT32)(data << 8) >> 8;
2279	2217	break;
2280	2218
2281	2219	case fstartB:
2282	2220	data = float_to_int32(data, 12);
2283	2221	case startB:
2284		if (chips & 1) v->fbi.startb = (INT32)(data << 8) >> 8;
	2222	if (chips & 1) vd->fbi.startb = (INT32)(data << 8) >> 8;
2285	2223	break;
2286	2224
2287	2225	case fstartA:
2288	2226	data = float_to_int32(data, 12);
2289	2227	case startA:
2290		if (chips & 1) v->fbi.starta = (INT32)(data << 8) >> 8;
	2228	if (chips & 1) vd->fbi.starta = (INT32)(data << 8) >> 8;
2291	2229	break;
2292	2230
2293	2231	case fdRdX:
2294	2232	data = float_to_int32(data, 12);
2295	2233	case dRdX:
2296		if (chips & 1) v->fbi.drdx = (INT32)(data << 8) >> 8;
	2234	if (chips & 1) vd->fbi.drdx = (INT32)(data << 8) >> 8;
2297	2235	break;
2298	2236
2299	2237	case fdGdX:
2300	2238	data = float_to_int32(data, 12);
2301	2239	case dGdX:
2302		if (chips & 1) v->fbi.dgdx = (INT32)(data << 8) >> 8;
	2240	if (chips & 1) vd->fbi.dgdx = (INT32)(data << 8) >> 8;
2303	2241	break;
2304	2242
2305	2243	case fdBdX:
2306	2244	data = float_to_int32(data, 12);
2307	2245	case dBdX:
2308		if (chips & 1) v->fbi.dbdx = (INT32)(data << 8) >> 8;
	2246	if (chips & 1) vd->fbi.dbdx = (INT32)(data << 8) >> 8;
2309	2247	break;
2310	2248
2311	2249	case fdAdX:
2312	2250	data = float_to_int32(data, 12);
2313	2251	case dAdX:
2314		if (chips & 1) v->fbi.dadx = (INT32)(data << 8) >> 8;
	2252	if (chips & 1) vd->fbi.dadx = (INT32)(data << 8) >> 8;
2315	2253	break;
2316	2254
2317	2255	case fdRdY:
2318	2256	data = float_to_int32(data, 12);
2319	2257	case dRdY:
2320		if (chips & 1) v->fbi.drdy = (INT32)(data << 8) >> 8;
	2258	if (chips & 1) vd->fbi.drdy = (INT32)(data << 8) >> 8;
2321	2259	break;
2322	2260
2323	2261	case fdGdY:
2324	2262	data = float_to_int32(data, 12);
2325	2263	case dGdY:
2326		if (chips & 1) v->fbi.dgdy = (INT32)(data << 8) >> 8;
	2264	if (chips & 1) vd->fbi.dgdy = (INT32)(data << 8) >> 8;
2327	2265	break;
2328	2266
2329	2267	case fdBdY:
2330	2268	data = float_to_int32(data, 12);
2331	2269	case dBdY:
2332		if (chips & 1) v->fbi.dbdy = (INT32)(data << 8) >> 8;
	2270	if (chips & 1) vd->fbi.dbdy = (INT32)(data << 8) >> 8;
2333	2271	break;
2334	2272
2335	2273	case fdAdY:
2336	2274	data = float_to_int32(data, 12);
2337	2275	case dAdY:
2338		if (chips & 1) v->fbi.dady = (INT32)(data << 8) >> 8;
	2276	if (chips & 1) vd->fbi.dady = (INT32)(data << 8) >> 8;
2339	2277	break;
2340	2278
2341	2279	/* Z data is 20.12 formatted fixed point */
2342	2280	case fstartZ:
2343	2281	data = float_to_int32(data, 12);
2344	2282	case startZ:
2345		if (chips & 1) v->fbi.startz = (INT32)data;
	2283	if (chips & 1) vd->fbi.startz = (INT32)data;
2346	2284	break;
2347	2285
2348	2286	case fdZdX:
2349	2287	data = float_to_int32(data, 12);
2350	2288	case dZdX:
2351		if (chips & 1) v->fbi.dzdx = (INT32)data;
	2289	if (chips & 1) vd->fbi.dzdx = (INT32)data;
2352	2290	break;
2353	2291
2354	2292	case fdZdY:
2355	2293	data = float_to_int32(data, 12);
2356	2294	case dZdY:
2357		if (chips & 1) v->fbi.dzdy = (INT32)data;
	2295	if (chips & 1) vd->fbi.dzdy = (INT32)data;
2358	2296	break;
2359	2297
2360	2298	/* S,T data is 14.18 formatted fixed point, converted to 16.32 internally */
2361	2299	case fstartS:
2362	2300	data64 = float_to_int64(data, 32);
2363		if (chips & 2) v->tmu[0].starts = data64;
2364		if (chips & 4) v->tmu[1].starts = data64;
	2301	if (chips & 2) vd->tmu[0].starts = data64;
	2302	if (chips & 4) vd->tmu[1].starts = data64;
2365	2303	break;
2366	2304	case startS:
2367		if (chips & 2) v->tmu[0].starts = (INT64)(INT32)data << 14;
2368		if (chips & 4) v->tmu[1].starts = (INT64)(INT32)data << 14;
	2305	if (chips & 2) vd->tmu[0].starts = (INT64)(INT32)data << 14;
	2306	if (chips & 4) vd->tmu[1].starts = (INT64)(INT32)data << 14;
2369	2307	break;
2370	2308
2371	2309	case fstartT:
2372	2310	data64 = float_to_int64(data, 32);
2373		if (chips & 2) v->tmu[0].startt = data64;
2374		if (chips & 4) v->tmu[1].startt = data64;
	2311	if (chips & 2) vd->tmu[0].startt = data64;
	2312	if (chips & 4) vd->tmu[1].startt = data64;
2375	2313	break;
2376	2314	case startT:
2377		if (chips & 2) v->tmu[0].startt = (INT64)(INT32)data << 14;
2378		if (chips & 4) v->tmu[1].startt = (INT64)(INT32)data << 14;
	2315	if (chips & 2) vd->tmu[0].startt = (INT64)(INT32)data << 14;
	2316	if (chips & 4) vd->tmu[1].startt = (INT64)(INT32)data << 14;
2379	2317	break;
2380	2318
2381	2319	case fdSdX:
2382	2320	data64 = float_to_int64(data, 32);
2383		if (chips & 2) v->tmu[0].dsdx = data64;
2384		if (chips & 4) v->tmu[1].dsdx = data64;
	2321	if (chips & 2) vd->tmu[0].dsdx = data64;
	2322	if (chips & 4) vd->tmu[1].dsdx = data64;
2385	2323	break;
2386	2324	case dSdX:
2387		if (chips & 2) v->tmu[0].dsdx = (INT64)(INT32)data << 14;
2388		if (chips & 4) v->tmu[1].dsdx = (INT64)(INT32)data << 14;
	2325	if (chips & 2) vd->tmu[0].dsdx = (INT64)(INT32)data << 14;
	2326	if (chips & 4) vd->tmu[1].dsdx = (INT64)(INT32)data << 14;
2389	2327	break;
2390	2328
2391	2329	case fdTdX:
2392	2330	data64 = float_to_int64(data, 32);
2393		if (chips & 2) v->tmu[0].dtdx = data64;
2394		if (chips & 4) v->tmu[1].dtdx = data64;
	2331	if (chips & 2) vd->tmu[0].dtdx = data64;
	2332	if (chips & 4) vd->tmu[1].dtdx = data64;
2395	2333	break;
2396	2334	case dTdX:
2397		if (chips & 2) v->tmu[0].dtdx = (INT64)(INT32)data << 14;
2398		if (chips & 4) v->tmu[1].dtdx = (INT64)(INT32)data << 14;
	2335	if (chips & 2) vd->tmu[0].dtdx = (INT64)(INT32)data << 14;
	2336	if (chips & 4) vd->tmu[1].dtdx = (INT64)(INT32)data << 14;
2399	2337	break;
2400	2338
2401	2339	case fdSdY:
2402	2340	data64 = float_to_int64(data, 32);
2403		if (chips & 2) v->tmu[0].dsdy = data64;
2404		if (chips & 4) v->tmu[1].dsdy = data64;
	2341	if (chips & 2) vd->tmu[0].dsdy = data64;
	2342	if (chips & 4) vd->tmu[1].dsdy = data64;
2405	2343	break;
2406	2344	case dSdY:
2407		if (chips & 2) v->tmu[0].dsdy = (INT64)(INT32)data << 14;
2408		if (chips & 4) v->tmu[1].dsdy = (INT64)(INT32)data << 14;
	2345	if (chips & 2) vd->tmu[0].dsdy = (INT64)(INT32)data << 14;
	2346	if (chips & 4) vd->tmu[1].dsdy = (INT64)(INT32)data << 14;
2409	2347	break;
2410	2348
2411	2349	case fdTdY:
2412	2350	data64 = float_to_int64(data, 32);
2413		if (chips & 2) v->tmu[0].dtdy = data64;
2414		if (chips & 4) v->tmu[1].dtdy = data64;
	2351	if (chips & 2) vd->tmu[0].dtdy = data64;
	2352	if (chips & 4) vd->tmu[1].dtdy = data64;
2415	2353	break;
2416	2354	case dTdY:
2417		if (chips & 2) v->tmu[0].dtdy = (INT64)(INT32)data << 14;
2418		if (chips & 4) v->tmu[1].dtdy = (INT64)(INT32)data << 14;
	2355	if (chips & 2) vd->tmu[0].dtdy = (INT64)(INT32)data << 14;
	2356	if (chips & 4) vd->tmu[1].dtdy = (INT64)(INT32)data << 14;
2419	2357	break;
2420	2358
2421	2359	/* W data is 2.30 formatted fixed point, converted to 16.32 internally */
2422	2360	case fstartW:
2423	2361	data64 = float_to_int64(data, 32);
2424		if (chips & 1) v->fbi.startw = data64;
2425		if (chips & 2) v->tmu[0].startw = data64;
2426		if (chips & 4) v->tmu[1].startw = data64;
	2362	if (chips & 1) vd->fbi.startw = data64;
	2363	if (chips & 2) vd->tmu[0].startw = data64;
	2364	if (chips & 4) vd->tmu[1].startw = data64;
2427	2365	break;
2428	2366	case startW:
2429		if (chips & 1) v->fbi.startw = (INT64)(INT32)data << 2;
2430		if (chips & 2) v->tmu[0].startw = (INT64)(INT32)data << 2;
2431		if (chips & 4) v->tmu[1].startw = (INT64)(INT32)data << 2;
	2367	if (chips & 1) vd->fbi.startw = (INT64)(INT32)data << 2;
	2368	if (chips & 2) vd->tmu[0].startw = (INT64)(INT32)data << 2;
	2369	if (chips & 4) vd->tmu[1].startw = (INT64)(INT32)data << 2;
2432	2370	break;
2433	2371
2434	2372	case fdWdX:
2435	2373	data64 = float_to_int64(data, 32);
2436		if (chips & 1) v->fbi.dwdx = data64;
2437		if (chips & 2) v->tmu[0].dwdx = data64;
2438		if (chips & 4) v->tmu[1].dwdx = data64;
	2374	if (chips & 1) vd->fbi.dwdx = data64;
	2375	if (chips & 2) vd->tmu[0].dwdx = data64;
	2376	if (chips & 4) vd->tmu[1].dwdx = data64;
2439	2377	break;
2440	2378	case dWdX:
2441		if (chips & 1) v->fbi.dwdx = (INT64)(INT32)data << 2;
2442		if (chips & 2) v->tmu[0].dwdx = (INT64)(INT32)data << 2;
2443		if (chips & 4) v->tmu[1].dwdx = (INT64)(INT32)data << 2;
	2379	if (chips & 1) vd->fbi.dwdx = (INT64)(INT32)data << 2;
	2380	if (chips & 2) vd->tmu[0].dwdx = (INT64)(INT32)data << 2;
	2381	if (chips & 4) vd->tmu[1].dwdx = (INT64)(INT32)data << 2;
2444	2382	break;
2445	2383
2446	2384	case fdWdY:
2447	2385	data64 = float_to_int64(data, 32);
2448		if (chips & 1) v->fbi.dwdy = data64;
2449		if (chips & 2) v->tmu[0].dwdy = data64;
2450		if (chips & 4) v->tmu[1].dwdy = data64;
	2386	if (chips & 1) vd->fbi.dwdy = data64;
	2387	if (chips & 2) vd->tmu[0].dwdy = data64;
	2388	if (chips & 4) vd->tmu[1].dwdy = data64;
2451	2389	break;
2452	2390	case dWdY:
2453		if (chips & 1) v->fbi.dwdy = (INT64)(INT32)data << 2;
2454		if (chips & 2) v->tmu[0].dwdy = (INT64)(INT32)data << 2;
2455		if (chips & 4) v->tmu[1].dwdy = (INT64)(INT32)data << 2;
	2391	if (chips & 1) vd->fbi.dwdy = (INT64)(INT32)data << 2;
	2392	if (chips & 2) vd->tmu[0].dwdy = (INT64)(INT32)data << 2;
	2393	if (chips & 4) vd->tmu[1].dwdy = (INT64)(INT32)data << 2;
2456	2394	break;
2457	2395
2458	2396	/* setup bits */
r253153	r253154
2460	2398	if (chips & 1)
2461	2399	{
2462	2400	rgb_t rgbdata(data);
2463		v->reg[sAlpha].f = rgbdata.a();
2464		v->reg[sRed].f = rgbdata.r();
2465		v->reg[sGreen].f = rgbdata.g();
2466		v->reg[sBlue].f = rgbdata.b();
	2401	vd->reg[sAlpha].f = rgbdata.a();
	2402	vd->reg[sRed].f = rgbdata.r();
	2403	vd->reg[sGreen].f = rgbdata.g();
	2404	vd->reg[sBlue].f = rgbdata.b();
2467	2405	}
2468	2406	break;
2469	2407
2470	2408	/* mask off invalid bits for different cards */
2471	2409	case fbzColorPath:
2472		poly_wait(v->poly, v->regnames[regnum]);
2473		if (v->type < TYPE_VOODOO_2)
	2410	poly_wait(vd->poly, vd->regnames[regnum]);
	2411	if (vd->vd_type < TYPE_VOODOO_2)
2474	2412	data &= 0x0fffffff;
2475		if (chips & 1) v->reg[fbzColorPath].u = data;
	2413	if (chips & 1) vd->reg[fbzColorPath].u = data;
2476	2414	break;
2477	2415
2478	2416	case fbzMode:
2479		poly_wait(v->poly, v->regnames[regnum]);
2480		if (v->type < TYPE_VOODOO_2)
	2417	poly_wait(vd->poly, vd->regnames[regnum]);
	2418	if (vd->vd_type < TYPE_VOODOO_2)
2481	2419	data &= 0x001fffff;
2482		if (chips & 1) v->reg[fbzMode].u = data;
	2420	if (chips & 1) vd->reg[fbzMode].u = data;
2483	2421	break;
2484	2422
2485	2423	case fogMode:
2486		poly_wait(v->poly, v->regnames[regnum]);
2487		if (v->type < TYPE_VOODOO_2)
	2424	poly_wait(vd->poly, vd->regnames[regnum]);
	2425	if (vd->vd_type < TYPE_VOODOO_2)
2488	2426	data &= 0x0000003f;
2489		if (chips & 1) v->reg[fogMode].u = data;
	2427	if (chips & 1) vd->reg[fogMode].u = data;
2490	2428	break;
2491	2429
2492	2430	/* triangle drawing */
2493	2431	case triangleCMD:
2494		v->fbi.cheating_allowed = (v->fbi.ax != 0 \|\| v->fbi.ay != 0 \|\| v->fbi.bx > 50 \|\| v->fbi.by != 0 \|\| v->fbi.cx != 0 \|\| v->fbi.cy > 50);
2495		v->fbi.sign = data;
2496		cycles = triangle(v);
	2432	vd->fbi.cheating_allowed = (vd->fbi.ax != 0 \|\| vd->fbi.ay != 0 \|\| vd->fbi.bx > 50 \|\| vd->fbi.by != 0 \|\| vd->fbi.cx != 0 \|\| vd->fbi.cy > 50);
	2433	vd->fbi.sign = data;
	2434	cycles = triangle(vd);
2497	2435	break;
2498	2436
2499	2437	case ftriangleCMD:
2500		v->fbi.cheating_allowed = TRUE;
2501		v->fbi.sign = data;
2502		cycles = triangle(v);
	2438	vd->fbi.cheating_allowed = TRUE;
	2439	vd->fbi.sign = data;
	2440	cycles = triangle(vd);
2503	2441	break;
2504	2442
2505	2443	case sBeginTriCMD:
2506		cycles = begin_triangle(v);
	2444	cycles = begin_triangle(vd);
2507	2445	break;
2508	2446
2509	2447	case sDrawTriCMD:
2510		cycles = draw_triangle(v);
	2448	cycles = draw_triangle(vd);
2511	2449	break;
2512	2450
2513	2451	/* other commands */
2514	2452	case nopCMD:
2515		poly_wait(v->poly, v->regnames[regnum]);
	2453	poly_wait(vd->poly, vd->regnames[regnum]);
2516	2454	if (data & 1)
2517		reset_counters(v);
	2455	reset_counters(vd);
2518	2456	if (data & 2)
2519		v->reg[fbiTrianglesOut].u = 0;
	2457	vd->reg[fbiTrianglesOut].u = 0;
2520	2458	break;
2521	2459
2522	2460	case fastfillCMD:
2523		cycles = fastfill(v);
	2461	cycles = fastfill(vd);
2524	2462	break;
2525	2463
2526	2464	case swapbufferCMD:
2527		poly_wait(v->poly, v->regnames[regnum]);
2528		cycles = swapbuffer(v, data);
	2465	poly_wait(vd->poly, vd->regnames[regnum]);
	2466	cycles = swapbuffer(vd, data);
2529	2467	break;
2530	2468
2531	2469	case userIntrCMD:
2532		poly_wait(v->poly, v->regnames[regnum]);
	2470	poly_wait(vd->poly, vd->regnames[regnum]);
2533	2471	//fatalerror("userIntrCMD\n");
2534	2472
2535		v->reg[intrCtrl].u \|= 0x1800;
2536		v->reg[intrCtrl].u &= ~0x80000000;
	2473	vd->reg[intrCtrl].u \|= 0x1800;
	2474	vd->reg[intrCtrl].u &= ~0x80000000;
2537	2475
2538	2476	// TODO: rename vblank_client for less confusion?
2539		if (!v->device->m_vblank.isnull())
2540		v->device->m_vblank(TRUE);
	2477	if (!vd->device->m_vblank.isnull())
	2478	vd->device->m_vblank(TRUE);
2541	2479	break;
2542	2480
2543	2481	/* gamma table access -- Voodoo/Voodoo2 only */
2544	2482	case clutData:
2545		if (v->type <= TYPE_VOODOO_2 && (chips & 1))
	2483	if (vd->vd_type <= TYPE_VOODOO_2 && (chips & 1))
2546	2484	{
2547		poly_wait(v->poly, v->regnames[regnum]);
2548		if (!FBIINIT1_VIDEO_TIMING_RESET(v->reg[fbiInit1].u))
	2485	poly_wait(vd->poly, vd->regnames[regnum]);
	2486	if (!FBIINIT1_VIDEO_TIMING_RESET(vd->reg[fbiInit1].u))
2549	2487	{
2550	2488	int index = data >> 24;
2551	2489	if (index <= 32)
2552	2490	{
2553		v->fbi.clut[index] = data;
2554		v->fbi.clut_dirty = TRUE;
	2491	vd->fbi.clut[index] = data;
	2492	vd->fbi.clut_dirty = TRUE;
2555	2493	}
2556	2494	}
2557	2495	else
2558		v->device->logerror("clutData ignored because video timing reset = 1\n");
	2496	vd->device->logerror("clutData ignored because video timing reset = 1\n");
2559	2497	}
2560	2498	break;
2561	2499
2562	2500	/* external DAC access -- Voodoo/Voodoo2 only */
2563	2501	case dacData:
2564		if (v->type <= TYPE_VOODOO_2 && (chips & 1))
	2502	if (vd->vd_type <= TYPE_VOODOO_2 && (chips & 1))
2565	2503	{
2566		poly_wait(v->poly, v->regnames[regnum]);
	2504	poly_wait(vd->poly, vd->regnames[regnum]);
2567	2505	if (!(data & 0x800))
2568		dacdata_w(&v->dac, (data >> 8) & 7, data & 0xff);
	2506	dacdata_w(&vd->dac, (data >> 8) & 7, data & 0xff);
2569	2507	else
2570		dacdata_r(&v->dac, (data >> 8) & 7);
	2508	dacdata_r(&vd->dac, (data >> 8) & 7);
2571	2509	}
2572	2510	break;
2573	2511
r253153	r253154
2576	2514	case vSync:
2577	2515	case backPorch:
2578	2516	case videoDimensions:
2579		if (v->type <= TYPE_VOODOO_2 && (chips & 1))
	2517	if (vd->vd_type <= TYPE_VOODOO_2 && (chips & 1))
2580	2518	{
2581		poly_wait(v->poly, v->regnames[regnum]);
2582		v->reg[regnum].u = data;
2583		if (v->reg[hSync].u != 0 && v->reg[vSync].u != 0 && v->reg[videoDimensions].u != 0)
	2519	poly_wait(vd->poly, vd->regnames[regnum]);
	2520	vd->reg[regnum].u = data;
	2521	if (vd->reg[hSync].u != 0 && vd->reg[vSync].u != 0 && vd->reg[videoDimensions].u != 0)
2584	2522	{
2585	2523	int hvis, vvis, htotal, vtotal, hbp, vbp;
2586		attoseconds_t refresh = v->screen->frame_period().attoseconds();
	2524	attoseconds_t refresh = vd->screen->frame_period().attoseconds();
2587	2525	attoseconds_t stdperiod, medperiod, vgaperiod;
2588	2526	attoseconds_t stddiff, meddiff, vgadiff;
2589	2527	rectangle visarea;
2590	2528
2591		if (v->type == TYPE_VOODOO_2)
	2529	if (vd->vd_type == TYPE_VOODOO_2)
2592	2530	{
2593		htotal = ((v->reg[hSync].u >> 16) & 0x7ff) + 1 + (v->reg[hSync].u & 0x1ff) + 1;
2594		vtotal = ((v->reg[vSync].u >> 16) & 0x1fff) + (v->reg[vSync].u & 0x1fff);
2595		hvis = v->reg[videoDimensions].u & 0x7ff;
2596		vvis = (v->reg[videoDimensions].u >> 16) & 0x7ff;
2597		hbp = (v->reg[backPorch].u & 0x1ff) + 2;
2598		vbp = (v->reg[backPorch].u >> 16) & 0x1ff;
	2531	htotal = ((vd->reg[hSync].u >> 16) & 0x7ff) + 1 + (vd->reg[hSync].u & 0x1ff) + 1;
	2532	vtotal = ((vd->reg[vSync].u >> 16) & 0x1fff) + (vd->reg[vSync].u & 0x1fff);
	2533	hvis = vd->reg[videoDimensions].u & 0x7ff;
	2534	vvis = (vd->reg[videoDimensions].u >> 16) & 0x7ff;
	2535	hbp = (vd->reg[backPorch].u & 0x1ff) + 2;
	2536	vbp = (vd->reg[backPorch].u >> 16) & 0x1ff;
2599	2537	}
2600	2538	else
2601	2539	{
2602		htotal = ((v->reg[hSync].u >> 16) & 0x3ff) + 1 + (v->reg[hSync].u & 0xff) + 1;
2603		vtotal = ((v->reg[vSync].u >> 16) & 0xfff) + (v->reg[vSync].u & 0xfff);
2604		hvis = v->reg[videoDimensions].u & 0x3ff;
2605		vvis = (v->reg[videoDimensions].u >> 16) & 0x3ff;
2606		hbp = (v->reg[backPorch].u & 0xff) + 2;
2607		vbp = (v->reg[backPorch].u >> 16) & 0xff;
	2540	htotal = ((vd->reg[hSync].u >> 16) & 0x3ff) + 1 + (vd->reg[hSync].u & 0xff) + 1;
	2541	vtotal = ((vd->reg[vSync].u >> 16) & 0xfff) + (vd->reg[vSync].u & 0xfff);
	2542	hvis = vd->reg[videoDimensions].u & 0x3ff;
	2543	vvis = (vd->reg[videoDimensions].u >> 16) & 0x3ff;
	2544	hbp = (vd->reg[backPorch].u & 0xff) + 2;
	2545	vbp = (vd->reg[backPorch].u >> 16) & 0xff;
2608	2546	}
2609	2547
2610	2548	/* create a new visarea */
r253153	r253154
2628	2566	if (vgadiff < 0) vgadiff = -vgadiff;
2629	2567
2630	2568	osd_printf_debug("hSync=%08X vSync=%08X backPorch=%08X videoDimensions=%08X\n",
2631		v->reg[hSync].u, v->reg[vSync].u, v->reg[backPorch].u, v->reg[videoDimensions].u);
	2569	vd->reg[hSync].u, vd->reg[vSync].u, vd->reg[backPorch].u, vd->reg[videoDimensions].u);
2632	2570	osd_printf_debug("Horiz: %d-%d (%d total) Vert: %d-%d (%d total) -- ", visarea.min_x, visarea.max_x, htotal, visarea.min_y, visarea.max_y, vtotal);
2633	2571
2634	2572	/* configure the screen based on which one matches the closest */
2635	2573	if (stddiff < meddiff && stddiff < vgadiff)
2636	2574	{
2637		v->screen->configure(htotal, vtotal, visarea, stdperiod);
	2575	vd->screen->configure(htotal, vtotal, visarea, stdperiod);
2638	2576	osd_printf_debug("Standard resolution, %f Hz\n", ATTOSECONDS_TO_HZ(stdperiod));
2639	2577	}
2640	2578	else if (meddiff < vgadiff)
2641	2579	{
2642		v->screen->configure(htotal, vtotal, visarea, medperiod);
	2580	vd->screen->configure(htotal, vtotal, visarea, medperiod);
2643	2581	osd_printf_debug("Medium resolution, %f Hz\n", ATTOSECONDS_TO_HZ(medperiod));
2644	2582	}
2645	2583	else
2646	2584	{
2647		v->screen->configure(htotal, vtotal, visarea, vgaperiod);
	2585	vd->screen->configure(htotal, vtotal, visarea, vgaperiod);
2648	2586	osd_printf_debug("VGA resolution, %f Hz\n", ATTOSECONDS_TO_HZ(vgaperiod));
2649	2587	}
2650	2588
2651	2589	/* configure the new framebuffer info */
2652		v->fbi.width = hvis;
2653		v->fbi.height = vvis;
2654		v->fbi.xoffs = hbp;
2655		v->fbi.yoffs = vbp;
2656		v->fbi.vsyncscan = (v->reg[vSync].u >> 16) & 0xfff;
	2590	vd->fbi.width = hvis;
	2591	vd->fbi.height = vvis;
	2592	vd->fbi.xoffs = hbp;
	2593	vd->fbi.yoffs = vbp;
	2594	vd->fbi.vsyncscan = (vd->reg[vSync].u >> 16) & 0xfff;
2657	2595
2658	2596	/* recompute the time of VBLANK */
2659		adjust_vblank_timer(v);
	2597	adjust_vblank_timer(vd);
2660	2598
2661	2599	/* if changing dimensions, update video memory layout */
2662	2600	if (regnum == videoDimensions)
2663		recompute_video_memory(v);
	2601	recompute_video_memory(vd);
2664	2602	}
2665	2603	}
2666	2604	break;
2667	2605
2668	2606	/* fbiInit0 can only be written if initEnable says we can -- Voodoo/Voodoo2 only */
2669	2607	case fbiInit0:
2670		poly_wait(v->poly, v->regnames[regnum]);
2671		if (v->type <= TYPE_VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(v->pci.init_enable))
	2608	poly_wait(vd->poly, vd->regnames[regnum]);
	2609	if (vd->vd_type <= TYPE_VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(vd->pci.init_enable))
2672	2610	{
2673		v->reg[fbiInit0].u = data;
	2611	vd->reg[fbiInit0].u = data;
2674	2612	if (FBIINIT0_GRAPHICS_RESET(data))
2675		soft_reset(v);
	2613	soft_reset(vd);
2676	2614	if (FBIINIT0_FIFO_RESET(data))
2677		fifo_reset(&v->pci.fifo);
2678		recompute_video_memory(v);
	2615	fifo_reset(&vd->pci.fifo);
	2616	recompute_video_memory(vd);
2679	2617	}
2680	2618	break;
2681	2619
2682	2620	/* fbiInit5-7 are Voodoo 2-only; ignore them on anything else */
2683	2621	case fbiInit5:
2684	2622	case fbiInit6:
2685		if (v->type < TYPE_VOODOO_2)
	2623	if (vd->vd_type < TYPE_VOODOO_2)
2686	2624	break;
2687	2625	/* else fall through... */
2688	2626
r253153	r253154
2691	2629	case fbiInit1:
2692	2630	case fbiInit2:
2693	2631	case fbiInit4:
2694		poly_wait(v->poly, v->regnames[regnum]);
2695		if (v->type <= TYPE_VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(v->pci.init_enable))
	2632	poly_wait(vd->poly, vd->regnames[regnum]);
	2633	if (vd->vd_type <= TYPE_VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(vd->pci.init_enable))
2696	2634	{
2697		v->reg[regnum].u = data;
2698		recompute_video_memory(v);
2699		v->fbi.video_changed = TRUE;
	2635	vd->reg[regnum].u = data;
	2636	recompute_video_memory(vd);
	2637	vd->fbi.video_changed = TRUE;
2700	2638	}
2701	2639	break;
2702	2640
2703	2641	case fbiInit3:
2704		poly_wait(v->poly, v->regnames[regnum]);
2705		if (v->type <= TYPE_VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(v->pci.init_enable))
	2642	poly_wait(vd->poly, vd->regnames[regnum]);
	2643	if (vd->vd_type <= TYPE_VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(vd->pci.init_enable))
2706	2644	{
2707		v->reg[regnum].u = data;
2708		v->alt_regmap = FBIINIT3_TRI_REGISTER_REMAP(data);
2709		v->fbi.yorigin = FBIINIT3_YORIGIN_SUBTRACT(v->reg[fbiInit3].u);
2710		recompute_video_memory(v);
	2645	vd->reg[regnum].u = data;
	2646	vd->alt_regmap = FBIINIT3_TRI_REGISTER_REMAP(data);
	2647	vd->fbi.yorigin = FBIINIT3_YORIGIN_SUBTRACT(vd->reg[fbiInit3].u);
	2648	recompute_video_memory(vd);
2711	2649	}
2712	2650	break;
2713	2651
2714	2652	case fbiInit7:
2715	2653	/* case swapPending: -- Banshee */
2716		if (v->type == TYPE_VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(v->pci.init_enable))
	2654	if (vd->vd_type == TYPE_VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(vd->pci.init_enable))
2717	2655	{
2718		poly_wait(v->poly, v->regnames[regnum]);
2719		v->reg[regnum].u = data;
2720		v->fbi.cmdfifo[0].enable = FBIINIT7_CMDFIFO_ENABLE(data);
2721		v->fbi.cmdfifo[0].count_holes = !FBIINIT7_DISABLE_CMDFIFO_HOLES(data);
	2656	poly_wait(vd->poly, vd->regnames[regnum]);
	2657	vd->reg[regnum].u = data;
	2658	vd->fbi.cmdfifo[0].enable = FBIINIT7_CMDFIFO_ENABLE(data);
	2659	vd->fbi.cmdfifo[0].count_holes = !FBIINIT7_DISABLE_CMDFIFO_HOLES(data);
2722	2660	}
2723		else if (v->type >= TYPE_VOODOO_BANSHEE)
2724		v->fbi.swaps_pending++;
	2661	else if (vd->vd_type >= TYPE_VOODOO_BANSHEE)
	2662	vd->fbi.swaps_pending++;
2725	2663	break;
2726	2664
2727	2665	/* cmdFifo -- Voodoo2 only */
2728	2666	case cmdFifoBaseAddr:
2729		if (v->type == TYPE_VOODOO_2 && (chips & 1))
	2667	if (vd->vd_type == TYPE_VOODOO_2 && (chips & 1))
2730	2668	{
2731		poly_wait(v->poly, v->regnames[regnum]);
2732		v->reg[regnum].u = data;
2733		v->fbi.cmdfifo[0].base = (data & 0x3ff) << 12;
2734		v->fbi.cmdfifo[0].end = (((data >> 16) & 0x3ff) + 1) << 12;
	2669	poly_wait(vd->poly, vd->regnames[regnum]);
	2670	vd->reg[regnum].u = data;
	2671	vd->fbi.cmdfifo[0].base = (data & 0x3ff) << 12;
	2672	vd->fbi.cmdfifo[0].end = (((data >> 16) & 0x3ff) + 1) << 12;
2735	2673	}
2736	2674	break;
2737	2675
2738	2676	case cmdFifoBump:
2739		if (v->type == TYPE_VOODOO_2 && (chips & 1))
	2677	if (vd->vd_type == TYPE_VOODOO_2 && (chips & 1))
2740	2678	fatalerror("cmdFifoBump\n");
2741	2679	break;
2742	2680
2743	2681	case cmdFifoRdPtr:
2744		if (v->type == TYPE_VOODOO_2 && (chips & 1))
2745		v->fbi.cmdfifo[0].rdptr = data;
	2682	if (vd->vd_type == TYPE_VOODOO_2 && (chips & 1))
	2683	vd->fbi.cmdfifo[0].rdptr = data;
2746	2684	break;
2747	2685
2748	2686	case cmdFifoAMin:
2749	2687	/* case colBufferAddr: -- Banshee */
2750		if (v->type == TYPE_VOODOO_2 && (chips & 1))
2751		v->fbi.cmdfifo[0].amin = data;
2752		else if (v->type >= TYPE_VOODOO_BANSHEE && (chips & 1))
2753		v->fbi.rgboffs[1] = data & v->fbi.mask & ~0x0f;
	2688	if (vd->vd_type == TYPE_VOODOO_2 && (chips & 1))
	2689	vd->fbi.cmdfifo[0].amin = data;
	2690	else if (vd->vd_type >= TYPE_VOODOO_BANSHEE && (chips & 1))
	2691	vd->fbi.rgboffs[1] = data & vd->fbi.mask & ~0x0f;
2754	2692	break;
2755	2693
2756	2694	case cmdFifoAMax:
2757	2695	/* case colBufferStride: -- Banshee */
2758		if (v->type == TYPE_VOODOO_2 && (chips & 1))
2759		v->fbi.cmdfifo[0].amax = data;
2760		else if (v->type >= TYPE_VOODOO_BANSHEE && (chips & 1))
	2696	if (vd->vd_type == TYPE_VOODOO_2 && (chips & 1))
	2697	vd->fbi.cmdfifo[0].amax = data;
	2698	else if (vd->vd_type >= TYPE_VOODOO_BANSHEE && (chips & 1))
2761	2699	{
2762	2700	if (data & 0x8000)
2763		v->fbi.rowpixels = (data & 0x7f) << 6;
	2701	vd->fbi.rowpixels = (data & 0x7f) << 6;
2764	2702	else
2765		v->fbi.rowpixels = (data & 0x3fff) >> 1;
	2703	vd->fbi.rowpixels = (data & 0x3fff) >> 1;
2766	2704	}
2767	2705	break;
2768	2706
2769	2707	case cmdFifoDepth:
2770	2708	/* case auxBufferAddr: -- Banshee */
2771		if (v->type == TYPE_VOODOO_2 && (chips & 1))
2772		v->fbi.cmdfifo[0].depth = data;
2773		else if (v->type >= TYPE_VOODOO_BANSHEE && (chips & 1))
2774		v->fbi.auxoffs = data & v->fbi.mask & ~0x0f;
	2709	if (vd->vd_type == TYPE_VOODOO_2 && (chips & 1))
	2710	vd->fbi.cmdfifo[0].depth = data;
	2711	else if (vd->vd_type >= TYPE_VOODOO_BANSHEE && (chips & 1))
	2712	vd->fbi.auxoffs = data & vd->fbi.mask & ~0x0f;
2775	2713	break;
2776	2714
2777	2715	case cmdFifoHoles:
2778	2716	/* case auxBufferStride: -- Banshee */
2779		if (v->type == TYPE_VOODOO_2 && (chips & 1))
2780		v->fbi.cmdfifo[0].holes = data;
2781		else if (v->type >= TYPE_VOODOO_BANSHEE && (chips & 1))
	2717	if (vd->vd_type == TYPE_VOODOO_2 && (chips & 1))
	2718	vd->fbi.cmdfifo[0].holes = data;
	2719	else if (vd->vd_type >= TYPE_VOODOO_BANSHEE && (chips & 1))
2782	2720	{
2783	2721	int rowpixels;
2784	2722
r253153	r253154
2786	2724	rowpixels = (data & 0x7f) << 6;
2787	2725	else
2788	2726	rowpixels = (data & 0x3fff) >> 1;
2789		if (v->fbi.rowpixels != rowpixels)
	2727	if (vd->fbi.rowpixels != rowpixels)
2790	2728	fatalerror("aux buffer stride differs from color buffer stride\n");
2791	2729	}
2792	2730	break;
r253153	r253154
2804	2742	case nccTable+9:
2805	2743	case nccTable+10:
2806	2744	case nccTable+11:
2807		poly_wait(v->poly, v->regnames[regnum]);
2808		if (chips & 2) ncc_table_write(&v->tmu[0].ncc[0], regnum - nccTable, data);
2809		if (chips & 4) ncc_table_write(&v->tmu[1].ncc[0], regnum - nccTable, data);
	2745	poly_wait(vd->poly, vd->regnames[regnum]);
	2746	if (chips & 2) ncc_table_write(&vd->tmu[0].ncc[0], regnum - nccTable, data);
	2747	if (chips & 4) ncc_table_write(&vd->tmu[1].ncc[0], regnum - nccTable, data);
2810	2748	break;
2811	2749
2812	2750	case nccTable+12:
r253153	r253154
2821	2759	case nccTable+21:
2822	2760	case nccTable+22:
2823	2761	case nccTable+23:
2824		poly_wait(v->poly, v->regnames[regnum]);
2825		if (chips & 2) ncc_table_write(&v->tmu[0].ncc[1], regnum - (nccTable+12), data);
2826		if (chips & 4) ncc_table_write(&v->tmu[1].ncc[1], regnum - (nccTable+12), data);
	2762	poly_wait(vd->poly, vd->regnames[regnum]);
	2763	if (chips & 2) ncc_table_write(&vd->tmu[0].ncc[1], regnum - (nccTable+12), data);
	2764	if (chips & 4) ncc_table_write(&vd->tmu[1].ncc[1], regnum - (nccTable+12), data);
2827	2765	break;
2828	2766
2829	2767	/* fogTable entries are processed and expanded immediately */
r253153	r253154
2859	2797	case fogTable+29:
2860	2798	case fogTable+30:
2861	2799	case fogTable+31:
2862		poly_wait(v->poly, v->regnames[regnum]);
	2800	poly_wait(vd->poly, vd->regnames[regnum]);
2863	2801	if (chips & 1)
2864	2802	{
2865	2803	int base = 2 * (regnum - fogTable);
2866		v->fbi.fogdelta[base + 0] = (data >> 0) & 0xff;
2867		v->fbi.fogblend[base + 0] = (data >> 8) & 0xff;
2868		v->fbi.fogdelta[base + 1] = (data >> 16) & 0xff;
2869		v->fbi.fogblend[base + 1] = (data >> 24) & 0xff;
	2804	vd->fbi.fogdelta[base + 0] = (data >> 0) & 0xff;
	2805	vd->fbi.fogblend[base + 0] = (data >> 8) & 0xff;
	2806	vd->fbi.fogdelta[base + 1] = (data >> 16) & 0xff;
	2807	vd->fbi.fogblend[base + 1] = (data >> 24) & 0xff;
2870	2808	}
2871	2809	break;
2872	2810
r253153	r253154
2878	2816	case texBaseAddr_1:
2879	2817	case texBaseAddr_2:
2880	2818	case texBaseAddr_3_8:
2881		poly_wait(v->poly, v->regnames[regnum]);
	2819	poly_wait(vd->poly, vd->regnames[regnum]);
2882	2820	if (chips & 2)
2883	2821	{
2884		v->tmu[0].reg[regnum].u = data;
2885		v->tmu[0].regdirty = TRUE;
	2822	vd->tmu[0].reg[regnum].u = data;
	2823	vd->tmu[0].regdirty = TRUE;
2886	2824	}
2887	2825	if (chips & 4)
2888	2826	{
2889		v->tmu[1].reg[regnum].u = data;
2890		v->tmu[1].regdirty = TRUE;
	2827	vd->tmu[1].reg[regnum].u = data;
	2828	vd->tmu[1].regdirty = TRUE;
2891	2829	}
2892	2830	break;
2893	2831
2894	2832	case trexInit1:
2895	2833	/* send tmu config data to the frame buffer */
2896		v->send_config = (TREXINIT_SEND_TMU_CONFIG(data) > 0);
	2834	vd->send_config = (TREXINIT_SEND_TMU_CONFIG(data) > 0);
2897	2835	goto default_case;
2898	2836
2899	2837	/* these registers are referenced in the renderer; we must wait for pending work before changing */
r253153	r253154
2907	2845	case color0:
2908	2846	case clipLowYHighY:
2909	2847	case clipLeftRight:
2910		poly_wait(v->poly, v->regnames[regnum]);
	2848	poly_wait(vd->poly, vd->regnames[regnum]);
2911	2849	/* fall through to default implementation */
2912	2850
2913	2851	/* by default, just feed the data to the chips */
2914	2852	default:
2915	2853	default_case:
2916		if (chips & 1) v->reg[0x000 + regnum].u = data;
2917		if (chips & 2) v->reg[0x100 + regnum].u = data;
2918		if (chips & 4) v->reg[0x200 + regnum].u = data;
2919		if (chips & 8) v->reg[0x300 + regnum].u = data;
	2854	if (chips & 1) vd->reg[0x000 + regnum].u = data;
	2855	if (chips & 2) vd->reg[0x100 + regnum].u = data;
	2856	if (chips & 4) vd->reg[0x200 + regnum].u = data;
	2857	if (chips & 8) vd->reg[0x300 + regnum].u = data;
2920	2858	break;
2921	2859	}
2922	2860
2923	2861	if (LOG_REGISTERS)
2924	2862	{
2925	2863	if (regnum < fvertexAx \|\| regnum > fdWdY)
2926		v->device->logerror("VOODOO.%d.REG:%s(%d) write = %08X\n", v->index, (regnum < 0x384/4) ? v->regnames[regnum] : "oob", chips, origdata);
	2864	vd->device->logerror("VOODOO.%d.REG:%s(%d) write = %08X\n", vd->index, (regnum < 0x384/4) ? vd->regnames[regnum] : "oob", chips, origdata);
2927	2865	else
2928		v->device->logerror("VOODOO.%d.REG:%s(%d) write = %f\n", v->index, (regnum < 0x384/4) ? v->regnames[regnum] : "oob", chips, (double) u2f(origdata));
	2866	vd->device->logerror("VOODOO.%d.REG:%s(%d) write = %f\n", vd->index, (regnum < 0x384/4) ? vd->regnames[regnum] : "oob", chips, (double) u2f(origdata));
2929	2867	}
2930	2868
2931	2869	return cycles;
r253153	r253154
2938	2876	* Voodoo LFB writes
2939	2877	*
2940	2878	*************************************/
2941		static INT32 lfb_direct_w(voodoo_state *v, offs_t offset, UINT32 data, UINT32 mem_mask)
2942		{
	2879	INT32 voodoo_device::lfb_direct_w(voodoo_device *vd, offs_t offset, UINT32 data, UINT32 mem_mask)
	2880	{
2943	2881	UINT16 *dest;
2944	2882	UINT32 destmax;
2945	2883	int x, y;
2946	2884	UINT32 bufoffs;
2947	2885
2948	2886	/* statistics */
2949		v->stats.lfb_writes++;
	2887	vd->stats.lfb_writes++;
2950	2888
2951	2889	/* byte swizzling */
2952		if (LFBMODE_BYTE_SWIZZLE_WRITES(v->reg[lfbMode].u))
	2890	if (LFBMODE_BYTE_SWIZZLE_WRITES(vd->reg[lfbMode].u))
2953	2891	{
2954	2892	data = FLIPENDIAN_INT32(data);
2955	2893	mem_mask = FLIPENDIAN_INT32(mem_mask);
2956	2894	}
2957	2895
2958	2896	/* word swapping */
2959		if (LFBMODE_WORD_SWAP_WRITES(v->reg[lfbMode].u))
	2897	if (LFBMODE_WORD_SWAP_WRITES(vd->reg[lfbMode].u))
2960	2898	{
2961	2899	data = (data << 16) \| (data >> 16);
2962	2900	mem_mask = (mem_mask << 16) \| (mem_mask >> 16);
r253153	r253154
2966	2904	// For direct lfb access just write the data
2967	2905	/* compute X,Y */
2968	2906	offset <<= 1;
2969		x = offset & ((1 << v->fbi.lfb_stride) - 1);
2970		y = (offset >> v->fbi.lfb_stride);
2971		dest = (UINT16 )(v->fbi.ram + v->fbi.lfb_base4);
2972		destmax = (v->fbi.mask + 1 - v->fbi.lfb_base*4) / 2;
2973		bufoffs = y * v->fbi.rowpixels + x;
	2907	x = offset & ((1 << vd->fbi.lfb_stride) - 1);
	2908	y = (offset >> vd->fbi.lfb_stride);
	2909	dest = (UINT16 )(vd->fbi.ram + vd->fbi.lfb_base4);
	2910	destmax = (vd->fbi.mask + 1 - vd->fbi.lfb_base*4) / 2;
	2911	bufoffs = y * vd->fbi.rowpixels + x;
2974	2912	if (bufoffs >= destmax) {
2975		v->device->logerror("lfb_direct_w: Buffer offset out of bounds x=%i y=%i offset=%08X bufoffs=%08X data=%08X\n", x, y, offset, (UINT32) bufoffs, data);
	2913	vd->device->logerror("lfb_direct_w: Buffer offset out of bounds x=%i y=%i offset=%08X bufoffs=%08X data=%08X\n", x, y, offset, (UINT32) bufoffs, data);
2976	2914	return 0;
2977	2915	}
2978	2916	if (ACCESSING_BITS_0_15)
2979	2917	dest[bufoffs + 0] = data&0xffff;
2980	2918	if (ACCESSING_BITS_16_31)
2981	2919	dest[bufoffs + 1] = data>>16;
2982		if (LOG_LFB) v->device->logerror("VOODOO.%d.LFB:write direct (%d,%d) = %08X & %08X\n", v->index, x, y, data, mem_mask);
	2920	if (LOG_LFB) vd->device->logerror("VOODOO.%d.LFB:write direct (%d,%d) = %08X & %08X\n", vd->index, x, y, data, mem_mask);
2983	2921	return 0;
2984	2922	}
2985	2923
2986		~~static~~ INT32 lfb_w(voodoo_~~stat~~e *v, offs_t offset, UINT32 data, UINT32 mem_mask)
	2924	INT32 voodoo_device::lfb_w(voodoo_device* vd, offs_t offset, UINT32 data, UINT32 mem_mask)
2987	2925	{
	2926
2988	2927	UINT16 dest, depth;
2989	2928	UINT32 destmax, depthmax;
2990	2929	int sr[2], sg[2], sb[2], sa[2], sw[2];
r253153	r253154
2992	2931	int pix, destbuf;
2993	2932
2994	2933	/* statistics */
2995		v->stats.lfb_writes++;
	2934	vd->stats.lfb_writes++;
2996	2935
2997	2936	/* byte swizzling */
2998		if (LFBMODE_BYTE_SWIZZLE_WRITES(v->reg[lfbMode].u))
	2937	if (LFBMODE_BYTE_SWIZZLE_WRITES(vd->reg[lfbMode].u))
2999	2938	{
3000	2939	data = FLIPENDIAN_INT32(data);
3001	2940	mem_mask = FLIPENDIAN_INT32(mem_mask);
3002	2941	}
3003	2942
3004	2943	/* word swapping */
3005		if (LFBMODE_WORD_SWAP_WRITES(v->reg[lfbMode].u))
	2944	if (LFBMODE_WORD_SWAP_WRITES(vd->reg[lfbMode].u))
3006	2945	{
3007	2946	data = (data << 16) \| (data >> 16);
3008	2947	mem_mask = (mem_mask << 16) \| (mem_mask >> 16);
3009	2948	}
3010	2949
3011	2950	/* extract default depth and alpha values */
3012		sw[0] = sw[1] = v->reg[zaColor].u & 0xffff;
3013		sa[0] = sa[1] = v->reg[zaColor].u >> 24;
	2951	sw[0] = sw[1] = vd->reg[zaColor].u & 0xffff;
	2952	sa[0] = sa[1] = vd->reg[zaColor].u >> 24;
3014	2953
3015	2954	/* first extract A,R,G,B from the data */
3016		switch (LFBMODE_WRITE_FORMAT(v->reg[lfbMode].u) + 16 * LFBMODE_RGBA_LANES(v->reg[lfbMode].u))
	2955	switch (LFBMODE_WRITE_FORMAT(vd->reg[lfbMode].u) + 16 * LFBMODE_RGBA_LANES(vd->reg[lfbMode].u))
3017	2956	{
3018	2957	case 160 + 0: / ARGB, 16-bit RGB 5-6-5 */
3019	2958	case 162 + 0: / RGBA, 16-bit RGB 5-6-5 */
r253153	r253154
3180	3119	break;
3181	3120
3182	3121	default: /* reserved */
3183		v->device->logerror("lfb_w: Unknown format\n");
	3122	vd->device->logerror("lfb_w: Unknown format\n");
3184	3123	return 0;
3185	3124	}
3186	3125
3187	3126	/* compute X,Y */
3188		x = offset & ((1 << v->fbi.lfb_stride) - 1);
3189		y = (offset >> v->fbi.lfb_stride) & 0x3ff;
	3127	x = offset & ((1 << vd->fbi.lfb_stride) - 1);
	3128	y = (offset >> vd->fbi.lfb_stride) & 0x3ff;
3190	3129
3191	3130	/* adjust the mask based on which half of the data is written */
3192	3131	if (!ACCESSING_BITS_0_15)
r253153	r253154
3195	3134	mask &= ~(0xf0 + LFB_DEPTH_PRESENT_MSW);
3196	3135
3197	3136	/* select the target buffer */
3198		destbuf = (v->type >= TYPE_VOODOO_BANSHEE) ? 1 : LFBMODE_WRITE_BUFFER_SELECT(v->reg[lfbMode].u);
	3137	destbuf = (vd->vd_type >= TYPE_VOODOO_BANSHEE) ? 1 : LFBMODE_WRITE_BUFFER_SELECT(vd->reg[lfbMode].u);
3199	3138	switch (destbuf)
3200	3139	{
3201	3140	case 0: /* front buffer */
3202		dest = (UINT16 *)(v->fbi.ram + v->fbi.rgboffs[v->fbi.frontbuf]);
3203		destmax = (v->fbi.mask + 1 - v->fbi.rgboffs[v->fbi.frontbuf]) / 2;
3204		v->fbi.video_changed = TRUE;
	3141	dest = (UINT16 *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.frontbuf]);
	3142	destmax = (vd->fbi.mask + 1 - vd->fbi.rgboffs[vd->fbi.frontbuf]) / 2;
	3143	vd->fbi.video_changed = TRUE;
3205	3144	break;
3206	3145
3207	3146	case 1: /* back buffer */
3208		dest = (UINT16 *)(v->fbi.ram + v->fbi.rgboffs[v->fbi.backbuf]);
3209		destmax = (v->fbi.mask + 1 - v->fbi.rgboffs[v->fbi.backbuf]) / 2;
	3147	dest = (UINT16 *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.backbuf]);
	3148	destmax = (vd->fbi.mask + 1 - vd->fbi.rgboffs[vd->fbi.backbuf]) / 2;
3210	3149	break;
3211	3150
3212	3151	default: /* reserved */
3213	3152	return 0;
3214	3153	}
3215		depth = (UINT16 *)(v->fbi.ram + v->fbi.auxoffs);
3216		depthmax = (v->fbi.mask + 1 - v->fbi.auxoffs) / 2;
	3154	depth = (UINT16 *)(vd->fbi.ram + vd->fbi.auxoffs);
	3155	depthmax = (vd->fbi.mask + 1 - vd->fbi.auxoffs) / 2;
3217	3156
3218	3157	/* simple case: no pipeline */
3219		if (!LFBMODE_ENABLE_PIXEL_PIPELINE(v->reg[lfbMode].u))
	3158	if (!LFBMODE_ENABLE_PIXEL_PIPELINE(vd->reg[lfbMode].u))
3220	3159	{
3221	3160	DECLARE_DITHER_POINTERS_NO_DITHER_VAR;
3222	3161	UINT32 bufoffs;
3223	3162
3224		if (LOG_LFB) v->device->logerror("VOODOO.%d.LFB:write raw mode %X (%d,%d) = %08X & %08X\n", v->index, LFBMODE_WRITE_FORMAT(v->reg[lfbMode].u), x, y, data, mem_mask);
	3163	if (LOG_LFB) vd->device->logerror("VOODOO.%d.LFB:write raw mode %X (%d,%d) = %08X & %08X\n", vd->index, LFBMODE_WRITE_FORMAT(vd->reg[lfbMode].u), x, y, data, mem_mask);
3225	3164
3226	3165	/* determine the screen Y */
3227	3166	scry = y;
3228		if (LFBMODE_Y_ORIGIN(v->reg[lfbMode].u))
3229		scry = (v->fbi.yorigin - y) & 0x3ff;
	3167	if (LFBMODE_Y_ORIGIN(vd->reg[lfbMode].u))
	3168	scry = (vd->fbi.yorigin - y) & 0x3ff;
3230	3169
3231	3170	/* advance pointers to the proper row */
3232		bufoffs = scry * v->fbi.rowpixels + x;
	3171	bufoffs = scry * vd->fbi.rowpixels + x;
3233	3172
3234	3173	/* compute dithering */
3235		COMPUTE_DITHER_POINTERS_NO_DITHER_VAR(v->reg[fbzMode].u, y);
	3174	COMPUTE_DITHER_POINTERS_NO_DITHER_VAR(vd->reg[fbzMode].u, y);
3236	3175
3237	3176	/* wait for any outstanding work to finish */
3238		poly_wait(v->poly, "LFB Write");
	3177	poly_wait(vd->poly, "LFB Write");
3239	3178
3240	3179	/* loop over up to two pixels */
3241	3180	for (pix = 0; mask; pix++)
r253153	r253154
3247	3186	if ((mask & LFB_RGB_PRESENT) && bufoffs < destmax)
3248	3187	{
3249	3188	/* apply dithering and write to the screen */
3250		APPLY_DITHER(v->reg[fbzMode].u, x, dither_lookup, sr[pix], sg[pix], sb[pix]);
	3189	APPLY_DITHER(vd->reg[fbzMode].u, x, dither_lookup, sr[pix], sg[pix], sb[pix]);
3251	3190	dest[bufoffs] = (sr[pix] << 11) \| (sg[pix] << 5) \| sb[pix];
3252	3191	}
3253	3192
r253153	r253154
3255	3194	if (depth && bufoffs < depthmax)
3256	3195	{
3257	3196	/* write to the alpha buffer */
3258		if ((mask & LFB_ALPHA_PRESENT) && FBZMODE_ENABLE_ALPHA_PLANES(v->reg[fbzMode].u))
	3197	if ((mask & LFB_ALPHA_PRESENT) && FBZMODE_ENABLE_ALPHA_PLANES(vd->reg[fbzMode].u))
3259	3198	depth[bufoffs] = sa[pix];
3260	3199
3261	3200	/* write to the depth buffer */
3262		if ((mask & (LFB_DEPTH_PRESENT \| LFB_DEPTH_PRESENT_MSW)) && !FBZMODE_ENABLE_ALPHA_PLANES(v->reg[fbzMode].u))
	3201	if ((mask & (LFB_DEPTH_PRESENT \| LFB_DEPTH_PRESENT_MSW)) && !FBZMODE_ENABLE_ALPHA_PLANES(vd->reg[fbzMode].u))
3263	3202	depth[bufoffs] = sw[pix];
3264	3203	}
3265	3204
3266	3205	/* track pixel writes to the frame buffer regardless of mask */
3267		v->reg[fbiPixelsOut].u++;
	3206	vd->reg[fbiPixelsOut].u++;
3268	3207	}
3269	3208
3270	3209	/* advance our pointers */
r253153	r253154
3279	3218	{
3280	3219	DECLARE_DITHER_POINTERS;
3281	3220
3282		if (LOG_LFB) v->device->logerror("VOODOO.%d.LFB:write pipelined mode %X (%d,%d) = %08X & %08X\n", v->index, LFBMODE_WRITE_FORMAT(v->reg[lfbMode].u), x, y, data, mem_mask);
	3221	if (LOG_LFB) vd->device->logerror("VOODOO.%d.LFB:write pipelined mode %X (%d,%d) = %08X & %08X\n", vd->index, LFBMODE_WRITE_FORMAT(vd->reg[lfbMode].u), x, y, data, mem_mask);
3283	3222
3284	3223	/* determine the screen Y */
3285	3224	scry = y;
3286		if (FBZMODE_Y_ORIGIN(v->reg[fbzMode].u))
3287		scry = (v->fbi.yorigin - y) & 0x3ff;
	3225	if (FBZMODE_Y_ORIGIN(vd->reg[fbzMode].u))
	3226	scry = (vd->fbi.yorigin - y) & 0x3ff;
3288	3227
3289	3228	/* advance pointers to the proper row */
3290		dest += scry * v->fbi.rowpixels;
	3229	dest += scry * vd->fbi.rowpixels;
3291	3230	if (depth)
3292		depth += scry * v->fbi.rowpixels;
	3231	depth += scry * vd->fbi.rowpixels;
3293	3232
3294	3233	/* compute dithering */
3295		COMPUTE_DITHER_POINTERS(v->reg[fbzMode].u, y);
	3234	COMPUTE_DITHER_POINTERS(vd->reg[fbzMode].u, y);
3296	3235
3297	3236	/* loop over up to two pixels */
3298	3237	for (pix = 0; mask; pix++)
r253153	r253154
3300	3239	/* make sure we care about this pixel */
3301	3240	if (mask & 0x0f)
3302	3241	{
3303		stats_block *stats = &v->fbi.lfb_stats;
	3242	stats_block *stats = &vd->fbi.lfb_stats;
3304	3243	INT64 iterw;
3305		if (LFBMODE_WRITE_W_SELECT(v->reg[lfbMode].u)) {
3306		iterw = (UINT32) v->reg[zaColor].u << 16;
	3244	if (LFBMODE_WRITE_W_SELECT(vd->reg[lfbMode].u)) {
	3245	iterw = (UINT32) vd->reg[zaColor].u << 16;
3307	3246	} else {
3308	3247	// The most significant fractional bits of 16.32 W are set to z
3309	3248	iterw = (UINT32) sw[pix] << 16;
r253153	r253154
3311	3250	INT32 iterz = sw[pix] << 12;
3312	3251
3313	3252	/* apply clipping */
3314		if (FBZMODE_ENABLE_CLIPPING(v->reg[fbzMode].u))
	3253	if (FBZMODE_ENABLE_CLIPPING(vd->reg[fbzMode].u))
3315	3254	{
3316		if (x < ((v->reg[clipLeftRight].u >> 16) & 0x3ff) \|\|
3317		x >= (v->reg[clipLeftRight].u & 0x3ff) \|\|
3318		scry < ((v->reg[clipLowYHighY].u >> 16) & 0x3ff) \|\|
3319		scry >= (v->reg[clipLowYHighY].u & 0x3ff))
	3255	if (x < ((vd->reg[clipLeftRight].u >> 16) & 0x3ff) \|\|
	3256	x >= (vd->reg[clipLeftRight].u & 0x3ff) \|\|
	3257	scry < ((vd->reg[clipLowYHighY].u >> 16) & 0x3ff) \|\|
	3258	scry >= (vd->reg[clipLowYHighY].u & 0x3ff))
3320	3259	{
3321	3260	stats->pixels_in++;
3322	3261	stats->clip_fail++;
r253153	r253154
3329	3268
3330	3269
3331	3270	/* pixel pipeline part 1 handles depth testing and stippling */
3332		//PIXEL_PIPELINE_BEGIN(v, stats, x, y, v->reg[fbzColorPath].u, v->reg[fbzMode].u, iterz, iterw);
	3271	//PIXEL_PIPELINE_BEGIN(v, stats, x, y, vd->reg[fbzColorPath].u, vd->reg[fbzMode].u, iterz, iterw);
3333	3272	// Start PIXEL_PIPE_BEGIN copy
3334	3273	//#define PIXEL_PIPELINE_BEGIN(VV, STATS, XX, YY, FBZCOLORPATH, FBZMODE, ITERZ, ITERW)
3335	3274	INT32 fogdepth, biasdepth;
r253153	r253154
3341	3280	/* note that for perf reasons, we assume the caller has done clipping */
3342	3281
3343	3282	/* handle stippling */
3344		if (FBZMODE_ENABLE_STIPPLE(v->reg[fbzMode].u))
	3283	if (FBZMODE_ENABLE_STIPPLE(vd->reg[fbzMode].u))
3345	3284	{
3346	3285	/* rotate mode */
3347		if (FBZMODE_STIPPLE_PATTERN(v->reg[fbzMode].u) == 0)
	3286	if (FBZMODE_STIPPLE_PATTERN(vd->reg[fbzMode].u) == 0)
3348	3287	{
3349		v->reg[stipple].u = (v->reg[stipple].u << 1) \| (v->reg[stipple].u >> 31);
3350		if ((v->reg[stipple].u & 0x80000000) == 0)
	3288	vd->reg[stipple].u = (vd->reg[stipple].u << 1) \| (vd->reg[stipple].u >> 31);
	3289	if ((vd->reg[stipple].u & 0x80000000) == 0)
3351	3290	{
3352		v->stats.total_stippled++;
	3291	vd->stats.total_stippled++;
3353	3292	goto skipdrawdepth;
3354	3293	}
3355	3294	}
r253153	r253154
3358	3297	else
3359	3298	{
3360	3299	int stipple_index = ((y & 3) << 3) \| (~x & 7);
3361		if (((v->reg[stipple].u >> stipple_index) & 1) == 0)
	3300	if (((vd->reg[stipple].u >> stipple_index) & 1) == 0)
3362	3301	{
3363		v->stats.total_stippled++;
	3302	vd->stats.total_stippled++;
3364	3303	goto nextpixel;
3365	3304	}
3366	3305	}
r253153	r253154
3372	3311
3373	3312
3374	3313	/* Perform depth testing */
3375		if (!depthTest((UINT16) v->reg[zaColor].u, stats, depth[x], v->reg[fbzMode].u, biasdepth))
	3314	if (!depthTest((UINT16) vd->reg[zaColor].u, stats, depth[x], vd->reg[fbzMode].u, biasdepth))
3376	3315	goto nextpixel;
3377	3316
3378	3317	/* use the RGBA we stashed above */
3379	3318	color.set(sa[pix], sr[pix], sg[pix], sb[pix]);
3380	3319
3381	3320	/* handle chroma key */
3382		if (!chromaKeyTest(v, stats, v->reg[fbzMode].u, color))
	3321	if (!chromaKeyTest(vd, stats, vd->reg[fbzMode].u, color))
3383	3322	goto nextpixel;
3384	3323	/* handle alpha mask */
3385		if (!alphaMaskTest(stats, v->reg[fbzMode].u, color.get_a()))
	3324	if (!alphaMaskTest(stats, vd->reg[fbzMode].u, color.get_a()))
3386	3325	goto nextpixel;
3387	3326	/* handle alpha test */
3388		if (!alphaTest(v, stats, v->reg[alphaMode].u, color.get_a()))
	3327	if (!alphaTest(vd, stats, vd->reg[alphaMode].u, color.get_a()))
3389	3328	goto nextpixel;
3390	3329
3391	3330
3392	3331	/* wait for any outstanding work to finish */
3393		poly_wait(v->poly, "LFB Write");
	3332	poly_wait(vd->poly, "LFB Write");
3394	3333
3395	3334	/* pixel pipeline part 2 handles color combine, fog, alpha, and final output */
3396		PIXEL_PIPELINE_END(v, stats, dither, dither4, dither_lookup, x, dest, depth,
3397		v->reg[fbzMode].u, v->reg[fbzColorPath].u, v->reg[alphaMode].u, v->reg[fogMode].u,
	3335	PIXEL_PIPELINE_END(vd, stats, dither, dither4, dither_lookup, x, dest, depth,
	3336	vd->reg[fbzMode].u, vd->reg[fbzColorPath].u, vd->reg[alphaMode].u, vd->reg[fogMode].u,
3398	3337	iterz, iterw, iterargb) {};
3399	3338	nextpixel:
3400	3339	/* advance our pointers */
r253153	r253154
3414	3353	*
3415	3354	*************************************/
3416	3355
3417		~~static~~ INT32 texture_w(voodoo_~~stat~~e *v, offs_t offset, UINT32 data)
	3356	INT32 voodoo_device::texture_w(voodoo_device *vd, offs_t offset, UINT32 data)
3418	3357	{
3419	3358	int tmunum = (offset >> 19) & 0x03;
3420	3359	tmu_state *t;
3421	3360
3422	3361	/* statistics */
3423		v->stats.tex_writes++;
	3362	vd->stats.tex_writes++;
3424	3363
3425	3364	/* point to the right TMU */
3426		if (!(v->chipmask & (2 << tmunum)))
	3365	if (!(vd->chipmask & (2 << tmunum)))
3427	3366	return 0;
3428		t = &v->tmu[tmunum];
	3367	t = &vd->tmu[tmunum];
3429	3368
3430	3369	if (TEXLOD_TDIRECT_WRITE(t->reg[tLOD].u))
3431	3370	fatalerror("Texture direct write!\n");
3432	3371
3433	3372	/* wait for any outstanding work to finish */
3434		poly_wait(v->poly, "Texture write");
	3373	poly_wait(vd->poly, "Texture write");
3435	3374
3436	3375	/* update texture info if dirty */
3437	3376	if (t->regdirty)
r253153	r253154
3451	3390	UINT8 *dest;
3452	3391
3453	3392	/* extract info */
3454		if (v->type <= TYPE_VOODOO_2)
	3393	if (vd->vd_type <= TYPE_VOODOO_2)
3455	3394	{
3456	3395	lod = (offset >> 15) & 0x0f;
3457	3396	tt = (offset >> 7) & 0xff;
3458	3397
3459	3398	/* old code has a bit about how this is broken in gauntleg unless we always look at TMU0 */
3460		if (TEXMODE_SEQ_8_DOWNLD(v->tmu[0].reg/t->reg/[textureMode].u))
	3399	if (TEXMODE_SEQ_8_DOWNLD(vd->tmu[0].reg/t->reg/[textureMode].u))
3461	3400	ts = (offset << 2) & 0xfc;
3462	3401	else
3463	3402	ts = (offset << 1) & 0xfc;
r253153	r253154
3470	3409	tbaseaddr = t->lodoffset[lod];
3471	3410	tbaseaddr += tt * ((t->wmask >> lod) + 1) + ts;
3472	3411
3473		if (LOG_TEXTURE_RAM) v->device->logerror("Texture 8-bit w: lod=%d s=%d t=%d data=%08X\n", lod, ts, tt, data);
	3412	if (LOG_TEXTURE_RAM) vd->device->logerror("Texture 8-bit w: lod=%d s=%d t=%d data=%08X\n", lod, ts, tt, data);
3474	3413	}
3475	3414	else
3476	3415	{
3477	3416	tbaseaddr = t->lodoffset[0] + offset*4;
3478	3417
3479		if (LOG_TEXTURE_RAM) v->device->logerror("Texture 8-bit w: offset=%X data=%08X\n", offset*4, data);
	3418	if (LOG_TEXTURE_RAM) vd->device->logerror("Texture 8-bit w: offset=%X data=%08X\n", offset*4, data);
3480	3419	}
3481	3420
3482	3421	/* write the four bytes in little-endian order */
r253153	r253154
3496	3435	UINT16 *dest;
3497	3436
3498	3437	/* extract info */
3499		if (v->type <= TYPE_VOODOO_2)
	3438	if (vd->vd_type <= TYPE_VOODOO_2)
3500	3439	{
3501	3440	lod = (offset >> 15) & 0x0f;
3502	3441	tt = (offset >> 7) & 0xff;
r253153	r253154
3510	3449	tbaseaddr = t->lodoffset[lod];
3511	3450	tbaseaddr += 2 * (tt * ((t->wmask >> lod) + 1) + ts);
3512	3451
3513		if (LOG_TEXTURE_RAM) v->device->logerror("Texture 16-bit w: lod=%d s=%d t=%d data=%08X\n", lod, ts, tt, data);
	3452	if (LOG_TEXTURE_RAM) vd->device->logerror("Texture 16-bit w: lod=%d s=%d t=%d data=%08X\n", lod, ts, tt, data);
3514	3453	}
3515	3454	else
3516	3455	{
3517	3456	tbaseaddr = t->lodoffset[0] + offset*4;
3518	3457
3519		if (LOG_TEXTURE_RAM) v->device->logerror("Texture 16-bit w: offset=%X data=%08X\n", offset*4, data);
	3458	if (LOG_TEXTURE_RAM) vd->device->logerror("Texture 16-bit w: offset=%X data=%08X\n", offset*4, data);
3520	3459	}
3521	3460
3522	3461	/* write the two words in little-endian order */
r253153	r253154
3538	3477	*
3539	3478	*************************************/
3540	3479
3541		~~static~~ void flush_fifos(voodoo_~~stat~~e *v, attotime current_time)
	3480	void voodoo_device::flush_fifos(voodoo_device *vd, attotime current_time)
3542	3481	{
3543	3482	static UINT8 in_flush;
3544	3483
r253153	r253154
3547	3486	return;
3548	3487	in_flush = TRUE;
3549	3488
3550		if (!v->pci.op_pending) fatalerror("flush_fifos called with no pending operation\n");
	3489	if (!vd->pci.op_pending) fatalerror("flush_fifos called with no pending operation\n");
3551	3490
3552		if (LOG_FIFO_VERBOSE) v->device->logerror("VOODOO.%d.FIFO:flush_fifos start -- pending=%d.%08X%08X cur=%d.%08X%08X\n", v->index,
3553		v->pci.op_end_time.seconds(), (UINT32)(v->pci.op_end_time.attoseconds() >> 32), (UINT32)v->pci.op_end_time.attoseconds(),
	3491	if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:flush_fifos start -- pending=%d.%08X%08X cur=%d.%08X%08X\n", vd->index,
	3492	vd->pci.op_end_time.seconds(), (UINT32)(vd->pci.op_end_time.attoseconds() >> 32), (UINT32)vd->pci.op_end_time.attoseconds(),
3554	3493	current_time.seconds(), (UINT32)(current_time.attoseconds() >> 32), (UINT32)current_time.attoseconds());
3555	3494
3556	3495	/* loop while we still have cycles to burn */
3557		while (v->pci.op_end_time <= current_time)
	3496	while (vd->pci.op_end_time <= current_time)
3558	3497	{
3559	3498	INT32 extra_cycles = 0;
3560	3499	INT32 cycles;
r253153	r253154
3567	3506	UINT32 data;
3568	3507
3569	3508	/* we might be in CMDFIFO mode */
3570		if (v->fbi.cmdfifo[0].enable)
	3509	if (vd->fbi.cmdfifo[0].enable)
3571	3510	{
3572	3511	/* if we don't have anything to execute, we're done for now */
3573		cycles = cmdfifo_execute_if_ready(v, &v->fbi.cmdfifo[0]);
	3512	cycles = cmdfifo_execute_if_ready(vd, &vd->fbi.cmdfifo[0]);
3574	3513	if (cycles == -1)
3575	3514	{
3576		v->pci.op_pending = FALSE;
	3515	vd->pci.op_pending = FALSE;
3577	3516	in_flush = FALSE;
3578		if (LOG_FIFO_VERBOSE) v->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- CMDFIFO empty\n", v->index);
	3517	if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- CMDFIFO empty\n", vd->index);
3579	3518	return;
3580	3519	}
3581	3520	}
3582		else if (v->fbi.cmdfifo[1].enable)
	3521	else if (vd->fbi.cmdfifo[1].enable)
3583	3522	{
3584	3523	/* if we don't have anything to execute, we're done for now */
3585		cycles = cmdfifo_execute_if_ready(v, &v->fbi.cmdfifo[1]);
	3524	cycles = cmdfifo_execute_if_ready(vd, &vd->fbi.cmdfifo[1]);
3586	3525	if (cycles == -1)
3587	3526	{
3588		v->pci.op_pending = FALSE;
	3527	vd->pci.op_pending = FALSE;
3589	3528	in_flush = FALSE;
3590		if (LOG_FIFO_VERBOSE) v->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- CMDFIFO empty\n", v->index);
	3529	if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- CMDFIFO empty\n", vd->index);
3591	3530	return;
3592	3531	}
3593	3532	}
r253153	r253154
3596	3535	else
3597	3536	{
3598	3537	/* choose which FIFO to read from */
3599		if (!fifo_empty(&v->fbi.fifo))
3600		fifo = &v->fbi.fifo;
3601		else if (!fifo_empty(&v->pci.fifo))
3602		fifo = &v->pci.fifo;
	3538	if (!fifo_empty(&vd->fbi.fifo))
	3539	fifo = &vd->fbi.fifo;
	3540	else if (!fifo_empty(&vd->pci.fifo))
	3541	fifo = &vd->pci.fifo;
3603	3542	else
3604	3543	{
3605		v->pci.op_pending = FALSE;
	3544	vd->pci.op_pending = FALSE;
3606	3545	in_flush = FALSE;
3607		if (LOG_FIFO_VERBOSE) v->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- FIFOs empty\n", v->index);
	3546	if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- FIFOs empty\n", vd->index);
3608	3547	return;
3609	3548	}
3610	3549
r253153	r253154
3614	3553
3615	3554	/* target the appropriate location */
3616	3555	if ((address & (0xc00000/4)) == 0)
3617		cycles = register_w(v, address, data);
	3556	cycles = register_w(vd, address, data);
3618	3557	else if (address & (0x800000/4))
3619		cycles = texture_w(v, address, data);
	3558	cycles = texture_w(vd, address, data);
3620	3559	else
3621	3560	{
3622	3561	UINT32 mem_mask = 0xffffffff;
r253153	r253154
3628	3567	mem_mask &= 0xffff0000;
3629	3568	address &= 0xffffff;
3630	3569
3631		cycles = lfb_w(v, address, data, mem_mask);
	3570	cycles = lfb_w(vd, address, data, mem_mask);
3632	3571	}
3633	3572	}
3634	3573
r253153	r253154
3645	3584	cycles += extra_cycles;
3646	3585
3647	3586	/* account for those cycles */
3648		v->pci.op_end_time += attotime(0, (attoseconds_t)cycles * v->attoseconds_per_cycle);
	3587	vd->pci.op_end_time += attotime(0, (attoseconds_t)cycles * vd->attoseconds_per_cycle);
3649	3588
3650		if (LOG_FIFO_VERBOSE) v->device->logerror("VOODOO.%d.FIFO:update -- pending=%d.%08X%08X cur=%d.%08X%08X\n", v->index,
3651		v->pci.op_end_time.seconds(), (UINT32)(v->pci.op_end_time.attoseconds() >> 32), (UINT32)v->pci.op_end_time.attoseconds(),
	3589	if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:update -- pending=%d.%08X%08X cur=%d.%08X%08X\n", vd->index,
	3590	vd->pci.op_end_time.seconds(), (UINT32)(vd->pci.op_end_time.attoseconds() >> 32), (UINT32)vd->pci.op_end_time.attoseconds(),
3652	3591	current_time.seconds(), (UINT32)(current_time.attoseconds() >> 32), (UINT32)current_time.attoseconds());
3653	3592	}
3654	3593
3655		if (LOG_FIFO_VERBOSE) v->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- pending command complete at %d.%08X%08X\n", v->index,
3656		v->pci.op_end_time.seconds(), (UINT32)(v->pci.op_end_time.attoseconds() >> 32), (UINT32)v->pci.op_end_time.attoseconds());
	3594	if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- pending command complete at %d.%08X%08X\n", vd->index,
	3595	vd->pci.op_end_time.seconds(), (UINT32)(vd->pci.op_end_time.attoseconds() >> 32), (UINT32)vd->pci.op_end_time.attoseconds());
3657	3596
3658	3597	in_flush = FALSE;
3659	3598	}
r253153	r253154
3669	3608
3670	3609	WRITE32_MEMBER( voodoo_device::voodoo_w )
3671	3610	{
3672		voodoo_state *v = get_safe_token(this);
3673	3611	int stall = FALSE;
3674	3612
3675	3613	g_profiler.start(PROFILER_USER1);
3676	3614
3677	3615	/* should not be getting accesses while stalled */
3678		if (~~v->~~pci.stall_state != NOT_STALLED)
	3616	if (pci.stall_state != NOT_STALLED)
3679	3617	logerror("voodoo_w while stalled!\n");
3680	3618
3681	3619	/* if we have something pending, flush the FIFOs up to the current time */
3682		if (v->pci.op_pending)
3683		flush_fifos(v, machine().time());
	3620	if (pci.op_pending)
	3621	flush_fifos(this, machine().time());
3684	3622
3685	3623	/* special handling for registers */
3686	3624	if ((offset & 0xc00000/4) == 0)
r253153	r253154
3688	3626	UINT8 access;
3689	3627
3690	3628	/* some special stuff for Voodoo 2 */
3691		if (v->type >= TYPE_VOODOO_2)
	3629	if (vd_type >= TYPE_VOODOO_2)
3692	3630	{
3693	3631	/* we might be in CMDFIFO mode */
3694		if (FBIINIT7_CMDFIFO_ENABLE(~~v->~~reg[fbiInit7].u))
	3632	if (FBIINIT7_CMDFIFO_ENABLE(reg[fbiInit7].u))
3695	3633	{
3696	3634	/* if bit 21 is set, we're writing to the FIFO */
3697	3635	if (offset & 0x200000/4)
r253153	r253154
3699	3637	/* check for byte swizzling (bit 18) */
3700	3638	if (offset & 0x40000/4)
3701	3639	data = FLIPENDIAN_INT32(data);
3702		cmdfifo_w(v, &~~v->~~fbi.cmdfifo[0], offset & 0xffff, data);
	3640	cmdfifo_w(this, &fbi.cmdfifo[0], offset & 0xffff, data);
3703	3641	g_profiler.stop();
3704	3642	return;
3705	3643	}
3706	3644
3707	3645	/* we're a register access; but only certain ones are allowed */
3708		access = ~~v->~~regaccess[offset & 0xff];
	3646	access = regaccess[offset & 0xff];
3709	3647	if (!(access & REGISTER_WRITETHRU))
3710	3648	{
3711	3649	/* track swap buffers regardless */
3712	3650	if ((offset & 0xff) == swapbufferCMD)
3713		~~v->~~fbi.swaps_pending++;
	3651	fbi.swaps_pending++;
3714	3652
3715		logerror("Ignoring write to %s in CMDFIFO mode\n", ~~v->~~regnames[offset & 0xff]);
	3653	logerror("Ignoring write to %s in CMDFIFO mode\n", regnames[offset & 0xff]);
3716	3654	g_profiler.stop();
3717	3655	return;
3718	3656	}
r253153	r253154
3725	3663
3726	3664	/* check the access behavior; note that the table works even if the */
3727	3665	/* alternate mapping is used */
3728		access = ~~v->~~regaccess[offset & 0xff];
	3666	access = regaccess[offset & 0xff];
3729	3667
3730	3668	/* ignore if writes aren't allowed */
3731	3669	if (!(access & REGISTER_WRITE))
r253153	r253154
3740	3678
3741	3679	/* track swap buffers */
3742	3680	if ((offset & 0xff) == swapbufferCMD)
3743		~~v->~~fbi.swaps_pending++;
	3681	fbi.swaps_pending++;
3744	3682	}
3745	3683
3746	3684	/* if we don't have anything pending, or if FIFOs are disabled, just execute */
3747		if (!~~v->~~pci.op_pending \|\| !INITEN_ENABLE_PCI_FIFO(~~v->~~pci.init_enable))
	3685	if (!pci.op_pending \|\| !INITEN_ENABLE_PCI_FIFO(pci.init_enable))
3748	3686	{
3749	3687	int cycles;
3750	3688
3751	3689	/* target the appropriate location */
3752	3690	if ((offset & (0xc00000/4)) == 0)
3753		cycles = register_w(v, offset, data);
	3691	cycles = register_w(this, offset, data);
3754	3692	else if (offset & (0x800000/4))
3755		cycles = texture_w(v, offset, data);
	3693	cycles = texture_w(this, offset, data);
3756	3694	else
3757		cycles = lfb_w(v, offset, data, mem_mask);
	3695	cycles = lfb_w(this, offset, data, mem_mask);
3758	3696
3759	3697	/* if we ended up with cycles, mark the operation pending */
3760	3698	if (cycles)
3761	3699	{
3762		v->pci.op_pending = TRUE;
3763		v->pci.op_end_time = machine().time() + attotime(0, (attoseconds_t)cycles * v->attoseconds_per_cycle);
	3700	pci.op_pending = TRUE;
	3701	pci.op_end_time = machine().time() + attotime(0, (attoseconds_t)cycles * attoseconds_per_cycle);
3764	3702
3765		if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:direct write start at %d.%08X%08X end at %d.%08X%08X\n", ~~v->~~index,
	3703	if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:direct write start at %d.%08X%08X end at %d.%08X%08X\n", index,
3766	3704	machine().time().seconds(), (UINT32)(machine().time().attoseconds() >> 32), (UINT32)machine().time().attoseconds(),
3767		~~v->~~pci.op_end_time.seconds(), (UINT32)(~~v->~~pci.op_end_time.attoseconds() >> 32), (UINT32)~~v->~~pci.op_end_time.attoseconds());
	3705	pci.op_end_time.seconds(), (UINT32)(pci.op_end_time.attoseconds() >> 32), (UINT32)pci.op_end_time.attoseconds());
3768	3706	}
3769	3707	g_profiler.stop();
3770	3708	return;
r253153	r253154
3780	3718	}
3781	3719
3782	3720	/* if there's room in the PCI FIFO, add there */
3783		if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:voodoo_w adding to PCI FIFO @ %08X=%08X\n", v->index, offset, data);
3784		if (!fifo_full(&v->pci.fifo))
	3721	if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:voodoo_w adding to PCI FIFO @ %08X=%08X\n", this, offset, data);
	3722	if (!fifo_full(&pci.fifo))
3785	3723	{
3786		fifo_add(&v->pci.fifo, offset);
3787		fifo_add(&v->pci.fifo, data);
	3724	fifo_add(&pci.fifo, offset);
	3725	fifo_add(&pci.fifo, data);
3788	3726	}
3789	3727	else
3790	3728	fatalerror("PCI FIFO full\n");
3791	3729
3792	3730	/* handle flushing to the memory FIFO */
3793		if (FBIINIT0_ENABLE_MEMORY_FIFO(v->reg[fbiInit0].u) &&
3794		fifo_space(&v->pci.fifo) <= 2 * FBIINIT4_MEMORY_FIFO_LWM(v->reg[fbiInit4].u))
	3731	if (FBIINIT0_ENABLE_MEMORY_FIFO(reg[fbiInit0].u) &&
	3732	fifo_space(&pci.fifo) <= 2 * FBIINIT4_MEMORY_FIFO_LWM(reg[fbiInit4].u))
3795	3733	{
3796	3734	UINT8 valid[4];
3797	3735
3798	3736	/* determine which types of data can go to the memory FIFO */
3799	3737	valid[0] = TRUE;
3800		valid[1] = FBIINIT0_LFB_TO_MEMORY_FIFO(v->reg[fbiInit0].u);
3801		valid[2] = valid[3] = FBIINIT0_TEXMEM_TO_MEMORY_FIFO(v->reg[fbiInit0].u);
	3738	valid[1] = FBIINIT0_LFB_TO_MEMORY_FIFO(reg[fbiInit0].u);
	3739	valid[2] = valid[3] = FBIINIT0_TEXMEM_TO_MEMORY_FIFO(reg[fbiInit0].u);
3802	3740
3803	3741	/* flush everything we can */
3804		if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:voodoo_w moving PCI FIFO to memory FIFO\n", v->index);
3805		while (!fifo_empty(&v->pci.fifo) && valid[(fifo_peek(&v->pci.fifo) >> 22) & 3])
	3742	if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:voodoo_w moving PCI FIFO to memory FIFO\n", index);
	3743	while (!fifo_empty(&pci.fifo) && valid[(fifo_peek(&pci.fifo) >> 22) & 3])
3806	3744	{
3807		fifo_add(&v->fbi.fifo, fifo_remove(&v->pci.fifo));
3808		fifo_add(&v->fbi.fifo, fifo_remove(&v->pci.fifo));
	3745	fifo_add(&fbi.fifo, fifo_remove(&pci.fifo));
	3746	fifo_add(&fbi.fifo, fifo_remove(&pci.fifo));
3809	3747	}
3810	3748
3811	3749	/* if we're above the HWM as a result, stall */
3812		if (FBIINIT0_STALL_PCIE_FOR_HWM(v->reg[fbiInit0].u) &&
3813		fifo_items(&v->fbi.fifo) >= 2 * 32 * FBIINIT0_MEMORY_FIFO_HWM(v->reg[fbiInit0].u))
	3750	if (FBIINIT0_STALL_PCIE_FOR_HWM(reg[fbiInit0].u) &&
	3751	fifo_items(&fbi.fifo) >= 2 * 32 * FBIINIT0_MEMORY_FIFO_HWM(reg[fbiInit0].u))
3814	3752	{
3815		if (LOG_FIFO) logerror("VOODOO.%d.FIFO:voodoo_w hit memory FIFO HWM -- stalling\n", v->index);
3816		stall_cpu(v, STALLED_UNTIL_FIFO_LWM, machine().time());
	3753	if (LOG_FIFO) logerror("VOODOO.%d.FIFO:voodoo_w hit memory FIFO HWM -- stalling\n", index);
	3754	stall_cpu(this, STALLED_UNTIL_FIFO_LWM, machine().time());
3817	3755	}
3818	3756	}
3819	3757
3820	3758	/* if we're at the LWM for the PCI FIFO, stall */
3821		if (FBIINIT0_STALL_PCIE_FOR_HWM(v->reg[fbiInit0].u) &&
3822		fifo_space(&v->pci.fifo) <= 2 * FBIINIT0_PCI_FIFO_LWM(v->reg[fbiInit0].u))
	3759	if (FBIINIT0_STALL_PCIE_FOR_HWM(reg[fbiInit0].u) &&
	3760	fifo_space(&pci.fifo) <= 2 * FBIINIT0_PCI_FIFO_LWM(reg[fbiInit0].u))
3823	3761	{
3824		if (LOG_FIFO) logerror("VOODOO.%d.FIFO:voodoo_w hit PCI FIFO free LWM -- stalling\n", v->index);
3825		stall_cpu(v, STALLED_UNTIL_FIFO_LWM, machine().time());
	3762	if (LOG_FIFO) logerror("VOODOO.%d.FIFO:voodoo_w hit PCI FIFO free LWM -- stalling\n", index);
	3763	stall_cpu(this, STALLED_UNTIL_FIFO_LWM, machine().time());
3826	3764	}
3827	3765
3828	3766	/* if we weren't ready, and this is a non-FIFO access, stall until the FIFOs are clear */
3829	3767	if (stall)
3830	3768	{
3831		if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:voodoo_w wrote non-FIFO register -- stalling until clear\n", v->index);
3832		stall_cpu(v, STALLED_UNTIL_FIFO_EMPTY, machine().time());
	3769	if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:voodoo_w wrote non-FIFO register -- stalling until clear\n", index);
	3770	stall_cpu(this, STALLED_UNTIL_FIFO_EMPTY, machine().time());
3833	3771	}
3834	3772
3835	3773	g_profiler.stop();
r253153	r253154
3843	3781	*
3844	3782	*************************************/
3845	3783
3846		static UINT32 register_r(voodoo_~~stat~~e *v, offs_t offset)
	3784	static UINT32 register_r(voodoo_device *vd, offs_t offset)
3847	3785	{
	3786
3848	3787	int regnum = offset & 0xff;
3849	3788	UINT32 result;
3850	3789
3851	3790	/* statistics */
3852		v->stats.reg_reads++;
	3791	vd->stats.reg_reads++;
3853	3792
3854	3793	/* first make sure this register is readable */
3855		if (!(v->regaccess[regnum] & REGISTER_READ))
	3794	if (!(vd->regaccess[regnum] & REGISTER_READ))
3856	3795	{
3857		v->device->logerror("VOODOO.%d.ERROR:Invalid attempt to read %s\n", v->index, regnum < 225 ? v->regnames[regnum] : "unknown register");
	3796	vd->device->logerror("VOODOO.%d.ERROR:Invalid attempt to read %s\n", vd->index, regnum < 225 ? vd->regnames[regnum] : "unknown register");
3858	3797	return 0xffffffff;
3859	3798	}
3860	3799
3861	3800	/* default result is the FBI register value */
3862		result = v->reg[regnum].u;
	3801	result = vd->reg[regnum].u;
3863	3802
3864	3803	/* some registers are dynamic; compute them */
3865	3804	switch (regnum)
3866	3805	{
3867		case status:
	3806	case vdstatus:
3868	3807
3869	3808	/* start with a blank slate */
3870	3809	result = 0;
3871	3810
3872	3811	/* bits 5:0 are the PCI FIFO free space */
3873		if (fifo_empty(&v->pci.fifo))
	3812	if (fifo_empty(&vd->pci.fifo))
3874	3813	result \|= 0x3f << 0;
3875	3814	else
3876	3815	{
3877		int temp = fifo_space(&v->pci.fifo)/2;
	3816	int temp = fifo_space(&vd->pci.fifo)/2;
3878	3817	if (temp > 0x3f)
3879	3818	temp = 0x3f;
3880	3819	result \|= temp << 0;
3881	3820	}
3882	3821
3883	3822	/* bit 6 is the vertical retrace */
3884		result \|= v->fbi.vblank << 6;
	3823	result \|= vd->fbi.vblank << 6;
3885	3824
3886	3825	/* bit 7 is FBI graphics engine busy */
3887		if (v->pci.op_pending)
	3826	if (vd->pci.op_pending)
3888	3827	result \|= 1 << 7;
3889	3828
3890	3829	/* bit 8 is TREX busy */
3891		if (v->pci.op_pending)
	3830	if (vd->pci.op_pending)
3892	3831	result \|= 1 << 8;
3893	3832
3894	3833	/* bit 9 is overall busy */
3895		if (v->pci.op_pending)
	3834	if (vd->pci.op_pending)
3896	3835	result \|= 1 << 9;
3897	3836
3898	3837	/* Banshee is different starting here */
3899		if (v->type < TYPE_VOODOO_BANSHEE)
	3838	if (vd->vd_type < TYPE_VOODOO_BANSHEE)
3900	3839	{
3901	3840	/* bits 11:10 specifies which buffer is visible */
3902		result \|= v->fbi.frontbuf << 10;
	3841	result \|= vd->fbi.frontbuf << 10;
3903	3842
3904	3843	/* bits 27:12 indicate memory FIFO freespace */
3905		if (!FBIINIT0_ENABLE_MEMORY_FIFO(v->reg[fbiInit0].u) \|\| fifo_empty(&v->fbi.fifo))
	3844	if (!FBIINIT0_ENABLE_MEMORY_FIFO(vd->reg[fbiInit0].u) \|\| fifo_empty(&vd->fbi.fifo))
3906	3845	result \|= 0xffff << 12;
3907	3846	else
3908	3847	{
3909		int temp = fifo_space(&v->fbi.fifo)/2;
	3848	int temp = fifo_space(&vd->fbi.fifo)/2;
3910	3849	if (temp > 0xffff)
3911	3850	temp = 0xffff;
3912	3851	result \|= temp << 12;
r253153	r253154
3917	3856	/* bit 10 is 2D busy */
3918	3857
3919	3858	/* bit 11 is cmd FIFO 0 busy */
3920		if (v->fbi.cmdfifo[0].enable && v->fbi.cmdfifo[0].depth > 0)
	3859	if (vd->fbi.cmdfifo[0].enable && vd->fbi.cmdfifo[0].depth > 0)
3921	3860	result \|= 1 << 11;
3922	3861
3923	3862	/* bit 12 is cmd FIFO 1 busy */
3924		if (v->fbi.cmdfifo[1].enable && v->fbi.cmdfifo[1].depth > 0)
	3863	if (vd->fbi.cmdfifo[1].enable && vd->fbi.cmdfifo[1].depth > 0)
3925	3864	result \|= 1 << 12;
3926	3865	}
3927	3866
3928	3867	/* bits 30:28 are the number of pending swaps */
3929		if (v->fbi.swaps_pending > 7)
	3868	if (vd->fbi.swaps_pending > 7)
3930	3869	result \|= 7 << 28;
3931	3870	else
3932		result \|= v->fbi.swaps_pending << 28;
	3871	result \|= vd->fbi.swaps_pending << 28;
3933	3872
3934	3873	/* bit 31 is not used */
3935	3874
3936	3875	/* eat some cycles since people like polling here */
3937		if (EAT_CYCLES) v->cpu->execute().eat_cycles(1000);
	3876	if (EAT_CYCLES) vd->cpu->execute().eat_cycles(1000);
3938	3877	break;
3939	3878
3940	3879	/* bit 2 of the initEnable register maps this to dacRead */
3941	3880	case fbiInit2:
3942		if (INITEN_REMAP_INIT_TO_DAC(v->pci.init_enable))
3943		result = v->dac.read_result;
	3881	if (INITEN_REMAP_INIT_TO_DAC(vd->pci.init_enable))
	3882	result = vd->dac.read_result;
3944	3883	break;
3945	3884
3946	3885	/* return the current scanline for now */
3947	3886	case vRetrace:
3948	3887
3949	3888	/* eat some cycles since people like polling here */
3950		if (EAT_CYCLES) v->cpu->execute().eat_cycles(10);
3951		result = v->screen->vpos();
	3889	if (EAT_CYCLES) vd->cpu->execute().eat_cycles(10);
	3890	result = vd->screen->vpos();
3952	3891	break;
3953	3892
3954	3893	/* reserved area in the TMU read by the Vegas startup sequence */
r253153	r253154
3959	3898
3960	3899	/* cmdFifo -- Voodoo2 only */
3961	3900	case cmdFifoRdPtr:
3962		result = v->fbi.cmdfifo[0].rdptr;
	3901	result = vd->fbi.cmdfifo[0].rdptr;
3963	3902
3964	3903	/* eat some cycles since people like polling here */
3965		if (EAT_CYCLES) v->cpu->execute().eat_cycles(1000);
	3904	if (EAT_CYCLES) vd->cpu->execute().eat_cycles(1000);
3966	3905	break;
3967	3906
3968	3907	case cmdFifoAMin:
3969		result = v->fbi.cmdfifo[0].amin;
	3908	result = vd->fbi.cmdfifo[0].amin;
3970	3909	break;
3971	3910
3972	3911	case cmdFifoAMax:
3973		result = v->fbi.cmdfifo[0].amax;
	3912	result = vd->fbi.cmdfifo[0].amax;
3974	3913	break;
3975	3914
3976	3915	case cmdFifoDepth:
3977		result = v->fbi.cmdfifo[0].depth;
	3916	result = vd->fbi.cmdfifo[0].depth;
3978	3917	break;
3979	3918
3980	3919	case cmdFifoHoles:
3981		result = v->fbi.cmdfifo[0].holes;
	3920	result = vd->fbi.cmdfifo[0].holes;
3982	3921	break;
3983	3922
3984	3923	/* all counters are 24-bit only */
r253153	r253154
3987	3926	case fbiZfuncFail:
3988	3927	case fbiAfuncFail:
3989	3928	case fbiPixelsOut:
3990		update_statistics(v, TRUE);
	3929	update_statistics(vd, TRUE);
3991	3930	case fbiTrianglesOut:
3992		result = v->reg[regnum].u & 0xffffff;
	3931	result = vd->reg[regnum].u & 0xffffff;
3993	3932	break;
3994	3933	}
3995	3934
r253153	r253154
3998	3937	int logit = TRUE;
3999	3938
4000	3939	/* don't log multiple identical status reads from the same address */
4001		if (regnum == status)
	3940	if (regnum == vdstatus)
4002	3941	{
4003		offs_t pc = v->cpu->safe_pc();
4004		if (pc == v->last_status_pc && result == v->last_status_value)
	3942	offs_t pc = vd->cpu->safe_pc();
	3943	if (pc == vd->last_status_pc && result == vd->last_status_value)
4005	3944	logit = FALSE;
4006		v->last_status_pc = pc;
4007		v->last_status_value = result;
	3945	vd->last_status_pc = pc;
	3946	vd->last_status_value = result;
4008	3947	}
4009	3948	if (regnum == cmdFifoRdPtr)
4010	3949	logit = FALSE;
4011	3950
4012	3951	if (logit)
4013		v->device->logerror("VOODOO.%d.REG:%s read = %08X\n", v->index, v->regnames[regnum], result);
	3952	vd->device->logerror("VOODOO.%d.REG:%s read = %08X\n", vd->index, vd->regnames[regnum], result);
4014	3953	}
4015	3954
4016	3955	return result;
r253153	r253154
4024	3963	*
4025	3964	*************************************/
4026	3965
4027		static UINT32 lfb_r(voodoo_~~stat~~e *v, offs_t offset, bool lfb_3d)
	3966	static UINT32 lfb_r(voodoo_device *vd, offs_t offset, bool lfb_3d)
4028	3967	{
4029	3968	UINT16 *buffer;
4030	3969	UINT32 bufmax;
r253153	r253154
4033	3972	int x, y, scry, destbuf;
4034	3973
4035	3974	/* statistics */
4036		v->stats.lfb_reads++;
	3975	vd->stats.lfb_reads++;
4037	3976
4038	3977	/* compute X,Y */
4039	3978	offset <<= 1;
4040		x = offset & ((1 << v->fbi.lfb_stride) - 1);
4041		y = (offset >> v->fbi.lfb_stride);
	3979	x = offset & ((1 << vd->fbi.lfb_stride) - 1);
	3980	y = (offset >> vd->fbi.lfb_stride);
4042	3981
4043	3982	/* select the target buffer */
4044	3983	if (lfb_3d) {
4045	3984	y &= 0x3ff;
4046		destbuf = (v->type >= TYPE_VOODOO_BANSHEE) ? 1 : LFBMODE_READ_BUFFER_SELECT(v->reg[lfbMode].u);
	3985	destbuf = (vd->vd_type >= TYPE_VOODOO_BANSHEE) ? 1 : LFBMODE_READ_BUFFER_SELECT(vd->reg[lfbMode].u);
4047	3986	switch (destbuf)
4048	3987	{
4049	3988	case 0: /* front buffer */
4050		buffer = (UINT16 *)(v->fbi.ram + v->fbi.rgboffs[v->fbi.frontbuf]);
4051		bufmax = (v->fbi.mask + 1 - v->fbi.rgboffs[v->fbi.frontbuf]) / 2;
	3989	buffer = (UINT16 *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.frontbuf]);
	3990	bufmax = (vd->fbi.mask + 1 - vd->fbi.rgboffs[vd->fbi.frontbuf]) / 2;
4052	3991	break;
4053	3992
4054	3993	case 1: /* back buffer */
4055		buffer = (UINT16 *)(v->fbi.ram + v->fbi.rgboffs[v->fbi.backbuf]);
4056		bufmax = (v->fbi.mask + 1 - v->fbi.rgboffs[v->fbi.backbuf]) / 2;
	3994	buffer = (UINT16 *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.backbuf]);
	3995	bufmax = (vd->fbi.mask + 1 - vd->fbi.rgboffs[vd->fbi.backbuf]) / 2;
4057	3996	break;
4058	3997
4059	3998	case 2: /* aux buffer */
4060		if (v->fbi.auxoffs == ~0)
	3999	if (vd->fbi.auxoffs == ~0)
4061	4000	return 0xffffffff;
4062		buffer = (UINT16 *)(v->fbi.ram + v->fbi.auxoffs);
4063		bufmax = (v->fbi.mask + 1 - v->fbi.auxoffs) / 2;
	4001	buffer = (UINT16 *)(vd->fbi.ram + vd->fbi.auxoffs);
	4002	bufmax = (vd->fbi.mask + 1 - vd->fbi.auxoffs) / 2;
4064	4003	break;
4065	4004
4066	4005	default: /* reserved */
r253153	r253154
4069	4008
4070	4009	/* determine the screen Y */
4071	4010	scry = y;
4072		if (LFBMODE_Y_ORIGIN(v->reg[lfbMode].u))
4073		scry = (v->fbi.yorigin - y) & 0x3ff;
	4011	if (LFBMODE_Y_ORIGIN(vd->reg[lfbMode].u))
	4012	scry = (vd->fbi.yorigin - y) & 0x3ff;
4074	4013	} else {
4075	4014	// Direct lfb access
4076		buffer = (UINT16 )(v->fbi.ram + v->fbi.lfb_base4);
4077		bufmax = (v->fbi.mask + 1 - v->fbi.lfb_base*4) / 2;
	4015	buffer = (UINT16 )(vd->fbi.ram + vd->fbi.lfb_base4);
	4016	bufmax = (vd->fbi.mask + 1 - vd->fbi.lfb_base*4) / 2;
4078	4017	scry = y;
4079	4018	}
4080	4019
4081	4020	/* advance pointers to the proper row */
4082		bufoffs = scry * v->fbi.rowpixels + x;
	4021	bufoffs = scry * vd->fbi.rowpixels + x;
4083	4022	if (bufoffs >= bufmax) {
4084		v->device->logerror("LFB_R: Buffer offset out of bounds x=%i y=%i lfb_3d=%i offset=%08X bufoffs=%08X\n", x, y, lfb_3d, offset, (UINT32) bufoffs);
	4023	vd->device->logerror("LFB_R: Buffer offset out of bounds x=%i y=%i lfb_3d=%i offset=%08X bufoffs=%08X\n", x, y, lfb_3d, offset, (UINT32) bufoffs);
4085	4024	return 0xffffffff;
4086	4025	}
4087	4026
4088	4027	/* wait for any outstanding work to finish */
4089		poly_wait(v->poly, "LFB read");
	4028	poly_wait(vd->poly, "LFB read");
4090	4029
4091	4030	/* compute the data */
4092	4031	data = buffer[bufoffs + 0] \| (buffer[bufoffs + 1] << 16);
4093	4032
4094	4033	/* word swapping */
4095		if (LFBMODE_WORD_SWAP_READS(v->reg[lfbMode].u))
	4034	if (LFBMODE_WORD_SWAP_READS(vd->reg[lfbMode].u))
4096	4035	data = (data << 16) \| (data >> 16);
4097	4036
4098	4037	/* byte swizzling */
4099		if (LFBMODE_BYTE_SWIZZLE_READS(v->reg[lfbMode].u))
	4038	if (LFBMODE_BYTE_SWIZZLE_READS(vd->reg[lfbMode].u))
4100	4039	data = FLIPENDIAN_INT32(data);
4101	4040
4102		if (LOG_LFB) v->device->logerror("VOODOO.%d.LFB:read (%d,%d) = %08X\n", v->index, x, y, data);
	4041	if (LOG_LFB) vd->device->logerror("VOODOO.%d.LFB:read (%d,%d) = %08X\n", vd->index, x, y, data);
4103	4042	return data;
4104	4043	}
4105	4044
r253153	r253154
4114	4053
4115	4054	READ32_MEMBER( voodoo_device::voodoo_r )
4116	4055	{
4117		voodoo_state *v = get_safe_token(this);
4118	4056
4119	4057	/* if we have something pending, flush the FIFOs up to the current time */
4120		if (v->pci.op_pending)
4121		flush_fifos(v, machine().time());
	4058	if (pci.op_pending)
	4059	flush_fifos(this, machine().time());
4122	4060
4123	4061	/* target the appropriate location */
4124	4062	if (!(offset & (0xc00000/4)))
4125		return register_r(v, offset);
	4063	return register_r(this, offset);
4126	4064	else if (!(offset & (0x800000/4)))
4127		return lfb_r(v, offset, true);
	4065	return lfb_r(this, offset, true);
4128	4066
4129	4067	return 0xffffffff;
4130	4068	}
r253153	r253154
4140	4078
4141	4079	READ32_MEMBER( voodoo_banshee_device::banshee_agp_r )
4142	4080	{
4143		voodoo_state *v = get_safe_token(this);
4144	4081	UINT32 result;
4145	4082
4146	4083	offset &= 0x1ff/4;
r253153	r253154
4149	4086	switch (offset)
4150	4087	{
4151	4088	case cmdRdPtrL0:
4152		result = ~~v->~~fbi.cmdfifo[0].rdptr;
	4089	result = fbi.cmdfifo[0].rdptr;
4153	4090	break;
4154	4091
4155	4092	case cmdAMin0:
4156		result = ~~v->~~fbi.cmdfifo[0].amin;
	4093	result = fbi.cmdfifo[0].amin;
4157	4094	break;
4158	4095
4159	4096	case cmdAMax0:
4160		result = ~~v->~~fbi.cmdfifo[0].amax;
	4097	result = fbi.cmdfifo[0].amax;
4161	4098	break;
4162	4099
4163	4100	case cmdFifoDepth0:
4164		result = ~~v->~~fbi.cmdfifo[0].depth;
	4101	result = fbi.cmdfifo[0].depth;
4165	4102	break;
4166	4103
4167	4104	case cmdHoleCnt0:
4168		result = ~~v->~~fbi.cmdfifo[0].holes;
	4105	result = fbi.cmdfifo[0].holes;
4169	4106	break;
4170	4107
4171	4108	case cmdRdPtrL1:
4172		result = ~~v->~~fbi.cmdfifo[1].rdptr;
	4109	result = fbi.cmdfifo[1].rdptr;
4173	4110	break;
4174	4111
4175	4112	case cmdAMin1:
4176		result = ~~v->~~fbi.cmdfifo[1].amin;
	4113	result = fbi.cmdfifo[1].amin;
4177	4114	break;
4178	4115
4179	4116	case cmdAMax1:
4180		result = ~~v->~~fbi.cmdfifo[1].amax;
	4117	result = fbi.cmdfifo[1].amax;
4181	4118	break;
4182	4119
4183	4120	case cmdFifoDepth1:
4184		result = ~~v->~~fbi.cmdfifo[1].depth;
	4121	result = fbi.cmdfifo[1].depth;
4185	4122	break;
4186	4123
4187	4124	case cmdHoleCnt1:
4188		result = ~~v->~~fbi.cmdfifo[1].holes;
	4125	result = fbi.cmdfifo[1].holes;
4189	4126	break;
4190	4127
4191	4128	default:
4192		result = ~~v->~~banshee.agp[offset];
	4129	result = banshee.agp[offset];
4193	4130	break;
4194	4131	}
4195	4132
4196	4133	if (LOG_REGISTERS)
4197		logerror("%s:banshee_r(AGP:%s)\n", ~~v->~~device->machine().describe_context(), banshee_agp_reg_name[offset]);
	4134	logerror("%s:banshee_r(AGP:%s)\n", device->machine().describe_context(), banshee_agp_reg_name[offset]);
4198	4135	return result;
4199	4136	}
4200	4137
4201	4138
4202	4139	READ32_MEMBER( voodoo_banshee_device::banshee_r )
4203	4140	{
4204		voodoo_state *v = get_safe_token(this);
4205	4141	UINT32 result = 0xffffffff;
4206	4142
4207	4143	/* if we have something pending, flush the FIFOs up to the current time */
4208		if (v->pci.op_pending)
4209		flush_fifos(v, machine().time());
	4144	if (pci.op_pending)
	4145	flush_fifos(this, machine().time());
4210	4146
4211	4147	if (offset < 0x80000/4)
4212	4148	result = banshee_io_r(space, offset, mem_mask);
r253153	r253154
4215	4151	else if (offset < 0x200000/4)
4216	4152	logerror("%s:banshee_r(2D:%X)\n", machine().describe_context(), (offset*4) & 0xfffff);
4217	4153	else if (offset < 0x600000/4)
4218		result = register_r(v, offset & 0x1fffff/4);
	4154	result = register_r(this, offset & 0x1fffff/4);
4219	4155	else if (offset < 0x800000/4)
4220	4156	logerror("%s:banshee_r(TEX0:%X)\n", machine().describe_context(), (offset*4) & 0x1fffff);
4221	4157	else if (offset < 0xa00000/4)
r253153	r253154
4226	4162	logerror("%s:banshee_r(YUV:%X)\n", machine().describe_context(), (offset*4) & 0x3fffff);
4227	4163	else if (offset < 0x2000000/4)
4228	4164	{
4229		result = lfb_r(v, offset & 0xffffff/4, true);
	4165	result = lfb_r(this, offset & 0xffffff/4, true);
4230	4166	} else {
4231	4167	logerror("%s:banshee_r(%X) Access out of bounds\n", machine().describe_context(), offset*4);
4232	4168	}
r253153	r253154
4236	4172
4237	4173	READ32_MEMBER( voodoo_banshee_device::banshee_fb_r )
4238	4174	{
4239		voodoo_state *v = get_safe_token(this);
4240	4175	UINT32 result = 0xffffffff;
4241	4176
4242	4177	/* if we have something pending, flush the FIFOs up to the current time */
4243		if (v->pci.op_pending)
4244		flush_fifos(v, machine().time());
	4178	if (pci.op_pending)
	4179	flush_fifos(this, machine().time());
4245	4180
4246		if (offset < ~~v->~~fbi.lfb_base)
	4181	if (offset < fbi.lfb_base)
4247	4182	{
4248	4183	#if LOG_LFB
4249	4184	logerror("%s:banshee_fb_r(%X)\n", machine().describe_context(), offset*4);
4250	4185	#endif
4251		if (offset*4 <= v->fbi.mask)
4252		result = ((UINT32 *)v->fbi.ram)[offset];
	4186	if (offset*4 <= fbi.mask)
	4187	result = ((UINT32 *)fbi.ram)[offset];
4253	4188	else
4254	4189	logerror("%s:banshee_fb_r(%X) Access out of bounds\n", machine().describe_context(), offset*4);
4255	4190	}
4256	4191	else {
4257	4192	if (LOG_LFB)
4258		logerror("%s:banshee_fb_r(%X) to lfb_r: %08X lfb_base=%08X\n", machine().describe_context(), offset*4, offset - v->fbi.lfb_base, v->fbi.lfb_base);
4259		result = lfb_r(v, offset - v->fbi.lfb_base, false);
	4193	logerror("%s:banshee_fb_r(%X) to lfb_r: %08X lfb_base=%08X\n", machine().describe_context(), offset*4, offset - fbi.lfb_base, fbi.lfb_base);
	4194	result = lfb_r(this, offset - fbi.lfb_base, false);
4260	4195	}
4261	4196	return result;
4262	4197	}
r253153	r253154
4264	4199
4265	4200	READ8_MEMBER( voodoo_banshee_device::banshee_vga_r )
4266	4201	{
4267		voodoo_state *v = get_safe_token(this);
4268	4202	UINT8 result = 0xff;
4269	4203
4270	4204	offset &= 0x1f;
r253153	r253154
4274	4208	{
4275	4209	/* attribute access */
4276	4210	case 0x3c0:
4277		if (v->banshee.vga[0x3c1 & 0x1f] < ARRAY_LENGTH(v->banshee.att))
4278		result = v->banshee.att[v->banshee.vga[0x3c1 & 0x1f]];
	4211	if (banshee.vga[0x3c1 & 0x1f] < ARRAY_LENGTH(banshee.att))
	4212	result = banshee.att[banshee.vga[0x3c1 & 0x1f]];
4279	4213	if (LOG_REGISTERS)
4280		logerror("%s:banshee_att_r(%X)\n", machine().describe_context(), ~~v->~~banshee.vga[0x3c1 & 0x1f]);
	4214	logerror("%s:banshee_att_r(%X)\n", machine().describe_context(), banshee.vga[0x3c1 & 0x1f]);
4281	4215	break;
4282	4216
4283	4217	/* Input status 0 */
r253153	r253154
4295	4229
4296	4230	/* Sequencer access */
4297	4231	case 0x3c5:
4298		if (v->banshee.vga[0x3c4 & 0x1f] < ARRAY_LENGTH(v->banshee.seq))
4299		result = v->banshee.seq[v->banshee.vga[0x3c4 & 0x1f]];
	4232	if (banshee.vga[0x3c4 & 0x1f] < ARRAY_LENGTH(banshee.seq))
	4233	result = banshee.seq[banshee.vga[0x3c4 & 0x1f]];
4300	4234	if (LOG_REGISTERS)
4301		logerror("%s:banshee_seq_r(%X)\n", machine().describe_context(), ~~v->~~banshee.vga[0x3c4 & 0x1f]);
	4235	logerror("%s:banshee_seq_r(%X)\n", machine().describe_context(), banshee.vga[0x3c4 & 0x1f]);
4302	4236	break;
4303	4237
4304	4238	/* Feature control */
4305	4239	case 0x3ca:
4306		result = v->banshee.vga[0x3da & 0x1f];
4307		v->banshee.attff = 0;
	4240	result = banshee.vga[0x3da & 0x1f];
	4241	banshee.attff = 0;
4308	4242	if (LOG_REGISTERS)
4309	4243	logerror("%s:banshee_vga_r(%X)\n", machine().describe_context(), 0x300+offset);
4310	4244	break;
4311	4245
4312	4246	/* Miscellaneous output */
4313	4247	case 0x3cc:
4314		result = ~~v->~~banshee.vga[0x3c2 & 0x1f];
	4248	result = banshee.vga[0x3c2 & 0x1f];
4315	4249	if (LOG_REGISTERS)
4316	4250	logerror("%s:banshee_vga_r(%X)\n", machine().describe_context(), 0x300+offset);
4317	4251	break;
4318	4252
4319	4253	/* Graphics controller access */
4320	4254	case 0x3cf:
4321		if (v->banshee.vga[0x3ce & 0x1f] < ARRAY_LENGTH(v->banshee.gc))
4322		result = v->banshee.gc[v->banshee.vga[0x3ce & 0x1f]];
	4255	if (banshee.vga[0x3ce & 0x1f] < ARRAY_LENGTH(banshee.gc))
	4256	result = banshee.gc[banshee.vga[0x3ce & 0x1f]];
4323	4257	if (LOG_REGISTERS)
4324		logerror("%s:banshee_gc_r(%X)\n", machine().describe_context(), ~~v->~~banshee.vga[0x3ce & 0x1f]);
	4258	logerror("%s:banshee_gc_r(%X)\n", machine().describe_context(), banshee.vga[0x3ce & 0x1f]);
4325	4259	break;
4326	4260
4327	4261	/* CRTC access */
4328	4262	case 0x3d5:
4329		if (v->banshee.vga[0x3d4 & 0x1f] < ARRAY_LENGTH(v->banshee.crtc))
4330		result = v->banshee.crtc[v->banshee.vga[0x3d4 & 0x1f]];
	4263	if (banshee.vga[0x3d4 & 0x1f] < ARRAY_LENGTH(banshee.crtc))
	4264	result = banshee.crtc[banshee.vga[0x3d4 & 0x1f]];
4331	4265	if (LOG_REGISTERS)
4332		logerror("%s:banshee_crtc_r(%X)\n", machine().describe_context(), ~~v->~~banshee.vga[0x3d4 & 0x1f]);
	4266	logerror("%s:banshee_crtc_r(%X)\n", machine().describe_context(), banshee.vga[0x3d4 & 0x1f]);
4333	4267	break;
4334	4268
4335	4269	/* Input status 1 */
r253153	r253154
4349	4283	break;
4350	4284
4351	4285	default:
4352		result = ~~v->~~banshee.vga[offset];
	4286	result = banshee.vga[offset];
4353	4287	if (LOG_REGISTERS)
4354	4288	logerror("%s:banshee_vga_r(%X)\n", machine().describe_context(), 0x300+offset);
4355	4289	break;
r253153	r253154
4360	4294
4361	4295	READ32_MEMBER( voodoo_banshee_device::banshee_io_r )
4362	4296	{
4363		voodoo_state *v = get_safe_token(this);
4364	4297	UINT32 result;
4365	4298
4366	4299	offset &= 0xff/4;
r253153	r253154
4369	4302	switch (offset)
4370	4303	{
4371	4304	case io_status:
4372		result = register_r(v, 0);
	4305	result = register_r(this, 0);
4373	4306	break;
4374	4307
4375	4308	case io_dacData:
4376		result = ~~v->~~fbi.clut[~~v->~~banshee.io[io_dacAddr] & 0x1ff] = ~~v->~~banshee.io[offset];
	4309	result = fbi.clut[banshee.io[io_dacAddr] & 0x1ff] = banshee.io[offset];
4377	4310	if (LOG_REGISTERS)
4378		logerror("%s:banshee_dac_r(%X)\n", machine().describe_context(), ~~v->~~banshee.io[io_dacAddr] & 0x1ff);
	4311	logerror("%s:banshee_dac_r(%X)\n", machine().describe_context(), banshee.io[io_dacAddr] & 0x1ff);
4379	4312	break;
4380	4313
4381	4314	case io_vgab0: case io_vgab4: case io_vgab8: case io_vgabc:
r253153	r253154
4393	4326	break;
4394	4327
4395	4328	default:
4396		result = ~~v->~~banshee.io[offset];
	4329	result = banshee.io[offset];
4397	4330	if (LOG_REGISTERS)
4398	4331	logerror("%s:banshee_io_r(%s)\n", machine().describe_context(), banshee_io_reg_name[offset]);
4399	4332	break;
r253153	r253154
4409	4342	return 0xffffffff;
4410	4343	}
4411	4344
4412		static void blit_2d(voodoo_~~stat~~e *v, UINT32 data)
	4345	static void blit_2d(voodoo_device *vd, UINT32 data)
4413	4346	{
4414		switch (v->banshee.blt_cmd)
	4347	switch (vd->banshee.blt_cmd)
4415	4348	{
4416	4349	case 0: // NOP - wait for idle
4417	4350	{
r253153	r253154
4434	4367
4435	4368	case 3: // Host-to-screen blit
4436	4369	{
4437		UINT32 addr = v->banshee.blt_dst_base;
	4370	UINT32 addr = vd->banshee.blt_dst_base;
4438	4371
4439		addr += (v->banshee.blt_dst_y * v->banshee.blt_dst_stride) + (v->banshee.blt_dst_x * v->banshee.blt_dst_bpp);
	4372	addr += (vd->banshee.blt_dst_y * vd->banshee.blt_dst_stride) + (vd->banshee.blt_dst_x * vd->banshee.blt_dst_bpp);
4440	4373
4441	4374	#if LOG_BANSHEE_2D
4442		logerror(" blit_2d:host_to_screen: %08x -> %08x, %d, %d\n", data, addr, v->banshee.blt_dst_x, v->banshee.blt_dst_y);
	4375	logerror(" blit_2d:host_to_screen: %08x -> %08x, %d, %d\n", data, addr, vd->banshee.blt_dst_x, vd->banshee.blt_dst_y);
4443	4376	#endif
4444	4377
4445		switch (v->banshee.blt_dst_bpp)
	4378	switch (vd->banshee.blt_dst_bpp)
4446	4379	{
4447	4380	case 1:
4448		v->fbi.ram[addr+0] = data & 0xff;
4449		v->fbi.ram[addr+1] = (data >> 8) & 0xff;
4450		v->fbi.ram[addr+2] = (data >> 16) & 0xff;
4451		v->fbi.ram[addr+3] = (data >> 24) & 0xff;
4452		v->banshee.blt_dst_x += 4;
	4381	vd->fbi.ram[addr+0] = data & 0xff;
	4382	vd->fbi.ram[addr+1] = (data >> 8) & 0xff;
	4383	vd->fbi.ram[addr+2] = (data >> 16) & 0xff;
	4384	vd->fbi.ram[addr+3] = (data >> 24) & 0xff;
	4385	vd->banshee.blt_dst_x += 4;
4453	4386	break;
4454	4387	case 2:
4455		v->fbi.ram[addr+1] = data & 0xff;
4456		v->fbi.ram[addr+0] = (data >> 8) & 0xff;
4457		v->fbi.ram[addr+3] = (data >> 16) & 0xff;
4458		v->fbi.ram[addr+2] = (data >> 24) & 0xff;
4459		v->banshee.blt_dst_x += 2;
	4388	vd->fbi.ram[addr+1] = data & 0xff;
	4389	vd->fbi.ram[addr+0] = (data >> 8) & 0xff;
	4390	vd->fbi.ram[addr+3] = (data >> 16) & 0xff;
	4391	vd->fbi.ram[addr+2] = (data >> 24) & 0xff;
	4392	vd->banshee.blt_dst_x += 2;
4460	4393	break;
4461	4394	case 3:
4462		v->banshee.blt_dst_x += 1;
	4395	vd->banshee.blt_dst_x += 1;
4463	4396	break;
4464	4397	case 4:
4465		v->fbi.ram[addr+3] = data & 0xff;
4466		v->fbi.ram[addr+2] = (data >> 8) & 0xff;
4467		v->fbi.ram[addr+1] = (data >> 16) & 0xff;
4468		v->fbi.ram[addr+0] = (data >> 24) & 0xff;
4469		v->banshee.blt_dst_x += 1;
	4398	vd->fbi.ram[addr+3] = data & 0xff;
	4399	vd->fbi.ram[addr+2] = (data >> 8) & 0xff;
	4400	vd->fbi.ram[addr+1] = (data >> 16) & 0xff;
	4401	vd->fbi.ram[addr+0] = (data >> 24) & 0xff;
	4402	vd->banshee.blt_dst_x += 1;
4470	4403	break;
4471	4404	}
4472	4405
4473		if (v->banshee.blt_dst_x >= v->banshee.blt_dst_width)
	4406	if (vd->banshee.blt_dst_x >= vd->banshee.blt_dst_width)
4474	4407	{
4475		v->banshee.blt_dst_x = 0;
4476		v->banshee.blt_dst_y++;
	4408	vd->banshee.blt_dst_x = 0;
	4409	vd->banshee.blt_dst_y++;
4477	4410	}
4478	4411	break;
4479	4412	}
r253153	r253154
4500	4433
4501	4434	default:
4502	4435	{
4503		fatalerror("blit_2d: unknown command %d\n", v->banshee.blt_cmd);
	4436	fatalerror("blit_2d: unknown command %d\n", vd->banshee.blt_cmd);
4504	4437	}
4505	4438	}
4506	4439	}
4507	4440
4508		~~static~~ INT32 banshee_2d_w(voodoo_~~stat~~e *v, offs_t offset, UINT32 data)
	4441	INT32 voodoo_device::banshee_2d_w(voodoo_device *vd, offs_t offset, UINT32 data)
4509	4442	{
4510	4443	switch (offset)
4511	4444	{
r253153	r253154
4514	4447	logerror(" 2D:command: cmd %d, ROP0 %02X\n", data & 0xf, data >> 24);
4515	4448	#endif
4516	4449
4517		v->banshee.blt_src_x = v->banshee.blt_regs[banshee2D_srcXY] & 0xfff;
4518		v->banshee.blt_src_y = (v->banshee.blt_regs[banshee2D_srcXY] >> 16) & 0xfff;
4519		v->banshee.blt_src_base = v->banshee.blt_regs[banshee2D_srcBaseAddr] & 0xffffff;
4520		v->banshee.blt_src_stride = v->banshee.blt_regs[banshee2D_srcFormat] & 0x3fff;
4521		v->banshee.blt_src_width = v->banshee.blt_regs[banshee2D_srcSize] & 0xfff;
4522		v->banshee.blt_src_height = (v->banshee.blt_regs[banshee2D_srcSize] >> 16) & 0xfff;
	4450	vd->banshee.blt_src_x = vd->banshee.blt_regs[banshee2D_srcXY] & 0xfff;
	4451	vd->banshee.blt_src_y = (vd->banshee.blt_regs[banshee2D_srcXY] >> 16) & 0xfff;
	4452	vd->banshee.blt_src_base = vd->banshee.blt_regs[banshee2D_srcBaseAddr] & 0xffffff;
	4453	vd->banshee.blt_src_stride = vd->banshee.blt_regs[banshee2D_srcFormat] & 0x3fff;
	4454	vd->banshee.blt_src_width = vd->banshee.blt_regs[banshee2D_srcSize] & 0xfff;
	4455	vd->banshee.blt_src_height = (vd->banshee.blt_regs[banshee2D_srcSize] >> 16) & 0xfff;
4523	4456
4524		switch ((v->banshee.blt_regs[banshee2D_srcFormat] >> 16) & 0xf)
	4457	switch ((vd->banshee.blt_regs[banshee2D_srcFormat] >> 16) & 0xf)
4525	4458	{
4526		case 1: v->banshee.blt_src_bpp = 1; break;
4527		case 3: v->banshee.blt_src_bpp = 2; break;
4528		case 4: v->banshee.blt_src_bpp = 3; break;
4529		case 5: v->banshee.blt_src_bpp = 4; break;
4530		case 8: v->banshee.blt_src_bpp = 2; break;
4531		case 9: v->banshee.blt_src_bpp = 2; break;
4532		default: v->banshee.blt_src_bpp = 1; break;
	4459	case 1: vd->banshee.blt_src_bpp = 1; break;
	4460	case 3: vd->banshee.blt_src_bpp = 2; break;
	4461	case 4: vd->banshee.blt_src_bpp = 3; break;
	4462	case 5: vd->banshee.blt_src_bpp = 4; break;
	4463	case 8: vd->banshee.blt_src_bpp = 2; break;
	4464	case 9: vd->banshee.blt_src_bpp = 2; break;
	4465	default: vd->banshee.blt_src_bpp = 1; break;
4533	4466	}
4534	4467
4535		v->banshee.blt_dst_x = v->banshee.blt_regs[banshee2D_dstXY] & 0xfff;
4536		v->banshee.blt_dst_y = (v->banshee.blt_regs[banshee2D_dstXY] >> 16) & 0xfff;
4537		v->banshee.blt_dst_base = v->banshee.blt_regs[banshee2D_dstBaseAddr] & 0xffffff;
4538		v->banshee.blt_dst_stride = v->banshee.blt_regs[banshee2D_dstFormat] & 0x3fff;
4539		v->banshee.blt_dst_width = v->banshee.blt_regs[banshee2D_dstSize] & 0xfff;
4540		v->banshee.blt_dst_height = (v->banshee.blt_regs[banshee2D_dstSize] >> 16) & 0xfff;
	4468	vd->banshee.blt_dst_x = vd->banshee.blt_regs[banshee2D_dstXY] & 0xfff;
	4469	vd->banshee.blt_dst_y = (vd->banshee.blt_regs[banshee2D_dstXY] >> 16) & 0xfff;
	4470	vd->banshee.blt_dst_base = vd->banshee.blt_regs[banshee2D_dstBaseAddr] & 0xffffff;
	4471	vd->banshee.blt_dst_stride = vd->banshee.blt_regs[banshee2D_dstFormat] & 0x3fff;
	4472	vd->banshee.blt_dst_width = vd->banshee.blt_regs[banshee2D_dstSize] & 0xfff;
	4473	vd->banshee.blt_dst_height = (vd->banshee.blt_regs[banshee2D_dstSize] >> 16) & 0xfff;
4541	4474
4542		switch ((v->banshee.blt_regs[banshee2D_dstFormat] >> 16) & 0x7)
	4475	switch ((vd->banshee.blt_regs[banshee2D_dstFormat] >> 16) & 0x7)
4543	4476	{
4544		case 1: v->banshee.blt_dst_bpp = 1; break;
4545		case 3: v->banshee.blt_dst_bpp = 2; break;
4546		case 4: v->banshee.blt_dst_bpp = 3; break;
4547		case 5: v->banshee.blt_dst_bpp = 4; break;
4548		default: v->banshee.blt_dst_bpp = 1; break;
	4477	case 1: vd->banshee.blt_dst_bpp = 1; break;
	4478	case 3: vd->banshee.blt_dst_bpp = 2; break;
	4479	case 4: vd->banshee.blt_dst_bpp = 3; break;
	4480	case 5: vd->banshee.blt_dst_bpp = 4; break;
	4481	default: vd->banshee.blt_dst_bpp = 1; break;
4549	4482	}
4550	4483
4551		v->banshee.blt_cmd = data & 0xf;
	4484	vd->banshee.blt_cmd = data & 0xf;
4552	4485	break;
4553	4486
4554	4487	case banshee2D_colorBack:
4555	4488	#if LOG_BANSHEE_2D
4556	4489	logerror(" 2D:colorBack: %08X\n", data);
4557	4490	#endif
4558		v->banshee.blt_regs[banshee2D_colorBack] = data;
	4491	vd->banshee.blt_regs[banshee2D_colorBack] = data;
4559	4492	break;
4560	4493
4561	4494	case banshee2D_colorFore:
4562	4495	#if LOG_BANSHEE_2D
4563	4496	logerror(" 2D:colorFore: %08X\n", data);
4564	4497	#endif
4565		v->banshee.blt_regs[banshee2D_colorFore] = data;
	4498	vd->banshee.blt_regs[banshee2D_colorFore] = data;
4566	4499	break;
4567	4500
4568	4501	case banshee2D_srcBaseAddr:
4569	4502	#if LOG_BANSHEE_2D
4570	4503	logerror(" 2D:srcBaseAddr: %08X, %s\n", data & 0xffffff, data & 0x80000000 ? "tiled" : "non-tiled");
4571	4504	#endif
4572		v->banshee.blt_regs[banshee2D_srcBaseAddr] = data;
	4505	vd->banshee.blt_regs[banshee2D_srcBaseAddr] = data;
4573	4506	break;
4574	4507
4575	4508	case banshee2D_dstBaseAddr:
4576	4509	#if LOG_BANSHEE_2D
4577	4510	logerror(" 2D:dstBaseAddr: %08X, %s\n", data & 0xffffff, data & 0x80000000 ? "tiled" : "non-tiled");
4578	4511	#endif
4579		v->banshee.blt_regs[banshee2D_dstBaseAddr] = data;
	4512	vd->banshee.blt_regs[banshee2D_dstBaseAddr] = data;
4580	4513	break;
4581	4514
4582	4515	case banshee2D_srcSize:
4583	4516	#if LOG_BANSHEE_2D
4584	4517	logerror(" 2D:srcSize: %d, %d\n", data & 0xfff, (data >> 16) & 0xfff);
4585	4518	#endif
4586		v->banshee.blt_regs[banshee2D_srcSize] = data;
	4519	vd->banshee.blt_regs[banshee2D_srcSize] = data;
4587	4520	break;
4588	4521
4589	4522	case banshee2D_dstSize:
4590	4523	#if LOG_BANSHEE_2D
4591	4524	logerror(" 2D:dstSize: %d, %d\n", data & 0xfff, (data >> 16) & 0xfff);
4592	4525	#endif
4593		v->banshee.blt_regs[banshee2D_dstSize] = data;
	4526	vd->banshee.blt_regs[banshee2D_dstSize] = data;
4594	4527	break;
4595	4528
4596	4529	case banshee2D_srcXY:
4597	4530	#if LOG_BANSHEE_2D
4598	4531	logerror(" 2D:srcXY: %d, %d\n", data & 0xfff, (data >> 16) & 0xfff);
4599	4532	#endif
4600		v->banshee.blt_regs[banshee2D_srcXY] = data;
	4533	vd->banshee.blt_regs[banshee2D_srcXY] = data;
4601	4534	break;
4602	4535
4603	4536	case banshee2D_dstXY:
4604	4537	#if LOG_BANSHEE_2D
4605	4538	logerror(" 2D:dstXY: %d, %d\n", data & 0xfff, (data >> 16) & 0xfff);
4606	4539	#endif
4607		v->banshee.blt_regs[banshee2D_dstXY] = data;
	4540	vd->banshee.blt_regs[banshee2D_dstXY] = data;
4608	4541	break;
4609	4542
4610	4543	case banshee2D_srcFormat:
4611	4544	#if LOG_BANSHEE_2D
4612	4545	logerror(" 2D:srcFormat: str %d, fmt %d, packing %d\n", data & 0x3fff, (data >> 16) & 0xf, (data >> 22) & 0x3);
4613	4546	#endif
4614		v->banshee.blt_regs[banshee2D_srcFormat] = data;
	4547	vd->banshee.blt_regs[banshee2D_srcFormat] = data;
4615	4548	break;
4616	4549
4617	4550	case banshee2D_dstFormat:
4618	4551	#if LOG_BANSHEE_2D
4619	4552	logerror(" 2D:dstFormat: str %d, fmt %d\n", data & 0x3fff, (data >> 16) & 0xf);
4620	4553	#endif
4621		v->banshee.blt_regs[banshee2D_dstFormat] = data;
	4554	vd->banshee.blt_regs[banshee2D_dstFormat] = data;
4622	4555	break;
4623	4556
4624	4557	case banshee2D_clip0Min:
4625	4558	#if LOG_BANSHEE_2D
4626	4559	logerror(" 2D:clip0Min: %d, %d\n", data & 0xfff, (data >> 16) & 0xfff);
4627	4560	#endif
4628		v->banshee.blt_regs[banshee2D_clip0Min] = data;
	4561	vd->banshee.blt_regs[banshee2D_clip0Min] = data;
4629	4562	break;
4630	4563
4631	4564	case banshee2D_clip0Max:
4632	4565	#if LOG_BANSHEE_2D
4633	4566	logerror(" 2D:clip0Max: %d, %d\n", data & 0xfff, (data >> 16) & 0xfff);
4634	4567	#endif
4635		v->banshee.blt_regs[banshee2D_clip0Max] = data;
	4568	vd->banshee.blt_regs[banshee2D_clip0Max] = data;
4636	4569	break;
4637	4570
4638	4571	case banshee2D_clip1Min:
4639	4572	#if LOG_BANSHEE_2D
4640	4573	logerror(" 2D:clip1Min: %d, %d\n", data & 0xfff, (data >> 16) & 0xfff);
4641	4574	#endif
4642		v->banshee.blt_regs[banshee2D_clip1Min] = data;
	4575	vd->banshee.blt_regs[banshee2D_clip1Min] = data;
4643	4576	break;
4644	4577
4645	4578	case banshee2D_clip1Max:
4646	4579	#if LOG_BANSHEE_2D
4647	4580	logerror(" 2D:clip1Max: %d, %d\n", data & 0xfff, (data >> 16) & 0xfff);
4648	4581	#endif
4649		v->banshee.blt_regs[banshee2D_clip1Max] = data;
	4582	vd->banshee.blt_regs[banshee2D_clip1Max] = data;
4650	4583	break;
4651	4584
4652	4585	case banshee2D_rop:
4653	4586	#if LOG_BANSHEE_2D
4654	4587	logerror(" 2D:rop: %d, %d, %d\n", data & 0xff, (data >> 8) & 0xff, (data >> 16) & 0xff);
4655	4588	#endif
4656		v->banshee.blt_regs[banshee2D_rop] = data;
	4589	vd->banshee.blt_regs[banshee2D_rop] = data;
4657	4590	break;
4658	4591
4659	4592	default:
4660	4593	if (offset >= 0x20 && offset < 0x40)
4661	4594	{
4662		blit_2d(v, data);
	4595	blit_2d(vd, data);
4663	4596	}
4664	4597	else if (offset >= 0x40 && offset < 0x80)
4665	4598	{
r253153	r253154
4677	4610
4678	4611	WRITE32_MEMBER( voodoo_banshee_device::banshee_agp_w )
4679	4612	{
4680		voodoo_state *v = get_safe_token(this);
4681	4613	offset &= 0x1ff/4;
4682	4614
4683	4615	/* switch off the offset */
4684	4616	switch (offset)
4685	4617	{
4686	4618	case cmdBaseAddr0:
4687		COMBINE_DATA(&v->banshee.agp[offset]);
4688		v->fbi.cmdfifo[0].base = (data & 0xffffff) << 12;
4689		v->fbi.cmdfifo[0].end = v->fbi.cmdfifo[0].base + (((v->banshee.agp[cmdBaseSize0] & 0xff) + 1) << 12);
	4619	COMBINE_DATA(&banshee.agp[offset]);
	4620	fbi.cmdfifo[0].base = (data & 0xffffff) << 12;
	4621	fbi.cmdfifo[0].end = fbi.cmdfifo[0].base + (((banshee.agp[cmdBaseSize0] & 0xff) + 1) << 12);
4690	4622	break;
4691	4623
4692	4624	case cmdBaseSize0:
4693		COMBINE_DATA(&v->banshee.agp[offset]);
4694		v->fbi.cmdfifo[0].end = v->fbi.cmdfifo[0].base + (((v->banshee.agp[cmdBaseSize0] & 0xff) + 1) << 12);
4695		v->fbi.cmdfifo[0].enable = (data >> 8) & 1;
4696		v->fbi.cmdfifo[0].count_holes = (~data >> 10) & 1;
	4625	COMBINE_DATA(&banshee.agp[offset]);
	4626	fbi.cmdfifo[0].end = fbi.cmdfifo[0].base + (((banshee.agp[cmdBaseSize0] & 0xff) + 1) << 12);
	4627	fbi.cmdfifo[0].enable = (data >> 8) & 1;
	4628	fbi.cmdfifo[0].count_holes = (~data >> 10) & 1;
4697	4629	break;
4698	4630
4699	4631	case cmdBump0:
4700	4632	fatalerror("cmdBump0\n");
4701	4633
4702	4634	case cmdRdPtrL0:
4703		~~v->~~fbi.cmdfifo[0].rdptr = data;
	4635	fbi.cmdfifo[0].rdptr = data;
4704	4636	break;
4705	4637
4706	4638	case cmdAMin0:
4707		~~v->~~fbi.cmdfifo[0].amin = data;
	4639	fbi.cmdfifo[0].amin = data;
4708	4640	break;
4709	4641
4710	4642	case cmdAMax0:
4711		~~v->~~fbi.cmdfifo[0].amax = data;
	4643	fbi.cmdfifo[0].amax = data;
4712	4644	break;
4713	4645
4714	4646	case cmdFifoDepth0:
4715		~~v->~~fbi.cmdfifo[0].depth = data;
	4647	fbi.cmdfifo[0].depth = data;
4716	4648	break;
4717	4649
4718	4650	case cmdHoleCnt0:
4719		~~v->~~fbi.cmdfifo[0].holes = data;
	4651	fbi.cmdfifo[0].holes = data;
4720	4652	break;
4721	4653
4722	4654	case cmdBaseAddr1:
4723		COMBINE_DATA(&v->banshee.agp[offset]);
4724		v->fbi.cmdfifo[1].base = (data & 0xffffff) << 12;
4725		v->fbi.cmdfifo[1].end = v->fbi.cmdfifo[1].base + (((v->banshee.agp[cmdBaseSize1] & 0xff) + 1) << 12);
	4655	COMBINE_DATA(&banshee.agp[offset]);
	4656	fbi.cmdfifo[1].base = (data & 0xffffff) << 12;
	4657	fbi.cmdfifo[1].end = fbi.cmdfifo[1].base + (((banshee.agp[cmdBaseSize1] & 0xff) + 1) << 12);
4726	4658	break;
4727	4659
4728	4660	case cmdBaseSize1:
4729		COMBINE_DATA(&v->banshee.agp[offset]);
4730		v->fbi.cmdfifo[1].end = v->fbi.cmdfifo[1].base + (((v->banshee.agp[cmdBaseSize1] & 0xff) + 1) << 12);
4731		v->fbi.cmdfifo[1].enable = (data >> 8) & 1;
4732		v->fbi.cmdfifo[1].count_holes = (~data >> 10) & 1;
	4661	COMBINE_DATA(&banshee.agp[offset]);
	4662	fbi.cmdfifo[1].end = fbi.cmdfifo[1].base + (((banshee.agp[cmdBaseSize1] & 0xff) + 1) << 12);
	4663	fbi.cmdfifo[1].enable = (data >> 8) & 1;
	4664	fbi.cmdfifo[1].count_holes = (~data >> 10) & 1;
4733	4665	break;
4734	4666
4735	4667	case cmdBump1:
4736	4668	fatalerror("cmdBump1\n");
4737	4669
4738	4670	case cmdRdPtrL1:
4739		~~v->~~fbi.cmdfifo[1].rdptr = data;
	4671	fbi.cmdfifo[1].rdptr = data;
4740	4672	break;
4741	4673
4742	4674	case cmdAMin1:
4743		~~v->~~fbi.cmdfifo[1].amin = data;
	4675	fbi.cmdfifo[1].amin = data;
4744	4676	break;
4745	4677
4746	4678	case cmdAMax1:
4747		~~v->~~fbi.cmdfifo[1].amax = data;
	4679	fbi.cmdfifo[1].amax = data;
4748	4680	break;
4749	4681
4750	4682	case cmdFifoDepth1:
4751		~~v->~~fbi.cmdfifo[1].depth = data;
	4683	fbi.cmdfifo[1].depth = data;
4752	4684	break;
4753	4685
4754	4686	case cmdHoleCnt1:
4755		~~v->~~fbi.cmdfifo[1].holes = data;
	4687	fbi.cmdfifo[1].holes = data;
4756	4688	break;
4757	4689
4758	4690	default:
4759		COMBINE_DATA(&~~v->~~banshee.agp[offset]);
	4691	COMBINE_DATA(&banshee.agp[offset]);
4760	4692	break;
4761	4693	}
4762	4694
r253153	r253154
4767	4699
4768	4700	WRITE32_MEMBER( voodoo_banshee_device::banshee_w )
4769	4701	{
4770		voodoo_state *v = get_safe_token(this);
4771	4702
4772	4703	/* if we have something pending, flush the FIFOs up to the current time */
4773		if (v->pci.op_pending)
4774		flush_fifos(v, machine().time());
	4704	if (pci.op_pending)
	4705	flush_fifos(this, machine().time());
4775	4706
4776	4707	if (offset < 0x80000/4)
4777	4708	banshee_io_w(space, offset, data, mem_mask);
r253153	r253154
4780	4711	else if (offset < 0x200000/4)
4781	4712	logerror("%s:banshee_w(2D:%X) = %08X & %08X\n", machine().describe_context(), (offset*4) & 0xfffff, data, mem_mask);
4782	4713	else if (offset < 0x600000/4)
4783		register_w(v, offset & 0x1fffff/4, data);
	4714	register_w(this, offset & 0x1fffff/4, data);
4784	4715	else if (offset < 0x800000/4)
4785	4716	logerror("%s:banshee_w(TEX0:%X) = %08X & %08X\n", machine().describe_context(), (offset*4) & 0x1fffff, data, mem_mask);
4786	4717	else if (offset < 0xa00000/4)
r253153	r253154
4791	4722	logerror("%s:banshee_w(YUV:%X) = %08X & %08X\n", machine().describe_context(), (offset*4) & 0x3fffff, data, mem_mask);
4792	4723	else if (offset < 0x2000000/4)
4793	4724	{
4794		lfb_w(v, offset & 0xffffff/4, data, mem_mask);
	4725	lfb_w(this, offset & 0xffffff/4, data, mem_mask);
4795	4726	} else {
4796	4727	logerror("%s:banshee_w Address out of range %08X = %08X & %08X\n", machine().describe_context(), (offset*4), data, mem_mask);
4797	4728	}
r253153	r253154
4800	4731
4801	4732	WRITE32_MEMBER( voodoo_banshee_device::banshee_fb_w )
4802	4733	{
4803		voodoo_state *v = get_safe_token(this);
4804	4734	UINT32 addr = offset*4;
4805	4735
4806	4736	/* if we have something pending, flush the FIFOs up to the current time */
4807		if (v->pci.op_pending)
4808		flush_fifos(v, machine().time());
	4737	if (pci.op_pending)
	4738	flush_fifos(this, machine().time());
4809	4739
4810		if (offset < ~~v->~~fbi.lfb_base)
	4740	if (offset < fbi.lfb_base)
4811	4741	{
4812		if (v->fbi.cmdfifo[0].enable && addr >= v->fbi.cmdfifo[0].base && addr < v->fbi.cmdfifo[0].end)
4813		cmdfifo_w(v, &v->fbi.cmdfifo[0], (addr - v->fbi.cmdfifo[0].base) / 4, data);
4814		else if (v->fbi.cmdfifo[1].enable && addr >= v->fbi.cmdfifo[1].base && addr < v->fbi.cmdfifo[1].end)
4815		cmdfifo_w(v, &v->fbi.cmdfifo[1], (addr - v->fbi.cmdfifo[1].base) / 4, data);
	4742	if (fbi.cmdfifo[0].enable && addr >= fbi.cmdfifo[0].base && addr < fbi.cmdfifo[0].end)
	4743	cmdfifo_w(this, &fbi.cmdfifo[0], (addr - fbi.cmdfifo[0].base) / 4, data);
	4744	else if (fbi.cmdfifo[1].enable && addr >= fbi.cmdfifo[1].base && addr < fbi.cmdfifo[1].end)
	4745	cmdfifo_w(this, &fbi.cmdfifo[1], (addr - fbi.cmdfifo[1].base) / 4, data);
4816	4746	else
4817	4747	{
4818		if (offset*4 <= v->fbi.mask)
4819		COMBINE_DATA(&((UINT32 *)v->fbi.ram)[offset]);
	4748	if (offset*4 <= fbi.mask)
	4749	COMBINE_DATA(&((UINT32 *)fbi.ram)[offset]);
4820	4750	else
4821	4751	logerror("%s:banshee_fb_w Out of bounds (%X) = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
4822	4752	#if LOG_LFB
r253153	r253154
4825	4755	}
4826	4756	}
4827	4757	else
4828		lfb_direct_w(v, offset - ~~v->~~fbi.lfb_base, data, mem_mask);
	4758	lfb_direct_w(this, offset - fbi.lfb_base, data, mem_mask);
4829	4759	}
4830	4760
4831	4761
4832	4762	WRITE8_MEMBER( voodoo_banshee_device::banshee_vga_w )
4833	4763	{
4834		voodoo_state *v = get_safe_token(this);
4835	4764	offset &= 0x1f;
4836	4765
4837	4766	/* switch off the offset */
r253153	r253154
4840	4769	/* attribute access */
4841	4770	case 0x3c0:
4842	4771	case 0x3c1:
4843		if (~~v->~~banshee.attff == 0)
	4772	if (banshee.attff == 0)
4844	4773	{
4845		~~v->~~banshee.vga[0x3c1 & 0x1f] = data;
	4774	banshee.vga[0x3c1 & 0x1f] = data;
4846	4775	if (LOG_REGISTERS)
4847	4776	logerror("%s:banshee_vga_w(%X) = %02X\n", machine().describe_context(), 0x3c0+offset, data);
4848	4777	}
4849	4778	else
4850	4779	{
4851		if (v->banshee.vga[0x3c1 & 0x1f] < ARRAY_LENGTH(v->banshee.att))
4852		v->banshee.att[v->banshee.vga[0x3c1 & 0x1f]] = data;
	4780	if (banshee.vga[0x3c1 & 0x1f] < ARRAY_LENGTH(banshee.att))
	4781	banshee.att[banshee.vga[0x3c1 & 0x1f]] = data;
4853	4782	if (LOG_REGISTERS)
4854		logerror("%s:banshee_att_w(%X) = %02X\n", machine().describe_context(), ~~v->~~banshee.vga[0x3c1 & 0x1f], data);
	4783	logerror("%s:banshee_att_w(%X) = %02X\n", machine().describe_context(), banshee.vga[0x3c1 & 0x1f], data);
4855	4784	}
4856		~~v->~~banshee.attff ^= 1;
	4785	banshee.attff ^= 1;
4857	4786	break;
4858	4787
4859	4788	/* Sequencer access */
4860	4789	case 0x3c5:
4861		if (v->banshee.vga[0x3c4 & 0x1f] < ARRAY_LENGTH(v->banshee.seq))
4862		v->banshee.seq[v->banshee.vga[0x3c4 & 0x1f]] = data;
	4790	if (banshee.vga[0x3c4 & 0x1f] < ARRAY_LENGTH(banshee.seq))
	4791	banshee.seq[banshee.vga[0x3c4 & 0x1f]] = data;
4863	4792	if (LOG_REGISTERS)
4864		logerror("%s:banshee_seq_w(%X) = %02X\n", machine().describe_context(), ~~v->~~banshee.vga[0x3c4 & 0x1f], data);
	4793	logerror("%s:banshee_seq_w(%X) = %02X\n", machine().describe_context(), banshee.vga[0x3c4 & 0x1f], data);
4865	4794	break;
4866	4795
4867	4796	/* Graphics controller access */
4868	4797	case 0x3cf:
4869		if (v->banshee.vga[0x3ce & 0x1f] < ARRAY_LENGTH(v->banshee.gc))
4870		v->banshee.gc[v->banshee.vga[0x3ce & 0x1f]] = data;
	4798	if (banshee.vga[0x3ce & 0x1f] < ARRAY_LENGTH(banshee.gc))
	4799	banshee.gc[banshee.vga[0x3ce & 0x1f]] = data;
4871	4800	if (LOG_REGISTERS)
4872		logerror("%s:banshee_gc_w(%X) = %02X\n", machine().describe_context(), ~~v->~~banshee.vga[0x3ce & 0x1f], data);
	4801	logerror("%s:banshee_gc_w(%X) = %02X\n", machine().describe_context(), banshee.vga[0x3ce & 0x1f], data);
4873	4802	break;
4874	4803
4875	4804	/* CRTC access */
4876	4805	case 0x3d5:
4877		if (v->banshee.vga[0x3d4 & 0x1f] < ARRAY_LENGTH(v->banshee.crtc))
4878		v->banshee.crtc[v->banshee.vga[0x3d4 & 0x1f]] = data;
	4806	if (banshee.vga[0x3d4 & 0x1f] < ARRAY_LENGTH(banshee.crtc))
	4807	banshee.crtc[banshee.vga[0x3d4 & 0x1f]] = data;
4879	4808	if (LOG_REGISTERS)
4880		logerror("%s:banshee_crtc_w(%X) = %02X\n", machine().describe_context(), ~~v->~~banshee.vga[0x3d4 & 0x1f], data);
	4809	logerror("%s:banshee_crtc_w(%X) = %02X\n", machine().describe_context(), banshee.vga[0x3d4 & 0x1f], data);
4881	4810	break;
4882	4811
4883	4812	default:
4884		~~v->~~banshee.vga[offset] = data;
	4813	banshee.vga[offset] = data;
4885	4814	if (LOG_REGISTERS)
4886	4815	logerror("%s:banshee_vga_w(%X) = %02X\n", machine().describe_context(), 0x3c0+offset, data);
4887	4816	break;
r253153	r253154
4891	4820
4892	4821	WRITE32_MEMBER( voodoo_banshee_device::banshee_io_w )
4893	4822	{
4894		voodoo_state *v = get_safe_token(this);
4895	4823	UINT32 old;
4896	4824
4897	4825	offset &= 0xff/4;
4898		old = ~~v->~~banshee.io[offset];
	4826	old = banshee.io[offset];
4899	4827
4900	4828	/* switch off the offset */
4901	4829	switch (offset)
4902	4830	{
4903	4831	case io_vidProcCfg:
4904		COMBINE_DATA(&v->banshee.io[offset]);
4905		if ((v->banshee.io[offset] ^ old) & 0x2800)
4906		v->fbi.clut_dirty = TRUE;
	4832	COMBINE_DATA(&banshee.io[offset]);
	4833	if ((banshee.io[offset] ^ old) & 0x2800)
	4834	fbi.clut_dirty = TRUE;
4907	4835	if (LOG_REGISTERS)
4908	4836	logerror("%s:banshee_io_w(%s) = %08X & %08X\n", machine().describe_context(), banshee_io_reg_name[offset], data, mem_mask);
4909	4837	break;
4910	4838
4911	4839	case io_dacData:
4912		COMBINE_DATA(&v->banshee.io[offset]);
4913		if (v->banshee.io[offset] != v->fbi.clut[v->banshee.io[io_dacAddr] & 0x1ff])
	4840	COMBINE_DATA(&banshee.io[offset]);
	4841	if (banshee.io[offset] != fbi.clut[banshee.io[io_dacAddr] & 0x1ff])
4914	4842	{
4915		v->fbi.clut[v->banshee.io[io_dacAddr] & 0x1ff] = v->banshee.io[offset];
4916		v->fbi.clut_dirty = TRUE;
	4843	fbi.clut[banshee.io[io_dacAddr] & 0x1ff] = banshee.io[offset];
	4844	fbi.clut_dirty = TRUE;
4917	4845	}
4918	4846	if (LOG_REGISTERS)
4919		logerror("%s:banshee_dac_w(%X) = %08X & %08X\n", machine().describe_context(), ~~v->~~banshee.io[io_dacAddr] & 0x1ff, data, mem_mask);
	4847	logerror("%s:banshee_dac_w(%X) = %08X & %08X\n", machine().describe_context(), banshee.io[io_dacAddr] & 0x1ff, data, mem_mask);
4920	4848	break;
4921	4849
4922	4850	case io_miscInit0:
4923		COMBINE_DATA(&v->banshee.io[offset]);
4924		v->fbi.yorigin = (data >> 18) & 0xfff;
	4851	COMBINE_DATA(&banshee.io[offset]);
	4852	fbi.yorigin = (data >> 18) & 0xfff;
4925	4853	if (LOG_REGISTERS)
4926	4854	logerror("%s:banshee_io_w(%s) = %08X & %08X\n", machine().describe_context(), banshee_io_reg_name[offset], data, mem_mask);
4927	4855	break;
4928	4856
4929	4857	case io_vidScreenSize:
4930	4858	if (data & 0xfff)
4931		~~v->~~fbi.width = data & 0xfff;
	4859	fbi.width = data & 0xfff;
4932	4860	if (data & 0xfff000)
4933		~~v->~~fbi.height = (data >> 12) & 0xfff;
	4861	fbi.height = (data >> 12) & 0xfff;
4934	4862	/* fall through */
4935	4863	case io_vidOverlayDudx:
4936	4864	case io_vidOverlayDvdy:
4937	4865	{
4938	4866	/* warning: this is a hack for now! We should really compute the screen size */
4939	4867	/* from the CRTC registers */
4940		COMBINE_DATA(&~~v->~~banshee.io[offset]);
	4868	COMBINE_DATA(&banshee.io[offset]);
4941	4869
4942		int width = v->fbi.width;
4943		int height = v->fbi.height;
	4870	int width = fbi.width;
	4871	int height = fbi.height;
4944	4872
4945		if (v->banshee.io[io_vidOverlayDudx] != 0)
4946		width = (v->fbi.width * v->banshee.io[io_vidOverlayDudx]) / 1048576;
4947		if (v->banshee.io[io_vidOverlayDvdy] != 0)
4948		height = (v->fbi.height * v->banshee.io[io_vidOverlayDvdy]) / 1048576;
	4873	if (banshee.io[io_vidOverlayDudx] != 0)
	4874	width = (fbi.width * banshee.io[io_vidOverlayDudx]) / 1048576;
	4875	if (banshee.io[io_vidOverlayDvdy] != 0)
	4876	height = (fbi.height * banshee.io[io_vidOverlayDvdy]) / 1048576;
4949	4877
4950		~~v->~~screen->set_visible_area(0, width - 1, 0, height - 1);
	4878	screen->set_visible_area(0, width - 1, 0, height - 1);
4951	4879
4952		adjust_vblank_timer(v);
	4880	adjust_vblank_timer(this);
4953	4881	if (LOG_REGISTERS)
4954	4882	logerror("%s:banshee_io_w(%s) = %08X & %08X\n", machine().describe_context(), banshee_io_reg_name[offset], data, mem_mask);
4955	4883	break;
4956	4884	}
4957	4885
4958	4886	case io_lfbMemoryConfig:
4959		v->fbi.lfb_base = (data & 0x1fff) << (12-2);
4960		v->fbi.lfb_stride = ((data >> 13) & 7) + 9;
	4887	fbi.lfb_base = (data & 0x1fff) << (12-2);
	4888	fbi.lfb_stride = ((data >> 13) & 7) + 9;
4961	4889	if (LOG_REGISTERS)
4962	4890	logerror("%s:banshee_io_w(%s) = %08X & %08X\n", machine().describe_context(), banshee_io_reg_name[offset], data, mem_mask);
4963	4891	break;
r253153	r253154
4976	4904	break;
4977	4905
4978	4906	default:
4979		COMBINE_DATA(&~~v->~~banshee.io[offset]);
	4907	COMBINE_DATA(&banshee.io[offset]);
4980	4908	if (LOG_REGISTERS)
4981	4909	logerror("%s:banshee_io_w(%s) = %08X & %08X\n", machine().describe_context(), banshee_io_reg_name[offset], data, mem_mask);
4982	4910	break;
r253153	r253154
4995	4923
4996	4924	void voodoo_device::common_start_voodoo(UINT8 type)
4997	4925	{
4998		voodoo_state *v = get_safe_token(this);
4999	4926	const raster_info *info;
5000	4927	void fbmem, tmumem[2];
5001	4928	UINT32 tmumem0, tmumem1;
r253153	r253154
5007	4934	assert(m_fbmem > 0);
5008	4935
5009	4936	/* store a pointer back to the device */
5010		v->device = this;
5011		v->type = type;
	4937	device = this;
	4938	vd_type = type;
5012	4939
5013	4940	/* copy config data */
5014		v->freq = clock();
5015		v->device->m_vblank.resolve();
5016		v->device->m_stall.resolve();
	4941	freq = clock();
	4942	device->m_vblank.resolve();
	4943	device->m_stall.resolve();
5017	4944
5018	4945	/* create a multiprocessor work queue */
5019		v->poly = poly_alloc(machine(), 64, sizeof(poly_extra_data), 0);
5020		v->thread_stats = auto_alloc_array(machine(), stats_block, WORK_MAX_THREADS);
	4946	poly = poly_alloc(machine(), 64, sizeof(poly_extra_data), 0);
	4947	thread_stats = auto_alloc_array(machine(), stats_block, WORK_MAX_THREADS);
5021	4948
5022	4949	/* create a table of precomputed 1/n and log2(n) values */
5023	4950	/* n ranges from 1.0000 to 2.0000 */
r253153	r253154
5048	4975	}
5049	4976	}
5050	4977
5051		~~v->~~tmu_config = 0x11; // revision 1
	4978	tmu_config = 0x11; // revision 1
5052	4979
5053	4980	/* configure type-specific values */
5054		switch (v->type)
	4981	switch (vd_type)
5055	4982	{
5056	4983	case TYPE_VOODOO_1:
5057		v->regaccess = voodoo_register_access;
5058		v->regnames = voodoo_reg_name;
5059		v->alt_regmap = 0;
5060		v->fbi.lfb_stride = 10;
	4984	regaccess = voodoo_register_access;
	4985	regnames = voodoo_reg_name;
	4986	alt_regmap = 0;
	4987	fbi.lfb_stride = 10;
5061	4988	break;
5062	4989
5063	4990	case TYPE_VOODOO_2:
5064		v->regaccess = voodoo2_register_access;
5065		v->regnames = voodoo_reg_name;
5066		v->alt_regmap = 0;
5067		v->fbi.lfb_stride = 10;
5068		v->tmu_config \|= 0x800;
	4991	regaccess = voodoo2_register_access;
	4992	regnames = voodoo_reg_name;
	4993	alt_regmap = 0;
	4994	fbi.lfb_stride = 10;
	4995	tmu_config \|= 0x800;
5069	4996	break;
5070	4997
5071	4998	case TYPE_VOODOO_BANSHEE:
5072		v->regaccess = banshee_register_access;
5073		v->regnames = banshee_reg_name;
5074		v->alt_regmap = 1;
5075		v->fbi.lfb_stride = 11;
	4999	regaccess = banshee_register_access;
	5000	regnames = banshee_reg_name;
	5001	alt_regmap = 1;
	5002	fbi.lfb_stride = 11;
5076	5003	break;
5077	5004
5078	5005	case TYPE_VOODOO_3:
5079		v->regaccess = banshee_register_access;
5080		v->regnames = banshee_reg_name;
5081		v->alt_regmap = 1;
5082		v->fbi.lfb_stride = 11;
	5006	regaccess = banshee_register_access;
	5007	regnames = banshee_reg_name;
	5008	alt_regmap = 1;
	5009	fbi.lfb_stride = 11;
5083	5010	break;
5084	5011
5085	5012	default:
r253153	r253154
5088	5015
5089	5016	/* set the type, and initialize the chip mask */
5090	5017	device_iterator iter(machine().root_device());
5091		~~v->~~index = 0;
	5018	index = 0;
5092	5019	for (device_t *scan = iter.first(); scan != nullptr; scan = iter.next())
5093	5020	if (scan->type() == this->type())
5094	5021	{
5095	5022	if (scan == this)
5096	5023	break;
5097		~~v->~~index++;
	5024	index++;
5098	5025	}
5099		v->screen = downcast<screen_device *>(machine().device(m_screen));
5100		assert_always(v->screen != nullptr, "Unable to find screen attached to voodoo");
5101		v->cpu = machine().device(m_cputag);
5102		assert_always(v->cpu != nullptr, "Unable to find CPU attached to voodoo");
	5026	screen = downcast<screen_device *>(machine().device(m_screen));
	5027	assert_always(screen != nullptr, "Unable to find screen attached to voodoo");
	5028	cpu = machine().device(m_cputag);
	5029	assert_always(cpu != nullptr, "Unable to find CPU attached to voodoo");
5103	5030
5104	5031	if (m_tmumem1 != 0)
5105		~~v->~~tmu_config \|= 0xc0; // two TMUs
	5032	tmu_config \|= 0xc0; // two TMUs
5106	5033
5107		v->chipmask = 0x01;
5108		v->attoseconds_per_cycle = ATTOSECONDS_PER_SECOND / v->freq;
5109		v->trigger = 51324 + v->index;
	5034	chipmask = 0x01;
	5035	attoseconds_per_cycle = ATTOSECONDS_PER_SECOND / freq;
	5036	trigger = 51324 + index;
5110	5037
5111	5038	/* build the rasterizer table */
5112	5039	for (info = predef_raster_table; info->callback; info++)
5113		add_rasterizer(v, info);
	5040	add_rasterizer(this, info);
5114	5041
5115	5042	/* set up the PCI FIFO */
5116		v->pci.fifo.base = v->pci.fifo_mem;
5117		v->pci.fifo.size = 64*2;
5118		v->pci.fifo.in = v->pci.fifo.out = 0;
5119		v->pci.stall_state = NOT_STALLED;
5120		v->pci.continue_timer = machine().scheduler().timer_alloc(FUNC(stall_cpu_callback), v);
5121
	5043	pci.fifo.base = pci.fifo_mem;
	5044	pci.fifo.size = 64*2;
	5045	pci.fifo.in = pci.fifo.out = 0;
	5046	pci.stall_state = NOT_STALLED;
	5047	pci.continue_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(voodoo_device::stall_cpu_callback),this), nullptr);
	5048
5122	5049	/* allocate memory */
5123	5050	tmumem0 = m_tmumem0;
5124	5051	tmumem1 = m_tmumem1;
5125		if (v->type <= TYPE_VOODOO_2)
	5052	if (vd_type <= TYPE_VOODOO_2)
5126	5053	{
5127	5054	/* separate FB/TMU memory */
5128	5055	fbmem = auto_alloc_array(machine(), UINT8, m_fbmem << 20);
r253153	r253154
5134	5061	/* shared memory */
5135	5062	tmumem[0] = tmumem[1] = fbmem = auto_alloc_array(machine(), UINT8, m_fbmem << 20);
5136	5063	tmumem0 = m_fbmem;
5137		if (v->type == TYPE_VOODOO_3)
	5064	if (vd_type == TYPE_VOODOO_3)
5138	5065	tmumem1 = m_fbmem;
5139	5066	}
5140	5067
5141	5068	/* set up frame buffer */
5142		init_fbi(v, &~~v->~~fbi, fbmem, m_fbmem << 20);
	5069	init_fbi(this, &fbi, fbmem, m_fbmem << 20);
5143	5070
5144	5071	/* build shared TMU tables */
5145		init_tmu_shared(&~~v->~~tmushare);
	5072	init_tmu_shared(&tmushare);
5146	5073
5147	5074	/* set up the TMUs */
5148		init_tmu(v, &v->tmu[0], &v->reg[0x100], tmumem[0], tmumem0 << 20);
5149		v->chipmask \|= 0x02;
	5075	init_tmu(this, &tmu[0], &reg[0x100], tmumem[0], tmumem0 << 20);
	5076	chipmask \|= 0x02;
5150	5077	if (tmumem1 != 0)
5151	5078	{
5152		init_tmu(v, &v->tmu[1], &v->reg[0x200], tmumem[1], tmumem1 << 20);
5153		v->chipmask \|= 0x04;
5154		v->tmu_config \|= 0x40;
	5079	init_tmu(this, &tmu[1], &reg[0x200], tmumem[1], tmumem1 << 20);
	5080	chipmask \|= 0x04;
	5081	tmu_config \|= 0x40;
5155	5082	}
5156	5083
5157	5084	/* initialize some registers */
5158		memset(v->reg, 0, sizeof(v->reg));
5159		v->pci.init_enable = 0;
5160		v->reg[fbiInit0].u = (1 << 4) \| (0x10 << 6);
5161		v->reg[fbiInit1].u = (1 << 1) \| (1 << 8) \| (1 << 12) \| (2 << 20);
5162		v->reg[fbiInit2].u = (1 << 6) \| (0x100 << 23);
5163		v->reg[fbiInit3].u = (2 << 13) \| (0xf << 17);
5164		v->reg[fbiInit4].u = (1 << 0);
	5085	memset(reg, 0, sizeof(reg));
	5086	pci.init_enable = 0;
	5087	reg[fbiInit0].u = (1 << 4) \| (0x10 << 6);
	5088	reg[fbiInit1].u = (1 << 1) \| (1 << 8) \| (1 << 12) \| (2 << 20);
	5089	reg[fbiInit2].u = (1 << 6) \| (0x100 << 23);
	5090	reg[fbiInit3].u = (2 << 13) \| (0xf << 17);
	5091	reg[fbiInit4].u = (1 << 0);
5165	5092
5166	5093	/* initialize banshee registers */
5167		memset(v->banshee.io, 0, sizeof(v->banshee.io));
5168		v->banshee.io[io_pciInit0] = 0x01800040;
5169		v->banshee.io[io_sipMonitor] = 0x40000000;
5170		v->banshee.io[io_lfbMemoryConfig] = 0x000a2200;
5171		v->banshee.io[io_dramInit0] = 0x00579d29;
5172		v->banshee.io[io_dramInit0] \|= 0x08000000; // Konami Viper expects 16MBit SGRAMs
5173		v->banshee.io[io_dramInit1] = 0x00f02200;
5174		v->banshee.io[io_tmuGbeInit] = 0x00000bfb;
	5094	memset(banshee.io, 0, sizeof(banshee.io));
	5095	banshee.io[io_pciInit0] = 0x01800040;
	5096	banshee.io[io_sipMonitor] = 0x40000000;
	5097	banshee.io[io_lfbMemoryConfig] = 0x000a2200;
	5098	banshee.io[io_dramInit0] = 0x00579d29;
	5099	banshee.io[io_dramInit0] \|= 0x08000000; // Konami Viper expects 16MBit SGRAMs
	5100	banshee.io[io_dramInit1] = 0x00f02200;
	5101	banshee.io[io_tmuGbeInit] = 0x00000bfb;
5175	5102
5176	5103	/* do a soft reset to reset everything else */
5177		soft_reset(v);
	5104	soft_reset(this);
5178	5105
5179	5106	/* register for save states */
5180	5107	init_save_state(this);
r253153	r253154
5191	5118	command
5192	5119	-------------------------------------------------*/
5193	5120
5194		~~static~~ INT32 fastfill(voodoo_~~stat~~e *v)
	5121	INT32 voodoo_device::fastfill(voodoo_device *vd)
5195	5122	{
5196		int sx = (v->reg[clipLeftRight].u >> 16) & 0x3ff;
5197		int ex = (v->reg[clipLeftRight].u >> 0) & 0x3ff;
5198		int sy = (v->reg[clipLowYHighY].u >> 16) & 0x3ff;
5199		int ey = (v->reg[clipLowYHighY].u >> 0) & 0x3ff;
	5123	int sx = (vd->reg[clipLeftRight].u >> 16) & 0x3ff;
	5124	int ex = (vd->reg[clipLeftRight].u >> 0) & 0x3ff;
	5125	int sy = (vd->reg[clipLowYHighY].u >> 16) & 0x3ff;
	5126	int ey = (vd->reg[clipLowYHighY].u >> 0) & 0x3ff;
5200	5127	poly_extent extents[64];
5201	5128	UINT16 dithermatrix[16];
5202	5129	UINT16 *drawbuf = nullptr;
r253153	r253154
5204	5131	int extnum, x, y;
5205	5132
5206	5133	/* if we're not clearing either, take no time */
5207		if (!FBZMODE_RGB_BUFFER_MASK(v->reg[fbzMode].u) && !FBZMODE_AUX_BUFFER_MASK(v->reg[fbzMode].u))
	5134	if (!FBZMODE_RGB_BUFFER_MASK(vd->reg[fbzMode].u) && !FBZMODE_AUX_BUFFER_MASK(vd->reg[fbzMode].u))
5208	5135	return 0;
5209	5136
5210	5137	/* are we clearing the RGB buffer? */
5211		if (FBZMODE_RGB_BUFFER_MASK(v->reg[fbzMode].u))
	5138	if (FBZMODE_RGB_BUFFER_MASK(vd->reg[fbzMode].u))
5212	5139	{
5213	5140	/* determine the draw buffer */
5214		int destbuf = (v->type >= TYPE_VOODOO_BANSHEE) ? 1 : FBZMODE_DRAW_BUFFER(v->reg[fbzMode].u);
	5141	int destbuf = (vd->vd_type >= TYPE_VOODOO_BANSHEE) ? 1 : FBZMODE_DRAW_BUFFER(vd->reg[fbzMode].u);
5215	5142	switch (destbuf)
5216	5143	{
5217	5144	case 0: /* front buffer */
5218		drawbuf = (UINT16 *)(v->fbi.ram + v->fbi.rgboffs[v->fbi.frontbuf]);
	5145	drawbuf = (UINT16 *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.frontbuf]);
5219	5146	break;
5220	5147
5221	5148	case 1: /* back buffer */
5222		drawbuf = (UINT16 *)(v->fbi.ram + v->fbi.rgboffs[v->fbi.backbuf]);
	5149	drawbuf = (UINT16 *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.backbuf]);
5223	5150	break;
5224	5151
5225	5152	default: /* reserved */
r253153	r253154
5230	5157	for (y = 0; y < 4; y++)
5231	5158	{
5232	5159	DECLARE_DITHER_POINTERS_NO_DITHER_VAR;
5233		COMPUTE_DITHER_POINTERS_NO_DITHER_VAR(v->reg[fbzMode].u, y);
	5160	COMPUTE_DITHER_POINTERS_NO_DITHER_VAR(vd->reg[fbzMode].u, y);
5234	5161	for (x = 0; x < 4; x++)
5235	5162	{
5236		int r = v->reg[color1].rgb.r;
5237		int g = v->reg[color1].rgb.g;
5238		int b = v->reg[color1].rgb.b;
	5163	int r = vd->reg[color1].rgb.r;
	5164	int g = vd->reg[color1].rgb.g;
	5165	int b = vd->reg[color1].rgb.b;
5239	5166
5240		APPLY_DITHER(v->reg[fbzMode].u, x, dither_lookup, r, g, b);
	5167	APPLY_DITHER(vd->reg[fbzMode].u, x, dither_lookup, r, g, b);
5241	5168	dithermatrix[y*4 + x] = (r << 11) \| (g << 5) \| b;
5242	5169	}
5243	5170	}
r253153	r253154
5252	5179	/* iterate over blocks of extents */
5253	5180	for (y = sy; y < ey; y += ARRAY_LENGTH(extents))
5254	5181	{
5255		poly_extra_data extra = (poly_extra_data )poly_get_extra_data(v->poly);
	5182	poly_extra_data extra = (poly_extra_data )poly_get_extra_data(vd->poly);
5256	5183	int count = MIN(ey - y, ARRAY_LENGTH(extents));
5257	5184
5258		extra->~~stat~~e = v;
	5185	extra->device= vd;
5259	5186	memcpy(extra->dither, dithermatrix, sizeof(extra->dither));
5260	5187
5261		pixels += poly_render_triangle_custom(v->poly, drawbuf, global_cliprect, raster_fastfill, y, count, extents);
	5188	pixels += poly_render_triangle_custom(vd->poly, drawbuf, global_cliprect, raster_fastfill, y, count, extents);
5262	5189	}
5263	5190
5264	5191	/* 2 pixels per clock */
r253153	r253154
5271	5198	command
5272	5199	-------------------------------------------------*/
5273	5200
5274		~~static~~ INT32 swapbuffer(voodoo_~~stat~~e *v, UINT32 data)
	5201	INT32 voodoo_device::swapbuffer(voodoo_device* vd, UINT32 data)
5275	5202	{
5276	5203	/* set the don't swap value for Voodoo 2 */
5277		v->fbi.vblank_swap_pending = TRUE;
5278		v->fbi.vblank_swap = (data >> 1) & 0xff;
5279		v->fbi.vblank_dont_swap = (data >> 9) & 1;
	5204	vd->fbi.vblank_swap_pending = TRUE;
	5205	vd->fbi.vblank_swap = (data >> 1) & 0xff;
	5206	vd->fbi.vblank_dont_swap = (data >> 9) & 1;
5280	5207
5281	5208	/* if we're not syncing to the retrace, process the command immediately */
5282	5209	if (!(data & 1))
5283	5210	{
5284		swap_buffers(v);
	5211	swap_buffers(vd);
5285	5212	return 0;
5286	5213	}
5287	5214
5288	5215	/* determine how many cycles to wait; we deliberately overshoot here because */
5289	5216	/* the final count gets updated on the VBLANK */
5290		return (v->fbi.vblank_swap + 1) * v->freq / 30;
	5217	return (vd->fbi.vblank_swap + 1) * vd->freq / 30;
5291	5218	}
5292	5219
5293	5220
r253153	r253154
5296	5223	command
5297	5224	-------------------------------------------------*/
5298	5225
5299		~~static~~ INT32 triangle(voodoo_~~stat~~e *v)
	5226	INT32 voodoo_device::triangle(voodoo_device *vd)
5300	5227	{
5301	5228	int texcount;
5302	5229	UINT16 *drawbuf;
r253153	r253154
5307	5234
5308	5235	/* determine the number of TMUs involved */
5309	5236	texcount = 0;
5310		if (!FBIINIT3_DISABLE_TMUS(v->reg[fbiInit3].u) && FBZCP_TEXTURE_ENABLE(v->reg[fbzColorPath].u))
	5237	if (!FBIINIT3_DISABLE_TMUS(vd->reg[fbiInit3].u) && FBZCP_TEXTURE_ENABLE(vd->reg[fbzColorPath].u))
5311	5238	{
5312	5239	texcount = 1;
5313		if (v->chipmask & 0x04)
	5240	if (vd->chipmask & 0x04)
5314	5241	texcount = 2;
5315	5242	}
5316	5243
5317	5244	/* perform subpixel adjustments */
5318		if (FBZCP_CCA_SUBPIXEL_ADJUST(v->reg[fbzColorPath].u))
	5245	if (FBZCP_CCA_SUBPIXEL_ADJUST(vd->reg[fbzColorPath].u))
5319	5246	{
5320		INT32 dx = 8 - (v->fbi.ax & 15);
5321		INT32 dy = 8 - (v->fbi.ay & 15);
	5247	INT32 dx = 8 - (vd->fbi.ax & 15);
	5248	INT32 dy = 8 - (vd->fbi.ay & 15);
5322	5249
5323	5250	/* adjust iterated R,G,B,A and W/Z */
5324		v->fbi.startr += (dy * v->fbi.drdy + dx * v->fbi.drdx) >> 4;
5325		v->fbi.startg += (dy * v->fbi.dgdy + dx * v->fbi.dgdx) >> 4;
5326		v->fbi.startb += (dy * v->fbi.dbdy + dx * v->fbi.dbdx) >> 4;
5327		v->fbi.starta += (dy * v->fbi.dady + dx * v->fbi.dadx) >> 4;
5328		v->fbi.startw += (dy * v->fbi.dwdy + dx * v->fbi.dwdx) >> 4;
5329		v->fbi.startz += mul_32x32_shift(dy, v->fbi.dzdy, 4) + mul_32x32_shift(dx, v->fbi.dzdx, 4);
	5251	vd->fbi.startr += (dy * vd->fbi.drdy + dx * vd->fbi.drdx) >> 4;
	5252	vd->fbi.startg += (dy * vd->fbi.dgdy + dx * vd->fbi.dgdx) >> 4;
	5253	vd->fbi.startb += (dy * vd->fbi.dbdy + dx * vd->fbi.dbdx) >> 4;
	5254	vd->fbi.starta += (dy * vd->fbi.dady + dx * vd->fbi.dadx) >> 4;
	5255	vd->fbi.startw += (dy * vd->fbi.dwdy + dx * vd->fbi.dwdx) >> 4;
	5256	vd->fbi.startz += mul_32x32_shift(dy, vd->fbi.dzdy, 4) + mul_32x32_shift(dx, vd->fbi.dzdx, 4);
5330	5257
5331	5258	/* adjust iterated W/S/T for TMU 0 */
5332	5259	if (texcount >= 1)
5333	5260	{
5334		v->tmu[0].startw += (dy * v->tmu[0].dwdy + dx * v->tmu[0].dwdx) >> 4;
5335		v->tmu[0].starts += (dy * v->tmu[0].dsdy + dx * v->tmu[0].dsdx) >> 4;
5336		v->tmu[0].startt += (dy * v->tmu[0].dtdy + dx * v->tmu[0].dtdx) >> 4;
	5261	vd->tmu[0].startw += (dy * vd->tmu[0].dwdy + dx * vd->tmu[0].dwdx) >> 4;
	5262	vd->tmu[0].starts += (dy * vd->tmu[0].dsdy + dx * vd->tmu[0].dsdx) >> 4;
	5263	vd->tmu[0].startt += (dy * vd->tmu[0].dtdy + dx * vd->tmu[0].dtdx) >> 4;
5337	5264
5338	5265	/* adjust iterated W/S/T for TMU 1 */
5339	5266	if (texcount >= 2)
5340	5267	{
5341		v->tmu[1].startw += (dy * v->tmu[1].dwdy + dx * v->tmu[1].dwdx) >> 4;
5342		v->tmu[1].starts += (dy * v->tmu[1].dsdy + dx * v->tmu[1].dsdx) >> 4;
5343		v->tmu[1].startt += (dy * v->tmu[1].dtdy + dx * v->tmu[1].dtdx) >> 4;
	5268	vd->tmu[1].startw += (dy * vd->tmu[1].dwdy + dx * vd->tmu[1].dwdx) >> 4;
	5269	vd->tmu[1].starts += (dy * vd->tmu[1].dsdy + dx * vd->tmu[1].dsdx) >> 4;
	5270	vd->tmu[1].startt += (dy * vd->tmu[1].dtdy + dx * vd->tmu[1].dtdx) >> 4;
5344	5271	}
5345	5272	}
5346	5273	}
5347	5274
5348	5275	/* wait for any outstanding work to finish */
5349		// poly_wait(v->poly, "triangle");
	5276	// poly_wait(vd->poly, "triangle");
5350	5277
5351	5278	/* determine the draw buffer */
5352		destbuf = (v->type >= TYPE_VOODOO_BANSHEE) ? 1 : FBZMODE_DRAW_BUFFER(v->reg[fbzMode].u);
	5279	destbuf = (vd->vd_type >= TYPE_VOODOO_BANSHEE) ? 1 : FBZMODE_DRAW_BUFFER(vd->reg[fbzMode].u);
5353	5280	switch (destbuf)
5354	5281	{
5355	5282	case 0: /* front buffer */
5356		drawbuf = (UINT16 *)(v->fbi.ram + v->fbi.rgboffs[v->fbi.frontbuf]);
5357		v->fbi.video_changed = TRUE;
	5283	drawbuf = (UINT16 *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.frontbuf]);
	5284	vd->fbi.video_changed = TRUE;
5358	5285	break;
5359	5286
5360	5287	case 1: /* back buffer */
5361		drawbuf = (UINT16 *)(v->fbi.ram + v->fbi.rgboffs[v->fbi.backbuf]);
	5288	drawbuf = (UINT16 *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.backbuf]);
5362	5289	break;
5363	5290
5364	5291	default: /* reserved */
r253153	r253154
5366	5293	}
5367	5294
5368	5295	/* find a rasterizer that matches our current state */
5369		pixels = triangle_create_work_item(v, drawbuf, texcount);
	5296	pixels = triangle_create_work_item(vd, drawbuf, texcount);
5370	5297
5371	5298	/* update stats */
5372		v->reg[fbiTrianglesOut].u++;
	5299	vd->reg[fbiTrianglesOut].u++;
5373	5300
5374	5301	/* update stats */
5375		v->stats.total_triangles++;
	5302	vd->stats.total_triangles++;
5376	5303
5377	5304	g_profiler.stop();
5378	5305
5379	5306	/* 1 pixel per clock, plus some setup time */
5380		if (LOG_REGISTERS) v->device->logerror("cycles = %d\n", TRIANGLE_SETUP_CLOCKS + pixels);
	5307	if (LOG_REGISTERS) vd->device->logerror("cycles = %d\n", TRIANGLE_SETUP_CLOCKS + pixels);
5381	5308	return TRIANGLE_SETUP_CLOCKS + pixels;
5382	5309	}
5383	5310
r253153	r253154
5387	5314	command
5388	5315	-------------------------------------------------*/
5389	5316
5390		~~static~~ INT32 begin_triangle(voodoo_~~stat~~e *v)
	5317	INT32 voodoo_device::begin_triangle(voodoo_device *vd)
5391	5318	{
5392		setup_vertex *sv = &v->fbi.svert[2];
	5319	setup_vertex *sv = &vd->fbi.svert[2];
5393	5320
5394	5321	/* extract all the data from registers */
5395		sv->x = v->reg[sVx].f;
5396		sv->y = v->reg[sVy].f;
5397		sv->wb = v->reg[sWb].f;
5398		sv->w0 = v->reg[sWtmu0].f;
5399		sv->s0 = v->reg[sS_W0].f;
5400		sv->t0 = v->reg[sT_W0].f;
5401		sv->w1 = v->reg[sWtmu1].f;
5402		sv->s1 = v->reg[sS_Wtmu1].f;
5403		sv->t1 = v->reg[sT_Wtmu1].f;
5404		sv->a = v->reg[sAlpha].f;
5405		sv->r = v->reg[sRed].f;
5406		sv->g = v->reg[sGreen].f;
5407		sv->b = v->reg[sBlue].f;
	5322	sv->x = vd->reg[sVx].f;
	5323	sv->y = vd->reg[sVy].f;
	5324	sv->wb = vd->reg[sWb].f;
	5325	sv->w0 = vd->reg[sWtmu0].f;
	5326	sv->s0 = vd->reg[sS_W0].f;
	5327	sv->t0 = vd->reg[sT_W0].f;
	5328	sv->w1 = vd->reg[sWtmu1].f;
	5329	sv->s1 = vd->reg[sS_Wtmu1].f;
	5330	sv->t1 = vd->reg[sT_Wtmu1].f;
	5331	sv->a = vd->reg[sAlpha].f;
	5332	sv->r = vd->reg[sRed].f;
	5333	sv->g = vd->reg[sGreen].f;
	5334	sv->b = vd->reg[sBlue].f;
5408	5335
5409	5336	/* spread it across all three verts and reset the count */
5410		v->fbi.svert[0] = v->fbi.svert[1] = v->fbi.svert[2];
5411		v->fbi.sverts = 1;
	5337	vd->fbi.svert[0] = vd->fbi.svert[1] = vd->fbi.svert[2];
	5338	vd->fbi.sverts = 1;
5412	5339
5413	5340	return 0;
5414	5341	}
r253153	r253154
5419	5346	command
5420	5347	-------------------------------------------------*/
5421	5348
5422		~~static~~ INT32 draw_triangle(voodoo_~~stat~~e *v)
	5349	INT32 voodoo_device::draw_triangle(voodoo_device *vd)
5423	5350	{
5424		setup_vertex *sv = &v->fbi.svert[2];
	5351	setup_vertex *sv = &vd->fbi.svert[2];
5425	5352	int cycles = 0;
5426	5353
5427	5354	/* for strip mode, shuffle vertex 1 down to 0 */
5428		if (!(v->reg[sSetupMode].u & (1 << 16)))
5429		v->fbi.svert[0] = v->fbi.svert[1];
	5355	if (!(vd->reg[sSetupMode].u & (1 << 16)))
	5356	vd->fbi.svert[0] = vd->fbi.svert[1];
5430	5357
5431	5358	/* copy 2 down to 1 regardless */
5432		v->fbi.svert[1] = v->fbi.svert[2];
	5359	vd->fbi.svert[1] = vd->fbi.svert[2];
5433	5360
5434	5361	/* extract all the data from registers */
5435		sv->x = v->reg[sVx].f;
5436		sv->y = v->reg[sVy].f;
5437		sv->wb = v->reg[sWb].f;
5438		sv->w0 = v->reg[sWtmu0].f;
5439		sv->s0 = v->reg[sS_W0].f;
5440		sv->t0 = v->reg[sT_W0].f;
5441		sv->w1 = v->reg[sWtmu1].f;
5442		sv->s1 = v->reg[sS_Wtmu1].f;
5443		sv->t1 = v->reg[sT_Wtmu1].f;
5444		sv->a = v->reg[sAlpha].f;
5445		sv->r = v->reg[sRed].f;
5446		sv->g = v->reg[sGreen].f;
5447		sv->b = v->reg[sBlue].f;
	5362	sv->x = vd->reg[sVx].f;
	5363	sv->y = vd->reg[sVy].f;
	5364	sv->wb = vd->reg[sWb].f;
	5365	sv->w0 = vd->reg[sWtmu0].f;
	5366	sv->s0 = vd->reg[sS_W0].f;
	5367	sv->t0 = vd->reg[sT_W0].f;
	5368	sv->w1 = vd->reg[sWtmu1].f;
	5369	sv->s1 = vd->reg[sS_Wtmu1].f;
	5370	sv->t1 = vd->reg[sT_Wtmu1].f;
	5371	sv->a = vd->reg[sAlpha].f;
	5372	sv->r = vd->reg[sRed].f;
	5373	sv->g = vd->reg[sGreen].f;
	5374	sv->b = vd->reg[sBlue].f;
5448	5375
5449	5376	/* if we have enough verts, go ahead and draw */
5450		if (++v->fbi.sverts >= 3)
5451		cycles = setup_and_draw_triangle(v);
	5377	if (++vd->fbi.sverts >= 3)
	5378	cycles = setup_and_draw_triangle(vd);
5452	5379
5453	5380	return cycles;
5454	5381	}
r253153	r253154
5464	5391	parameters and render the triangle
5465	5392	-------------------------------------------------*/
5466	5393
5467		~~static~~ INT32 setup_and_draw_triangle(voodoo_~~stat~~e *v)
	5394	INT32 voodoo_device::setup_and_draw_triangle(voodoo_device *vd)
5468	5395	{
5469	5396	float dx1, dy1, dx2, dy2;
5470	5397	float divisor, tdiv;
5471	5398
5472	5399	/* grab the X/Ys at least */
5473		v->fbi.ax = (INT16)(v->fbi.svert[0].x * 16.0f);
5474		v->fbi.ay = (INT16)(v->fbi.svert[0].y * 16.0f);
5475		v->fbi.bx = (INT16)(v->fbi.svert[1].x * 16.0f);
5476		v->fbi.by = (INT16)(v->fbi.svert[1].y * 16.0f);
5477		v->fbi.cx = (INT16)(v->fbi.svert[2].x * 16.0f);
5478		v->fbi.cy = (INT16)(v->fbi.svert[2].y * 16.0f);
	5400	vd->fbi.ax = (INT16)(vd->fbi.svert[0].x * 16.0f);
	5401	vd->fbi.ay = (INT16)(vd->fbi.svert[0].y * 16.0f);
	5402	vd->fbi.bx = (INT16)(vd->fbi.svert[1].x * 16.0f);
	5403	vd->fbi.by = (INT16)(vd->fbi.svert[1].y * 16.0f);
	5404	vd->fbi.cx = (INT16)(vd->fbi.svert[2].x * 16.0f);
	5405	vd->fbi.cy = (INT16)(vd->fbi.svert[2].y * 16.0f);
5479	5406
5480	5407	/* compute the divisor */
5481		divisor = 1.0f / ((v->fbi.svert[0].x - v->fbi.svert[1].x) * (v->fbi.svert[0].y - v->fbi.svert[2].y) -
5482		(v->fbi.svert[0].x - v->fbi.svert[2].x) * (v->fbi.svert[0].y - v->fbi.svert[1].y));
	5408	divisor = 1.0f / ((vd->fbi.svert[0].x - vd->fbi.svert[1].x) * (vd->fbi.svert[0].y - vd->fbi.svert[2].y) -
	5409	(vd->fbi.svert[0].x - vd->fbi.svert[2].x) * (vd->fbi.svert[0].y - vd->fbi.svert[1].y));
5483	5410
5484	5411	/* backface culling */
5485		if (v->reg[sSetupMode].u & 0x20000)
	5412	if (vd->reg[sSetupMode].u & 0x20000)
5486	5413	{
5487		int culling_sign = (v->reg[sSetupMode].u >> 18) & 1;
	5414	int culling_sign = (vd->reg[sSetupMode].u >> 18) & 1;
5488	5415	int divisor_sign = (divisor < 0);
5489	5416
5490	5417	/* if doing strips and ping pong is enabled, apply the ping pong */
5491		if ((v->reg[sSetupMode].u & 0x90000) == 0x00000)
5492		culling_sign ^= (v->fbi.sverts - 3) & 1;
	5418	if ((vd->reg[sSetupMode].u & 0x90000) == 0x00000)
	5419	culling_sign ^= (vd->fbi.sverts - 3) & 1;
5493	5420
5494	5421	/* if our sign matches the culling sign, we're done for */
5495	5422	if (divisor_sign == culling_sign)
r253153	r253154
5497	5424	}
5498	5425
5499	5426	/* compute the dx/dy values */
5500		dx1 = v->fbi.svert[0].y - v->fbi.svert[2].y;
5501		dx2 = v->fbi.svert[0].y - v->fbi.svert[1].y;
5502		dy1 = v->fbi.svert[0].x - v->fbi.svert[1].x;
5503		dy2 = v->fbi.svert[0].x - v->fbi.svert[2].x;
	5427	dx1 = vd->fbi.svert[0].y - vd->fbi.svert[2].y;
	5428	dx2 = vd->fbi.svert[0].y - vd->fbi.svert[1].y;
	5429	dy1 = vd->fbi.svert[0].x - vd->fbi.svert[1].x;
	5430	dy2 = vd->fbi.svert[0].x - vd->fbi.svert[2].x;
5504	5431
5505	5432	/* set up R,G,B */
5506	5433	tdiv = divisor * 4096.0f;
5507		if (v->reg[sSetupMode].u & (1 << 0))
	5434	if (vd->reg[sSetupMode].u & (1 << 0))
5508	5435	{
5509		v->fbi.startr = (INT32)(v->fbi.svert[0].r * 4096.0f);
5510		v->fbi.drdx = (INT32)(((v->fbi.svert[0].r - v->fbi.svert[1].r) * dx1 - (v->fbi.svert[0].r - v->fbi.svert[2].r) * dx2) * tdiv);
5511		v->fbi.drdy = (INT32)(((v->fbi.svert[0].r - v->fbi.svert[2].r) * dy1 - (v->fbi.svert[0].r - v->fbi.svert[1].r) * dy2) * tdiv);
5512		v->fbi.startg = (INT32)(v->fbi.svert[0].g * 4096.0f);
5513		v->fbi.dgdx = (INT32)(((v->fbi.svert[0].g - v->fbi.svert[1].g) * dx1 - (v->fbi.svert[0].g - v->fbi.svert[2].g) * dx2) * tdiv);
5514		v->fbi.dgdy = (INT32)(((v->fbi.svert[0].g - v->fbi.svert[2].g) * dy1 - (v->fbi.svert[0].g - v->fbi.svert[1].g) * dy2) * tdiv);
5515		v->fbi.startb = (INT32)(v->fbi.svert[0].b * 4096.0f);
5516		v->fbi.dbdx = (INT32)(((v->fbi.svert[0].b - v->fbi.svert[1].b) * dx1 - (v->fbi.svert[0].b - v->fbi.svert[2].b) * dx2) * tdiv);
5517		v->fbi.dbdy = (INT32)(((v->fbi.svert[0].b - v->fbi.svert[2].b) * dy1 - (v->fbi.svert[0].b - v->fbi.svert[1].b) * dy2) * tdiv);
	5436	vd->fbi.startr = (INT32)(vd->fbi.svert[0].r * 4096.0f);
	5437	vd->fbi.drdx = (INT32)(((vd->fbi.svert[0].r - vd->fbi.svert[1].r) * dx1 - (vd->fbi.svert[0].r - vd->fbi.svert[2].r) * dx2) * tdiv);
	5438	vd->fbi.drdy = (INT32)(((vd->fbi.svert[0].r - vd->fbi.svert[2].r) * dy1 - (vd->fbi.svert[0].r - vd->fbi.svert[1].r) * dy2) * tdiv);
	5439	vd->fbi.startg = (INT32)(vd->fbi.svert[0].g * 4096.0f);
	5440	vd->fbi.dgdx = (INT32)(((vd->fbi.svert[0].g - vd->fbi.svert[1].g) * dx1 - (vd->fbi.svert[0].g - vd->fbi.svert[2].g) * dx2) * tdiv);
	5441	vd->fbi.dgdy = (INT32)(((vd->fbi.svert[0].g - vd->fbi.svert[2].g) * dy1 - (vd->fbi.svert[0].g - vd->fbi.svert[1].g) * dy2) * tdiv);
	5442	vd->fbi.startb = (INT32)(vd->fbi.svert[0].b * 4096.0f);
	5443	vd->fbi.dbdx = (INT32)(((vd->fbi.svert[0].b - vd->fbi.svert[1].b) * dx1 - (vd->fbi.svert[0].b - vd->fbi.svert[2].b) * dx2) * tdiv);
	5444	vd->fbi.dbdy = (INT32)(((vd->fbi.svert[0].b - vd->fbi.svert[2].b) * dy1 - (vd->fbi.svert[0].b - vd->fbi.svert[1].b) * dy2) * tdiv);
5518	5445	}
5519	5446
5520	5447	/* set up alpha */
5521		if (v->reg[sSetupMode].u & (1 << 1))
	5448	if (vd->reg[sSetupMode].u & (1 << 1))
5522	5449	{
5523		v->fbi.starta = (INT32)(v->fbi.svert[0].a * 4096.0f);
5524		v->fbi.dadx = (INT32)(((v->fbi.svert[0].a - v->fbi.svert[1].a) * dx1 - (v->fbi.svert[0].a - v->fbi.svert[2].a) * dx2) * tdiv);
5525		v->fbi.dady = (INT32)(((v->fbi.svert[0].a - v->fbi.svert[2].a) * dy1 - (v->fbi.svert[0].a - v->fbi.svert[1].a) * dy2) * tdiv);
	5450	vd->fbi.starta = (INT32)(vd->fbi.svert[0].a * 4096.0f);
	5451	vd->fbi.dadx = (INT32)(((vd->fbi.svert[0].a - vd->fbi.svert[1].a) * dx1 - (vd->fbi.svert[0].a - vd->fbi.svert[2].a) * dx2) * tdiv);
	5452	vd->fbi.dady = (INT32)(((vd->fbi.svert[0].a - vd->fbi.svert[2].a) * dy1 - (vd->fbi.svert[0].a - vd->fbi.svert[1].a) * dy2) * tdiv);
5526	5453	}
5527	5454
5528	5455	/* set up Z */
5529		if (v->reg[sSetupMode].u & (1 << 2))
	5456	if (vd->reg[sSetupMode].u & (1 << 2))
5530	5457	{
5531		v->fbi.startz = (INT32)(v->fbi.svert[0].z * 4096.0f);
5532		v->fbi.dzdx = (INT32)(((v->fbi.svert[0].z - v->fbi.svert[1].z) * dx1 - (v->fbi.svert[0].z - v->fbi.svert[2].z) * dx2) * tdiv);
5533		v->fbi.dzdy = (INT32)(((v->fbi.svert[0].z - v->fbi.svert[2].z) * dy1 - (v->fbi.svert[0].z - v->fbi.svert[1].z) * dy2) * tdiv);
	5458	vd->fbi.startz = (INT32)(vd->fbi.svert[0].z * 4096.0f);
	5459	vd->fbi.dzdx = (INT32)(((vd->fbi.svert[0].z - vd->fbi.svert[1].z) * dx1 - (vd->fbi.svert[0].z - vd->fbi.svert[2].z) * dx2) * tdiv);
	5460	vd->fbi.dzdy = (INT32)(((vd->fbi.svert[0].z - vd->fbi.svert[2].z) * dy1 - (vd->fbi.svert[0].z - vd->fbi.svert[1].z) * dy2) * tdiv);
5534	5461	}
5535	5462
5536	5463	/* set up Wb */
5537	5464	tdiv = divisor * 65536.0f * 65536.0f;
5538		if (v->reg[sSetupMode].u & (1 << 3))
	5465	if (vd->reg[sSetupMode].u & (1 << 3))
5539	5466	{
5540		v->fbi.startw = v->tmu[0].startw = v->tmu[1].startw = (INT64)(v->fbi.svert[0].wb * 65536.0f * 65536.0f);
5541		v->fbi.dwdx = v->tmu[0].dwdx = v->tmu[1].dwdx = ((v->fbi.svert[0].wb - v->fbi.svert[1].wb) * dx1 - (v->fbi.svert[0].wb - v->fbi.svert[2].wb) * dx2) * tdiv;
5542		v->fbi.dwdy = v->tmu[0].dwdy = v->tmu[1].dwdy = ((v->fbi.svert[0].wb - v->fbi.svert[2].wb) * dy1 - (v->fbi.svert[0].wb - v->fbi.svert[1].wb) * dy2) * tdiv;
	5467	vd->fbi.startw = vd->tmu[0].startw = vd->tmu[1].startw = (INT64)(vd->fbi.svert[0].wb * 65536.0f * 65536.0f);
	5468	vd->fbi.dwdx = vd->tmu[0].dwdx = vd->tmu[1].dwdx = ((vd->fbi.svert[0].wb - vd->fbi.svert[1].wb) * dx1 - (vd->fbi.svert[0].wb - vd->fbi.svert[2].wb) * dx2) * tdiv;
	5469	vd->fbi.dwdy = vd->tmu[0].dwdy = vd->tmu[1].dwdy = ((vd->fbi.svert[0].wb - vd->fbi.svert[2].wb) * dy1 - (vd->fbi.svert[0].wb - vd->fbi.svert[1].wb) * dy2) * tdiv;
5543	5470	}
5544	5471
5545	5472	/* set up W0 */
5546		if (v->reg[sSetupMode].u & (1 << 4))
	5473	if (vd->reg[sSetupMode].u & (1 << 4))
5547	5474	{
5548		v->tmu[0].startw = v->tmu[1].startw = (INT64)(v->fbi.svert[0].w0 * 65536.0f * 65536.0f);
5549		v->tmu[0].dwdx = v->tmu[1].dwdx = ((v->fbi.svert[0].w0 - v->fbi.svert[1].w0) * dx1 - (v->fbi.svert[0].w0 - v->fbi.svert[2].w0) * dx2) * tdiv;
5550		v->tmu[0].dwdy = v->tmu[1].dwdy = ((v->fbi.svert[0].w0 - v->fbi.svert[2].w0) * dy1 - (v->fbi.svert[0].w0 - v->fbi.svert[1].w0) * dy2) * tdiv;
	5475	vd->tmu[0].startw = vd->tmu[1].startw = (INT64)(vd->fbi.svert[0].w0 * 65536.0f * 65536.0f);
	5476	vd->tmu[0].dwdx = vd->tmu[1].dwdx = ((vd->fbi.svert[0].w0 - vd->fbi.svert[1].w0) * dx1 - (vd->fbi.svert[0].w0 - vd->fbi.svert[2].w0) * dx2) * tdiv;
	5477	vd->tmu[0].dwdy = vd->tmu[1].dwdy = ((vd->fbi.svert[0].w0 - vd->fbi.svert[2].w0) * dy1 - (vd->fbi.svert[0].w0 - vd->fbi.svert[1].w0) * dy2) * tdiv;
5551	5478	}
5552	5479
5553	5480	/* set up S0,T0 */
5554		if (v->reg[sSetupMode].u & (1 << 5))
	5481	if (vd->reg[sSetupMode].u & (1 << 5))
5555	5482	{
5556		v->tmu[0].starts = v->tmu[1].starts = (INT64)(v->fbi.svert[0].s0 * 65536.0f * 65536.0f);
5557		v->tmu[0].dsdx = v->tmu[1].dsdx = ((v->fbi.svert[0].s0 - v->fbi.svert[1].s0) * dx1 - (v->fbi.svert[0].s0 - v->fbi.svert[2].s0) * dx2) * tdiv;
5558		v->tmu[0].dsdy = v->tmu[1].dsdy = ((v->fbi.svert[0].s0 - v->fbi.svert[2].s0) * dy1 - (v->fbi.svert[0].s0 - v->fbi.svert[1].s0) * dy2) * tdiv;
5559		v->tmu[0].startt = v->tmu[1].startt = (INT64)(v->fbi.svert[0].t0 * 65536.0f * 65536.0f);
5560		v->tmu[0].dtdx = v->tmu[1].dtdx = ((v->fbi.svert[0].t0 - v->fbi.svert[1].t0) * dx1 - (v->fbi.svert[0].t0 - v->fbi.svert[2].t0) * dx2) * tdiv;
5561		v->tmu[0].dtdy = v->tmu[1].dtdy = ((v->fbi.svert[0].t0 - v->fbi.svert[2].t0) * dy1 - (v->fbi.svert[0].t0 - v->fbi.svert[1].t0) * dy2) * tdiv;
	5483	vd->tmu[0].starts = vd->tmu[1].starts = (INT64)(vd->fbi.svert[0].s0 * 65536.0f * 65536.0f);
	5484	vd->tmu[0].dsdx = vd->tmu[1].dsdx = ((vd->fbi.svert[0].s0 - vd->fbi.svert[1].s0) * dx1 - (vd->fbi.svert[0].s0 - vd->fbi.svert[2].s0) * dx2) * tdiv;
	5485	vd->tmu[0].dsdy = vd->tmu[1].dsdy = ((vd->fbi.svert[0].s0 - vd->fbi.svert[2].s0) * dy1 - (vd->fbi.svert[0].s0 - vd->fbi.svert[1].s0) * dy2) * tdiv;
	5486	vd->tmu[0].startt = vd->tmu[1].startt = (INT64)(vd->fbi.svert[0].t0 * 65536.0f * 65536.0f);
	5487	vd->tmu[0].dtdx = vd->tmu[1].dtdx = ((vd->fbi.svert[0].t0 - vd->fbi.svert[1].t0) * dx1 - (vd->fbi.svert[0].t0 - vd->fbi.svert[2].t0) * dx2) * tdiv;
	5488	vd->tmu[0].dtdy = vd->tmu[1].dtdy = ((vd->fbi.svert[0].t0 - vd->fbi.svert[2].t0) * dy1 - (vd->fbi.svert[0].t0 - vd->fbi.svert[1].t0) * dy2) * tdiv;
5562	5489	}
5563	5490
5564	5491	/* set up W1 */
5565		if (v->reg[sSetupMode].u & (1 << 6))
	5492	if (vd->reg[sSetupMode].u & (1 << 6))
5566	5493	{
5567		v->tmu[1].startw = (INT64)(v->fbi.svert[0].w1 * 65536.0f * 65536.0f);
5568		v->tmu[1].dwdx = ((v->fbi.svert[0].w1 - v->fbi.svert[1].w1) * dx1 - (v->fbi.svert[0].w1 - v->fbi.svert[2].w1) * dx2) * tdiv;
5569		v->tmu[1].dwdy = ((v->fbi.svert[0].w1 - v->fbi.svert[2].w1) * dy1 - (v->fbi.svert[0].w1 - v->fbi.svert[1].w1) * dy2) * tdiv;
	5494	vd->tmu[1].startw = (INT64)(vd->fbi.svert[0].w1 * 65536.0f * 65536.0f);
	5495	vd->tmu[1].dwdx = ((vd->fbi.svert[0].w1 - vd->fbi.svert[1].w1) * dx1 - (vd->fbi.svert[0].w1 - vd->fbi.svert[2].w1) * dx2) * tdiv;
	5496	vd->tmu[1].dwdy = ((vd->fbi.svert[0].w1 - vd->fbi.svert[2].w1) * dy1 - (vd->fbi.svert[0].w1 - vd->fbi.svert[1].w1) * dy2) * tdiv;
5570	5497	}
5571	5498
5572	5499	/* set up S1,T1 */
5573		if (v->reg[sSetupMode].u & (1 << 7))
	5500	if (vd->reg[sSetupMode].u & (1 << 7))
5574	5501	{
5575		v->tmu[1].starts = (INT64)(v->fbi.svert[0].s1 * 65536.0f * 65536.0f);
5576		v->tmu[1].dsdx = ((v->fbi.svert[0].s1 - v->fbi.svert[1].s1) * dx1 - (v->fbi.svert[0].s1 - v->fbi.svert[2].s1) * dx2) * tdiv;
5577		v->tmu[1].dsdy = ((v->fbi.svert[0].s1 - v->fbi.svert[2].s1) * dy1 - (v->fbi.svert[0].s1 - v->fbi.svert[1].s1) * dy2) * tdiv;
5578		v->tmu[1].startt = (INT64)(v->fbi.svert[0].t1 * 65536.0f * 65536.0f);
5579		v->tmu[1].dtdx = ((v->fbi.svert[0].t1 - v->fbi.svert[1].t1) * dx1 - (v->fbi.svert[0].t1 - v->fbi.svert[2].t1) * dx2) * tdiv;
5580		v->tmu[1].dtdy = ((v->fbi.svert[0].t1 - v->fbi.svert[2].t1) * dy1 - (v->fbi.svert[0].t1 - v->fbi.svert[1].t1) * dy2) * tdiv;
	5502	vd->tmu[1].starts = (INT64)(vd->fbi.svert[0].s1 * 65536.0f * 65536.0f);
	5503	vd->tmu[1].dsdx = ((vd->fbi.svert[0].s1 - vd->fbi.svert[1].s1) * dx1 - (vd->fbi.svert[0].s1 - vd->fbi.svert[2].s1) * dx2) * tdiv;
	5504	vd->tmu[1].dsdy = ((vd->fbi.svert[0].s1 - vd->fbi.svert[2].s1) * dy1 - (vd->fbi.svert[0].s1 - vd->fbi.svert[1].s1) * dy2) * tdiv;
	5505	vd->tmu[1].startt = (INT64)(vd->fbi.svert[0].t1 * 65536.0f * 65536.0f);
	5506	vd->tmu[1].dtdx = ((vd->fbi.svert[0].t1 - vd->fbi.svert[1].t1) * dx1 - (vd->fbi.svert[0].t1 - vd->fbi.svert[2].t1) * dx2) * tdiv;
	5507	vd->tmu[1].dtdy = ((vd->fbi.svert[0].t1 - vd->fbi.svert[2].t1) * dy1 - (vd->fbi.svert[0].t1 - vd->fbi.svert[1].t1) * dy2) * tdiv;
5581	5508	}
5582	5509
5583	5510	/* draw the triangle */
5584		v->fbi.cheating_allowed = 1;
5585		return triangle(v);
	5511	vd->fbi.cheating_allowed = 1;
	5512	return triangle(vd);
5586	5513	}
5587	5514
5588	5515
r253153	r253154
5591	5518	setup and create the work item
5592	5519	-------------------------------------------------*/
5593	5520
5594		~~static~~ INT32 triangle_create_work_item(voodoo_~~stat~~e v, UINT16 drawbuf, int texcount)
	5521	INT32 voodoo_device::triangle_create_work_item(voodoo_device* vd, UINT16 *drawbuf, int texcount)
5595	5522	{
5596		poly_extra_data extra = (poly_extra_data )poly_get_extra_data(v->poly);
5597		raster_info *info = find_rasterizer(v, texcount);
	5523	poly_extra_data extra = (poly_extra_data )poly_get_extra_data(vd->poly);
	5524
	5525	raster_info *info = find_rasterizer(vd, texcount);
5598	5526	poly_vertex vert[3];
5599	5527
5600	5528	/* fill in the vertex data */
5601		vert[0].x = (float)v->fbi.ax * (1.0f / 16.0f);
5602		vert[0].y = (float)v->fbi.ay * (1.0f / 16.0f);
5603		vert[1].x = (float)v->fbi.bx * (1.0f / 16.0f);
5604		vert[1].y = (float)v->fbi.by * (1.0f / 16.0f);
5605		vert[2].x = (float)v->fbi.cx * (1.0f / 16.0f);
5606		vert[2].y = (float)v->fbi.cy * (1.0f / 16.0f);
	5529	vert[0].x = (float)vd->fbi.ax * (1.0f / 16.0f);
	5530	vert[0].y = (float)vd->fbi.ay * (1.0f / 16.0f);
	5531	vert[1].x = (float)vd->fbi.bx * (1.0f / 16.0f);
	5532	vert[1].y = (float)vd->fbi.by * (1.0f / 16.0f);
	5533	vert[2].x = (float)vd->fbi.cx * (1.0f / 16.0f);
	5534	vert[2].y = (float)vd->fbi.cy * (1.0f / 16.0f);
5607	5535
5608	5536	/* fill in the extra data */
5609		extra->~~stat~~e = v;
	5537	extra->device = vd;
5610	5538	extra->info = info;
5611	5539
5612	5540	/* fill in triangle parameters */
5613		extra->ax = v->fbi.ax;
5614		extra->ay = v->fbi.ay;
5615		extra->startr = v->fbi.startr;
5616		extra->startg = v->fbi.startg;
5617		extra->startb = v->fbi.startb;
5618		extra->starta = v->fbi.starta;
5619		extra->startz = v->fbi.startz;
5620		extra->startw = v->fbi.startw;
5621		extra->drdx = v->fbi.drdx;
5622		extra->dgdx = v->fbi.dgdx;
5623		extra->dbdx = v->fbi.dbdx;
5624		extra->dadx = v->fbi.dadx;
5625		extra->dzdx = v->fbi.dzdx;
5626		extra->dwdx = v->fbi.dwdx;
5627		extra->drdy = v->fbi.drdy;
5628		extra->dgdy = v->fbi.dgdy;
5629		extra->dbdy = v->fbi.dbdy;
5630		extra->dady = v->fbi.dady;
5631		extra->dzdy = v->fbi.dzdy;
5632		extra->dwdy = v->fbi.dwdy;
	5541	extra->ax = vd->fbi.ax;
	5542	extra->ay = vd->fbi.ay;
	5543	extra->startr = vd->fbi.startr;
	5544	extra->startg = vd->fbi.startg;
	5545	extra->startb = vd->fbi.startb;
	5546	extra->starta = vd->fbi.starta;
	5547	extra->startz = vd->fbi.startz;
	5548	extra->startw = vd->fbi.startw;
	5549	extra->drdx = vd->fbi.drdx;
	5550	extra->dgdx = vd->fbi.dgdx;
	5551	extra->dbdx = vd->fbi.dbdx;
	5552	extra->dadx = vd->fbi.dadx;
	5553	extra->dzdx = vd->fbi.dzdx;
	5554	extra->dwdx = vd->fbi.dwdx;
	5555	extra->drdy = vd->fbi.drdy;
	5556	extra->dgdy = vd->fbi.dgdy;
	5557	extra->dbdy = vd->fbi.dbdy;
	5558	extra->dady = vd->fbi.dady;
	5559	extra->dzdy = vd->fbi.dzdy;
	5560	extra->dwdy = vd->fbi.dwdy;
5633	5561
5634	5562	/* fill in texture 0 parameters */
5635	5563	if (texcount > 0)
5636	5564	{
5637		extra->starts0 = v->tmu[0].starts;
5638		extra->startt0 = v->tmu[0].startt;
5639		extra->startw0 = v->tmu[0].startw;
5640		extra->ds0dx = v->tmu[0].dsdx;
5641		extra->dt0dx = v->tmu[0].dtdx;
5642		extra->dw0dx = v->tmu[0].dwdx;
5643		extra->ds0dy = v->tmu[0].dsdy;
5644		extra->dt0dy = v->tmu[0].dtdy;
5645		extra->dw0dy = v->tmu[0].dwdy;
5646		extra->lodbase0 = prepare_tmu(&v->tmu[0]);
5647		v->stats.texture_mode[TEXMODE_FORMAT(v->tmu[0].reg[textureMode].u)]++;
	5565	extra->starts0 = vd->tmu[0].starts;
	5566	extra->startt0 = vd->tmu[0].startt;
	5567	extra->startw0 = vd->tmu[0].startw;
	5568	extra->ds0dx = vd->tmu[0].dsdx;
	5569	extra->dt0dx = vd->tmu[0].dtdx;
	5570	extra->dw0dx = vd->tmu[0].dwdx;
	5571	extra->ds0dy = vd->tmu[0].dsdy;
	5572	extra->dt0dy = vd->tmu[0].dtdy;
	5573	extra->dw0dy = vd->tmu[0].dwdy;
	5574	extra->lodbase0 = prepare_tmu(&vd->tmu[0]);
	5575	vd->stats.texture_mode[TEXMODE_FORMAT(vd->tmu[0].reg[textureMode].u)]++;
5648	5576
5649	5577	/* fill in texture 1 parameters */
5650	5578	if (texcount > 1)
5651	5579	{
5652		extra->starts1 = v->tmu[1].starts;
5653		extra->startt1 = v->tmu[1].startt;
5654		extra->startw1 = v->tmu[1].startw;
5655		extra->ds1dx = v->tmu[1].dsdx;
5656		extra->dt1dx = v->tmu[1].dtdx;
5657		extra->dw1dx = v->tmu[1].dwdx;
5658		extra->ds1dy = v->tmu[1].dsdy;
5659		extra->dt1dy = v->tmu[1].dtdy;
5660		extra->dw1dy = v->tmu[1].dwdy;
5661		extra->lodbase1 = prepare_tmu(&v->tmu[1]);
5662		v->stats.texture_mode[TEXMODE_FORMAT(v->tmu[1].reg[textureMode].u)]++;
	5580	extra->starts1 = vd->tmu[1].starts;
	5581	extra->startt1 = vd->tmu[1].startt;
	5582	extra->startw1 = vd->tmu[1].startw;
	5583	extra->ds1dx = vd->tmu[1].dsdx;
	5584	extra->dt1dx = vd->tmu[1].dtdx;
	5585	extra->dw1dx = vd->tmu[1].dwdx;
	5586	extra->ds1dy = vd->tmu[1].dsdy;
	5587	extra->dt1dy = vd->tmu[1].dtdy;
	5588	extra->dw1dy = vd->tmu[1].dwdy;
	5589	extra->lodbase1 = prepare_tmu(&vd->tmu[1]);
	5590	vd->stats.texture_mode[TEXMODE_FORMAT(vd->tmu[1].reg[textureMode].u)]++;
5663	5591	}
5664	5592	}
5665	5593
5666	5594	/* farm the rasterization out to other threads */
5667	5595	info->polys++;
5668		return poly_render_triangle(v->poly, drawbuf, global_cliprect, info->callback, 0, &vert[0], &vert[1], &vert[2]);
	5596	return poly_render_triangle(vd->poly, drawbuf, global_cliprect, info->callback, 0, &vert[0], &vert[1], &vert[2]);
5669	5597	}
5670	5598
5671	5599
r253153	r253154
5679	5607	hash table
5680	5608	-------------------------------------------------*/
5681	5609
5682		~~static~~ raster_info add_rasterizer(voodoo_~~stat~~e v, const raster_info *cinfo)
	5610	raster_info voodoo_device::add_rasterizer(voodoo_device vd, const raster_info *cinfo)
5683	5611	{
5684		raster_info *info = &v->rasterizer[v->next_rasterizer++];
	5612	raster_info *info = &vd->rasterizer[vd->next_rasterizer++];
5685	5613	int hash = compute_raster_hash(cinfo);
5686	5614
5687		assert_always(v->next_rasterizer <= MAX_RASTERIZERS, "Out of space for new rasterizers!");
	5615	assert_always(vd->next_rasterizer <= MAX_RASTERIZERS, "Out of space for new rasterizers!");
5688	5616
5689	5617	/* make a copy of the info */
5690	5618	info = cinfo;
r253153	r253154
5695	5623	info->hash = hash;
5696	5624
5697	5625	/* hook us into the hash table */
5698		info->next = v->raster_hash[hash];
5699		v->raster_hash[hash] = info;
	5626	info->next = vd->raster_hash[hash];
	5627	vd->raster_hash[hash] = info;
5700	5628
5701	5629	if (LOG_RASTERIZERS)
5702	5630	printf("Adding rasterizer @ %p : cp=%08X am=%08X %08X fbzM=%08X tm0=%08X tm1=%08X (hash=%d)\n",
r253153	r253154
5714	5642	it, creating a new one if necessary
5715	5643	-------------------------------------------------*/
5716	5644
5717		~~static~~ raster_info find_rasterizer(voodoo_~~stat~~e v, int texcount)
	5645	raster_info voodoo_device::find_rasterizer(voodoo_device vd, int texcount)
5718	5646	{
5719	5647	raster_info info, prev = nullptr;
5720	5648	raster_info curinfo;
5721	5649	int hash;
5722	5650
5723	5651	/* build an info struct with all the parameters */
5724		curinfo.eff_color_path = normalize_color_path(v->reg[fbzColorPath].u);
5725		curinfo.eff_alpha_mode = normalize_alpha_mode(v->reg[alphaMode].u);
5726		curinfo.eff_fog_mode = normalize_fog_mode(v->reg[fogMode].u);
5727		curinfo.eff_fbz_mode = normalize_fbz_mode(v->reg[fbzMode].u);
5728		curinfo.eff_tex_mode_0 = (texcount >= 1) ? normalize_tex_mode(v->tmu[0].reg[textureMode].u) : 0xffffffff;
5729		curinfo.eff_tex_mode_1 = (texcount >= 2) ? normalize_tex_mode(v->tmu[1].reg[textureMode].u) : 0xffffffff;
	5652	curinfo.eff_color_path = normalize_color_path(vd->reg[fbzColorPath].u);
	5653	curinfo.eff_alpha_mode = normalize_alpha_mode(vd->reg[alphaMode].u);
	5654	curinfo.eff_fog_mode = normalize_fog_mode(vd->reg[fogMode].u);
	5655	curinfo.eff_fbz_mode = normalize_fbz_mode(vd->reg[fbzMode].u);
	5656	curinfo.eff_tex_mode_0 = (texcount >= 1) ? normalize_tex_mode(vd->tmu[0].reg[textureMode].u) : 0xffffffff;
	5657	curinfo.eff_tex_mode_1 = (texcount >= 2) ? normalize_tex_mode(vd->tmu[1].reg[textureMode].u) : 0xffffffff;
5730	5658
5731	5659	/* compute the hash */
5732	5660	hash = compute_raster_hash(&curinfo);
5733	5661
5734	5662	/* find the appropriate hash entry */
5735		for (info = v->raster_hash[hash]; info; prev = info, info = info->next)
	5663	for (info = vd->raster_hash[hash]; info; prev = info, info = info->next)
5736	5664	if (info->eff_color_path == curinfo.eff_color_path &&
5737	5665	info->eff_alpha_mode == curinfo.eff_alpha_mode &&
5738	5666	info->eff_fog_mode == curinfo.eff_fog_mode &&
r253153	r253154
5744	5672	if (prev)
5745	5673	{
5746	5674	prev->next = info->next;
5747		info->next = v->raster_hash[hash];
5748		v->raster_hash[hash] = info;
	5675	info->next = vd->raster_hash[hash];
	5676	vd->raster_hash[hash] = info;
5749	5677	}
5750	5678
5751	5679	/* return the result */
r253153	r253154
5761	5689	curinfo.next = nullptr;
5762	5690	curinfo.hash = hash;
5763	5691
5764		return add_rasterizer(v, &curinfo);
	5692	return add_rasterizer(vd, &curinfo);
5765	5693	}
5766	5694
5767	5695
r253153	r253154
5770	5698	the current rasterizer usage patterns
5771	5699	-------------------------------------------------*/
5772	5700
5773		~~static~~ void dump_rasterizer_stats(voodoo_~~stat~~e *v)
	5701	void voodoo_device::dump_rasterizer_stats(voodoo_device *vd)
5774	5702	{
5775	5703	static UINT8 display_index;
5776	5704	raster_info cur, best;
r253153	r253154
5786	5714
5787	5715	/* find the highest entry */
5788	5716	for (hash = 0; hash < RASTER_HASH_SIZE; hash++)
5789		for (cur = v->raster_hash[hash]; cur; cur = cur->next)
	5717	for (cur = vd->raster_hash[hash]; cur; cur = cur->next)
5790	5718	if (cur->display != display_index && (best == nullptr \|\| cur->hits > best->hits))
5791	5719	best = cur;
5792	5720
r253153	r253154
5822	5750	m_vblank(*this),
5823	5751	m_stall(*this)
5824	5752	{
5825		m_token = global_alloc_clear<voodoo_state>();
5826	5753	}
5827	5754
5828	5755	voodoo_device::~voodoo_device()
5829	5756	{
5830		global_free(m_token);
5831	5757	}
5832	5758
5833	5759	//-------------------------------------------------
r253153	r253154
5846	5772
5847	5773	void voodoo_device::device_reset()
5848	5774	{
5849		voodoo_state *v = get_safe_token(this);
5850		soft_reset(v);
	5775	soft_reset(this);
5851	5776	}
5852	5777
5853	5778	//-------------------------------------------------
r253153	r253154
5856	5781
5857	5782	void voodoo_device::device_stop()
5858	5783	{
5859		voodoo_state *v = get_safe_token(this);
5860
5861	5784	/* release the work queue, ensuring all work is finished */
5862		if (v->poly != nullptr)
5863		poly_free(v->poly);
	5785	if (poly != nullptr)
	5786	poly_free(poly);
5864	5787	}
5865	5788
5866	5789
r253153	r253154
5947	5870	implementation of the 'fastfill' command
5948	5871	-------------------------------------------------*/
5949	5872
5950		~~static~~ void raster_fastfill(void destbase, INT32 y, const poly_extent extent, const void *extradata, int threadid)
	5873	void voodoo_device::raster_fastfill(void destbase, INT32 y, const poly_extent extent, const void *extradata, int threadid)
5951	5874	{
5952	5875	const poly_extra_data extra = (const poly_extra_data )extradata;
5953		voodoo_state *v = extra->state;
5954		stats_block *stats = &v->thread_stats[threadid];
	5876	voodoo_device* vd = extra->device;
	5877	stats_block *stats = &vd->thread_stats[threadid];
5955	5878	INT32 startx = extent->startx;
5956	5879	INT32 stopx = extent->stopx;
5957	5880	int scry, x;
5958	5881
5959	5882	/* determine the screen Y */
5960	5883	scry = y;
5961		if (FBZMODE_Y_ORIGIN(v->reg[fbzMode].u))
5962		scry = (v->fbi.yorigin - y) & 0x3ff;
	5884	if (FBZMODE_Y_ORIGIN(vd->reg[fbzMode].u))
	5885	scry = (vd->fbi.yorigin - y) & 0x3ff;
5963	5886
5964	5887	/* fill this RGB row */
5965		if (FBZMODE_RGB_BUFFER_MASK(v->reg[fbzMode].u))
	5888	if (FBZMODE_RGB_BUFFER_MASK(vd->reg[fbzMode].u))
5966	5889	{
5967	5890	const UINT16 ditherow = &extra->dither[(y & 3) 4];
5968	5891	UINT64 expanded = (UINT64 )ditherow;
5969		UINT16 dest = (UINT16 )destbase + scry * v->fbi.rowpixels;
	5892	UINT16 dest = (UINT16 )destbase + scry * vd->fbi.rowpixels;
5970	5893
5971	5894	for (x = startx; x < stopx && (x & 3) != 0; x++)
5972	5895	dest[x] = ditherow[x & 3];
r253153	r253154
5978	5901	}
5979	5902
5980	5903	/* fill this dest buffer row */
5981		if (FBZMODE_AUX_BUFFER_MASK(v->reg[fbzMode].u) && v->fbi.auxoffs != ~0)
	5904	if (FBZMODE_AUX_BUFFER_MASK(vd->reg[fbzMode].u) && vd->fbi.auxoffs != ~0)
5982	5905	{
5983		UINT16 color = v->reg[zaColor].u;
	5906	UINT16 color = vd->reg[zaColor].u;
5984	5907	UINT64 expanded = ((UINT64)color << 48) \| ((UINT64)color << 32) \| (color << 16) \| color;
5985		UINT16 dest = (UINT16 )(v->fbi.ram + v->fbi.auxoffs) + scry * v->fbi.rowpixels;
	5908	UINT16 dest = (UINT16 )(vd->fbi.ram + vd->fbi.auxoffs) + scry * vd->fbi.rowpixels;
5986	5909
5987	5910	for (x = startx; x < stopx && (x & 3) != 0; x++)
5988	5911	dest[x] = color;
r253153	r253154
5998	5921	generic_0tmu - generic rasterizer for 0 TMUs
5999	5922	-------------------------------------------------*/
6000	5923
6001		RASTERIZER(generic_0tmu, 0, v->reg[fbzColorPath].u, v->reg[fbzMode].u, v->reg[alphaMode].u,
6002		v->reg[fogMode].u, 0, 0)
	5924	RASTERIZER(generic_0tmu, 0, vd->reg[fbzColorPath].u, vd->reg[fbzMode].u, vd->reg[alphaMode].u,
	5925	vd->reg[fogMode].u, 0, 0)
6003	5926
6004	5927
6005	5928	/*-------------------------------------------------
6006	5929	generic_1tmu - generic rasterizer for 1 TMU
6007	5930	-------------------------------------------------*/
6008	5931
6009		RASTERIZER(generic_1tmu, 1, v->reg[fbzColorPath].u, v->reg[fbzMode].u, v->reg[alphaMode].u,
6010		v->reg[fogMode].u, v->tmu[0].reg[textureMode].u, 0)
	5932	RASTERIZER(generic_1tmu, 1, vd->reg[fbzColorPath].u, vd->reg[fbzMode].u, vd->reg[alphaMode].u,
	5933	vd->reg[fogMode].u, vd->tmu[0].reg[textureMode].u, 0)
6011	5934
6012	5935
6013	5936	/*-------------------------------------------------
6014	5937	generic_2tmu - generic rasterizer for 2 TMUs
6015	5938	-------------------------------------------------*/
6016	5939
6017		RASTERIZER(generic_2tmu, 2, v->reg[fbzColorPath].u, v->reg[fbzMode].u, v->reg[alphaMode].u,
6018		v->reg[fogMode].u, v->tmu[0].reg[textureMode].u, v->tmu[1].reg[textureMode].u)
	5940	RASTERIZER(generic_2tmu, 2, vd->reg[fbzColorPath].u, vd->reg[fbzMode].u, vd->reg[alphaMode].u,
	5941	vd->reg[fogMode].u, vd->tmu[0].reg[textureMode].u, vd->tmu[1].reg[textureMode].u)

trunk/src/devices/video/voodoo.h
r253153	r253154
11	11	#ifndef __VOODOO_H__
12	12	#define __VOODOO_H__
13	13
	14	#include "video/polylgcy.h"
	15
14	16	#pragma once
15	17
16	18
	19	/*************************************
	20	*
	21	* Misc. constants
	22	*
	23	*************************************/
17	24
	25	/* enumeration describing reasons we might be stalled */
	26	enum
	27	{
	28	NOT_STALLED = 0,
	29	STALLED_UNTIL_FIFO_LWM,
	30	STALLED_UNTIL_FIFO_EMPTY
	31	};
	32
	33
	34
	35	// Use old table lookup versus straight double divide
	36	#define USE_FAST_RECIP 0
	37
	38	/* maximum number of TMUs */
	39	#define MAX_TMU 2
	40
	41	/* accumulate operations less than this number of clocks */
	42	#define ACCUMULATE_THRESHOLD 0
	43
	44	/* number of clocks to set up a triangle (just a guess) */
	45	#define TRIANGLE_SETUP_CLOCKS 100
	46
	47	/* maximum number of rasterizers */
	48	#define MAX_RASTERIZERS 1024
	49
	50	/* size of the rasterizer hash table */
	51	#define RASTER_HASH_SIZE 97
	52
	53	/* flags for LFB writes */
	54	#define LFB_RGB_PRESENT 1
	55	#define LFB_ALPHA_PRESENT 2
	56	#define LFB_DEPTH_PRESENT 4
	57	#define LFB_DEPTH_PRESENT_MSW 8
	58
	59	/* flags for the register access array */
	60	#define REGISTER_READ 0x01 /* reads are allowed */
	61	#define REGISTER_WRITE 0x02 /* writes are allowed */
	62	#define REGISTER_PIPELINED 0x04 /* writes are pipelined */
	63	#define REGISTER_FIFO 0x08 /* writes go to FIFO */
	64	#define REGISTER_WRITETHRU 0x10 /* writes are valid even for CMDFIFO */
	65
	66	/* shorter combinations to make the table smaller */
	67	#define REG_R (REGISTER_READ)
	68	#define REG_W (REGISTER_WRITE)
	69	#define REG_WT (REGISTER_WRITE \| REGISTER_WRITETHRU)
	70	#define REG_RW (REGISTER_READ \| REGISTER_WRITE)
	71	#define REG_RWT (REGISTER_READ \| REGISTER_WRITE \| REGISTER_WRITETHRU)
	72	#define REG_RP (REGISTER_READ \| REGISTER_PIPELINED)
	73	#define REG_WP (REGISTER_WRITE \| REGISTER_PIPELINED)
	74	#define REG_RWP (REGISTER_READ \| REGISTER_WRITE \| REGISTER_PIPELINED)
	75	#define REG_RWPT (REGISTER_READ \| REGISTER_WRITE \| REGISTER_PIPELINED \| REGISTER_WRITETHRU)
	76	#define REG_RF (REGISTER_READ \| REGISTER_FIFO)
	77	#define REG_WF (REGISTER_WRITE \| REGISTER_FIFO)
	78	#define REG_RWF (REGISTER_READ \| REGISTER_WRITE \| REGISTER_FIFO)
	79	#define REG_RPF (REGISTER_READ \| REGISTER_PIPELINED \| REGISTER_FIFO)
	80	#define REG_WPF (REGISTER_WRITE \| REGISTER_PIPELINED \| REGISTER_FIFO)
	81	#define REG_RWPF (REGISTER_READ \| REGISTER_WRITE \| REGISTER_PIPELINED \| REGISTER_FIFO)
	82
	83	/* lookup bits is the log2 of the size of the reciprocal/log table */
	84	#define RECIPLOG_LOOKUP_BITS 9
	85
	86	/* input precision is how many fraction bits the input value has; this is a 64-bit number */
	87	#define RECIPLOG_INPUT_PREC 32
	88
	89	/* lookup precision is how many fraction bits each table entry contains */
	90	#define RECIPLOG_LOOKUP_PREC 22
	91
	92	/* output precision is how many fraction bits the result should have */
	93	#define RECIP_OUTPUT_PREC 15
	94	#define LOG_OUTPUT_PREC 8
	95
	96
	97
	98	/*************************************
	99	*
	100	* Register constants
	101	*
	102	*************************************/
	103
	104	/* Codes to the right:
	105	R = readable
	106	W = writeable
	107	P = pipelined
	108	F = goes to FIFO
	109	*/
	110
	111	/* 0x000 */
	112	#define vdstatus (0x000/4) /* R P */
	113	#define intrCtrl (0x004/4) /* RW P -- Voodoo2/Banshee only */
	114	#define vertexAx (0x008/4) /* W PF */
	115	#define vertexAy (0x00c/4) /* W PF */
	116	#define vertexBx (0x010/4) /* W PF */
	117	#define vertexBy (0x014/4) /* W PF */
	118	#define vertexCx (0x018/4) /* W PF */
	119	#define vertexCy (0x01c/4) /* W PF */
	120	#define startR (0x020/4) /* W PF */
	121	#define startG (0x024/4) /* W PF */
	122	#define startB (0x028/4) /* W PF */
	123	#define startZ (0x02c/4) /* W PF */
	124	#define startA (0x030/4) /* W PF */
	125	#define startS (0x034/4) /* W PF */
	126	#define startT (0x038/4) /* W PF */
	127	#define startW (0x03c/4) /* W PF */
	128
	129	/* 0x040 */
	130	#define dRdX (0x040/4) /* W PF */
	131	#define dGdX (0x044/4) /* W PF */
	132	#define dBdX (0x048/4) /* W PF */
	133	#define dZdX (0x04c/4) /* W PF */
	134	#define dAdX (0x050/4) /* W PF */
	135	#define dSdX (0x054/4) /* W PF */
	136	#define dTdX (0x058/4) /* W PF */
	137	#define dWdX (0x05c/4) /* W PF */
	138	#define dRdY (0x060/4) /* W PF */
	139	#define dGdY (0x064/4) /* W PF */
	140	#define dBdY (0x068/4) /* W PF */
	141	#define dZdY (0x06c/4) /* W PF */
	142	#define dAdY (0x070/4) /* W PF */
	143	#define dSdY (0x074/4) /* W PF */
	144	#define dTdY (0x078/4) /* W PF */
	145	#define dWdY (0x07c/4) /* W PF */
	146
	147	/* 0x080 */
	148	#define triangleCMD (0x080/4) /* W PF */
	149	#define fvertexAx (0x088/4) /* W PF */
	150	#define fvertexAy (0x08c/4) /* W PF */
	151	#define fvertexBx (0x090/4) /* W PF */
	152	#define fvertexBy (0x094/4) /* W PF */
	153	#define fvertexCx (0x098/4) /* W PF */
	154	#define fvertexCy (0x09c/4) /* W PF */
	155	#define fstartR (0x0a0/4) /* W PF */
	156	#define fstartG (0x0a4/4) /* W PF */
	157	#define fstartB (0x0a8/4) /* W PF */
	158	#define fstartZ (0x0ac/4) /* W PF */
	159	#define fstartA (0x0b0/4) /* W PF */
	160	#define fstartS (0x0b4/4) /* W PF */
	161	#define fstartT (0x0b8/4) /* W PF */
	162	#define fstartW (0x0bc/4) /* W PF */
	163
	164	/* 0x0c0 */
	165	#define fdRdX (0x0c0/4) /* W PF */
	166	#define fdGdX (0x0c4/4) /* W PF */
	167	#define fdBdX (0x0c8/4) /* W PF */
	168	#define fdZdX (0x0cc/4) /* W PF */
	169	#define fdAdX (0x0d0/4) /* W PF */
	170	#define fdSdX (0x0d4/4) /* W PF */
	171	#define fdTdX (0x0d8/4) /* W PF */
	172	#define fdWdX (0x0dc/4) /* W PF */
	173	#define fdRdY (0x0e0/4) /* W PF */
	174	#define fdGdY (0x0e4/4) /* W PF */
	175	#define fdBdY (0x0e8/4) /* W PF */
	176	#define fdZdY (0x0ec/4) /* W PF */
	177	#define fdAdY (0x0f0/4) /* W PF */
	178	#define fdSdY (0x0f4/4) /* W PF */
	179	#define fdTdY (0x0f8/4) /* W PF */
	180	#define fdWdY (0x0fc/4) /* W PF */
	181
	182	/* 0x100 */
	183	#define ftriangleCMD (0x100/4) /* W PF */
	184	#define fbzColorPath (0x104/4) /* RW PF */
	185	#define fogMode (0x108/4) /* RW PF */
	186	#define alphaMode (0x10c/4) /* RW PF */
	187	#define fbzMode (0x110/4) /* RW F */
	188	#define lfbMode (0x114/4) /* RW F */
	189	#define clipLeftRight (0x118/4) /* RW F */
	190	#define clipLowYHighY (0x11c/4) /* RW F */
	191	#define nopCMD (0x120/4) /* W F */
	192	#define fastfillCMD (0x124/4) /* W F */
	193	#define swapbufferCMD (0x128/4) /* W F */
	194	#define fogColor (0x12c/4) /* W F */
	195	#define zaColor (0x130/4) /* W F */
	196	#define chromaKey (0x134/4) /* W F */
	197	#define chromaRange (0x138/4) /* W F -- Voodoo2/Banshee only */
	198	#define userIntrCMD (0x13c/4) /* W F -- Voodoo2/Banshee only */
	199
	200	/* 0x140 */
	201	#define stipple (0x140/4) /* RW F */
	202	#define color0 (0x144/4) /* RW F */
	203	#define color1 (0x148/4) /* RW F */
	204	#define fbiPixelsIn (0x14c/4) /* R */
	205	#define fbiChromaFail (0x150/4) /* R */
	206	#define fbiZfuncFail (0x154/4) /* R */
	207	#define fbiAfuncFail (0x158/4) /* R */
	208	#define fbiPixelsOut (0x15c/4) /* R */
	209	#define fogTable (0x160/4) /* W F */
	210
	211	/* 0x1c0 */
	212	#define cmdFifoBaseAddr (0x1e0/4) /* RW -- Voodoo2 only */
	213	#define cmdFifoBump (0x1e4/4) /* RW -- Voodoo2 only */
	214	#define cmdFifoRdPtr (0x1e8/4) /* RW -- Voodoo2 only */
	215	#define cmdFifoAMin (0x1ec/4) /* RW -- Voodoo2 only */
	216	#define colBufferAddr (0x1ec/4) /* RW -- Banshee only */
	217	#define cmdFifoAMax (0x1f0/4) /* RW -- Voodoo2 only */
	218	#define colBufferStride (0x1f0/4) /* RW -- Banshee only */
	219	#define cmdFifoDepth (0x1f4/4) /* RW -- Voodoo2 only */
	220	#define auxBufferAddr (0x1f4/4) /* RW -- Banshee only */
	221	#define cmdFifoHoles (0x1f8/4) /* RW -- Voodoo2 only */
	222	#define auxBufferStride (0x1f8/4) /* RW -- Banshee only */
	223
	224	/* 0x200 */
	225	#define fbiInit4 (0x200/4) /* RW -- Voodoo/Voodoo2 only */
	226	#define clipLeftRight1 (0x200/4) /* RW -- Banshee only */
	227	#define vRetrace (0x204/4) /* R -- Voodoo/Voodoo2 only */
	228	#define clipTopBottom1 (0x204/4) /* RW -- Banshee only */
	229	#define backPorch (0x208/4) /* RW -- Voodoo/Voodoo2 only */
	230	#define videoDimensions (0x20c/4) /* RW -- Voodoo/Voodoo2 only */
	231	#define fbiInit0 (0x210/4) /* RW -- Voodoo/Voodoo2 only */
	232	#define fbiInit1 (0x214/4) /* RW -- Voodoo/Voodoo2 only */
	233	#define fbiInit2 (0x218/4) /* RW -- Voodoo/Voodoo2 only */
	234	#define fbiInit3 (0x21c/4) /* RW -- Voodoo/Voodoo2 only */
	235	#define hSync (0x220/4) /* W -- Voodoo/Voodoo2 only */
	236	#define vSync (0x224/4) /* W -- Voodoo/Voodoo2 only */
	237	#define clutData (0x228/4) /* W F -- Voodoo/Voodoo2 only */
	238	#define dacData (0x22c/4) /* W -- Voodoo/Voodoo2 only */
	239	#define maxRgbDelta (0x230/4) /* W -- Voodoo/Voodoo2 only */
	240	#define hBorder (0x234/4) /* W -- Voodoo2 only */
	241	#define vBorder (0x238/4) /* W -- Voodoo2 only */
	242	#define borderColor (0x23c/4) /* W -- Voodoo2 only */
	243
	244	/* 0x240 */
	245	#define hvRetrace (0x240/4) /* R -- Voodoo2 only */
	246	#define fbiInit5 (0x244/4) /* RW -- Voodoo2 only */
	247	#define fbiInit6 (0x248/4) /* RW -- Voodoo2 only */
	248	#define fbiInit7 (0x24c/4) /* RW -- Voodoo2 only */
	249	#define swapPending (0x24c/4) /* W -- Banshee only */
	250	#define leftOverlayBuf (0x250/4) /* W -- Banshee only */
	251	#define rightOverlayBuf (0x254/4) /* W -- Banshee only */
	252	#define fbiSwapHistory (0x258/4) /* R -- Voodoo2/Banshee only */
	253	#define fbiTrianglesOut (0x25c/4) /* R -- Voodoo2/Banshee only */
	254	#define sSetupMode (0x260/4) /* W PF -- Voodoo2/Banshee only */
	255	#define sVx (0x264/4) /* W PF -- Voodoo2/Banshee only */
	256	#define sVy (0x268/4) /* W PF -- Voodoo2/Banshee only */
	257	#define sARGB (0x26c/4) /* W PF -- Voodoo2/Banshee only */
	258	#define sRed (0x270/4) /* W PF -- Voodoo2/Banshee only */
	259	#define sGreen (0x274/4) /* W PF -- Voodoo2/Banshee only */
	260	#define sBlue (0x278/4) /* W PF -- Voodoo2/Banshee only */
	261	#define sAlpha (0x27c/4) /* W PF -- Voodoo2/Banshee only */
	262
	263	/* 0x280 */
	264	#define sVz (0x280/4) /* W PF -- Voodoo2/Banshee only */
	265	#define sWb (0x284/4) /* W PF -- Voodoo2/Banshee only */
	266	#define sWtmu0 (0x288/4) /* W PF -- Voodoo2/Banshee only */
	267	#define sS_W0 (0x28c/4) /* W PF -- Voodoo2/Banshee only */
	268	#define sT_W0 (0x290/4) /* W PF -- Voodoo2/Banshee only */
	269	#define sWtmu1 (0x294/4) /* W PF -- Voodoo2/Banshee only */
	270	#define sS_Wtmu1 (0x298/4) /* W PF -- Voodoo2/Banshee only */
	271	#define sT_Wtmu1 (0x29c/4) /* W PF -- Voodoo2/Banshee only */
	272	#define sDrawTriCMD (0x2a0/4) /* W PF -- Voodoo2/Banshee only */
	273	#define sBeginTriCMD (0x2a4/4) /* W PF -- Voodoo2/Banshee only */
	274
	275	/* 0x2c0 */
	276	#define bltSrcBaseAddr (0x2c0/4) /* RW PF -- Voodoo2 only */
	277	#define bltDstBaseAddr (0x2c4/4) /* RW PF -- Voodoo2 only */
	278	#define bltXYStrides (0x2c8/4) /* RW PF -- Voodoo2 only */
	279	#define bltSrcChromaRange (0x2cc/4) /* RW PF -- Voodoo2 only */
	280	#define bltDstChromaRange (0x2d0/4) /* RW PF -- Voodoo2 only */
	281	#define bltClipX (0x2d4/4) /* RW PF -- Voodoo2 only */
	282	#define bltClipY (0x2d8/4) /* RW PF -- Voodoo2 only */
	283	#define bltSrcXY (0x2e0/4) /* RW PF -- Voodoo2 only */
	284	#define bltDstXY (0x2e4/4) /* RW PF -- Voodoo2 only */
	285	#define bltSize (0x2e8/4) /* RW PF -- Voodoo2 only */
	286	#define bltRop (0x2ec/4) /* RW PF -- Voodoo2 only */
	287	#define bltColor (0x2f0/4) /* RW PF -- Voodoo2 only */
	288	#define bltCommand (0x2f8/4) /* RW PF -- Voodoo2 only */
	289	#define bltData (0x2fc/4) /* W PF -- Voodoo2 only */
	290
	291	/* 0x300 */
	292	#define textureMode (0x300/4) /* W PF */
	293	#define tLOD (0x304/4) /* W PF */
	294	#define tDetail (0x308/4) /* W PF */
	295	#define texBaseAddr (0x30c/4) /* W PF */
	296	#define texBaseAddr_1 (0x310/4) /* W PF */
	297	#define texBaseAddr_2 (0x314/4) /* W PF */
	298	#define texBaseAddr_3_8 (0x318/4) /* W PF */
	299	#define trexInit0 (0x31c/4) /* W F -- Voodoo/Voodoo2 only */
	300	#define trexInit1 (0x320/4) /* W F */
	301	#define nccTable (0x324/4) /* W F */
	302
	303
	304
	305	// 2D registers
	306	#define banshee2D_clip0Min (0x008/4)
	307	#define banshee2D_clip0Max (0x00c/4)
	308	#define banshee2D_dstBaseAddr (0x010/4)
	309	#define banshee2D_dstFormat (0x014/4)
	310	#define banshee2D_srcColorkeyMin (0x018/4)
	311	#define banshee2D_srcColorkeyMax (0x01c/4)
	312	#define banshee2D_dstColorkeyMin (0x020/4)
	313	#define banshee2D_dstColorkeyMax (0x024/4)
	314	#define banshee2D_bresError0 (0x028/4)
	315	#define banshee2D_bresError1 (0x02c/4)
	316	#define banshee2D_rop (0x030/4)
	317	#define banshee2D_srcBaseAddr (0x034/4)
	318	#define banshee2D_commandExtra (0x038/4)
	319	#define banshee2D_lineStipple (0x03c/4)
	320	#define banshee2D_lineStyle (0x040/4)
	321	#define banshee2D_pattern0Alias (0x044/4)
	322	#define banshee2D_pattern1Alias (0x048/4)
	323	#define banshee2D_clip1Min (0x04c/4)
	324	#define banshee2D_clip1Max (0x050/4)
	325	#define banshee2D_srcFormat (0x054/4)
	326	#define banshee2D_srcSize (0x058/4)
	327	#define banshee2D_srcXY (0x05c/4)
	328	#define banshee2D_colorBack (0x060/4)
	329	#define banshee2D_colorFore (0x064/4)
	330	#define banshee2D_dstSize (0x068/4)
	331	#define banshee2D_dstXY (0x06c/4)
	332	#define banshee2D_command (0x070/4)
	333
	334
	335	/*************************************
	336	*
	337	* Alias map of the first 64
	338	* registers when remapped
	339	*
	340	*************************************/
	341
	342	static const UINT8 register_alias_map[0x40] =
	343	{
	344	vdstatus, 0x004/4, vertexAx, vertexAy,
	345	vertexBx, vertexBy, vertexCx, vertexCy,
	346	startR, dRdX, dRdY, startG,
	347	dGdX, dGdY, startB, dBdX,
	348	dBdY, startZ, dZdX, dZdY,
	349	startA, dAdX, dAdY, startS,
	350	dSdX, dSdY, startT, dTdX,
	351	dTdY, startW, dWdX, dWdY,
	352
	353	triangleCMD,0x084/4, fvertexAx, fvertexAy,
	354	fvertexBx, fvertexBy, fvertexCx, fvertexCy,
	355	fstartR, fdRdX, fdRdY, fstartG,
	356	fdGdX, fdGdY, fstartB, fdBdX,
	357	fdBdY, fstartZ, fdZdX, fdZdY,
	358	fstartA, fdAdX, fdAdY, fstartS,
	359	fdSdX, fdSdY, fstartT, fdTdX,
	360	fdTdY, fstartW, fdWdX, fdWdY
	361	};
	362
	363
	364
	365	/*************************************
	366	*
	367	* Table of per-register access rights
	368	*
	369	*************************************/
	370
	371	static const UINT8 voodoo_register_access[0x100] =
	372	{
	373	/* 0x000 */
	374	REG_RP, 0, REG_WPF, REG_WPF,
	375	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	376	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	377	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	378
	379	/* 0x040 */
	380	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	381	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	382	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	383	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	384
	385	/* 0x080 */
	386	REG_WPF, 0, REG_WPF, REG_WPF,
	387	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	388	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	389	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	390
	391	/* 0x0c0 */
	392	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	393	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	394	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	395	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	396
	397	/* 0x100 */
	398	REG_WPF, REG_RWPF, REG_RWPF, REG_RWPF,
	399	REG_RWF, REG_RWF, REG_RWF, REG_RWF,
	400	REG_WF, REG_WF, REG_WF, REG_WF,
	401	REG_WF, REG_WF, 0, 0,
	402
	403	/* 0x140 */
	404	REG_RWF, REG_RWF, REG_RWF, REG_R,
	405	REG_R, REG_R, REG_R, REG_R,
	406	REG_WF, REG_WF, REG_WF, REG_WF,
	407	REG_WF, REG_WF, REG_WF, REG_WF,
	408
	409	/* 0x180 */
	410	REG_WF, REG_WF, REG_WF, REG_WF,
	411	REG_WF, REG_WF, REG_WF, REG_WF,
	412	REG_WF, REG_WF, REG_WF, REG_WF,
	413	REG_WF, REG_WF, REG_WF, REG_WF,
	414
	415	/* 0x1c0 */
	416	REG_WF, REG_WF, REG_WF, REG_WF,
	417	REG_WF, REG_WF, REG_WF, REG_WF,
	418	0, 0, 0, 0,
	419	0, 0, 0, 0,
	420
	421	/* 0x200 */
	422	REG_RW, REG_R, REG_RW, REG_RW,
	423	REG_RW, REG_RW, REG_RW, REG_RW,
	424	REG_W, REG_W, REG_W, REG_W,
	425	REG_W, 0, 0, 0,
	426
	427	/* 0x240 */
	428	0, 0, 0, 0,
	429	0, 0, 0, 0,
	430	0, 0, 0, 0,
	431	0, 0, 0, 0,
	432
	433	/* 0x280 */
	434	0, 0, 0, 0,
	435	0, 0, 0, 0,
	436	0, 0, 0, 0,
	437	0, 0, 0, 0,
	438
	439	/* 0x2c0 */
	440	0, 0, 0, 0,
	441	0, 0, 0, 0,
	442	0, 0, 0, 0,
	443	0, 0, 0, 0,
	444
	445	/* 0x300 */
	446	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	447	REG_WPF, REG_WPF, REG_WPF, REG_WF,
	448	REG_WF, REG_WF, REG_WF, REG_WF,
	449	REG_WF, REG_WF, REG_WF, REG_WF,
	450
	451	/* 0x340 */
	452	REG_WF, REG_WF, REG_WF, REG_WF,
	453	REG_WF, REG_WF, REG_WF, REG_WF,
	454	REG_WF, REG_WF, REG_WF, REG_WF,
	455	REG_WF, REG_WF, REG_WF, REG_WF,
	456
	457	/* 0x380 */
	458	REG_WF
	459	};
	460
	461
	462	static const UINT8 voodoo2_register_access[0x100] =
	463	{
	464	/* 0x000 */
	465	REG_RP, REG_RWPT, REG_WPF, REG_WPF,
	466	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	467	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	468	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	469
	470	/* 0x040 */
	471	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	472	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	473	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	474	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	475
	476	/* 0x080 */
	477	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	478	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	479	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	480	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	481
	482	/* 0x0c0 */
	483	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	484	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	485	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	486	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	487
	488	/* 0x100 */
	489	REG_WPF, REG_RWPF, REG_RWPF, REG_RWPF,
	490	REG_RWF, REG_RWF, REG_RWF, REG_RWF,
	491	REG_WF, REG_WF, REG_WF, REG_WF,
	492	REG_WF, REG_WF, REG_WF, REG_WF,
	493
	494	/* 0x140 */
	495	REG_RWF, REG_RWF, REG_RWF, REG_R,
	496	REG_R, REG_R, REG_R, REG_R,
	497	REG_WF, REG_WF, REG_WF, REG_WF,
	498	REG_WF, REG_WF, REG_WF, REG_WF,
	499
	500	/* 0x180 */
	501	REG_WF, REG_WF, REG_WF, REG_WF,
	502	REG_WF, REG_WF, REG_WF, REG_WF,
	503	REG_WF, REG_WF, REG_WF, REG_WF,
	504	REG_WF, REG_WF, REG_WF, REG_WF,
	505
	506	/* 0x1c0 */
	507	REG_WF, REG_WF, REG_WF, REG_WF,
	508	REG_WF, REG_WF, REG_WF, REG_WF,
	509	REG_RWT, REG_RWT, REG_RWT, REG_RWT,
	510	REG_RWT, REG_RWT, REG_RWT, REG_RW,
	511
	512	/* 0x200 */
	513	REG_RWT, REG_R, REG_RWT, REG_RWT,
	514	REG_RWT, REG_RWT, REG_RWT, REG_RWT,
	515	REG_WT, REG_WT, REG_WF, REG_WT,
	516	REG_WT, REG_WT, REG_WT, REG_WT,
	517
	518	/* 0x240 */
	519	REG_R, REG_RWT, REG_RWT, REG_RWT,
	520	0, 0, REG_R, REG_R,
	521	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	522	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	523
	524	/* 0x280 */
	525	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	526	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	527	REG_WPF, REG_WPF, 0, 0,
	528	0, 0, 0, 0,
	529
	530	/* 0x2c0 */
	531	REG_RWPF, REG_RWPF, REG_RWPF, REG_RWPF,
	532	REG_RWPF, REG_RWPF, REG_RWPF, REG_RWPF,
	533	REG_RWPF, REG_RWPF, REG_RWPF, REG_RWPF,
	534	REG_RWPF, REG_RWPF, REG_RWPF, REG_WPF,
	535
	536	/* 0x300 */
	537	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	538	REG_WPF, REG_WPF, REG_WPF, REG_WF,
	539	REG_WF, REG_WF, REG_WF, REG_WF,
	540	REG_WF, REG_WF, REG_WF, REG_WF,
	541
	542	/* 0x340 */
	543	REG_WF, REG_WF, REG_WF, REG_WF,
	544	REG_WF, REG_WF, REG_WF, REG_WF,
	545	REG_WF, REG_WF, REG_WF, REG_WF,
	546	REG_WF, REG_WF, REG_WF, REG_WF,
	547
	548	/* 0x380 */
	549	REG_WF
	550	};
	551
	552
	553	static const UINT8 banshee_register_access[0x100] =
	554	{
	555	/* 0x000 */
	556	REG_RP, REG_RWPT, REG_WPF, REG_WPF,
	557	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	558	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	559	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	560
	561	/* 0x040 */
	562	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	563	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	564	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	565	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	566
	567	/* 0x080 */
	568	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	569	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	570	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	571	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	572
	573	/* 0x0c0 */
	574	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	575	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	576	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	577	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	578
	579	/* 0x100 */
	580	REG_WPF, REG_RWPF, REG_RWPF, REG_RWPF,
	581	REG_RWF, REG_RWF, REG_RWF, REG_RWF,
	582	REG_WF, REG_WF, REG_WF, REG_WF,
	583	REG_WF, REG_WF, REG_WF, REG_WF,
	584
	585	/* 0x140 */
	586	REG_RWF, REG_RWF, REG_RWF, REG_R,
	587	REG_R, REG_R, REG_R, REG_R,
	588	REG_WF, REG_WF, REG_WF, REG_WF,
	589	REG_WF, REG_WF, REG_WF, REG_WF,
	590
	591	/* 0x180 */
	592	REG_WF, REG_WF, REG_WF, REG_WF,
	593	REG_WF, REG_WF, REG_WF, REG_WF,
	594	REG_WF, REG_WF, REG_WF, REG_WF,
	595	REG_WF, REG_WF, REG_WF, REG_WF,
	596
	597	/* 0x1c0 */
	598	REG_WF, REG_WF, REG_WF, REG_WF,
	599	REG_WF, REG_WF, REG_WF, REG_WF,
	600	0, 0, 0, REG_RWF,
	601	REG_RWF, REG_RWF, REG_RWF, 0,
	602
	603	/* 0x200 */
	604	REG_RWF, REG_RWF, 0, 0,
	605	0, 0, 0, 0,
	606	0, 0, 0, 0,
	607	0, 0, 0, 0,
	608
	609	/* 0x240 */
	610	0, 0, 0, REG_WT,
	611	REG_RWF, REG_RWF, REG_WPF, REG_WPF,
	612	REG_WPF, REG_WPF, REG_R, REG_R,
	613	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	614
	615	/* 0x280 */
	616	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	617	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	618	REG_WPF, REG_WPF, 0, 0,
	619	0, 0, 0, 0,
	620
	621	/* 0x2c0 */
	622	0, 0, 0, 0,
	623	0, 0, 0, 0,
	624	0, 0, 0, 0,
	625	0, 0, 0, 0,
	626
	627	/* 0x300 */
	628	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	629	REG_WPF, REG_WPF, REG_WPF, 0,
	630	REG_WF, REG_WF, REG_WF, REG_WF,
	631	REG_WF, REG_WF, REG_WF, REG_WF,
	632
	633	/* 0x340 */
	634	REG_WF, REG_WF, REG_WF, REG_WF,
	635	REG_WF, REG_WF, REG_WF, REG_WF,
	636	REG_WF, REG_WF, REG_WF, REG_WF,
	637	REG_WF, REG_WF, REG_WF, REG_WF,
	638
	639	/* 0x380 */
	640	REG_WF
	641	};
	642
	643
	644
	645	/*************************************
	646	*
	647	* Register string table for debug
	648	*
	649	*************************************/
	650
	651	static const char *const voodoo_reg_name[] =
	652	{
	653	/* 0x000 */
	654	"status", "{intrCtrl}", "vertexAx", "vertexAy",
	655	"vertexBx", "vertexBy", "vertexCx", "vertexCy",
	656	"startR", "startG", "startB", "startZ",
	657	"startA", "startS", "startT", "startW",
	658	/* 0x040 */
	659	"dRdX", "dGdX", "dBdX", "dZdX",
	660	"dAdX", "dSdX", "dTdX", "dWdX",
	661	"dRdY", "dGdY", "dBdY", "dZdY",
	662	"dAdY", "dSdY", "dTdY", "dWdY",
	663	/* 0x080 */
	664	"triangleCMD", "reserved084", "fvertexAx", "fvertexAy",
	665	"fvertexBx", "fvertexBy", "fvertexCx", "fvertexCy",
	666	"fstartR", "fstartG", "fstartB", "fstartZ",
	667	"fstartA", "fstartS", "fstartT", "fstartW",
	668	/* 0x0c0 */
	669	"fdRdX", "fdGdX", "fdBdX", "fdZdX",
	670	"fdAdX", "fdSdX", "fdTdX", "fdWdX",
	671	"fdRdY", "fdGdY", "fdBdY", "fdZdY",
	672	"fdAdY", "fdSdY", "fdTdY", "fdWdY",
	673	/* 0x100 */
	674	"ftriangleCMD", "fbzColorPath", "fogMode", "alphaMode",
	675	"fbzMode", "lfbMode", "clipLeftRight","clipLowYHighY",
	676	"nopCMD", "fastfillCMD", "swapbufferCMD","fogColor",
	677	"zaColor", "chromaKey", "{chromaRange}","{userIntrCMD}",
	678	/* 0x140 */
	679	"stipple", "color0", "color1", "fbiPixelsIn",
	680	"fbiChromaFail","fbiZfuncFail", "fbiAfuncFail", "fbiPixelsOut",
	681	"fogTable160", "fogTable164", "fogTable168", "fogTable16c",
	682	"fogTable170", "fogTable174", "fogTable178", "fogTable17c",
	683	/* 0x180 */
	684	"fogTable180", "fogTable184", "fogTable188", "fogTable18c",
	685	"fogTable190", "fogTable194", "fogTable198", "fogTable19c",
	686	"fogTable1a0", "fogTable1a4", "fogTable1a8", "fogTable1ac",
	687	"fogTable1b0", "fogTable1b4", "fogTable1b8", "fogTable1bc",
	688	/* 0x1c0 */
	689	"fogTable1c0", "fogTable1c4", "fogTable1c8", "fogTable1cc",
	690	"fogTable1d0", "fogTable1d4", "fogTable1d8", "fogTable1dc",
	691	"{cmdFifoBaseAddr}","{cmdFifoBump}","{cmdFifoRdPtr}","{cmdFifoAMin}",
	692	"{cmdFifoAMax}","{cmdFifoDepth}","{cmdFifoHoles}","reserved1fc",
	693	/* 0x200 */
	694	"fbiInit4", "vRetrace", "backPorch", "videoDimensions",
	695	"fbiInit0", "fbiInit1", "fbiInit2", "fbiInit3",
	696	"hSync", "vSync", "clutData", "dacData",
	697	"maxRgbDelta", "{hBorder}", "{vBorder}", "{borderColor}",
	698	/* 0x240 */
	699	"{hvRetrace}", "{fbiInit5}", "{fbiInit6}", "{fbiInit7}",
	700	"reserved250", "reserved254", "{fbiSwapHistory}","{fbiTrianglesOut}",
	701	"{sSetupMode}", "{sVx}", "{sVy}", "{sARGB}",
	702	"{sRed}", "{sGreen}", "{sBlue}", "{sAlpha}",
	703	/* 0x280 */
	704	"{sVz}", "{sWb}", "{sWtmu0}", "{sS/Wtmu0}",
	705	"{sT/Wtmu0}", "{sWtmu1}", "{sS/Wtmu1}", "{sT/Wtmu1}",
	706	"{sDrawTriCMD}","{sBeginTriCMD}","reserved2a8", "reserved2ac",
	707	"reserved2b0", "reserved2b4", "reserved2b8", "reserved2bc",
	708	/* 0x2c0 */
	709	"{bltSrcBaseAddr}","{bltDstBaseAddr}","{bltXYStrides}","{bltSrcChromaRange}",
	710	"{bltDstChromaRange}","{bltClipX}","{bltClipY}","reserved2dc",
	711	"{bltSrcXY}", "{bltDstXY}", "{bltSize}", "{bltRop}",
	712	"{bltColor}", "reserved2f4", "{bltCommand}", "{bltData}",
	713	/* 0x300 */
	714	"textureMode", "tLOD", "tDetail", "texBaseAddr",
	715	"texBaseAddr_1","texBaseAddr_2","texBaseAddr_3_8","trexInit0",
	716	"trexInit1", "nccTable0.0", "nccTable0.1", "nccTable0.2",
	717	"nccTable0.3", "nccTable0.4", "nccTable0.5", "nccTable0.6",
	718	/* 0x340 */
	719	"nccTable0.7", "nccTable0.8", "nccTable0.9", "nccTable0.A",
	720	"nccTable0.B", "nccTable1.0", "nccTable1.1", "nccTable1.2",
	721	"nccTable1.3", "nccTable1.4", "nccTable1.5", "nccTable1.6",
	722	"nccTable1.7", "nccTable1.8", "nccTable1.9", "nccTable1.A",
	723	/* 0x380 */
	724	"nccTable1.B"
	725	};
	726
	727
	728	static const char *const banshee_reg_name[] =
	729	{
	730	/* 0x000 */
	731	"status", "intrCtrl", "vertexAx", "vertexAy",
	732	"vertexBx", "vertexBy", "vertexCx", "vertexCy",
	733	"startR", "startG", "startB", "startZ",
	734	"startA", "startS", "startT", "startW",
	735	/* 0x040 */
	736	"dRdX", "dGdX", "dBdX", "dZdX",
	737	"dAdX", "dSdX", "dTdX", "dWdX",
	738	"dRdY", "dGdY", "dBdY", "dZdY",
	739	"dAdY", "dSdY", "dTdY", "dWdY",
	740	/* 0x080 */
	741	"triangleCMD", "reserved084", "fvertexAx", "fvertexAy",
	742	"fvertexBx", "fvertexBy", "fvertexCx", "fvertexCy",
	743	"fstartR", "fstartG", "fstartB", "fstartZ",
	744	"fstartA", "fstartS", "fstartT", "fstartW",
	745	/* 0x0c0 */
	746	"fdRdX", "fdGdX", "fdBdX", "fdZdX",
	747	"fdAdX", "fdSdX", "fdTdX", "fdWdX",
	748	"fdRdY", "fdGdY", "fdBdY", "fdZdY",
	749	"fdAdY", "fdSdY", "fdTdY", "fdWdY",
	750	/* 0x100 */
	751	"ftriangleCMD", "fbzColorPath", "fogMode", "alphaMode",
	752	"fbzMode", "lfbMode", "clipLeftRight","clipLowYHighY",
	753	"nopCMD", "fastfillCMD", "swapbufferCMD","fogColor",
	754	"zaColor", "chromaKey", "chromaRange", "userIntrCMD",
	755	/* 0x140 */
	756	"stipple", "color0", "color1", "fbiPixelsIn",
	757	"fbiChromaFail","fbiZfuncFail", "fbiAfuncFail", "fbiPixelsOut",
	758	"fogTable160", "fogTable164", "fogTable168", "fogTable16c",
	759	"fogTable170", "fogTable174", "fogTable178", "fogTable17c",
	760	/* 0x180 */
	761	"fogTable180", "fogTable184", "fogTable188", "fogTable18c",
	762	"fogTable190", "fogTable194", "fogTable198", "fogTable19c",
	763	"fogTable1a0", "fogTable1a4", "fogTable1a8", "fogTable1ac",
	764	"fogTable1b0", "fogTable1b4", "fogTable1b8", "fogTable1bc",
	765	/* 0x1c0 */
	766	"fogTable1c0", "fogTable1c4", "fogTable1c8", "fogTable1cc",
	767	"fogTable1d0", "fogTable1d4", "fogTable1d8", "fogTable1dc",
	768	"reserved1e0", "reserved1e4", "reserved1e8", "colBufferAddr",
	769	"colBufferStride","auxBufferAddr","auxBufferStride","reserved1fc",
	770	/* 0x200 */
	771	"clipLeftRight1","clipTopBottom1","reserved208","reserved20c",
	772	"reserved210", "reserved214", "reserved218", "reserved21c",
	773	"reserved220", "reserved224", "reserved228", "reserved22c",
	774	"reserved230", "reserved234", "reserved238", "reserved23c",
	775	/* 0x240 */
	776	"reserved240", "reserved244", "reserved248", "swapPending",
	777	"leftOverlayBuf","rightOverlayBuf","fbiSwapHistory","fbiTrianglesOut",
	778	"sSetupMode", "sVx", "sVy", "sARGB",
	779	"sRed", "sGreen", "sBlue", "sAlpha",
	780	/* 0x280 */
	781	"sVz", "sWb", "sWtmu0", "sS/Wtmu0",
	782	"sT/Wtmu0", "sWtmu1", "sS/Wtmu1", "sT/Wtmu1",
	783	"sDrawTriCMD", "sBeginTriCMD", "reserved2a8", "reserved2ac",
	784	"reserved2b0", "reserved2b4", "reserved2b8", "reserved2bc",
	785	/* 0x2c0 */
	786	"reserved2c0", "reserved2c4", "reserved2c8", "reserved2cc",
	787	"reserved2d0", "reserved2d4", "reserved2d8", "reserved2dc",
	788	"reserved2e0", "reserved2e4", "reserved2e8", "reserved2ec",
	789	"reserved2f0", "reserved2f4", "reserved2f8", "reserved2fc",
	790	/* 0x300 */
	791	"textureMode", "tLOD", "tDetail", "texBaseAddr",
	792	"texBaseAddr_1","texBaseAddr_2","texBaseAddr_3_8","reserved31c",
	793	"trexInit1", "nccTable0.0", "nccTable0.1", "nccTable0.2",
	794	"nccTable0.3", "nccTable0.4", "nccTable0.5", "nccTable0.6",
	795	/* 0x340 */
	796	"nccTable0.7", "nccTable0.8", "nccTable0.9", "nccTable0.A",
	797	"nccTable0.B", "nccTable1.0", "nccTable1.1", "nccTable1.2",
	798	"nccTable1.3", "nccTable1.4", "nccTable1.5", "nccTable1.6",
	799	"nccTable1.7", "nccTable1.8", "nccTable1.9", "nccTable1.A",
	800	/* 0x380 */
	801	"nccTable1.B"
	802	};
	803
	804
	805
	806	/*************************************
	807	*
	808	* Voodoo Banshee I/O space registers
	809	*
	810	*************************************/
	811
	812	/* 0x000 */
	813	#define io_status (0x000/4) /* */
	814	#define io_pciInit0 (0x004/4) /* */
	815	#define io_sipMonitor (0x008/4) /* */
	816	#define io_lfbMemoryConfig (0x00c/4) /* */
	817	#define io_miscInit0 (0x010/4) /* */
	818	#define io_miscInit1 (0x014/4) /* */
	819	#define io_dramInit0 (0x018/4) /* */
	820	#define io_dramInit1 (0x01c/4) /* */
	821	#define io_agpInit (0x020/4) /* */
	822	#define io_tmuGbeInit (0x024/4) /* */
	823	#define io_vgaInit0 (0x028/4) /* */
	824	#define io_vgaInit1 (0x02c/4) /* */
	825	#define io_dramCommand (0x030/4) /* */
	826	#define io_dramData (0x034/4) /* */
	827
	828	/* 0x040 */
	829	#define io_pllCtrl0 (0x040/4) /* */
	830	#define io_pllCtrl1 (0x044/4) /* */
	831	#define io_pllCtrl2 (0x048/4) /* */
	832	#define io_dacMode (0x04c/4) /* */
	833	#define io_dacAddr (0x050/4) /* */
	834	#define io_dacData (0x054/4) /* */
	835	#define io_rgbMaxDelta (0x058/4) /* */
	836	#define io_vidProcCfg (0x05c/4) /* */
	837	#define io_hwCurPatAddr (0x060/4) /* */
	838	#define io_hwCurLoc (0x064/4) /* */
	839	#define io_hwCurC0 (0x068/4) /* */
	840	#define io_hwCurC1 (0x06c/4) /* */
	841	#define io_vidInFormat (0x070/4) /* */
	842	#define io_vidInStatus (0x074/4) /* */
	843	#define io_vidSerialParallelPort (0x078/4) /* */
	844	#define io_vidInXDecimDeltas (0x07c/4) /* */
	845
	846	/* 0x080 */
	847	#define io_vidInDecimInitErrs (0x080/4) /* */
	848	#define io_vidInYDecimDeltas (0x084/4) /* */
	849	#define io_vidPixelBufThold (0x088/4) /* */
	850	#define io_vidChromaMin (0x08c/4) /* */
	851	#define io_vidChromaMax (0x090/4) /* */
	852	#define io_vidCurrentLine (0x094/4) /* */
	853	#define io_vidScreenSize (0x098/4) /* */
	854	#define io_vidOverlayStartCoords (0x09c/4) /* */
	855	#define io_vidOverlayEndScreenCoord (0x0a0/4) /* */
	856	#define io_vidOverlayDudx (0x0a4/4) /* */
	857	#define io_vidOverlayDudxOffsetSrcWidth (0x0a8/4) /* */
	858	#define io_vidOverlayDvdy (0x0ac/4) /* */
	859	#define io_vgab0 (0x0b0/4) /* */
	860	#define io_vgab4 (0x0b4/4) /* */
	861	#define io_vgab8 (0x0b8/4) /* */
	862	#define io_vgabc (0x0bc/4) /* */
	863
	864	/* 0x0c0 */
	865	#define io_vgac0 (0x0c0/4) /* */
	866	#define io_vgac4 (0x0c4/4) /* */
	867	#define io_vgac8 (0x0c8/4) /* */
	868	#define io_vgacc (0x0cc/4) /* */
	869	#define io_vgad0 (0x0d0/4) /* */
	870	#define io_vgad4 (0x0d4/4) /* */
	871	#define io_vgad8 (0x0d8/4) /* */
	872	#define io_vgadc (0x0dc/4) /* */
	873	#define io_vidOverlayDvdyOffset (0x0e0/4) /* */
	874	#define io_vidDesktopStartAddr (0x0e4/4) /* */
	875	#define io_vidDesktopOverlayStride (0x0e8/4) /* */
	876	#define io_vidInAddr0 (0x0ec/4) /* */
	877	#define io_vidInAddr1 (0x0f0/4) /* */
	878	#define io_vidInAddr2 (0x0f4/4) /* */
	879	#define io_vidInStride (0x0f8/4) /* */
	880	#define io_vidCurrOverlayStartAddr (0x0fc/4) /* */
	881
	882
	883
	884	/*************************************
	885	*
	886	* Register string table for debug
	887	*
	888	*************************************/
	889
	890	static const char *const banshee_io_reg_name[] =
	891	{
	892	/* 0x000 */
	893	"status", "pciInit0", "sipMonitor", "lfbMemoryConfig",
	894	"miscInit0", "miscInit1", "dramInit0", "dramInit1",
	895	"agpInit", "tmuGbeInit", "vgaInit0", "vgaInit1",
	896	"dramCommand", "dramData", "reserved38", "reserved3c",
	897
	898	/* 0x040 */
	899	"pllCtrl0", "pllCtrl1", "pllCtrl2", "dacMode",
	900	"dacAddr", "dacData", "rgbMaxDelta", "vidProcCfg",
	901	"hwCurPatAddr", "hwCurLoc", "hwCurC0", "hwCurC1",
	902	"vidInFormat", "vidInStatus", "vidSerialParallelPort","vidInXDecimDeltas",
	903
	904	/* 0x080 */
	905	"vidInDecimInitErrs","vidInYDecimDeltas","vidPixelBufThold","vidChromaMin",
	906	"vidChromaMax", "vidCurrentLine","vidScreenSize","vidOverlayStartCoords",
	907	"vidOverlayEndScreenCoord","vidOverlayDudx","vidOverlayDudxOffsetSrcWidth","vidOverlayDvdy",
	908	"vga[b0]", "vga[b4]", "vga[b8]", "vga[bc]",
	909
	910	/* 0x0c0 */
	911	"vga[c0]", "vga[c4]", "vga[c8]", "vga[cc]",
	912	"vga[d0]", "vga[d4]", "vga[d8]", "vga[dc]",
	913	"vidOverlayDvdyOffset","vidDesktopStartAddr","vidDesktopOverlayStride","vidInAddr0",
	914	"vidInAddr1", "vidInAddr2", "vidInStride", "vidCurrOverlayStartAddr"
	915	};
	916
	917
	918
	919	/*************************************
	920	*
	921	* Voodoo Banshee AGP space registers
	922	*
	923	*************************************/
	924
	925	/* 0x000 */
	926	#define agpReqSize (0x000/4) /* */
	927	#define agpHostAddressLow (0x004/4) /* */
	928	#define agpHostAddressHigh (0x008/4) /* */
	929	#define agpGraphicsAddress (0x00c/4) /* */
	930	#define agpGraphicsStride (0x010/4) /* */
	931	#define agpMoveCMD (0x014/4) /* */
	932	#define cmdBaseAddr0 (0x020/4) /* */
	933	#define cmdBaseSize0 (0x024/4) /* */
	934	#define cmdBump0 (0x028/4) /* */
	935	#define cmdRdPtrL0 (0x02c/4) /* */
	936	#define cmdRdPtrH0 (0x030/4) /* */
	937	#define cmdAMin0 (0x034/4) /* */
	938	#define cmdAMax0 (0x03c/4) /* */
	939
	940	/* 0x040 */
	941	#define cmdFifoDepth0 (0x044/4) /* */
	942	#define cmdHoleCnt0 (0x048/4) /* */
	943	#define cmdBaseAddr1 (0x050/4) /* */
	944	#define cmdBaseSize1 (0x054/4) /* */
	945	#define cmdBump1 (0x058/4) /* */
	946	#define cmdRdPtrL1 (0x05c/4) /* */
	947	#define cmdRdPtrH1 (0x060/4) /* */
	948	#define cmdAMin1 (0x064/4) /* */
	949	#define cmdAMax1 (0x06c/4) /* */
	950	#define cmdFifoDepth1 (0x074/4) /* */
	951	#define cmdHoleCnt1 (0x078/4) /* */
	952
	953	/* 0x080 */
	954	#define cmdFifoThresh (0x080/4) /* */
	955	#define cmdHoleInt (0x084/4) /* */
	956
	957	/* 0x100 */
	958	#define yuvBaseAddress (0x100/4) /* */
	959	#define yuvStride (0x104/4) /* */
	960	#define crc1 (0x120/4) /* */
	961	#define crc2 (0x130/4) /* */
	962
	963
	964
	965	/*************************************
	966	*
	967	* Register string table for debug
	968	*
	969	*************************************/
	970
	971	static const char *const banshee_agp_reg_name[] =
	972	{
	973	/* 0x000 */
	974	"agpReqSize", "agpHostAddressLow","agpHostAddressHigh","agpGraphicsAddress",
	975	"agpGraphicsStride","agpMoveCMD","reserved18", "reserved1c",
	976	"cmdBaseAddr0", "cmdBaseSize0", "cmdBump0", "cmdRdPtrL0",
	977	"cmdRdPtrH0", "cmdAMin0", "reserved38", "cmdAMax0",
	978
	979	/* 0x040 */
	980	"reserved40", "cmdFifoDepth0","cmdHoleCnt0", "reserved4c",
	981	"cmdBaseAddr1", "cmdBaseSize1", "cmdBump1", "cmdRdPtrL1",
	982	"cmdRdPtrH1", "cmdAMin1", "reserved68", "cmdAMax1",
	983	"reserved70", "cmdFifoDepth1","cmdHoleCnt1", "reserved7c",
	984
	985	/* 0x080 */
	986	"cmdFifoThresh","cmdHoleInt", "reserved88", "reserved8c",
	987	"reserved90", "reserved94", "reserved98", "reserved9c",
	988	"reserveda0", "reserveda4", "reserveda8", "reservedac",
	989	"reservedb0", "reservedb4", "reservedb8", "reservedbc",
	990
	991	/* 0x0c0 */
	992	"reservedc0", "reservedc4", "reservedc8", "reservedcc",
	993	"reservedd0", "reservedd4", "reservedd8", "reserveddc",
	994	"reservede0", "reservede4", "reservede8", "reservedec",
	995	"reservedf0", "reservedf4", "reservedf8", "reservedfc",
	996
	997	/* 0x100 */
	998	"yuvBaseAddress","yuvStride", "reserved108", "reserved10c",
	999	"reserved110", "reserved114", "reserved118", "reserved11c",
	1000	"crc1", "reserved124", "reserved128", "reserved12c",
	1001	"crc2", "reserved134", "reserved138", "reserved13c"
	1002	};
	1003
	1004
	1005
	1006	/*************************************
	1007	*
	1008	* Dithering tables
	1009	*
	1010	*************************************/
	1011
	1012	static const UINT8 dither_matrix_4x4[16] =
	1013	{
	1014	0, 8, 2, 10,
	1015	12, 4, 14, 6,
	1016	3, 11, 1, 9,
	1017	15, 7, 13, 5
	1018	};
	1019
	1020	static const UINT8 dither_matrix_2x2[16] =
	1021	{
	1022	2, 10, 2, 10,
	1023	14, 6, 14, 6,
	1024	2, 10, 2, 10,
	1025	14, 6, 14, 6
	1026	};
	1027
	1028
	1029
	1030	/*************************************
	1031	*
	1032	* Macros for extracting pixels
	1033	*
	1034	*************************************/
	1035
	1036	#define EXTRACT_565_TO_888(val, a, b, c) \
	1037	(a) = (((val) >> 8) & 0xf8) \| (((val) >> 13) & 0x07); \
	1038	(b) = (((val) >> 3) & 0xfc) \| (((val) >> 9) & 0x03); \
	1039	(c) = (((val) << 3) & 0xf8) \| (((val) >> 2) & 0x07);
	1040	#define EXTRACT_x555_TO_888(val, a, b, c) \
	1041	(a) = (((val) >> 7) & 0xf8) \| (((val) >> 12) & 0x07); \
	1042	(b) = (((val) >> 2) & 0xf8) \| (((val) >> 7) & 0x07); \
	1043	(c) = (((val) << 3) & 0xf8) \| (((val) >> 2) & 0x07);
	1044	#define EXTRACT_555x_TO_888(val, a, b, c) \
	1045	(a) = (((val) >> 8) & 0xf8) \| (((val) >> 13) & 0x07); \
	1046	(b) = (((val) >> 3) & 0xf8) \| (((val) >> 8) & 0x07); \
	1047	(c) = (((val) << 2) & 0xf8) \| (((val) >> 3) & 0x07);
	1048	#define EXTRACT_1555_TO_8888(val, a, b, c, d) \
	1049	(a) = ((INT16)(val) >> 15) & 0xff; \
	1050	EXTRACT_x555_TO_888(val, b, c, d)
	1051	#define EXTRACT_5551_TO_8888(val, a, b, c, d) \
	1052	EXTRACT_555x_TO_888(val, a, b, c) \
	1053	(d) = ((val) & 0x0001) ? 0xff : 0x00;
	1054	#define EXTRACT_x888_TO_888(val, a, b, c) \
	1055	(a) = ((val) >> 16) & 0xff; \
	1056	(b) = ((val) >> 8) & 0xff; \
	1057	(c) = ((val) >> 0) & 0xff;
	1058	#define EXTRACT_888x_TO_888(val, a, b, c) \
	1059	(a) = ((val) >> 24) & 0xff; \
	1060	(b) = ((val) >> 16) & 0xff; \
	1061	(c) = ((val) >> 8) & 0xff;
	1062	#define EXTRACT_8888_TO_8888(val, a, b, c, d) \
	1063	(a) = ((val) >> 24) & 0xff; \
	1064	(b) = ((val) >> 16) & 0xff; \
	1065	(c) = ((val) >> 8) & 0xff; \
	1066	(d) = ((val) >> 0) & 0xff;
	1067	#define EXTRACT_4444_TO_8888(val, a, b, c, d) \
	1068	(a) = (((val) >> 8) & 0xf0) \| (((val) >> 12) & 0x0f); \
	1069	(b) = (((val) >> 4) & 0xf0) \| (((val) >> 8) & 0x0f); \
	1070	(c) = (((val) >> 0) & 0xf0) \| (((val) >> 4) & 0x0f); \
	1071	(d) = (((val) << 4) & 0xf0) \| (((val) >> 0) & 0x0f);
	1072	#define EXTRACT_332_TO_888(val, a, b, c) \
	1073	(a) = (((val) >> 0) & 0xe0) \| (((val) >> 3) & 0x1c) \| (((val) >> 6) & 0x03); \
	1074	(b) = (((val) << 3) & 0xe0) \| (((val) >> 0) & 0x1c) \| (((val) >> 3) & 0x03); \
	1075	(c) = (((val) << 6) & 0xc0) \| (((val) << 4) & 0x30) \| (((val) << 2) & 0x0c) \| (((val) << 0) & 0x03);
	1076
	1077
	1078	/*************************************
	1079	*
	1080	* Misc. macros
	1081	*
	1082	*************************************/
	1083
	1084	/* macro for clamping a value between minimum and maximum values */
	1085	#define CLAMP(val,min,max) do { if ((val) < (min)) { (val) = (min); } else if ((val) > (max)) { (val) = (max); } } while (0)
	1086
	1087	/* macro to compute the base 2 log for LOD calculations */
	1088	#define LOGB2(x) (log((double)(x)) / log(2.0))
	1089
	1090
	1091
	1092	/*************************************
	1093	*
	1094	* Macros for extracting bitfields
	1095	*
	1096	*************************************/
	1097
	1098	#define INITEN_ENABLE_HW_INIT(val) (((val) >> 0) & 1)
	1099	#define INITEN_ENABLE_PCI_FIFO(val) (((val) >> 1) & 1)
	1100	#define INITEN_REMAP_INIT_TO_DAC(val) (((val) >> 2) & 1)
	1101	#define INITEN_ENABLE_SNOOP0(val) (((val) >> 4) & 1)
	1102	#define INITEN_SNOOP0_MEMORY_MATCH(val) (((val) >> 5) & 1)
	1103	#define INITEN_SNOOP0_READWRITE_MATCH(val) (((val) >> 6) & 1)
	1104	#define INITEN_ENABLE_SNOOP1(val) (((val) >> 7) & 1)
	1105	#define INITEN_SNOOP1_MEMORY_MATCH(val) (((val) >> 8) & 1)
	1106	#define INITEN_SNOOP1_READWRITE_MATCH(val) (((val) >> 9) & 1)
	1107	#define INITEN_SLI_BUS_OWNER(val) (((val) >> 10) & 1)
	1108	#define INITEN_SLI_ODD_EVEN(val) (((val) >> 11) & 1)
	1109	#define INITEN_SECONDARY_REV_ID(val) (((val) >> 12) & 0xf) /* voodoo 2 only */
	1110	#define INITEN_MFCTR_FAB_ID(val) (((val) >> 16) & 0xf) /* voodoo 2 only */
	1111	#define INITEN_ENABLE_PCI_INTERRUPT(val) (((val) >> 20) & 1) /* voodoo 2 only */
	1112	#define INITEN_PCI_INTERRUPT_TIMEOUT(val) (((val) >> 21) & 1) /* voodoo 2 only */
	1113	#define INITEN_ENABLE_NAND_TREE_TEST(val) (((val) >> 22) & 1) /* voodoo 2 only */
	1114	#define INITEN_ENABLE_SLI_ADDRESS_SNOOP(val) (((val) >> 23) & 1) /* voodoo 2 only */
	1115	#define INITEN_SLI_SNOOP_ADDRESS(val) (((val) >> 24) & 0xff) /* voodoo 2 only */
	1116
	1117	#define FBZCP_CC_RGBSELECT(val) (((val) >> 0) & 3)
	1118	#define FBZCP_CC_ASELECT(val) (((val) >> 2) & 3)
	1119	#define FBZCP_CC_LOCALSELECT(val) (((val) >> 4) & 1)
	1120	#define FBZCP_CCA_LOCALSELECT(val) (((val) >> 5) & 3)
	1121	#define FBZCP_CC_LOCALSELECT_OVERRIDE(val) (((val) >> 7) & 1)
	1122	#define FBZCP_CC_ZERO_OTHER(val) (((val) >> 8) & 1)
	1123	#define FBZCP_CC_SUB_CLOCAL(val) (((val) >> 9) & 1)
	1124	#define FBZCP_CC_MSELECT(val) (((val) >> 10) & 7)
	1125	#define FBZCP_CC_REVERSE_BLEND(val) (((val) >> 13) & 1)
	1126	#define FBZCP_CC_ADD_ACLOCAL(val) (((val) >> 14) & 3)
	1127	#define FBZCP_CC_INVERT_OUTPUT(val) (((val) >> 16) & 1)
	1128	#define FBZCP_CCA_ZERO_OTHER(val) (((val) >> 17) & 1)
	1129	#define FBZCP_CCA_SUB_CLOCAL(val) (((val) >> 18) & 1)
	1130	#define FBZCP_CCA_MSELECT(val) (((val) >> 19) & 7)
	1131	#define FBZCP_CCA_REVERSE_BLEND(val) (((val) >> 22) & 1)
	1132	#define FBZCP_CCA_ADD_ACLOCAL(val) (((val) >> 23) & 3)
	1133	#define FBZCP_CCA_INVERT_OUTPUT(val) (((val) >> 25) & 1)
	1134	#define FBZCP_CCA_SUBPIXEL_ADJUST(val) (((val) >> 26) & 1)
	1135	#define FBZCP_TEXTURE_ENABLE(val) (((val) >> 27) & 1)
	1136	#define FBZCP_RGBZW_CLAMP(val) (((val) >> 28) & 1) /* voodoo 2 only */
	1137	#define FBZCP_ANTI_ALIAS(val) (((val) >> 29) & 1) /* voodoo 2 only */
	1138
	1139	#define ALPHAMODE_ALPHATEST(val) (((val) >> 0) & 1)
	1140	#define ALPHAMODE_ALPHAFUNCTION(val) (((val) >> 1) & 7)
	1141	#define ALPHAMODE_ALPHABLEND(val) (((val) >> 4) & 1)
	1142	#define ALPHAMODE_ANTIALIAS(val) (((val) >> 5) & 1)
	1143	#define ALPHAMODE_SRCRGBBLEND(val) (((val) >> 8) & 15)
	1144	#define ALPHAMODE_DSTRGBBLEND(val) (((val) >> 12) & 15)
	1145	#define ALPHAMODE_SRCALPHABLEND(val) (((val) >> 16) & 15)
	1146	#define ALPHAMODE_DSTALPHABLEND(val) (((val) >> 20) & 15)
	1147	#define ALPHAMODE_ALPHAREF(val) (((val) >> 24) & 0xff)
	1148
	1149	#define FOGMODE_ENABLE_FOG(val) (((val) >> 0) & 1)
	1150	#define FOGMODE_FOG_ADD(val) (((val) >> 1) & 1)
	1151	#define FOGMODE_FOG_MULT(val) (((val) >> 2) & 1)
	1152	#define FOGMODE_FOG_ZALPHA(val) (((val) >> 3) & 3)
	1153	#define FOGMODE_FOG_CONSTANT(val) (((val) >> 5) & 1)
	1154	#define FOGMODE_FOG_DITHER(val) (((val) >> 6) & 1) /* voodoo 2 only */
	1155	#define FOGMODE_FOG_ZONES(val) (((val) >> 7) & 1) /* voodoo 2 only */
	1156
	1157	#define FBZMODE_ENABLE_CLIPPING(val) (((val) >> 0) & 1)
	1158	#define FBZMODE_ENABLE_CHROMAKEY(val) (((val) >> 1) & 1)
	1159	#define FBZMODE_ENABLE_STIPPLE(val) (((val) >> 2) & 1)
	1160	#define FBZMODE_WBUFFER_SELECT(val) (((val) >> 3) & 1)
	1161	#define FBZMODE_ENABLE_DEPTHBUF(val) (((val) >> 4) & 1)
	1162	#define FBZMODE_DEPTH_FUNCTION(val) (((val) >> 5) & 7)
	1163	#define FBZMODE_ENABLE_DITHERING(val) (((val) >> 8) & 1)
	1164	#define FBZMODE_RGB_BUFFER_MASK(val) (((val) >> 9) & 1)
	1165	#define FBZMODE_AUX_BUFFER_MASK(val) (((val) >> 10) & 1)
	1166	#define FBZMODE_DITHER_TYPE(val) (((val) >> 11) & 1)
	1167	#define FBZMODE_STIPPLE_PATTERN(val) (((val) >> 12) & 1)
	1168	#define FBZMODE_ENABLE_ALPHA_MASK(val) (((val) >> 13) & 1)
	1169	#define FBZMODE_DRAW_BUFFER(val) (((val) >> 14) & 3)
	1170	#define FBZMODE_ENABLE_DEPTH_BIAS(val) (((val) >> 16) & 1)
	1171	#define FBZMODE_Y_ORIGIN(val) (((val) >> 17) & 1)
	1172	#define FBZMODE_ENABLE_ALPHA_PLANES(val) (((val) >> 18) & 1)
	1173	#define FBZMODE_ALPHA_DITHER_SUBTRACT(val) (((val) >> 19) & 1)
	1174	#define FBZMODE_DEPTH_SOURCE_COMPARE(val) (((val) >> 20) & 1)
	1175	#define FBZMODE_DEPTH_FLOAT_SELECT(val) (((val) >> 21) & 1) /* voodoo 2 only */
	1176
	1177	#define LFBMODE_WRITE_FORMAT(val) (((val) >> 0) & 0xf)
	1178	#define LFBMODE_WRITE_BUFFER_SELECT(val) (((val) >> 4) & 3)
	1179	#define LFBMODE_READ_BUFFER_SELECT(val) (((val) >> 6) & 3)
	1180	#define LFBMODE_ENABLE_PIXEL_PIPELINE(val) (((val) >> 8) & 1)
	1181	#define LFBMODE_RGBA_LANES(val) (((val) >> 9) & 3)
	1182	#define LFBMODE_WORD_SWAP_WRITES(val) (((val) >> 11) & 1)
	1183	#define LFBMODE_BYTE_SWIZZLE_WRITES(val) (((val) >> 12) & 1)
	1184	#define LFBMODE_Y_ORIGIN(val) (((val) >> 13) & 1)
	1185	#define LFBMODE_WRITE_W_SELECT(val) (((val) >> 14) & 1)
	1186	#define LFBMODE_WORD_SWAP_READS(val) (((val) >> 15) & 1)
	1187	#define LFBMODE_BYTE_SWIZZLE_READS(val) (((val) >> 16) & 1)
	1188
	1189	#define CHROMARANGE_BLUE_EXCLUSIVE(val) (((val) >> 24) & 1)
	1190	#define CHROMARANGE_GREEN_EXCLUSIVE(val) (((val) >> 25) & 1)
	1191	#define CHROMARANGE_RED_EXCLUSIVE(val) (((val) >> 26) & 1)
	1192	#define CHROMARANGE_UNION_MODE(val) (((val) >> 27) & 1)
	1193	#define CHROMARANGE_ENABLE(val) (((val) >> 28) & 1)
	1194
	1195	#define FBIINIT0_VGA_PASSTHRU(val) (((val) >> 0) & 1)
	1196	#define FBIINIT0_GRAPHICS_RESET(val) (((val) >> 1) & 1)
	1197	#define FBIINIT0_FIFO_RESET(val) (((val) >> 2) & 1)
	1198	#define FBIINIT0_SWIZZLE_REG_WRITES(val) (((val) >> 3) & 1)
	1199	#define FBIINIT0_STALL_PCIE_FOR_HWM(val) (((val) >> 4) & 1)
	1200	#define FBIINIT0_PCI_FIFO_LWM(val) (((val) >> 6) & 0x1f)
	1201	#define FBIINIT0_LFB_TO_MEMORY_FIFO(val) (((val) >> 11) & 1)
	1202	#define FBIINIT0_TEXMEM_TO_MEMORY_FIFO(val) (((val) >> 12) & 1)
	1203	#define FBIINIT0_ENABLE_MEMORY_FIFO(val) (((val) >> 13) & 1)
	1204	#define FBIINIT0_MEMORY_FIFO_HWM(val) (((val) >> 14) & 0x7ff)
	1205	#define FBIINIT0_MEMORY_FIFO_BURST(val) (((val) >> 25) & 0x3f)
	1206
	1207	#define FBIINIT1_PCI_DEV_FUNCTION(val) (((val) >> 0) & 1)
	1208	#define FBIINIT1_PCI_WRITE_WAIT_STATES(val) (((val) >> 1) & 1)
	1209	#define FBIINIT1_MULTI_SST1(val) (((val) >> 2) & 1) /* not on voodoo 2 */
	1210	#define FBIINIT1_ENABLE_LFB(val) (((val) >> 3) & 1)
	1211	#define FBIINIT1_X_VIDEO_TILES(val) (((val) >> 4) & 0xf)
	1212	#define FBIINIT1_VIDEO_TIMING_RESET(val) (((val) >> 8) & 1)
	1213	#define FBIINIT1_SOFTWARE_OVERRIDE(val) (((val) >> 9) & 1)
	1214	#define FBIINIT1_SOFTWARE_HSYNC(val) (((val) >> 10) & 1)
	1215	#define FBIINIT1_SOFTWARE_VSYNC(val) (((val) >> 11) & 1)
	1216	#define FBIINIT1_SOFTWARE_BLANK(val) (((val) >> 12) & 1)
	1217	#define FBIINIT1_DRIVE_VIDEO_TIMING(val) (((val) >> 13) & 1)
	1218	#define FBIINIT1_DRIVE_VIDEO_BLANK(val) (((val) >> 14) & 1)
	1219	#define FBIINIT1_DRIVE_VIDEO_SYNC(val) (((val) >> 15) & 1)
	1220	#define FBIINIT1_DRIVE_VIDEO_DCLK(val) (((val) >> 16) & 1)
	1221	#define FBIINIT1_VIDEO_TIMING_VCLK(val) (((val) >> 17) & 1)
	1222	#define FBIINIT1_VIDEO_CLK_2X_DELAY(val) (((val) >> 18) & 3)
	1223	#define FBIINIT1_VIDEO_TIMING_SOURCE(val) (((val) >> 20) & 3)
	1224	#define FBIINIT1_ENABLE_24BPP_OUTPUT(val) (((val) >> 22) & 1)
	1225	#define FBIINIT1_ENABLE_SLI(val) (((val) >> 23) & 1)
	1226	#define FBIINIT1_X_VIDEO_TILES_BIT5(val) (((val) >> 24) & 1) /* voodoo 2 only */
	1227	#define FBIINIT1_ENABLE_EDGE_FILTER(val) (((val) >> 25) & 1)
	1228	#define FBIINIT1_INVERT_VID_CLK_2X(val) (((val) >> 26) & 1)
	1229	#define FBIINIT1_VID_CLK_2X_SEL_DELAY(val) (((val) >> 27) & 3)
	1230	#define FBIINIT1_VID_CLK_DELAY(val) (((val) >> 29) & 3)
	1231	#define FBIINIT1_DISABLE_FAST_READAHEAD(val) (((val) >> 31) & 1)
	1232
	1233	#define FBIINIT2_DISABLE_DITHER_SUB(val) (((val) >> 0) & 1)
	1234	#define FBIINIT2_DRAM_BANKING(val) (((val) >> 1) & 1)
	1235	#define FBIINIT2_ENABLE_TRIPLE_BUF(val) (((val) >> 4) & 1)
	1236	#define FBIINIT2_ENABLE_FAST_RAS_READ(val) (((val) >> 5) & 1)
	1237	#define FBIINIT2_ENABLE_GEN_DRAM_OE(val) (((val) >> 6) & 1)
	1238	#define FBIINIT2_ENABLE_FAST_READWRITE(val) (((val) >> 7) & 1)
	1239	#define FBIINIT2_ENABLE_PASSTHRU_DITHER(val) (((val) >> 8) & 1)
	1240	#define FBIINIT2_SWAP_BUFFER_ALGORITHM(val) (((val) >> 9) & 3)
	1241	#define FBIINIT2_VIDEO_BUFFER_OFFSET(val) (((val) >> 11) & 0x1ff)
	1242	#define FBIINIT2_ENABLE_DRAM_BANKING(val) (((val) >> 20) & 1)
	1243	#define FBIINIT2_ENABLE_DRAM_READ_FIFO(val) (((val) >> 21) & 1)
	1244	#define FBIINIT2_ENABLE_DRAM_REFRESH(val) (((val) >> 22) & 1)
	1245	#define FBIINIT2_REFRESH_LOAD_VALUE(val) (((val) >> 23) & 0x1ff)
	1246
	1247	#define FBIINIT3_TRI_REGISTER_REMAP(val) (((val) >> 0) & 1)
	1248	#define FBIINIT3_VIDEO_FIFO_THRESH(val) (((val) >> 1) & 0x1f)
	1249	#define FBIINIT3_DISABLE_TMUS(val) (((val) >> 6) & 1)
	1250	#define FBIINIT3_FBI_MEMORY_TYPE(val) (((val) >> 8) & 7)
	1251	#define FBIINIT3_VGA_PASS_RESET_VAL(val) (((val) >> 11) & 1)
	1252	#define FBIINIT3_HARDCODE_PCI_BASE(val) (((val) >> 12) & 1)
	1253	#define FBIINIT3_FBI2TREX_DELAY(val) (((val) >> 13) & 0xf)
	1254	#define FBIINIT3_TREX2FBI_DELAY(val) (((val) >> 17) & 0x1f)
	1255	#define FBIINIT3_YORIGIN_SUBTRACT(val) (((val) >> 22) & 0x3ff)
	1256
	1257	#define FBIINIT4_PCI_READ_WAITS(val) (((val) >> 0) & 1)
	1258	#define FBIINIT4_ENABLE_LFB_READAHEAD(val) (((val) >> 1) & 1)
	1259	#define FBIINIT4_MEMORY_FIFO_LWM(val) (((val) >> 2) & 0x3f)
	1260	#define FBIINIT4_MEMORY_FIFO_START_ROW(val) (((val) >> 8) & 0x3ff)
	1261	#define FBIINIT4_MEMORY_FIFO_STOP_ROW(val) (((val) >> 18) & 0x3ff)
	1262	#define FBIINIT4_VIDEO_CLOCKING_DELAY(val) (((val) >> 29) & 7) /* voodoo 2 only */
	1263
	1264	#define FBIINIT5_DISABLE_PCI_STOP(val) (((val) >> 0) & 1) /* voodoo 2 only */
	1265	#define FBIINIT5_PCI_SLAVE_SPEED(val) (((val) >> 1) & 1) /* voodoo 2 only */
	1266	#define FBIINIT5_DAC_DATA_OUTPUT_WIDTH(val) (((val) >> 2) & 1) /* voodoo 2 only */
	1267	#define FBIINIT5_DAC_DATA_17_OUTPUT(val) (((val) >> 3) & 1) /* voodoo 2 only */
	1268	#define FBIINIT5_DAC_DATA_18_OUTPUT(val) (((val) >> 4) & 1) /* voodoo 2 only */
	1269	#define FBIINIT5_GENERIC_STRAPPING(val) (((val) >> 5) & 0xf) /* voodoo 2 only */
	1270	#define FBIINIT5_BUFFER_ALLOCATION(val) (((val) >> 9) & 3) /* voodoo 2 only */
	1271	#define FBIINIT5_DRIVE_VID_CLK_SLAVE(val) (((val) >> 11) & 1) /* voodoo 2 only */
	1272	#define FBIINIT5_DRIVE_DAC_DATA_16(val) (((val) >> 12) & 1) /* voodoo 2 only */
	1273	#define FBIINIT5_VCLK_INPUT_SELECT(val) (((val) >> 13) & 1) /* voodoo 2 only */
	1274	#define FBIINIT5_MULTI_CVG_DETECT(val) (((val) >> 14) & 1) /* voodoo 2 only */
	1275	#define FBIINIT5_SYNC_RETRACE_READS(val) (((val) >> 15) & 1) /* voodoo 2 only */
	1276	#define FBIINIT5_ENABLE_RHBORDER_COLOR(val) (((val) >> 16) & 1) /* voodoo 2 only */
	1277	#define FBIINIT5_ENABLE_LHBORDER_COLOR(val) (((val) >> 17) & 1) /* voodoo 2 only */
	1278	#define FBIINIT5_ENABLE_BVBORDER_COLOR(val) (((val) >> 18) & 1) /* voodoo 2 only */
	1279	#define FBIINIT5_ENABLE_TVBORDER_COLOR(val) (((val) >> 19) & 1) /* voodoo 2 only */
	1280	#define FBIINIT5_DOUBLE_HORIZ(val) (((val) >> 20) & 1) /* voodoo 2 only */
	1281	#define FBIINIT5_DOUBLE_VERT(val) (((val) >> 21) & 1) /* voodoo 2 only */
	1282	#define FBIINIT5_ENABLE_16BIT_GAMMA(val) (((val) >> 22) & 1) /* voodoo 2 only */
	1283	#define FBIINIT5_INVERT_DAC_HSYNC(val) (((val) >> 23) & 1) /* voodoo 2 only */
	1284	#define FBIINIT5_INVERT_DAC_VSYNC(val) (((val) >> 24) & 1) /* voodoo 2 only */
	1285	#define FBIINIT5_ENABLE_24BIT_DACDATA(val) (((val) >> 25) & 1) /* voodoo 2 only */
	1286	#define FBIINIT5_ENABLE_INTERLACING(val) (((val) >> 26) & 1) /* voodoo 2 only */
	1287	#define FBIINIT5_DAC_DATA_18_CONTROL(val) (((val) >> 27) & 1) /* voodoo 2 only */
	1288	#define FBIINIT5_RASTERIZER_UNIT_MODE(val) (((val) >> 30) & 3) /* voodoo 2 only */
	1289
	1290	#define FBIINIT6_WINDOW_ACTIVE_COUNTER(val) (((val) >> 0) & 7) /* voodoo 2 only */
	1291	#define FBIINIT6_WINDOW_DRAG_COUNTER(val) (((val) >> 3) & 0x1f) /* voodoo 2 only */
	1292	#define FBIINIT6_SLI_SYNC_MASTER(val) (((val) >> 8) & 1) /* voodoo 2 only */
	1293	#define FBIINIT6_DAC_DATA_22_OUTPUT(val) (((val) >> 9) & 3) /* voodoo 2 only */
	1294	#define FBIINIT6_DAC_DATA_23_OUTPUT(val) (((val) >> 11) & 3) /* voodoo 2 only */
	1295	#define FBIINIT6_SLI_SYNCIN_OUTPUT(val) (((val) >> 13) & 3) /* voodoo 2 only */
	1296	#define FBIINIT6_SLI_SYNCOUT_OUTPUT(val) (((val) >> 15) & 3) /* voodoo 2 only */
	1297	#define FBIINIT6_DAC_RD_OUTPUT(val) (((val) >> 17) & 3) /* voodoo 2 only */
	1298	#define FBIINIT6_DAC_WR_OUTPUT(val) (((val) >> 19) & 3) /* voodoo 2 only */
	1299	#define FBIINIT6_PCI_FIFO_LWM_RDY(val) (((val) >> 21) & 0x7f) /* voodoo 2 only */
	1300	#define FBIINIT6_VGA_PASS_N_OUTPUT(val) (((val) >> 28) & 3) /* voodoo 2 only */
	1301	#define FBIINIT6_X_VIDEO_TILES_BIT0(val) (((val) >> 30) & 1) /* voodoo 2 only */
	1302
	1303	#define FBIINIT7_GENERIC_STRAPPING(val) (((val) >> 0) & 0xff) /* voodoo 2 only */
	1304	#define FBIINIT7_CMDFIFO_ENABLE(val) (((val) >> 8) & 1) /* voodoo 2 only */
	1305	#define FBIINIT7_CMDFIFO_MEMORY_STORE(val) (((val) >> 9) & 1) /* voodoo 2 only */
	1306	#define FBIINIT7_DISABLE_CMDFIFO_HOLES(val) (((val) >> 10) & 1) /* voodoo 2 only */
	1307	#define FBIINIT7_CMDFIFO_READ_THRESH(val) (((val) >> 11) & 0x1f) /* voodoo 2 only */
	1308	#define FBIINIT7_SYNC_CMDFIFO_WRITES(val) (((val) >> 16) & 1) /* voodoo 2 only */
	1309	#define FBIINIT7_SYNC_CMDFIFO_READS(val) (((val) >> 17) & 1) /* voodoo 2 only */
	1310	#define FBIINIT7_RESET_PCI_PACKER(val) (((val) >> 18) & 1) /* voodoo 2 only */
	1311	#define FBIINIT7_ENABLE_CHROMA_STUFF(val) (((val) >> 19) & 1) /* voodoo 2 only */
	1312	#define FBIINIT7_CMDFIFO_PCI_TIMEOUT(val) (((val) >> 20) & 0x7f) /* voodoo 2 only */
	1313	#define FBIINIT7_ENABLE_TEXTURE_BURST(val) (((val) >> 27) & 1) /* voodoo 2 only */
	1314
	1315	#define TEXMODE_ENABLE_PERSPECTIVE(val) (((val) >> 0) & 1)
	1316	#define TEXMODE_MINIFICATION_FILTER(val) (((val) >> 1) & 1)
	1317	#define TEXMODE_MAGNIFICATION_FILTER(val) (((val) >> 2) & 1)
	1318	#define TEXMODE_CLAMP_NEG_W(val) (((val) >> 3) & 1)
	1319	#define TEXMODE_ENABLE_LOD_DITHER(val) (((val) >> 4) & 1)
	1320	#define TEXMODE_NCC_TABLE_SELECT(val) (((val) >> 5) & 1)
	1321	#define TEXMODE_CLAMP_S(val) (((val) >> 6) & 1)
	1322	#define TEXMODE_CLAMP_T(val) (((val) >> 7) & 1)
	1323	#define TEXMODE_FORMAT(val) (((val) >> 8) & 0xf)
	1324	#define TEXMODE_TC_ZERO_OTHER(val) (((val) >> 12) & 1)
	1325	#define TEXMODE_TC_SUB_CLOCAL(val) (((val) >> 13) & 1)
	1326	#define TEXMODE_TC_MSELECT(val) (((val) >> 14) & 7)
	1327	#define TEXMODE_TC_REVERSE_BLEND(val) (((val) >> 17) & 1)
	1328	#define TEXMODE_TC_ADD_ACLOCAL(val) (((val) >> 18) & 3)
	1329	#define TEXMODE_TC_INVERT_OUTPUT(val) (((val) >> 20) & 1)
	1330	#define TEXMODE_TCA_ZERO_OTHER(val) (((val) >> 21) & 1)
	1331	#define TEXMODE_TCA_SUB_CLOCAL(val) (((val) >> 22) & 1)
	1332	#define TEXMODE_TCA_MSELECT(val) (((val) >> 23) & 7)
	1333	#define TEXMODE_TCA_REVERSE_BLEND(val) (((val) >> 26) & 1)
	1334	#define TEXMODE_TCA_ADD_ACLOCAL(val) (((val) >> 27) & 3)
	1335	#define TEXMODE_TCA_INVERT_OUTPUT(val) (((val) >> 29) & 1)
	1336	#define TEXMODE_TRILINEAR(val) (((val) >> 30) & 1)
	1337	#define TEXMODE_SEQ_8_DOWNLD(val) (((val) >> 31) & 1)
	1338
	1339	#define TEXLOD_LODMIN(val) (((val) >> 0) & 0x3f)
	1340	#define TEXLOD_LODMAX(val) (((val) >> 6) & 0x3f)
	1341	#define TEXLOD_LODBIAS(val) (((val) >> 12) & 0x3f)
	1342	#define TEXLOD_LOD_ODD(val) (((val) >> 18) & 1)
	1343	#define TEXLOD_LOD_TSPLIT(val) (((val) >> 19) & 1)
	1344	#define TEXLOD_LOD_S_IS_WIDER(val) (((val) >> 20) & 1)
	1345	#define TEXLOD_LOD_ASPECT(val) (((val) >> 21) & 3)
	1346	#define TEXLOD_LOD_ZEROFRAC(val) (((val) >> 23) & 1)
	1347	#define TEXLOD_TMULTIBASEADDR(val) (((val) >> 24) & 1)
	1348	#define TEXLOD_TDATA_SWIZZLE(val) (((val) >> 25) & 1)
	1349	#define TEXLOD_TDATA_SWAP(val) (((val) >> 26) & 1)
	1350	#define TEXLOD_TDIRECT_WRITE(val) (((val) >> 27) & 1) /* Voodoo 2 only */
	1351
	1352	#define TEXDETAIL_DETAIL_MAX(val) (((val) >> 0) & 0xff)
	1353	#define TEXDETAIL_DETAIL_BIAS(val) (((val) >> 8) & 0x3f)
	1354	#define TEXDETAIL_DETAIL_SCALE(val) (((val) >> 14) & 7)
	1355	#define TEXDETAIL_RGB_MIN_FILTER(val) (((val) >> 17) & 1) /* Voodoo 2 only */
	1356	#define TEXDETAIL_RGB_MAG_FILTER(val) (((val) >> 18) & 1) /* Voodoo 2 only */
	1357	#define TEXDETAIL_ALPHA_MIN_FILTER(val) (((val) >> 19) & 1) /* Voodoo 2 only */
	1358	#define TEXDETAIL_ALPHA_MAG_FILTER(val) (((val) >> 20) & 1) /* Voodoo 2 only */
	1359	#define TEXDETAIL_SEPARATE_RGBA_FILTER(val) (((val) >> 21) & 1) /* Voodoo 2 only */
	1360
	1361	#define TREXINIT_SEND_TMU_CONFIG(val) (((val) >> 18) & 1)
	1362
	1363
	1364
	1365	struct voodoo_state;
	1366	struct poly_extra_data;
	1367	class voodoo_device;
	1368
	1369	struct rgba
	1370	{
	1371	#ifdef LSB_FIRST
	1372	UINT8 b, g, r, a;
	1373	#else
	1374	UINT8 a, r, g, b;
	1375	#endif
	1376	};
	1377
	1378
	1379	union voodoo_reg
	1380	{
	1381	INT32 i;
	1382	UINT32 u;
	1383	float f;
	1384	rgba rgb;
	1385	};
	1386
	1387
	1388
	1389	struct voodoo_stats
	1390	{
	1391	UINT8 lastkey; /* last key state */
	1392	UINT8 display; /* display stats? */
	1393	INT32 swaps; /* total swaps */
	1394	INT32 stalls; /* total stalls */
	1395	INT32 total_triangles; /* total triangles */
	1396	INT32 total_pixels_in; /* total pixels in */
	1397	INT32 total_pixels_out; /* total pixels out */
	1398	INT32 total_chroma_fail; /* total chroma fail */
	1399	INT32 total_zfunc_fail; /* total z func fail */
	1400	INT32 total_afunc_fail; /* total a func fail */
	1401	INT32 total_clipped; /* total clipped */
	1402	INT32 total_stippled; /* total stippled */
	1403	INT32 lfb_writes; /* LFB writes */
	1404	INT32 lfb_reads; /* LFB reads */
	1405	INT32 reg_writes; /* register writes */
	1406	INT32 reg_reads; /* register reads */
	1407	INT32 tex_writes; /* texture writes */
	1408	INT32 texture_mode[16]; /* 16 different texture modes */
	1409	UINT8 render_override; /* render override */
	1410	char buffer[1024]; /* string */
	1411	};
	1412
	1413
	1414	/* note that this structure is an even 64 bytes long */
	1415	struct stats_block
	1416	{
	1417	INT32 pixels_in; /* pixels in statistic */
	1418	INT32 pixels_out; /* pixels out statistic */
	1419	INT32 chroma_fail; /* chroma test fail statistic */
	1420	INT32 zfunc_fail; /* z function test fail statistic */
	1421	INT32 afunc_fail; /* alpha function test fail statistic */
	1422	INT32 clip_fail; /* clipping fail statistic */
	1423	INT32 stipple_count; /* stipple statistic */
	1424	INT32 filler[64/4 - 7]; /* pad this structure to 64 bytes */
	1425	};
	1426
	1427
	1428	struct fifo_state
	1429	{
	1430	UINT32 * base; /* base of the FIFO */
	1431	INT32 size; /* size of the FIFO */
	1432	INT32 in; /* input pointer */
	1433	INT32 out; /* output pointer */
	1434	};
	1435
	1436
	1437	struct cmdfifo_info
	1438	{
	1439	UINT8 enable; /* enabled? */
	1440	UINT8 count_holes; /* count holes? */
	1441	UINT32 base; /* base address in framebuffer RAM */
	1442	UINT32 end; /* end address in framebuffer RAM */
	1443	UINT32 rdptr; /* current read pointer */
	1444	UINT32 amin; /* minimum address */
	1445	UINT32 amax; /* maximum address */
	1446	UINT32 depth; /* current depth */
	1447	UINT32 holes; /* number of holes */
	1448	};
	1449
	1450
	1451	struct pci_state
	1452	{
	1453	fifo_state fifo; /* PCI FIFO */
	1454	UINT32 init_enable; /* initEnable value */
	1455	UINT8 stall_state; /* state of the system if we're stalled */
	1456	UINT8 op_pending; /* true if an operation is pending */
	1457	attotime op_end_time; /* time when the pending operation ends */
	1458	emu_timer * continue_timer; /* timer to use to continue processing */
	1459	UINT32 fifo_mem[642]; / memory backing the PCI FIFO */
	1460	};
	1461
	1462
	1463	struct ncc_table
	1464	{
	1465	UINT8 dirty; /* is the texel lookup dirty? */
	1466	voodoo_reg * reg; /* pointer to our registers */
	1467	INT32 ir[4], ig[4], ib[4]; /* I values for R,G,B */
	1468	INT32 qr[4], qg[4], qb[4]; /* Q values for R,G,B */
	1469	INT32 y[16]; /* Y values */
	1470	rgb_t * palette; /* pointer to associated RGB palette */
	1471	rgb_t * palettea; /* pointer to associated ARGB palette */
	1472	rgb_t texel[256]; /* texel lookup */
	1473	};
	1474
	1475
	1476	struct tmu_state
	1477	{
	1478	UINT8 * ram; /* pointer to our RAM */
	1479	UINT32 mask; /* mask to apply to pointers */
	1480	voodoo_reg * reg; /* pointer to our register base */
	1481	UINT32 regdirty; /* true if the LOD/mode/base registers have changed */
	1482
	1483	UINT32 texaddr_mask; /* mask for texture address */
	1484	UINT8 texaddr_shift; /* shift for texture address */
	1485
	1486	INT64 starts, startt; /* starting S,T (14.18) */
	1487	INT64 startw; /* starting W (2.30) */
	1488	INT64 dsdx, dtdx; /* delta S,T per X */
	1489	INT64 dwdx; /* delta W per X */
	1490	INT64 dsdy, dtdy; /* delta S,T per Y */
	1491	INT64 dwdy; /* delta W per Y */
	1492
	1493	INT32 lodmin, lodmax; /* min, max LOD values */
	1494	INT32 lodbias; /* LOD bias */
	1495	UINT32 lodmask; /* mask of available LODs */
	1496	UINT32 lodoffset[9]; /* offset of texture base for each LOD */
	1497	INT32 detailmax; /* detail clamp */
	1498	INT32 detailbias; /* detail bias */
	1499	UINT8 detailscale; /* detail scale */
	1500
	1501	UINT32 wmask; /* mask for the current texture width */
	1502	UINT32 hmask; /* mask for the current texture height */
	1503
	1504	UINT32 bilinear_mask; /* mask for bilinear resolution (0xf0 for V1, 0xff for V2) */
	1505
	1506	ncc_table ncc[2]; /* two NCC tables */
	1507
	1508	rgb_t * lookup; /* currently selected lookup */
	1509	rgb_t * texel[16]; /* texel lookups for each format */
	1510
	1511	rgb_t palette[256]; /* palette lookup table */
	1512	rgb_t palettea[256]; /* palette+alpha lookup table */
	1513	};
	1514
	1515
	1516	struct tmu_shared_state
	1517	{
	1518	rgb_t rgb332[256]; /* RGB 3-3-2 lookup table */
	1519	rgb_t alpha8[256]; /* alpha 8-bit lookup table */
	1520	rgb_t int8[256]; /* intensity 8-bit lookup table */
	1521	rgb_t ai44[256]; /* alpha, intensity 4-4 lookup table */
	1522
	1523	rgb_t rgb565[65536]; /* RGB 5-6-5 lookup table */
	1524	rgb_t argb1555[65536]; /* ARGB 1-5-5-5 lookup table */
	1525	rgb_t argb4444[65536]; /* ARGB 4-4-4-4 lookup table */
	1526	};
	1527
	1528
	1529	struct setup_vertex
	1530	{
	1531	float x, y; /* X, Y coordinates */
	1532	float a, r, g, b; /* A, R, G, B values */
	1533	float z, wb; /* Z and broadcast W values */
	1534	float w0, s0, t0; /* W, S, T for TMU 0 */
	1535	float w1, s1, t1; /* W, S, T for TMU 1 */
	1536	};
	1537
	1538
	1539	struct fbi_state
	1540	{
	1541	UINT8 * ram; /* pointer to frame buffer RAM */
	1542	UINT32 mask; /* mask to apply to pointers */
	1543	UINT32 rgboffs[3]; /* word offset to 3 RGB buffers */
	1544	UINT32 auxoffs; /* word offset to 1 aux buffer */
	1545
	1546	UINT8 frontbuf; /* front buffer index */
	1547	UINT8 backbuf; /* back buffer index */
	1548	UINT8 swaps_pending; /* number of pending swaps */
	1549	UINT8 video_changed; /* did the frontbuffer video change? */
	1550
	1551	UINT32 yorigin; /* Y origin subtract value */
	1552	UINT32 lfb_base; /* base of LFB in memory */
	1553	UINT8 lfb_stride; /* stride of LFB accesses in bits */
	1554
	1555	UINT32 width; /* width of current frame buffer */
	1556	UINT32 height; /* height of current frame buffer */
	1557	UINT32 xoffs; /* horizontal offset (back porch) */
	1558	UINT32 yoffs; /* vertical offset (back porch) */
	1559	UINT32 vsyncscan; /* vertical sync scanline */
	1560	UINT32 rowpixels; /* pixels per row */
	1561	UINT32 tile_width; /* width of video tiles */
	1562	UINT32 tile_height; /* height of video tiles */
	1563	UINT32 x_tiles; /* number of tiles in the X direction */
	1564
	1565	emu_timer * vblank_timer; /* VBLANK timer */
	1566	UINT8 vblank; /* VBLANK state */
	1567	UINT8 vblank_count; /* number of VBLANKs since last swap */
	1568	UINT8 vblank_swap_pending; /* a swap is pending, waiting for a vblank */
	1569	UINT8 vblank_swap; /* swap when we hit this count */
	1570	UINT8 vblank_dont_swap; /* don't actually swap when we hit this point */
	1571
	1572	/* triangle setup info */
	1573	UINT8 cheating_allowed; /* allow cheating? */
	1574	INT32 sign; /* triangle sign */
	1575	INT16 ax, ay; /* vertex A x,y (12.4) */
	1576	INT16 bx, by; /* vertex B x,y (12.4) */
	1577	INT16 cx, cy; /* vertex C x,y (12.4) */
	1578	INT32 startr, startg, startb, starta; /* starting R,G,B,A (12.12) */
	1579	INT32 startz; /* starting Z (20.12) */
	1580	INT64 startw; /* starting W (16.32) */
	1581	INT32 drdx, dgdx, dbdx, dadx; /* delta R,G,B,A per X */
	1582	INT32 dzdx; /* delta Z per X */
	1583	INT64 dwdx; /* delta W per X */
	1584	INT32 drdy, dgdy, dbdy, dady; /* delta R,G,B,A per Y */
	1585	INT32 dzdy; /* delta Z per Y */
	1586	INT64 dwdy; /* delta W per Y */
	1587
	1588	stats_block lfb_stats; /* LFB-access statistics */
	1589
	1590	UINT8 sverts; /* number of vertices ready */
	1591	setup_vertex svert[3]; /* 3 setup vertices */
	1592
	1593	fifo_state fifo; /* framebuffer memory fifo */
	1594	cmdfifo_info cmdfifo[2]; /* command FIFOs */
	1595
	1596	UINT8 fogblend[64]; /* 64-entry fog table */
	1597	UINT8 fogdelta[64]; /* 64-entry fog table */
	1598	UINT8 fogdelta_mask; /* mask for for delta (0xff for V1, 0xfc for V2) */
	1599
	1600	rgb_t pen[65536]; /* mapping from pixels to pens */
	1601	rgb_t clut[512]; /* clut gamma data */
	1602	UINT8 clut_dirty; /* do we need to recompute? */
	1603	};
	1604
	1605
	1606	struct dac_state
	1607	{
	1608	UINT8 reg[8]; /* 8 registers */
	1609	UINT8 read_result; /* pending read result */
	1610	};
	1611
	1612
	1613	struct raster_info
	1614	{
	1615	raster_info * next; /* pointer to next entry with the same hash */
	1616	poly_draw_scanline_func callback; /* callback pointer */
	1617	UINT8 is_generic; /* TRUE if this is one of the generic rasterizers */
	1618	UINT8 display; /* display index */
	1619	UINT32 hits; /* how many hits (pixels) we've used this for */
	1620	UINT32 polys; /* how many polys we've used this for */
	1621	UINT32 eff_color_path; /* effective fbzColorPath value */
	1622	UINT32 eff_alpha_mode; /* effective alphaMode value */
	1623	UINT32 eff_fog_mode; /* effective fogMode value */
	1624	UINT32 eff_fbz_mode; /* effective fbzMode value */
	1625	UINT32 eff_tex_mode_0; /* effective textureMode value for TMU #0 */
	1626	UINT32 eff_tex_mode_1; /* effective textureMode value for TMU #1 */
	1627	UINT32 hash;
	1628	};
	1629
	1630
	1631	struct poly_extra_data
	1632	{
	1633	voodoo_device * device;
	1634	raster_info * info; /* pointer to rasterizer information */
	1635
	1636	INT16 ax, ay; /* vertex A x,y (12.4) */
	1637	INT32 startr, startg, startb, starta; /* starting R,G,B,A (12.12) */
	1638	INT32 startz; /* starting Z (20.12) */
	1639	INT64 startw; /* starting W (16.32) */
	1640	INT32 drdx, dgdx, dbdx, dadx; /* delta R,G,B,A per X */
	1641	INT32 dzdx; /* delta Z per X */
	1642	INT64 dwdx; /* delta W per X */
	1643	INT32 drdy, dgdy, dbdy, dady; /* delta R,G,B,A per Y */
	1644	INT32 dzdy; /* delta Z per Y */
	1645	INT64 dwdy; /* delta W per Y */
	1646
	1647	INT64 starts0, startt0; /* starting S,T (14.18) */
	1648	INT64 startw0; /* starting W (2.30) */
	1649	INT64 ds0dx, dt0dx; /* delta S,T per X */
	1650	INT64 dw0dx; /* delta W per X */
	1651	INT64 ds0dy, dt0dy; /* delta S,T per Y */
	1652	INT64 dw0dy; /* delta W per Y */
	1653	INT32 lodbase0; /* used during rasterization */
	1654
	1655	INT64 starts1, startt1; /* starting S,T (14.18) */
	1656	INT64 startw1; /* starting W (2.30) */
	1657	INT64 ds1dx, dt1dx; /* delta S,T per X */
	1658	INT64 dw1dx; /* delta W per X */
	1659	INT64 ds1dy, dt1dy; /* delta S,T per Y */
	1660	INT64 dw1dy; /* delta W per Y */
	1661	INT32 lodbase1; /* used during rasterization */
	1662
	1663	UINT16 dither[16]; /* dither matrix, for fastfill */
	1664	};
	1665
	1666
	1667	struct banshee_info
	1668	{
	1669	UINT32 io[0x40]; /* I/O registers */
	1670	UINT32 agp[0x80]; /* AGP registers */
	1671	UINT8 vga[0x20]; /* VGA registers */
	1672	UINT8 crtc[0x27]; /* VGA CRTC registers */
	1673	UINT8 seq[0x05]; /* VGA sequencer registers */
	1674	UINT8 gc[0x05]; /* VGA graphics controller registers */
	1675	UINT8 att[0x15]; /* VGA attribute registers */
	1676	UINT8 attff; /* VGA attribute flip-flop */
	1677
	1678	UINT32 blt_regs[0x20]; /* 2D Blitter registers */
	1679	UINT32 blt_dst_base;
	1680	UINT32 blt_dst_x;
	1681	UINT32 blt_dst_y;
	1682	UINT32 blt_dst_width;
	1683	UINT32 blt_dst_height;
	1684	UINT32 blt_dst_stride;
	1685	UINT32 blt_dst_bpp;
	1686	UINT32 blt_cmd;
	1687	UINT32 blt_src_base;
	1688	UINT32 blt_src_x;
	1689	UINT32 blt_src_y;
	1690	UINT32 blt_src_width;
	1691	UINT32 blt_src_height;
	1692	UINT32 blt_src_stride;
	1693	UINT32 blt_src_bpp;
	1694	};
	1695
	1696
	1697	typedef voodoo_reg rgb_union;
	1698
	1699
	1700
	1701
	1702
18	1703	/***************************************************************************
19	1704	CONSTANTS
20	1705	***************************************************************************/
r253153	r253154
61	1746	FUNCTION PROTOTYPES
62	1747	***************************************************************************/
63	1748
64		int voodoo_update(device_t *device, bitmap_rgb32 &bitmap, const rectangle &cliprect);
65		int voodoo_get_type(device_t *device);
66		int voodoo_is_stalled(device_t *device);
67		void voodoo_set_init_enable(device_t *device, UINT32 newval);
	1749	struct stats_block;
68	1750
69	1751	/* ----- device interface ----- */
70	1752
r253153	r253154
86	1768	DECLARE_WRITE32_MEMBER( voodoo_w );
87	1769
88	1770	// access to legacy token
89		struct voodoo_state *token() const { assert(m_token != nullptr); return m_token; }
90	1771	void common_start_voodoo(UINT8 type);
91	1772
92	1773	UINT8 m_fbmem;
r253153	r253154
96	1777	const char * m_cputag;
97	1778	devcb_write_line m_vblank;
98	1779	devcb_write_line m_stall;
	1780
	1781	TIMER_CALLBACK_MEMBER( vblank_off_callback );
	1782	TIMER_CALLBACK_MEMBER( stall_cpu_callback );
	1783	TIMER_CALLBACK_MEMBER( vblank_callback );
99	1784
	1785	static void voodoo_postload(voodoo_device *vd);
	1786
	1787	int voodoo_update(bitmap_rgb32 &bitmap, const rectangle &cliprect);
	1788	int voodoo_get_type();
	1789	int voodoo_is_stalled();
	1790	void voodoo_set_init_enable(UINT32 newval);
	1791
	1792	// not all of these need to be static, review.
	1793
	1794	static void check_stalled_cpu(voodoo_device* vd, attotime current_time);
	1795	static void flush_fifos( voodoo_device* vd, attotime current_time);
	1796	static void init_fbi(voodoo_device vd, fbi_state f, void *memory, int fbmem);
	1797	static INT32 register_w(voodoo_device *vd, offs_t offset, UINT32 data);
	1798	static INT32 swapbuffer(voodoo_device *vd, UINT32 data);
	1799	static void init_tmu(voodoo_device vd, tmu_state t, voodoo_reg reg, void memory, int tmem);
	1800	static INT32 lfb_w(voodoo_device *vd, offs_t offset, UINT32 data, UINT32 mem_mask);
	1801	static INT32 texture_w(voodoo_device *vd, offs_t offset, UINT32 data);
	1802	static INT32 lfb_direct_w(voodoo_device *vd, offs_t offset, UINT32 data, UINT32 mem_mask);
	1803	static INT32 banshee_2d_w(voodoo_device *vd, offs_t offset, UINT32 data);
	1804	static void stall_cpu(voodoo_device *vd, int state, attotime current_time);
	1805	static void soft_reset(voodoo_device *vd);
	1806	static void recompute_video_memory(voodoo_device *vd);
	1807	static INT32 fastfill(voodoo_device *vd);
	1808	static INT32 triangle(voodoo_device *vd);
	1809	static INT32 begin_triangle(voodoo_device *vd);
	1810	static INT32 draw_triangle(voodoo_device *vd);
	1811	static INT32 setup_and_draw_triangle(voodoo_device *vd);
	1812	static INT32 triangle_create_work_item(voodoo_device* vd,UINT16 *drawbuf, int texcount);
	1813	static raster_info add_rasterizer(voodoo_device vd, const raster_info *cinfo);
	1814	static raster_info find_rasterizer(voodoo_device vd, int texcount);
	1815	static void dump_rasterizer_stats(voodoo_device *vd);
	1816	static void init_tmu_shared(tmu_shared_state *s);
	1817
	1818	static void swap_buffers(voodoo_device *vd);
	1819	static UINT32 cmdfifo_execute(voodoo_device vd, cmdfifo_info f);
	1820	static INT32 cmdfifo_execute_if_ready(voodoo_device* vd, cmdfifo_info *f);
	1821	static void cmdfifo_w(voodoo_device vd, cmdfifo_info f, offs_t offset, UINT32 data);
	1822
	1823	static void raster_fastfill(void dest, INT32 scanline, const poly_extent extent, const void *extradata, int threadid);
	1824	static void raster_generic_0tmu(void dest, INT32 scanline, const poly_extent extent, const void *extradata, int threadid);
	1825	static void raster_generic_1tmu(void dest, INT32 scanline, const poly_extent extent, const void *extradata, int threadid);
	1826	static void raster_generic_2tmu(void dest, INT32 scanline, const poly_extent extent, const void *extradata, int threadid);
	1827
	1828	#define RASTERIZER_HEADER(name) \
	1829	static void raster_##name(void destbase, INT32 y, const poly_extent extent, const void *extradata, int threadid); \
	1830
	1831	#define RASTERIZER_ENTRY(fbzcp, alpha, fog, fbz, tex0, tex1) \
	1832	RASTERIZER_HEADER(fbzcp##_##alpha##_##fog##_##fbz##_##tex0##_##tex1) \
	1833
	1834	#include "voodoo_rast.inc"
	1835
	1836	#undef RASTERIZER_ENTRY
	1837
	1838
	1839
100	1840	protected:
101	1841	// device-level overrides
102	1842	virtual void device_config_complete() override;
103	1843	virtual void device_stop() override;
104	1844	virtual void device_reset() override;
105		private:
106		// internal state
107		struct voodoo_state *m_token;
	1845	public:
	1846	// voodoo_state
	1847	UINT8 index; /* index of board */
	1848	voodoo_device device; / pointer to our containing device */
	1849	screen_device screen; / the screen we are acting on */
	1850	device_t cpu; / the CPU we interact with */
	1851	UINT8 vd_type; /* type of system */
	1852	UINT8 chipmask; /* mask for which chips are available */
	1853	UINT32 freq; /* operating frequency */
	1854	attoseconds_t attoseconds_per_cycle; /* attoseconds per cycle */
	1855	UINT32 extra_cycles; /* extra cycles not yet accounted for */
	1856	int trigger; /* trigger used for stalling */
	1857
	1858	voodoo_reg reg[0x400]; /* raw registers */
	1859	const UINT8 * regaccess; /* register access array */
	1860	const char const regnames; /* register names array */
	1861	UINT8 alt_regmap; /* enable alternate register map? */
	1862
	1863	pci_state pci; /* PCI state */
	1864	dac_state dac; /* DAC state */
	1865
	1866	fbi_state fbi; /* FBI states */
	1867	tmu_state tmu[MAX_TMU]; /* TMU states */
	1868	tmu_shared_state tmushare; /* TMU shared state */
	1869	banshee_info banshee; /* Banshee state */
	1870
	1871	legacy_poly_manager * poly; /* polygon manager */
	1872	stats_block * thread_stats; /* per-thread statistics */
	1873
	1874	voodoo_stats stats; /* internal statistics */
	1875
	1876	offs_t last_status_pc; /* PC of last status description (for logging) */
	1877	UINT32 last_status_value; /* value of last status read (for logging) */
	1878
	1879	int next_rasterizer; /* next rasterizer index */
	1880	raster_info rasterizer[MAX_RASTERIZERS]; /* array of rasterizers */
	1881	raster_info * raster_hash[RASTER_HASH_SIZE]; /* hash table of rasterizers */
	1882
	1883	bool send_config;
	1884	UINT32 tmu_config;
	1885
108	1886	};
109	1887
110	1888	class voodoo_1_device : public voodoo_device

trunk/src/devices/video/voodoo_pci.cpp
r253153	r253154
153	153
154	154	UINT32 voodoo_pci_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
155	155	{
156		return voodoo_update(~~m_voodoo,~~ bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
	156	return m_voodoo->voodoo_update(bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
157	157	}
158	158
159	159	// PCI bus control
r253153	r253154
170	170	switch (offset) {
171	171	case 0x0/4: // The address map starts at 0x40
172	172	// HW initEnable
173		voodoo_set_init_enable(~~m_voodoo,~~ data);
	173	m_voodoo->voodoo_set_init_enable(data);
174	174	logerror("%06X:voodoo_pci_device pcictrl_w to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
175	175	break;
176	176	default:

trunk/src/emu/emuopts.cpp
r253153	r253154
262	262	{
263	263	std::string featurename = std::string(name).append("_default");
264	264	const char *value = swpart->feature(featurename.c_str());
265		if (value != nullptr)
	265	if (value != nullptr && (*value == '\0' \|\| slot->option(value) != nullptr))
266	266	set_default_value(name, value);
267	267	}
268	268	}

trunk/src/mame/arcade.lst
r253153	r253154
5143	5143	vmahjong // 1997.02 Virtual Mahjong (Micronet)
5144	5144	pclub2kc // 1997.02 Print Club Kome Kome Club
5145	5145	pclub2fc // 1997.04 Print Club 2 Felix The Cat
	5146	pclub2pe //
	5147	pclub2pf //
	5148	pclub26w //
	5149	pclub27s //
	5150	pclubyo2 //
5146	5151	groovef // 1997.05 Groove on Fight (Atlus)
5147	5152	nclubv3 // 1997.07 Name Club Ver. 3
	5153	nclubv2 //
	5154	nameclub //
5148	5155	pclb2elk // 1997.07 Print Club Custom
5149	5156	pclub2 // 1997.09 Print Club 2
5150	5157	thunt // 1997.09 Puzzle & Action Treasure Hunt (Sega (Deniam License))
r253153	r253154
5152	5159	winterht // 1997.10 Winter Heat (Data East)
5153	5160	pclb297w // 1997.10 Print Club 2 '97 Winter Ver
5154	5161	pclub298 // 1997.10 Print Club 2 '98 Spring Ver
	5162	pclove
5155	5163	cotton2 // 1997.11 Cotton 2 (Success)
5156	5164	hanagumi // 1997.11 Sakura Taisen Hanagumi Taisen Columns
5157	5165	findlove // 1997.12 Find Love (Daiki / FCF)
r253153	r253154
9270	9278	bonkadv // (c) 1994 Kaneko
9271	9279	gtmr // (c) 1994 Kaneko
9272	9280	gtmra // (c) 1994 Kaneko
	9281	gtmrb // (c) 1994 Kaneko
9273	9282	gtmro // (c) 1994 Kaneko
9274	9283	gtmre // (c) 1994 Kaneko
9275	9284	gtmrusa // (c) 1994 Kaneko (US)
r253153	r253154
9852	9861
9853	9862	// ESD games
9854	9863	// http://www.esdgame.co.kr/english/
9855		multchmp // (c) 1998 (World)
	9864	multchmp // (c) 1999 (World)
9856	9865	multchmpk // (c) 1998 (Korea)
	9866	multchmpa // (c) 1998 (World)
9857	9867	mchampdx // (c) 1999 ESD
9858	9868	mchampdxa // (c) 1999 ESD
9859	9869	mchampdxb // (c) 1999 ESD
r253153	r253154
10859	10869	dorachan // (c) 1980 Craul Denshi
10860	10870	ladyfrog // (c) 1990 Mondial Games
10861	10871	toucheme
	10872	touchemea
10862	10873	rabbit // (c) 1997 Electronic Arts
10863	10874	tmmjprd // (c) 1997 Media / Sonnet
10864	10875	tmpdoki // (c) 1998 Media Syouji

trunk/src/mame/drivers/arkanoid.cpp
r253153	r253154
1245	1245
1246	1246	void arkanoid_state::machine_start()
1247	1247	{
	1248	// allocate the MCU timer, even if we have no MCU, and set it to fire NEVER.
	1249	m_68705_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(arkanoid_state::timer_68705_increment),this));
	1250	m_68705_timer->adjust(attotime::never);
	1251
1248	1252	save_item(NAME(m_gfxbank));
1249	1253	save_item(NAME(m_palettebank));
1250	1254
r253153	r253154
1284	1288	m_z80HasWritten = 0;
1285	1289	m_68705HasWritten = 0;
1286	1290	if (m_mcu.found()) m_mcu->set_input_line(M68705_IRQ_LINE, CLEAR_LINE);
	1291	if (m_mcu.found()) m_68705_timer->adjust(attotime::from_hz(((XTAL_12MHz/4)/4)/(1<<7)));
1287	1292
1288	1293	m_port_a_in = 0;
1289	1294	m_port_a_out = 0;

trunk/src/mame/drivers/esd16.cpp
r253153	r253154
826	826	ROM_LOAD( "esd4.su10", 0x00000, 0x20000, CRC(6e741fcd) SHA1(742e0952916c00f67dd9f8d01e721a9a538d2fc4) )
827	827	ROM_END
828	828
	829	ROM_START( multchmpa )
	830	ROM_REGION( 0x080000, "maincpu", 0 ) /* 68000 Code */
	831	ROM_LOAD16_BYTE( "esd2.cu02", 0x000000, 0x040000, CRC(bfd39198) SHA1(11c0cb7a865daa1be9301ddfa5f5d2014e8f9908) )
	832	ROM_LOAD16_BYTE( "esd1.cu03", 0x000001, 0x040000, CRC(cd769077) SHA1(741cca679393dab031691834874c96fee791241e) )
	833
	834	ROM_REGION( 0x40000, "audiocpu", 0 ) /* Z80 Code */
	835	ROM_LOAD( "esd3.su01", 0x00000, 0x20000, CRC(7c178bd7) SHA1(8754d3c70d9b2bf369a5ce0cce4cc0696ed22750) )
	836
	837	ROM_REGION( 0x180000, "spr", 0 ) /* Sprites, 16x16x5 */
	838	ROM_LOAD16_BYTE( "esd17.ju06", 0x000000, 0x040000, CRC(51f01067) SHA1(d5ebbc7d358b63724d2f24da8b2ce4a202be37a5) )
	839	ROM_LOAD16_BYTE( "esd16.ju05", 0x000001, 0x040000, CRC(88e252e8) SHA1(07d898379798c6be42b636762b0af61b9111a480) )
	840	ROM_LOAD16_BYTE( "esd15.ju04", 0x080000, 0x040000, CRC(b1ae7f08) SHA1(37dd9d4cef8b9e1d09d7b46a9794fb2b777c9a01) )
	841	ROM_LOAD16_BYTE( "esd14.ju03", 0x080001, 0x040000, CRC(d8f06fa8) SHA1(f76912f93f99578529612a7f01d82ac7229a8e41) )
	842	ROM_LOAD16_BYTE( "esd13.ju07", 0x100000, 0x040000, CRC(9d1590a6) SHA1(35f634dbf0df06ec62359c7bae43c7f5d14b0ab2) )
	843
	844	ROM_REGION( 0x400000, "bgs", 0 ) /* Layers, 16x16x8 */
	845	ROM_LOAD32_BYTE( "esd9.fu28", 0x000000, 0x080000, CRC(a3cfe895) SHA1(a8dc0d5d9e64d4c5112177b8f20b5bdb86ca73af) )
	846	ROM_LOAD32_BYTE( "esd11.fu29", 0x000001, 0x080000, CRC(d3c1855e) SHA1(bb547d4a45a745e9ae4a6727087cdf325105de90) )
	847	ROM_LOAD32_BYTE( "esd7.fu26", 0x000002, 0x080000, CRC(042d59ff) SHA1(8e45a4757e07d8aaf50b151d8849c1a27424e64b) )
	848	ROM_LOAD32_BYTE( "esd5.fu27", 0x000003, 0x080000, CRC(ed5b4e58) SHA1(82c3ee9e2525c0b370a29d5560c21ec6380d1a43) )
	849	ROM_LOAD32_BYTE( "esd10.fu31", 0x200000, 0x080000, CRC(396d77b6) SHA1(f22449a7f9f50e172e36db4f399c14e527409884) )
	850	ROM_LOAD32_BYTE( "esd12.fu33", 0x200001, 0x080000, CRC(a68848a8) SHA1(915239a961d76af6a1a567eb89b1569f158e714e) )
	851	ROM_LOAD32_BYTE( "esd8.fu30", 0x200002, 0x080000, CRC(fa8cd2d3) SHA1(ddc1b98867e6d2eee458bf35a933e7cdc59f4c7e) )
	852	ROM_LOAD32_BYTE( "esd6.fu32", 0x200003, 0x080000, CRC(97fde7b1) SHA1(b3610f6fcc1367ff079dc01121c86bc1e1f4c7a2) )
	853
	854	ROM_REGION( 0x40000, "oki", 0 ) /* Samples */
	855	ROM_LOAD( "esd4.su08", 0x00000, 0x20000, CRC(6e741fcd) SHA1(742e0952916c00f67dd9f8d01e721a9a538d2fc4) )
	856	ROM_END
	857
	858
	859
829	860	/*
830	861
831	862	Multi Champ Deluxe
r253153	r253154
1530	1561
1531	1562	/* ESD 11-09-98 */
1532	1563	GAME( 1999, multchmp, 0, esd16, multchmp, driver_device, 0, ROT0, "ESD", "Multi Champ (World, ver. 2.5)", MACHINE_SUPPORTS_SAVE )
1533		GAME( 1998, multchmpk,multchmp, esd16, multchmp, driver_device, 0, ROT0, "ESD", "Multi Champ (Korea)", MACHINE_SUPPORTS_SAVE )
	1564	GAME( 1998, multchmpk,multchmp, esd16, multchmp, driver_device, 0, ROT0, "ESD", "Multi Champ (Korea, older)", MACHINE_SUPPORTS_SAVE )
	1565	GAME( 1998, multchmpa,multchmp, esd16, multchmp, driver_device, 0, ROT0, "ESD", "Multi Champ (World, older)", MACHINE_SUPPORTS_SAVE )
	1566
1534	1567	GAME( 2001, jumppop, 0, jumppop, jumppop, driver_device, 0, ROT0, "ESD", "Jumping Pop (set 1)", MACHINE_SUPPORTS_SAVE ) /* Redesigned(?) ESD 11-09-98 with no ID# */
1535	1568	GAME( 2001, jumppope, jumppop, jumppop, jumppop, driver_device, 0, ROT0, "Emag Soft", "Jumping Pop (set 2)", MACHINE_SUPPORTS_SAVE )
1536	1569

trunk/src/mame/drivers/fidelz80.cpp
r253153	r253154
1537	1537	Machine Drivers
1538	1538	******************************************************************************/
1539	1539
	1540	static MACHINE_CONFIG_START( cc7, fidelz80_state )
	1541
	1542	/* basic machine hardware */
	1543	MCFG_CPU_ADD("maincpu", Z80, XTAL_3_579545MHz)
	1544	MCFG_CPU_PROGRAM_MAP(cc10_map)
	1545	//MCFG_CPU_IO_MAP(vcc_io)
	1546
	1547	MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", fidelz80base_state, display_decay_tick, attotime::from_msec(1))
	1548	MCFG_DEFAULT_LAYOUT(layout_fidel_cc)
	1549
	1550	/* sound hardware */
	1551	MCFG_SPEAKER_STANDARD_MONO("mono")
	1552	MCFG_SOUND_ADD("beeper", BEEP, 0)
	1553	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
	1554	MACHINE_CONFIG_END
	1555
1540	1556	static MACHINE_CONFIG_START( cc10, fidelz80_state )
1541	1557
1542	1558	/* basic machine hardware */
r253153	r253154
1641	1657	ROM Definitions
1642	1658	******************************************************************************/
1643	1659
	1660	ROM_START( cc7 )
	1661	ROM_REGION( 0x10000, "maincpu", 0 )
	1662	ROM_LOAD( "cn19103n_bcc-revb", 0x0000, 0x1000, CRC(a397d471) SHA1(9b12bc442fccee40f4d8500c792bc9d886c5e1a5) ) // 2332
	1663	ROM_END
	1664
1644	1665	ROM_START( cc10 )
1645	1666	ROM_REGION( 0x10000, "maincpu", 0 )
1646	1667	ROM_LOAD( "cc10b", 0x0000, 0x1000, CRC(afd3ca99) SHA1(870d09b2b52ccb8572d69642c59b5215d5fb26ab) ) // 2332
r253153	r253154
1804	1825	******************************************************************************/
1805	1826
1806	1827	/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY, FULLNAME, FLAGS */
1807		COMP( 1978, cc10, 0, 0, cc10, cc10, driver_device, 0, "Fidelity Electronics", "Chess Challenger 10 (version B)", MACHINE_SUPPORTS_SAVE )
	1828	COMP( 1978, cc10, 0, 0, cc10, cc10, driver_device, 0, "Fidelity Electronics", "Chess Challenger 10 (rev. B)", MACHINE_SUPPORTS_SAVE )
	1829	COMP( 1979, cc7, 0, 0, cc7, cc10, driver_device, 0, "Fidelity Electronics", "Chess Challenger 7 (rev. B)", MACHINE_SUPPORTS_SAVE \| MACHINE_NOT_WORKING )
1808	1830
1809	1831	COMP( 1979, vcc, 0, 0, vcc, vcc, driver_device, 0, "Fidelity Electronics", "Voice Chess Challenger (English)", MACHINE_SUPPORTS_SAVE )
1810	1832	COMP( 1979, vccsp, vcc, 0, vcc, vccsp, driver_device, 0, "Fidelity Electronics", "Voice Chess Challenger (Spanish)", MACHINE_SUPPORTS_SAVE )

trunk/src/mame/drivers/funkball.cpp
r253153	r253154
142	142
143	143	UINT32 funkball_state::screen_update( screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect )
144	144	{
145		return voodoo_update(~~m_voodoo,~~ bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
	145	return m_voodoo->voodoo_update(bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
146	146	}
147	147
148	148	static UINT32 voodoo_0_pci_r(device_t busdevice, device_t device, int function, int reg, UINT32 mem_mask)
r253153	r253154
186	186	break;
187	187	case 0x40:
188	188	state->m_voodoo_pci_regs.init_enable = data;
189		voodoo_set_init_enable(~~state->m_voodoo,~~ data);
	189	state->m_voodoo->voodoo_set_init_enable(data);
190	190	break;
191	191	}
192	192	}

trunk/src/mame/drivers/gticlub.cpp
r253153	r253154
910	910
911	911	if (strcmp(screen.tag(), ":lscreen") == 0)
912	912	{
913		device_t *voodoo = machine().device("voodoo0");
	913	voodoo_device voodoo = (voodoo_device)machine().device("voodoo0");
914	914
915	915	// m_k001604_1->draw_back_layer(bitmap, cliprect);
916	916
917		voodoo_update(~~voodoo,~~ bitmap, cliprect);
	917	voodoo->voodoo_update(bitmap, cliprect);
918	918
919	919	m_k001604_1->draw_front_layer(screen, bitmap, cliprect);
920	920	}
921	921	else if (strcmp(screen.tag(), ":rscreen") == 0)
922	922	{
923		device_t *voodoo = machine().device("voodoo1");
	923	voodoo_device voodoo = (voodoo_device)machine().device("voodoo1");
924	924
925	925	// m_k001604_2->draw_back_layer(bitmap, cliprect);
926	926
927		voodoo_update(~~voodoo,~~ bitmap, cliprect);
	927	voodoo->voodoo_update(bitmap, cliprect);
928	928
929	929	m_k001604_2->draw_front_layer(screen, bitmap, cliprect);
930	930	}

trunk/src/mame/drivers/hornet.cpp
r253153	r253154
478	478
479	479	UINT32 hornet_state::screen_update_hornet(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
480	480	{
481		device_t *voodoo = machine().device("voodoo0");
	481	voodoo_device* voodoo = (voodoo_device*)machine().device("voodoo0");
482	482
483		voodoo_update(~~voodoo,~~ bitmap, cliprect);
	483	voodoo->voodoo_update(bitmap, cliprect);
484	484
485	485	m_k037122_1->tile_draw(screen, bitmap, cliprect);
486	486
r253153	r253154
493	493	{
494	494	if (strcmp(screen.tag(), ":lscreen") == 0)
495	495	{
496		device_t *voodoo = machine().device("voodoo0");
497		voodoo_update(voodoo, bitmap, cliprect);
	496	voodoo_device voodoo = (voodoo_device)machine().device("voodoo0");
	497	voodoo->voodoo_update(bitmap, cliprect);
498	498
499	499	/* TODO: tilemaps per screen */
500	500	m_k037122_1->tile_draw(screen, bitmap, cliprect);
501	501	}
502	502	else if (strcmp(screen.tag(), ":rscreen") == 0)
503	503	{
504		device_t *voodoo = machine().device("voodoo1");
505		voodoo_update(voodoo, bitmap, cliprect);
	504	voodoo_device voodoo = (voodoo_device)machine().device("voodoo1");
	505	voodoo->voodoo_update(bitmap, cliprect);
506	506
507	507	/* TODO: tilemaps per screen */
508	508	m_k037122_2->tile_draw(screen, bitmap, cliprect);

trunk/src/mame/drivers/kaneko16.cpp
r253153	r253154
3342	3342	/* Not present on this board */
3343	3343	ROM_END
3344	3344
	3345	ROM_START( gtmrb )
	3346	ROM_REGION( 0x100000, "maincpu", 0 ) /* 68000 Code */
	3347	ROM_LOAD16_BYTE( "mmp0x1.u514", 0x000000, 0x080000, CRC(6c163f12) SHA1(7f33d1475dcb754c83f68b5fb686fb236ba81256) )
	3348	ROM_LOAD16_BYTE( "mmp1x1.u513", 0x000001, 0x080000, CRC(424dc7e1) SHA1(a9cb8d1fd0549c8c77462552c649c180c30eef89) )
3345	3349
	3350	ROM_REGION( 0x020000, "mcudata", 0 ) /* MCU Code */
	3351	ROM_LOAD16_WORD_SWAP( "mmd0x1.u124", 0x000000, 0x020000, CRC(3d7cb329) SHA1(053106acde642a414fde0b01105fe6762b6a10f6) ) // == mmd0x2
	3352
	3353	ROM_REGION( 0x840000, "gfx1", 0 ) /* Sprites */
	3354	ROM_LOAD( "mm-200-402-s0.bin", 0x000000, 0x200000, CRC(c0ab3efc) SHA1(e6cd15480977b036234d91e6f3a6e21b7f0a3c3e) )
	3355	ROM_LOAD( "mm-201-403-s1.bin", 0x200000, 0x200000, CRC(cf6b23dc) SHA1(ccfd0b17507e091e55c169361cd6a6b19641b717) )
	3356	ROM_LOAD( "mm-202-404-s2.bin", 0x400000, 0x200000, CRC(8f27f5d3) SHA1(219a86446ce2556682009d8aff837480f040a01e) )
	3357	ROM_LOAD( "mm-203-405-s3.bin", 0x600000, 0x080000, CRC(e9747c8c) SHA1(2507102ec34755c6f110eadb3444e6d3a3474051) )
	3358	ROM_LOAD16_BYTE( "mms1x1.u30", 0x800001, 0x020000, CRC(9463825c) SHA1(696bbfc816b564b3cff1487e1b848d375951f923) )
	3359	ROM_LOAD16_BYTE( "mms0x1.u29", 0x800000, 0x020000, CRC(bd22b7d2) SHA1(ef82d00d72439590c71aed33ecfabc6ee71a6ff9) ) // == mms0x2
	3360
	3361	ROM_REGION( 0x200000, "gfx2", 0 ) /* Tiles (scrambled) */
	3362	ROM_LOAD( "mm-300-406-a0.bin", 0x000000, 0x200000, CRC(b15f6b7f) SHA1(5e84919d788add53fc87f4d85f437df413b1dbc5) )
	3363
	3364	ROM_REGION( 0x200000, "gfx3", 0 ) /* Tiles (scrambled) */
	3365	ROM_COPY("gfx2",0x000000,0,0x200000) // it isn't on the board twice.
	3366
	3367	ROM_REGION( 0x400000, "oki1", 0 ) /* Samples, plus room for expansion */
	3368	ROM_LOAD( "mm-100-401-e0.bin", 0x000000, 0x100000, CRC(b9cbfbee) SHA1(051d48a68477ef9c29bd5cc0bb7955d513a0ab94) ) // 16 x $10000
	3369
	3370	ROM_REGION( 0x100000, "oki2", ROMREGION_ERASE00 ) /* Samples */
	3371	/* Not present on this board */
	3372	ROM_END
	3373
	3374
3346	3375	ROM_START( gtmro )
3347	3376	ROM_REGION( 0x100000, "maincpu", 0 ) /* 68000 Code */
3348	3377	ROM_LOAD16_BYTE( "u514.bin", 0x000000, 0x080000, CRC(2e857685) SHA1(43b6d88df51a3b4fb0cb910f63a5ec26b06e216a) )
r253153	r253154
4380	4409	GAME( 1994, bonkadv, 0, bonkadv , bonkadv, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "B.C. Kid / Bonk's Adventure / Kyukyoku!! PC Genjin", MACHINE_SUPPORTS_SAVE )
4381	4410	GAME( 1994, bloodwar, 0, bloodwar, bloodwar, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "Blood Warrior", MACHINE_SUPPORTS_SAVE )
4382	4411	GAME( 1994, oedfight, bloodwar, bloodwar, bloodwar, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "Oedo Fight (Japan Bloodshed Ver.)", MACHINE_SUPPORTS_SAVE )
4383		GAME( 1994, gtmr, 0, gtmr, gtmr, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "1000 Miglia: Great 1000 Miles Rally (94/07/18)", MACHINE_SUPPORTS_SAVE )
	4412	GAME( 1994, gtmr, 0, gtmr, gtmr, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "1000 Miglia: Great 1000 Miles Rally (94/07/18)", MACHINE_SUPPORTS_SAVE ) // this set shows 'PCB by Jinwei Co Ltd. ROC'
4384	4413	GAME( 1994, gtmra, gtmr, gtmr, gtmr, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "1000 Miglia: Great 1000 Miles Rally (94/06/13)", MACHINE_SUPPORTS_SAVE )
	4414	GAME( 1994, gtmrb, gtmr, gtmr, gtmr, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "1000 Miglia: Great 1000 Miles Rally (94/05/26)", MACHINE_SUPPORTS_SAVE )
4385	4415	GAME( 1994, gtmro, gtmr, gtmr, gtmr, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "1000 Miglia: Great 1000 Miles Rally (94/05/10)", MACHINE_SUPPORTS_SAVE ) // possible prototype
4386	4416	GAME( 1994, gtmre, gtmr, gtmre, gtmr, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "Great 1000 Miles Rally: Evolution Model!!! (94/09/06)", MACHINE_SUPPORTS_SAVE )
4387	4417	GAME( 1994, gtmrusa, gtmr, gtmre, gtmr, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "Great 1000 Miles Rally: U.S.A Version! (94/09/06)", MACHINE_SUPPORTS_SAVE ) // U.S.A version seems part of the title, rather than region

trunk/src/mame/drivers/ladyfrog.cpp
r253153	r253154
365	365	ROM_LOAD( "8.ic10", 0x20000, 0x10000, CRC(fc6808bf) SHA1(f1f1b75a79dfdb500012f9b52c6364f0a13dce2d) )
366	366	ROM_END
367	367
	368	ROM_START( touchemea )
	369	ROM_REGION( 0x10000, "maincpu", 0 )
	370	ROM_LOAD( "2.ic107", 0x0000, 0x10000, CRC(4e72312d) SHA1(a7d178608f05c87a53c650298b903bcf34b3b755) ) // sldh
	371
	372	ROM_REGION( 0x10000, "audiocpu", 0 )
	373	ROM_LOAD( "1.ic115", 0x0000, 0x8000, CRC(902589aa) SHA1(d60088fc31a67fec91f908f671af77bb87a5e59c) )
	374
	375	ROM_REGION( 0x60000, "gfx1", ROMREGION_INVERT )
	376	ROM_LOAD( "3.ic32", 0x30000, 0x10000, CRC(223b4435) SHA1(fb5a4096012093bae5fda213a5de317e63a88ec3) )
	377	ROM_LOAD( "4.ic33", 0x40000, 0x10000, CRC(96dcc2f3) SHA1(9c61f8161771e40ca41b6e102bc04583dc97cd0d) )
	378	ROM_LOAD( "5.ic34", 0x50000, 0x10000, CRC(b8667a6b) SHA1(288a5cbd8fc01b24822e89fbc1e6d7f45c181483) )
	379	ROM_LOAD( "6.ic8", 0x00000, 0x10000, CRC(d257382f) SHA1(9c459b90c9ddfe90de4a252f29a7bee809412b46) )
	380	ROM_LOAD( "7.ic9", 0x10000, 0x10000, CRC(feb1b974) SHA1(ffd4527472cdf655fbebebf4d3abb61962e54457) )
	381	ROM_LOAD( "8.ic10", 0x20000, 0x10000, CRC(fc6808bf) SHA1(f1f1b75a79dfdb500012f9b52c6364f0a13dce2d) )
	382	ROM_END
	383
368	384	GAME( 1990, ladyfrog, 0, ladyfrog, ladyfrog, driver_device, 0, ORIENTATION_SWAP_XY, "Mondial Games", "Lady Frog", MACHINE_SUPPORTS_SAVE )
369	385
370	386	// toucheme art style is similar to ladyfrog, so it's probably the same manufacturer
371		GAME( 19??, toucheme, 0, toucheme, toucheme, driver_device, 0, ORIENTATION_SWAP_XY, "<unknown>", "Touche Me", MACHINE_SUPPORTS_SAVE )
	387	GAME( 19??, toucheme, 0, toucheme, toucheme, driver_device, 0, ORIENTATION_SWAP_XY, "<unknown>", "Touche Me (set 1)", MACHINE_SUPPORTS_SAVE )
	388	GAME( 19??, touchemea,toucheme, toucheme, toucheme, driver_device, 0, ORIENTATION_SWAP_XY, "<unknown>", "Touche Me (set 2, harder)", MACHINE_SUPPORTS_SAVE )

trunk/src/mame/drivers/magictg.cpp
r253153	r253154
180	180
181	181
182	182	/* 3Dfx Voodoo */
183		device_t* m_voodoo[2];
	183	voodoo_device* m_voodoo[2];
184	184
185	185	struct
186	186	{
r253153	r253154
241	241
242	242	void magictg_state::machine_start()
243	243	{
244		m_voodoo[0] = machine().device("voodoo_0");
245		m_voodoo[1] = machine().device("voodoo_1");
	244	m_voodoo[0] = (voodoo_device*)machine().device("voodoo_0");
	245	m_voodoo[1] = (voodoo_device*)machine().device("voodoo_1");
246	246	}
247	247
248	248
r253153	r253154
278	278
279	279	UINT32 magictg_state::screen_update_magictg(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
280	280	{
281		return voodoo_update(~~m_voodoo[0],~~ bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
	281	return m_voodoo[0]->voodoo_update(bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
282	282	}
283	283
284	284
r253153	r253154
338	338	break;
339	339	case 0x40:
340	340	state->m_voodoo_pci_regs[0].init_enable = data;
341		voodoo_set_init_enable(~~state->m_voodoo[0],~~ data);
	341	state->m_voodoo[0]->voodoo_set_init_enable(data);
342	342	break;
343	343
344	344	default:
r253153	r253154
601	601	UINT32 dst_addr = m_dma_ch[ch].dst_addr;
602	602	//device_t *voodoo = dst_addr > 0xa000000 voodoo0 : voodoo1;
603	603
604		assert(DWORD_ALIGNED(src_addr));
605		assert(DWORD_ALIGNED(dst_addr));
	604	assert((src_addr & 3) == 0);
	605	assert((dst_addr & 3) == 0);
606	606
607	607	while (m_dma_ch[ch].count > 3)
608	608	{

trunk/src/mame/drivers/nibble.cpp
r253153	r253154
2	2	// copyright-holders:Roberto Fresca
3	3	/*************************************************************************
4	4
5		Unknown 'Nibble' game
6
7		Preliminary driver by Roberto Fresca.
	5	Lucky 9, Nibble.
8	6
	7	Driver by Roberto Fresca.
	8
	9	Seems some sort of gambling game with playing cards (no poker)
	10	and girls graphics...
	11
	12
9	13	**************************************************************************
10	14
11	15	Specs:
12	16
13		1x UM6845
14		1x AY38910A/p
	17	1x UM6845 (U67).
	18	1x AY38910A/p (U75).
15	19
16		3x HY6264P-12
17		2x IMSG171P-50G
	20	3x HY6264P-12 (U153, U154, U25).
	21	2x IMSG171P-50G (U32, U104).
18	22
19	23	2 Chips with no markings!
20	24
21		8x 64K Graphics ROMs.
22		1x 64K Program ROM.
23		1x 128K unknown ROM.
	25	8x 64K Graphics ROMs (U139, U141, U149, U147, U137, U143, U145, U152).
	26	1x 64K Program ROM (U123).
	27	1x 128K unknown ROM (U138).
24	28
	29	1x TI LF347N (U158) Operational Amplifier.
	30	1x LM380N (U82) 2.5W Audio Power Amplifier.
	31
25	32	2x XTAL - 11.98135 KDS9C
26	33	2x 8 DIP switches banks.
	34	1x 3.6V lithium battery.
27	35
28	36
29	37	**************************************************************************
r253153	r253154
31	39	Tech notes...
32	40
33	41	About the unknown ICs:
34		DIP64 CPU with Xtal tied to pins 30 % 31. --> TMS9900? (ROM 9)
35		DIP40 CPU or sound IC driving 128k (ROM 10) data? (pin 20 tied to GND)
	42	DIP64 (U101) CPU with Xtal tied to pins 30 % 31. --> TMS9900? (ROM 9)
	43	DIP40 (U64) CPU or sound IC driving 128k (ROM 10) data? (pin 20 tied to GND)
36	44
37	45
38	46	*************************************************************************/
39	47
	48
40	49	#define MASTER_CLOCK XTAL_12MHz
41	50
42	51	#include "emu.h"
	52	#include "cpu/tms9900/tms9980a.h"
	53	//#include "cpu/tms9900/tms9900.h"
43	54	#include "sound/ay8910.h"
44	55	#include "video/mc6845.h"
45	56
r253153	r253154
48	59	{
49	60	public:
50	61	nibble_state(const machine_config &mconfig, device_type type, const char *tag)
51		: driver_device(mconfig, type, tag)
52		// ,m_maincpu(*this, "maincpu")
53		{ }
	62	: driver_device(mconfig, type, tag),
	63	m_videoram(*this, "videoram"),
	64	m_maincpu(*this, "maincpu"),
	65	m_gfxdecode(*this, "gfxdecode") { }
54	66
	67	required_shared_ptr<UINT8> m_videoram;
	68	tilemap_t *m_bg_tilemap;
	69	DECLARE_WRITE8_MEMBER(nibble_videoram_w);
	70	TILE_GET_INFO_MEMBER(get_bg_tile_info);
	71
55	72	virtual void machine_start() override;
56	73	virtual void machine_reset() override;
	74	virtual void video_start() override;
	75	DECLARE_PALETTE_INIT(nibble);
	76	UINT32 screen_update_nibble(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	77	INTERRUPT_GEN_MEMBER(nibble_interrupt);
	78	required_device<cpu_device> m_maincpu;
	79	required_device<gfxdecode_device> m_gfxdecode;
	80	};
57	81
58		// required_device<cpu_device> m_maincpu;
59	82
60		};
	83	/*************************
	84	* Video Hardware *
	85	*************************/
61	86
62		static INPUT_PORTS_START( nibble )
63		INPUT_PORTS_END
	87	WRITE8_MEMBER(nibble_state::nibble_videoram_w)
	88	{
	89	m_videoram[offset] = data;
	90	m_bg_tilemap->mark_tile_dirty(offset);
	91	}
64	92
65	93
	94	TILE_GET_INFO_MEMBER(nibble_state::get_bg_tile_info)
	95	{
	96	/* - bits -
	97	7654 3210
	98	---- ---- bank select.
	99	---- ---- color code.
	100	---- ---- seems unused.
	101	*/
	102	int code = m_videoram[tile_index];
	103
	104	SET_TILE_INFO_MEMBER(0 /* bank /, code, 0 / color */, 0);
	105	}
	106
	107	void nibble_state::video_start()
	108	{
	109	m_bg_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(nibble_state::get_bg_tile_info),this), TILEMAP_SCAN_ROWS, 8, 8, 32, 32);
	110	}
	111
	112	UINT32 nibble_state::screen_update_nibble(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
	113	{
	114	m_bg_tilemap->draw(screen, bitmap, cliprect, 0, 0);
	115	return 0;
	116	}
	117
	118	PALETTE_INIT_MEMBER(nibble_state, nibble)
	119	{
	120	}
	121
	122
	123	/**************************
	124	* Read / Write Handlers *
	125	**************************/
	126
	127	INTERRUPT_GEN_MEMBER(nibble_state::nibble_interrupt)
	128	{
	129	}
	130
	131
	132	/************************
	133	* Start & Reset *
	134	************************/
	135
66	136	void nibble_state::machine_start()
67	137	{
68	138	}
69	139
	140
70	141	void nibble_state::machine_reset()
71	142	{
72	143	}
73	144
74	145
	146	/*************************
	147	* Memory Map Information *
	148	*************************/
	149
	150	static ADDRESS_MAP_START( nibble_map, AS_PROGRAM, 8, nibble_state )
	151	ADDRESS_MAP_GLOBAL_MASK(0x3fff)
	152	AM_RANGE(0x0000, 0xbfff) AM_ROM
	153	AM_RANGE(0xc000, 0xc3ff) AM_WRITE(nibble_videoram_w) AM_SHARE("videoram") // placeholder
	154	// AM_RANGE(0xff00, 0xff01) AM_DEVWRITE("crtc", mc6845_device, address_w)
	155	// AM_RANGE(0xff02, 0xff03) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
	156	ADDRESS_MAP_END
	157
	158
	159	static ADDRESS_MAP_START( nibble_cru_map, AS_IO, 8, nibble_state )
	160	ADDRESS_MAP_END
	161
	162
	163	/*************************
	164	* Input Ports *
	165	*************************/
	166
	167	static INPUT_PORTS_START( nibble )
	168	PORT_START("IN0")
	169	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_1) PORT_NAME("IN0-1")
	170	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_2) PORT_NAME("IN0-2")
	171	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_3) PORT_NAME("IN0-3")
	172	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_4) PORT_NAME("IN0-4")
	173	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_5) PORT_NAME("IN0-5")
	174	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_6) PORT_NAME("IN0-6")
	175	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_7) PORT_NAME("IN0-7")
	176	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_8) PORT_NAME("IN0-8")
	177
	178	PORT_START("IN1")
	179	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Q) PORT_NAME("IN1-1")
	180	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_W) PORT_NAME("IN1-2")
	181	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_E) PORT_NAME("IN1-3")
	182	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_R) PORT_NAME("IN1-4")
	183	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_T) PORT_NAME("IN1-5")
	184	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Y) PORT_NAME("IN1-6")
	185	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_U) PORT_NAME("IN1-7")
	186	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_I) PORT_NAME("IN1-8")
	187
	188	PORT_START("IN2")
	189	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_A) PORT_NAME("IN2-1")
	190	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_S) PORT_NAME("IN2-2")
	191	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_D) PORT_NAME("IN2-3")
	192	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_F) PORT_NAME("IN2-4")
	193	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_G) PORT_NAME("IN2-5")
	194	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_H) PORT_NAME("IN2-6")
	195	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_J) PORT_NAME("IN2-7")
	196	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_K) PORT_NAME("IN2-8")
	197
	198	PORT_START("IN3")
	199	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Z) PORT_NAME("IN3-1")
	200	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_X) PORT_NAME("IN3-2")
	201	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_C) PORT_NAME("IN3-3")
	202	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_V) PORT_NAME("IN3-4")
	203	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_B) PORT_NAME("IN3-5")
	204	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_N) PORT_NAME("IN3-6")
	205	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_M) PORT_NAME("IN3-7")
	206	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_L) PORT_NAME("IN3-8")
	207
	208	PORT_START("IN4")
	209	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_1_PAD) PORT_NAME("IN4-1")
	210	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_2_PAD) PORT_NAME("IN4-2")
	211	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_3_PAD) PORT_NAME("IN4-3")
	212	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_4_PAD) PORT_NAME("IN4-4")
	213	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_5_PAD) PORT_NAME("IN4-5")
	214	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("IN4-6")
	215	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("IN4-7")
	216	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("IN4-8")
	217
	218	PORT_START("DSW1")
	219	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
	220	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	221	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	222	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	223	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	224	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	225	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	226	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	227	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	228	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
	229	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	230	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	231	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	232	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	233	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	234	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	235	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	236	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	237	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	238	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	239	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	240	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	241	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	242	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	243
	244	PORT_START("DSW2")
	245	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
	246	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	247	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	248	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	249	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	250	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	251	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	252	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	253	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	254	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
	255	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	256	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	257	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	258	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	259	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	260	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	261	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	262	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	263	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	264	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	265	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	266	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	267	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	268	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	269
	270	INPUT_PORTS_END
	271
	272
	273	/*************************
	274	* Graphics Layouts *
	275	*************************/
	276
	277	static const gfx_layout charlayout =
	278	{
	279	8,8,
	280	RGN_FRAC(1,8),
	281	8,
	282	{ RGN_FRAC(0,8), RGN_FRAC(1,8), RGN_FRAC(2,8), RGN_FRAC(3,8), RGN_FRAC(4,8), RGN_FRAC(5,8), RGN_FRAC(6,8), RGN_FRAC(7,8) },
	283	{ 0, 1, 2, 3, 4, 5, 6, 7 },
	284	{ 08, 18, 28, 38, 48, 58, 68, 78 },
	285	8*8
	286	};
	287
	288
	289	/******************************
	290	* Graphics Decode Information *
	291	******************************/
	292
	293	static GFXDECODE_START( nibble )
	294	GFXDECODE_ENTRY( "gfx", 0, charlayout, 0, 16 )
	295	GFXDECODE_END
	296
	297
	298	/*************************
	299	* Machine Drivers *
	300	*************************/
	301
75	302	static MACHINE_CONFIG_START( nibble, nibble_state )
76	303
77		/* basic machine hardware */
78		// MCFG_CPU_ADD("maincpu", ??, 3000000) // unknown DIP64 CPU
79		// MCFG_CPU_PROGRAM_MAP(nibble_map)
80		// MCFG_CPU_IO_MAP(nibble_io)
81		// MCFG_CPU_VBLANK_INT_DRIVER("screen", nibble_state, irq0_line_hold)
	304	// CPU should be switched to TMS9900
	305	MCFG_TMS99xx_ADD("maincpu", TMS9980A, MASTER_CLOCK/4, nibble_map, nibble_cru_map)
	306	MCFG_CPU_VBLANK_INT_DRIVER("screen", nibble_state, nibble_interrupt)
82	307
83		/* sound hardware */
84		// MCFG_SPEAKER_STANDARD_MONO("mono")
	308	/* video hardware */
	309	MCFG_SCREEN_ADD("screen", RASTER)
	310	MCFG_SCREEN_REFRESH_RATE(60)
	311	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
	312	MCFG_SCREEN_SIZE(328, 328)
	313	MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 08, 328-1)
	314	MCFG_SCREEN_UPDATE_DRIVER(nibble_state, screen_update_nibble)
	315	MCFG_SCREEN_PALETTE("palette")
85	316
86		// MCFG_SOUND_ADD("aysnd", AY8910, MASTER_CLOCK/8)
87		// MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
	317	MCFG_GFXDECODE_ADD("gfxdecode", "palette", nibble)
	318
	319	MCFG_PALETTE_ADD("palette", 256)
	320	MCFG_PALETTE_INIT_OWNER(nibble_state, nibble)
	321
	322	MCFG_MC6845_ADD("crtc", MC6845, "screen", MASTER_CLOCK/8) /* guess */
	323	MCFG_MC6845_SHOW_BORDER_AREA(false)
	324	MCFG_MC6845_CHAR_WIDTH(8)
	325
88	326	MACHINE_CONFIG_END
89	327
90	328
	329	/*************************
	330	* Rom Load *
	331	*************************/
	332
91	333	ROM_START( l9nibble )
92	334	ROM_REGION( 0x10000, "maincpu", 0 )
93		ROM_LOAD( "09.U123", 0x00000, 0x10000, CRC(dfef685d) SHA1(0aeb4257e408e8549df629a0cdb5f2b6790e32de) ) // ~~unkn~~own
	335	ROM_LOAD( "09.U123", 0x00000, 0x10000, CRC(dfef685d) SHA1(0aeb4257e408e8549df629a0cdb5f2b6790e32de) ) // tms9900 code?
94	336
95		ROM_REGION( 0x80000, "oki", 0 )
96		ROM_LOAD( "01.U139", 0x00000, 0x10000, CRC(aba06e58) SHA1(5841beec122613eed2ba9f48cb1d51bfa0ff450c) )
97		ROM_LOAD( "02.U141", 0x00000, 0x10000, CRC(a1e5d6d1) SHA1(8ec85b0544dd75bcb13600bae503ad2b20978281) )
98		ROM_LOAD( "03.U149", 0x00000, 0x10000, CRC(ae66f77c) SHA1(6c9e98cc00b72252cb238f14686c0faef47134df) )
99		ROM_LOAD( "04.U147", 0x00000, 0x10000, CRC(f1864094) SHA1(b439f9e8c2cc4575f9edbda45b9e724257015a73) )
100		ROM_LOAD( "05.U137", 0x00000, 0x10000, CRC(2e8ae9de) SHA1(5f2831f71b351e34df82af37041c9aa815eb372c) )
101		ROM_LOAD( "06.U143", 0x00000, 0x10000, CRC(8a56f324) SHA1(68790a12ca57c999bd7b7f26adc206aab3c06976) )
102		ROM_LOAD( "07.U145", 0x00000, 0x10000, CRC(4f757912) SHA1(63e5fc2672552463060680b7a5a94df45f3d4b68) )
103		ROM_LOAD( "08.U152", 0x00000, 0x10000, CRC(4f878ee4) SHA1(215f3ead0c358cc09c21515981cbb0a1e58c2ca6) )
	337	ROM_REGION( 0x80000, "gfx", 0 )
	338	ROM_LOAD( "01.u139", 0x00000, 0x10000, CRC(aba06e58) SHA1(5841beec122613eed2ba9f48cb1d51bfa0ff450c) )
	339	ROM_LOAD( "02.u141", 0x10000, 0x10000, CRC(a1e5d6d1) SHA1(8ec85b0544dd75bcb13600bae503ad2b20978281) )
	340	ROM_LOAD( "03.u149", 0x20000, 0x10000, CRC(ae66f77c) SHA1(6c9e98cc00b72252cb238f14686c0faef47134df) )
	341	ROM_LOAD( "04.u147", 0x30000, 0x10000, CRC(f1864094) SHA1(b439f9e8c2cc4575f9edbda45b9e724257015a73) )
	342	ROM_LOAD( "05.u137", 0x40000, 0x10000, CRC(2e8ae9de) SHA1(5f2831f71b351e34df82af37041c9aa815eb372c) )
	343	ROM_LOAD( "06.u143", 0x50000, 0x10000, CRC(8a56f324) SHA1(68790a12ca57c999bd7b7f26adc206aab3c06976) )
	344	ROM_LOAD( "07.u145", 0x60000, 0x10000, CRC(4f757912) SHA1(63e5fc2672552463060680b7a5a94df45f3d4b68) )
	345	ROM_LOAD( "08.u152", 0x70000, 0x10000, CRC(4f878ee4) SHA1(215f3ead0c358cc09c21515981cbb0a1e58c2ca6) )
104	346
105	347	ROM_REGION( 0x20000, "user", 0 )
106		ROM_LOAD( "10.U138", 0x00000, 0x20000, CRC(ed831d2a) SHA1(ce5c3b24979d220215d7f0e8d50f45550aec15bd) )
	348	ROM_LOAD( "10.u138", 0x00000, 0x20000, CRC(ed831d2a) SHA1(ce5c3b24979d220215d7f0e8d50f45550aec15bd) ) // unknown data...
107	349
	350	ROM_REGION( 0x0400, "plds", 0 )
	351	ROM_LOAD( "pal16l8acn.u23", 0x0000, 0x0104, NO_DUMP )
	352	ROM_LOAD( "pal16l8acn.uxx", 0x0200, 0x0104, NO_DUMP )
	353
108	354	ROM_END
109	355
110	356
111		/* YEAR NAME PARENT MACHINE INPUT STATE INIT ROT COMPANY FULLNAME FLAGS... */
112		GAME( 19??, l9nibble, 0, nibble, nibble, driver_device, 0, ROT0, "Nibble?", "Unknown Nibble game", MACHINE_IS_SKELETON )
	357	/*************************
	358	* Game Drivers *
	359	*************************/
	360
	361	/* YEAR NAME PARENT MACHINE INPUT STATE INIT ROT COMPANY FULLNAME FLAGS... */
	362	GAME( 19??, l9nibble, 0, nibble, nibble, driver_device, 0, ROT0, "Nibble", "Lucky 9", MACHINE_NO_SOUND \| MACHINE_NOT_WORKING )

trunk/src/mame/drivers/nwk-tr.cpp
r253153	r253154
304	304	int m_fpga_uploaded;
305	305	int m_lanc2_ram_r;
306	306	int m_lanc2_ram_w;
	307	UINT8 m_lanc2_reg[3];
307	308	std::unique_ptr<UINT8[]> m_lanc2_ram;
308	309	std::unique_ptr<UINT32[]> m_sharc_dataram;
309	310	DECLARE_WRITE32_MEMBER(paletteram32_w);
r253153	r253154
346	347
347	348	UINT32 nwktr_state::screen_update_nwktr(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
348	349	{
349		device_t *voodoo = machine().device("voodoo0");
	350	voodoo_device voodoo = (voodoo_device)machine().device("voodoo0");
350	351
351	352	bitmap.fill(m_palette->pen(0), cliprect);
352	353
353		voodoo_update(~~voodoo,~~ bitmap, cliprect);
	354	voodoo->voodoo_update(bitmap, cliprect);
354	355
355	356	const rectangle &visarea = screen.visible_area();
356	357	const rectangle tilemap_rect(visarea.min_x, visarea.max_x, visarea.min_y+16, visarea.max_y);
r253153	r253154
521	522	((value << 7) & 0x80);
522	523
523	524	m_fpga_uploaded = 1;
	525	m_lanc2_reg[0] = (UINT8)(data >> 24);
524	526
525	527	//printf("lanc2_fpga_w: %02X at %08X\n", value, space.device().safe_pc());
526	528	}
r253153	r253154
528	530	{
529	531	m_lanc2_ram_r = 0;
530	532	m_lanc2_ram_w = 0;
	533	m_lanc2_reg[1] = (UINT8)(data >> 8);
531	534	}
532	535	else if (ACCESSING_BITS_16_23)
533	536	{
534		m_lanc2_ram[2] = (data >> 20) & 0xf;
535		m_lanc2_ram[3] = 0;
	537	if (m_lanc2_reg[0] != 0)
	538	{
	539	m_lanc2_ram[2] = (data >> 20) & 0xf;
	540	m_lanc2_ram[3] = 0;
	541	}
	542	m_lanc2_reg[2] = (UINT8)(data >> 16);
536	543	}
537	544	else if (ACCESSING_BITS_0_7)
538	545	{

trunk/src/mame/drivers/overdriv.cpp
r253153	r253154
82	82	{
83	83	// m_screen->frame_number() & 1
84	84	m_maincpu->set_input_line(4, HOLD_LINE);
85		m_subcpu->set_input_line(4, HOLD_LINE); // likely wrong
86	85	}
87	86	else if(m_fake_timer >= timer_threshold) // timer irq
88	87	{
r253153	r253154
91	90	}
92	91	}
93	92
	93	#ifdef UNUSED_FUNCTION
94	94	INTERRUPT_GEN_MEMBER(overdriv_state::cpuB_interrupt)
95	95	{
96	96	// this doesn't get turned on until the irq has happened? wrong irq?
97		if (m_k053246->k053246_is_irq_enabled())
98		m_subcpu->set_input_line(6, HOLD_LINE); // likely wrong
99	97	}
	98	#endif
100	99
101
102	100	WRITE16_MEMBER(overdriv_state::cpuA_ctrl_w)
103	101	{
104	102	if (ACCESSING_BITS_0_7)
r253153	r253154
142	140	}
143	141
144	142
145		WRITE16_MEMBER(overdriv_state::overdriv_cpuB_irq_x_w)
	143
	144
	145	WRITE16_MEMBER(overdriv_state::slave_irq4_assert_w)
146	146	{
147		m_subcpu->set_input_line(5, HOLD_LINE); // likely wrong
	147	// used in-game
	148	m_subcpu->set_input_line(4, HOLD_LINE);
148	149	}
149	150
150		WRITE16_MEMBER(overdriv_state::ove~~rdriv~~_~~cpuB_~~irq_y_w)
	151	WRITE16_MEMBER(overdriv_state::slave_irq5_assert_w)
151	152	{
	153	// tests GFX ROMs with this irq (indeed enabled only in test mode)
	154	m_subcpu->set_input_line(5, HOLD_LINE);
152	155	}
153	156
154	157	static ADDRESS_MAP_START( overdriv_master_map, AS_PROGRAM, 16, overdriv_state )
r253153	r253154
174	177	AM_RANGE(0x218000, 0x218fff) AM_DEVREADWRITE8("k051316_2", k051316_device, read, write, 0xff00)
175	178	AM_RANGE(0x220000, 0x220fff) AM_DEVREAD8("k051316_1", k051316_device, rom_r, 0xff00)
176	179	AM_RANGE(0x228000, 0x228fff) AM_DEVREAD8("k051316_2", k051316_device, rom_r, 0xff00)
177		AM_RANGE(0x230000, 0x230001) AM_WRITE(overdriv_cpuB_irq_y_w)
178		AM_RANGE(0x238000, 0x238001) AM_WRITE(overdriv_cpuB_irq_x_w)
	180	AM_RANGE(0x230000, 0x230001) AM_WRITE(slave_irq4_assert_w)
	181	AM_RANGE(0x238000, 0x238001) AM_WRITE(slave_irq5_assert_w)
179	182	ADDRESS_MAP_END
180	183
181	184	#ifdef UNUSED_FUNCTION
r253153	r253154
203	206	}
204	207	#endif
205	208
	209	TIMER_CALLBACK_MEMBER(overdriv_state::objdma_end_cb )
	210	{
	211	m_subcpu->set_input_line(6, HOLD_LINE);
	212	}
	213
	214	WRITE16_MEMBER(overdriv_state::objdma_w)
	215	{
	216	if(data & 0x10)
	217	machine().scheduler().timer_set(attotime::from_usec(100), timer_expired_delegate(FUNC(overdriv_state::objdma_end_cb), this));
	218
	219	m_k053246->k053246_w(space,5,data,mem_mask);
	220	}
	221
206	222	static ADDRESS_MAP_START( overdriv_slave_map, AS_PROGRAM, 16, overdriv_state )
207	223	AM_RANGE(0x000000, 0x03ffff) AM_ROM
208	224	AM_RANGE(0x080000, 0x083fff) AM_RAM /* work RAM */
r253153	r253154
212	228	AM_RANGE(0x118000, 0x118fff) AM_DEVREADWRITE("k053246", k053247_device, k053247_word_r, k053247_word_w) // data gets copied to sprite chip with DMA..
213	229	AM_RANGE(0x120000, 0x120001) AM_DEVREAD("k053246", k053247_device, k053246_word_r)
214	230	AM_RANGE(0x128000, 0x128001) AM_READWRITE(cpuB_ctrl_r, cpuB_ctrl_w) /* enable K053247 ROM reading, plus something else */
	231	AM_RANGE(0x130004, 0x130005) AM_WRITE(objdma_w)
215	232	AM_RANGE(0x130000, 0x130007) AM_DEVREADWRITE8("k053246", k053247_device, k053246_r,k053246_w,0xffff)
216		//AM_RANGE(0x140000, 0x140001) used in later stages
	233	//AM_RANGE(0x140000, 0x140001) used in later stages, set after writes at 0x208000-0x20bfff range
217	234	AM_RANGE(0x200000, 0x203fff) AM_RAM AM_SHARE("share1")
218		AM_RANGE(0x208000, 0x20bfff) AM_RAM
	235	AM_RANGE(0x208000, 0x20bfff) AM_RAM // sprite indirect table?
219	236	AM_RANGE(0x218000, 0x219fff) AM_DEVREAD("k053250_1", k053250_device, rom_r)
220	237	AM_RANGE(0x220000, 0x221fff) AM_DEVREAD("k053250_2", k053250_device, rom_r)
221	238	ADDRESS_MAP_END
r253153	r253154
303	320
304	321	MCFG_CPU_ADD("sub", M68000, XTAL_24MHz/2) /* 12 MHz */
305	322	MCFG_CPU_PROGRAM_MAP(overdriv_slave_map)
306		MCFG_CPU_VBLANK_INT_DRIVER("screen", overdriv_state, cpuB_interrupt) /* IRQ 5 and 6 are generated by the main CPU. */
307		/* IRQ 5 is used only in test mode, to request the checksums of the gfx ROMs. */
	323	//MCFG_CPU_VBLANK_INT_DRIVER("screen", overdriv_state, cpuB_interrupt)
	324	/* IRQ 5 and 6 are generated by the main CPU. */
	325	/* IRQ 5 is used only in test mode, to request the checksums of the gfx ROMs. */
308	326
309	327	MCFG_CPU_ADD("audiocpu", M6809, XTAL_3_579545MHz) /* 1.789 MHz?? This might be the right speed, but ROM testing */
310	328	MCFG_CPU_PROGRAM_MAP(overdriv_sound_map) /* takes a little too much (the counter wraps from 0000 to 9999). */

trunk/src/mame/drivers/pc9801.cpp
r253153	r253154
425	425	#include "machine/pc9801_118.h"
426	426	#include "machine/pc9801_cbus.h"
427	427	#include "machine/pc9801_kbd.h"
	428	#include "machine/pc9801_cd.h"
428	429
429	430	#include "machine/idectrl.h"
430	431	#include "machine/idehd.h"
r253153	r253154
3218	3219	}
3219	3220	}
3220	3221
	3222	SLOT_INTERFACE_START(pc9801_atapi_devices)
	3223	SLOT_INTERFACE("pc9801_cd", PC9801_CD)
	3224	SLOT_INTERFACE_END
	3225
3221	3226	static MACHINE_CONFIG_FRAGMENT( pc9801_keyboard )
3222	3227	MCFG_DEVICE_ADD("keyb", PC9801_KBD, 53)
3223	3228	MCFG_PC9801_KBD_IRQ_CALLBACK(DEVWRITELINE("pic8259_master", pic8259_device, ir1_w))
r253153	r253154
3266	3271	static MACHINE_CONFIG_FRAGMENT( pc9801_ide )
3267	3272	MCFG_ATA_INTERFACE_ADD("ide1", ata_devices, "hdd", nullptr, false)
3268	3273	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(pc9801_state, ide1_irq_w))
3269		MCFG_ATA_INTERFACE_ADD("ide2", ata_devices, "cd~~rom~~", nullptr, false)
	3274	MCFG_ATA_INTERFACE_ADD("ide2", pc9801_atapi_devices, "pc9801_cd", nullptr, false)
3270	3275	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(pc9801_state, ide2_irq_w))
3271	3276	MACHINE_CONFIG_END
3272	3277

trunk/src/mame/drivers/savquest.cpp
r253153	r253154
336	336	m_pci_3dfx_regs[0x08 / 4] = 2; // revision ID
337	337	m_pci_3dfx_regs[0x10 / 4] = 0xff000000;
338	338	m_pci_3dfx_regs[0x40 / 4] = 0x4000; //INITEN_SECONDARY_REV_ID
339		voodoo_set_init_enable(~~m_voodoo,~~ 0x4000); //INITEN_SECONDARY_REV_ID
	339	m_voodoo->voodoo_set_init_enable(0x4000); //INITEN_SECONDARY_REV_ID
340	340	}
341	341
342	342	static UINT32 pci_3dfx_r(device_t busdevice, device_t device, int function, int reg, UINT32 mem_mask)
r253153	r253154
358	358	}
359	359	else if (reg == 0x40)
360	360	{
361		voodoo_set_init_enable(~~state->m_voodoo,~~ data);
	361	state->m_voodoo->voodoo_set_init_enable(data);
362	362	}
363	363	else if (reg == 0x54)
364	364	{

trunk/src/mame/drivers/seattle.cpp
r253153	r253154
540	540
541	541	UINT32 seattle_state::screen_update_seattle(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
542	542	{
543		return voodoo_update(~~m_voodoo,~~ bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
	543	return m_voodoo->voodoo_update(bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
544	544	}
545	545
546	546
r253153	r253154
876	876	break;
877	877
878	878	case 0x10: /* initEnable register */
879		voodoo_set_init_enable(~~m_voodoo,~~ data);
	879	m_voodoo->voodoo_set_init_enable(data);
880	880	break;
881	881	}
882	882	if (LOG_PCI)

trunk/src/mame/drivers/stv.cpp
r253153	r253154
2901	2901	ROM_END
2902	2902
2903	2903
	2904	ROM_START( pclub2pf ) // set to 1p
	2905	STV_BIOS
	2906
	2907	ROM_REGION32_BE( 0x3000000, "cart", ROMREGION_ERASE00 ) /* SH2 code */
	2908
	2909	ROM_LOAD16_WORD_SWAP( "pclb2puf.IC22", 0x0200000, 0x0200000, CRC(a14282f2) SHA1(b96e70693d8e71b090e20efdd3aa6228e7289fa4) ) // OK
	2910	ROM_LOAD16_WORD_SWAP( "pclb2puf.IC24", 0x0400000, 0x0200000, CRC(4fb4dc74) SHA1(1f174512c9cd5420d7f935cbc6b5875836f6e825) ) // OK
	2911	ROM_LOAD16_WORD_SWAP( "pclb2puf.IC26", 0x0600000, 0x0200000, CRC(d20bbfb5) SHA1(5f2768e0e306bd0e3ed9b4e1d234aac8fd7155e6) ) // OK
	2912	ROM_LOAD16_WORD_SWAP( "pclb2puf.IC28", 0x0800000, 0x0200000, CRC(da658ae9) SHA1(24293c2b23b3009956fc05df5177a27415754301) ) // OK
	2913	ROM_LOAD16_WORD_SWAP( "pclb2puf.IC30", 0x0a00000, 0x0200000, CRC(cafc0e6b) SHA1(fa2ac54260336d5dd1ced7ccaf87115511ece1f8) ) // OK
	2914
	2915	ROM_REGION16_BE( 0x80, "eeprom", 0 ) // preconfigured to 1 player
	2916	ROM_LOAD( "pclub2pf.nv", 0x0000, 0x0080, CRC(447bb3bd) SHA1(9fefec09849bfa0c14b49e73ff13e2a538dff511) )
	2917	ROM_END
	2918
2904	2919	ROM_START( pclb297w ) // set to 1p
2905	2920	STV_BIOS
2906	2921
r253153	r253154
2940	2955	ROM_LOAD( "pclub298.nv", 0x0000, 0x0080, CRC(a23dd0f2) SHA1(457282b5d40a17477b95330bba91e05c603f951e) )
2941	2956	ROM_END
2942	2957
	2958
	2959	ROM_START( pclub26w ) // set to 1p
	2960	STV_BIOS
	2961
	2962	ROM_REGION32_BE( 0x3000000, "cart", ROMREGION_ERASE00 ) /* SH2 code */
	2963
	2964	ROM_LOAD16_WORD_SWAP( "pclbvol6w_IC22", 0x0200000, 0x0200000, CRC(72aa320c) SHA1(09bc30e8cb00a5a4014c44e468cc64f6c3425d92) )
	2965	ROM_LOAD16_WORD_SWAP( "pclbvol6w_IC24", 0x0400000, 0x0200000, CRC(d98371e2) SHA1(813ac5f3c5b57d07cc319c73560bc0719ddcfe6b) )
	2966	ROM_LOAD16_WORD_SWAP( "pclbvol6w_IC26", 0x0600000, 0x0200000, CRC(e6bbe3a5) SHA1(b2f642b8ca0779ad66cfbbadece40f4e3dc41fd1) )
	2967	ROM_LOAD16_WORD_SWAP( "pclbvol6w_IC28", 0x0800000, 0x0200000, CRC(3c330c9b) SHA1(92f8e8d4f43db7c4ce431d17501492a7f8d8a867) )
	2968	ROM_LOAD16_WORD_SWAP( "pclbvol6w_IC30", 0x0a00000, 0x0200000, CRC(67646090) SHA1(ed6402a22acafa0203c587b871edc547f0ec5277) )
	2969
	2970	ROM_REGION16_BE( 0x80, "eeprom", 0 ) // preconfigured to 1 player
	2971	ROM_LOAD( "pclub26w.nv", 0x0000, 0x0080, CRC(448f770d) SHA1(5f966c511c4c8e9d5b2d257c41c2c88a453b4944) )
	2972	ROM_END
	2973
	2974	ROM_START( pclub27s ) // set to 1p
	2975	STV_BIOS
	2976
	2977	ROM_REGION32_BE( 0x3000000, "cart", ROMREGION_ERASE00 ) /* SH2 code */
	2978
	2979	ROM_LOAD16_WORD_SWAP( "pclub2v7.IC22", 0x0200000, 0x0200000, CRC(44c8ab27) SHA1(65e2705b2918da32ea40375707df4e148b311159) )
	2980	ROM_LOAD16_WORD_SWAP( "pclub2v7.IC24", 0x0400000, 0x0200000, CRC(24818437) SHA1(5293d45b53680301abaf0b32a62596aaaa2552d6) )
	2981	ROM_LOAD16_WORD_SWAP( "pclub2v7.IC26", 0x0600000, 0x0200000, CRC(076c1d44) SHA1(d597ed4524bb03eb0ef8ada08d49f3dc0fc8136d) )
	2982	ROM_LOAD16_WORD_SWAP( "pclub2v7.IC28", 0x0800000, 0x0200000, CRC(ff9643ca) SHA1(3309f970f87324b06cc48add386019f769abcd89) )
	2983	ROM_LOAD16_WORD_SWAP( "pclub2v7.IC30", 0x0a00000, 0x0200000, CRC(03b9eacf) SHA1(d69c10f7613d9f52042dd6cce64e74e2b1ecc2d8) )
	2984
	2985	ROM_REGION16_BE( 0x80, "eeprom", 0 ) // preconfigured to 1 player
	2986	ROM_LOAD( "pclub27s.nv", 0x0000, 0x0080, CRC(e58c7167) SHA1(d88b1648c5d86a90615a8c6a1bf87bc9e75dc320) )
	2987	ROM_END
	2988
	2989	ROM_START( pclub2pe ) // set to 1p
	2990	STV_BIOS
	2991
	2992	ROM_REGION32_BE( 0x3000000, "cart", ROMREGION_ERASE00 ) /* SH2 code */
	2993
	2994	ROM_LOAD16_WORD_SWAP( "pclb2psi_IC22", 0x0200000, 0x0200000, CRC(caadc660) SHA1(f2e84bee96266bb03d8f9009249c17c27935f82e) )
	2995	ROM_LOAD16_WORD_SWAP( "pclb2psi_IC24", 0x0400000, 0x0200000, CRC(ece82698) SHA1(b17b1ea8adc13c3722067c9854d1b7fdf3917090) )
	2996	ROM_LOAD16_WORD_SWAP( "pclb2psi_IC26", 0x0600000, 0x0200000, CRC(c8a1e335) SHA1(a95ddfc41fdd9f720c11208f45ef5db4bee6cb97) )
	2997	ROM_LOAD16_WORD_SWAP( "pclb2psi_IC28", 0x0800000, 0x0200000, CRC(52f09627) SHA1(e2ffc321bb0f2a650d0c0b39c3ec68226e1ca7f4) )
	2998	ROM_LOAD16_WORD_SWAP( "pclb2psi_IC30", 0x0a00000, 0x0200000, CRC(03b9eacf) SHA1(d69c10f7613d9f52042dd6cce64e74e2b1ecc2d8) )
	2999
	3000	ROM_REGION16_BE( 0x80, "eeprom", 0 ) // preconfigured to 1 player
	3001	ROM_LOAD( "pclub2pe.nv", 0x0000, 0x0080, CRC(447bb3bd) SHA1(9fefec09849bfa0c14b49e73ff13e2a538dff511))
	3002	ROM_END
	3003
	3004
	3005	ROM_START( pclubyo2 ) // set to 1p
	3006	STV_BIOS
	3007
	3008	ROM_REGION32_BE( 0x3000000, "cart", ROMREGION_ERASE00 ) /* SH2 code */
	3009
	3010	ROM_LOAD16_WORD_SWAP( "pclbyov2.IC22", 0x0200000, 0x0200000, CRC(719a4d27) SHA1(328dfb8debea02e8660e636e953982d381529945) )
	3011	ROM_LOAD16_WORD_SWAP( "pclbyov2.IC24", 0x0400000, 0x0200000, CRC(790dc7b5) SHA1(829ead39930779617a9bef41d8615362ca86c4c7) )
	3012	ROM_LOAD16_WORD_SWAP( "pclbyov2.IC26", 0x0600000, 0x0200000, CRC(12ae1606) SHA1(9534fb2dbf6fd2c258ba2716783cc5bab8bd8dc0) )
	3013	ROM_LOAD16_WORD_SWAP( "pclbyov2.IC28", 0x0800000, 0x0200000, CRC(ff9643ca) SHA1(3309f970f87324b06cc48add386019f769abcd89) )
	3014	ROM_LOAD16_WORD_SWAP( "pclbyov2.IC30", 0x0a00000, 0x0200000, CRC(03b9eacf) SHA1(d69c10f7613d9f52042dd6cce64e74e2b1ecc2d8) )
	3015
	3016	ROM_REGION16_BE( 0x80, "eeprom", 0 ) // preconfigured to 1 player
	3017	ROM_LOAD( "pclubyo2.nv", 0x0000, 0x0080, CRC(2b26a8f7) SHA1(32f34096cac05a37c492ee389ed8e4c02694c268) )
	3018	ROM_END
	3019
	3020
2943	3021	ROM_START( pclb298a ) // set to 1p
2944	3022	STV_BIOS
2945	3023
r253153	r253154
3058	3136	ROM_LOAD( "pclb2elk.nv", 0x0000, 0x0080, CRC(54c7564f) SHA1(574dcc5e8fe4aac091fee1476347485ed660eddd) )
3059	3137	ROM_END
3060	3138
	3139	ROM_START( pclove )
	3140	STV_BIOS
3061	3141
	3142	ROM_REGION32_BE( 0x3000000, "cart", ROMREGION_ERASE00 ) /* SH2 code */
	3143	// note, 'IC2' in service mode (the test of IC24/IC26) fails once you map the protection device because it occupies the same memory address as the rom at IC26
	3144	// there must be a way to enable / disable it.
	3145	ROM_LOAD16_WORD_SWAP( "pclbLove.ic22", 0x0200000, 0x0200000, CRC(8cd25a0f) SHA1(c938d5f4f800db019abc2e17cce1e780e93f3d02) ) // OK (tested as IC7)
	3146	ROM_LOAD16_WORD_SWAP( "pclbLove.ic24", 0x0400000, 0x0200000, CRC(85583e2c) SHA1(7f407d1bce40317fc10433dafcd82ee41be05839) ) // OK (tested as IC2)
	3147	ROM_LOAD16_WORD_SWAP( "pclbLove.ic26", 0x0600000, 0x0200000, CRC(7efcabcc) SHA1(b99a67ab2053c3be5ce37530b65f9693c2a4eef8) ) // OK (tested as IC2)
	3148	ROM_LOAD16_WORD_SWAP( "pclbLove.ic28", 0x0800000, 0x0200000, CRC(a1336da7) SHA1(ba26810067a13968a54a8867025b8d8e96384ae7) ) // OK (tested as IC3)
	3149	ROM_LOAD16_WORD_SWAP( "pclbLove.ic30", 0x0a00000, 0x0200000, CRC(ec5b5e28) SHA1(89bcddb52c176c86ad4bdb9f4f052be5b75bcd1b) ) // OK (tested as IC3)
	3150	ROM_LOAD16_WORD_SWAP( "pclbLove.ic32", 0x0c00000, 0x0200000, CRC(9a4109e5) SHA1(ba59caac5f5a80fc52c507d8a47f322a380aa9a1) ) // FF fill? (not tested either)
	3151
	3152	// protection device used to decrypt some startup code
	3153
	3154	ROM_REGION16_BE( 0x80, "eeprom", 0 ) // preconfigured to 1 player
	3155	ROM_LOAD( "pclove.nv", 0x0000, 0x0080, CRC(3c78e3bd) SHA1(6d5fe8545f434b4cc1e8229549adb0a49ac45bd1) )
	3156	ROM_END
	3157
	3158	// Name Club / Name Club vol.2
	3159	// have an unusual rom mapping compared to other games, the cartridge is a little different too, with a large PALCE16V8H-10 marked 315-6026
	3160	// For Name Club vol. 2, the protection device (317-0229 on both) is checked in the 'each game test' menu as 'RCDD2'
	3161	// For the service mode test the game just passes a large block of compressed data and checksums the result, it doesn't even look like it's
	3162	// passing 100% valid data, just an entire section of ROM, checking the result against a pre-calculated checksum.
	3163
	3164	// The device is accessed by the game when you choose to print, it looks like it's decompressing the full-size graphics for the printer rather
	3165	// than anything you see onscreen. It makes quite extensive use of the device, with lots of different dictionaries, unlike Decathlete where
	3166	// there are only 2 that cover all the data.
	3167
	3168	ROM_START( nameclub )
	3169	STV_BIOS
	3170
	3171	ROM_REGION32_BE( 0x3000000, "cart", ROMREGION_ERASEFF ) /* SH2 code */
	3172	ROM_LOAD16_WORD_SWAP( "ic22", 0x0200000, 0x0200000, CRC(ac23c648) SHA1(4dd099a92ff162082eb24a61a277ca907b3f9892) ) // OK
	3173	ROM_LOAD16_WORD_SWAP( "ic24", 0x0600000, 0x0200000, CRC(a16902e3) SHA1(85c582cb0d02ef028a8ae32688c20a5b5aeeaae8) ) // OK
	3174	ROM_LOAD16_WORD_SWAP( "ic26", 0x0a00000, 0x0200000, CRC(a5eab3f3) SHA1(1b7263639bb8f4aa644cc46133988ef4d2b6c9de) ) // OK
	3175	ROM_LOAD16_WORD_SWAP( "ic28", 0x0e00000, 0x0200000, CRC(34ed677a) SHA1(ff2c4dd8fae33ac618f6e3e28ba71c4ecb4ca88f) ) // OK
	3176
	3177	ROM_REGION16_BE( 0x80, "eeprom", 0 ) // preconfigured to 1 player
	3178	ROM_LOAD( "nameclub.nv", 0x0000, 0x0080, CRC(680a64bc) SHA1(45194bbe4a7e67f0e44f858589881967884f63a6) )
	3179	ROM_END
	3180
	3181	ROM_START( nclubv2 )
	3182	STV_BIOS
	3183
	3184	ROM_REGION32_BE( 0x3000000, "cart", ROMREGION_ERASEFF ) /* SH2 code */
	3185	ROM_LOAD16_WORD_SWAP( "nclubv2.ic22", 0x0200000, 0x0200000, CRC(7e81676d) SHA1(fc0f0dcdb4aaf71218d7c1dd0e4ddc5381e8b13b) ) // OK
	3186	ROM_LOAD16_WORD_SWAP( "nclubv2.ic24", 0x0600000, 0x0200000, CRC(1b7637de) SHA1(43c3094f60a6582298a45bad923fef57e98c5b2b) ) // OK
	3187	ROM_LOAD16_WORD_SWAP( "nclubv2.ic26", 0x0a00000, 0x0200000, CRC(630be99d) SHA1(ac7fbaae98b126fad5228b0ebffa91a0f0a94516) ) // OK
	3188	ROM_LOAD16_WORD_SWAP( "nclubv2.ic28", 0x0e00000, 0x0200000, CRC(1a3ca5e2) SHA1(4d3aed51d29c54e71175d828f648c9feb813ac04) ) // OK
	3189
	3190	ROM_REGION16_BE( 0x80, "eeprom", 0 ) // preconfigured to 1 player
	3191	ROM_LOAD( "nclubv2.nv", 0x0000, 0x0080, CRC(96d55fa9) SHA1(b3c821d6cd4ed52d0e20565e12a06d8f81a08dbc) )
	3192	ROM_END
	3193
	3194
	3195
3062	3196	GAME( 1996, stvbios, 0, stv_slot, stv, stv_state, stv, ROT0, "Sega", "ST-V Bios", MACHINE_IS_BIOS_ROOT )
3063	3197
3064	3198	//GAME YEAR, NAME, PARENT, MACH, INP, INIT, MONITOR
r253153	r253154
3114	3248	GAME( 1997, znpwfv, stvbios, stv, stv, stv_state, znpwfv, ROT0, "Sega", "Zen Nippon Pro-Wrestling Featuring Virtua (J 971123 V1.000)", MACHINE_IMPERFECT_SOUND \| MACHINE_IMPERFECT_GRAPHICS )
3115	3249
3116	3250	/* Unemulated printer / camera devices */
3117		GAME( 1998, stress, stvbios, stv, stv, stv_state, stv, ROT0, "Sega", "Stress Busters (J 981020 V1.000)", MACHINE_NOT_WORKING \| MACHINE_IMPERFECT_GRAPHICS \| MACHINE_IMPERFECT_SOUND )
3118		GAME( 1997, nclubv3, stvbios, stv, stv, stv_state, nameclv3, ROT0, "Sega", "Name Club Ver.3 (J 970723 V1.000)", MACHINE_IMPERFECT_SOUND \| MACHINE_IMPERFECT_GRAPHICS \| MACHINE_NOT_WORKING )
3119		GAME( 1997, pclub2, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 (U 970921 V1.000)", MACHINE_NOT_WORKING )
	3251	// USA sets
	3252	GAME( 1997, pclub2, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 (U 970921 V1.000)", MACHINE_NOT_WORKING )
	3253	GAME( 1999, pclub2v3, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Vol. 3 (U 990310 V1.000)", MACHINE_NOT_WORKING ) // Hello Kitty themed
	3254	GAME( 1999, pclubpok, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club Pokemon B (U 991126 V1.000)", MACHINE_NOT_WORKING )
	3255	// Japan sets
3120	3256	GAME( 1999, pclub2fc, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Felix The Cat (Rev. A) (J 970415 V1.100)", MACHINE_NOT_WORKING )
3121		GAME( 1997, pclb297w, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 '97 Winter Ver (J 971017 V1.100)", MACHINE_NOT_WORKING )
3122		GAME( 1997, pclub298, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 '98 Spring Ver (J 971017 V1.100)", MACHINE_NOT_WORKING )
	3257	GAME( 1998, pclub2pf, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Puffy (Japan)", MACHINE_NOT_WORKING ) // version info is blank
	3258	GAME( 1997, pclb2elk, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Earth Limited Kobe (Print Club Custom) (J 970808 V1.000)", MACHINE_NOT_WORKING )
	3259	GAME( 1997, pclub2pe, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Pepsiman (J 970618 V1.100)", MACHINE_NOT_WORKING )
	3260
	3261	GAME( 1997, pclub26w, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Vol. 6 Winter (J 961210 V1.000)", MACHINE_NOT_WORKING ) // internal string is 'PURIKURA2 97FUYU' (but in reality it seems to be an end of 96 Winter version)
	3262	GAME( 1997, pclub27s, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Vol. 7 Spring (J 970313 V1.100)", MACHINE_NOT_WORKING )
	3263	// Summer 97?
	3264	// Autumn 97?
	3265	GAME( 1997, pclb297w, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 '97 Winter Ver (J 971017 V1.100)", MACHINE_NOT_WORKING ) // internal string is '97WINTER' (3 roms bad / missing tho, need new dump)
	3266	GAME( 1997, pclub298, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 '98 Spring Ver (J 971017 V1.100)", MACHINE_NOT_WORKING ) // date is the same as previous version, surely incorrect / not updated when the game was
	3267	// Summer 98?
3123	3268	GAME( 1998, pclb298a, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 '98 Autumn Ver (J 980827 V1.000)", MACHINE_NOT_WORKING )
	3269
	3270
3124	3271	GAME( 1999, pclubor, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club Goukakenran (J 991104 V1.000)", MACHINE_NOT_WORKING )
3125	3272	GAME( 1999, pclubol, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club Olive (J 980717 V1.000)", MACHINE_NOT_WORKING )
3126		GAME( 1999, pclub2v3, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Vol. 3 (U 990310 V1.000)", MACHINE_NOT_WORKING )
3127		GAME( 1999, pclubpok, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club Pokemon B (U 991126 V1.000)", MACHINE_NOT_WORKING )
3128	3273	GAME( 1997, pclub2kc, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club Kome Kome Club (J 970203 V1.000)", MACHINE_NOT_WORKING )
3129		GAME( 1997, pclb2elk, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Earth Limited Kobe (Print Club Custom) (J 970808 V1.000)", MACHINE_NOT_WORKING )
	3274	GAME( 1997, pclove, stvbios, stv_5838, stv, stv_state, decathlt, ROT0, "Atlus", "Print Club LoveLove (J 970421 V1.000)", MACHINE_NOT_WORKING ) // uses the same type of protection as decathlete!!
	3275	GAME( 1997, pclubyo2, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club Yoshimoto V2 (J 970422 V1.100)", MACHINE_NOT_WORKING )
3130	3276
	3277	GAME( 1998, stress, stvbios, stv, stv, stv_state, stv, ROT0, "Sega", "Stress Busters (J 981020 V1.000)", MACHINE_NOT_WORKING \| MACHINE_IMPERFECT_GRAPHICS \| MACHINE_IMPERFECT_SOUND )
3131	3278
	3279	GAME( 1996, nameclub, stvbios, stv_5838, stv, stv_state, decathlt, ROT0, "Sega", "Name Club (J 960315 V1.000)", MACHINE_NOT_WORKING ) // uses the same type of protection as decathlete!!
	3280	GAME( 1996, nclubv2, stvbios, stv_5838, stv, stv_state, decathlt, ROT0, "Sega", "Name Club Ver.2 (J 960315 V1.000)", MACHINE_NOT_WORKING ) // ^ (has the same datecode as nameclub, probably incorrect unless both were released today)
	3281	GAME( 1997, nclubv3, stvbios, stv, stv, stv_state, nameclv3, ROT0, "Sega", "Name Club Ver.3 (J 970723 V1.000)", MACHINE_IMPERFECT_SOUND \| MACHINE_IMPERFECT_GRAPHICS \| MACHINE_NOT_WORKING ) // no protection
	3282
	3283
	3284
3132	3285	/* Doing something.. but not enough yet */
3133	3286	GAME( 1995, vfremix, stvbios, stv, stv, stv_state, vfremix, ROT0, "Sega", "Virtua Fighter Remix (JUETBKAL 950428 V1.000)", MACHINE_IMPERFECT_SOUND \| MACHINE_IMPERFECT_GRAPHICS \| MACHINE_NOT_WORKING )
3134	3287	GAME( 1996, decathlt, stvbios, stv_5838, stv, stv_state, decathlt, ROT0, "Sega", "Decathlete (JUET 960709 V1.001)", MACHINE_NO_SOUND \| MACHINE_NOT_WORKING \| MACHINE_UNEMULATED_PROTECTION )

trunk/src/mame/drivers/tispeak.cpp
r253153	r253154
80	80	- notes: this one has a dedicated voice actor
81	81
82	82	Speak & Spell (France) "La Dictee Magique", 1980
83		- MCU: CD2702*
	83	- MCU: CD2702, labeled CD2702AN2L (die labeled TMC0270F 2702A)
84	84	- TMS51xx: CD2801
85	85	- VSM: 16KB CD2352
86	86
r253153	r253154
143	143	Speak & Math:
144	144
145	145	Speak & Math (US), 1980 (renamed to "Speak & Maths" in UK, but is the same product)
146		- MCU: CD2704*
	146	- MCU: CD2704, labeled CD2704B-N2L (die labeled TMC0270F 2704B) - 2nd revision?(mid-1982)
147	147	- TMS51xx: CD2801
148	148	- VSM(1/2): 16KB CD2392
149	149	- VSM(2/2): 16KB CD2393
r253153	r253154
170	170	Speak & Read:
171	171
172	172	Speak & Read (US), 1980
173		- MCU: CD2705, labeled CD2705B-N2L (die labeled TMC0270E 2705B) - 2nd revision?
	173	- MCU: CD2705, labeled CD2705B-N2L (die labeled TMC0270E 2705B) - 2nd revision?(late-1981)
174	174	- TMS51xx: CD2801
175	175	- VSM(1/2): 16KB CD2394(rev.A)
176	176	- VSM(2/2): 16KB CD2395(rev.A)
r253153	r253154
1242	1242	ROM_REGION( 2127, "maincpu:mpla", 0 )
1243	1243	ROM_LOAD( "tms0270_common2_micro.pla", 0, 2127, CRC(86737ac1) SHA1(4aa0444f3ddf88738ea74aec404c684bf54eddba) )
1244	1244	ROM_REGION( 1246, "maincpu:opla", 0 )
1245		ROM_LOAD( "tms0270_tmc0271_output.pla", 0, 1246, CRC(9ebe12ab) SHA1(acb4e07ba26f2daca5f1c234885ac0371c7ce87f) ) // using the one from 1~~978~~ version
	1245	ROM_LOAD( "tms0270_tmc0271_output.pla", 0, 1246, CRC(9ebe12ab) SHA1(acb4e07ba26f2daca5f1c234885ac0371c7ce87f) ) // using the one from 1st version
1246	1246
1247	1247	ROM_REGION( 0x10000, "tms6100", ROMREGION_ERASEFF ) // 8000-bfff = space reserved for cartridge
1248		ROM_LOAD( "tmc0351nl.vsm", 0x0000, 0x4000, CRC(beea3373) SHA1(8b0f7586d2f12c3d4a885fdb528cf23feffa1a3b) ) // using the one from 1~~978~~ version
	1248	ROM_LOAD( "tmc0351nl.vsm", 0x0000, 0x4000, CRC(beea3373) SHA1(8b0f7586d2f12c3d4a885fdb528cf23feffa1a3b) ) // using the one from 1st version
1249	1249	ROM_LOAD( "tmc0352nl.vsm", 0x4000, 0x4000, CRC(d51f0587) SHA1(ddaa484be1bba5fef46b481cafae517e4acaa8ed) ) // "
1250	1250	ROM_END
1251	1251
r253153	r253154
1256	1256	ROM_REGION( 1246, "maincpu:ipla", 0 )
1257	1257	ROM_LOAD( "tms0980_common1_instr.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
1258	1258	ROM_REGION( 2127, "maincpu:mpla", 0 )
1259		ROM_LOAD( "tms0270_common2_micro.pla", 0, 2127, ~~BAD_DUMP~~ CRC(86737ac1) SHA1(4aa0444f3ddf88738ea74aec404c684bf54eddba) ) ~~// not verified~~
	1259	ROM_LOAD( "tms0270_common2_micro.pla", 0, 2127, CRC(86737ac1) SHA1(4aa0444f3ddf88738ea74aec404c684bf54eddba) )
1260	1260	ROM_REGION( 1246, "maincpu:opla", 0 )
1261	1261	ROM_LOAD( "tms0270_tmc0271_output.pla", 0, 1246, CRC(9ebe12ab) SHA1(acb4e07ba26f2daca5f1c234885ac0371c7ce87f) )
1262	1262
r253153	r253154
1287	1287	ROM_REGION( 1246, "maincpu:ipla", 0 )
1288	1288	ROM_LOAD( "tms0980_common1_instr.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
1289	1289	ROM_REGION( 2127, "maincpu:mpla", 0 )
1290		ROM_LOAD( "tms0270_common2_micro.pla", 0, 2127, ~~BAD_DUMP~~ CRC(86737ac1) SHA1(4aa0444f3ddf88738ea74aec404c684bf54eddba) ) ~~// not verified~~
	1290	ROM_LOAD( "tms0270_common2_micro.pla", 0, 2127, CRC(86737ac1) SHA1(4aa0444f3ddf88738ea74aec404c684bf54eddba) )
1291	1291	ROM_REGION( 1246, "maincpu:opla", 0 )
1292	1292	ROM_LOAD( "tms0270_tmc0271_output.pla", 0, 1246, CRC(9ebe12ab) SHA1(acb4e07ba26f2daca5f1c234885ac0371c7ce87f) )
1293	1293
r253153	r253154
1329	1329
1330	1330	ROM_START( snspellfr )
1331	1331	ROM_REGION( 0x1000, "maincpu", 0 )
1332		ROM_LOAD( "tmc027~~1h-~~n2l", 0x0000, 0x1000, ~~BAD_DUMP~~ CRC(f83b5d2d) SHA1(~~10155~~b~~0b7f7f~~1583c~~7def~~8a693553cd35944ea6f) ) ~~// placeholder, use the one we have~~
	1332	ROM_LOAD( "cd2702an2l", 0x0000, 0x1000, CRC(895d6a4e) SHA1(a8bc118c83a84260033734191dcaa71a93dfa52b) )
1333	1333
1334	1334	ROM_REGION( 1246, "maincpu:ipla", 0 )
1335	1335	ROM_LOAD( "tms0980_common1_instr.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
1336	1336	ROM_REGION( 2127, "maincpu:mpla", 0 )
1337		ROM_LOAD( "tms0270_common2_micro.pla", 0, 2127, ~~BAD_DUMP~~ CRC(86~~737ac1~~) SHA1(~~4aa~~0~~444f3ddf88~~738ea74aec40~~4c6~~84bf54~~edd~~ba) ) ~~// not verified~~
	1337	ROM_LOAD( "tms0270_common1_micro.pla", 0, 2127, CRC(504b96bb) SHA1(67b691e7c0b97239410587e50e5182bf46475b43) )
1338	1338	ROM_REGION( 1246, "maincpu:opla", 0 )
1339		ROM_LOAD( "tms0270_tmc0271h_output.pla", 0, 1246, ~~BAD_DUMP~~ CRC(2478c595) SHA1(9a8ac690902731e1e01533279a1c9223011e1537) ) ~~// placeholder, use the one we have~~
	1339	ROM_LOAD( "tms0270_cd2702_output.pla", 0, 1246, CRC(2478c595) SHA1(9a8ac690902731e1e01533279a1c9223011e1537) )
1340	1340
1341	1341	ROM_REGION( 0x10000, "tms6100", ROMREGION_ERASEFF ) // uses only 1 rom, 8000-bfff = space reserved for cartridge
1342	1342	ROM_LOAD( "cd2352.vsm", 0x0000, 0x4000, CRC(181a239e) SHA1(e16043766c385e152b7005c1c010be4c5fccdd9b) )
r253153	r253154
1344	1344
1345	1345	ROM_START( snspellit )
1346	1346	ROM_REGION( 0x1000, "maincpu", 0 )
1347		ROM_LOAD( "tmc027~~1h-~~n2l", 0x0000, 0x1000, ~~BAD_DUMP~~ CRC(f83b5d2d) SHA1(~~10155~~b~~0b7f7f~~1583c~~7def~~8a693553cd35944ea6f) ) ~~// placeholder, use the one we have~~
	1347	ROM_LOAD( "cd2702an2l", 0x0000, 0x1000, CRC(895d6a4e) SHA1(a8bc118c83a84260033734191dcaa71a93dfa52b) )
1348	1348
1349	1349	ROM_REGION( 1246, "maincpu:ipla", 0 )
1350	1350	ROM_LOAD( "tms0980_common1_instr.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
1351	1351	ROM_REGION( 2127, "maincpu:mpla", 0 )
1352		ROM_LOAD( "tms0270_common2_micro.pla", 0, 2127, ~~BAD_DUMP~~ CRC(86~~737ac1~~) SHA1(~~4aa~~0~~444f3ddf88~~738ea74aec40~~4c6~~84bf54~~edd~~ba) ) ~~// not verified~~
	1352	ROM_LOAD( "tms0270_common1_micro.pla", 0, 2127, CRC(504b96bb) SHA1(67b691e7c0b97239410587e50e5182bf46475b43) )
1353	1353	ROM_REGION( 1246, "maincpu:opla", 0 )
1354		ROM_LOAD( "tms0270_tmc0271h_output.pla", 0, 1246, ~~BAD_DUMP~~ CRC(2478c595) SHA1(9a8ac690902731e1e01533279a1c9223011e1537) ) ~~// placeholder, use the one we have~~
	1354	ROM_LOAD( "tms0270_cd2702_output.pla", 0, 1246, CRC(2478c595) SHA1(9a8ac690902731e1e01533279a1c9223011e1537) )
1355	1355
1356	1356	ROM_REGION( 0x10000, "tms6100", ROMREGION_ERASEFF ) // uses only 1 rom, 8000-bfff = space reserved for cartridge
1357	1357	ROM_LOAD( "cd62190.vsm", 0x0000, 0x4000, CRC(63832002) SHA1(ea8124b2bf0f5908c5f1a56d60063f2468a10143) )
r253153	r253154
1400	1400
1401	1401	ROM_START( snmath )
1402	1402	ROM_REGION( 0x1000, "maincpu", 0 )
1403		ROM_LOAD( "cd2708n2l", 0x0000, 0x1000, CRC(~~3593~~7360) SHA1(69c3~~62c7~~5~~bb45905~~6~~c09c7f~~ab37c9104048~~5474~~b) )
	1403	ROM_LOAD( "cd2704b-n2l", 0x0000, 0x1000, CRC(7e06c7c5) SHA1(d60a35a8163ab593c31afc840a0d8a9b3a762f29) )
1404	1404
1405	1405	ROM_REGION( 1246, "maincpu:ipla", 0 )
1406	1406	ROM_LOAD( "tms0980_common1_instr.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
1407	1407	ROM_REGION( 2127, "maincpu:mpla", 0 )
1408	1408	ROM_LOAD( "tms0270_common1_micro.pla", 0, 2127, CRC(504b96bb) SHA1(67b691e7c0b97239410587e50e5182bf46475b43) )
1409	1409	ROM_REGION( 1246, "maincpu:opla", 0 )
	1410	ROM_LOAD( "tms0270_cd2704_output.pla", 0, 1246, CRC(5a2eb949) SHA1(8bb161d4884f229af65f8d155e59b9d8966fe3d1) )
	1411
	1412	ROM_REGION( 0x8000, "tms6100", ROMREGION_ERASEFF )
	1413	ROM_LOAD( "cd2392.vsm", 0x0000, 0x4000, CRC(4ed2e920) SHA1(8896f29e25126c1e4d9a47c9a325b35dddecc61f) )
	1414	ROM_LOAD( "cd2393.vsm", 0x4000, 0x4000, CRC(571d5b5a) SHA1(83284755d9b77267d320b5b87fdc39f352433715) )
	1415	ROM_END
	1416
	1417	ROM_START( snmatha )
	1418	ROM_REGION( 0x1000, "maincpu", 0 )
	1419	ROM_LOAD( "cd2708-n2l", 0x0000, 0x1000, CRC(35937360) SHA1(69c362c75bb459056c09c7fab37c91040485474b) )
	1420
	1421	ROM_REGION( 1246, "maincpu:ipla", 0 )
	1422	ROM_LOAD( "tms0980_common1_instr.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
	1423	ROM_REGION( 2127, "maincpu:mpla", 0 )
	1424	ROM_LOAD( "tms0270_common1_micro.pla", 0, 2127, CRC(504b96bb) SHA1(67b691e7c0b97239410587e50e5182bf46475b43) )
	1425	ROM_REGION( 1246, "maincpu:opla", 0 )
1410	1426	ROM_LOAD( "tms0270_cd2708_output.pla", 0, 1246, CRC(1abad753) SHA1(53d20b519ed73ce248368047a056836afbe3cd46) )
1411	1427
1412	1428	ROM_REGION( 0x8000, "tms6100", ROMREGION_ERASEFF )
r253153	r253154
1426	1442	ROM_REGION( 1246, "maincpu:ipla", 0 )
1427	1443	ROM_LOAD( "tms0980_common1_instr.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
1428	1444	ROM_REGION( 2127, "maincpu:mpla", 0 )
1429		ROM_LOAD( "tms0270_common1_micro.pla", 0, 2127, ~~BAD_DUMP~~ CRC(504b96bb) SHA1(67b691e7c0b97239410587e50e5182bf46475b43) ) ~~// not verified~~
	1445	ROM_LOAD( "tms0270_common1_micro.pla", 0, 2127, CRC(504b96bb) SHA1(67b691e7c0b97239410587e50e5182bf46475b43) )
1430	1446	ROM_REGION( 1246, "maincpu:opla", 0 )
1431		ROM_LOAD( "tms0270_cd2708_output.pla", 0, 1246, ~~BAD_DUMP~~ CRC(1ab~~ad753~~) SHA1(~~53d20~~b519ed~~73ce2~~48368047a056836afbe3cd46) ) // taken from ~~cd2708, need~~ to ver~~ify if it'~~s ~~same as cd2704~~
	1447	ROM_LOAD( "tms0270_cd2704_output.pla", 0, 1246, CRC(5a2eb949) SHA1(8bb161d4884f229af65f8d155e59b9d8966fe3d1) ) // using the one from 1st version
1432	1448
1433	1449	ROM_REGION( 0x8000, "tms6100", ROMREGION_ERASEFF )
1434		ROM_LOAD( "cd2392.vsm", 0x0000, 0x4000, CRC(4ed2e920) SHA1(8896f29e25126c1e4d9a47c9a325b35dddecc61f) )
1435		ROM_LOAD( "cd2393.vsm", 0x4000, 0x4000, CRC(571d5b5a) SHA1(83284755d9b77267d320b5b87fdc39f352433715) )
	1450	ROM_LOAD( "cd2392.vsm", 0x0000, 0x4000, CRC(4ed2e920) SHA1(8896f29e25126c1e4d9a47c9a325b35dddecc61f) ) // using the one from 1st version
	1451	ROM_LOAD( "cd2393.vsm", 0x4000, 0x4000, CRC(571d5b5a) SHA1(83284755d9b77267d320b5b87fdc39f352433715) ) // "
1436	1452	ROM_END
1437	1453
1438	1454
r253153	r253154
1537	1553
1538	1554
1539	1555	/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY, FULLNAME, FLAGS */
1540		COMP( 1978, snspell, 0, 0, sns_tmc0281, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (US, 1979 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
	1556	COMP( 1979, snspell, 0, 0, sns_tmc0281, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (US, 1979 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1541	1557	COMP( 1978, snspellp, snspell, 0, sns_tmc0281, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (US, patent)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1542	1558	COMP( 1980, snspellub, snspell, 0, sns_tmc0281d, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (US, 1980 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1543		COMP( 1979, snspellua, snspell, 0, sns_tmc0281, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (US, 1978 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_NOT_WORKING ) // incomplete dump, using 1979 MCU ROM instead
1544		COMP( 1978, snspelluk, snspell, 0, sns_tmc0281, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (UK, 1978 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_NOT_WORKING ) // "
	1559	COMP( 1978, snspellua, snspell, 0, sns_tmc0281, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (US, 1978 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND ) // incomplete dump, using 1979 MCU ROM instead
	1560	COMP( 1978, snspelluk, snspell, 0, sns_tmc0281, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (UK, 1978 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND ) // "
1545	1561	COMP( 1981, snspelluka, snspell, 0, sns_cd2801, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (UK, 1981 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1546	1562	COMP( 1979, snspelljp, snspell, 0, sns_tmc0281, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (Japan)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1547		COMP( 1980, snspellfr, snspell, 0, sns_cd2801, snspellfr, tispeak_state, snspell, "Texas Instruments", "La Dictee Magique (France)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_NOT_WORKING ) // doesn't work due to missing CD2702 MCU dump, German/Italian version has CD2702 too
1548		COMP( 1982, snspellit, snspell, 0, sns_cd2801_m, snspellit, tispeak_state, snspell, "Texas Instruments", "Grillo Parlante (Italy)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_NOT_WORKING ) // "
	1563	COMP( 1980, snspellfr, snspell, 0, sns_cd2801, snspellfr, tispeak_state, snspell, "Texas Instruments", "La Dictee Magique (France)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
	1564	COMP( 1982, snspellit, snspell, 0, sns_cd2801_m, snspellit, tispeak_state, snspell, "Texas Instruments", "Grillo Parlante (Italy)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1549	1565
1550	1566	COMP( 1981, snspellc, 0, 0, snspellc, snspellc, tispeak_state, snspell, "Texas Instruments", "Speak & Spell Compact (US, 1981 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1551	1567	COMP( 1982, snspellca, snspellc, 0, snspellc, snspellc, tispeak_state, snspell, "Texas Instruments", "Speak & Spell Compact (US, 1982 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1552	1568	COMP( 1982, snspellcuk, snspellc, 0, snspellcuk, snspellcuk, tispeak_state, snspell, "Texas Instruments", "Speak & Write (UK)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1553	1569
1554		COMP( 1986, snmath, 0, 0, snmath, snmath, driver_device, 0, "Texas Instruments", "Speak & Math (US, 1986 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1555		COMP( 1980, snmathp, snmath, 0, snmath, snmath, driver_device, 0, "Texas Instruments", "Speak & Math (US, 1980 version/patent)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_NOT_WORKING )
	1570	COMP( 1980, snmath, 0, 0, snmath, snmath, driver_device, 0, "Texas Instruments", "Speak & Math (US, 1980 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
	1571	COMP( 1986, snmatha, snmath, 0, snmath, snmath, driver_device, 0, "Texas Instruments", "Speak & Math (US, 1986 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
	1572	COMP( 1980, snmathp, snmath, 0, snmath, snmath, driver_device, 0, "Texas Instruments", "Speak & Math (US, patent)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_IS_INCOMPLETE )
1556	1573
1557	1574	COMP( 1980, snread, 0, 0, snread, snread, tispeak_state, snspell, "Texas Instruments", "Speak & Read (US)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1558	1575
1559	1576	COMP( 1979, lantutor, 0, 0, lantutor, lantutor, tispeak_state, lantutor, "Texas Instruments", "Language Tutor (patent)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_NOT_WORKING )
1560	1577
1561		COMP( 1981, tntell, 0, 0, tntell, tntell, tispeak_state, tntell, "Texas Instruments", "Touch & Tell (US, 1981 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_CLICKABLE_ARTWORK \| MACHINE_REQUIRES_ARTWORK ) // assume there is an older version too, with CD8010 MCU
1562		COMP( 1980, tntellp, tntell, 0, tntell, tntell, tispeak_state, tntell, "Texas Instruments", "Touch & Tell (patent)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_CLICKABLE_ARTWORK \| MACHINE_REQUIRES_ARTWORK \| MACHINE_NOT_WORKING )
	1578	COMP( 1981, tntell, 0, 0, tntell, tntell, tispeak_state, tntell, "Texas Instruments", "Touch & Tell (US)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_CLICKABLE_ARTWORK \| MACHINE_REQUIRES_ARTWORK )
	1579	COMP( 1980, tntellp, tntell, 0, tntell, tntell, tispeak_state, tntell, "Texas Instruments", "Touch & Tell (US, patent)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_CLICKABLE_ARTWORK \| MACHINE_REQUIRES_ARTWORK \| MACHINE_NOT_WORKING )
1563	1580	COMP( 1981, tntelluk, tntell, 0, tntell, tntell, tispeak_state, tntell, "Texas Instruments", "Touch & Tell (UK)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_CLICKABLE_ARTWORK \| MACHINE_REQUIRES_ARTWORK )
1564	1581	COMP( 1981, tntellfr, tntell, 0, tntell, tntell, tispeak_state, tntell, "Texas Instruments", "Le Livre Magique (France)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_CLICKABLE_ARTWORK \| MACHINE_REQUIRES_ARTWORK )
1565	1582

trunk/src/mame/drivers/vc4000.cpp
r253153	r253154
722	722	CONS(1979, krvnjvtv, 0, vc4000, vc4000, vc4000, driver_device, 0, "SOE", "OC Jeu Video TV Karvan", MACHINE_IMPERFECT_GRAPHICS ) /* France */
723	723	CONS(1979, oc2000, krvnjvtv, 0, vc4000, vc4000, driver_device, 0, "SOE", "OC-2000", MACHINE_IMPERFECT_GRAPHICS ) /* France */
724	724	CONS(1980, mpt05, 0, vc4000, vc4000, vc4000, driver_device, 0, "ITMC", "MPT-05", MACHINE_IMPERFECT_GRAPHICS ) /* France */
725		CONS(1982, h21, 0, 0, h21, vc4000, driver_device, 0, "TRQ", "Video Computer H-21", MACHINE_IMPERFECT_GRAPHICS) // Spain
	725	CONS(1982, h21, 0, vc4000, h21, vc4000, driver_device, 0, "TRQ", "Video Computer H-21", MACHINE_IMPERFECT_GRAPHICS) // Spain
726	726	CONS(1979, elektor, 0, 0, elektor, elektor, driver_device, 0, "Elektor", "Elektor TV Games Computer", MACHINE_IMPERFECT_GRAPHICS )

trunk/src/mame/drivers/vegas.cpp
r253153	r253154
493	493	UINT8 m_sio_led_state;
494	494	UINT8 m_pending_analog_read;
495	495	UINT8 m_cmos_unlocked;
496		device_t *m_voodoo;
	496	voodoo_device *m_voodoo;
497	497	UINT8 m_dcs_idma_cs;
498	498	int m_count;
499	499	int m_dynamic_count;
r253153	r253154
567	567
568	568	UINT32 vegas_state::screen_update_vegas(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
569	569	{
570		return voodoo_update(~~m_voodoo,~~ bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
	570	return m_voodoo->voodoo_update(bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
571	571	}
572	572
573	573
r253153	r253154
579	579
580	580	void vegas_state::machine_start()
581	581	{
582		m_voodoo = machine().device("voodoo");
	582	m_voodoo = (voodoo_device*)machine().device("voodoo");
583	583
584	584	/* allocate timers for the NILE */
585	585	m_timer[0] = machine().scheduler().timer_alloc(FUNC_NULL);
r253153	r253154
797	797
798	798	READ32_MEMBER( vegas_state::pci_3dfx_r )
799	799	{
800		int voodoo_type = voodoo_get_type(~~m_voodoo~~);
	800	int voodoo_type = m_voodoo->voodoo_get_type();
801	801	UINT32 result = m_pci_3dfx_regs[offset];
802	802
803	803	switch (offset)
r253153	r253154
830	830
831	831	WRITE32_MEMBER( vegas_state::pci_3dfx_w )
832	832	{
833		int voodoo_type = voodoo_get_type(~~m_voodoo~~);
	833	int voodoo_type = m_voodoo->voodoo_get_type();
834	834
835	835	m_pci_3dfx_regs[offset] = data;
836	836
r253153	r253154
869	869	break;
870	870
871	871	case 0x10: /* initEnable register */
872		voodoo_set_init_enable(~~m_voodoo,~~ data);
	872	m_voodoo->voodoo_set_init_enable(data);
873	873	break;
874	874
875	875	}
r253153	r253154
1555	1555	void vegas_state::remap_dynamic_addresses()
1556	1556	{
1557	1557	dynamic_address *dynamic = m_dynamic;
1558		int voodoo_type = voodoo_get_type(~~m_voodoo~~);
	1558	int voodoo_type = m_voodoo->voodoo_get_type();
1559	1559	offs_t base;
1560	1560	int addr;
1561	1561

trunk/src/mame/drivers/viper.cpp
r253153	r253154
435	435
436	436	UINT32 viper_state::screen_update_viper(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
437	437	{
438		device_t *device = machine().device("voodoo");
439		return voodoo_update(device, bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
	438	voodoo_device voodoo = (voodoo_device)machine().device("voodoo");
	439	return voodoo->voodoo_update(bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
440	440	}
441	441
442	442	UINT32 m_mpc8240_regs[256/4];

trunk/src/mame/includes/arkanoid.h
r253153	r253154
62	62	UINT8 m_ddr_c;
63	63	UINT8 m_tdr;
64	64	UINT8 m_tcr;
	65	emu_timer *m_68705_timer;
65	66
66
67	67	/* hexaa */
68	68	UINT8 m_hexaa_from_main;
69	69	UINT8 m_hexaa_from_sub;

trunk/src/mame/includes/chihiro.h
r253153	r253154
346	346	B8 = 9,
347	347	G8B8 = 10
348	348	};
	349	enum class NV2A_GL_FRONT_FACE {
	350	CW = 0x0900,
	351	CCW = 0x0901
	352	};
	353	enum class NV2A_GL_CULL_FACE {
	354	FRONT = 0x0404,
	355	BACK = 0x0405,
	356	FRONT_AND_BACK = 0x0408
	357	};
349	358
350	359	nv2a_renderer(running_machine &machine) : poly_manager<float, nvidia_object_data, 13, 8192>(machine)
351	360	{
r253153	r253154
363	372	indexesleft_count = 0;
364	373	vertex_pipeline = 4;
365	374	color_mask = 0xffffffff;
	375	backface_culling_enabled = false;
	376	backface_culling_winding = NV2A_GL_FRONT_FACE::CCW;
	377	backface_culling_culled = NV2A_GL_CULL_FACE::BACK;
366	378	alpha_test_enabled = false;
367	379	alpha_reference = 0;
368	380	alpha_func = NV2A_COMPARISON_OP::ALWAYS;
r253153	r253154
464	476	int read_vertices_0x1810(address_space & space, vertex_nv *destination, int offset, int limit);
465	477	int read_vertices_0x1818(address_space & space, vertex_nv *destination, UINT32 address, int limit);
466	478	void convert_vertices_poly(vertex_nv source, vertex_t destination, int count);
	479	UINT32 render_triangle_culling(const rectangle &cliprect, render_delegate callback, int paramcount, const vertex_t &_v1, const vertex_t &_v2, const vertex_t &_v3);
467	480	void clear_render_target(int what, UINT32 value);
468	481	void clear_depth_buffer(int what, UINT32 value);
469	482	inline UINT8 *direct_access_ptr(offs_t address);
r253153	r253154
630	643	std::mutex lock;
631	644	} combiner;
632	645	UINT32 color_mask;
	646	bool backface_culling_enabled;
	647	NV2A_GL_FRONT_FACE backface_culling_winding;
	648	NV2A_GL_CULL_FACE backface_culling_culled;
633	649	bool alpha_test_enabled;
634	650	NV2A_COMPARISON_OP alpha_func;
635	651	int alpha_reference;

trunk/src/mame/includes/overdriv.h
r253153	r253154
51	51	DECLARE_WRITE16_MEMBER(cpuB_ctrl_w);
52	52	DECLARE_WRITE16_MEMBER(overdriv_soundirq_w);
53	53	DECLARE_WRITE8_MEMBER(sound_ack_w);
54		DECLARE_WRITE16_MEMBER(overdriv_cpuB_irq_x_w);
55		DECLARE_WRITE16_MEMBER(overdriv_cpuB_irq_y_w);
	54	DECLARE_WRITE16_MEMBER(slave_irq4_assert_w);
	55	DECLARE_WRITE16_MEMBER(slave_irq5_assert_w);
	56	DECLARE_WRITE16_MEMBER(objdma_w);
	57	TIMER_CALLBACK_MEMBER(objdma_end_cb);
	58
56	59	virtual void machine_start() override;
57	60	virtual void machine_reset() override;
58	61	UINT32 screen_update_overdriv(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
59		INTERRUPT_GEN_MEMBER(cpuB_interrupt);
	62	//INTERRUPT_GEN_MEMBER(cpuB_interrupt);
60	63	TIMER_DEVICE_CALLBACK_MEMBER(overdriv_cpuA_scanline);
61	64	int m_fake_timer;
62	65

trunk/src/mame/machine/315-5838_317-0229_comp.cpp
r253153	r253154
4	4
5	5	315-5838 - Decathlete (ST-V)
6	6	317-0229 - Dead or Alive (Model 2A)
	7	317-0229 - Name Club Ver 2 (ST-V) (tested as RCDD2 in the service menu!)
	8	317-0231 - Print Club Love Love (ST-V)
7	9
	10	Several Print Club (ST-V) carts have
	11	an unpopulated space marked '317-0229' on the PCB
	12
8	13	Package Type: TQFP100
9	14
10		This appears to be a dual channel compression chip, used in 1996, predating the 5881.
11		Decathlete uses it to compress ALL the game graphics, Dead or Alive uses it for a
12		dumb security check, decompressing a single string.
	15	Decathlete accesses the chip at 2 different addresses, however, I don't think there
	16	are 2 channels / sets of registers, instead the 2nd set of addresses are just a
	17	mirror that allows access to a different set of source roms; the tables etc. are
	18	re-uploaded before every transfer.
13	19
14		Each channel appears to be connected to a different set of ROMs, however there is
15		defintiely only a single 315-5838 chip. (could the different channels actually just
16		be mirror addresses, with part of the address determining the ROMs to use?)
17
18		Dead of Alive only uses a single channel, and has the source data in RAM, not ROM.
	20	Dead of Alive has the source data in RAM, not ROM.
19	21	This is similar to how some 5881 games were set up, with the ST-V versions decrypting
20	22	data directly from ROM and the Model 2 ones using a RAM source buffer.
21	23
r253153	r253154
49	51
50	52	void sega_315_5838_comp_device::device_start()
51	53	{
	54	m_decathlt_lastcount = 0;
	55	m_decathlt_prot_uploadmode = 0;
	56	m_decathlt_prot_uploadoffset = 0;
	57
52	58	for (auto & elem : m_channel)
53	59	{
54		elem.m_decathlt_lastcount = 0;
55		elem.m_decathlt_prot_uploadmode = 0;
56		elem.m_decathlt_prot_uploadoffset = 0;
57	60	elem.m_read_ch.bind_relative_to(*owner());
58	61
59	62	}
r253153	r253154
61	64
62	65	void sega_315_5838_comp_device::device_reset()
63	66	{
64		for (auto & elem : m_channel)
65		{
66		elem.m_srcoffset = 0;
67		elem.m_decathlt_lastcount = 0;
68		elem.m_decathlt_prot_uploadmode = 0;
69		elem.m_decathlt_prot_uploadoffset = 0;
70		}
71
	67	m_srcoffset = 0;
	68	m_decathlt_lastcount = 0;
	69	m_decathlt_prot_uploadmode = 0;
	70	m_decathlt_prot_uploadoffset = 0;
72	71	m_protstate = 0;
73	72	}
74	73
r253153	r253154
100	99	// UINT32 fake0 = (UINT32)memregion( ":fake0" )->base();
101	100	// UINT32 retvalue = 0xffff;
102	101
103		switch (m_~~channel[channel].m_~~srcoffset)
	102	switch (m_srcoffset)
104	103	{
105	104	default:
106	105
107		m_~~channel[channel].m_~~decathlt_lastcount++;
	106	m_decathlt_lastcount++;
108	107
109	108	UINT32 tempdata = 0;
110		tempdata \|= m_channel[channel].m_read_ch(m_channel[channel].m_srcoffset) << 0;
111		m_channel[channel].m_srcoffset++;
112		tempdata \|= m_channel[channel].m_read_ch(m_channel[channel].m_srcoffset) << 16;
113		m_channel[channel].m_srcoffset++;
	109	tempdata \|= m_channel[channel].m_read_ch(m_srcoffset) << 0;
	110	m_srcoffset++;
	111	tempdata \|= m_channel[channel].m_read_ch(m_srcoffset) << 16;
	112	m_srcoffset++;
114	113
115	114
116	115	#ifdef DEBUG_DATA_DUMP
117		//printf("read addr %08x, blah_r %08x - read count count %08x\n", m_~~channel[channel].m_~~srcoffset2, tempdata, ~~m_channel[channel].~~m_decathlt_lastcount4);
	116	//printf("read addr %08x, blah_r %08x - read count count %08x\n", m_srcoffset2, tempdata, m_decathlt_lastcount4);
118	117	fwrite(&tempdata, 1, 4, tempfile);
119	118	#else
120		logerror("read addr %08x, blah_r %08x - read count count %08x\n", m_~~channel[channel].m_~~srcoffset2, tempdata, ~~m_channel[channel].~~m_decathlt_lastcount4);
	119	logerror("read addr %08x, blah_r %08x - read count count %08x\n", m_srcoffset2, tempdata, m_decathlt_lastcount4);
121	120	#endif
122	121
123	122	return tempdata;
124	123	#if 0
125	124	case 0x03228e4:
126		if (fake0) retvalue = fake0[(((0x20080/4)+m_channel[channel].m_decathlt_lastcount))];
127		m_channel[channel].m_decathlt_lastcount++;
	125	if (fake0) retvalue = fake0[(((0x20080/4)+m_decathlt_lastcount))];
	126	m_decathlt_lastcount++;
128	127	return retvalue;
129	128
130	129	case 0x00a9f3a:
131		if (fake0) retvalue = fake0[(((0x00000/4)+m_channel[channel].m_decathlt_lastcount))];
132		m_channel[channel].m_decathlt_lastcount++;
	130	if (fake0) retvalue = fake0[(((0x00000/4)+m_decathlt_lastcount))];
	131	m_decathlt_lastcount++;
133	132	return retvalue;
134	133
135	134	case 0x0213ab4:
136		if (fake0) retvalue = fake0[(((0x40000/4)+m_channel[channel].m_decathlt_lastcount))];
137		m_channel[channel].m_decathlt_lastcount++;
	135	if (fake0) retvalue = fake0[(((0x40000/4)+m_decathlt_lastcount))];
	136	m_decathlt_lastcount++;
138	137	return retvalue;
139	138
140	139	case 0x01efaf0:
141		if (fake0) retvalue = fake0[(((0x60000/4)+m_channel[channel].m_decathlt_lastcount))];
142		m_channel[channel].m_decathlt_lastcount++;
	140	if (fake0) retvalue = fake0[(((0x60000/4)+m_decathlt_lastcount))];
	141	m_decathlt_lastcount++;
143	142	return retvalue;
144	143
145	144	case 0x033f16c:
r253153	r253154
180	179	void sega_315_5838_comp_device::set_prot_addr(UINT32 data, UINT32 mem_mask, int channel)
181	180	{
182	181	// printf("set_prot_addr\n");
183		COMBINE_DATA(&m_~~channel[channel].m_~~srcoffset);
	182	COMBINE_DATA(&m_srcoffset);
184	183
185		//if (m_decathlt_part==0) logerror("%d, last read count was %06x\n",channel, m_channel[channel].m_decathlt_lastcount*4);
186		m_channel[channel].m_decathlt_lastcount = 0;
	184	//if (m_decathlt_part==0) logerror("%d, last read count was %06x\n",channel, m_decathlt_lastcount*4);
	185	m_decathlt_lastcount = 0;
187	186
188	187	if (mem_mask == 0x0000ffff)
189	188	{
190		printf("set source address to %08x (channel %d)\n", m_~~channel[channel].m_~~srcoffset, channel);
	189	printf("set source address to %08x (channel %d)\n", m_srcoffset, channel);
191	190	}
192	191
193	192
r253153	r253154
198	197	fclose(tempfile);
199	198
200	199	char filename[256];
201		sprintf(filename, "%d_compressed_%08x", channel, m_~~channel[channel].m_~~srcoffset * 2);
	200	sprintf(filename, "%d_compressed_%08x", channel, m_srcoffset * 2);
202	201	tempfile = fopen(filename, "w+b");
203	202
204	203	// the table and dictionary are uploaded repeatedly, usually before groups of data transfers but
205	204	// it's always the same tables (one pair for each channel)
206	205	{
207	206	FILE* fp;
208		sprintf(filename, "%d_compressed_table1", channel);
	207	sprintf(filename, "%d_compressed_table1_%08x", channel, m_srcoffset * 2);
209	208	fp = fopen(filename, "w+b");
210		fwrite(&m_~~channel[channel].m_~~decathlt_prottable1, 24, 2, fp);
	209	fwrite(&m_decathlt_prottable1, 24, 2, fp);
211	210	fclose(fp);
212	211	}
213	212
214	213	{
215	214	FILE* fp;
216		sprintf(filename, "%d_compressed_dictionary", channel);
	215	sprintf(filename, "%d_compressed_dictionary_%08x", channel, m_srcoffset * 2);
217	216	fp = fopen(filename, "w+b");
218		fwrite(&m_~~channel[channel].m_~~decathlt_dictionary, 128, 2, fp);
	217	fwrite(&m_decathlt_dictionaryy, 128, 2, fp);
219	218	fclose(fp);
220	219	}
221	220	}
r253153	r253154
228	227	if ((data == 0x8000) \|\| (data == 0x0000))
229	228	{
230	229	// logerror("changed to upload mode 1\n");
231		m_channel[channel].m_decathlt_prot_uploadmode = 1;
232		m_channel[channel].m_decathlt_prot_uploadoffset = 0;
	230	m_decathlt_prot_uploadmode = 1;
	231	m_decathlt_prot_uploadoffset = 0;
233	232	}
234	233	else if ((data == 0x8080) \|\| (data == 0x0080))
235	234	{
236		m_channel[channel].m_decathlt_prot_uploadmode = 2;
237		m_channel[channel].m_decathlt_prot_uploadoffset = 0;
	235	m_decathlt_prot_uploadmode = 2;
	236	m_decathlt_prot_uploadoffset = 0;
238	237	}
239	238	else
240	239	{
r253153	r253154
244	243
245	244	void sega_315_5838_comp_device::upload_table_data(UINT16 data, int channel)
246	245	{
247		if (m_~~channel[channel].m_~~decathlt_prot_uploadmode == 1)
	246	if (m_decathlt_prot_uploadmode == 1)
248	247	{
249		if (m_~~channel[channel].m_~~decathlt_prot_uploadoffset >= 24)
	248	if (m_decathlt_prot_uploadoffset >= 24)
250	249	{
251	250	fatalerror("upload mode 1 error, too big\n");
252	251	return;
253	252	}
254	253
255		//logerror("uploading table 1 %04x %04x\n",m_channel[channel].m_decathlt_prot_uploadoffset, data&0xffff);
256		m_channel[channel].m_decathlt_prottable1[m_channel[channel].m_decathlt_prot_uploadoffset] = data & 0xffff;
257		m_channel[channel].m_decathlt_prot_uploadoffset++;
	254	//logerror("uploading table 1 %04x %04x\n",m_decathlt_prot_uploadoffset, data&0xffff);
	255	m_decathlt_prottable1[m_decathlt_prot_uploadoffset] = data & 0xffff;
	256	m_decathlt_prot_uploadoffset++;
258	257	printf("unk table 1 %04x (channel %d)\n", data & 0xffff, channel);
259	258	}
260		else if (m_~~channel[channel].m_~~decathlt_prot_uploadmode == 2)
	259	else if (m_decathlt_prot_uploadmode == 2)
261	260	{
262		if (m_~~channel[channel].m_~~decathlt_prot_uploadoffset >= 128)
	261	if (m_decathlt_prot_uploadoffset >= 128)
263	262	{
264	263	fatalerror("upload mode 2 error, too big\n");
265	264	return;
266	265	}
267	266
268		//logerror("uploading table 2 %04x %04x\n",m_channel[channel].m_decathlt_prot_uploadoffset, data&0xffff);
269		m_channel[channel].m_decathlt_dictionary[m_channel[channel].m_decathlt_prot_uploadoffset] = data & 0xffff;
270		m_channel[channel].m_decathlt_prot_uploadoffset++;
	267	//logerror("uploading table 2 %04x %04x\n",m_decathlt_prot_uploadoffset, data&0xffff);
	268	m_decathlt_dictionaryy[m_decathlt_prot_uploadoffset] = data & 0xffff;
	269	m_decathlt_prot_uploadoffset++;
271	270	printf("dictionary %04x (channel %d)\n", data & 0xffff, channel);
272	271	}
273	272	}

trunk/src/mame/machine/315-5838_317-0229_comp.h
r253153	r253154
65	65	virtual void device_reset() override;
66	66
67	67	private:
	68	UINT16 m_decathlt_prottable1[24];
	69	UINT16 m_decathlt_dictionaryy[128];
68	70
	71	UINT32 m_srcoffset;
	72
	73	UINT32 m_decathlt_lastcount;
	74	UINT32 m_decathlt_prot_uploadmode;
	75	UINT32 m_decathlt_prot_uploadoffset;
	76
	77
69	78	// Decathlete specific variables and functions (see machine/decathlt.c)
70	79	struct channel_type
71	80	{
72		UINT32 m_srcoffset;
73		UINT16 m_decathlt_prottable1[24];
74		UINT16 m_decathlt_dictionary[128];
75
76		UINT32 m_decathlt_lastcount;
77		UINT32 m_decathlt_prot_uploadmode;
78		UINT32 m_decathlt_prot_uploadoffset;
79	81	sega_dec_read_delegate m_read_ch;
80	82
81	83	};

trunk/src/mame/machine/arkanoid.cpp
r253153	r253154
82	82	if ((m_tcr^data)&0x20)// check if TIN state changed
83	83	{
84	84	/* logerror("timer enable state changed!\n"); */
85		if (data&0x20) timer_set(attotime::never, TIMER_68705_PRESCALER_EXPIRED);
86		else timer_set(attotime::from_hz(((XTAL_12MHz/4)/4)/(1<<(data&0x7))), TIMER_68705_PRESCALER_EXPIRED);
	85	if (data&0x20) m_68705_timer->adjust(attotime::never, TIMER_68705_PRESCALER_EXPIRED);
	86	else m_68705_timer->adjust(attotime::from_hz(((XTAL_12MHz/4)/4)/(1<<(data&0x7))), TIMER_68705_PRESCALER_EXPIRED);
87	87	}
88	88	// prescaler check: if timer prescaler has changed, or the PSC bit is set, adjust the timer length for the prescaler expired timer, but only if the timer would be running
89	89	if ( (((m_tcr&0x07)!=(data&0x07))\|\|(data&0x08)) && ((data&0x20)==0) )
90	90	{
91	91	/* logerror("timer reset due to PSC or prescaler change!\n"); */
92		timer_set(attotime::from_hz(((XTAL_12MHz/4)/4)/(1<<(data&0x7))), TIMER_68705_PRESCALER_EXPIRED);
	92	m_68705_timer->adjust(attotime::from_hz(((XTAL_12MHz/4)/4)/(1<<(data&0x7))), TIMER_68705_PRESCALER_EXPIRED);
93	93	}
94	94	m_tcr = data;
95	95	// if int state is set, and TIM is unmasked, assert an interrupt. otherwise clear it.
r253153	r253154
120	120	m_mcu->set_input_line(M68705_INT_TIMER, ASSERT_LINE);
121	121	else
122	122	m_mcu->set_input_line(M68705_INT_TIMER, CLEAR_LINE);
123		timer_set(attotime::from_hz(((XTAL_12MHz/4)/4)/(1<<(m_tcr&0x7))), TIMER_68705_PRESCALER_EXPIRED);
	123	m_68705_timer->adjust(attotime::from_hz(((XTAL_12MHz/4)/4)/(1<<(m_tcr&0x7))), TIMER_68705_PRESCALER_EXPIRED);
124	124	}
125	125
126	126	READ8_MEMBER(arkanoid_state::arkanoid_68705_port_c_r)

trunk/src/mame/machine/pc9801_cd.cpp
r0	r253154
	1	// license:BSD-3-Clause
	2	// copyright-holders:smf
	3	#include "pc9801_cd.h"
	4
	5	// device type definition
	6	const device_type PC9801_CD = &device_creator<pc9801_cd_device>;
	7
	8	pc9801_cd_device::pc9801_cd_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
	9	atapi_cdrom_device(mconfig, PC9801_CD, "PC9801 CD-ROM Drive", tag, owner, clock, "pc9801_cd", __FILE__)
	10	{
	11	}
	12
	13	void pc9801_cd_device::fill_buffer()
	14	{
	15	atapi_hle_device::fill_buffer();
	16	m_status \|= IDE_STATUS_DRDY \| IDE_STATUS_SERV;
	17	}
	18
	19	void pc9801_cd_device::process_buffer()
	20	{
	21	atapi_hle_device::process_buffer();
	22	m_status \|= IDE_STATUS_DRDY \| IDE_STATUS_SERV;
	23	}
	24
	25	void pc9801_cd_device::process_command()
	26	{
	27	atapi_hle_device::process_command();
	28	switch(m_command)
	29	{
	30	case IDE_COMMAND_CHECK_POWER_MODE:
	31	m_status = IDE_STATUS_DRDY \| IDE_STATUS_SERV;
	32	break;
	33	}
	34	}

trunk/src/mame/machine/pc9801_cd.h
r0	r253154
	1	// license:BSD-3-Clause
	2	// copyright-holders:smf
	3
	4	#ifndef __PC9801_CD_H__
	5	#define __PC9801_CD_H__
	6
	7	#include "machine/atapicdr.h"
	8
	9	class pc9801_cd_device : public atapi_cdrom_device
	10	{
	11	public:
	12	pc9801_cd_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	13
	14	protected:
	15	virtual void fill_buffer() override;
	16	virtual void process_command() override;
	17	virtual void process_buffer() override;
	18	};
	19
	20	// device type definition
	21	extern const device_type PC9801_CD;
	22
	23	#endif

trunk/src/mame/machine/pc9801_kbd.cpp
r253153	r253154
257	257
258	258	m_keyb_tx = 0xff;
259	259	m_keyb_rx = 0;
	260	m_key_avail = false;
260	261	}
261	262
262	263	//-------------------------------------------------
r253153	r253154
276	277	{
277	278	m_keyb_tx = i \| 0x80;
278	279	m_write_irq(ASSERT_LINE);
	280	m_key_avail = true;
279	281	m_rx_buf[i] = 0;
280	282	return;
281	283	}
r253153	r253154
288	290	{
289	291	m_keyb_tx = i;
290	292	m_write_irq(ASSERT_LINE);
	293	m_key_avail = true;
291	294	m_rx_buf[i] = 0;
292	295	return;
293	296	}
r253153	r253154
303	306	{
304	307	m_write_irq(CLEAR_LINE);
305	308	if(!offset)
	309	{
	310	m_key_avail = false;
306	311	return m_keyb_tx;
307		return 1 \| 4 \| 2;
	312	}
	313	return 1 \| 4 \| (m_key_avail ? 2 : 0);
308	314	}
309	315
310	316	WRITE8_MEMBER( pc9801_kbd_device::tx_w )

trunk/src/mame/machine/pc9801_kbd.h
r253153	r253154
55	55	UINT8 m_rx_buf[0x80];
56	56	UINT8 m_keyb_tx;
57	57	UINT8 m_keyb_rx;
	58	bool m_key_avail;
58	59	};
59	60
60	61

trunk/src/mame/mess.lst
r253153	r253154
2142	2142
2143	2143	// Fidelity
2144	2144	cc10
	2145	cc7
2145	2146	vcc // VCC: Voice Chess Challenger (English)
2146	2147	vccg // * Spanish
2147	2148	vccfr // * German
r253153	r253154
2344	2345	snspellca
2345	2346	snspellcuk
2346	2347	snmath
	2348	snmatha
2347	2349	snmathp
2348	2350	snread
2349	2351	lantutor

trunk/src/mame/video/chihiro.cpp
r253153	r253154
2549	2549	}
2550	2550	}
2551	2551
	2552	UINT32 nv2a_renderer::render_triangle_culling(const rectangle &cliprect, render_delegate callback, int paramcount, const vertex_t &_v1, const vertex_t &_v2, const vertex_t &_v3)
	2553	{
	2554	float areax2;
	2555
	2556	if (backface_culling_enabled == false)
	2557	return render_triangle(cliprect, callback, paramcount, _v1, _v2, _v3);
	2558	if (backface_culling_culled == NV2A_GL_CULL_FACE::FRONT_AND_BACK)
	2559	return 0;
	2560	areax2 = _v1.x(_v2.y - _v3.y) + _v2.x(_v3.y - _v1.y) + _v3.x*(_v1.y - _v2.y);
	2561	if (backface_culling_winding == NV2A_GL_FRONT_FACE::CCW)
	2562	areax2 = -areax2;
	2563	// if areax2 >= 0 then front faced else back faced
	2564	if ((backface_culling_culled == NV2A_GL_CULL_FACE::FRONT) && (areax2 >= 0))
	2565	return 0;
	2566	if ((backface_culling_culled == NV2A_GL_CULL_FACE::BACK) && (areax2 < 0))
	2567	return 0;
	2568	return render_triangle(cliprect, callback, paramcount, _v1, _v2, _v3);
	2569	}
	2570
2552	2571	int nv2a_renderer::geforce_exec_method(address_space & space, UINT32 chanel, UINT32 subchannel, UINT32 method, UINT32 address, int &countlen)
2553	2572	{
2554	2573	UINT32 maddress;
r253153	r253154
2592	2611	for (n = 0; n <= count; n += 4) {
2593	2612	read_vertices_0x1810(space, vertex_software + vertex_first, n + offset, 4);
2594	2613	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 4);
2595		render_polygon<4>(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy + vertex_first); // 4 rgba, 4 texture units 2 uv
	2614	//render_polygon<4>(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy + vertex_first); // 4 rgba, 4 texture units 2 uv
	2615	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[vertex_first + 1], vertex_xy[vertex_first + 2]);
	2616	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[vertex_first + 2], vertex_xy[vertex_first + 3]);
2596	2617	vertex_first = (vertex_first + 4) & 1023;
2597	2618	vertex_count = vertex_count + 4;
2598	2619	wait();
r253153	r253154
2602	2623	for (n = 0; n <= count; n += 3) {
2603	2624	read_vertices_0x1810(space, vertex_software + vertex_first, n + offset, 3);
2604	2625	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 3);
2605		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[(vertex_first + 1) & 1023], vertex_xy[(vertex_first + 2) & 1023]); // 4 rgba, 4 texture units 2 uv
	2626	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[(vertex_first + 1) & 1023], vertex_xy[(vertex_first + 2) & 1023]); // 4 rgba, 4 texture units 2 uv
2606	2627	vertex_first = (vertex_first + 3) & 1023;
2607	2628	vertex_count = vertex_count + 3;
2608	2629	wait();
r253153	r253154
2624	2645	for (n = 0; n <= count; n++) {
2625	2646	read_vertices_0x1810(space, vertex_software + vertex_first, offset + n, 1);
2626	2647	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 1);
2627		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[1024], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
	2648	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[1024], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
2628	2649	vertex_first = (vertex_first + 1) & 1023;
2629	2650	vertex_count = vertex_count + 1;
2630	2651	wait();
r253153	r253154
2645	2666	read_vertices_0x1810(space, vertex_software + vertex_first, offset + n, 1);
2646	2667	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 1);
2647	2668	if ((vertex_count & 1) == 0)
2648		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
	2669	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
2649	2670	else
2650		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[vertex_first], vertex_xy[(vertex_first - 1) & 1023]);
	2671	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[vertex_first], vertex_xy[(vertex_first - 1) & 1023]);
2651	2672	vertex_first = (vertex_first + 1) & 1023;
2652	2673	vertex_count = vertex_count + 1;
2653	2674	wait();
r253153	r253154
2691	2712	address = address + c * 4;
2692	2713	countlen = countlen - c;
2693	2714	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 4);
2694		render_polygon<4>(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy + vertex_first); // 4 rgba, 4 texture units 2 uv
	2715	//render_polygon<4>(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy + vertex_first); // 4 rgba, 4 texture units 2 uv
	2716	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[vertex_first + 1], vertex_xy[vertex_first + 2]);
	2717	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[vertex_first + 2], vertex_xy[vertex_first + 3]);
2695	2718	vertex_first = (vertex_first + 4) & 1023;
2696	2719	vertex_count = vertex_count + 4;
2697	2720	wait();
r253153	r253154
2733	2756	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 1);
2734	2757	address = address + c * 4;
2735	2758	countlen = countlen - c;
2736		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[1024], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
	2759	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[1024], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
2737	2760	vertex_first = (vertex_first + 1) & 1023;
2738	2761	vertex_count = vertex_count + 1;
2739	2762	wait();
r253153	r253154
2753	2776	address = address + c * 4;
2754	2777	countlen = countlen - c;
2755	2778	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 3);
2756		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[(vertex_first + 1) & 1023], vertex_xy[(vertex_first + 2) & 1023]); // 4 rgba, 4 texture units 2 uv
	2779	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[(vertex_first + 1) & 1023], vertex_xy[(vertex_first + 2) & 1023]); // 4 rgba, 4 texture units 2 uv
2757	2780	vertex_first = (vertex_first + 3) & 1023;
2758	2781	vertex_count = vertex_count + 3;
2759	2782	wait();
r253153	r253154
2789	2812	countlen = countlen - c;
2790	2813	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 1);
2791	2814	if ((vertex_count & 1) == 0)
2792		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
	2815	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
2793	2816	else
2794		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[vertex_first], vertex_xy[(vertex_first - 1) & 1023]);
	2817	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[vertex_first], vertex_xy[(vertex_first - 1) & 1023]);
2795	2818	vertex_first = (vertex_first + 1) & 1023;
2796	2819	vertex_count = vertex_count + 1;
2797	2820	wait();
r253153	r253154
2849	2872	break;
2850	2873	}
2851	2874	address = address + c * 4;
2852		render_polygon<4>(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy); // 4 rgba, 4 texture units 2 uv
	2875	//render_polygon<4>(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy); // 4 rgba, 4 texture units 2 uv
	2876	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[vertex_first + 1], vertex_xy[vertex_first + 2]);
	2877	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[vertex_first + 2], vertex_xy[vertex_first + 3]);
2853	2878	vertex_first = (vertex_first + 4) & 1023;
2854	2879	vertex_count = vertex_count + 4;
2855	2880	wait();
r253153	r253154
2877	2902	return 0;
2878	2903	}
2879	2904	address = address + c * 4;
2880		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[n & 3], vertex_xy[(n + 1) & 3], vertex_xy[(n + 2) & 3]);
2881		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(n + 2) & 3], vertex_xy[(n + 1) & 3], vertex_xy[(n + 3) & 3]);
	2905	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[n & 3], vertex_xy[(n + 1) & 3], vertex_xy[(n + 2) & 3]);
	2906	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(n + 2) & 3], vertex_xy[(n + 1) & 3], vertex_xy[(n + 3) & 3]);
2882	2907	wait();
2883	2908	}
2884	2909	}
r253153	r253154
2914	2939	}
2915	2940	address = address + c * 4;
2916	2941	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 1);
2917		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[1024], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
	2942	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[1024], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
2918	2943	vertex_first = (vertex_first + 1) & 1023;
2919	2944	vertex_count = vertex_count + 1;
2920	2945	wait();
r253153	r253154
2933	2958	break;
2934	2959	}
2935	2960	address = address + c * 4;
2936		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[(vertex_first + 1) & 1023], vertex_xy[(vertex_first + 2) & 1023]); // 4 rgba, 4 texture units 2 uv
	2961	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[(vertex_first + 1) & 1023], vertex_xy[(vertex_first + 2) & 1023]); // 4 rgba, 4 texture units 2 uv
2937	2962	vertex_first = (vertex_first + 3) & 1023;
2938	2963	vertex_count = vertex_count + 3;
2939	2964	wait();
r253153	r253154
2968	2993	}
2969	2994	address = address + c * 4;
2970	2995	if ((vertex_count & 1) == 0)
2971		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
	2996	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
2972	2997	else
2973		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[vertex_first], vertex_xy[(vertex_first - 1) & 1023]);
	2998	render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[vertex_first], vertex_xy[(vertex_first - 1) & 1023]);
2974	2999	vertex_first = (vertex_first + 1) & 1023;
2975	3000	vertex_count = vertex_count + 1;
2976	3001	wait();
r253153	r253154
3028	3053	}
3029	3054	if ((maddress == 0x1d6c) \|\| (maddress == 0x1d70) \|\| (maddress == 0x1a4))
3030	3055	countlen--;
	3056	if (maddress == 0x0308) {
	3057	backface_culling_enabled = data != 0 ? true : false;
	3058	}
	3059	if (maddress == 0x03a0) {
	3060	backface_culling_winding = (NV2A_GL_FRONT_FACE)data;
	3061	}
	3062	if (maddress == 0x039c) {
	3063	backface_culling_culled = (NV2A_GL_CULL_FACE)data;
	3064	}
3031	3065	if (maddress == 0x019c) {
3032	3066	geforce_read_dma_object(data, dma_offset[0], dma_size[0]);
3033	3067	}

https://github.com/mamedev/mame/commit/f80737595e3579a86d064cc869ed9682e28a782b

199869 Revisions