MAME SVN History

199869 Revisions

r44640 Monday 1st February, 2016 at 22:54:57 UTC by Brandon Munger
r9751: Added more dma registers for serial and floppy

[/trunk]	makefile
[scripts/src]	3rdparty.lua
[scripts/target/mame]	mess.lua
[src/devices/bus/a2bus]	a2pic.cpp
[src/devices/bus/centronics]	epson_lx810l.cpp
[src/devices/machine]	i8271.cpp i8271.h k033906.cpp k033906.h
[src/devices/video]	vooddefs.h voodoo.cpp voodoo.h voodoo_pci.cpp
[src/emu]	emuopts.cpp
[src/mame]	arcade.lst mess.lst
[src/mame/drivers]	arkanoid.cpp esd16.cpp fidelz80.cpp funkball.cpp gticlub.cpp hornet.cpp kaneko16.cpp ladyfrog.cpp magictg.cpp nibble.cpp nwk-tr.cpp overdriv.cpp pc9801.cpp r9751.cpp savquest.cpp seattle.cpp stv.cpp tispeak.cpp vc4000.cpp vegas.cpp viper.cpp
[src/mame/includes]	arkanoid.h chihiro.h overdriv.h
[src/mame/machine]	315-5838_317-0229_comp.cpp 315-5838_317-0229_comp.h arkanoid.cpp ~~pc9801_cd.cpp~~ ~~pc9801_cd.h~~ pc9801_kbd.cpp pc9801_kbd.h
[src/mame/video]	chihiro.cpp

trunk/makefile
r253151	r253152
1267	1267	$(SILENT)$(PYTHON) scripts/build/file2str.py $< $@ layout_$(basename $(notdir $<))
1268	1268
1269	1269	$(SRC)/devices/cpu/m68000/m68kops.cpp: $(SRC)/devices/cpu/m68000/m68k_in.cpp $(SRC)/devices/cpu/m68000/m68kmake.cpp
1270		ifeq ($(TARGETOS),asmjs)
1271		$(SILENT) $(MAKE) -C $(SRC)/devices/cpu/m68000
1272		else
1273	1270	$(SILENT) $(MAKE) -C $(SRC)/devices/cpu/m68000 CC=$(CC) CXX=$(CXX)
1274		endif
1275	1271
1276	1272	#-------------------------------------------------
1277	1273	# Regression tests

trunk/scripts/src/3rdparty.lua
r253151	r253152
967	967	"/wd4210", -- warning C4210: nonstandard extension used : function given file scope
968	968	"/wd4701", -- warning C4701: potentially uninitialized local variable 'xxx' used
969	969	"/wd4703", -- warning C4703: potentially uninitialized local pointer variable 'xxx' used
970		"/wd4477", -- warning C4477: '<function>' : format string '<format-string>' requires an argument of type '<type>', but variadic argument <position> has type '<type>'
971	970	}
972	971
973	972	configuration { }

trunk/scripts/target/mame/mess.lua
r253151	r253152
2090	2090	MAME_DIR .. "src/mame/machine/pc9801_cbus.h",
2091	2091	MAME_DIR .. "src/mame/machine/pc9801_kbd.cpp",
2092	2092	MAME_DIR .. "src/mame/machine/pc9801_kbd.h",
2093		MAME_DIR .. "src/mame/machine/pc9801_cd.cpp",
2094		MAME_DIR .. "src/mame/machine/pc9801_cd.h",
2095	2093	MAME_DIR .. "src/mame/drivers/tk80bs.cpp",
2096	2094	MAME_DIR .. "src/mame/drivers/hh_ucom4.cpp",
2097	2095	MAME_DIR .. "src/mame/includes/hh_ucom4.h",

trunk/src/devices/bus/a2bus/a2pic.cpp
r253151	r253152
49	49	PORT_DIPSETTING( 0x06, "13 microseconds" )
50	50	PORT_DIPSETTING( 0x07, "15 microseconds" )
51	51
52		PORT_DIPNAME( 0x08, 0x08, "Strobe polarity (SW4)" )
	52	PORT_DIPNAME( 0x08, 0x00, "Strobe polarity (SW4)" )
53	53	PORT_DIPSETTING( 0x00, "Positive" )
54	54	PORT_DIPSETTING( 0x08, "Negative" )
55	55
56		PORT_DIPNAME( 0x10, 0x10, "Acknowledge polarity (SW5)" )
	56	PORT_DIPNAME( 0x10, 0x00, "Acknowledge polarity (SW5)" )
57	57	PORT_DIPSETTING( 0x00, "Positive" )
58	58	PORT_DIPSETTING( 0x10, "Negative" )
59	59
r253151	r253152
181	181
182	182	UINT8 a2bus_pic_device::read_c0nx(address_space &space, UINT8 offset)
183	183	{
184		UINT8 rv = 0;
185
186	184	switch (offset)
187	185	{
188	186	case 3:
189	187	return m_ctx_data_in->read();
190	188
191	189	case 4:
192		r~~v =~~ m_ack;
	190	return m_ack;
193	191
194		// clear flip-flop
195		if (m_dsw1->read() & 0x10) // negative polarity
196		{
197		m_ack \|= 0x80;
198		}
199		else
200		{
201		m_ack &= ~0x80;
202		}
203
204		return rv;
205
206	192	case 6: // does reading this really work?
207	193	m_irqenable = true;
208	194	break;

trunk/src/devices/bus/centronics/epson_lx810l.cpp
r253151	r253152
26	26	*/
27	27
28	28	#include "epson_lx810l.h"
29		//extern const char layout_lx800[]; /* use layout from lx800 */
	29	extern const char layout_lx800[]; /* use layout from lx800 */
30	30
31	31	//#define LX810LDEBUG
32	32	#ifdef LX810LDEBUG
r253151	r253152
132	132	MCFG_UPD7810_CO0(WRITELINE(epson_lx810l_t, co0_w))
133	133	MCFG_UPD7810_CO1(WRITELINE(epson_lx810l_t, co1_w))
134	134
135		// MCFG_DEFAULT_LAYOUT(layout_lx800)
	135	MCFG_DEFAULT_LAYOUT(layout_lx800)
136	136
137	137	/* video hardware (simulates paper) */
138	138	MCFG_SCREEN_ADD("screen", RASTER)

trunk/src/devices/machine/i8271.cpp
r253151	r253152
88	88	flopi[i].live = false;
89	89	flopi[i].ready = get_ready(i);
90	90	}
91		hdl_cb(false);
92	91	set_irq(false);
93	92	set_drq(false);
94	93	command_pos = 0;
r253151	r253152
888	887	{
889	888	logerror("%s: command done (%s) - %02x\n", tag(), data_completion ? "data" : "seek", rr);
890	889	fi.main_state = fi.sub_state = IDLE;
891		idle_icnt = 0;
892	890	main_phase = PHASE_RESULT;
893	891	set_irq(true);
894	892	}
r253151	r253152
983	981	void i8271_device::read_data_start(floppy_info &fi)
984	982	{
985	983	fi.main_state = READ_DATA;
986		hdl_cb(true);
987	984	fi.sub_state = HEAD_LOAD_DONE;
988	985
989	986	logerror("%s: command read%s data%s cmd=%02x crn=(%d, %d, %d) len=%02x rate=%d\n",
r253151	r253152
1013	1010	void i8271_device::scan_start(floppy_info &fi)
1014	1011	{
1015	1012	fi.main_state = SCAN_DATA;
1016		hdl_cb(true);
1017	1013	fi.sub_state = HEAD_LOAD_DONE;
1018	1014
1019	1015	logerror("%s: command scan%s data%s cmd=%02x crn=(%d, %d, %d) len=%02x rate=%d\n",
r253151	r253152
1045	1041	void i8271_device::verify_data_start(floppy_info &fi)
1046	1042	{
1047	1043	fi.main_state = VERIFY_DATA;
1048		hdl_cb(true);
1049	1044	fi.sub_state = HEAD_LOAD_DONE;
1050	1045
1051	1046	logerror("%s: command verify%s data%s cmd=%02x crn=(%d, %d, %d) len=%02x rate=%d\n",
r253151	r253152
1103	1098	return;
1104	1099
1105	1100	case SEEK_WAIT_STEP_TIME_DONE:
1106		hdl_cb(true);
1107	1101	do {
1108	1102	if(fi.pcn > command[1])
1109	1103	fi.pcn--;
r253151	r253152
1187	1181	void i8271_device::write_data_start(floppy_info &fi)
1188	1182	{
1189	1183	fi.main_state = WRITE_DATA;
1190		hdl_cb(true);
1191	1184	fi.sub_state = HEAD_LOAD_DONE;
1192
1193	1185	logerror("%s: command write%s data%s cmd=%02x crn=(%d, %d, %d) len=%02x rate=%d\n",
1194	1186	tag(),
1195	1187	command[0] & 0x04 ? " deleted" : "",
r253151	r253152
1246	1238	return;
1247	1239
1248	1240	case SEEK_WAIT_STEP_TIME_DONE:
1249		hdl_cb(true);
1250	1241	do {
1251	1242	if(fi.pcn > command[1])
1252	1243	fi.pcn--;
r253151	r253152
1320	1311	void i8271_device::format_track_start(floppy_info &fi)
1321	1312	{
1322	1313	fi.main_state = FORMAT_TRACK;
1323		hdl_cb(true);
1324	1314	fi.sub_state = HEAD_LOAD_DONE;
1325	1315
1326	1316	logerror("%s: command format track c=%02x n=%02x sc=%02x gap3=%02x gap5=%02x gap1=%02x\n",
r253151	r253152
1374	1364	return;
1375	1365
1376	1366	case SEEK_WAIT_STEP_TIME_DONE:
1377		hdl_cb(true);
1378	1367	do {
1379	1368	if(fi.pcn > command[1])
1380	1369	fi.pcn--;
r253151	r253152
1413	1402	void i8271_device::read_id_start(floppy_info &fi)
1414	1403	{
1415	1404	fi.main_state = READ_ID;
1416		hdl_cb(true);
1417	1405	fi.sub_state = HEAD_LOAD_DONE;
1418	1406
1419	1407	logerror("%s: command read id, rate=%d\n",
r253151	r253152
1469	1457	return;
1470	1458
1471	1459	case SEEK_WAIT_STEP_TIME_DONE:
1472		hdl_cb(true);
1473	1460	do {
1474	1461	if(fi.pcn > command[1])
1475	1462	fi.pcn--;
r253151	r253152
1566	1553	continue;
1567	1554	}
1568	1555
1569		if (fi.main_state == IDLE) {
1570		idle_icnt++;
1571		if (icnt != 0x0f && idle_icnt >= icnt) {
1572		hdl_cb(false);
1573		}
1574		}
1575
1576	1556	switch(fi.sub_state) {
1577	1557	case IDLE:
1578	1558	case SEEK_MOVE:

trunk/src/devices/machine/i8271.h
r253151	r253152
215	215	UINT8 srate, hset, icnt, hload;
216	216	int sector_size;
217	217	int cur_rate;
218		int idle_icnt;
219	218
220	219	static std::string tts(attotime t);
221	220	std::string ttsn();

trunk/src/devices/machine/k033906.cpp
r253151	r253152
33	33
34	34	void k033906_device::device_start()
35	35	{
36		m_voodoo = ~~(voodoo_device*)~~machine().device(m_voodoo_tag);
	36	m_voodoo = machine().device(m_voodoo_tag);
37	37
38	38	m_reg_set = 0;
39	39
r253151	r253152
95	95
96	96	case 0x10: // initEnable
97	97	{
98		m_voodoo~~->voodoo~~_set_init_enable(data);
	98	voodoo_set_init_enable(m_voodoo, data);
99	99	break;
100	100	}
101	101

trunk/src/devices/machine/k033906.h
r253151	r253152
12	12	#define __K033906_H__
13	13
14	14	#include "emu.h"
15		#include "video/voodoo.h"
16	15
17	16
	17
18	18	/***************************************************************************
19	19	DEVICE CONFIGURATION MACROS
20	20	***************************************************************************/
r253151	r253152
58	58	int m_reg_set; // 1 = access reg / 0 = access ram
59	59
60	60	const char *m_voodoo_tag;
61		~~voo~~d~~oo_d~~evice *m_voodoo;
	61	device_t *m_voodoo;
62	62
63	63	UINT32 m_reg[256];
64	64	UINT32 m_ram[32768];

trunk/src/devices/video/vooddefs.h
r253151	r253152
9	9	***************************************************************************/
10	10
11	11
	12	/*************************************
	13	*
	14	* Misc. constants
	15	*
	16	*************************************/
12	17
	18	/* enumeration describing reasons we might be stalled */
	19	enum
	20	{
	21	NOT_STALLED = 0,
	22	STALLED_UNTIL_FIFO_LWM,
	23	STALLED_UNTIL_FIFO_EMPTY
	24	};
13	25
	26
	27
	28	// Use old table lookup versus straight double divide
	29	#define USE_FAST_RECIP 0
	30
	31	/* maximum number of TMUs */
	32	#define MAX_TMU 2
	33
	34	/* accumulate operations less than this number of clocks */
	35	#define ACCUMULATE_THRESHOLD 0
	36
	37	/* number of clocks to set up a triangle (just a guess) */
	38	#define TRIANGLE_SETUP_CLOCKS 100
	39
	40	/* maximum number of rasterizers */
	41	#define MAX_RASTERIZERS 1024
	42
	43	/* size of the rasterizer hash table */
	44	#define RASTER_HASH_SIZE 97
	45
	46	/* flags for LFB writes */
	47	#define LFB_RGB_PRESENT 1
	48	#define LFB_ALPHA_PRESENT 2
	49	#define LFB_DEPTH_PRESENT 4
	50	#define LFB_DEPTH_PRESENT_MSW 8
	51
	52	/* flags for the register access array */
	53	#define REGISTER_READ 0x01 /* reads are allowed */
	54	#define REGISTER_WRITE 0x02 /* writes are allowed */
	55	#define REGISTER_PIPELINED 0x04 /* writes are pipelined */
	56	#define REGISTER_FIFO 0x08 /* writes go to FIFO */
	57	#define REGISTER_WRITETHRU 0x10 /* writes are valid even for CMDFIFO */
	58
	59	/* shorter combinations to make the table smaller */
	60	#define REG_R (REGISTER_READ)
	61	#define REG_W (REGISTER_WRITE)
	62	#define REG_WT (REGISTER_WRITE \| REGISTER_WRITETHRU)
	63	#define REG_RW (REGISTER_READ \| REGISTER_WRITE)
	64	#define REG_RWT (REGISTER_READ \| REGISTER_WRITE \| REGISTER_WRITETHRU)
	65	#define REG_RP (REGISTER_READ \| REGISTER_PIPELINED)
	66	#define REG_WP (REGISTER_WRITE \| REGISTER_PIPELINED)
	67	#define REG_RWP (REGISTER_READ \| REGISTER_WRITE \| REGISTER_PIPELINED)
	68	#define REG_RWPT (REGISTER_READ \| REGISTER_WRITE \| REGISTER_PIPELINED \| REGISTER_WRITETHRU)
	69	#define REG_RF (REGISTER_READ \| REGISTER_FIFO)
	70	#define REG_WF (REGISTER_WRITE \| REGISTER_FIFO)
	71	#define REG_RWF (REGISTER_READ \| REGISTER_WRITE \| REGISTER_FIFO)
	72	#define REG_RPF (REGISTER_READ \| REGISTER_PIPELINED \| REGISTER_FIFO)
	73	#define REG_WPF (REGISTER_WRITE \| REGISTER_PIPELINED \| REGISTER_FIFO)
	74	#define REG_RWPF (REGISTER_READ \| REGISTER_WRITE \| REGISTER_PIPELINED \| REGISTER_FIFO)
	75
	76	/* lookup bits is the log2 of the size of the reciprocal/log table */
	77	#define RECIPLOG_LOOKUP_BITS 9
	78
	79	/* input precision is how many fraction bits the input value has; this is a 64-bit number */
	80	#define RECIPLOG_INPUT_PREC 32
	81
	82	/* lookup precision is how many fraction bits each table entry contains */
	83	#define RECIPLOG_LOOKUP_PREC 22
	84
	85	/* output precision is how many fraction bits the result should have */
	86	#define RECIP_OUTPUT_PREC 15
	87	#define LOG_OUTPUT_PREC 8
	88
	89
	90
14	91	/*************************************
15	92	*
	93	* Register constants
	94	*
	95	*************************************/
	96
	97	/* Codes to the right:
	98	R = readable
	99	W = writeable
	100	P = pipelined
	101	F = goes to FIFO
	102	*/
	103
	104	/* 0x000 */
	105	#define status (0x000/4) /* R P */
	106	#define intrCtrl (0x004/4) /* RW P -- Voodoo2/Banshee only */
	107	#define vertexAx (0x008/4) /* W PF */
	108	#define vertexAy (0x00c/4) /* W PF */
	109	#define vertexBx (0x010/4) /* W PF */
	110	#define vertexBy (0x014/4) /* W PF */
	111	#define vertexCx (0x018/4) /* W PF */
	112	#define vertexCy (0x01c/4) /* W PF */
	113	#define startR (0x020/4) /* W PF */
	114	#define startG (0x024/4) /* W PF */
	115	#define startB (0x028/4) /* W PF */
	116	#define startZ (0x02c/4) /* W PF */
	117	#define startA (0x030/4) /* W PF */
	118	#define startS (0x034/4) /* W PF */
	119	#define startT (0x038/4) /* W PF */
	120	#define startW (0x03c/4) /* W PF */
	121
	122	/* 0x040 */
	123	#define dRdX (0x040/4) /* W PF */
	124	#define dGdX (0x044/4) /* W PF */
	125	#define dBdX (0x048/4) /* W PF */
	126	#define dZdX (0x04c/4) /* W PF */
	127	#define dAdX (0x050/4) /* W PF */
	128	#define dSdX (0x054/4) /* W PF */
	129	#define dTdX (0x058/4) /* W PF */
	130	#define dWdX (0x05c/4) /* W PF */
	131	#define dRdY (0x060/4) /* W PF */
	132	#define dGdY (0x064/4) /* W PF */
	133	#define dBdY (0x068/4) /* W PF */
	134	#define dZdY (0x06c/4) /* W PF */
	135	#define dAdY (0x070/4) /* W PF */
	136	#define dSdY (0x074/4) /* W PF */
	137	#define dTdY (0x078/4) /* W PF */
	138	#define dWdY (0x07c/4) /* W PF */
	139
	140	/* 0x080 */
	141	#define triangleCMD (0x080/4) /* W PF */
	142	#define fvertexAx (0x088/4) /* W PF */
	143	#define fvertexAy (0x08c/4) /* W PF */
	144	#define fvertexBx (0x090/4) /* W PF */
	145	#define fvertexBy (0x094/4) /* W PF */
	146	#define fvertexCx (0x098/4) /* W PF */
	147	#define fvertexCy (0x09c/4) /* W PF */
	148	#define fstartR (0x0a0/4) /* W PF */
	149	#define fstartG (0x0a4/4) /* W PF */
	150	#define fstartB (0x0a8/4) /* W PF */
	151	#define fstartZ (0x0ac/4) /* W PF */
	152	#define fstartA (0x0b0/4) /* W PF */
	153	#define fstartS (0x0b4/4) /* W PF */
	154	#define fstartT (0x0b8/4) /* W PF */
	155	#define fstartW (0x0bc/4) /* W PF */
	156
	157	/* 0x0c0 */
	158	#define fdRdX (0x0c0/4) /* W PF */
	159	#define fdGdX (0x0c4/4) /* W PF */
	160	#define fdBdX (0x0c8/4) /* W PF */
	161	#define fdZdX (0x0cc/4) /* W PF */
	162	#define fdAdX (0x0d0/4) /* W PF */
	163	#define fdSdX (0x0d4/4) /* W PF */
	164	#define fdTdX (0x0d8/4) /* W PF */
	165	#define fdWdX (0x0dc/4) /* W PF */
	166	#define fdRdY (0x0e0/4) /* W PF */
	167	#define fdGdY (0x0e4/4) /* W PF */
	168	#define fdBdY (0x0e8/4) /* W PF */
	169	#define fdZdY (0x0ec/4) /* W PF */
	170	#define fdAdY (0x0f0/4) /* W PF */
	171	#define fdSdY (0x0f4/4) /* W PF */
	172	#define fdTdY (0x0f8/4) /* W PF */
	173	#define fdWdY (0x0fc/4) /* W PF */
	174
	175	/* 0x100 */
	176	#define ftriangleCMD (0x100/4) /* W PF */
	177	#define fbzColorPath (0x104/4) /* RW PF */
	178	#define fogMode (0x108/4) /* RW PF */
	179	#define alphaMode (0x10c/4) /* RW PF */
	180	#define fbzMode (0x110/4) /* RW F */
	181	#define lfbMode (0x114/4) /* RW F */
	182	#define clipLeftRight (0x118/4) /* RW F */
	183	#define clipLowYHighY (0x11c/4) /* RW F */
	184	#define nopCMD (0x120/4) /* W F */
	185	#define fastfillCMD (0x124/4) /* W F */
	186	#define swapbufferCMD (0x128/4) /* W F */
	187	#define fogColor (0x12c/4) /* W F */
	188	#define zaColor (0x130/4) /* W F */
	189	#define chromaKey (0x134/4) /* W F */
	190	#define chromaRange (0x138/4) /* W F -- Voodoo2/Banshee only */
	191	#define userIntrCMD (0x13c/4) /* W F -- Voodoo2/Banshee only */
	192
	193	/* 0x140 */
	194	#define stipple (0x140/4) /* RW F */
	195	#define color0 (0x144/4) /* RW F */
	196	#define color1 (0x148/4) /* RW F */
	197	#define fbiPixelsIn (0x14c/4) /* R */
	198	#define fbiChromaFail (0x150/4) /* R */
	199	#define fbiZfuncFail (0x154/4) /* R */
	200	#define fbiAfuncFail (0x158/4) /* R */
	201	#define fbiPixelsOut (0x15c/4) /* R */
	202	#define fogTable (0x160/4) /* W F */
	203
	204	/* 0x1c0 */
	205	#define cmdFifoBaseAddr (0x1e0/4) /* RW -- Voodoo2 only */
	206	#define cmdFifoBump (0x1e4/4) /* RW -- Voodoo2 only */
	207	#define cmdFifoRdPtr (0x1e8/4) /* RW -- Voodoo2 only */
	208	#define cmdFifoAMin (0x1ec/4) /* RW -- Voodoo2 only */
	209	#define colBufferAddr (0x1ec/4) /* RW -- Banshee only */
	210	#define cmdFifoAMax (0x1f0/4) /* RW -- Voodoo2 only */
	211	#define colBufferStride (0x1f0/4) /* RW -- Banshee only */
	212	#define cmdFifoDepth (0x1f4/4) /* RW -- Voodoo2 only */
	213	#define auxBufferAddr (0x1f4/4) /* RW -- Banshee only */
	214	#define cmdFifoHoles (0x1f8/4) /* RW -- Voodoo2 only */
	215	#define auxBufferStride (0x1f8/4) /* RW -- Banshee only */
	216
	217	/* 0x200 */
	218	#define fbiInit4 (0x200/4) /* RW -- Voodoo/Voodoo2 only */
	219	#define clipLeftRight1 (0x200/4) /* RW -- Banshee only */
	220	#define vRetrace (0x204/4) /* R -- Voodoo/Voodoo2 only */
	221	#define clipTopBottom1 (0x204/4) /* RW -- Banshee only */
	222	#define backPorch (0x208/4) /* RW -- Voodoo/Voodoo2 only */
	223	#define videoDimensions (0x20c/4) /* RW -- Voodoo/Voodoo2 only */
	224	#define fbiInit0 (0x210/4) /* RW -- Voodoo/Voodoo2 only */
	225	#define fbiInit1 (0x214/4) /* RW -- Voodoo/Voodoo2 only */
	226	#define fbiInit2 (0x218/4) /* RW -- Voodoo/Voodoo2 only */
	227	#define fbiInit3 (0x21c/4) /* RW -- Voodoo/Voodoo2 only */
	228	#define hSync (0x220/4) /* W -- Voodoo/Voodoo2 only */
	229	#define vSync (0x224/4) /* W -- Voodoo/Voodoo2 only */
	230	#define clutData (0x228/4) /* W F -- Voodoo/Voodoo2 only */
	231	#define dacData (0x22c/4) /* W -- Voodoo/Voodoo2 only */
	232	#define maxRgbDelta (0x230/4) /* W -- Voodoo/Voodoo2 only */
	233	#define hBorder (0x234/4) /* W -- Voodoo2 only */
	234	#define vBorder (0x238/4) /* W -- Voodoo2 only */
	235	#define borderColor (0x23c/4) /* W -- Voodoo2 only */
	236
	237	/* 0x240 */
	238	#define hvRetrace (0x240/4) /* R -- Voodoo2 only */
	239	#define fbiInit5 (0x244/4) /* RW -- Voodoo2 only */
	240	#define fbiInit6 (0x248/4) /* RW -- Voodoo2 only */
	241	#define fbiInit7 (0x24c/4) /* RW -- Voodoo2 only */
	242	#define swapPending (0x24c/4) /* W -- Banshee only */
	243	#define leftOverlayBuf (0x250/4) /* W -- Banshee only */
	244	#define rightOverlayBuf (0x254/4) /* W -- Banshee only */
	245	#define fbiSwapHistory (0x258/4) /* R -- Voodoo2/Banshee only */
	246	#define fbiTrianglesOut (0x25c/4) /* R -- Voodoo2/Banshee only */
	247	#define sSetupMode (0x260/4) /* W PF -- Voodoo2/Banshee only */
	248	#define sVx (0x264/4) /* W PF -- Voodoo2/Banshee only */
	249	#define sVy (0x268/4) /* W PF -- Voodoo2/Banshee only */
	250	#define sARGB (0x26c/4) /* W PF -- Voodoo2/Banshee only */
	251	#define sRed (0x270/4) /* W PF -- Voodoo2/Banshee only */
	252	#define sGreen (0x274/4) /* W PF -- Voodoo2/Banshee only */
	253	#define sBlue (0x278/4) /* W PF -- Voodoo2/Banshee only */
	254	#define sAlpha (0x27c/4) /* W PF -- Voodoo2/Banshee only */
	255
	256	/* 0x280 */
	257	#define sVz (0x280/4) /* W PF -- Voodoo2/Banshee only */
	258	#define sWb (0x284/4) /* W PF -- Voodoo2/Banshee only */
	259	#define sWtmu0 (0x288/4) /* W PF -- Voodoo2/Banshee only */
	260	#define sS_W0 (0x28c/4) /* W PF -- Voodoo2/Banshee only */
	261	#define sT_W0 (0x290/4) /* W PF -- Voodoo2/Banshee only */
	262	#define sWtmu1 (0x294/4) /* W PF -- Voodoo2/Banshee only */
	263	#define sS_Wtmu1 (0x298/4) /* W PF -- Voodoo2/Banshee only */
	264	#define sT_Wtmu1 (0x29c/4) /* W PF -- Voodoo2/Banshee only */
	265	#define sDrawTriCMD (0x2a0/4) /* W PF -- Voodoo2/Banshee only */
	266	#define sBeginTriCMD (0x2a4/4) /* W PF -- Voodoo2/Banshee only */
	267
	268	/* 0x2c0 */
	269	#define bltSrcBaseAddr (0x2c0/4) /* RW PF -- Voodoo2 only */
	270	#define bltDstBaseAddr (0x2c4/4) /* RW PF -- Voodoo2 only */
	271	#define bltXYStrides (0x2c8/4) /* RW PF -- Voodoo2 only */
	272	#define bltSrcChromaRange (0x2cc/4) /* RW PF -- Voodoo2 only */
	273	#define bltDstChromaRange (0x2d0/4) /* RW PF -- Voodoo2 only */
	274	#define bltClipX (0x2d4/4) /* RW PF -- Voodoo2 only */
	275	#define bltClipY (0x2d8/4) /* RW PF -- Voodoo2 only */
	276	#define bltSrcXY (0x2e0/4) /* RW PF -- Voodoo2 only */
	277	#define bltDstXY (0x2e4/4) /* RW PF -- Voodoo2 only */
	278	#define bltSize (0x2e8/4) /* RW PF -- Voodoo2 only */
	279	#define bltRop (0x2ec/4) /* RW PF -- Voodoo2 only */
	280	#define bltColor (0x2f0/4) /* RW PF -- Voodoo2 only */
	281	#define bltCommand (0x2f8/4) /* RW PF -- Voodoo2 only */
	282	#define bltData (0x2fc/4) /* W PF -- Voodoo2 only */
	283
	284	/* 0x300 */
	285	#define textureMode (0x300/4) /* W PF */
	286	#define tLOD (0x304/4) /* W PF */
	287	#define tDetail (0x308/4) /* W PF */
	288	#define texBaseAddr (0x30c/4) /* W PF */
	289	#define texBaseAddr_1 (0x310/4) /* W PF */
	290	#define texBaseAddr_2 (0x314/4) /* W PF */
	291	#define texBaseAddr_3_8 (0x318/4) /* W PF */
	292	#define trexInit0 (0x31c/4) /* W F -- Voodoo/Voodoo2 only */
	293	#define trexInit1 (0x320/4) /* W F */
	294	#define nccTable (0x324/4) /* W F */
	295
	296
	297
	298	// 2D registers
	299	#define banshee2D_clip0Min (0x008/4)
	300	#define banshee2D_clip0Max (0x00c/4)
	301	#define banshee2D_dstBaseAddr (0x010/4)
	302	#define banshee2D_dstFormat (0x014/4)
	303	#define banshee2D_srcColorkeyMin (0x018/4)
	304	#define banshee2D_srcColorkeyMax (0x01c/4)
	305	#define banshee2D_dstColorkeyMin (0x020/4)
	306	#define banshee2D_dstColorkeyMax (0x024/4)
	307	#define banshee2D_bresError0 (0x028/4)
	308	#define banshee2D_bresError1 (0x02c/4)
	309	#define banshee2D_rop (0x030/4)
	310	#define banshee2D_srcBaseAddr (0x034/4)
	311	#define banshee2D_commandExtra (0x038/4)
	312	#define banshee2D_lineStipple (0x03c/4)
	313	#define banshee2D_lineStyle (0x040/4)
	314	#define banshee2D_pattern0Alias (0x044/4)
	315	#define banshee2D_pattern1Alias (0x048/4)
	316	#define banshee2D_clip1Min (0x04c/4)
	317	#define banshee2D_clip1Max (0x050/4)
	318	#define banshee2D_srcFormat (0x054/4)
	319	#define banshee2D_srcSize (0x058/4)
	320	#define banshee2D_srcXY (0x05c/4)
	321	#define banshee2D_colorBack (0x060/4)
	322	#define banshee2D_colorFore (0x064/4)
	323	#define banshee2D_dstSize (0x068/4)
	324	#define banshee2D_dstXY (0x06c/4)
	325	#define banshee2D_command (0x070/4)
	326
	327
	328	/*************************************
	329	*
	330	* Alias map of the first 64
	331	* registers when remapped
	332	*
	333	*************************************/
	334
	335	static const UINT8 register_alias_map[0x40] =
	336	{
	337	status, 0x004/4, vertexAx, vertexAy,
	338	vertexBx, vertexBy, vertexCx, vertexCy,
	339	startR, dRdX, dRdY, startG,
	340	dGdX, dGdY, startB, dBdX,
	341	dBdY, startZ, dZdX, dZdY,
	342	startA, dAdX, dAdY, startS,
	343	dSdX, dSdY, startT, dTdX,
	344	dTdY, startW, dWdX, dWdY,
	345
	346	triangleCMD,0x084/4, fvertexAx, fvertexAy,
	347	fvertexBx, fvertexBy, fvertexCx, fvertexCy,
	348	fstartR, fdRdX, fdRdY, fstartG,
	349	fdGdX, fdGdY, fstartB, fdBdX,
	350	fdBdY, fstartZ, fdZdX, fdZdY,
	351	fstartA, fdAdX, fdAdY, fstartS,
	352	fdSdX, fdSdY, fstartT, fdTdX,
	353	fdTdY, fstartW, fdWdX, fdWdY
	354	};
	355
	356
	357
	358	/*************************************
	359	*
	360	* Table of per-register access rights
	361	*
	362	*************************************/
	363
	364	static const UINT8 voodoo_register_access[0x100] =
	365	{
	366	/* 0x000 */
	367	REG_RP, 0, REG_WPF, REG_WPF,
	368	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	369	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	370	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	371
	372	/* 0x040 */
	373	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	374	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	375	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	376	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	377
	378	/* 0x080 */
	379	REG_WPF, 0, REG_WPF, REG_WPF,
	380	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	381	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	382	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	383
	384	/* 0x0c0 */
	385	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	386	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	387	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	388	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	389
	390	/* 0x100 */
	391	REG_WPF, REG_RWPF, REG_RWPF, REG_RWPF,
	392	REG_RWF, REG_RWF, REG_RWF, REG_RWF,
	393	REG_WF, REG_WF, REG_WF, REG_WF,
	394	REG_WF, REG_WF, 0, 0,
	395
	396	/* 0x140 */
	397	REG_RWF, REG_RWF, REG_RWF, REG_R,
	398	REG_R, REG_R, REG_R, REG_R,
	399	REG_WF, REG_WF, REG_WF, REG_WF,
	400	REG_WF, REG_WF, REG_WF, REG_WF,
	401
	402	/* 0x180 */
	403	REG_WF, REG_WF, REG_WF, REG_WF,
	404	REG_WF, REG_WF, REG_WF, REG_WF,
	405	REG_WF, REG_WF, REG_WF, REG_WF,
	406	REG_WF, REG_WF, REG_WF, REG_WF,
	407
	408	/* 0x1c0 */
	409	REG_WF, REG_WF, REG_WF, REG_WF,
	410	REG_WF, REG_WF, REG_WF, REG_WF,
	411	0, 0, 0, 0,
	412	0, 0, 0, 0,
	413
	414	/* 0x200 */
	415	REG_RW, REG_R, REG_RW, REG_RW,
	416	REG_RW, REG_RW, REG_RW, REG_RW,
	417	REG_W, REG_W, REG_W, REG_W,
	418	REG_W, 0, 0, 0,
	419
	420	/* 0x240 */
	421	0, 0, 0, 0,
	422	0, 0, 0, 0,
	423	0, 0, 0, 0,
	424	0, 0, 0, 0,
	425
	426	/* 0x280 */
	427	0, 0, 0, 0,
	428	0, 0, 0, 0,
	429	0, 0, 0, 0,
	430	0, 0, 0, 0,
	431
	432	/* 0x2c0 */
	433	0, 0, 0, 0,
	434	0, 0, 0, 0,
	435	0, 0, 0, 0,
	436	0, 0, 0, 0,
	437
	438	/* 0x300 */
	439	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	440	REG_WPF, REG_WPF, REG_WPF, REG_WF,
	441	REG_WF, REG_WF, REG_WF, REG_WF,
	442	REG_WF, REG_WF, REG_WF, REG_WF,
	443
	444	/* 0x340 */
	445	REG_WF, REG_WF, REG_WF, REG_WF,
	446	REG_WF, REG_WF, REG_WF, REG_WF,
	447	REG_WF, REG_WF, REG_WF, REG_WF,
	448	REG_WF, REG_WF, REG_WF, REG_WF,
	449
	450	/* 0x380 */
	451	REG_WF
	452	};
	453
	454
	455	static const UINT8 voodoo2_register_access[0x100] =
	456	{
	457	/* 0x000 */
	458	REG_RP, REG_RWPT, REG_WPF, REG_WPF,
	459	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	460	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	461	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	462
	463	/* 0x040 */
	464	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	465	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	466	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	467	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	468
	469	/* 0x080 */
	470	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	471	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	472	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	473	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	474
	475	/* 0x0c0 */
	476	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	477	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	478	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	479	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	480
	481	/* 0x100 */
	482	REG_WPF, REG_RWPF, REG_RWPF, REG_RWPF,
	483	REG_RWF, REG_RWF, REG_RWF, REG_RWF,
	484	REG_WF, REG_WF, REG_WF, REG_WF,
	485	REG_WF, REG_WF, REG_WF, REG_WF,
	486
	487	/* 0x140 */
	488	REG_RWF, REG_RWF, REG_RWF, REG_R,
	489	REG_R, REG_R, REG_R, REG_R,
	490	REG_WF, REG_WF, REG_WF, REG_WF,
	491	REG_WF, REG_WF, REG_WF, REG_WF,
	492
	493	/* 0x180 */
	494	REG_WF, REG_WF, REG_WF, REG_WF,
	495	REG_WF, REG_WF, REG_WF, REG_WF,
	496	REG_WF, REG_WF, REG_WF, REG_WF,
	497	REG_WF, REG_WF, REG_WF, REG_WF,
	498
	499	/* 0x1c0 */
	500	REG_WF, REG_WF, REG_WF, REG_WF,
	501	REG_WF, REG_WF, REG_WF, REG_WF,
	502	REG_RWT, REG_RWT, REG_RWT, REG_RWT,
	503	REG_RWT, REG_RWT, REG_RWT, REG_RW,
	504
	505	/* 0x200 */
	506	REG_RWT, REG_R, REG_RWT, REG_RWT,
	507	REG_RWT, REG_RWT, REG_RWT, REG_RWT,
	508	REG_WT, REG_WT, REG_WF, REG_WT,
	509	REG_WT, REG_WT, REG_WT, REG_WT,
	510
	511	/* 0x240 */
	512	REG_R, REG_RWT, REG_RWT, REG_RWT,
	513	0, 0, REG_R, REG_R,
	514	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	515	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	516
	517	/* 0x280 */
	518	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	519	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	520	REG_WPF, REG_WPF, 0, 0,
	521	0, 0, 0, 0,
	522
	523	/* 0x2c0 */
	524	REG_RWPF, REG_RWPF, REG_RWPF, REG_RWPF,
	525	REG_RWPF, REG_RWPF, REG_RWPF, REG_RWPF,
	526	REG_RWPF, REG_RWPF, REG_RWPF, REG_RWPF,
	527	REG_RWPF, REG_RWPF, REG_RWPF, REG_WPF,
	528
	529	/* 0x300 */
	530	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	531	REG_WPF, REG_WPF, REG_WPF, REG_WF,
	532	REG_WF, REG_WF, REG_WF, REG_WF,
	533	REG_WF, REG_WF, REG_WF, REG_WF,
	534
	535	/* 0x340 */
	536	REG_WF, REG_WF, REG_WF, REG_WF,
	537	REG_WF, REG_WF, REG_WF, REG_WF,
	538	REG_WF, REG_WF, REG_WF, REG_WF,
	539	REG_WF, REG_WF, REG_WF, REG_WF,
	540
	541	/* 0x380 */
	542	REG_WF
	543	};
	544
	545
	546	static const UINT8 banshee_register_access[0x100] =
	547	{
	548	/* 0x000 */
	549	REG_RP, REG_RWPT, REG_WPF, REG_WPF,
	550	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	551	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	552	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	553
	554	/* 0x040 */
	555	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	556	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	557	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	558	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	559
	560	/* 0x080 */
	561	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	562	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	563	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	564	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	565
	566	/* 0x0c0 */
	567	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	568	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	569	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	570	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	571
	572	/* 0x100 */
	573	REG_WPF, REG_RWPF, REG_RWPF, REG_RWPF,
	574	REG_RWF, REG_RWF, REG_RWF, REG_RWF,
	575	REG_WF, REG_WF, REG_WF, REG_WF,
	576	REG_WF, REG_WF, REG_WF, REG_WF,
	577
	578	/* 0x140 */
	579	REG_RWF, REG_RWF, REG_RWF, REG_R,
	580	REG_R, REG_R, REG_R, REG_R,
	581	REG_WF, REG_WF, REG_WF, REG_WF,
	582	REG_WF, REG_WF, REG_WF, REG_WF,
	583
	584	/* 0x180 */
	585	REG_WF, REG_WF, REG_WF, REG_WF,
	586	REG_WF, REG_WF, REG_WF, REG_WF,
	587	REG_WF, REG_WF, REG_WF, REG_WF,
	588	REG_WF, REG_WF, REG_WF, REG_WF,
	589
	590	/* 0x1c0 */
	591	REG_WF, REG_WF, REG_WF, REG_WF,
	592	REG_WF, REG_WF, REG_WF, REG_WF,
	593	0, 0, 0, REG_RWF,
	594	REG_RWF, REG_RWF, REG_RWF, 0,
	595
	596	/* 0x200 */
	597	REG_RWF, REG_RWF, 0, 0,
	598	0, 0, 0, 0,
	599	0, 0, 0, 0,
	600	0, 0, 0, 0,
	601
	602	/* 0x240 */
	603	0, 0, 0, REG_WT,
	604	REG_RWF, REG_RWF, REG_WPF, REG_WPF,
	605	REG_WPF, REG_WPF, REG_R, REG_R,
	606	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	607
	608	/* 0x280 */
	609	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	610	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	611	REG_WPF, REG_WPF, 0, 0,
	612	0, 0, 0, 0,
	613
	614	/* 0x2c0 */
	615	0, 0, 0, 0,
	616	0, 0, 0, 0,
	617	0, 0, 0, 0,
	618	0, 0, 0, 0,
	619
	620	/* 0x300 */
	621	REG_WPF, REG_WPF, REG_WPF, REG_WPF,
	622	REG_WPF, REG_WPF, REG_WPF, 0,
	623	REG_WF, REG_WF, REG_WF, REG_WF,
	624	REG_WF, REG_WF, REG_WF, REG_WF,
	625
	626	/* 0x340 */
	627	REG_WF, REG_WF, REG_WF, REG_WF,
	628	REG_WF, REG_WF, REG_WF, REG_WF,
	629	REG_WF, REG_WF, REG_WF, REG_WF,
	630	REG_WF, REG_WF, REG_WF, REG_WF,
	631
	632	/* 0x380 */
	633	REG_WF
	634	};
	635
	636
	637
	638	/*************************************
	639	*
	640	* Register string table for debug
	641	*
	642	*************************************/
	643
	644	static const char *const voodoo_reg_name[] =
	645	{
	646	/* 0x000 */
	647	"status", "{intrCtrl}", "vertexAx", "vertexAy",
	648	"vertexBx", "vertexBy", "vertexCx", "vertexCy",
	649	"startR", "startG", "startB", "startZ",
	650	"startA", "startS", "startT", "startW",
	651	/* 0x040 */
	652	"dRdX", "dGdX", "dBdX", "dZdX",
	653	"dAdX", "dSdX", "dTdX", "dWdX",
	654	"dRdY", "dGdY", "dBdY", "dZdY",
	655	"dAdY", "dSdY", "dTdY", "dWdY",
	656	/* 0x080 */
	657	"triangleCMD", "reserved084", "fvertexAx", "fvertexAy",
	658	"fvertexBx", "fvertexBy", "fvertexCx", "fvertexCy",
	659	"fstartR", "fstartG", "fstartB", "fstartZ",
	660	"fstartA", "fstartS", "fstartT", "fstartW",
	661	/* 0x0c0 */
	662	"fdRdX", "fdGdX", "fdBdX", "fdZdX",
	663	"fdAdX", "fdSdX", "fdTdX", "fdWdX",
	664	"fdRdY", "fdGdY", "fdBdY", "fdZdY",
	665	"fdAdY", "fdSdY", "fdTdY", "fdWdY",
	666	/* 0x100 */
	667	"ftriangleCMD", "fbzColorPath", "fogMode", "alphaMode",
	668	"fbzMode", "lfbMode", "clipLeftRight","clipLowYHighY",
	669	"nopCMD", "fastfillCMD", "swapbufferCMD","fogColor",
	670	"zaColor", "chromaKey", "{chromaRange}","{userIntrCMD}",
	671	/* 0x140 */
	672	"stipple", "color0", "color1", "fbiPixelsIn",
	673	"fbiChromaFail","fbiZfuncFail", "fbiAfuncFail", "fbiPixelsOut",
	674	"fogTable160", "fogTable164", "fogTable168", "fogTable16c",
	675	"fogTable170", "fogTable174", "fogTable178", "fogTable17c",
	676	/* 0x180 */
	677	"fogTable180", "fogTable184", "fogTable188", "fogTable18c",
	678	"fogTable190", "fogTable194", "fogTable198", "fogTable19c",
	679	"fogTable1a0", "fogTable1a4", "fogTable1a8", "fogTable1ac",
	680	"fogTable1b0", "fogTable1b4", "fogTable1b8", "fogTable1bc",
	681	/* 0x1c0 */
	682	"fogTable1c0", "fogTable1c4", "fogTable1c8", "fogTable1cc",
	683	"fogTable1d0", "fogTable1d4", "fogTable1d8", "fogTable1dc",
	684	"{cmdFifoBaseAddr}","{cmdFifoBump}","{cmdFifoRdPtr}","{cmdFifoAMin}",
	685	"{cmdFifoAMax}","{cmdFifoDepth}","{cmdFifoHoles}","reserved1fc",
	686	/* 0x200 */
	687	"fbiInit4", "vRetrace", "backPorch", "videoDimensions",
	688	"fbiInit0", "fbiInit1", "fbiInit2", "fbiInit3",
	689	"hSync", "vSync", "clutData", "dacData",
	690	"maxRgbDelta", "{hBorder}", "{vBorder}", "{borderColor}",
	691	/* 0x240 */
	692	"{hvRetrace}", "{fbiInit5}", "{fbiInit6}", "{fbiInit7}",
	693	"reserved250", "reserved254", "{fbiSwapHistory}","{fbiTrianglesOut}",
	694	"{sSetupMode}", "{sVx}", "{sVy}", "{sARGB}",
	695	"{sRed}", "{sGreen}", "{sBlue}", "{sAlpha}",
	696	/* 0x280 */
	697	"{sVz}", "{sWb}", "{sWtmu0}", "{sS/Wtmu0}",
	698	"{sT/Wtmu0}", "{sWtmu1}", "{sS/Wtmu1}", "{sT/Wtmu1}",
	699	"{sDrawTriCMD}","{sBeginTriCMD}","reserved2a8", "reserved2ac",
	700	"reserved2b0", "reserved2b4", "reserved2b8", "reserved2bc",
	701	/* 0x2c0 */
	702	"{bltSrcBaseAddr}","{bltDstBaseAddr}","{bltXYStrides}","{bltSrcChromaRange}",
	703	"{bltDstChromaRange}","{bltClipX}","{bltClipY}","reserved2dc",
	704	"{bltSrcXY}", "{bltDstXY}", "{bltSize}", "{bltRop}",
	705	"{bltColor}", "reserved2f4", "{bltCommand}", "{bltData}",
	706	/* 0x300 */
	707	"textureMode", "tLOD", "tDetail", "texBaseAddr",
	708	"texBaseAddr_1","texBaseAddr_2","texBaseAddr_3_8","trexInit0",
	709	"trexInit1", "nccTable0.0", "nccTable0.1", "nccTable0.2",
	710	"nccTable0.3", "nccTable0.4", "nccTable0.5", "nccTable0.6",
	711	/* 0x340 */
	712	"nccTable0.7", "nccTable0.8", "nccTable0.9", "nccTable0.A",
	713	"nccTable0.B", "nccTable1.0", "nccTable1.1", "nccTable1.2",
	714	"nccTable1.3", "nccTable1.4", "nccTable1.5", "nccTable1.6",
	715	"nccTable1.7", "nccTable1.8", "nccTable1.9", "nccTable1.A",
	716	/* 0x380 */
	717	"nccTable1.B"
	718	};
	719
	720
	721	static const char *const banshee_reg_name[] =
	722	{
	723	/* 0x000 */
	724	"status", "intrCtrl", "vertexAx", "vertexAy",
	725	"vertexBx", "vertexBy", "vertexCx", "vertexCy",
	726	"startR", "startG", "startB", "startZ",
	727	"startA", "startS", "startT", "startW",
	728	/* 0x040 */
	729	"dRdX", "dGdX", "dBdX", "dZdX",
	730	"dAdX", "dSdX", "dTdX", "dWdX",
	731	"dRdY", "dGdY", "dBdY", "dZdY",
	732	"dAdY", "dSdY", "dTdY", "dWdY",
	733	/* 0x080 */
	734	"triangleCMD", "reserved084", "fvertexAx", "fvertexAy",
	735	"fvertexBx", "fvertexBy", "fvertexCx", "fvertexCy",
	736	"fstartR", "fstartG", "fstartB", "fstartZ",
	737	"fstartA", "fstartS", "fstartT", "fstartW",
	738	/* 0x0c0 */
	739	"fdRdX", "fdGdX", "fdBdX", "fdZdX",
	740	"fdAdX", "fdSdX", "fdTdX", "fdWdX",
	741	"fdRdY", "fdGdY", "fdBdY", "fdZdY",
	742	"fdAdY", "fdSdY", "fdTdY", "fdWdY",
	743	/* 0x100 */
	744	"ftriangleCMD", "fbzColorPath", "fogMode", "alphaMode",
	745	"fbzMode", "lfbMode", "clipLeftRight","clipLowYHighY",
	746	"nopCMD", "fastfillCMD", "swapbufferCMD","fogColor",
	747	"zaColor", "chromaKey", "chromaRange", "userIntrCMD",
	748	/* 0x140 */
	749	"stipple", "color0", "color1", "fbiPixelsIn",
	750	"fbiChromaFail","fbiZfuncFail", "fbiAfuncFail", "fbiPixelsOut",
	751	"fogTable160", "fogTable164", "fogTable168", "fogTable16c",
	752	"fogTable170", "fogTable174", "fogTable178", "fogTable17c",
	753	/* 0x180 */
	754	"fogTable180", "fogTable184", "fogTable188", "fogTable18c",
	755	"fogTable190", "fogTable194", "fogTable198", "fogTable19c",
	756	"fogTable1a0", "fogTable1a4", "fogTable1a8", "fogTable1ac",
	757	"fogTable1b0", "fogTable1b4", "fogTable1b8", "fogTable1bc",
	758	/* 0x1c0 */
	759	"fogTable1c0", "fogTable1c4", "fogTable1c8", "fogTable1cc",
	760	"fogTable1d0", "fogTable1d4", "fogTable1d8", "fogTable1dc",
	761	"reserved1e0", "reserved1e4", "reserved1e8", "colBufferAddr",
	762	"colBufferStride","auxBufferAddr","auxBufferStride","reserved1fc",
	763	/* 0x200 */
	764	"clipLeftRight1","clipTopBottom1","reserved208","reserved20c",
	765	"reserved210", "reserved214", "reserved218", "reserved21c",
	766	"reserved220", "reserved224", "reserved228", "reserved22c",
	767	"reserved230", "reserved234", "reserved238", "reserved23c",
	768	/* 0x240 */
	769	"reserved240", "reserved244", "reserved248", "swapPending",
	770	"leftOverlayBuf","rightOverlayBuf","fbiSwapHistory","fbiTrianglesOut",
	771	"sSetupMode", "sVx", "sVy", "sARGB",
	772	"sRed", "sGreen", "sBlue", "sAlpha",
	773	/* 0x280 */
	774	"sVz", "sWb", "sWtmu0", "sS/Wtmu0",
	775	"sT/Wtmu0", "sWtmu1", "sS/Wtmu1", "sT/Wtmu1",
	776	"sDrawTriCMD", "sBeginTriCMD", "reserved2a8", "reserved2ac",
	777	"reserved2b0", "reserved2b4", "reserved2b8", "reserved2bc",
	778	/* 0x2c0 */
	779	"reserved2c0", "reserved2c4", "reserved2c8", "reserved2cc",
	780	"reserved2d0", "reserved2d4", "reserved2d8", "reserved2dc",
	781	"reserved2e0", "reserved2e4", "reserved2e8", "reserved2ec",
	782	"reserved2f0", "reserved2f4", "reserved2f8", "reserved2fc",
	783	/* 0x300 */
	784	"textureMode", "tLOD", "tDetail", "texBaseAddr",
	785	"texBaseAddr_1","texBaseAddr_2","texBaseAddr_3_8","reserved31c",
	786	"trexInit1", "nccTable0.0", "nccTable0.1", "nccTable0.2",
	787	"nccTable0.3", "nccTable0.4", "nccTable0.5", "nccTable0.6",
	788	/* 0x340 */
	789	"nccTable0.7", "nccTable0.8", "nccTable0.9", "nccTable0.A",
	790	"nccTable0.B", "nccTable1.0", "nccTable1.1", "nccTable1.2",
	791	"nccTable1.3", "nccTable1.4", "nccTable1.5", "nccTable1.6",
	792	"nccTable1.7", "nccTable1.8", "nccTable1.9", "nccTable1.A",
	793	/* 0x380 */
	794	"nccTable1.B"
	795	};
	796
	797
	798
	799	/*************************************
	800	*
	801	* Voodoo Banshee I/O space registers
	802	*
	803	*************************************/
	804
	805	/* 0x000 */
	806	#define io_status (0x000/4) /* */
	807	#define io_pciInit0 (0x004/4) /* */
	808	#define io_sipMonitor (0x008/4) /* */
	809	#define io_lfbMemoryConfig (0x00c/4) /* */
	810	#define io_miscInit0 (0x010/4) /* */
	811	#define io_miscInit1 (0x014/4) /* */
	812	#define io_dramInit0 (0x018/4) /* */
	813	#define io_dramInit1 (0x01c/4) /* */
	814	#define io_agpInit (0x020/4) /* */
	815	#define io_tmuGbeInit (0x024/4) /* */
	816	#define io_vgaInit0 (0x028/4) /* */
	817	#define io_vgaInit1 (0x02c/4) /* */
	818	#define io_dramCommand (0x030/4) /* */
	819	#define io_dramData (0x034/4) /* */
	820
	821	/* 0x040 */
	822	#define io_pllCtrl0 (0x040/4) /* */
	823	#define io_pllCtrl1 (0x044/4) /* */
	824	#define io_pllCtrl2 (0x048/4) /* */
	825	#define io_dacMode (0x04c/4) /* */
	826	#define io_dacAddr (0x050/4) /* */
	827	#define io_dacData (0x054/4) /* */
	828	#define io_rgbMaxDelta (0x058/4) /* */
	829	#define io_vidProcCfg (0x05c/4) /* */
	830	#define io_hwCurPatAddr (0x060/4) /* */
	831	#define io_hwCurLoc (0x064/4) /* */
	832	#define io_hwCurC0 (0x068/4) /* */
	833	#define io_hwCurC1 (0x06c/4) /* */
	834	#define io_vidInFormat (0x070/4) /* */
	835	#define io_vidInStatus (0x074/4) /* */
	836	#define io_vidSerialParallelPort (0x078/4) /* */
	837	#define io_vidInXDecimDeltas (0x07c/4) /* */
	838
	839	/* 0x080 */
	840	#define io_vidInDecimInitErrs (0x080/4) /* */
	841	#define io_vidInYDecimDeltas (0x084/4) /* */
	842	#define io_vidPixelBufThold (0x088/4) /* */
	843	#define io_vidChromaMin (0x08c/4) /* */
	844	#define io_vidChromaMax (0x090/4) /* */
	845	#define io_vidCurrentLine (0x094/4) /* */
	846	#define io_vidScreenSize (0x098/4) /* */
	847	#define io_vidOverlayStartCoords (0x09c/4) /* */
	848	#define io_vidOverlayEndScreenCoord (0x0a0/4) /* */
	849	#define io_vidOverlayDudx (0x0a4/4) /* */
	850	#define io_vidOverlayDudxOffsetSrcWidth (0x0a8/4) /* */
	851	#define io_vidOverlayDvdy (0x0ac/4) /* */
	852	#define io_vgab0 (0x0b0/4) /* */
	853	#define io_vgab4 (0x0b4/4) /* */
	854	#define io_vgab8 (0x0b8/4) /* */
	855	#define io_vgabc (0x0bc/4) /* */
	856
	857	/* 0x0c0 */
	858	#define io_vgac0 (0x0c0/4) /* */
	859	#define io_vgac4 (0x0c4/4) /* */
	860	#define io_vgac8 (0x0c8/4) /* */
	861	#define io_vgacc (0x0cc/4) /* */
	862	#define io_vgad0 (0x0d0/4) /* */
	863	#define io_vgad4 (0x0d4/4) /* */
	864	#define io_vgad8 (0x0d8/4) /* */
	865	#define io_vgadc (0x0dc/4) /* */
	866	#define io_vidOverlayDvdyOffset (0x0e0/4) /* */
	867	#define io_vidDesktopStartAddr (0x0e4/4) /* */
	868	#define io_vidDesktopOverlayStride (0x0e8/4) /* */
	869	#define io_vidInAddr0 (0x0ec/4) /* */
	870	#define io_vidInAddr1 (0x0f0/4) /* */
	871	#define io_vidInAddr2 (0x0f4/4) /* */
	872	#define io_vidInStride (0x0f8/4) /* */
	873	#define io_vidCurrOverlayStartAddr (0x0fc/4) /* */
	874
	875
	876
	877	/*************************************
	878	*
	879	* Register string table for debug
	880	*
	881	*************************************/
	882
	883	static const char *const banshee_io_reg_name[] =
	884	{
	885	/* 0x000 */
	886	"status", "pciInit0", "sipMonitor", "lfbMemoryConfig",
	887	"miscInit0", "miscInit1", "dramInit0", "dramInit1",
	888	"agpInit", "tmuGbeInit", "vgaInit0", "vgaInit1",
	889	"dramCommand", "dramData", "reserved38", "reserved3c",
	890
	891	/* 0x040 */
	892	"pllCtrl0", "pllCtrl1", "pllCtrl2", "dacMode",
	893	"dacAddr", "dacData", "rgbMaxDelta", "vidProcCfg",
	894	"hwCurPatAddr", "hwCurLoc", "hwCurC0", "hwCurC1",
	895	"vidInFormat", "vidInStatus", "vidSerialParallelPort","vidInXDecimDeltas",
	896
	897	/* 0x080 */
	898	"vidInDecimInitErrs","vidInYDecimDeltas","vidPixelBufThold","vidChromaMin",
	899	"vidChromaMax", "vidCurrentLine","vidScreenSize","vidOverlayStartCoords",
	900	"vidOverlayEndScreenCoord","vidOverlayDudx","vidOverlayDudxOffsetSrcWidth","vidOverlayDvdy",
	901	"vga[b0]", "vga[b4]", "vga[b8]", "vga[bc]",
	902
	903	/* 0x0c0 */
	904	"vga[c0]", "vga[c4]", "vga[c8]", "vga[cc]",
	905	"vga[d0]", "vga[d4]", "vga[d8]", "vga[dc]",
	906	"vidOverlayDvdyOffset","vidDesktopStartAddr","vidDesktopOverlayStride","vidInAddr0",
	907	"vidInAddr1", "vidInAddr2", "vidInStride", "vidCurrOverlayStartAddr"
	908	};
	909
	910
	911
	912	/*************************************
	913	*
	914	* Voodoo Banshee AGP space registers
	915	*
	916	*************************************/
	917
	918	/* 0x000 */
	919	#define agpReqSize (0x000/4) /* */
	920	#define agpHostAddressLow (0x004/4) /* */
	921	#define agpHostAddressHigh (0x008/4) /* */
	922	#define agpGraphicsAddress (0x00c/4) /* */
	923	#define agpGraphicsStride (0x010/4) /* */
	924	#define agpMoveCMD (0x014/4) /* */
	925	#define cmdBaseAddr0 (0x020/4) /* */
	926	#define cmdBaseSize0 (0x024/4) /* */
	927	#define cmdBump0 (0x028/4) /* */
	928	#define cmdRdPtrL0 (0x02c/4) /* */
	929	#define cmdRdPtrH0 (0x030/4) /* */
	930	#define cmdAMin0 (0x034/4) /* */
	931	#define cmdAMax0 (0x03c/4) /* */
	932
	933	/* 0x040 */
	934	#define cmdFifoDepth0 (0x044/4) /* */
	935	#define cmdHoleCnt0 (0x048/4) /* */
	936	#define cmdBaseAddr1 (0x050/4) /* */
	937	#define cmdBaseSize1 (0x054/4) /* */
	938	#define cmdBump1 (0x058/4) /* */
	939	#define cmdRdPtrL1 (0x05c/4) /* */
	940	#define cmdRdPtrH1 (0x060/4) /* */
	941	#define cmdAMin1 (0x064/4) /* */
	942	#define cmdAMax1 (0x06c/4) /* */
	943	#define cmdFifoDepth1 (0x074/4) /* */
	944	#define cmdHoleCnt1 (0x078/4) /* */
	945
	946	/* 0x080 */
	947	#define cmdFifoThresh (0x080/4) /* */
	948	#define cmdHoleInt (0x084/4) /* */
	949
	950	/* 0x100 */
	951	#define yuvBaseAddress (0x100/4) /* */
	952	#define yuvStride (0x104/4) /* */
	953	#define crc1 (0x120/4) /* */
	954	#define crc2 (0x130/4) /* */
	955
	956
	957
	958	/*************************************
	959	*
	960	* Register string table for debug
	961	*
	962	*************************************/
	963
	964	static const char *const banshee_agp_reg_name[] =
	965	{
	966	/* 0x000 */
	967	"agpReqSize", "agpHostAddressLow","agpHostAddressHigh","agpGraphicsAddress",
	968	"agpGraphicsStride","agpMoveCMD","reserved18", "reserved1c",
	969	"cmdBaseAddr0", "cmdBaseSize0", "cmdBump0", "cmdRdPtrL0",
	970	"cmdRdPtrH0", "cmdAMin0", "reserved38", "cmdAMax0",
	971
	972	/* 0x040 */
	973	"reserved40", "cmdFifoDepth0","cmdHoleCnt0", "reserved4c",
	974	"cmdBaseAddr1", "cmdBaseSize1", "cmdBump1", "cmdRdPtrL1",
	975	"cmdRdPtrH1", "cmdAMin1", "reserved68", "cmdAMax1",
	976	"reserved70", "cmdFifoDepth1","cmdHoleCnt1", "reserved7c",
	977
	978	/* 0x080 */
	979	"cmdFifoThresh","cmdHoleInt", "reserved88", "reserved8c",
	980	"reserved90", "reserved94", "reserved98", "reserved9c",
	981	"reserveda0", "reserveda4", "reserveda8", "reservedac",
	982	"reservedb0", "reservedb4", "reservedb8", "reservedbc",
	983
	984	/* 0x0c0 */
	985	"reservedc0", "reservedc4", "reservedc8", "reservedcc",
	986	"reservedd0", "reservedd4", "reservedd8", "reserveddc",
	987	"reservede0", "reservede4", "reservede8", "reservedec",
	988	"reservedf0", "reservedf4", "reservedf8", "reservedfc",
	989
	990	/* 0x100 */
	991	"yuvBaseAddress","yuvStride", "reserved108", "reserved10c",
	992	"reserved110", "reserved114", "reserved118", "reserved11c",
	993	"crc1", "reserved124", "reserved128", "reserved12c",
	994	"crc2", "reserved134", "reserved138", "reserved13c"
	995	};
	996
	997
	998
	999	/*************************************
	1000	*
	1001	* Dithering tables
	1002	*
	1003	*************************************/
	1004
	1005	static const UINT8 dither_matrix_4x4[16] =
	1006	{
	1007	0, 8, 2, 10,
	1008	12, 4, 14, 6,
	1009	3, 11, 1, 9,
	1010	15, 7, 13, 5
	1011	};
	1012
	1013	static const UINT8 dither_matrix_2x2[16] =
	1014	{
	1015	2, 10, 2, 10,
	1016	14, 6, 14, 6,
	1017	2, 10, 2, 10,
	1018	14, 6, 14, 6
	1019	};
	1020
	1021
	1022
	1023	/*************************************
	1024	*
	1025	* Macros for extracting pixels
	1026	*
	1027	*************************************/
	1028
	1029	#define EXTRACT_565_TO_888(val, a, b, c) \
	1030	(a) = (((val) >> 8) & 0xf8) \| (((val) >> 13) & 0x07); \
	1031	(b) = (((val) >> 3) & 0xfc) \| (((val) >> 9) & 0x03); \
	1032	(c) = (((val) << 3) & 0xf8) \| (((val) >> 2) & 0x07);
	1033	#define EXTRACT_x555_TO_888(val, a, b, c) \
	1034	(a) = (((val) >> 7) & 0xf8) \| (((val) >> 12) & 0x07); \
	1035	(b) = (((val) >> 2) & 0xf8) \| (((val) >> 7) & 0x07); \
	1036	(c) = (((val) << 3) & 0xf8) \| (((val) >> 2) & 0x07);
	1037	#define EXTRACT_555x_TO_888(val, a, b, c) \
	1038	(a) = (((val) >> 8) & 0xf8) \| (((val) >> 13) & 0x07); \
	1039	(b) = (((val) >> 3) & 0xf8) \| (((val) >> 8) & 0x07); \
	1040	(c) = (((val) << 2) & 0xf8) \| (((val) >> 3) & 0x07);
	1041	#define EXTRACT_1555_TO_8888(val, a, b, c, d) \
	1042	(a) = ((INT16)(val) >> 15) & 0xff; \
	1043	EXTRACT_x555_TO_888(val, b, c, d)
	1044	#define EXTRACT_5551_TO_8888(val, a, b, c, d) \
	1045	EXTRACT_555x_TO_888(val, a, b, c) \
	1046	(d) = ((val) & 0x0001) ? 0xff : 0x00;
	1047	#define EXTRACT_x888_TO_888(val, a, b, c) \
	1048	(a) = ((val) >> 16) & 0xff; \
	1049	(b) = ((val) >> 8) & 0xff; \
	1050	(c) = ((val) >> 0) & 0xff;
	1051	#define EXTRACT_888x_TO_888(val, a, b, c) \
	1052	(a) = ((val) >> 24) & 0xff; \
	1053	(b) = ((val) >> 16) & 0xff; \
	1054	(c) = ((val) >> 8) & 0xff;
	1055	#define EXTRACT_8888_TO_8888(val, a, b, c, d) \
	1056	(a) = ((val) >> 24) & 0xff; \
	1057	(b) = ((val) >> 16) & 0xff; \
	1058	(c) = ((val) >> 8) & 0xff; \
	1059	(d) = ((val) >> 0) & 0xff;
	1060	#define EXTRACT_4444_TO_8888(val, a, b, c, d) \
	1061	(a) = (((val) >> 8) & 0xf0) \| (((val) >> 12) & 0x0f); \
	1062	(b) = (((val) >> 4) & 0xf0) \| (((val) >> 8) & 0x0f); \
	1063	(c) = (((val) >> 0) & 0xf0) \| (((val) >> 4) & 0x0f); \
	1064	(d) = (((val) << 4) & 0xf0) \| (((val) >> 0) & 0x0f);
	1065	#define EXTRACT_332_TO_888(val, a, b, c) \
	1066	(a) = (((val) >> 0) & 0xe0) \| (((val) >> 3) & 0x1c) \| (((val) >> 6) & 0x03); \
	1067	(b) = (((val) << 3) & 0xe0) \| (((val) >> 0) & 0x1c) \| (((val) >> 3) & 0x03); \
	1068	(c) = (((val) << 6) & 0xc0) \| (((val) << 4) & 0x30) \| (((val) << 2) & 0x0c) \| (((val) << 0) & 0x03);
	1069
	1070
	1071	/*************************************
	1072	*
	1073	* Misc. macros
	1074	*
	1075	*************************************/
	1076
	1077	/* macro for clamping a value between minimum and maximum values */
	1078	#define CLAMP(val,min,max) do { if ((val) < (min)) { (val) = (min); } else if ((val) > (max)) { (val) = (max); } } while (0)
	1079
	1080	/* macro to compute the base 2 log for LOD calculations */
	1081	#define LOGB2(x) (log((double)(x)) / log(2.0))
	1082
	1083
	1084
	1085	/*************************************
	1086	*
	1087	* Macros for extracting bitfields
	1088	*
	1089	*************************************/
	1090
	1091	#define INITEN_ENABLE_HW_INIT(val) (((val) >> 0) & 1)
	1092	#define INITEN_ENABLE_PCI_FIFO(val) (((val) >> 1) & 1)
	1093	#define INITEN_REMAP_INIT_TO_DAC(val) (((val) >> 2) & 1)
	1094	#define INITEN_ENABLE_SNOOP0(val) (((val) >> 4) & 1)
	1095	#define INITEN_SNOOP0_MEMORY_MATCH(val) (((val) >> 5) & 1)
	1096	#define INITEN_SNOOP0_READWRITE_MATCH(val) (((val) >> 6) & 1)
	1097	#define INITEN_ENABLE_SNOOP1(val) (((val) >> 7) & 1)
	1098	#define INITEN_SNOOP1_MEMORY_MATCH(val) (((val) >> 8) & 1)
	1099	#define INITEN_SNOOP1_READWRITE_MATCH(val) (((val) >> 9) & 1)
	1100	#define INITEN_SLI_BUS_OWNER(val) (((val) >> 10) & 1)
	1101	#define INITEN_SLI_ODD_EVEN(val) (((val) >> 11) & 1)
	1102	#define INITEN_SECONDARY_REV_ID(val) (((val) >> 12) & 0xf) /* voodoo 2 only */
	1103	#define INITEN_MFCTR_FAB_ID(val) (((val) >> 16) & 0xf) /* voodoo 2 only */
	1104	#define INITEN_ENABLE_PCI_INTERRUPT(val) (((val) >> 20) & 1) /* voodoo 2 only */
	1105	#define INITEN_PCI_INTERRUPT_TIMEOUT(val) (((val) >> 21) & 1) /* voodoo 2 only */
	1106	#define INITEN_ENABLE_NAND_TREE_TEST(val) (((val) >> 22) & 1) /* voodoo 2 only */
	1107	#define INITEN_ENABLE_SLI_ADDRESS_SNOOP(val) (((val) >> 23) & 1) /* voodoo 2 only */
	1108	#define INITEN_SLI_SNOOP_ADDRESS(val) (((val) >> 24) & 0xff) /* voodoo 2 only */
	1109
	1110	#define FBZCP_CC_RGBSELECT(val) (((val) >> 0) & 3)
	1111	#define FBZCP_CC_ASELECT(val) (((val) >> 2) & 3)
	1112	#define FBZCP_CC_LOCALSELECT(val) (((val) >> 4) & 1)
	1113	#define FBZCP_CCA_LOCALSELECT(val) (((val) >> 5) & 3)
	1114	#define FBZCP_CC_LOCALSELECT_OVERRIDE(val) (((val) >> 7) & 1)
	1115	#define FBZCP_CC_ZERO_OTHER(val) (((val) >> 8) & 1)
	1116	#define FBZCP_CC_SUB_CLOCAL(val) (((val) >> 9) & 1)
	1117	#define FBZCP_CC_MSELECT(val) (((val) >> 10) & 7)
	1118	#define FBZCP_CC_REVERSE_BLEND(val) (((val) >> 13) & 1)
	1119	#define FBZCP_CC_ADD_ACLOCAL(val) (((val) >> 14) & 3)
	1120	#define FBZCP_CC_INVERT_OUTPUT(val) (((val) >> 16) & 1)
	1121	#define FBZCP_CCA_ZERO_OTHER(val) (((val) >> 17) & 1)
	1122	#define FBZCP_CCA_SUB_CLOCAL(val) (((val) >> 18) & 1)
	1123	#define FBZCP_CCA_MSELECT(val) (((val) >> 19) & 7)
	1124	#define FBZCP_CCA_REVERSE_BLEND(val) (((val) >> 22) & 1)
	1125	#define FBZCP_CCA_ADD_ACLOCAL(val) (((val) >> 23) & 3)
	1126	#define FBZCP_CCA_INVERT_OUTPUT(val) (((val) >> 25) & 1)
	1127	#define FBZCP_CCA_SUBPIXEL_ADJUST(val) (((val) >> 26) & 1)
	1128	#define FBZCP_TEXTURE_ENABLE(val) (((val) >> 27) & 1)
	1129	#define FBZCP_RGBZW_CLAMP(val) (((val) >> 28) & 1) /* voodoo 2 only */
	1130	#define FBZCP_ANTI_ALIAS(val) (((val) >> 29) & 1) /* voodoo 2 only */
	1131
	1132	#define ALPHAMODE_ALPHATEST(val) (((val) >> 0) & 1)
	1133	#define ALPHAMODE_ALPHAFUNCTION(val) (((val) >> 1) & 7)
	1134	#define ALPHAMODE_ALPHABLEND(val) (((val) >> 4) & 1)
	1135	#define ALPHAMODE_ANTIALIAS(val) (((val) >> 5) & 1)
	1136	#define ALPHAMODE_SRCRGBBLEND(val) (((val) >> 8) & 15)
	1137	#define ALPHAMODE_DSTRGBBLEND(val) (((val) >> 12) & 15)
	1138	#define ALPHAMODE_SRCALPHABLEND(val) (((val) >> 16) & 15)
	1139	#define ALPHAMODE_DSTALPHABLEND(val) (((val) >> 20) & 15)
	1140	#define ALPHAMODE_ALPHAREF(val) (((val) >> 24) & 0xff)
	1141
	1142	#define FOGMODE_ENABLE_FOG(val) (((val) >> 0) & 1)
	1143	#define FOGMODE_FOG_ADD(val) (((val) >> 1) & 1)
	1144	#define FOGMODE_FOG_MULT(val) (((val) >> 2) & 1)
	1145	#define FOGMODE_FOG_ZALPHA(val) (((val) >> 3) & 3)
	1146	#define FOGMODE_FOG_CONSTANT(val) (((val) >> 5) & 1)
	1147	#define FOGMODE_FOG_DITHER(val) (((val) >> 6) & 1) /* voodoo 2 only */
	1148	#define FOGMODE_FOG_ZONES(val) (((val) >> 7) & 1) /* voodoo 2 only */
	1149
	1150	#define FBZMODE_ENABLE_CLIPPING(val) (((val) >> 0) & 1)
	1151	#define FBZMODE_ENABLE_CHROMAKEY(val) (((val) >> 1) & 1)
	1152	#define FBZMODE_ENABLE_STIPPLE(val) (((val) >> 2) & 1)
	1153	#define FBZMODE_WBUFFER_SELECT(val) (((val) >> 3) & 1)
	1154	#define FBZMODE_ENABLE_DEPTHBUF(val) (((val) >> 4) & 1)
	1155	#define FBZMODE_DEPTH_FUNCTION(val) (((val) >> 5) & 7)
	1156	#define FBZMODE_ENABLE_DITHERING(val) (((val) >> 8) & 1)
	1157	#define FBZMODE_RGB_BUFFER_MASK(val) (((val) >> 9) & 1)
	1158	#define FBZMODE_AUX_BUFFER_MASK(val) (((val) >> 10) & 1)
	1159	#define FBZMODE_DITHER_TYPE(val) (((val) >> 11) & 1)
	1160	#define FBZMODE_STIPPLE_PATTERN(val) (((val) >> 12) & 1)
	1161	#define FBZMODE_ENABLE_ALPHA_MASK(val) (((val) >> 13) & 1)
	1162	#define FBZMODE_DRAW_BUFFER(val) (((val) >> 14) & 3)
	1163	#define FBZMODE_ENABLE_DEPTH_BIAS(val) (((val) >> 16) & 1)
	1164	#define FBZMODE_Y_ORIGIN(val) (((val) >> 17) & 1)
	1165	#define FBZMODE_ENABLE_ALPHA_PLANES(val) (((val) >> 18) & 1)
	1166	#define FBZMODE_ALPHA_DITHER_SUBTRACT(val) (((val) >> 19) & 1)
	1167	#define FBZMODE_DEPTH_SOURCE_COMPARE(val) (((val) >> 20) & 1)
	1168	#define FBZMODE_DEPTH_FLOAT_SELECT(val) (((val) >> 21) & 1) /* voodoo 2 only */
	1169
	1170	#define LFBMODE_WRITE_FORMAT(val) (((val) >> 0) & 0xf)
	1171	#define LFBMODE_WRITE_BUFFER_SELECT(val) (((val) >> 4) & 3)
	1172	#define LFBMODE_READ_BUFFER_SELECT(val) (((val) >> 6) & 3)
	1173	#define LFBMODE_ENABLE_PIXEL_PIPELINE(val) (((val) >> 8) & 1)
	1174	#define LFBMODE_RGBA_LANES(val) (((val) >> 9) & 3)
	1175	#define LFBMODE_WORD_SWAP_WRITES(val) (((val) >> 11) & 1)
	1176	#define LFBMODE_BYTE_SWIZZLE_WRITES(val) (((val) >> 12) & 1)
	1177	#define LFBMODE_Y_ORIGIN(val) (((val) >> 13) & 1)
	1178	#define LFBMODE_WRITE_W_SELECT(val) (((val) >> 14) & 1)
	1179	#define LFBMODE_WORD_SWAP_READS(val) (((val) >> 15) & 1)
	1180	#define LFBMODE_BYTE_SWIZZLE_READS(val) (((val) >> 16) & 1)
	1181
	1182	#define CHROMARANGE_BLUE_EXCLUSIVE(val) (((val) >> 24) & 1)
	1183	#define CHROMARANGE_GREEN_EXCLUSIVE(val) (((val) >> 25) & 1)
	1184	#define CHROMARANGE_RED_EXCLUSIVE(val) (((val) >> 26) & 1)
	1185	#define CHROMARANGE_UNION_MODE(val) (((val) >> 27) & 1)
	1186	#define CHROMARANGE_ENABLE(val) (((val) >> 28) & 1)
	1187
	1188	#define FBIINIT0_VGA_PASSTHRU(val) (((val) >> 0) & 1)
	1189	#define FBIINIT0_GRAPHICS_RESET(val) (((val) >> 1) & 1)
	1190	#define FBIINIT0_FIFO_RESET(val) (((val) >> 2) & 1)
	1191	#define FBIINIT0_SWIZZLE_REG_WRITES(val) (((val) >> 3) & 1)
	1192	#define FBIINIT0_STALL_PCIE_FOR_HWM(val) (((val) >> 4) & 1)
	1193	#define FBIINIT0_PCI_FIFO_LWM(val) (((val) >> 6) & 0x1f)
	1194	#define FBIINIT0_LFB_TO_MEMORY_FIFO(val) (((val) >> 11) & 1)
	1195	#define FBIINIT0_TEXMEM_TO_MEMORY_FIFO(val) (((val) >> 12) & 1)
	1196	#define FBIINIT0_ENABLE_MEMORY_FIFO(val) (((val) >> 13) & 1)
	1197	#define FBIINIT0_MEMORY_FIFO_HWM(val) (((val) >> 14) & 0x7ff)
	1198	#define FBIINIT0_MEMORY_FIFO_BURST(val) (((val) >> 25) & 0x3f)
	1199
	1200	#define FBIINIT1_PCI_DEV_FUNCTION(val) (((val) >> 0) & 1)
	1201	#define FBIINIT1_PCI_WRITE_WAIT_STATES(val) (((val) >> 1) & 1)
	1202	#define FBIINIT1_MULTI_SST1(val) (((val) >> 2) & 1) /* not on voodoo 2 */
	1203	#define FBIINIT1_ENABLE_LFB(val) (((val) >> 3) & 1)
	1204	#define FBIINIT1_X_VIDEO_TILES(val) (((val) >> 4) & 0xf)
	1205	#define FBIINIT1_VIDEO_TIMING_RESET(val) (((val) >> 8) & 1)
	1206	#define FBIINIT1_SOFTWARE_OVERRIDE(val) (((val) >> 9) & 1)
	1207	#define FBIINIT1_SOFTWARE_HSYNC(val) (((val) >> 10) & 1)
	1208	#define FBIINIT1_SOFTWARE_VSYNC(val) (((val) >> 11) & 1)
	1209	#define FBIINIT1_SOFTWARE_BLANK(val) (((val) >> 12) & 1)
	1210	#define FBIINIT1_DRIVE_VIDEO_TIMING(val) (((val) >> 13) & 1)
	1211	#define FBIINIT1_DRIVE_VIDEO_BLANK(val) (((val) >> 14) & 1)
	1212	#define FBIINIT1_DRIVE_VIDEO_SYNC(val) (((val) >> 15) & 1)
	1213	#define FBIINIT1_DRIVE_VIDEO_DCLK(val) (((val) >> 16) & 1)
	1214	#define FBIINIT1_VIDEO_TIMING_VCLK(val) (((val) >> 17) & 1)
	1215	#define FBIINIT1_VIDEO_CLK_2X_DELAY(val) (((val) >> 18) & 3)
	1216	#define FBIINIT1_VIDEO_TIMING_SOURCE(val) (((val) >> 20) & 3)
	1217	#define FBIINIT1_ENABLE_24BPP_OUTPUT(val) (((val) >> 22) & 1)
	1218	#define FBIINIT1_ENABLE_SLI(val) (((val) >> 23) & 1)
	1219	#define FBIINIT1_X_VIDEO_TILES_BIT5(val) (((val) >> 24) & 1) /* voodoo 2 only */
	1220	#define FBIINIT1_ENABLE_EDGE_FILTER(val) (((val) >> 25) & 1)
	1221	#define FBIINIT1_INVERT_VID_CLK_2X(val) (((val) >> 26) & 1)
	1222	#define FBIINIT1_VID_CLK_2X_SEL_DELAY(val) (((val) >> 27) & 3)
	1223	#define FBIINIT1_VID_CLK_DELAY(val) (((val) >> 29) & 3)
	1224	#define FBIINIT1_DISABLE_FAST_READAHEAD(val) (((val) >> 31) & 1)
	1225
	1226	#define FBIINIT2_DISABLE_DITHER_SUB(val) (((val) >> 0) & 1)
	1227	#define FBIINIT2_DRAM_BANKING(val) (((val) >> 1) & 1)
	1228	#define FBIINIT2_ENABLE_TRIPLE_BUF(val) (((val) >> 4) & 1)
	1229	#define FBIINIT2_ENABLE_FAST_RAS_READ(val) (((val) >> 5) & 1)
	1230	#define FBIINIT2_ENABLE_GEN_DRAM_OE(val) (((val) >> 6) & 1)
	1231	#define FBIINIT2_ENABLE_FAST_READWRITE(val) (((val) >> 7) & 1)
	1232	#define FBIINIT2_ENABLE_PASSTHRU_DITHER(val) (((val) >> 8) & 1)
	1233	#define FBIINIT2_SWAP_BUFFER_ALGORITHM(val) (((val) >> 9) & 3)
	1234	#define FBIINIT2_VIDEO_BUFFER_OFFSET(val) (((val) >> 11) & 0x1ff)
	1235	#define FBIINIT2_ENABLE_DRAM_BANKING(val) (((val) >> 20) & 1)
	1236	#define FBIINIT2_ENABLE_DRAM_READ_FIFO(val) (((val) >> 21) & 1)
	1237	#define FBIINIT2_ENABLE_DRAM_REFRESH(val) (((val) >> 22) & 1)
	1238	#define FBIINIT2_REFRESH_LOAD_VALUE(val) (((val) >> 23) & 0x1ff)
	1239
	1240	#define FBIINIT3_TRI_REGISTER_REMAP(val) (((val) >> 0) & 1)
	1241	#define FBIINIT3_VIDEO_FIFO_THRESH(val) (((val) >> 1) & 0x1f)
	1242	#define FBIINIT3_DISABLE_TMUS(val) (((val) >> 6) & 1)
	1243	#define FBIINIT3_FBI_MEMORY_TYPE(val) (((val) >> 8) & 7)
	1244	#define FBIINIT3_VGA_PASS_RESET_VAL(val) (((val) >> 11) & 1)
	1245	#define FBIINIT3_HARDCODE_PCI_BASE(val) (((val) >> 12) & 1)
	1246	#define FBIINIT3_FBI2TREX_DELAY(val) (((val) >> 13) & 0xf)
	1247	#define FBIINIT3_TREX2FBI_DELAY(val) (((val) >> 17) & 0x1f)
	1248	#define FBIINIT3_YORIGIN_SUBTRACT(val) (((val) >> 22) & 0x3ff)
	1249
	1250	#define FBIINIT4_PCI_READ_WAITS(val) (((val) >> 0) & 1)
	1251	#define FBIINIT4_ENABLE_LFB_READAHEAD(val) (((val) >> 1) & 1)
	1252	#define FBIINIT4_MEMORY_FIFO_LWM(val) (((val) >> 2) & 0x3f)
	1253	#define FBIINIT4_MEMORY_FIFO_START_ROW(val) (((val) >> 8) & 0x3ff)
	1254	#define FBIINIT4_MEMORY_FIFO_STOP_ROW(val) (((val) >> 18) & 0x3ff)
	1255	#define FBIINIT4_VIDEO_CLOCKING_DELAY(val) (((val) >> 29) & 7) /* voodoo 2 only */
	1256
	1257	#define FBIINIT5_DISABLE_PCI_STOP(val) (((val) >> 0) & 1) /* voodoo 2 only */
	1258	#define FBIINIT5_PCI_SLAVE_SPEED(val) (((val) >> 1) & 1) /* voodoo 2 only */
	1259	#define FBIINIT5_DAC_DATA_OUTPUT_WIDTH(val) (((val) >> 2) & 1) /* voodoo 2 only */
	1260	#define FBIINIT5_DAC_DATA_17_OUTPUT(val) (((val) >> 3) & 1) /* voodoo 2 only */
	1261	#define FBIINIT5_DAC_DATA_18_OUTPUT(val) (((val) >> 4) & 1) /* voodoo 2 only */
	1262	#define FBIINIT5_GENERIC_STRAPPING(val) (((val) >> 5) & 0xf) /* voodoo 2 only */
	1263	#define FBIINIT5_BUFFER_ALLOCATION(val) (((val) >> 9) & 3) /* voodoo 2 only */
	1264	#define FBIINIT5_DRIVE_VID_CLK_SLAVE(val) (((val) >> 11) & 1) /* voodoo 2 only */
	1265	#define FBIINIT5_DRIVE_DAC_DATA_16(val) (((val) >> 12) & 1) /* voodoo 2 only */
	1266	#define FBIINIT5_VCLK_INPUT_SELECT(val) (((val) >> 13) & 1) /* voodoo 2 only */
	1267	#define FBIINIT5_MULTI_CVG_DETECT(val) (((val) >> 14) & 1) /* voodoo 2 only */
	1268	#define FBIINIT5_SYNC_RETRACE_READS(val) (((val) >> 15) & 1) /* voodoo 2 only */
	1269	#define FBIINIT5_ENABLE_RHBORDER_COLOR(val) (((val) >> 16) & 1) /* voodoo 2 only */
	1270	#define FBIINIT5_ENABLE_LHBORDER_COLOR(val) (((val) >> 17) & 1) /* voodoo 2 only */
	1271	#define FBIINIT5_ENABLE_BVBORDER_COLOR(val) (((val) >> 18) & 1) /* voodoo 2 only */
	1272	#define FBIINIT5_ENABLE_TVBORDER_COLOR(val) (((val) >> 19) & 1) /* voodoo 2 only */
	1273	#define FBIINIT5_DOUBLE_HORIZ(val) (((val) >> 20) & 1) /* voodoo 2 only */
	1274	#define FBIINIT5_DOUBLE_VERT(val) (((val) >> 21) & 1) /* voodoo 2 only */
	1275	#define FBIINIT5_ENABLE_16BIT_GAMMA(val) (((val) >> 22) & 1) /* voodoo 2 only */
	1276	#define FBIINIT5_INVERT_DAC_HSYNC(val) (((val) >> 23) & 1) /* voodoo 2 only */
	1277	#define FBIINIT5_INVERT_DAC_VSYNC(val) (((val) >> 24) & 1) /* voodoo 2 only */
	1278	#define FBIINIT5_ENABLE_24BIT_DACDATA(val) (((val) >> 25) & 1) /* voodoo 2 only */
	1279	#define FBIINIT5_ENABLE_INTERLACING(val) (((val) >> 26) & 1) /* voodoo 2 only */
	1280	#define FBIINIT5_DAC_DATA_18_CONTROL(val) (((val) >> 27) & 1) /* voodoo 2 only */
	1281	#define FBIINIT5_RASTERIZER_UNIT_MODE(val) (((val) >> 30) & 3) /* voodoo 2 only */
	1282
	1283	#define FBIINIT6_WINDOW_ACTIVE_COUNTER(val) (((val) >> 0) & 7) /* voodoo 2 only */
	1284	#define FBIINIT6_WINDOW_DRAG_COUNTER(val) (((val) >> 3) & 0x1f) /* voodoo 2 only */
	1285	#define FBIINIT6_SLI_SYNC_MASTER(val) (((val) >> 8) & 1) /* voodoo 2 only */
	1286	#define FBIINIT6_DAC_DATA_22_OUTPUT(val) (((val) >> 9) & 3) /* voodoo 2 only */
	1287	#define FBIINIT6_DAC_DATA_23_OUTPUT(val) (((val) >> 11) & 3) /* voodoo 2 only */
	1288	#define FBIINIT6_SLI_SYNCIN_OUTPUT(val) (((val) >> 13) & 3) /* voodoo 2 only */
	1289	#define FBIINIT6_SLI_SYNCOUT_OUTPUT(val) (((val) >> 15) & 3) /* voodoo 2 only */
	1290	#define FBIINIT6_DAC_RD_OUTPUT(val) (((val) >> 17) & 3) /* voodoo 2 only */
	1291	#define FBIINIT6_DAC_WR_OUTPUT(val) (((val) >> 19) & 3) /* voodoo 2 only */
	1292	#define FBIINIT6_PCI_FIFO_LWM_RDY(val) (((val) >> 21) & 0x7f) /* voodoo 2 only */
	1293	#define FBIINIT6_VGA_PASS_N_OUTPUT(val) (((val) >> 28) & 3) /* voodoo 2 only */
	1294	#define FBIINIT6_X_VIDEO_TILES_BIT0(val) (((val) >> 30) & 1) /* voodoo 2 only */
	1295
	1296	#define FBIINIT7_GENERIC_STRAPPING(val) (((val) >> 0) & 0xff) /* voodoo 2 only */
	1297	#define FBIINIT7_CMDFIFO_ENABLE(val) (((val) >> 8) & 1) /* voodoo 2 only */
	1298	#define FBIINIT7_CMDFIFO_MEMORY_STORE(val) (((val) >> 9) & 1) /* voodoo 2 only */
	1299	#define FBIINIT7_DISABLE_CMDFIFO_HOLES(val) (((val) >> 10) & 1) /* voodoo 2 only */
	1300	#define FBIINIT7_CMDFIFO_READ_THRESH(val) (((val) >> 11) & 0x1f) /* voodoo 2 only */
	1301	#define FBIINIT7_SYNC_CMDFIFO_WRITES(val) (((val) >> 16) & 1) /* voodoo 2 only */
	1302	#define FBIINIT7_SYNC_CMDFIFO_READS(val) (((val) >> 17) & 1) /* voodoo 2 only */
	1303	#define FBIINIT7_RESET_PCI_PACKER(val) (((val) >> 18) & 1) /* voodoo 2 only */
	1304	#define FBIINIT7_ENABLE_CHROMA_STUFF(val) (((val) >> 19) & 1) /* voodoo 2 only */
	1305	#define FBIINIT7_CMDFIFO_PCI_TIMEOUT(val) (((val) >> 20) & 0x7f) /* voodoo 2 only */
	1306	#define FBIINIT7_ENABLE_TEXTURE_BURST(val) (((val) >> 27) & 1) /* voodoo 2 only */
	1307
	1308	#define TEXMODE_ENABLE_PERSPECTIVE(val) (((val) >> 0) & 1)
	1309	#define TEXMODE_MINIFICATION_FILTER(val) (((val) >> 1) & 1)
	1310	#define TEXMODE_MAGNIFICATION_FILTER(val) (((val) >> 2) & 1)
	1311	#define TEXMODE_CLAMP_NEG_W(val) (((val) >> 3) & 1)
	1312	#define TEXMODE_ENABLE_LOD_DITHER(val) (((val) >> 4) & 1)
	1313	#define TEXMODE_NCC_TABLE_SELECT(val) (((val) >> 5) & 1)
	1314	#define TEXMODE_CLAMP_S(val) (((val) >> 6) & 1)
	1315	#define TEXMODE_CLAMP_T(val) (((val) >> 7) & 1)
	1316	#define TEXMODE_FORMAT(val) (((val) >> 8) & 0xf)
	1317	#define TEXMODE_TC_ZERO_OTHER(val) (((val) >> 12) & 1)
	1318	#define TEXMODE_TC_SUB_CLOCAL(val) (((val) >> 13) & 1)
	1319	#define TEXMODE_TC_MSELECT(val) (((val) >> 14) & 7)
	1320	#define TEXMODE_TC_REVERSE_BLEND(val) (((val) >> 17) & 1)
	1321	#define TEXMODE_TC_ADD_ACLOCAL(val) (((val) >> 18) & 3)
	1322	#define TEXMODE_TC_INVERT_OUTPUT(val) (((val) >> 20) & 1)
	1323	#define TEXMODE_TCA_ZERO_OTHER(val) (((val) >> 21) & 1)
	1324	#define TEXMODE_TCA_SUB_CLOCAL(val) (((val) >> 22) & 1)
	1325	#define TEXMODE_TCA_MSELECT(val) (((val) >> 23) & 7)
	1326	#define TEXMODE_TCA_REVERSE_BLEND(val) (((val) >> 26) & 1)
	1327	#define TEXMODE_TCA_ADD_ACLOCAL(val) (((val) >> 27) & 3)
	1328	#define TEXMODE_TCA_INVERT_OUTPUT(val) (((val) >> 29) & 1)
	1329	#define TEXMODE_TRILINEAR(val) (((val) >> 30) & 1)
	1330	#define TEXMODE_SEQ_8_DOWNLD(val) (((val) >> 31) & 1)
	1331
	1332	#define TEXLOD_LODMIN(val) (((val) >> 0) & 0x3f)
	1333	#define TEXLOD_LODMAX(val) (((val) >> 6) & 0x3f)
	1334	#define TEXLOD_LODBIAS(val) (((val) >> 12) & 0x3f)
	1335	#define TEXLOD_LOD_ODD(val) (((val) >> 18) & 1)
	1336	#define TEXLOD_LOD_TSPLIT(val) (((val) >> 19) & 1)
	1337	#define TEXLOD_LOD_S_IS_WIDER(val) (((val) >> 20) & 1)
	1338	#define TEXLOD_LOD_ASPECT(val) (((val) >> 21) & 3)
	1339	#define TEXLOD_LOD_ZEROFRAC(val) (((val) >> 23) & 1)
	1340	#define TEXLOD_TMULTIBASEADDR(val) (((val) >> 24) & 1)
	1341	#define TEXLOD_TDATA_SWIZZLE(val) (((val) >> 25) & 1)
	1342	#define TEXLOD_TDATA_SWAP(val) (((val) >> 26) & 1)
	1343	#define TEXLOD_TDIRECT_WRITE(val) (((val) >> 27) & 1) /* Voodoo 2 only */
	1344
	1345	#define TEXDETAIL_DETAIL_MAX(val) (((val) >> 0) & 0xff)
	1346	#define TEXDETAIL_DETAIL_BIAS(val) (((val) >> 8) & 0x3f)
	1347	#define TEXDETAIL_DETAIL_SCALE(val) (((val) >> 14) & 7)
	1348	#define TEXDETAIL_RGB_MIN_FILTER(val) (((val) >> 17) & 1) /* Voodoo 2 only */
	1349	#define TEXDETAIL_RGB_MAG_FILTER(val) (((val) >> 18) & 1) /* Voodoo 2 only */
	1350	#define TEXDETAIL_ALPHA_MIN_FILTER(val) (((val) >> 19) & 1) /* Voodoo 2 only */
	1351	#define TEXDETAIL_ALPHA_MAG_FILTER(val) (((val) >> 20) & 1) /* Voodoo 2 only */
	1352	#define TEXDETAIL_SEPARATE_RGBA_FILTER(val) (((val) >> 21) & 1) /* Voodoo 2 only */
	1353
	1354	#define TREXINIT_SEND_TMU_CONFIG(val) (((val) >> 18) & 1)
	1355
	1356
	1357	/*************************************
	1358	*
16	1359	* Core types
17	1360	*
18	1361	*************************************/
r253151	r253152
21	1364	struct poly_extra_data;
22	1365
23	1366
	1367	struct rgba
	1368	{
	1369	#ifdef LSB_FIRST
	1370	UINT8 b, g, r, a;
	1371	#else
	1372	UINT8 a, r, g, b;
	1373	#endif
	1374	};
24	1375
25	1376
	1377	union voodoo_reg
	1378	{
	1379	INT32 i;
	1380	UINT32 u;
	1381	float f;
	1382	rgba rgb;
	1383	};
26	1384
	1385
	1386	typedef voodoo_reg rgb_union;
	1387
	1388
	1389	struct voodoo_stats
	1390	{
	1391	UINT8 lastkey; /* last key state */
	1392	UINT8 display; /* display stats? */
	1393	INT32 swaps; /* total swaps */
	1394	INT32 stalls; /* total stalls */
	1395	INT32 total_triangles; /* total triangles */
	1396	INT32 total_pixels_in; /* total pixels in */
	1397	INT32 total_pixels_out; /* total pixels out */
	1398	INT32 total_chroma_fail; /* total chroma fail */
	1399	INT32 total_zfunc_fail; /* total z func fail */
	1400	INT32 total_afunc_fail; /* total a func fail */
	1401	INT32 total_clipped; /* total clipped */
	1402	INT32 total_stippled; /* total stippled */
	1403	INT32 lfb_writes; /* LFB writes */
	1404	INT32 lfb_reads; /* LFB reads */
	1405	INT32 reg_writes; /* register writes */
	1406	INT32 reg_reads; /* register reads */
	1407	INT32 tex_writes; /* texture writes */
	1408	INT32 texture_mode[16]; /* 16 different texture modes */
	1409	UINT8 render_override; /* render override */
	1410	char buffer[1024]; /* string */
	1411	};
	1412
	1413
	1414	/* note that this structure is an even 64 bytes long */
	1415	struct stats_block
	1416	{
	1417	INT32 pixels_in; /* pixels in statistic */
	1418	INT32 pixels_out; /* pixels out statistic */
	1419	INT32 chroma_fail; /* chroma test fail statistic */
	1420	INT32 zfunc_fail; /* z function test fail statistic */
	1421	INT32 afunc_fail; /* alpha function test fail statistic */
	1422	INT32 clip_fail; /* clipping fail statistic */
	1423	INT32 stipple_count; /* stipple statistic */
	1424	INT32 filler[64/4 - 7]; /* pad this structure to 64 bytes */
	1425	};
	1426
	1427
	1428	struct fifo_state
	1429	{
	1430	UINT32 * base; /* base of the FIFO */
	1431	INT32 size; /* size of the FIFO */
	1432	INT32 in; /* input pointer */
	1433	INT32 out; /* output pointer */
	1434	};
	1435
	1436
	1437	struct cmdfifo_info
	1438	{
	1439	UINT8 enable; /* enabled? */
	1440	UINT8 count_holes; /* count holes? */
	1441	UINT32 base; /* base address in framebuffer RAM */
	1442	UINT32 end; /* end address in framebuffer RAM */
	1443	UINT32 rdptr; /* current read pointer */
	1444	UINT32 amin; /* minimum address */
	1445	UINT32 amax; /* maximum address */
	1446	UINT32 depth; /* current depth */
	1447	UINT32 holes; /* number of holes */
	1448	};
	1449
	1450
	1451	struct pci_state
	1452	{
	1453	fifo_state fifo; /* PCI FIFO */
	1454	UINT32 init_enable; /* initEnable value */
	1455	UINT8 stall_state; /* state of the system if we're stalled */
	1456	UINT8 op_pending; /* true if an operation is pending */
	1457	attotime op_end_time; /* time when the pending operation ends */
	1458	emu_timer * continue_timer; /* timer to use to continue processing */
	1459	UINT32 fifo_mem[642]; / memory backing the PCI FIFO */
	1460	};
	1461
	1462
	1463	struct ncc_table
	1464	{
	1465	UINT8 dirty; /* is the texel lookup dirty? */
	1466	voodoo_reg * reg; /* pointer to our registers */
	1467	INT32 ir[4], ig[4], ib[4]; /* I values for R,G,B */
	1468	INT32 qr[4], qg[4], qb[4]; /* Q values for R,G,B */
	1469	INT32 y[16]; /* Y values */
	1470	rgb_t * palette; /* pointer to associated RGB palette */
	1471	rgb_t * palettea; /* pointer to associated ARGB palette */
	1472	rgb_t texel[256]; /* texel lookup */
	1473	};
	1474
	1475
	1476	struct tmu_state
	1477	{
	1478	UINT8 * ram; /* pointer to our RAM */
	1479	UINT32 mask; /* mask to apply to pointers */
	1480	voodoo_reg * reg; /* pointer to our register base */
	1481	UINT32 regdirty; /* true if the LOD/mode/base registers have changed */
	1482
	1483	UINT32 texaddr_mask; /* mask for texture address */
	1484	UINT8 texaddr_shift; /* shift for texture address */
	1485
	1486	INT64 starts, startt; /* starting S,T (14.18) */
	1487	INT64 startw; /* starting W (2.30) */
	1488	INT64 dsdx, dtdx; /* delta S,T per X */
	1489	INT64 dwdx; /* delta W per X */
	1490	INT64 dsdy, dtdy; /* delta S,T per Y */
	1491	INT64 dwdy; /* delta W per Y */
	1492
	1493	INT32 lodmin, lodmax; /* min, max LOD values */
	1494	INT32 lodbias; /* LOD bias */
	1495	UINT32 lodmask; /* mask of available LODs */
	1496	UINT32 lodoffset[9]; /* offset of texture base for each LOD */
	1497	INT32 detailmax; /* detail clamp */
	1498	INT32 detailbias; /* detail bias */
	1499	UINT8 detailscale; /* detail scale */
	1500
	1501	UINT32 wmask; /* mask for the current texture width */
	1502	UINT32 hmask; /* mask for the current texture height */
	1503
	1504	UINT32 bilinear_mask; /* mask for bilinear resolution (0xf0 for V1, 0xff for V2) */
	1505
	1506	ncc_table ncc[2]; /* two NCC tables */
	1507
	1508	rgb_t * lookup; /* currently selected lookup */
	1509	rgb_t * texel[16]; /* texel lookups for each format */
	1510
	1511	rgb_t palette[256]; /* palette lookup table */
	1512	rgb_t palettea[256]; /* palette+alpha lookup table */
	1513	};
	1514
	1515
	1516	struct tmu_shared_state
	1517	{
	1518	rgb_t rgb332[256]; /* RGB 3-3-2 lookup table */
	1519	rgb_t alpha8[256]; /* alpha 8-bit lookup table */
	1520	rgb_t int8[256]; /* intensity 8-bit lookup table */
	1521	rgb_t ai44[256]; /* alpha, intensity 4-4 lookup table */
	1522
	1523	rgb_t rgb565[65536]; /* RGB 5-6-5 lookup table */
	1524	rgb_t argb1555[65536]; /* ARGB 1-5-5-5 lookup table */
	1525	rgb_t argb4444[65536]; /* ARGB 4-4-4-4 lookup table */
	1526	};
	1527
	1528
	1529	struct setup_vertex
	1530	{
	1531	float x, y; /* X, Y coordinates */
	1532	float a, r, g, b; /* A, R, G, B values */
	1533	float z, wb; /* Z and broadcast W values */
	1534	float w0, s0, t0; /* W, S, T for TMU 0 */
	1535	float w1, s1, t1; /* W, S, T for TMU 1 */
	1536	};
	1537
	1538
	1539	struct fbi_state
	1540	{
	1541	UINT8 * ram; /* pointer to frame buffer RAM */
	1542	UINT32 mask; /* mask to apply to pointers */
	1543	UINT32 rgboffs[3]; /* word offset to 3 RGB buffers */
	1544	UINT32 auxoffs; /* word offset to 1 aux buffer */
	1545
	1546	UINT8 frontbuf; /* front buffer index */
	1547	UINT8 backbuf; /* back buffer index */
	1548	UINT8 swaps_pending; /* number of pending swaps */
	1549	UINT8 video_changed; /* did the frontbuffer video change? */
	1550
	1551	UINT32 yorigin; /* Y origin subtract value */
	1552	UINT32 lfb_base; /* base of LFB in memory */
	1553	UINT8 lfb_stride; /* stride of LFB accesses in bits */
	1554
	1555	UINT32 width; /* width of current frame buffer */
	1556	UINT32 height; /* height of current frame buffer */
	1557	UINT32 xoffs; /* horizontal offset (back porch) */
	1558	UINT32 yoffs; /* vertical offset (back porch) */
	1559	UINT32 vsyncscan; /* vertical sync scanline */
	1560	UINT32 rowpixels; /* pixels per row */
	1561	UINT32 tile_width; /* width of video tiles */
	1562	UINT32 tile_height; /* height of video tiles */
	1563	UINT32 x_tiles; /* number of tiles in the X direction */
	1564
	1565	emu_timer * vblank_timer; /* VBLANK timer */
	1566	UINT8 vblank; /* VBLANK state */
	1567	UINT8 vblank_count; /* number of VBLANKs since last swap */
	1568	UINT8 vblank_swap_pending; /* a swap is pending, waiting for a vblank */
	1569	UINT8 vblank_swap; /* swap when we hit this count */
	1570	UINT8 vblank_dont_swap; /* don't actually swap when we hit this point */
	1571
	1572	/* triangle setup info */
	1573	UINT8 cheating_allowed; /* allow cheating? */
	1574	INT32 sign; /* triangle sign */
	1575	INT16 ax, ay; /* vertex A x,y (12.4) */
	1576	INT16 bx, by; /* vertex B x,y (12.4) */
	1577	INT16 cx, cy; /* vertex C x,y (12.4) */
	1578	INT32 startr, startg, startb, starta; /* starting R,G,B,A (12.12) */
	1579	INT32 startz; /* starting Z (20.12) */
	1580	INT64 startw; /* starting W (16.32) */
	1581	INT32 drdx, dgdx, dbdx, dadx; /* delta R,G,B,A per X */
	1582	INT32 dzdx; /* delta Z per X */
	1583	INT64 dwdx; /* delta W per X */
	1584	INT32 drdy, dgdy, dbdy, dady; /* delta R,G,B,A per Y */
	1585	INT32 dzdy; /* delta Z per Y */
	1586	INT64 dwdy; /* delta W per Y */
	1587
	1588	stats_block lfb_stats; /* LFB-access statistics */
	1589
	1590	UINT8 sverts; /* number of vertices ready */
	1591	setup_vertex svert[3]; /* 3 setup vertices */
	1592
	1593	fifo_state fifo; /* framebuffer memory fifo */
	1594	cmdfifo_info cmdfifo[2]; /* command FIFOs */
	1595
	1596	UINT8 fogblend[64]; /* 64-entry fog table */
	1597	UINT8 fogdelta[64]; /* 64-entry fog table */
	1598	UINT8 fogdelta_mask; /* mask for for delta (0xff for V1, 0xfc for V2) */
	1599
	1600	rgb_t pen[65536]; /* mapping from pixels to pens */
	1601	rgb_t clut[512]; /* clut gamma data */
	1602	UINT8 clut_dirty; /* do we need to recompute? */
	1603	};
	1604
	1605
	1606	struct dac_state
	1607	{
	1608	UINT8 reg[8]; /* 8 registers */
	1609	UINT8 read_result; /* pending read result */
	1610	};
	1611
	1612
	1613	struct raster_info
	1614	{
	1615	raster_info * next; /* pointer to next entry with the same hash */
	1616	poly_draw_scanline_func callback; /* callback pointer */
	1617	UINT8 is_generic; /* TRUE if this is one of the generic rasterizers */
	1618	UINT8 display; /* display index */
	1619	UINT32 hits; /* how many hits (pixels) we've used this for */
	1620	UINT32 polys; /* how many polys we've used this for */
	1621	UINT32 eff_color_path; /* effective fbzColorPath value */
	1622	UINT32 eff_alpha_mode; /* effective alphaMode value */
	1623	UINT32 eff_fog_mode; /* effective fogMode value */
	1624	UINT32 eff_fbz_mode; /* effective fbzMode value */
	1625	UINT32 eff_tex_mode_0; /* effective textureMode value for TMU #0 */
	1626	UINT32 eff_tex_mode_1; /* effective textureMode value for TMU #1 */
	1627	UINT32 hash;
	1628	};
	1629
	1630
	1631	struct poly_extra_data
	1632	{
	1633	voodoo_state * state; /* pointer back to the voodoo state */
	1634	raster_info * info; /* pointer to rasterizer information */
	1635
	1636	INT16 ax, ay; /* vertex A x,y (12.4) */
	1637	INT32 startr, startg, startb, starta; /* starting R,G,B,A (12.12) */
	1638	INT32 startz; /* starting Z (20.12) */
	1639	INT64 startw; /* starting W (16.32) */
	1640	INT32 drdx, dgdx, dbdx, dadx; /* delta R,G,B,A per X */
	1641	INT32 dzdx; /* delta Z per X */
	1642	INT64 dwdx; /* delta W per X */
	1643	INT32 drdy, dgdy, dbdy, dady; /* delta R,G,B,A per Y */
	1644	INT32 dzdy; /* delta Z per Y */
	1645	INT64 dwdy; /* delta W per Y */
	1646
	1647	INT64 starts0, startt0; /* starting S,T (14.18) */
	1648	INT64 startw0; /* starting W (2.30) */
	1649	INT64 ds0dx, dt0dx; /* delta S,T per X */
	1650	INT64 dw0dx; /* delta W per X */
	1651	INT64 ds0dy, dt0dy; /* delta S,T per Y */
	1652	INT64 dw0dy; /* delta W per Y */
	1653	INT32 lodbase0; /* used during rasterization */
	1654
	1655	INT64 starts1, startt1; /* starting S,T (14.18) */
	1656	INT64 startw1; /* starting W (2.30) */
	1657	INT64 ds1dx, dt1dx; /* delta S,T per X */
	1658	INT64 dw1dx; /* delta W per X */
	1659	INT64 ds1dy, dt1dy; /* delta S,T per Y */
	1660	INT64 dw1dy; /* delta W per Y */
	1661	INT32 lodbase1; /* used during rasterization */
	1662
	1663	UINT16 dither[16]; /* dither matrix, for fastfill */
	1664	};
	1665
	1666
	1667	struct banshee_info
	1668	{
	1669	UINT32 io[0x40]; /* I/O registers */
	1670	UINT32 agp[0x80]; /* AGP registers */
	1671	UINT8 vga[0x20]; /* VGA registers */
	1672	UINT8 crtc[0x27]; /* VGA CRTC registers */
	1673	UINT8 seq[0x05]; /* VGA sequencer registers */
	1674	UINT8 gc[0x05]; /* VGA graphics controller registers */
	1675	UINT8 att[0x15]; /* VGA attribute registers */
	1676	UINT8 attff; /* VGA attribute flip-flop */
	1677
	1678	UINT32 blt_regs[0x20]; /* 2D Blitter registers */
	1679	UINT32 blt_dst_base;
	1680	UINT32 blt_dst_x;
	1681	UINT32 blt_dst_y;
	1682	UINT32 blt_dst_width;
	1683	UINT32 blt_dst_height;
	1684	UINT32 blt_dst_stride;
	1685	UINT32 blt_dst_bpp;
	1686	UINT32 blt_cmd;
	1687	UINT32 blt_src_base;
	1688	UINT32 blt_src_x;
	1689	UINT32 blt_src_y;
	1690	UINT32 blt_src_width;
	1691	UINT32 blt_src_height;
	1692	UINT32 blt_src_stride;
	1693	UINT32 blt_src_bpp;
	1694	};
	1695
	1696
	1697	struct voodoo_state
	1698	{
	1699	UINT8 index; /* index of board */
	1700	voodoo_device device; / pointer to our containing device */
	1701	screen_device screen; / the screen we are acting on */
	1702	device_t cpu; / the CPU we interact with */
	1703	UINT8 type; /* type of system */
	1704	UINT8 chipmask; /* mask for which chips are available */
	1705	UINT32 freq; /* operating frequency */
	1706	attoseconds_t attoseconds_per_cycle; /* attoseconds per cycle */
	1707	UINT32 extra_cycles; /* extra cycles not yet accounted for */
	1708	int trigger; /* trigger used for stalling */
	1709
	1710	voodoo_reg reg[0x400]; /* raw registers */
	1711	const UINT8 * regaccess; /* register access array */
	1712	const char const regnames; /* register names array */
	1713	UINT8 alt_regmap; /* enable alternate register map? */
	1714
	1715	pci_state pci; /* PCI state */
	1716	dac_state dac; /* DAC state */
	1717
	1718	fbi_state fbi; /* FBI states */
	1719	tmu_state tmu[MAX_TMU]; /* TMU states */
	1720	tmu_shared_state tmushare; /* TMU shared state */
	1721	banshee_info banshee; /* Banshee state */
	1722
	1723	legacy_poly_manager * poly; /* polygon manager */
	1724	stats_block * thread_stats; /* per-thread statistics */
	1725
	1726	voodoo_stats stats; /* internal statistics */
	1727
	1728	offs_t last_status_pc; /* PC of last status description (for logging) */
	1729	UINT32 last_status_value; /* value of last status read (for logging) */
	1730
	1731	int next_rasterizer; /* next rasterizer index */
	1732	raster_info rasterizer[MAX_RASTERIZERS]; /* array of rasterizers */
	1733	raster_info * raster_hash[RASTER_HASH_SIZE]; /* hash table of rasterizers */
	1734
	1735	bool send_config;
	1736	UINT32 tmu_config;
	1737	};
	1738
	1739
	1740
27	1741	/*************************************
28	1742	*
29	1743	* Inline FIFO management
r253151	r253152
631	2345	} \
632	2346	while (0)
633	2347
634		static inline bool ATTR_FORCE_INLINE chromaKeyTest(voodoo_de~~vice~~ vd, stats_block stats, UINT32 fbzModeReg, rgbaint_t rgbaIntColor)
	2348	static inline bool ATTR_FORCE_INLINE chromaKeyTest(voodoo_state v, stats_block stats, UINT32 fbzModeReg, rgbaint_t rgbaIntColor)
635	2349	{
636	2350	if (FBZMODE_ENABLE_CHROMAKEY(fbzModeReg))
637	2351	{
638	2352	rgb_union color;
639	2353	color.u = (rgbaIntColor.get_a()<<24) \| (rgbaIntColor.get_r()<<16) \| (rgbaIntColor.get_g()<<8) \| rgbaIntColor.get_b();
640	2354	/* non-range version */
641		if (!CHROMARANGE_ENABLE(vd->reg[chromaRange].u))
	2355	if (!CHROMARANGE_ENABLE(v->reg[chromaRange].u))
642	2356	{
643		if (((color.u ^ vd->reg[chromaKey].u) & 0xffffff) == 0)
	2357	if (((color.u ^ v->reg[chromaKey].u) & 0xffffff) == 0)
644	2358	{
645	2359	stats->chroma_fail++;
646	2360	return false;
r253151	r253152
654	2368	int results;
655	2369
656	2370	/* check blue */
657		low = vd->reg[chromaKey].rgb.b;
658		high = vd->reg[chromaRange].rgb.b;
	2371	low = v->reg[chromaKey].rgb.b;
	2372	high = v->reg[chromaRange].rgb.b;
659	2373	test = color.rgb.b;
660	2374	results = (test >= low && test <= high);
661		results ^= CHROMARANGE_BLUE_EXCLUSIVE(vd->reg[chromaRange].u);
	2375	results ^= CHROMARANGE_BLUE_EXCLUSIVE(v->reg[chromaRange].u);
662	2376	results <<= 1;
663	2377
664	2378	/* check green */
665		low = vd->reg[chromaKey].rgb.g;
666		high = vd->reg[chromaRange].rgb.g;
	2379	low = v->reg[chromaKey].rgb.g;
	2380	high = v->reg[chromaRange].rgb.g;
667	2381	test = color.rgb.g;
668	2382	results \|= (test >= low && test <= high);
669		results ^= CHROMARANGE_GREEN_EXCLUSIVE(vd->reg[chromaRange].u);
	2383	results ^= CHROMARANGE_GREEN_EXCLUSIVE(v->reg[chromaRange].u);
670	2384	results <<= 1;
671	2385
672	2386	/* check red */
673		low = vd->reg[chromaKey].rgb.r;
674		high = vd->reg[chromaRange].rgb.r;
	2387	low = v->reg[chromaKey].rgb.r;
	2388	high = v->reg[chromaRange].rgb.r;
675	2389	test = color.rgb.r;
676	2390	results \|= (test >= low && test <= high);
677		results ^= CHROMARANGE_RED_EXCLUSIVE(vd->reg[chromaRange].u);
	2391	results ^= CHROMARANGE_RED_EXCLUSIVE(v->reg[chromaRange].u);
678	2392
679	2393	/* final result */
680		if (CHROMARANGE_UNION_MODE(vd->reg[chromaRange].u))
	2394	if (CHROMARANGE_UNION_MODE(v->reg[chromaRange].u))
681	2395	{
682	2396	if (results != 0)
683	2397	{
r253151	r253152
806	2520	} \
807	2521	while (0)
808	2522
809		static inline bool ATTR_FORCE_INLINE alphaTest(voodoo_de~~vice~~ vd, stats_block stats, UINT32 alphaModeReg, UINT8 alpha)
	2523	static inline bool ATTR_FORCE_INLINE alphaTest(voodoo_state v, stats_block stats, UINT32 alphaModeReg, UINT8 alpha)
810	2524	{
811	2525	if (ALPHAMODE_ALPHATEST(alphaModeReg))
812	2526	{
813		UINT8 alpharef = vd->reg[alphaMode].rgb.a;
	2527	UINT8 alpharef = v->reg[alphaMode].rgb.a;
814	2528	switch (ALPHAMODE_ALPHAFUNCTION(alphaModeReg))
815	2529	{
816	2530	case 0: /* alphaOP = never */
r253151	r253152
1353	3067	} \
1354	3068	while (0)
1355	3069
1356		static inline void ATTR_FORCE_INLINE applyFogging(voodoo_de~~vice~~ vd, UINT32 fogModeReg, UINT32 fbzCpReg, INT32 x, const UINT8 dither4, INT32 fogDepth,
	3070	static inline void ATTR_FORCE_INLINE applyFogging(voodoo_state v, UINT32 fogModeReg, UINT32 fbzCpReg, INT32 x, const UINT8 dither4, INT32 fogDepth,
1357	3071	rgbaint_t &color, INT32 iterz, INT64 iterw, UINT8 itera)
1358	3072	{
1359	3073	if (FOGMODE_ENABLE_FOG(fogModeReg))
r253151	r253152
1361	3075	UINT32 color_alpha = color.get_a();
1362	3076
1363	3077	/* constant fog bypasses everything else */
1364		rgbaint_t fogColorLocal(vd->reg[fogColor].u);
	3078	rgbaint_t fogColorLocal(v->reg[fogColor].u);
1365	3079
1366	3080	if (FOGMODE_FOG_CONSTANT(fogModeReg))
1367	3081	{
r253151	r253152
1405	3119	{
1406	3120	case 0: /* fog table */
1407	3121	{
1408		INT32 delta = vd->fbi.fogdelta[fogDepth >> 10];
	3122	INT32 delta = v->fbi.fogdelta[fogDepth >> 10];
1409	3123	INT32 deltaval;
1410	3124
1411	3125	/* perform the multiply against lower 8 bits of wfloat */
1412		deltaval = (delta & vd->fbi.fogdelta_mask) *
	3126	deltaval = (delta & v->fbi.fogdelta_mask) *
1413	3127	((fogDepth >> 2) & 0xff);
1414	3128
1415	3129	/* fog zones allow for negating this value */
r253151	r253152
1423	3137	deltaval >>= 4;
1424	3138
1425	3139	/* add to the blending factor */
1426		fogblend = vd->fbi.fogblend[fogDepth >> 10] + deltaval;
	3140	fogblend = v->fbi.fogblend[fogDepth >> 10] + deltaval;
1427	3141	break;
1428	3142	}
1429	3143
r253151	r253152
1828	3542	*
1829	3543	*************************************/
1830	3544
1831		#define PIXEL_PIPELINE_BEGIN(vd, STATS, XX, YY, FBZCOLORPATH, FBZMODE, ITERZ, ITERW) \
	3545	#define PIXEL_PIPELINE_BEGIN(VV, STATS, XX, YY, FBZCOLORPATH, FBZMODE, ITERZ, ITERW) \
1832	3546	do \
1833	3547	{ \
1834	3548	INT32 depthval, wfloat, fogdepth, biasdepth; \
r253151	r253152
1845	3559	/* rotate mode */ \
1846	3560	if (FBZMODE_STIPPLE_PATTERN(FBZMODE) == 0) \
1847	3561	{ \
1848		vd->reg[stipple].u = (vd->reg[stipple].u << 1) \| (vd->reg[stipple].u >> 31);\
1849		if ((vd->reg[stipple].u & 0x80000000) == 0) \
	3562	(VV)->reg[stipple].u = ((VV)->reg[stipple].u << 1) \| ((VV)->reg[stipple].u >> 31);\
	3563	if (((VV)->reg[stipple].u & 0x80000000) == 0) \
1850	3564	{ \
1851		vd->stats.total_stippled++; \
	3565	(VV)->stats.total_stippled++; \
1852	3566	goto skipdrawdepth; \
1853	3567	} \
1854	3568	} \
r253151	r253152
1857	3571	else \
1858	3572	{ \
1859	3573	int stipple_index = (((YY) & 3) << 3) \| (~(XX) & 7); \
1860		if (((vd->reg[stipple].u >> stipple_index) & 1) == 0) \
	3574	if ((((VV)->reg[stipple].u >> stipple_index) & 1) == 0) \
1861	3575	{ \
1862		vd->stats.total_stippled++; \
	3576	(VV)->stats.total_stippled++; \
1863	3577	goto skipdrawdepth; \
1864	3578	} \
1865	3579	} \
r253151	r253152
1883	3597	/* add the bias for fog selection*/ \
1884	3598	if (FBZMODE_ENABLE_DEPTH_BIAS(FBZMODE)) \
1885	3599	{ \
1886		fogdepth += (INT16)vd->reg[zaColor].u; \
	3600	fogdepth += (INT16)(VV)->reg[zaColor].u; \
1887	3601	CLAMP(fogdepth, 0, 0xffff); \
1888	3602	} \
1889	3603	\
r253151	r253152
1914	3628	biasdepth = depthval; \
1915	3629	if (FBZMODE_ENABLE_DEPTH_BIAS(FBZMODE)) \
1916	3630	{ \
1917		biasdepth += (INT16)vd->reg[zaColor].u; \
	3631	biasdepth += (INT16)(VV)->reg[zaColor].u; \
1918	3632	CLAMP(biasdepth, 0, 0xffff); \
1919	3633	}
1920	3634
1921	3635
1922		#define DEPTH_TEST(vd, STATS, XX, FBZMODE) \
	3636	#define DEPTH_TEST(VV, STATS, XX, FBZMODE) \
1923	3637	do \
1924	3638	{ \
1925	3639	/* handle depth buffer testing */ \
r253151	r253152
1932	3646	if (FBZMODE_DEPTH_SOURCE_COMPARE(FBZMODE) == 0) \
1933	3647	depthsource = biasdepth; \
1934	3648	else \
1935		depthsource = (UINT16)vd->reg[zaColor].u; \
	3649	depthsource = (UINT16)(VV)->reg[zaColor].u; \
1936	3650	\
1937	3651	/* test against the depth buffer */ \
1938	3652	switch (FBZMODE_DEPTH_FUNCTION(FBZMODE)) \
r253151	r253152
2072	3786	return true;
2073	3787	}
2074	3788
2075		#define PIXEL_PIPELINE_END(vd, STATS, DITHER, DITHER4, DITHER_LOOKUP, XX, dest, depth, FBZMODE, FBZCOLORPATH, ALPHAMODE, FOGMODE, ITERZ, ITERW, ITERAXXX) \
	3789	#define PIXEL_PIPELINE_END(VV, STATS, DITHER, DITHER4, DITHER_LOOKUP, XX, dest, depth, FBZMODE, FBZCOLORPATH, ALPHAMODE, FOGMODE, ITERZ, ITERW, ITERAXXX) \
2076	3790	\
2077	3791	/* perform fogging */ \
2078	3792	preFog.set(color); \
2079		applyFogging(vd, FOGMODE, FBZCOLORPATH, XX, DITHER4, fogdepth, color, ITERZ, ITERW, ITERAXXX.get_a()); \
	3793	applyFogging(VV, FOGMODE, FBZCOLORPATH, XX, DITHER4, fogdepth, color, ITERZ, ITERW, ITERAXXX.get_a()); \
2080	3794	/* perform alpha blending */ \
2081	3795	alphaBlend(FBZMODE, ALPHAMODE, XX, DITHER, dest[XX], depth, preFog, color); \
2082	3796	a = color.get_a(); r = color.get_r(); g = color.get_g(); b = color.get_b(); \
r253151	r253152
2407	4121	} \
2408	4122	while (0)
2409	4123
2410		static inline bool ATTR_FORCE_INLINE combineColor(voodoo_de~~vice~~ vd, stats_block STATS, UINT32 FBZCOLORPATH, UINT32 FBZMODE, UINT32 ALPHAMODE,
	4124	static inline bool ATTR_FORCE_INLINE combineColor(voodoo_state VV, stats_block STATS, UINT32 FBZCOLORPATH, UINT32 FBZMODE, UINT32 ALPHAMODE,
2411	4125	rgbaint_t TEXELARGB, INT32 ITERZ, INT64 ITERW, rgbaint_t &srcColor)
2412	4126	{
2413	4127	rgbaint_t c_other;
r253151	r253152
2425	4139	break;
2426	4140
2427	4141	case 2: /* color1 RGB */
2428		c_other.set(vd->reg[color1].u);
	4142	c_other.set((VV)->reg[color1].u);
2429	4143	break;
2430	4144
2431	4145	default: /* reserved - voodoo3 framebufferRGB */
r253151	r253152
2434	4148	}
2435	4149
2436	4150	/* handle chroma key */
2437		if (!chromaKeyTest(vd, STATS, FBZMODE, c_other))
	4151	if (!chromaKeyTest(VV, STATS, FBZMODE, c_other))
2438	4152	return false;
2439		//APPLY_CHROMAKEY(~~vd->m_vds~~, STATS, FBZMODE, c_other);
	4153	//APPLY_CHROMAKEY(VV, STATS, FBZMODE, c_other);
2440	4154
2441	4155	/* compute a_other */
2442	4156	switch (FBZCP_CC_ASELECT(FBZCOLORPATH))
r253151	r253152
2450	4164	break;
2451	4165
2452	4166	case 2: /* color1 alpha */
2453		c_other.set_a(vd->reg[color1].rgb.a);
	4167	c_other.set_a((VV)->reg[color1].rgb.a);
2454	4168	break;
2455	4169
2456	4170	default: /* reserved */
r253151	r253152
2461	4175	/* handle alpha mask */
2462	4176	if (!alphaMaskTest(STATS, FBZMODE, c_other.get_a()))
2463	4177	return false;
2464		//APPLY_ALPHAMASK(~~vd->m_vds~~, STATS, FBZMODE, c_other.rgb.a);
	4178	//APPLY_ALPHAMASK(VV, STATS, FBZMODE, c_other.rgb.a);
2465	4179
2466	4180
2467	4181	/* compute c_local */
r253151	r253152
2470	4184	if (FBZCP_CC_LOCALSELECT(FBZCOLORPATH) == 0) /* iterated RGB */
2471	4185	c_local.set(srcColor);
2472	4186	else /* color0 RGB */
2473		c_local.set(vd->reg[color0].u);
	4187	c_local.set((VV)->reg[color0].u);
2474	4188	}
2475	4189	else
2476	4190	{
2477	4191	if (!(TEXELARGB.get_a() & 0x80)) /* iterated RGB */
2478	4192	c_local.set(srcColor);
2479	4193	else /* color0 RGB */
2480		c_local.set(vd->reg[color0].u);
	4194	c_local.set((VV)->reg[color0].u);
2481	4195	}
2482	4196
2483	4197	/* compute a_local */
r253151	r253152
2489	4203	break;
2490	4204
2491	4205	case 1: /* color0 alpha */
2492		c_local.set_a(vd->reg[color0].rgb.a);
	4206	c_local.set_a((VV)->reg[color0].rgb.a);
2493	4207	break;
2494	4208
2495	4209	case 2: /* clamped iterated Z[27:20] */
r253151	r253152
2641	4355
2642	4356
2643	4357	/* handle alpha test */
2644		if (!alphaTest(vd, STATS, ALPHAMODE, srcColor.get_a()))
	4358	if (!alphaTest(VV, STATS, ALPHAMODE, srcColor.get_a()))
2645	4359	return false;
2646		//APPLY_ALPHATEST(~~vd->m_vds~~, STATS, ALPHAMODE, color.rgb.a);
	4360	//APPLY_ALPHATEST(VV, STATS, ALPHAMODE, color.rgb.a);
2647	4361
2648	4362	return true;
2649	4363	}
r253151	r253152
2658	4372
2659	4373	#define RASTERIZER(name, TMUS, FBZCOLORPATH, FBZMODE, ALPHAMODE, FOGMODE, TEXMODE0, TEXMODE1) \
2660	4374	\
2661		void vo~~odoo_dev~~i~~ce::~~raster_##name(void destbase, INT32 y, const poly_extent extent, const void *extradata, int threadid) \
	4375	static void raster_##name(void destbase, INT32 y, const poly_extent extent, const void *extradata, int threadid) \
2662	4376	{ \
2663	4377	const poly_extra_data extra = (const poly_extra_data )extradata; \
2664		voodoo_device *vd = extra->device; \
2665		stats_block *stats = &vd->thread_stats[threadid]; \
	4378	voodoo_state *v = extra->state; \
	4379	stats_block *stats = &v->thread_stats[threadid]; \
2666	4380	DECLARE_DITHER_POINTERS; \
2667	4381	INT32 startx = extent->startx; \
2668	4382	INT32 stopx = extent->stopx; \
r253151	r253152
2680	4394	/* determine the screen Y */ \
2681	4395	scry = y; \
2682	4396	if (FBZMODE_Y_ORIGIN(FBZMODE)) \
2683		scry = (vd->fbi.yorigin - y) & 0x3ff; \
	4397	scry = (v->fbi.yorigin - y) & 0x3ff; \
2684	4398	\
2685	4399	/* compute dithering */ \
2686	4400	COMPUTE_DITHER_POINTERS(FBZMODE, y); \
r253151	r253152
2691	4405	INT32 tempclip; \
2692	4406	\
2693	4407	/* Y clipping buys us the whole scanline */ \
2694		if (scry < ((vd->reg[clipLowYHighY].u >> 16) & 0x3ff) \|\| \
2695		scry >= (vd->reg[clipLowYHighY].u & 0x3ff)) \
	4408	if (scry < ((v->reg[clipLowYHighY].u >> 16) & 0x3ff) \|\| \
	4409	scry >= (v->reg[clipLowYHighY].u & 0x3ff)) \
2696	4410	{ \
2697	4411	stats->pixels_in += stopx - startx; \
2698	4412	stats->clip_fail += stopx - startx; \
r253151	r253152
2700	4414	} \
2701	4415	\
2702	4416	/* X clipping */ \
2703		tempclip = (vd->reg[clipLeftRight].u >> 16) & 0x3ff; \
	4417	tempclip = (v->reg[clipLeftRight].u >> 16) & 0x3ff; \
2704	4418	if (startx < tempclip) \
2705	4419	{ \
2706	4420	stats->pixels_in += tempclip - startx; \
2707		vd->stats.total_clipped += tempclip - startx; \
	4421	v->stats.total_clipped += tempclip - startx; \
2708	4422	startx = tempclip; \
2709	4423	} \
2710		tempclip = vd->reg[clipLeftRight].u & 0x3ff; \
	4424	tempclip = v->reg[clipLeftRight].u & 0x3ff; \
2711	4425	if (stopx >= tempclip) \
2712	4426	{ \
2713	4427	stats->pixels_in += stopx - tempclip; \
2714		vd->stats.total_clipped += stopx - tempclip; \
	4428	v->stats.total_clipped += stopx - tempclip; \
2715	4429	stopx = tempclip - 1; \
2716	4430	} \
2717	4431	} \
2718	4432	\
2719	4433	/* get pointers to the target buffer and depth buffer */ \
2720		dest = (UINT16 )destbase + scry vd->fbi.rowpixels; \
2721		depth = (vd->fbi.auxoffs != ~0) ? ((UINT16 )(vd->fbi.ram + vd->fbi.auxoffs) + scry vd->fbi.rowpixels) : NULL; \
	4434	dest = (UINT16 )destbase + scry v->fbi.rowpixels; \
	4435	depth = (v->fbi.auxoffs != ~0) ? ((UINT16 )(v->fbi.ram + v->fbi.auxoffs) + scry v->fbi.rowpixels) : NULL; \
2722	4436	\
2723	4437	/* compute the starting parameters */ \
2724	4438	dx = startx - (extra->ax >> 4); \
r253151	r253152
2751	4465	rgbaint_t color, preFog; \
2752	4466	\
2753	4467	/* pixel pipeline part 1 handles depth setup and stippling */ \
2754		PIXEL_PIPELINE_BEGIN(vd, stats, x, y, FBZCOLORPATH, FBZMODE, iterz, iterw); \
	4468	PIXEL_PIPELINE_BEGIN(v, stats, x, y, FBZCOLORPATH, FBZMODE, iterz, iterw); \
2755	4469	/* depth testing */ \
2756		if (!depthTest((UINT16) vd->reg[zaColor].u, stats, depth[x], FBZMODE, biasdepth)) \
	4470	if (!depthTest((UINT16) v->reg[zaColor].u, stats, depth[x], FBZMODE, biasdepth)) \
2757	4471	goto skipdrawdepth; \
2758	4472	\
2759	4473	/* run the texture pipeline on TMU1 to produce a value in texel */ \
2760	4474	/* note that they set LOD min to 8 to "disable" a TMU */ \
2761		if (TMUS >= 2 && vd->tmu[1].lodmin < (8 << 8)) { \
	4475	if (TMUS >= 2 && v->tmu[1].lodmin < (8 << 8)) { \
2762	4476	INT32 tmp; \
2763	4477	const rgbaint_t texelZero(0); \
2764		texel = genTexture(&vd->tmu[1], x, dither4, TEXMODE1, vd->tmu[1].lookup, extra->lodbase1, \
	4478	texel = genTexture(&v->tmu[1], x, dither4, TEXMODE1, v->tmu[1].lookup, extra->lodbase1, \
2765	4479	iters1, itert1, iterw1, tmp); \
2766		texel = combineTexture(&vd->tmu[1], TEXMODE1, texel, texelZero, tmp); \
	4480	texel = combineTexture(&v->tmu[1], TEXMODE1, texel, texelZero, tmp); \
2767	4481	} \
2768	4482	/* run the texture pipeline on TMU0 to produce a final */ \
2769	4483	/* result in texel */ \
2770	4484	/* note that they set LOD min to 8 to "disable" a TMU */ \
2771		if (TMUS >= 1 && vd->tmu[0].lodmin < (8 << 8)) \
	4485	if (TMUS >= 1 && v->tmu[0].lodmin < (8 << 8)) \
2772	4486	{ \
2773		if (!vd->send_config) \
	4487	if (!v->send_config) \
2774	4488	{ \
2775	4489	INT32 lod0; \
2776	4490	rgbaint_t texelT0; \
2777		texelT0 = genTexture(&vd->tmu[0], x, dither4, TEXMODE0, vd->tmu[0].lookup, extra->lodbase0, \
	4491	texelT0 = genTexture(&v->tmu[0], x, dither4, TEXMODE0, v->tmu[0].lookup, extra->lodbase0, \
2778	4492	iters0, itert0, iterw0, lod0); \
2779		texel = combineTexture(&vd->tmu[0], TEXMODE0, texelT0, texel, lod0); \
	4493	texel = combineTexture(&v->tmu[0], TEXMODE0, texelT0, texel, lod0); \
2780	4494	} \
2781	4495	else \
2782	4496	{ \
2783		texel.set(vd->tmu_config); \
	4497	texel.set(v->tmu_config); \
2784	4498	} \
2785	4499	} \
2786	4500	\
2787	4501	/* colorpath pipeline selects source colors and does blending */ \
2788	4502	color = clampARGB(iterargb, FBZCOLORPATH); \
2789		if (!combineColor(vd, stats, FBZCOLORPATH, FBZMODE, ALPHAMODE, texel, iterz, iterw, color)) \
	4503	if (!combineColor(v, stats, FBZCOLORPATH, FBZMODE, ALPHAMODE, texel, iterz, iterw, color)) \
2790	4504	goto skipdrawdepth; \
2791	4505	\
2792	4506	/* pixel pipeline part 2 handles fog, alpha, and final output */ \
2793		PIXEL_PIPELINE_END(vd, stats, dither, dither4, dither_lookup, x, dest, depth, \
	4507	PIXEL_PIPELINE_END(v, stats, dither, dither4, dither_lookup, x, dest, depth, \
2794	4508	FBZMODE, FBZCOLORPATH, ALPHAMODE, FOGMODE, \
2795	4509	iterz, iterw, iterargb); \
2796	4510	\

trunk/src/devices/video/voodoo.cpp
r253151	r253152
143	143
144	144
145	145	#include "emu.h"
146
	146	#include "video/polylgcy.h"
147	147	#include "video/rgbutil.h"
148	148	#include "voodoo.h"
149	149	#include "vooddefs.h"
r253151	r253152
194	194
195	195
196	196
	197	/*************************************
	198	*
	199	* Prototypes
	200	*
	201	*************************************/
197	202
	203	static void init_fbi(voodoo_state v, fbi_state f, void *memory, int fbmem);
	204	static void init_tmu_shared(tmu_shared_state *s);
	205	static void init_tmu(voodoo_state v, tmu_state t, voodoo_reg reg, void memory, int tmem);
	206	static void soft_reset(voodoo_state *v);
	207	static void recompute_video_memory(voodoo_state *v);
	208	static void check_stalled_cpu(voodoo_state *v, attotime current_time);
	209	static void flush_fifos(voodoo_state *v, attotime current_time);
	210	static TIMER_CALLBACK( stall_cpu_callback );
	211	static void stall_cpu(voodoo_state *v, int state, attotime current_time);
	212	static TIMER_CALLBACK( vblank_callback );
	213	static INT32 register_w(voodoo_state *v, offs_t offset, UINT32 data);
	214	static INT32 lfb_direct_w(voodoo_state *v, offs_t offset, UINT32 data, UINT32 mem_mask);
	215	static INT32 lfb_w(voodoo_state *v, offs_t offset, UINT32 data, UINT32 mem_mask);
	216	static INT32 texture_w(voodoo_state *v, offs_t offset, UINT32 data);
	217	static INT32 banshee_2d_w(voodoo_state *v, offs_t offset, UINT32 data);
198	218
	219	/* command handlers */
	220	static INT32 fastfill(voodoo_state *v);
	221	static INT32 swapbuffer(voodoo_state *v, UINT32 data);
	222	static INT32 triangle(voodoo_state *v);
	223	static INT32 begin_triangle(voodoo_state *v);
	224	static INT32 draw_triangle(voodoo_state *v);
	225
	226	/* triangle helpers */
	227	static INT32 setup_and_draw_triangle(voodoo_state *v);
	228	static INT32 triangle_create_work_item(voodoo_state v, UINT16 drawbuf, int texcount);
	229
	230	/* rasterizer management */
	231	static raster_info add_rasterizer(voodoo_state v, const raster_info *cinfo);
	232	static raster_info find_rasterizer(voodoo_state v, int texcount);
	233	static void dump_rasterizer_stats(voodoo_state *v);
	234
	235	/* generic rasterizers */
	236	static void raster_fastfill(void dest, INT32 scanline, const poly_extent extent, const void *extradata, int threadid);
	237	static void raster_generic_0tmu(void dest, INT32 scanline, const poly_extent extent, const void *extradata, int threadid);
	238	static void raster_generic_1tmu(void dest, INT32 scanline, const poly_extent extent, const void *extradata, int threadid);
	239	static void raster_generic_2tmu(void dest, INT32 scanline, const poly_extent extent, const void *extradata, int threadid);
	240
	241
	242
199	243	/*************************************
200	244	*
201	245	* Specific rasterizers
r253151	r253152
218	262	*************************************/
219	263
220	264	#define RASTERIZER_ENTRY(fbzcp, alpha, fog, fbz, tex0, tex1) \
221		{ NULL, ~~voodoo_device::~~raster_##fbzcp##_##alpha##_##fog##_##fbz##_##tex0##_##tex1, FALSE, 0, 0, 0, fbzcp, alpha, fog, fbz, tex0, tex1 },
	265	{ NULL, raster_##fbzcp##_##alpha##_##fog##_##fbz##_##tex0##_##tex1, FALSE, 0, 0, 0, fbzcp, alpha, fog, fbz, tex0, tex1 },
222	266
223	267	static const raster_info predef_raster_table[] =
224	268	{
r253151	r253152
234	278	INLINE FUNCTIONS
235	279	***************************************************************************/
236	280
	281	/*-------------------------------------------------
	282	get_safe_token - makes sure that the passed
	283	in device is, in fact, a voodoo device
	284	-------------------------------------------------*/
	285
	286	static inline voodoo_state get_safe_token(device_t device)
	287	{
	288	assert(device != nullptr);
	289	assert((device->type() == VOODOO_1) \|\| (device->type() == VOODOO_2) \|\| (device->type() == VOODOO_BANSHEE) \|\| (device->type() == VOODOO_3));
	290
	291	return (voodoo_state )downcast<voodoo_device >(device)->token();
	292	}
	293
	294
	295
237	296	/*************************************
238	297	*
239	298	* Video update
240	299	*
241	300	*************************************/
242	301
243		int voodoo_device~~::voodoo~~_~~upda~~te(bitmap_rgb32 &bitmap, const rectangle &cliprect)
	302	int voodoo_update(device_t *device, bitmap_rgb32 &bitmap, const rectangle &cliprect)
244	303	{
245		int changed = fbi.video_changed;
246		int drawbuf = fbi.frontbuf;
	304	voodoo_state *v = get_safe_token(device);
	305	int changed = v->fbi.video_changed;
	306	int drawbuf = v->fbi.frontbuf;
247	307	int statskey;
248	308	int x, y;
249	309
250	310	/* reset the video changed flag */
251		fbi.video_changed = FALSE;
	311	v->fbi.video_changed = FALSE;
252	312
253	313	/* if we are blank, just fill with black */
254		if (vd_type <= TYPE_VOODOO_2 && FBIINIT1_SOFTWARE_BLANK(reg[fbiInit1].u))
	314	if (v->type <= TYPE_VOODOO_2 && FBIINIT1_SOFTWARE_BLANK(v->reg[fbiInit1].u))
255	315	{
256	316	bitmap.fill(0, cliprect);
257	317	return changed;
258	318	}
259	319
260	320	/* if the CLUT is dirty, recompute the pens array */
261		if (fbi.clut_dirty)
	321	if (v->fbi.clut_dirty)
262	322	{
263	323	UINT8 rtable[32], gtable[64], btable[32];
264	324
265	325	/* Voodoo/Voodoo-2 have an internal 33-entry CLUT */
266		if (vd_type <= TYPE_VOODOO_2)
	326	if (v->type <= TYPE_VOODOO_2)
267	327	{
268	328	/* kludge: some of the Midway games write 0 to the last entry when they obviously mean FF */
269		if ((fbi.clut[32] & 0xffffff) == 0 && (fbi.clut[31] & 0xffffff) != 0)
270		fbi.clut[32] = 0x20ffffff;
	329	if ((v->fbi.clut[32] & 0xffffff) == 0 && (v->fbi.clut[31] & 0xffffff) != 0)
	330	v->fbi.clut[32] = 0x20ffffff;
271	331
272	332	/* compute the R/G/B pens first */
273	333	for (x = 0; x < 32; x++)
274	334	{
275	335	/* treat X as a 5-bit value, scale up to 8 bits, and linear interpolate for red/blue */
276	336	y = (x << 3) \| (x >> 2);
277		rtable[x] = (fbi.clut[y >> 3].r() * (8 - (y & 7)) + fbi.clut[(y >> 3) + 1].r() * (y & 7)) >> 3;
278		btable[x] = (fbi.clut[y >> 3].b() * (8 - (y & 7)) + fbi.clut[(y >> 3) + 1].b() * (y & 7)) >> 3;
	337	rtable[x] = (v->fbi.clut[y >> 3].r() * (8 - (y & 7)) + v->fbi.clut[(y >> 3) + 1].r() * (y & 7)) >> 3;
	338	btable[x] = (v->fbi.clut[y >> 3].b() * (8 - (y & 7)) + v->fbi.clut[(y >> 3) + 1].b() * (y & 7)) >> 3;
279	339
280	340	/* treat X as a 6-bit value with LSB=0, scale up to 8 bits, and linear interpolate */
281	341	y = (x * 2) + 0;
282	342	y = (y << 2) \| (y >> 4);
283		gtable[x2+0] = (fbi.clut[y >> 3].g() (8 - (y & 7)) + fbi.clut[(y >> 3) + 1].g() * (y & 7)) >> 3;
	343	gtable[x2+0] = (v->fbi.clut[y >> 3].g() (8 - (y & 7)) + v->fbi.clut[(y >> 3) + 1].g() * (y & 7)) >> 3;
284	344
285	345	/* treat X as a 6-bit value with LSB=1, scale up to 8 bits, and linear interpolate */
286	346	y = (x * 2) + 1;
287	347	y = (y << 2) \| (y >> 4);
288		gtable[x2+1] = (fbi.clut[y >> 3].g() (8 - (y & 7)) + fbi.clut[(y >> 3) + 1].g() * (y & 7)) >> 3;
	348	gtable[x2+1] = (v->fbi.clut[y >> 3].g() (8 - (y & 7)) + v->fbi.clut[(y >> 3) + 1].g() * (y & 7)) >> 3;
289	349	}
290	350	}
291	351
292	352	/* Banshee and later have a 512-entry CLUT that can be bypassed */
293	353	else
294	354	{
295		int which = (banshee.io[io_vidProcCfg] >> 13) & 1;
296		int bypass = (banshee.io[io_vidProcCfg] >> 11) & 1;
	355	int which = (v->banshee.io[io_vidProcCfg] >> 13) & 1;
	356	int bypass = (v->banshee.io[io_vidProcCfg] >> 11) & 1;
297	357
298	358	/* compute R/G/B pens first */
299	359	for (x = 0; x < 32; x++)
300	360	{
301	361	/* treat X as a 5-bit value, scale up to 8 bits */
302	362	y = (x << 3) \| (x >> 2);
303		rtable[x] = bypass ? y : fbi.clut[which * 256 + y].r();
304		btable[x] = bypass ? y : fbi.clut[which * 256 + y].b();
	363	rtable[x] = bypass ? y : v->fbi.clut[which * 256 + y].r();
	364	btable[x] = bypass ? y : v->fbi.clut[which * 256 + y].b();
305	365
306	366	/* treat X as a 6-bit value with LSB=0, scale up to 8 bits */
307	367	y = (x * 2) + 0;
308	368	y = (y << 2) \| (y >> 4);
309		gtable[x2+0] = bypass ? y : fbi.clut[which 256 + y].g();
	369	gtable[x2+0] = bypass ? y : v->fbi.clut[which 256 + y].g();
310	370
311	371	/* treat X as a 6-bit value with LSB=1, scale up to 8 bits, and linear interpolate */
312	372	y = (x * 2) + 1;
313	373	y = (y << 2) \| (y >> 4);
314		gtable[x2+1] = bypass ? y : fbi.clut[which 256 + y].g();
	374	gtable[x2+1] = bypass ? y : v->fbi.clut[which 256 + y].g();
315	375	}
316	376	}
317	377
r253151	r253152
321	381	int r = rtable[(x >> 11) & 0x1f];
322	382	int g = gtable[(x >> 5) & 0x3f];
323	383	int b = btable[x & 0x1f];
324		fbi.pen[x] = rgb_t(r, g, b);
	384	v->fbi.pen[x] = rgb_t(r, g, b);
325	385	}
326	386
327	387	/* no longer dirty */
328		fbi.clut_dirty = FALSE;
	388	v->fbi.clut_dirty = FALSE;
329	389	changed = TRUE;
330	390	}
331	391
332	392	/* debugging! */
333		if (machine().input().code_pressed(KEYCODE_L))
334		drawbuf = fbi.backbuf;
	393	if (device->machine().input().code_pressed(KEYCODE_L))
	394	drawbuf = v->fbi.backbuf;
335	395
336	396	/* copy from the current front buffer */
337	397	for (y = cliprect.min_y; y <= cliprect.max_y; y++)
338		if (y >= fbi.yoffs)
	398	if (y >= v->fbi.yoffs)
339	399	{
340		UINT16 src = (UINT16 )(fbi.ram + fbi.rgboffs[drawbuf]) + (y - fbi.yoffs) * fbi.rowpixels - fbi.xoffs;
	400	UINT16 src = (UINT16 )(v->fbi.ram + v->fbi.rgboffs[drawbuf]) + (y - v->fbi.yoffs) * v->fbi.rowpixels - v->fbi.xoffs;
341	401	UINT32 *dst = &bitmap.pix32(y);
342	402	for (x = cliprect.min_x; x <= cliprect.max_x; x++)
343		dst[x] = fbi.pen[src[x]];
	403	dst[x] = v->fbi.pen[src[x]];
344	404	}
345	405
346	406	/* update stats display */
347		statskey = (machine().input().code_pressed(KEYCODE_BACKSLASH) != 0);
348		if (statskey && statskey != stats.lastkey)
349		stats.display = !stats.display;
350		stats.lastkey = statskey;
	407	statskey = (device->machine().input().code_pressed(KEYCODE_BACKSLASH) != 0);
	408	if (statskey && statskey != v->stats.lastkey)
	409	v->stats.display = !v->stats.display;
	410	v->stats.lastkey = statskey;
351	411
352	412	/* display stats */
353		if (stats.display)
354		popmessage(stats.buffer, 0, 0);
	413	if (v->stats.display)
	414	device->popmessage(v->stats.buffer, 0, 0);
355	415
356	416	/* update render override */
357		stats.render_override = machine().input().code_pressed(KEYCODE_ENTER);
358		if (DEBUG_DEPTH && stats.render_override)
	417	v->stats.render_override = device->machine().input().code_pressed(KEYCODE_ENTER);
	418	if (DEBUG_DEPTH && v->stats.render_override)
359	419	{
360	420	for (y = cliprect.min_y; y <= cliprect.max_y; y++)
361	421	{
362		UINT16 src = (UINT16 )(fbi.ram + fbi.auxoffs) + (y - fbi.yoffs) * fbi.rowpixels - fbi.xoffs;
	422	UINT16 src = (UINT16 )(v->fbi.ram + v->fbi.auxoffs) + (y - v->fbi.yoffs) * v->fbi.rowpixels - v->fbi.xoffs;
363	423	UINT32 *dst = &bitmap.pix32(y);
364	424	for (x = cliprect.min_x; x <= cliprect.max_x; x++)
365	425	dst[x] = ((src[x] << 8) & 0xff0000) \| ((src[x] >> 0) & 0xff00) \| ((src[x] >> 8) & 0xff);
r253151	r253152
376	436	*
377	437	*************************************/
378	438
379
380		int voodoo_device::voodoo_get_type()
	439	int voodoo_get_type(device_t *device)
381	440	{
382		voodoo_device *vd = this;
383		return vd->vd_type;
	441	voodoo_state *v = get_safe_token(device);
	442	return v->type;
384	443	}
385	444
386	445
387		int voodoo_~~dev~~i~~ce::voodoo_i~~s_stalled()
	446	int voodoo_is_stalled(device_t *device)
388	447	{
389		voodoo_device *vd = this;
390		return (vd->pci.stall_state != NOT_STALLED);
	448	voodoo_state *v = get_safe_token(device);
	449	return (v->pci.stall_state != NOT_STALLED);
391	450	}
392	451
393	452
394		void voodoo_~~device::voodoo_~~set_init_enable(UINT32 newval)
	453	void voodoo_set_init_enable(device_t *device, UINT32 newval)
395	454	{
396		voodoo_device *vd = this;
397		vd->pci.init_enable = newval;
	455	voodoo_state *v = get_safe_token(device);
	456	v->pci.init_enable = newval;
398	457	if (LOG_REGISTERS)
399		logerror("VOODOO.%d.REG:initEnable write = %08X\n", vd->index, newval);
	458	device->logerror("VOODOO.%d.REG:initEnable write = %08X\n", v->index, newval);
400	459	}
401	460
402	461
r253151	r253152
407	466	*
408	467	*************************************/
409	468
410		void vood~~oo_dev~~i~~ce::i~~nit_fbi(voodoo_device* vd,fbi_state f, void memory, int fbmem)
	469	static void init_fbi(voodoo_state v, fbi_state f, void *memory, int fbmem)
411	470	{
412	471	int pen;
413	472
r253151	r253152
425	484
426	485	/* init the pens */
427	486	f->clut_dirty = TRUE;
428		if (vd->~~vd_~~type <= TYPE_VOODOO_2)
	487	if (v->type <= TYPE_VOODOO_2)
429	488	{
430	489	for (pen = 0; pen < 32; pen++)
431		vd->fbi.clut[pen] = rgb_t(pen, pal5bit(pen), pal5bit(pen), pal5bit(pen));
432		vd->fbi.clut[32] = rgb_t(32,0xff,0xff,0xff);
	490	v->fbi.clut[pen] = rgb_t(pen, pal5bit(pen), pal5bit(pen), pal5bit(pen));
	491	v->fbi.clut[32] = rgb_t(32,0xff,0xff,0xff);
433	492	}
434	493	else
435	494	{
436	495	for (pen = 0; pen < 512; pen++)
437		vd->fbi.clut[pen] = rgb_t(pen,pen,pen);
	496	v->fbi.clut[pen] = rgb_t(pen,pen,pen);
438	497	}
439	498
440	499	/* allocate a VBLANK timer */
441		f->vblank_timer = vd->device->machine().scheduler().timer_alloc(~~timer_expired_delegate(~~FUNC(v~~oodoo_device::v~~blank_callback),~~vd),~~ vd);
	500	f->vblank_timer = v->device->machine().scheduler().timer_alloc(FUNC(vblank_callback), v);
442	501	f->vblank = FALSE;
443	502
444	503	/* initialize the memory FIFO */
r253151	r253152
446	505	f->fifo.size = f->fifo.in = f->fifo.out = 0;
447	506
448	507	/* set the fog delta mask */
449		f->fogdelta_mask = (vd->~~vd_~~type < TYPE_VOODOO_2) ? 0xff : 0xfc;
	508	f->fogdelta_mask = (v->type < TYPE_VOODOO_2) ? 0xff : 0xfc;
450	509	}
451	510
452	511
453		void vo~~odoo_dev~~i~~ce::~~init_tmu_shared(tmu_shared_state *s)
	512	static void init_tmu_shared(tmu_shared_state *s)
454	513	{
455	514	int val;
456	515
r253151	r253152
495	554	}
496	555
497	556
498		void vood~~oo_dev~~i~~ce::i~~nit_tmu(voodoo_device* vd, tmu_state t, voodoo_reg reg, void *memory, int tmem)
	557	static void init_tmu(voodoo_state v, tmu_state t, voodoo_reg reg, void memory, int tmem)
499	558	{
500	559	/* allocate texture RAM */
501	560	t->ram = (UINT8 *)memory;
502	561	t->mask = tmem - 1;
503	562	t->reg = reg;
504	563	t->regdirty = TRUE;
505		t->bilinear_mask = (vd->~~vd_~~type >= TYPE_VOODOO_2) ? 0xff : 0xf0;
	564	t->bilinear_mask = (v->type >= TYPE_VOODOO_2) ? 0xff : 0xf0;
506	565
507	566	/* mark the NCC tables dirty and configure their registers */
508	567	t->ncc[0].dirty = t->ncc[1].dirty = TRUE;
r253151	r253152
510	569	t->ncc[1].reg = &t->reg[nccTable+12];
511	570
512	571	/* create pointers to all the tables */
513		t->texel[0] = vd->tmushare.rgb332;
	572	t->texel[0] = v->tmushare.rgb332;
514	573	t->texel[1] = t->ncc[0].texel;
515		t->texel[2] = vd->tmushare.alpha8;
516		t->texel[3] = vd->tmushare.int8;
517		t->texel[4] = vd->tmushare.ai44;
	574	t->texel[2] = v->tmushare.alpha8;
	575	t->texel[3] = v->tmushare.int8;
	576	t->texel[4] = v->tmushare.ai44;
518	577	t->texel[5] = t->palette;
519		t->texel[6] = (vd->~~vd_~~type >= TYPE_VOODOO_2) ? t->palettea : nullptr;
	578	t->texel[6] = (v->type >= TYPE_VOODOO_2) ? t->palettea : nullptr;
520	579	t->texel[7] = nullptr;
521		t->texel[8] = vd->tmushare.rgb332;
	580	t->texel[8] = v->tmushare.rgb332;
522	581	t->texel[9] = t->ncc[0].texel;
523		t->texel[10] = vd->tmushare.rgb565;
524		t->texel[11] = vd->tmushare.argb1555;
525		t->texel[12] = vd->tmushare.argb4444;
526		t->texel[13] = vd->tmushare.int8;
	582	t->texel[10] = v->tmushare.rgb565;
	583	t->texel[11] = v->tmushare.argb1555;
	584	t->texel[12] = v->tmushare.argb4444;
	585	t->texel[13] = v->tmushare.int8;
527	586	t->texel[14] = t->palette;
528	587	t->texel[15] = nullptr;
529	588	t->lookup = t->texel[0];
530	589
531	590	/* attach the palette to NCC table 0 */
532	591	t->ncc[0].palette = t->palette;
533		if (vd->~~vd_~~type >= TYPE_VOODOO_2)
	592	if (v->type >= TYPE_VOODOO_2)
534	593	t->ncc[0].palettea = t->palettea;
535	594
536	595	/* set up texture address calculations */
537		if (vd->~~vd_~~type <= TYPE_VOODOO_2)
	596	if (v->type <= TYPE_VOODOO_2)
538	597	{
539	598	t->texaddr_mask = 0x0fffff;
540	599	t->texaddr_shift = 3;
r253151	r253152
547	606	}
548	607
549	608
550		void voodoo_~~device::voodoo_~~postload(voodoo_de~~vice~~ *vd)
	609	static void voodoo_postload(voodoo_state *v)
551	610	{
552	611	int index, subindex;
553	612
554		vd->fbi.clut_dirty = TRUE;
555		for (index = 0; index < ARRAY_LENGTH(vd->tmu); index++)
	613	v->fbi.clut_dirty = TRUE;
	614	for (index = 0; index < ARRAY_LENGTH(v->tmu); index++)
556	615	{
557		vd->tmu[index].regdirty = TRUE;
558		for (subindex = 0; subindex < ARRAY_LENGTH(vd->tmu[index].ncc); subindex++)
559		vd->tmu[index].ncc[subindex].dirty = TRUE;
	616	v->tmu[index].regdirty = TRUE;
	617	for (subindex = 0; subindex < ARRAY_LENGTH(v->tmu[index].ncc); subindex++)
	618	v->tmu[index].ncc[subindex].dirty = TRUE;
560	619	}
561	620
562	621	/* recompute video memory to get the FBI FIFO base recomputed */
563		if (vd->vd_type <= TYPE_VOODOO_2)
564		recompute_video_memory(vd);
	622	if (v->type <= TYPE_VOODOO_2)
	623	recompute_video_memory(v);
565	624	}
566	625
567	626
568		static void init_save_state(~~voo~~d~~oo_d~~evice *vd)
	627	static void init_save_state(device_t *device)
569	628	{
	629	voodoo_state *v = get_safe_token(device);
570	630	int index, subindex;
571	631
572		vd->machine().save().register_postload(save_prepost_delegate(FUNC(voodoo_~~device::voodoo_~~postload), vd));
	632	device->machine().save().register_postload(save_prepost_delegate(FUNC(voodoo_postload), v));
573	633
574	634	/* register states: core */
575		vd->save_item(NAME(vd->extra_cycles));
576		vd->save_pointer(NAME(&vd->reg[0].u), ARRAY_LENGTH(vd->reg));
577		vd->save_item(NAME(vd->alt_regmap));
	635	device->save_item(NAME(v->extra_cycles));
	636	device->save_pointer(NAME(&v->reg[0].u), ARRAY_LENGTH(v->reg));
	637	device->save_item(NAME(v->alt_regmap));
578	638
579	639	/* register states: pci */
580		vd->save_item(NAME(vd->pci.fifo.in));
581		vd->save_item(NAME(vd->pci.fifo.out));
582		vd->save_item(NAME(vd->pci.init_enable));
583		vd->save_item(NAME(vd->pci.stall_state));
584		vd->save_item(NAME(vd->pci.op_pending));
585		vd->save_item(NAME(vd->pci.op_end_time));
586		vd->save_item(NAME(vd->pci.fifo_mem));
	640	device->save_item(NAME(v->pci.fifo.in));
	641	device->save_item(NAME(v->pci.fifo.out));
	642	device->save_item(NAME(v->pci.init_enable));
	643	device->save_item(NAME(v->pci.stall_state));
	644	device->save_item(NAME(v->pci.op_pending));
	645	device->save_item(NAME(v->pci.op_end_time));
	646	device->save_item(NAME(v->pci.fifo_mem));
587	647
588	648	/* register states: dac */
589		vd->save_item(NAME(vd->dac.reg));
590		vd->save_item(NAME(vd->dac.read_result));
	649	device->save_item(NAME(v->dac.reg));
	650	device->save_item(NAME(v->dac.read_result));
591	651
592	652	/* register states: fbi */
593		vd->save_pointer(NAME(vd->fbi.ram), vd->fbi.mask + 1);
594		vd->save_item(NAME(vd->fbi.rgboffs));
595		vd->save_item(NAME(vd->fbi.auxoffs));
596		vd->save_item(NAME(vd->fbi.frontbuf));
597		vd->save_item(NAME(vd->fbi.backbuf));
598		vd->save_item(NAME(vd->fbi.swaps_pending));
599		vd->save_item(NAME(vd->fbi.video_changed));
600		vd->save_item(NAME(vd->fbi.yorigin));
601		vd->save_item(NAME(vd->fbi.lfb_base));
602		vd->save_item(NAME(vd->fbi.lfb_stride));
603		vd->save_item(NAME(vd->fbi.width));
604		vd->save_item(NAME(vd->fbi.height));
605		vd->save_item(NAME(vd->fbi.xoffs));
606		vd->save_item(NAME(vd->fbi.yoffs));
607		vd->save_item(NAME(vd->fbi.vsyncscan));
608		vd->save_item(NAME(vd->fbi.rowpixels));
609		vd->save_item(NAME(vd->fbi.vblank));
610		vd->save_item(NAME(vd->fbi.vblank_count));
611		vd->save_item(NAME(vd->fbi.vblank_swap_pending));
612		vd->save_item(NAME(vd->fbi.vblank_swap));
613		vd->save_item(NAME(vd->fbi.vblank_dont_swap));
614		vd->save_item(NAME(vd->fbi.cheating_allowed));
615		vd->save_item(NAME(vd->fbi.sign));
616		vd->save_item(NAME(vd->fbi.ax));
617		vd->save_item(NAME(vd->fbi.ay));
618		vd->save_item(NAME(vd->fbi.bx));
619		vd->save_item(NAME(vd->fbi.by));
620		vd->save_item(NAME(vd->fbi.cx));
621		vd->save_item(NAME(vd->fbi.cy));
622		vd->save_item(NAME(vd->fbi.startr));
623		vd->save_item(NAME(vd->fbi.startg));
624		vd->save_item(NAME(vd->fbi.startb));
625		vd->save_item(NAME(vd->fbi.starta));
626		vd->save_item(NAME(vd->fbi.startz));
627		vd->save_item(NAME(vd->fbi.startw));
628		vd->save_item(NAME(vd->fbi.drdx));
629		vd->save_item(NAME(vd->fbi.dgdx));
630		vd->save_item(NAME(vd->fbi.dbdx));
631		vd->save_item(NAME(vd->fbi.dadx));
632		vd->save_item(NAME(vd->fbi.dzdx));
633		vd->save_item(NAME(vd->fbi.dwdx));
634		vd->save_item(NAME(vd->fbi.drdy));
635		vd->save_item(NAME(vd->fbi.dgdy));
636		vd->save_item(NAME(vd->fbi.dbdy));
637		vd->save_item(NAME(vd->fbi.dady));
638		vd->save_item(NAME(vd->fbi.dzdy));
639		vd->save_item(NAME(vd->fbi.dwdy));
640		vd->save_item(NAME(vd->fbi.lfb_stats.pixels_in));
641		vd->save_item(NAME(vd->fbi.lfb_stats.pixels_out));
642		vd->save_item(NAME(vd->fbi.lfb_stats.chroma_fail));
643		vd->save_item(NAME(vd->fbi.lfb_stats.zfunc_fail));
644		vd->save_item(NAME(vd->fbi.lfb_stats.afunc_fail));
645		vd->save_item(NAME(vd->fbi.lfb_stats.clip_fail));
646		vd->save_item(NAME(vd->fbi.lfb_stats.stipple_count));
647		vd->save_item(NAME(vd->fbi.sverts));
648		for (index = 0; index < ARRAY_LENGTH(vd->fbi.svert); index++)
	653	device->save_pointer(NAME(v->fbi.ram), v->fbi.mask + 1);
	654	device->save_item(NAME(v->fbi.rgboffs));
	655	device->save_item(NAME(v->fbi.auxoffs));
	656	device->save_item(NAME(v->fbi.frontbuf));
	657	device->save_item(NAME(v->fbi.backbuf));
	658	device->save_item(NAME(v->fbi.swaps_pending));
	659	device->save_item(NAME(v->fbi.video_changed));
	660	device->save_item(NAME(v->fbi.yorigin));
	661	device->save_item(NAME(v->fbi.lfb_base));
	662	device->save_item(NAME(v->fbi.lfb_stride));
	663	device->save_item(NAME(v->fbi.width));
	664	device->save_item(NAME(v->fbi.height));
	665	device->save_item(NAME(v->fbi.xoffs));
	666	device->save_item(NAME(v->fbi.yoffs));
	667	device->save_item(NAME(v->fbi.vsyncscan));
	668	device->save_item(NAME(v->fbi.rowpixels));
	669	device->save_item(NAME(v->fbi.vblank));
	670	device->save_item(NAME(v->fbi.vblank_count));
	671	device->save_item(NAME(v->fbi.vblank_swap_pending));
	672	device->save_item(NAME(v->fbi.vblank_swap));
	673	device->save_item(NAME(v->fbi.vblank_dont_swap));
	674	device->save_item(NAME(v->fbi.cheating_allowed));
	675	device->save_item(NAME(v->fbi.sign));
	676	device->save_item(NAME(v->fbi.ax));
	677	device->save_item(NAME(v->fbi.ay));
	678	device->save_item(NAME(v->fbi.bx));
	679	device->save_item(NAME(v->fbi.by));
	680	device->save_item(NAME(v->fbi.cx));
	681	device->save_item(NAME(v->fbi.cy));
	682	device->save_item(NAME(v->fbi.startr));
	683	device->save_item(NAME(v->fbi.startg));
	684	device->save_item(NAME(v->fbi.startb));
	685	device->save_item(NAME(v->fbi.starta));
	686	device->save_item(NAME(v->fbi.startz));
	687	device->save_item(NAME(v->fbi.startw));
	688	device->save_item(NAME(v->fbi.drdx));
	689	device->save_item(NAME(v->fbi.dgdx));
	690	device->save_item(NAME(v->fbi.dbdx));
	691	device->save_item(NAME(v->fbi.dadx));
	692	device->save_item(NAME(v->fbi.dzdx));
	693	device->save_item(NAME(v->fbi.dwdx));
	694	device->save_item(NAME(v->fbi.drdy));
	695	device->save_item(NAME(v->fbi.dgdy));
	696	device->save_item(NAME(v->fbi.dbdy));
	697	device->save_item(NAME(v->fbi.dady));
	698	device->save_item(NAME(v->fbi.dzdy));
	699	device->save_item(NAME(v->fbi.dwdy));
	700	device->save_item(NAME(v->fbi.lfb_stats.pixels_in));
	701	device->save_item(NAME(v->fbi.lfb_stats.pixels_out));
	702	device->save_item(NAME(v->fbi.lfb_stats.chroma_fail));
	703	device->save_item(NAME(v->fbi.lfb_stats.zfunc_fail));
	704	device->save_item(NAME(v->fbi.lfb_stats.afunc_fail));
	705	device->save_item(NAME(v->fbi.lfb_stats.clip_fail));
	706	device->save_item(NAME(v->fbi.lfb_stats.stipple_count));
	707	device->save_item(NAME(v->fbi.sverts));
	708	for (index = 0; index < ARRAY_LENGTH(v->fbi.svert); index++)
649	709	{
650		vd->save_item(NAME(vd->fbi.svert[index].x), index);
651		vd->save_item(NAME(vd->fbi.svert[index].y), index);
652		vd->save_item(NAME(vd->fbi.svert[index].a), index);
653		vd->save_item(NAME(vd->fbi.svert[index].r), index);
654		vd->save_item(NAME(vd->fbi.svert[index].g), index);
655		vd->save_item(NAME(vd->fbi.svert[index].b), index);
656		vd->save_item(NAME(vd->fbi.svert[index].z), index);
657		vd->save_item(NAME(vd->fbi.svert[index].wb), index);
658		vd->save_item(NAME(vd->fbi.svert[index].w0), index);
659		vd->save_item(NAME(vd->fbi.svert[index].s0), index);
660		vd->save_item(NAME(vd->fbi.svert[index].t0), index);
661		vd->save_item(NAME(vd->fbi.svert[index].w1), index);
662		vd->save_item(NAME(vd->fbi.svert[index].s1), index);
663		vd->save_item(NAME(vd->fbi.svert[index].t1), index);
	710	device->save_item(NAME(v->fbi.svert[index].x), index);
	711	device->save_item(NAME(v->fbi.svert[index].y), index);
	712	device->save_item(NAME(v->fbi.svert[index].a), index);
	713	device->save_item(NAME(v->fbi.svert[index].r), index);
	714	device->save_item(NAME(v->fbi.svert[index].g), index);
	715	device->save_item(NAME(v->fbi.svert[index].b), index);
	716	device->save_item(NAME(v->fbi.svert[index].z), index);
	717	device->save_item(NAME(v->fbi.svert[index].wb), index);
	718	device->save_item(NAME(v->fbi.svert[index].w0), index);
	719	device->save_item(NAME(v->fbi.svert[index].s0), index);
	720	device->save_item(NAME(v->fbi.svert[index].t0), index);
	721	device->save_item(NAME(v->fbi.svert[index].w1), index);
	722	device->save_item(NAME(v->fbi.svert[index].s1), index);
	723	device->save_item(NAME(v->fbi.svert[index].t1), index);
664	724	}
665		vd->save_item(NAME(vd->fbi.fifo.size));
666		vd->save_item(NAME(vd->fbi.fifo.in));
667		vd->save_item(NAME(vd->fbi.fifo.out));
668		for (index = 0; index < ARRAY_LENGTH(vd->fbi.cmdfifo); index++)
	725	device->save_item(NAME(v->fbi.fifo.size));
	726	device->save_item(NAME(v->fbi.fifo.in));
	727	device->save_item(NAME(v->fbi.fifo.out));
	728	for (index = 0; index < ARRAY_LENGTH(v->fbi.cmdfifo); index++)
669	729	{
670		vd->save_item(NAME(vd->fbi.cmdfifo[index].enable), index);
671		vd->save_item(NAME(vd->fbi.cmdfifo[index].count_holes), index);
672		vd->save_item(NAME(vd->fbi.cmdfifo[index].base), index);
673		vd->save_item(NAME(vd->fbi.cmdfifo[index].end), index);
674		vd->save_item(NAME(vd->fbi.cmdfifo[index].rdptr), index);
675		vd->save_item(NAME(vd->fbi.cmdfifo[index].amin), index);
676		vd->save_item(NAME(vd->fbi.cmdfifo[index].amax), index);
677		vd->save_item(NAME(vd->fbi.cmdfifo[index].depth), index);
678		vd->save_item(NAME(vd->fbi.cmdfifo[index].holes), index);
	730	device->save_item(NAME(v->fbi.cmdfifo[index].enable), index);
	731	device->save_item(NAME(v->fbi.cmdfifo[index].count_holes), index);
	732	device->save_item(NAME(v->fbi.cmdfifo[index].base), index);
	733	device->save_item(NAME(v->fbi.cmdfifo[index].end), index);
	734	device->save_item(NAME(v->fbi.cmdfifo[index].rdptr), index);
	735	device->save_item(NAME(v->fbi.cmdfifo[index].amin), index);
	736	device->save_item(NAME(v->fbi.cmdfifo[index].amax), index);
	737	device->save_item(NAME(v->fbi.cmdfifo[index].depth), index);
	738	device->save_item(NAME(v->fbi.cmdfifo[index].holes), index);
679	739	}
680		vd->save_item(NAME(vd->fbi.fogblend));
681		vd->save_item(NAME(vd->fbi.fogdelta));
682		vd->save_item(NAME(vd->fbi.clut));
	740	device->save_item(NAME(v->fbi.fogblend));
	741	device->save_item(NAME(v->fbi.fogdelta));
	742	device->save_item(NAME(v->fbi.clut));
683	743
684	744	/* register states: tmu */
685		for (index = 0; index < ARRAY_LENGTH(vd->tmu); index++)
	745	for (index = 0; index < ARRAY_LENGTH(v->tmu); index++)
686	746	{
687		tmu_state *tmu = &vd->tmu[index];
	747	tmu_state *tmu = &v->tmu[index];
688	748	if (tmu->ram == nullptr)
689	749	continue;
690		if (tmu->ram != vd->fbi.ram)
691		vd->save_pointer(NAME(tmu->ram), tmu->mask + 1, index);
692		vd->save_item(NAME(tmu->starts), index);
693		vd->save_item(NAME(tmu->startt), index);
694		vd->save_item(NAME(tmu->startw), index);
695		vd->save_item(NAME(tmu->dsdx), index);
696		vd->save_item(NAME(tmu->dtdx), index);
697		vd->save_item(NAME(tmu->dwdx), index);
698		vd->save_item(NAME(tmu->dsdy), index);
699		vd->save_item(NAME(tmu->dtdy), index);
700		vd->save_item(NAME(tmu->dwdy), index);
	750	if (tmu->ram != v->fbi.ram)
	751	device->save_pointer(NAME(tmu->ram), tmu->mask + 1, index);
	752	device->save_item(NAME(tmu->starts), index);
	753	device->save_item(NAME(tmu->startt), index);
	754	device->save_item(NAME(tmu->startw), index);
	755	device->save_item(NAME(tmu->dsdx), index);
	756	device->save_item(NAME(tmu->dtdx), index);
	757	device->save_item(NAME(tmu->dwdx), index);
	758	device->save_item(NAME(tmu->dsdy), index);
	759	device->save_item(NAME(tmu->dtdy), index);
	760	device->save_item(NAME(tmu->dwdy), index);
701	761	for (subindex = 0; subindex < ARRAY_LENGTH(tmu->ncc); subindex++)
702	762	{
703		vd->save_item(NAME(tmu->ncc[subindex].ir), index * ARRAY_LENGTH(tmu->ncc) + subindex);
704		vd->save_item(NAME(tmu->ncc[subindex].ig), index * ARRAY_LENGTH(tmu->ncc) + subindex);
705		vd->save_item(NAME(tmu->ncc[subindex].ib), index * ARRAY_LENGTH(tmu->ncc) + subindex);
706		vd->save_item(NAME(tmu->ncc[subindex].qr), index * ARRAY_LENGTH(tmu->ncc) + subindex);
707		vd->save_item(NAME(tmu->ncc[subindex].qg), index * ARRAY_LENGTH(tmu->ncc) + subindex);
708		vd->save_item(NAME(tmu->ncc[subindex].qb), index * ARRAY_LENGTH(tmu->ncc) + subindex);
709		vd->save_item(NAME(tmu->ncc[subindex].y), index * ARRAY_LENGTH(tmu->ncc) + subindex);
	763	device->save_item(NAME(tmu->ncc[subindex].ir), index * ARRAY_LENGTH(tmu->ncc) + subindex);
	764	device->save_item(NAME(tmu->ncc[subindex].ig), index * ARRAY_LENGTH(tmu->ncc) + subindex);
	765	device->save_item(NAME(tmu->ncc[subindex].ib), index * ARRAY_LENGTH(tmu->ncc) + subindex);
	766	device->save_item(NAME(tmu->ncc[subindex].qr), index * ARRAY_LENGTH(tmu->ncc) + subindex);
	767	device->save_item(NAME(tmu->ncc[subindex].qg), index * ARRAY_LENGTH(tmu->ncc) + subindex);
	768	device->save_item(NAME(tmu->ncc[subindex].qb), index * ARRAY_LENGTH(tmu->ncc) + subindex);
	769	device->save_item(NAME(tmu->ncc[subindex].y), index * ARRAY_LENGTH(tmu->ncc) + subindex);
710	770	}
711	771	}
712	772
713	773	/* register states: banshee */
714		if (vd->~~vd_~~type >= TYPE_VOODOO_BANSHEE)
	774	if (v->type >= TYPE_VOODOO_BANSHEE)
715	775	{
716		vd->save_item(NAME(vd->banshee.io));
717		vd->save_item(NAME(vd->banshee.agp));
718		vd->save_item(NAME(vd->banshee.vga));
719		vd->save_item(NAME(vd->banshee.crtc));
720		vd->save_item(NAME(vd->banshee.seq));
721		vd->save_item(NAME(vd->banshee.gc));
722		vd->save_item(NAME(vd->banshee.att));
723		vd->save_item(NAME(vd->banshee.attff));
	776	device->save_item(NAME(v->banshee.io));
	777	device->save_item(NAME(v->banshee.agp));
	778	device->save_item(NAME(v->banshee.vga));
	779	device->save_item(NAME(v->banshee.crtc));
	780	device->save_item(NAME(v->banshee.seq));
	781	device->save_item(NAME(v->banshee.gc));
	782	device->save_item(NAME(v->banshee.att));
	783	device->save_item(NAME(v->banshee.attff));
724	784	}
725	785	}
726	786
r253151	r253152
732	792	*
733	793	*************************************/
734	794
735		static void accumulate_statistics(voodoo_de~~vice~~ vd, const stats_block stats)
	795	static void accumulate_statistics(voodoo_state v, const stats_block stats)
736	796	{
737	797	/* apply internal voodoo statistics */
738		vd->reg[fbiPixelsIn].u += stats->pixels_in;
739		vd->reg[fbiPixelsOut].u += stats->pixels_out;
740		vd->reg[fbiChromaFail].u += stats->chroma_fail;
741		vd->reg[fbiZfuncFail].u += stats->zfunc_fail;
742		vd->reg[fbiAfuncFail].u += stats->afunc_fail;
	798	v->reg[fbiPixelsIn].u += stats->pixels_in;
	799	v->reg[fbiPixelsOut].u += stats->pixels_out;
	800	v->reg[fbiChromaFail].u += stats->chroma_fail;
	801	v->reg[fbiZfuncFail].u += stats->zfunc_fail;
	802	v->reg[fbiAfuncFail].u += stats->afunc_fail;
743	803
744	804	/* apply emulation statistics */
745		vd->stats.total_pixels_in += stats->pixels_in;
746		vd->stats.total_pixels_out += stats->pixels_out;
747		vd->stats.total_chroma_fail += stats->chroma_fail;
748		vd->stats.total_zfunc_fail += stats->zfunc_fail;
749		vd->stats.total_afunc_fail += stats->afunc_fail;
750		vd->stats.total_clipped += stats->clip_fail;
751		vd->stats.total_stippled += stats->stipple_count;
	805	v->stats.total_pixels_in += stats->pixels_in;
	806	v->stats.total_pixels_out += stats->pixels_out;
	807	v->stats.total_chroma_fail += stats->chroma_fail;
	808	v->stats.total_zfunc_fail += stats->zfunc_fail;
	809	v->stats.total_afunc_fail += stats->afunc_fail;
	810	v->stats.total_clipped += stats->clip_fail;
	811	v->stats.total_stippled += stats->stipple_count;
752	812	}
753	813
754	814
755		static void update_statistics(voodoo_de~~vice~~ *vd, int accumulate)
	815	static void update_statistics(voodoo_state *v, int accumulate)
756	816	{
757	817	int threadnum;
758	818
r253151	r253152
760	820	for (threadnum = 0; threadnum < WORK_MAX_THREADS; threadnum++)
761	821	{
762	822	if (accumulate)
763		accumulate_statistics(vd, &vd->thread_stats[threadnum]);
764		memset(&vd->thread_stats[threadnum], 0, sizeof(vd->thread_stats[threadnum]));
	823	accumulate_statistics(v, &v->thread_stats[threadnum]);
	824	memset(&v->thread_stats[threadnum], 0, sizeof(v->thread_stats[threadnum]));
765	825	}
766	826
767	827	/* accumulate/reset statistics from the LFB */
768	828	if (accumulate)
769		accumulate_statistics(vd, &vd->fbi.lfb_stats);
770		memset(&vd->fbi.lfb_stats, 0, sizeof(vd->fbi.lfb_stats));
	829	accumulate_statistics(v, &v->fbi.lfb_stats);
	830	memset(&v->fbi.lfb_stats, 0, sizeof(v->fbi.lfb_stats));
771	831	}
772	832
773	833
r253151	r253152
778	838	*
779	839	*************************************/
780	840
781		void vo~~odoo_dev~~i~~ce::~~swap_buffers(voodoo_de~~vice~~ *vd)
	841	static void swap_buffers(voodoo_state *v)
782	842	{
783	843	int count;
784	844
785		if (LOG_VBLANK_SWAP) vd->device->logerror("--- swap_buffers @ %d\n", vd->screen->vpos());
	845	if (LOG_VBLANK_SWAP) v->device->logerror("--- swap_buffers @ %d\n", v->screen->vpos());
786	846
787	847	/* force a partial update */
788		vd->screen->update_partial(vd->screen->vpos());
789		vd->fbi.video_changed = TRUE;
	848	v->screen->update_partial(v->screen->vpos());
	849	v->fbi.video_changed = TRUE;
790	850
791	851	/* keep a history of swap intervals */
792		count = vd->fbi.vblank_count;
	852	count = v->fbi.vblank_count;
793	853	if (count > 15)
794	854	count = 15;
795		vd->reg[fbiSwapHistory].u = (vd->reg[fbiSwapHistory].u << 4) \| count;
	855	v->reg[fbiSwapHistory].u = (v->reg[fbiSwapHistory].u << 4) \| count;
796	856
797	857	/* rotate the buffers */
798		if (vd->~~vd_~~type <= TYPE_VOODOO_2)
	858	if (v->type <= TYPE_VOODOO_2)
799	859	{
800		if (vd->~~vd_~~type < TYPE_VOODOO_2 \|\| !vd->fbi.vblank_dont_swap)
	860	if (v->type < TYPE_VOODOO_2 \|\| !v->fbi.vblank_dont_swap)
801	861	{
802		if (vd->fbi.rgboffs[2] == ~0)
	862	if (v->fbi.rgboffs[2] == ~0)
803	863	{
804		vd->fbi.frontbuf = 1 - vd->fbi.frontbuf;
805		vd->fbi.backbuf = 1 - vd->fbi.frontbuf;
	864	v->fbi.frontbuf = 1 - v->fbi.frontbuf;
	865	v->fbi.backbuf = 1 - v->fbi.frontbuf;
806	866	}
807	867	else
808	868	{
809		vd->fbi.frontbuf = (vd->fbi.frontbuf + 1) % 3;
810		vd->fbi.backbuf = (vd->fbi.frontbuf + 1) % 3;
	869	v->fbi.frontbuf = (v->fbi.frontbuf + 1) % 3;
	870	v->fbi.backbuf = (v->fbi.frontbuf + 1) % 3;
811	871	}
812	872	}
813	873	}
814	874	else
815		vd->fbi.rgboffs[0] = vd->reg[leftOverlayBuf].u & vd->fbi.mask & ~0x0f;
	875	v->fbi.rgboffs[0] = v->reg[leftOverlayBuf].u & v->fbi.mask & ~0x0f;
816	876
817	877	/* decrement the pending count and reset our state */
818		if (vd->fbi.swaps_pending)
819		vd->fbi.swaps_pending--;
820		vd->fbi.vblank_count = 0;
821		vd->fbi.vblank_swap_pending = FALSE;
	878	if (v->fbi.swaps_pending)
	879	v->fbi.swaps_pending--;
	880	v->fbi.vblank_count = 0;
	881	v->fbi.vblank_swap_pending = FALSE;
822	882
823	883	/* reset the last_op_time to now and start processing the next command */
824		if (vd->pci.op_pending)
	884	if (v->pci.op_pending)
825	885	{
826		vd->pci.op_end_time = vd->device->machine().time();
827		flush_fifos(vd, vd->pci.op_end_time);
	886	v->pci.op_end_time = v->device->machine().time();
	887	flush_fifos(v, v->pci.op_end_time);
828	888	}
829	889
830	890	/* we may be able to unstall now */
831		if (vd->pci.stall_state != NOT_STALLED)
832		check_stalled_cpu(vd, vd->device->machine().time());
	891	if (v->pci.stall_state != NOT_STALLED)
	892	check_stalled_cpu(v, v->device->machine().time());
833	893
834	894	/* periodically log rasterizer info */
835		vd->stats.swaps++;
836		if (LOG_RASTERIZERS && vd->stats.swaps % 1000 == 0)
837		dump_rasterizer_stats(vd);
	895	v->stats.swaps++;
	896	if (LOG_RASTERIZERS && v->stats.swaps % 1000 == 0)
	897	dump_rasterizer_stats(v);
838	898
839	899	/* update the statistics (debug) */
840		if (vd->stats.display)
	900	if (v->stats.display)
841	901	{
842		const rectangle &visible_area = vd->screen->visible_area();
	902	const rectangle &visible_area = v->screen->visible_area();
843	903	int screen_area = visible_area.width() * visible_area.height();
844		char *statsptr = vd->stats.buffer;
	904	char *statsptr = v->stats.buffer;
845	905	int pixelcount;
846	906	int i;
847	907
848		update_statistics(vd, TRUE);
849		pixelcount = vd->stats.total_pixels_out;
	908	update_statistics(v, TRUE);
	909	pixelcount = v->stats.total_pixels_out;
850	910
851		statsptr += sprintf(statsptr, "Swap:%6d\n", vd->stats.swaps);
852		statsptr += sprintf(statsptr, "Hist:%08X\n", vd->reg[fbiSwapHistory].u);
853		statsptr += sprintf(statsptr, "Stal:%6d\n", vd->stats.stalls);
	911	statsptr += sprintf(statsptr, "Swap:%6d\n", v->stats.swaps);
	912	statsptr += sprintf(statsptr, "Hist:%08X\n", v->reg[fbiSwapHistory].u);
	913	statsptr += sprintf(statsptr, "Stal:%6d\n", v->stats.stalls);
854	914	statsptr += sprintf(statsptr, "Rend:%6d%%\n", pixelcount * 100 / screen_area);
855		statsptr += sprintf(statsptr, "Poly:%6d\n", vd->stats.total_triangles);
856		statsptr += sprintf(statsptr, "PxIn:%6d\n", vd->stats.total_pixels_in);
857		statsptr += sprintf(statsptr, "POut:%6d\n", vd->stats.total_pixels_out);
858		statsptr += sprintf(statsptr, "Clip:%6d\n", vd->stats.total_clipped);
859		statsptr += sprintf(statsptr, "Stip:%6d\n", vd->stats.total_stippled);
860		statsptr += sprintf(statsptr, "Chro:%6d\n", vd->stats.total_chroma_fail);
861		statsptr += sprintf(statsptr, "ZFun:%6d\n", vd->stats.total_zfunc_fail);
862		statsptr += sprintf(statsptr, "AFun:%6d\n", vd->stats.total_afunc_fail);
863		statsptr += sprintf(statsptr, "RegW:%6d\n", vd->stats.reg_writes);
864		statsptr += sprintf(statsptr, "RegR:%6d\n", vd->stats.reg_reads);
865		statsptr += sprintf(statsptr, "LFBW:%6d\n", vd->stats.lfb_writes);
866		statsptr += sprintf(statsptr, "LFBR:%6d\n", vd->stats.lfb_reads);
867		statsptr += sprintf(statsptr, "TexW:%6d\n", vd->stats.tex_writes);
	915	statsptr += sprintf(statsptr, "Poly:%6d\n", v->stats.total_triangles);
	916	statsptr += sprintf(statsptr, "PxIn:%6d\n", v->stats.total_pixels_in);
	917	statsptr += sprintf(statsptr, "POut:%6d\n", v->stats.total_pixels_out);
	918	statsptr += sprintf(statsptr, "Clip:%6d\n", v->stats.total_clipped);
	919	statsptr += sprintf(statsptr, "Stip:%6d\n", v->stats.total_stippled);
	920	statsptr += sprintf(statsptr, "Chro:%6d\n", v->stats.total_chroma_fail);
	921	statsptr += sprintf(statsptr, "ZFun:%6d\n", v->stats.total_zfunc_fail);
	922	statsptr += sprintf(statsptr, "AFun:%6d\n", v->stats.total_afunc_fail);
	923	statsptr += sprintf(statsptr, "RegW:%6d\n", v->stats.reg_writes);
	924	statsptr += sprintf(statsptr, "RegR:%6d\n", v->stats.reg_reads);
	925	statsptr += sprintf(statsptr, "LFBW:%6d\n", v->stats.lfb_writes);
	926	statsptr += sprintf(statsptr, "LFBR:%6d\n", v->stats.lfb_reads);
	927	statsptr += sprintf(statsptr, "TexW:%6d\n", v->stats.tex_writes);
868	928	statsptr += sprintf(statsptr, "TexM:");
869	929	for (i = 0; i < 16; i++)
870		if (vd->stats.texture_mode[i])
	930	if (v->stats.texture_mode[i])
871	931	*statsptr++ = "0123456789ABCDEF"[i];
872	932	*statsptr = 0;
873	933	}
874	934
875	935	/* update statistics */
876		vd->stats.stalls = 0;
877		vd->stats.total_triangles = 0;
878		vd->stats.total_pixels_in = 0;
879		vd->stats.total_pixels_out = 0;
880		vd->stats.total_chroma_fail = 0;
881		vd->stats.total_zfunc_fail = 0;
882		vd->stats.total_afunc_fail = 0;
883		vd->stats.total_clipped = 0;
884		vd->stats.total_stippled = 0;
885		vd->stats.reg_writes = 0;
886		vd->stats.reg_reads = 0;
887		vd->stats.lfb_writes = 0;
888		vd->stats.lfb_reads = 0;
889		vd->stats.tex_writes = 0;
890		memset(vd->stats.texture_mode, 0, sizeof(vd->stats.texture_mode));
	936	v->stats.stalls = 0;
	937	v->stats.total_triangles = 0;
	938	v->stats.total_pixels_in = 0;
	939	v->stats.total_pixels_out = 0;
	940	v->stats.total_chroma_fail = 0;
	941	v->stats.total_zfunc_fail = 0;
	942	v->stats.total_afunc_fail = 0;
	943	v->stats.total_clipped = 0;
	944	v->stats.total_stippled = 0;
	945	v->stats.reg_writes = 0;
	946	v->stats.reg_reads = 0;
	947	v->stats.lfb_writes = 0;
	948	v->stats.lfb_reads = 0;
	949	v->stats.tex_writes = 0;
	950	memset(v->stats.texture_mode, 0, sizeof(v->stats.texture_mode));
891	951	}
892	952
893	953
894		static void adjust_vblank_timer(voodoo_de~~vice~~ *vd)
	954	static void adjust_vblank_timer(voodoo_state *v)
895	955	{
896		attotime vblank_period = vd->screen->time_until_pos(vd->fbi.vsyncscan);
	956	attotime vblank_period = v->screen->time_until_pos(v->fbi.vsyncscan);
897	957
898	958	/* if zero, adjust to next frame, otherwise we may get stuck in an infinite loop */
899	959	if (vblank_period == attotime::zero)
900		vblank_period = vd->screen->frame_period();
901		vd->fbi.vblank_timer->adjust(vblank_period);
	960	vblank_period = v->screen->frame_period();
	961	v->fbi.vblank_timer->adjust(vblank_period);
902	962	}
903	963
904	964
905		TIMER_CALLBACK~~_MEMBER~~( ~~voodoo_device::~~vblank_off_callback )
	965	static TIMER_CALLBACK( vblank_off_callback )
906	966	{
907		~~if (LOG_VBLANK_SWAP) de~~v~~ice->l~~o~~gerr~~o~~r("---~~ v~~blank~~ end~~\n"~~);
	967	voodoo_state v = (voodoo_state )ptr;
908	968
	969	if (LOG_VBLANK_SWAP) v->device->logerror("--- vblank end\n");
	970
909	971	/* set internal state and call the client */
910		fbi.vblank = FALSE;
	972	v->fbi.vblank = FALSE;
911	973
912	974	// TODO: Vblank IRQ enable is VOODOO3 only?
913		if (vd_type >= TYPE_VOODOO_3)
	975	if (v->type >= TYPE_VOODOO_3)
914	976	{
915		if (reg[intrCtrl].u & 0x8) // call IRQ handler if VSYNC interrupt (falling) is enabled
	977	if (v->reg[intrCtrl].u & 0x8) // call IRQ handler if VSYNC interrupt (falling) is enabled
916	978	{
917		reg[intrCtrl].u \|= 0x200; // VSYNC int (falling) active
	979	v->reg[intrCtrl].u \|= 0x200; // VSYNC int (falling) active
918	980
919		if (!device->m_vblank.isnull())
920		device->m_vblank(FALSE);
	981	if (!v->device->m_vblank.isnull())
	982	v->device->m_vblank(FALSE);
921	983
922	984	}
923	985	}
924	986	else
925	987	{
926		if (!device->m_vblank.isnull())
927		device->m_vblank(FALSE);
	988	if (!v->device->m_vblank.isnull())
	989	v->device->m_vblank(FALSE);
928	990	}
929	991
930	992	/* go to the end of the next frame */
931		adjust_vblank_timer(~~this~~);
	993	adjust_vblank_timer(v);
932	994	}
933	995
934	996
935		TIMER_CALLBACK~~_MEMBER~~( ~~voodoo_device::~~vblank_callback )
	997	static TIMER_CALLBACK( vblank_callback )
936	998	{
937		~~if (LOG_VBLANK_SWAP) de~~v~~ice->l~~o~~gerr~~o~~r("---~~ v~~blank~~ start~~\n"~~);
	999	voodoo_state v = (voodoo_state )ptr;
938	1000
	1001	if (LOG_VBLANK_SWAP) v->device->logerror("--- vblank start\n");
	1002
939	1003	/* flush the pipes */
940		if (pci.op_pending)
	1004	if (v->pci.op_pending)
941	1005	{
942		if (LOG_VBLANK_SWAP) device->logerror("---- vblank flush begin\n");
943		flush_fifos(this, machine().time());
944		if (LOG_VBLANK_SWAP) device->logerror("---- vblank flush end\n");
	1006	if (LOG_VBLANK_SWAP) v->device->logerror("---- vblank flush begin\n");
	1007	flush_fifos(v, machine.time());
	1008	if (LOG_VBLANK_SWAP) v->device->logerror("---- vblank flush end\n");
945	1009	}
946	1010
947	1011	/* increment the count */
948		fbi.vblank_count++;
949		if (fbi.vblank_count > 250)
950		fbi.vblank_count = 250;
951		if (LOG_VBLANK_SWAP) device->logerror("---- vblank count = %d", fbi.vblank_count);
952		if (fbi.vblank_swap_pending)
953		if (LOG_VBLANK_SWAP) device->logerror(" (target=%d)", fbi.vblank_swap);
954		if (LOG_VBLANK_SWAP) device->logerror("\n");
	1012	v->fbi.vblank_count++;
	1013	if (v->fbi.vblank_count > 250)
	1014	v->fbi.vblank_count = 250;
	1015	if (LOG_VBLANK_SWAP) v->device->logerror("---- vblank count = %d", v->fbi.vblank_count);
	1016	if (v->fbi.vblank_swap_pending)
	1017	if (LOG_VBLANK_SWAP) v->device->logerror(" (target=%d)", v->fbi.vblank_swap);
	1018	if (LOG_VBLANK_SWAP) v->device->logerror("\n");
955	1019
956	1020	/* if we're past the swap count, do the swap */
957		if (fbi.vblank_swap_pending && fbi.vblank_count >= fbi.vblank_swap)
958		swap_buffers(this);
	1021	if (v->fbi.vblank_swap_pending && v->fbi.vblank_count >= v->fbi.vblank_swap)
	1022	swap_buffers(v);
959	1023
960	1024	/* set a timer for the next off state */
961		machine().scheduler().timer_set(screen->time_until_pos(0), ~~timer_expired_delegate(~~FUNC(v~~oodoo_device::v~~blank_off_callback),~~this),~~ 0, ~~this~~);
	1025	machine.scheduler().timer_set(v->screen->time_until_pos(0), FUNC(vblank_off_callback), 0, v);
962	1026
963
964
965	1027	/* set internal state and call the client */
966		fbi.vblank = TRUE;
	1028	v->fbi.vblank = TRUE;
967	1029
968	1030	// TODO: Vblank IRQ enable is VOODOO3 only?
969		if (vd_type >= TYPE_VOODOO_3)
	1031	if (v->type >= TYPE_VOODOO_3)
970	1032	{
971		if (reg[intrCtrl].u & 0x4) // call IRQ handler if VSYNC interrupt (rising) is enabled
	1033	if (v->reg[intrCtrl].u & 0x4) // call IRQ handler if VSYNC interrupt (rising) is enabled
972	1034	{
973		reg[intrCtrl].u \|= 0x100; // VSYNC int (rising) active
	1035	v->reg[intrCtrl].u \|= 0x100; // VSYNC int (rising) active
974	1036
975		if (!device->m_vblank.isnull())
976		device->m_vblank(TRUE);
	1037	if (!v->device->m_vblank.isnull())
	1038	v->device->m_vblank(TRUE);
977	1039	}
978	1040	}
979	1041	else
980	1042	{
981		if (!device->m_vblank.isnull())
982		device->m_vblank(TRUE);
	1043	if (!v->device->m_vblank.isnull())
	1044	v->device->m_vblank(TRUE);
983	1045	}
984	1046	}
985	1047
r253151	r253152
991	1053	*
992	1054	*************************************/
993	1055
994		static void reset_counters(voodoo_de~~vice~~ *vd)
	1056	static void reset_counters(voodoo_state *v)
995	1057	{
996		update_statistics(vd, FALSE);
997		vd->reg[fbiPixelsIn].u = 0;
998		vd->reg[fbiChromaFail].u = 0;
999		vd->reg[fbiZfuncFail].u = 0;
1000		vd->reg[fbiAfuncFail].u = 0;
1001		vd->reg[fbiPixelsOut].u = 0;
	1058	update_statistics(v, FALSE);
	1059	v->reg[fbiPixelsIn].u = 0;
	1060	v->reg[fbiChromaFail].u = 0;
	1061	v->reg[fbiZfuncFail].u = 0;
	1062	v->reg[fbiAfuncFail].u = 0;
	1063	v->reg[fbiPixelsOut].u = 0;
1002	1064	}
1003	1065
1004	1066
1005		void vo~~odoo_dev~~i~~ce::~~soft_reset(voodoo_de~~vice~~ *vd)
	1067	static void soft_reset(voodoo_state *v)
1006	1068	{
1007		reset_counters(vd);
1008		vd->reg[fbiTrianglesOut].u = 0;
1009		fifo_reset(&vd->fbi.fifo);
1010		fifo_reset(&vd->pci.fifo);
	1069	reset_counters(v);
	1070	v->reg[fbiTrianglesOut].u = 0;
	1071	fifo_reset(&v->fbi.fifo);
	1072	fifo_reset(&v->pci.fifo);
1011	1073	}
1012	1074
1013	1075
r253151	r253152
1018	1080	*
1019	1081	*************************************/
1020	1082
1021		void vo~~odoo_dev~~i~~ce::~~recompute_video_memory(voodoo_de~~vice~~ *vd)
	1083	static void recompute_video_memory(voodoo_state *v)
1022	1084	{
1023		UINT32 buffer_pages = FBIINIT2_VIDEO_BUFFER_OFFSET(vd->reg[fbiInit2].u);
1024		UINT32 fifo_start_page = FBIINIT4_MEMORY_FIFO_START_ROW(vd->reg[fbiInit4].u);
1025		UINT32 fifo_last_page = FBIINIT4_MEMORY_FIFO_STOP_ROW(vd->reg[fbiInit4].u);
	1085	UINT32 buffer_pages = FBIINIT2_VIDEO_BUFFER_OFFSET(v->reg[fbiInit2].u);
	1086	UINT32 fifo_start_page = FBIINIT4_MEMORY_FIFO_START_ROW(v->reg[fbiInit4].u);
	1087	UINT32 fifo_last_page = FBIINIT4_MEMORY_FIFO_STOP_ROW(v->reg[fbiInit4].u);
1026	1088	UINT32 memory_config;
1027	1089	int buf;
1028	1090
1029	1091	/* memory config is determined differently between V1 and V2 */
1030		memory_config = FBIINIT2_ENABLE_TRIPLE_BUF(vd->reg[fbiInit2].u);
1031		if (vd->vd_type == TYPE_VOODOO_2 && memory_config == 0)
1032		memory_config = FBIINIT5_BUFFER_ALLOCATION(vd->reg[fbiInit5].u);
	1092	memory_config = FBIINIT2_ENABLE_TRIPLE_BUF(v->reg[fbiInit2].u);
	1093	if (v->type == TYPE_VOODOO_2 && memory_config == 0)
	1094	memory_config = FBIINIT5_BUFFER_ALLOCATION(v->reg[fbiInit5].u);
1033	1095
1034	1096	/* tiles are 64x16/32; x_tiles specifies how many half-tiles */
1035		vd->fbi.tile_width = (vd->vd_type == TYPE_VOODOO_1) ? 64 : 32;
1036		vd->fbi.tile_height = (vd->vd_type == TYPE_VOODOO_1) ? 16 : 32;
1037		vd->fbi.x_tiles = FBIINIT1_X_VIDEO_TILES(vd->reg[fbiInit1].u);
1038		if (vd->vd_type == TYPE_VOODOO_2)
	1097	v->fbi.tile_width = (v->type == TYPE_VOODOO_1) ? 64 : 32;
	1098	v->fbi.tile_height = (v->type == TYPE_VOODOO_1) ? 16 : 32;
	1099	v->fbi.x_tiles = FBIINIT1_X_VIDEO_TILES(v->reg[fbiInit1].u);
	1100	if (v->type == TYPE_VOODOO_2)
1039	1101	{
1040		vd->fbi.x_tiles = (vd->fbi.x_tiles << 1) \|
1041		(FBIINIT1_X_VIDEO_TILES_BIT5(vd->reg[fbiInit1].u) << 5) \|
1042		(FBIINIT6_X_VIDEO_TILES_BIT0(vd->reg[fbiInit6].u));
	1102	v->fbi.x_tiles = (v->fbi.x_tiles << 1) \|
	1103	(FBIINIT1_X_VIDEO_TILES_BIT5(v->reg[fbiInit1].u) << 5) \|
	1104	(FBIINIT6_X_VIDEO_TILES_BIT0(v->reg[fbiInit6].u));
1043	1105	}
1044		vd->fbi.rowpixels = vd->fbi.tile_width * vd->fbi.x_tiles;
	1106	v->fbi.rowpixels = v->fbi.tile_width * v->fbi.x_tiles;
1045	1107
1046		// logerror("VOODOO.%d.VIDMEM: buffer_pages=%X fifo=%X-%X tiles=%X rowpix=%d\n", vd->index, buffer_pages, fifo_start_page, fifo_last_page, vd->fbi.x_tiles, vd->fbi.rowpixels);
	1108	// logerror("VOODOO.%d.VIDMEM: buffer_pages=%X fifo=%X-%X tiles=%X rowpix=%d\n", v->index, buffer_pages, fifo_start_page, fifo_last_page, v->fbi.x_tiles, v->fbi.rowpixels);
1047	1109
1048	1110	/* first RGB buffer always starts at 0 */
1049		vd->fbi.rgboffs[0] = 0;
	1111	v->fbi.rgboffs[0] = 0;
1050	1112
1051	1113	/* second RGB buffer starts immediately afterwards */
1052		vd->fbi.rgboffs[1] = buffer_pages * 0x1000;
	1114	v->fbi.rgboffs[1] = buffer_pages * 0x1000;
1053	1115
1054	1116	/* remaining buffers are based on the config */
1055	1117	switch (memory_config)
1056	1118	{
1057	1119	case 3: /* reserved */
1058		vd->device->logerror("VOODOO.%d.ERROR:Unexpected memory configuration in recompute_video_memory!\n", vd->index);
	1120	v->device->logerror("VOODOO.%d.ERROR:Unexpected memory configuration in recompute_video_memory!\n", v->index);
1059	1121
1060	1122	case 0: /* 2 color buffers, 1 aux buffer */
1061		vd->fbi.rgboffs[2] = ~0;
1062		vd->fbi.auxoffs = 2 * buffer_pages * 0x1000;
	1123	v->fbi.rgboffs[2] = ~0;
	1124	v->fbi.auxoffs = 2 * buffer_pages * 0x1000;
1063	1125	break;
1064	1126
1065	1127	case 1: /* 3 color buffers, 0 aux buffers */
1066		vd->fbi.rgboffs[2] = 2 * buffer_pages * 0x1000;
1067		vd->fbi.auxoffs = ~0;
	1128	v->fbi.rgboffs[2] = 2 * buffer_pages * 0x1000;
	1129	v->fbi.auxoffs = ~0;
1068	1130	break;
1069	1131
1070	1132	case 2: /* 3 color buffers, 1 aux buffers */
1071		vd->fbi.rgboffs[2] = 2 * buffer_pages * 0x1000;
1072		vd->fbi.auxoffs = 3 * buffer_pages * 0x1000;
	1133	v->fbi.rgboffs[2] = 2 * buffer_pages * 0x1000;
	1134	v->fbi.auxoffs = 3 * buffer_pages * 0x1000;
1073	1135	break;
1074	1136	}
1075	1137
1076	1138	/* clamp the RGB buffers to video memory */
1077	1139	for (buf = 0; buf < 3; buf++)
1078		if (vd->fbi.rgboffs[buf] != ~0 && vd->fbi.rgboffs[buf] > vd->fbi.mask)
1079		vd->fbi.rgboffs[buf] = vd->fbi.mask;
	1140	if (v->fbi.rgboffs[buf] != ~0 && v->fbi.rgboffs[buf] > v->fbi.mask)
	1141	v->fbi.rgboffs[buf] = v->fbi.mask;
1080	1142
1081	1143	/* clamp the aux buffer to video memory */
1082		if (vd->fbi.auxoffs != ~0 && vd->fbi.auxoffs > vd->fbi.mask)
1083		vd->fbi.auxoffs = vd->fbi.mask;
	1144	if (v->fbi.auxoffs != ~0 && v->fbi.auxoffs > v->fbi.mask)
	1145	v->fbi.auxoffs = v->fbi.mask;
1084	1146
1085	1147	/* osd_printf_debug("rgb[0] = %08X rgb[1] = %08X rgb[2] = %08X aux = %08X\n",
1086		vd->fbi.rgboffs[0], vd->fbi.rgboffs[1], vd->fbi.rgboffs[2], vd->fbi.auxoffs);*/
	1148	v->fbi.rgboffs[0], v->fbi.rgboffs[1], v->fbi.rgboffs[2], v->fbi.auxoffs);*/
1087	1149
1088	1150	/* compute the memory FIFO location and size */
1089		if (fifo_last_page > vd->fbi.mask / 0x1000)
1090		fifo_last_page = vd->fbi.mask / 0x1000;
	1151	if (fifo_last_page > v->fbi.mask / 0x1000)
	1152	fifo_last_page = v->fbi.mask / 0x1000;
1091	1153
1092	1154	/* is it valid and enabled? */
1093		if (fifo_start_page <= fifo_last_page && FBIINIT0_ENABLE_MEMORY_FIFO(vd->reg[fbiInit0].u))
	1155	if (fifo_start_page <= fifo_last_page && FBIINIT0_ENABLE_MEMORY_FIFO(v->reg[fbiInit0].u))
1094	1156	{
1095		vd->fbi.fifo.base = (UINT32 )(vd->fbi.ram + fifo_start_page 0x1000);
1096		vd->fbi.fifo.size = (fifo_last_page + 1 - fifo_start_page) * 0x1000 / 4;
1097		if (vd->fbi.fifo.size > 65536*2)
1098		vd->fbi.fifo.size = 65536*2;
	1157	v->fbi.fifo.base = (UINT32 )(v->fbi.ram + fifo_start_page 0x1000);
	1158	v->fbi.fifo.size = (fifo_last_page + 1 - fifo_start_page) * 0x1000 / 4;
	1159	if (v->fbi.fifo.size > 65536*2)
	1160	v->fbi.fifo.size = 65536*2;
1099	1161	}
1100	1162
1101	1163	/* if not, disable the FIFO */
1102	1164	else
1103	1165	{
1104		vd->fbi.fifo.base = nullptr;
1105		vd->fbi.fifo.size = 0;
	1166	v->fbi.fifo.base = nullptr;
	1167	v->fbi.fifo.size = 0;
1106	1168	}
1107	1169
1108	1170	/* reset the FIFO */
1109		fifo_reset(&vd->fbi.fifo);
	1171	fifo_reset(&v->fbi.fifo);
1110	1172
1111	1173	/* reset our front/back buffers if they are out of range */
1112		if (vd->fbi.rgboffs[2] == ~0)
	1174	if (v->fbi.rgboffs[2] == ~0)
1113	1175	{
1114		if (vd->fbi.frontbuf == 2)
1115		vd->fbi.frontbuf = 0;
1116		if (vd->fbi.backbuf == 2)
1117		vd->fbi.backbuf = 0;
	1176	if (v->fbi.frontbuf == 2)
	1177	v->fbi.frontbuf = 0;
	1178	if (v->fbi.backbuf == 2)
	1179	v->fbi.backbuf = 0;
1118	1180	}
1119	1181	}
1120	1182
r253151	r253152
1414	1476	*
1415	1477	*************************************/
1416	1478
1417		static int cmdfifo_compute_expected_depth(voodoo_de~~vice~~ vd, cmdfifo_info f)
	1479	static int cmdfifo_compute_expected_depth(voodoo_state v, cmdfifo_info f)
1418	1480	{
1419		UINT32 fifobase = (UINT32 )vd->fbi.ram;
	1481	UINT32 fifobase = (UINT32 )v->fbi.ram;
1420	1482	UINT32 readptr = f->rdptr;
1421	1483	UINT32 command = fifobase[readptr / 4];
1422	1484	int i, count = 0;
r253151	r253152
1554	1616	*
1555	1617	*************************************/
1556	1618
1557		UINT32 ~~voodoo_devi~~c~~e::c~~mdfifo_execute(voodoo_de~~vice~~ vd, cmdfifo_info f)
	1619	static UINT32 cmdfifo_execute(voodoo_state v, cmdfifo_info f)
1558	1620	{
1559		UINT32 fifobase = (UINT32 )vd->fbi.ram;
	1621	UINT32 fifobase = (UINT32 )v->fbi.ram;
1560	1622	UINT32 readptr = f->rdptr;
1561	1623	UINT32 *src = &fifobase[readptr / 4];
1562	1624	UINT32 command = *src++;
r253151	r253152
1587	1649	switch ((command >> 3) & 7)
1588	1650	{
1589	1651	case 0: /* NOP */
1590		if (LOG_CMDFIFO) vd->device->logerror(" NOP\n");
	1652	if (LOG_CMDFIFO) v->device->logerror(" NOP\n");
1591	1653	break;
1592	1654
1593	1655	case 1: /* JSR */
1594		if (LOG_CMDFIFO) vd->device->logerror(" JSR $%06X\n", target);
	1656	if (LOG_CMDFIFO) v->device->logerror(" JSR $%06X\n", target);
1595	1657	osd_printf_debug("JSR in CMDFIFO!\n");
1596	1658	src = &fifobase[target / 4];
1597	1659	break;
1598	1660
1599	1661	case 2: /* RET */
1600		if (LOG_CMDFIFO) vd->device->logerror(" RET $%06X\n", target);
	1662	if (LOG_CMDFIFO) v->device->logerror(" RET $%06X\n", target);
1601	1663	fatalerror("RET in CMDFIFO!\n");
1602	1664
1603	1665	case 3: /* JMP LOCAL FRAME BUFFER */
1604		if (LOG_CMDFIFO) vd->device->logerror(" JMP LOCAL FRAMEBUF $%06X\n", target);
	1666	if (LOG_CMDFIFO) v->device->logerror(" JMP LOCAL FRAMEBUF $%06X\n", target);
1605	1667	src = &fifobase[target / 4];
1606	1668	break;
1607	1669
1608	1670	case 4: /* JMP AGP */
1609		if (LOG_CMDFIFO) vd->device->logerror(" JMP AGP $%06X\n", target);
	1671	if (LOG_CMDFIFO) v->device->logerror(" JMP AGP $%06X\n", target);
1610	1672	fatalerror("JMP AGP in CMDFIFO!\n");
1611	1673	src = &fifobase[target / 4];
1612	1674	break;
r253151	r253152
1634	1696	inc = (command >> 15) & 1;
1635	1697	target = (command >> 3) & 0xfff;
1636	1698
1637		if (LOG_CMDFIFO) vd->device->logerror(" PACKET TYPE 1: count=%d inc=%d reg=%04X\n", count, inc, target);
	1699	if (LOG_CMDFIFO) v->device->logerror(" PACKET TYPE 1: count=%d inc=%d reg=%04X\n", count, inc, target);
1638	1700
1639		if (vd->~~vd_~~type >= TYPE_VOODOO_BANSHEE && (target & 0x800))
	1701	if (v->type >= TYPE_VOODOO_BANSHEE && (target & 0x800))
1640	1702	{
1641	1703	// Banshee/Voodoo3 2D register writes
1642	1704
1643	1705	/* loop over all registers and write them one at a time */
1644	1706	for (i = 0; i < count; i++, target += inc)
1645	1707	{
1646		cycles += banshee_2d_w(vd, target & 0xff, *src);
	1708	cycles += banshee_2d_w(v, target & 0xff, *src);
1647	1709	//logerror(" 2d reg: %03x = %08X\n", target & 0x7ff, *src);
1648	1710	src++;
1649	1711	}
r253151	r253152
1652	1714	{
1653	1715	/* loop over all registers and write them one at a time */
1654	1716	for (i = 0; i < count; i++, target += inc)
1655		cycles += register_w(vd, target, *src++);
	1717	cycles += register_w(v, target, *src++);
1656	1718	}
1657	1719	break;
1658	1720
r253151	r253152
1665	1727	1 31:0 = Data word
1666	1728	*/
1667	1729	case 2:
1668		if (LOG_CMDFIFO) vd->device->logerror(" PACKET TYPE 2: mask=%X\n", (command >> 3) & 0x1ffffff);
	1730	if (LOG_CMDFIFO) v->device->logerror(" PACKET TYPE 2: mask=%X\n", (command >> 3) & 0x1ffffff);
1669	1731
1670	1732	/* loop over all registers and write them one at a time */
1671	1733	for (i = 3; i <= 31; i++)
1672	1734	if (command & (1 << i))
1673		cycles += register_w(vd, banshee2D_clip0Min + (i - 3), *src++);
	1735	cycles += register_w(v, banshee2D_clip0Min + (i - 3), *src++);
1674	1736	break;
1675	1737
1676	1738	/*
r253151	r253152
1702	1764	count = (command >> 6) & 15;
1703	1765	code = (command >> 3) & 7;
1704	1766
1705		if (LOG_CMDFIFO) vd->device->logerror(" PACKET TYPE 3: count=%d code=%d mask=%03X smode=%02X pc=%d\n", count, code, (command >> 10) & 0xfff, (command >> 22) & 0x3f, (command >> 28) & 1);
	1767	if (LOG_CMDFIFO) v->device->logerror(" PACKET TYPE 3: count=%d code=%d mask=%03X smode=%02X pc=%d\n", count, code, (command >> 10) & 0xfff, (command >> 22) & 0x3f, (command >> 28) & 1);
1706	1768
1707	1769	/* copy relevant bits into the setup mode register */
1708		vd->reg[sSetupMode].u = ((command >> 10) & 0xff) \| ((command >> 6) & 0xf0000);
	1770	v->reg[sSetupMode].u = ((command >> 10) & 0xff) \| ((command >> 6) & 0xf0000);
1709	1771
1710	1772	/* loop over triangles */
1711	1773	for (i = 0; i < count; i++)
r253151	r253152
1772	1834	/* for a series of individual triangles, initialize all the verts */
1773	1835	if ((code == 1 && i == 0) \|\| (code == 0 && i % 3 == 0))
1774	1836	{
1775		vd->fbi.sverts = 1;
1776		vd->fbi.svert[0] = vd->fbi.svert[1] = vd->fbi.svert[2] = svert;
	1837	v->fbi.sverts = 1;
	1838	v->fbi.svert[0] = v->fbi.svert[1] = v->fbi.svert[2] = svert;
1777	1839	}
1778	1840
1779	1841	/* otherwise, add this to the list */
r253151	r253152
1781	1843	{
1782	1844	/* for strip mode, shuffle vertex 1 down to 0 */
1783	1845	if (!(command & (1 << 22)))
1784		vd->fbi.svert[0] = vd->fbi.svert[1];
	1846	v->fbi.svert[0] = v->fbi.svert[1];
1785	1847
1786	1848	/* copy 2 down to 1 and add our new one regardless */
1787		vd->fbi.svert[1] = vd->fbi.svert[2];
1788		vd->fbi.svert[2] = svert;
	1849	v->fbi.svert[1] = v->fbi.svert[2];
	1850	v->fbi.svert[2] = svert;
1789	1851
1790	1852	/* if we have enough, draw */
1791		if (++vd->fbi.sverts >= 3)
1792		cycles += setup_and_draw_triangle(vd);
	1853	if (++v->fbi.sverts >= 3)
	1854	cycles += setup_and_draw_triangle(v);
1793	1855	}
1794	1856	}
1795	1857
r253151	r253152
1812	1874	/* extract parameters */
1813	1875	target = (command >> 3) & 0xfff;
1814	1876
1815		if (LOG_CMDFIFO) vd->device->logerror(" PACKET TYPE 4: mask=%X reg=%04X pad=%d\n", (command >> 15) & 0x3fff, target, command >> 29);
	1877	if (LOG_CMDFIFO) v->device->logerror(" PACKET TYPE 4: mask=%X reg=%04X pad=%d\n", (command >> 15) & 0x3fff, target, command >> 29);
1816	1878
1817		if (vd->~~vd_~~type >= TYPE_VOODOO_BANSHEE && (target & 0x800))
	1879	if (v->type >= TYPE_VOODOO_BANSHEE && (target & 0x800))
1818	1880	{
1819	1881	// Banshee/Voodoo3 2D register writes
1820	1882
r253151	r253152
1824	1886	{
1825	1887	if (command & (1 << i))
1826	1888	{
1827		cycles += banshee_2d_w(vd, target + (i - 15), *src);
	1889	cycles += banshee_2d_w(v, target + (i - 15), *src);
1828	1890	//logerror(" 2d reg: %03x = %08X\n", target & 0x7ff, *src);
1829	1891	src++;
1830	1892	}
r253151	r253152
1835	1897	/* loop over all registers and write them one at a time */
1836	1898	for (i = 15; i <= 28; i++)
1837	1899	if (command & (1 << i))
1838		cycles += register_w(vd, target + (i - 15), *src++);
	1900	cycles += register_w(v, target + (i - 15), *src++);
1839	1901	}
1840	1902
1841	1903	/* account for the extra dummy words */
r253151	r253152
1866	1928	{
1867	1929	case 0: // Linear FB
1868	1930	{
1869		if (LOG_CMDFIFO) vd->device->logerror(" PACKET TYPE 5: FB count=%d dest=%08X bd2=%X bdN=%X\n", count, target, (command >> 26) & 15, (command >> 22) & 15);
	1931	if (LOG_CMDFIFO) v->device->logerror(" PACKET TYPE 5: FB count=%d dest=%08X bd2=%X bdN=%X\n", count, target, (command >> 26) & 15, (command >> 22) & 15);
1870	1932
1871	1933	UINT32 addr = target * 4;
1872	1934	for (i=0; i < count; i++)
1873	1935	{
1874	1936	UINT32 data = *src++;
1875	1937
1876		vd->fbi.ram[BYTE_XOR_LE(addr + 0)] = (UINT8)(data);
1877		vd->fbi.ram[BYTE_XOR_LE(addr + 1)] = (UINT8)(data >> 8);
1878		vd->fbi.ram[BYTE_XOR_LE(addr + 2)] = (UINT8)(data >> 16);
1879		vd->fbi.ram[BYTE_XOR_LE(addr + 3)] = (UINT8)(data >> 24);
	1938	v->fbi.ram[BYTE_XOR_LE(addr + 0)] = (UINT8)(data);
	1939	v->fbi.ram[BYTE_XOR_LE(addr + 1)] = (UINT8)(data >> 8);
	1940	v->fbi.ram[BYTE_XOR_LE(addr + 2)] = (UINT8)(data >> 16);
	1941	v->fbi.ram[BYTE_XOR_LE(addr + 3)] = (UINT8)(data >> 24);
1880	1942
1881	1943	addr += 4;
1882	1944	}
r253151	r253152
1884	1946	}
1885	1947	case 2: // 3D LFB
1886	1948	{
1887		if (LOG_CMDFIFO) vd->device->logerror(" PACKET TYPE 5: 3D LFB count=%d dest=%08X bd2=%X bdN=%X\n", count, target, (command >> 26) & 15, (command >> 22) & 15);
	1949	if (LOG_CMDFIFO) v->device->logerror(" PACKET TYPE 5: 3D LFB count=%d dest=%08X bd2=%X bdN=%X\n", count, target, (command >> 26) & 15, (command >> 22) & 15);
1888	1950
1889	1951	/* loop over words */
1890	1952	for (i = 0; i < count; i++)
1891		cycles += lfb_w(vd, target++, *src++, 0xffffffff);
	1953	cycles += lfb_w(v, target++, *src++, 0xffffffff);
1892	1954
1893	1955	break;
1894	1956	}
r253151	r253152
1909	1971
1910	1972	case 3: // Texture Port
1911	1973	{
1912		if (LOG_CMDFIFO) vd->device->logerror(" PACKET TYPE 5: textureRAM count=%d dest=%08X bd2=%X bdN=%X\n", count, target, (command >> 26) & 15, (command >> 22) & 15);
	1974	if (LOG_CMDFIFO) v->device->logerror(" PACKET TYPE 5: textureRAM count=%d dest=%08X bd2=%X bdN=%X\n", count, target, (command >> 26) & 15, (command >> 22) & 15);
1913	1975
1914	1976	/* loop over words */
1915	1977	for (i = 0; i < count; i++)
1916		cycles += texture_w(vd, target++, *src++);
	1978	cycles += texture_w(v, target++, *src++);
1917	1979
1918	1980	break;
1919	1981	}
r253151	r253152
1939	2001	*
1940	2002	*************************************/
1941	2003
1942		INT32 ~~voodoo_devi~~c~~e::c~~mdfifo_execute_if_ready(voodoo_device* vd, cmdfifo_info *f)
	2004	static INT32 cmdfifo_execute_if_ready(voodoo_state v, cmdfifo_info f)
1943	2005	{
1944	2006	int needed_depth;
1945	2007	int cycles;
r253151	r253152
1949	2011	return -1;
1950	2012
1951	2013	/* see if we have enough for the current command */
1952		needed_depth = cmdfifo_compute_expected_depth(vd, f);
	2014	needed_depth = cmdfifo_compute_expected_depth(v, f);
1953	2015	if (f->depth < needed_depth)
1954	2016	return -1;
1955	2017
1956	2018	/* execute */
1957		cycles = cmdfifo_execute(vd, f);
	2019	cycles = cmdfifo_execute(v, f);
1958	2020	f->depth -= needed_depth;
1959	2021	return cycles;
1960	2022	}
r253151	r253152
1967	2029	*
1968	2030	*************************************/
1969	2031
1970		void vo~~odoo_dev~~ic~~e::c~~mdfifo_w(voodoo_de~~vice~~ vd, cmdfifo_info f, offs_t offset, UINT32 data)
	2032	static void cmdfifo_w(voodoo_state v, cmdfifo_info f, offs_t offset, UINT32 data)
1971	2033	{
1972	2034	UINT32 addr = f->base + offset * 4;
1973		UINT32 fifobase = (UINT32 )vd->fbi.ram;
	2035	UINT32 fifobase = (UINT32 )v->fbi.ram;
1974	2036
1975		if (LOG_CMDFIFO_VERBOSE) vd->device->logerror("CMDFIFO_w(%04X) = %08X\n", offset, data);
	2037	if (LOG_CMDFIFO_VERBOSE) v->device->logerror("CMDFIFO_w(%04X) = %08X\n", offset, data);
1976	2038
1977	2039	/* write the data */
1978	2040	if (addr < f->end)
r253151	r253152
1992	2054	else if (addr < f->amin)
1993	2055	{
1994	2056	if (f->holes != 0)
1995		vd->device->logerror("Unexpected CMDFIFO: AMin=%08X AMax=%08X Holes=%d WroteTo:%08X\n",
	2057	v->device->logerror("Unexpected CMDFIFO: AMin=%08X AMax=%08X Holes=%d WroteTo:%08X\n",
1996	2058	f->amin, f->amax, f->holes, addr);
1997	2059	//f->amin = f->amax = addr;
1998	2060	f->holes += (addr - f->base) / 4;
r253151	r253152
2022	2084	}
2023	2085
2024	2086	/* execute if we can */
2025		if (!vd->pci.op_pending)
	2087	if (!v->pci.op_pending)
2026	2088	{
2027		INT32 cycles = cmdfifo_execute_if_ready(vd, f);
	2089	INT32 cycles = cmdfifo_execute_if_ready(v, f);
2028	2090	if (cycles > 0)
2029	2091	{
2030		vd->pci.op_pending = TRUE;
2031		vd->pci.op_end_time = vd->device->machine().time() + attotime(0, (attoseconds_t)cycles * vd->attoseconds_per_cycle);
	2092	v->pci.op_pending = TRUE;
	2093	v->pci.op_end_time = v->device->machine().time() + attotime(0, (attoseconds_t)cycles * v->attoseconds_per_cycle);
2032	2094
2033		if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:direct write start at %d.%08X%08X end at %d.%08X%08X\n", vd->index,
2034		vd->device->machine().time().seconds(), (UINT32)(vd->device->machine().time().attoseconds() >> 32), (UINT32)vd->device->machine().time().attoseconds(),
2035		vd->pci.op_end_time.seconds(), (UINT32)(vd->pci.op_end_time.attoseconds() >> 32), (UINT32)vd->pci.op_end_time.attoseconds());
	2095	if (LOG_FIFO_VERBOSE) v->device->logerror("VOODOO.%d.FIFO:direct write start at %d.%08X%08X end at %d.%08X%08X\n", v->index,
	2096	v->device->machine().time().seconds(), (UINT32)(v->device->machine().time().attoseconds() >> 32), (UINT32)v->device->machine().time().attoseconds(),
	2097	v->pci.op_end_time.seconds(), (UINT32)(v->pci.op_end_time.attoseconds() >> 32), (UINT32)v->pci.op_end_time.attoseconds());
2036	2098	}
2037	2099	}
2038	2100	}
r253151	r253152
2046	2108	*
2047	2109	*************************************/
2048	2110
2049		TIMER_CALLBACK~~_MEMBER~~( ~~voodoo_device::~~stall_cpu_callback )
	2111	static TIMER_CALLBACK( stall_cpu_callback )
2050	2112	{
2051		check_stalled_cpu(~~thi~~s, machine().time());
	2113	check_stalled_cpu((voodoo_state *)ptr, machine.time());
2052	2114	}
2053	2115
2054	2116
2055		void vo~~odoo_dev~~ic~~e::c~~heck_stalled_cpu(voodoo_device* vd, attotime current_time)
	2117	static void check_stalled_cpu(voodoo_state *v, attotime current_time)
2056	2118	{
2057	2119	int resume = FALSE;
2058	2120
2059	2121	/* flush anything we can */
2060		if (vd->pci.op_pending)
2061		flush_fifos(vd, current_time);
	2122	if (v->pci.op_pending)
	2123	flush_fifos(v, current_time);
2062	2124
2063	2125	/* if we're just stalled until the LWM is passed, see if we're ok now */
2064		if (vd->pci.stall_state == STALLED_UNTIL_FIFO_LWM)
	2126	if (v->pci.stall_state == STALLED_UNTIL_FIFO_LWM)
2065	2127	{
2066	2128	/* if there's room in the memory FIFO now, we can proceed */
2067		if (FBIINIT0_ENABLE_MEMORY_FIFO(vd->reg[fbiInit0].u))
	2129	if (FBIINIT0_ENABLE_MEMORY_FIFO(v->reg[fbiInit0].u))
2068	2130	{
2069		if (fifo_items(&vd->fbi.fifo) < 2 * 32 * FBIINIT0_MEMORY_FIFO_HWM(vd->reg[fbiInit0].u))
	2131	if (fifo_items(&v->fbi.fifo) < 2 * 32 * FBIINIT0_MEMORY_FIFO_HWM(v->reg[fbiInit0].u))
2070	2132	resume = TRUE;
2071	2133	}
2072		else if (fifo_space(&vd->pci.fifo) > 2 * FBIINIT0_PCI_FIFO_LWM(vd->reg[fbiInit0].u))
	2134	else if (fifo_space(&v->pci.fifo) > 2 * FBIINIT0_PCI_FIFO_LWM(v->reg[fbiInit0].u))
2073	2135	resume = TRUE;
2074	2136	}
2075	2137
2076	2138	/* if we're stalled until the FIFOs are empty, check now */
2077		else if (vd->pci.stall_state == STALLED_UNTIL_FIFO_EMPTY)
	2139	else if (v->pci.stall_state == STALLED_UNTIL_FIFO_EMPTY)
2078	2140	{
2079		if (FBIINIT0_ENABLE_MEMORY_FIFO(vd->reg[fbiInit0].u))
	2141	if (FBIINIT0_ENABLE_MEMORY_FIFO(v->reg[fbiInit0].u))
2080	2142	{
2081		if (fifo_empty(&vd->fbi.fifo) && fifo_empty(&vd->pci.fifo))
	2143	if (fifo_empty(&v->fbi.fifo) && fifo_empty(&v->pci.fifo))
2082	2144	resume = TRUE;
2083	2145	}
2084		else if (fifo_empty(&vd->pci.fifo))
	2146	else if (fifo_empty(&v->pci.fifo))
2085	2147	resume = TRUE;
2086	2148	}
2087	2149
2088	2150	/* resume if necessary */
2089		if (resume \|\| !vd->pci.op_pending)
	2151	if (resume \|\| !v->pci.op_pending)
2090	2152	{
2091		if (LOG_FIFO) vd->device->logerror("VOODOO.%d.FIFO:Stall condition cleared; resuming\n", vd->index);
2092		vd->pci.stall_state = NOT_STALLED;
	2153	if (LOG_FIFO) v->device->logerror("VOODOO.%d.FIFO:Stall condition cleared; resuming\n", v->index);
	2154	v->pci.stall_state = NOT_STALLED;
2093	2155
2094	2156	/* either call the callback, or trigger the trigger */
2095		if (!vd->device->m_stall.isnull())
2096		vd->device->m_stall(FALSE);
	2157	if (!v->device->m_stall.isnull())
	2158	v->device->m_stall(FALSE);
2097	2159	else
2098		vd->device->machine().scheduler().trigger(vd->trigger);
	2160	v->device->machine().scheduler().trigger(v->trigger);
2099	2161	}
2100	2162
2101	2163	/* if not, set a timer for the next one */
2102	2164	else
2103	2165	{
2104		vd->pci.continue_timer->adjust(vd->pci.op_end_time - current_time);
	2166	v->pci.continue_timer->adjust(v->pci.op_end_time - current_time);
2105	2167	}
2106	2168	}
2107	2169
2108	2170
2109		void vo~~odoo_dev~~i~~ce::~~stall_cpu(voodoo_de~~vice~~ *vd, int state, attotime current_time)
	2171	static void stall_cpu(voodoo_state *v, int state, attotime current_time)
2110	2172	{
2111	2173	/* sanity check */
2112		if (!vd->pci.op_pending) fatalerror("FIFOs not empty, no op pending!\n");
	2174	if (!v->pci.op_pending) fatalerror("FIFOs not empty, no op pending!\n");
2113	2175
2114	2176	/* set the state and update statistics */
2115		vd->pci.stall_state = state;
2116		vd->stats.stalls++;
	2177	v->pci.stall_state = state;
	2178	v->stats.stalls++;
2117	2179
2118	2180	/* either call the callback, or spin the CPU */
2119		if (!vd->device->m_stall.isnull())
2120		vd->device->m_stall(TRUE);
	2181	if (!v->device->m_stall.isnull())
	2182	v->device->m_stall(TRUE);
2121	2183	else
2122		vd->cpu->execute().spin_until_trigger(vd->trigger);
	2184	v->cpu->execute().spin_until_trigger(v->trigger);
2123	2185
2124	2186	/* set a timer to clear the stall */
2125		vd->pci.continue_timer->adjust(vd->pci.op_end_time - current_time);
	2187	v->pci.continue_timer->adjust(v->pci.op_end_time - current_time);
2126	2188	}
2127	2189
2128	2190
r253151	r253152
2133	2195	*
2134	2196	*************************************/
2135	2197
2136		INT32 ~~voodoo_device::~~register_w(voodoo_de~~vice~~ *vd, offs_t offset, UINT32 data)
	2198	static INT32 register_w(voodoo_state *v, offs_t offset, UINT32 data)
2137	2199	{
2138	2200	UINT32 origdata = data;
2139	2201	INT32 cycles = 0;
r253151	r253152
2142	2204	UINT8 chips;
2143	2205
2144	2206	/* statistics */
2145		vd->stats.reg_writes++;
	2207	v->stats.reg_writes++;
2146	2208
2147	2209	/* determine which chips we are addressing */
2148	2210	chips = (offset >> 8) & 0xf;
2149	2211	if (chips == 0)
2150	2212	chips = 0xf;
2151		chips &= vd->chipmask;
	2213	chips &= v->chipmask;
2152	2214
2153	2215	/* the first 64 registers can be aliased differently */
2154		if ((offset & 0x800c0) == 0x80000 && vd->alt_regmap)
	2216	if ((offset & 0x800c0) == 0x80000 && v->alt_regmap)
2155	2217	regnum = register_alias_map[offset & 0x3f];
2156	2218	else
2157	2219	regnum = offset & 0xff;
2158	2220
2159	2221	/* first make sure this register is readable */
2160		if (!(vd->regaccess[regnum] & REGISTER_WRITE))
	2222	if (!(v->regaccess[regnum] & REGISTER_WRITE))
2161	2223	{
2162		vd->device->logerror("VOODOO.%d.ERROR:Invalid attempt to write %s\n", vd->index, vd->regnames[regnum]);
	2224	v->device->logerror("VOODOO.%d.ERROR:Invalid attempt to write %s\n", v->index, v->regnames[regnum]);
2163	2225	return 0;
2164	2226	}
2165	2227
r253151	r253152
2170	2232	case fvertexAx:
2171	2233	data = float_to_int32(data, 4);
2172	2234	case vertexAx:
2173		if (chips & 1) vd->fbi.ax = (INT16)data;
	2235	if (chips & 1) v->fbi.ax = (INT16)data;
2174	2236	break;
2175	2237
2176	2238	case fvertexAy:
2177	2239	data = float_to_int32(data, 4);
2178	2240	case vertexAy:
2179		if (chips & 1) vd->fbi.ay = (INT16)data;
	2241	if (chips & 1) v->fbi.ay = (INT16)data;
2180	2242	break;
2181	2243
2182	2244	case fvertexBx:
2183	2245	data = float_to_int32(data, 4);
2184	2246	case vertexBx:
2185		if (chips & 1) vd->fbi.bx = (INT16)data;
	2247	if (chips & 1) v->fbi.bx = (INT16)data;
2186	2248	break;
2187	2249
2188	2250	case fvertexBy:
2189	2251	data = float_to_int32(data, 4);
2190	2252	case vertexBy:
2191		if (chips & 1) vd->fbi.by = (INT16)data;
	2253	if (chips & 1) v->fbi.by = (INT16)data;
2192	2254	break;
2193	2255
2194	2256	case fvertexCx:
2195	2257	data = float_to_int32(data, 4);
2196	2258	case vertexCx:
2197		if (chips & 1) vd->fbi.cx = (INT16)data;
	2259	if (chips & 1) v->fbi.cx = (INT16)data;
2198	2260	break;
2199	2261
2200	2262	case fvertexCy:
2201	2263	data = float_to_int32(data, 4);
2202	2264	case vertexCy:
2203		if (chips & 1) vd->fbi.cy = (INT16)data;
	2265	if (chips & 1) v->fbi.cy = (INT16)data;
2204	2266	break;
2205	2267
2206	2268	/* RGB data is 12.12 formatted fixed point */
2207	2269	case fstartR:
2208	2270	data = float_to_int32(data, 12);
2209	2271	case startR:
2210		if (chips & 1) vd->fbi.startr = (INT32)(data << 8) >> 8;
	2272	if (chips & 1) v->fbi.startr = (INT32)(data << 8) >> 8;
2211	2273	break;
2212	2274
2213	2275	case fstartG:
2214	2276	data = float_to_int32(data, 12);
2215	2277	case startG:
2216		if (chips & 1) vd->fbi.startg = (INT32)(data << 8) >> 8;
	2278	if (chips & 1) v->fbi.startg = (INT32)(data << 8) >> 8;
2217	2279	break;
2218	2280
2219	2281	case fstartB:
2220	2282	data = float_to_int32(data, 12);
2221	2283	case startB:
2222		if (chips & 1) vd->fbi.startb = (INT32)(data << 8) >> 8;
	2284	if (chips & 1) v->fbi.startb = (INT32)(data << 8) >> 8;
2223	2285	break;
2224	2286
2225	2287	case fstartA:
2226	2288	data = float_to_int32(data, 12);
2227	2289	case startA:
2228		if (chips & 1) vd->fbi.starta = (INT32)(data << 8) >> 8;
	2290	if (chips & 1) v->fbi.starta = (INT32)(data << 8) >> 8;
2229	2291	break;
2230	2292
2231	2293	case fdRdX:
2232	2294	data = float_to_int32(data, 12);
2233	2295	case dRdX:
2234		if (chips & 1) vd->fbi.drdx = (INT32)(data << 8) >> 8;
	2296	if (chips & 1) v->fbi.drdx = (INT32)(data << 8) >> 8;
2235	2297	break;
2236	2298
2237	2299	case fdGdX:
2238	2300	data = float_to_int32(data, 12);
2239	2301	case dGdX:
2240		if (chips & 1) vd->fbi.dgdx = (INT32)(data << 8) >> 8;
	2302	if (chips & 1) v->fbi.dgdx = (INT32)(data << 8) >> 8;
2241	2303	break;
2242	2304
2243	2305	case fdBdX:
2244	2306	data = float_to_int32(data, 12);
2245	2307	case dBdX:
2246		if (chips & 1) vd->fbi.dbdx = (INT32)(data << 8) >> 8;
	2308	if (chips & 1) v->fbi.dbdx = (INT32)(data << 8) >> 8;
2247	2309	break;
2248	2310
2249	2311	case fdAdX:
2250	2312	data = float_to_int32(data, 12);
2251	2313	case dAdX:
2252		if (chips & 1) vd->fbi.dadx = (INT32)(data << 8) >> 8;
	2314	if (chips & 1) v->fbi.dadx = (INT32)(data << 8) >> 8;
2253	2315	break;
2254	2316
2255	2317	case fdRdY:
2256	2318	data = float_to_int32(data, 12);
2257	2319	case dRdY:
2258		if (chips & 1) vd->fbi.drdy = (INT32)(data << 8) >> 8;
	2320	if (chips & 1) v->fbi.drdy = (INT32)(data << 8) >> 8;
2259	2321	break;
2260	2322
2261	2323	case fdGdY:
2262	2324	data = float_to_int32(data, 12);
2263	2325	case dGdY:
2264		if (chips & 1) vd->fbi.dgdy = (INT32)(data << 8) >> 8;
	2326	if (chips & 1) v->fbi.dgdy = (INT32)(data << 8) >> 8;
2265	2327	break;
2266	2328
2267	2329	case fdBdY:
2268	2330	data = float_to_int32(data, 12);
2269	2331	case dBdY:
2270		if (chips & 1) vd->fbi.dbdy = (INT32)(data << 8) >> 8;
	2332	if (chips & 1) v->fbi.dbdy = (INT32)(data << 8) >> 8;
2271	2333	break;
2272	2334
2273	2335	case fdAdY:
2274	2336	data = float_to_int32(data, 12);
2275	2337	case dAdY:
2276		if (chips & 1) vd->fbi.dady = (INT32)(data << 8) >> 8;
	2338	if (chips & 1) v->fbi.dady = (INT32)(data << 8) >> 8;
2277	2339	break;
2278	2340
2279	2341	/* Z data is 20.12 formatted fixed point */
2280	2342	case fstartZ:
2281	2343	data = float_to_int32(data, 12);
2282	2344	case startZ:
2283		if (chips & 1) vd->fbi.startz = (INT32)data;
	2345	if (chips & 1) v->fbi.startz = (INT32)data;
2284	2346	break;
2285	2347
2286	2348	case fdZdX:
2287	2349	data = float_to_int32(data, 12);
2288	2350	case dZdX:
2289		if (chips & 1) vd->fbi.dzdx = (INT32)data;
	2351	if (chips & 1) v->fbi.dzdx = (INT32)data;
2290	2352	break;
2291	2353
2292	2354	case fdZdY:
2293	2355	data = float_to_int32(data, 12);
2294	2356	case dZdY:
2295		if (chips & 1) vd->fbi.dzdy = (INT32)data;
	2357	if (chips & 1) v->fbi.dzdy = (INT32)data;
2296	2358	break;
2297	2359
2298	2360	/* S,T data is 14.18 formatted fixed point, converted to 16.32 internally */
2299	2361	case fstartS:
2300	2362	data64 = float_to_int64(data, 32);
2301		if (chips & 2) vd->tmu[0].starts = data64;
2302		if (chips & 4) vd->tmu[1].starts = data64;
	2363	if (chips & 2) v->tmu[0].starts = data64;
	2364	if (chips & 4) v->tmu[1].starts = data64;
2303	2365	break;
2304	2366	case startS:
2305		if (chips & 2) vd->tmu[0].starts = (INT64)(INT32)data << 14;
2306		if (chips & 4) vd->tmu[1].starts = (INT64)(INT32)data << 14;
	2367	if (chips & 2) v->tmu[0].starts = (INT64)(INT32)data << 14;
	2368	if (chips & 4) v->tmu[1].starts = (INT64)(INT32)data << 14;
2307	2369	break;
2308	2370
2309	2371	case fstartT:
2310	2372	data64 = float_to_int64(data, 32);
2311		if (chips & 2) vd->tmu[0].startt = data64;
2312		if (chips & 4) vd->tmu[1].startt = data64;
	2373	if (chips & 2) v->tmu[0].startt = data64;
	2374	if (chips & 4) v->tmu[1].startt = data64;
2313	2375	break;
2314	2376	case startT:
2315		if (chips & 2) vd->tmu[0].startt = (INT64)(INT32)data << 14;
2316		if (chips & 4) vd->tmu[1].startt = (INT64)(INT32)data << 14;
	2377	if (chips & 2) v->tmu[0].startt = (INT64)(INT32)data << 14;
	2378	if (chips & 4) v->tmu[1].startt = (INT64)(INT32)data << 14;
2317	2379	break;
2318	2380
2319	2381	case fdSdX:
2320	2382	data64 = float_to_int64(data, 32);
2321		if (chips & 2) vd->tmu[0].dsdx = data64;
2322		if (chips & 4) vd->tmu[1].dsdx = data64;
	2383	if (chips & 2) v->tmu[0].dsdx = data64;
	2384	if (chips & 4) v->tmu[1].dsdx = data64;
2323	2385	break;
2324	2386	case dSdX:
2325		if (chips & 2) vd->tmu[0].dsdx = (INT64)(INT32)data << 14;
2326		if (chips & 4) vd->tmu[1].dsdx = (INT64)(INT32)data << 14;
	2387	if (chips & 2) v->tmu[0].dsdx = (INT64)(INT32)data << 14;
	2388	if (chips & 4) v->tmu[1].dsdx = (INT64)(INT32)data << 14;
2327	2389	break;
2328	2390
2329	2391	case fdTdX:
2330	2392	data64 = float_to_int64(data, 32);
2331		if (chips & 2) vd->tmu[0].dtdx = data64;
2332		if (chips & 4) vd->tmu[1].dtdx = data64;
	2393	if (chips & 2) v->tmu[0].dtdx = data64;
	2394	if (chips & 4) v->tmu[1].dtdx = data64;
2333	2395	break;
2334	2396	case dTdX:
2335		if (chips & 2) vd->tmu[0].dtdx = (INT64)(INT32)data << 14;
2336		if (chips & 4) vd->tmu[1].dtdx = (INT64)(INT32)data << 14;
	2397	if (chips & 2) v->tmu[0].dtdx = (INT64)(INT32)data << 14;
	2398	if (chips & 4) v->tmu[1].dtdx = (INT64)(INT32)data << 14;
2337	2399	break;
2338	2400
2339	2401	case fdSdY:
2340	2402	data64 = float_to_int64(data, 32);
2341		if (chips & 2) vd->tmu[0].dsdy = data64;
2342		if (chips & 4) vd->tmu[1].dsdy = data64;
	2403	if (chips & 2) v->tmu[0].dsdy = data64;
	2404	if (chips & 4) v->tmu[1].dsdy = data64;
2343	2405	break;
2344	2406	case dSdY:
2345		if (chips & 2) vd->tmu[0].dsdy = (INT64)(INT32)data << 14;
2346		if (chips & 4) vd->tmu[1].dsdy = (INT64)(INT32)data << 14;
	2407	if (chips & 2) v->tmu[0].dsdy = (INT64)(INT32)data << 14;
	2408	if (chips & 4) v->tmu[1].dsdy = (INT64)(INT32)data << 14;
2347	2409	break;
2348	2410
2349	2411	case fdTdY:
2350	2412	data64 = float_to_int64(data, 32);
2351		if (chips & 2) vd->tmu[0].dtdy = data64;
2352		if (chips & 4) vd->tmu[1].dtdy = data64;
	2413	if (chips & 2) v->tmu[0].dtdy = data64;
	2414	if (chips & 4) v->tmu[1].dtdy = data64;
2353	2415	break;
2354	2416	case dTdY:
2355		if (chips & 2) vd->tmu[0].dtdy = (INT64)(INT32)data << 14;
2356		if (chips & 4) vd->tmu[1].dtdy = (INT64)(INT32)data << 14;
	2417	if (chips & 2) v->tmu[0].dtdy = (INT64)(INT32)data << 14;
	2418	if (chips & 4) v->tmu[1].dtdy = (INT64)(INT32)data << 14;
2357	2419	break;
2358	2420
2359	2421	/* W data is 2.30 formatted fixed point, converted to 16.32 internally */
2360	2422	case fstartW:
2361	2423	data64 = float_to_int64(data, 32);
2362		if (chips & 1) vd->fbi.startw = data64;
2363		if (chips & 2) vd->tmu[0].startw = data64;
2364		if (chips & 4) vd->tmu[1].startw = data64;
	2424	if (chips & 1) v->fbi.startw = data64;
	2425	if (chips & 2) v->tmu[0].startw = data64;
	2426	if (chips & 4) v->tmu[1].startw = data64;
2365	2427	break;
2366	2428	case startW:
2367		if (chips & 1) vd->fbi.startw = (INT64)(INT32)data << 2;
2368		if (chips & 2) vd->tmu[0].startw = (INT64)(INT32)data << 2;
2369		if (chips & 4) vd->tmu[1].startw = (INT64)(INT32)data << 2;
	2429	if (chips & 1) v->fbi.startw = (INT64)(INT32)data << 2;
	2430	if (chips & 2) v->tmu[0].startw = (INT64)(INT32)data << 2;
	2431	if (chips & 4) v->tmu[1].startw = (INT64)(INT32)data << 2;
2370	2432	break;
2371	2433
2372	2434	case fdWdX:
2373	2435	data64 = float_to_int64(data, 32);
2374		if (chips & 1) vd->fbi.dwdx = data64;
2375		if (chips & 2) vd->tmu[0].dwdx = data64;
2376		if (chips & 4) vd->tmu[1].dwdx = data64;
	2436	if (chips & 1) v->fbi.dwdx = data64;
	2437	if (chips & 2) v->tmu[0].dwdx = data64;
	2438	if (chips & 4) v->tmu[1].dwdx = data64;
2377	2439	break;
2378	2440	case dWdX:
2379		if (chips & 1) vd->fbi.dwdx = (INT64)(INT32)data << 2;
2380		if (chips & 2) vd->tmu[0].dwdx = (INT64)(INT32)data << 2;
2381		if (chips & 4) vd->tmu[1].dwdx = (INT64)(INT32)data << 2;
	2441	if (chips & 1) v->fbi.dwdx = (INT64)(INT32)data << 2;
	2442	if (chips & 2) v->tmu[0].dwdx = (INT64)(INT32)data << 2;
	2443	if (chips & 4) v->tmu[1].dwdx = (INT64)(INT32)data << 2;
2382	2444	break;
2383	2445
2384	2446	case fdWdY:
2385	2447	data64 = float_to_int64(data, 32);
2386		if (chips & 1) vd->fbi.dwdy = data64;
2387		if (chips & 2) vd->tmu[0].dwdy = data64;
2388		if (chips & 4) vd->tmu[1].dwdy = data64;
	2448	if (chips & 1) v->fbi.dwdy = data64;
	2449	if (chips & 2) v->tmu[0].dwdy = data64;
	2450	if (chips & 4) v->tmu[1].dwdy = data64;
2389	2451	break;
2390	2452	case dWdY:
2391		if (chips & 1) vd->fbi.dwdy = (INT64)(INT32)data << 2;
2392		if (chips & 2) vd->tmu[0].dwdy = (INT64)(INT32)data << 2;
2393		if (chips & 4) vd->tmu[1].dwdy = (INT64)(INT32)data << 2;
	2453	if (chips & 1) v->fbi.dwdy = (INT64)(INT32)data << 2;
	2454	if (chips & 2) v->tmu[0].dwdy = (INT64)(INT32)data << 2;
	2455	if (chips & 4) v->tmu[1].dwdy = (INT64)(INT32)data << 2;
2394	2456	break;
2395	2457
2396	2458	/* setup bits */
r253151	r253152
2398	2460	if (chips & 1)
2399	2461	{
2400	2462	rgb_t rgbdata(data);
2401		vd->reg[sAlpha].f = rgbdata.a();
2402		vd->reg[sRed].f = rgbdata.r();
2403		vd->reg[sGreen].f = rgbdata.g();
2404		vd->reg[sBlue].f = rgbdata.b();
	2463	v->reg[sAlpha].f = rgbdata.a();
	2464	v->reg[sRed].f = rgbdata.r();
	2465	v->reg[sGreen].f = rgbdata.g();
	2466	v->reg[sBlue].f = rgbdata.b();
2405	2467	}
2406	2468	break;
2407	2469
2408	2470	/* mask off invalid bits for different cards */
2409	2471	case fbzColorPath:
2410		poly_wait(vd->poly, vd->regnames[regnum]);
2411		if (vd->vd_type < TYPE_VOODOO_2)
	2472	poly_wait(v->poly, v->regnames[regnum]);
	2473	if (v->type < TYPE_VOODOO_2)
2412	2474	data &= 0x0fffffff;
2413		if (chips & 1) vd->reg[fbzColorPath].u = data;
	2475	if (chips & 1) v->reg[fbzColorPath].u = data;
2414	2476	break;
2415	2477
2416	2478	case fbzMode:
2417		poly_wait(vd->poly, vd->regnames[regnum]);
2418		if (vd->vd_type < TYPE_VOODOO_2)
	2479	poly_wait(v->poly, v->regnames[regnum]);
	2480	if (v->type < TYPE_VOODOO_2)
2419	2481	data &= 0x001fffff;
2420		if (chips & 1) vd->reg[fbzMode].u = data;
	2482	if (chips & 1) v->reg[fbzMode].u = data;
2421	2483	break;
2422	2484
2423	2485	case fogMode:
2424		poly_wait(vd->poly, vd->regnames[regnum]);
2425		if (vd->vd_type < TYPE_VOODOO_2)
	2486	poly_wait(v->poly, v->regnames[regnum]);
	2487	if (v->type < TYPE_VOODOO_2)
2426	2488	data &= 0x0000003f;
2427		if (chips & 1) vd->reg[fogMode].u = data;
	2489	if (chips & 1) v->reg[fogMode].u = data;
2428	2490	break;
2429	2491
2430	2492	/* triangle drawing */
2431	2493	case triangleCMD:
2432		vd->fbi.cheating_allowed = (vd->fbi.ax != 0 \|\| vd->fbi.ay != 0 \|\| vd->fbi.bx > 50 \|\| vd->fbi.by != 0 \|\| vd->fbi.cx != 0 \|\| vd->fbi.cy > 50);
2433		vd->fbi.sign = data;
2434		cycles = triangle(vd);
	2494	v->fbi.cheating_allowed = (v->fbi.ax != 0 \|\| v->fbi.ay != 0 \|\| v->fbi.bx > 50 \|\| v->fbi.by != 0 \|\| v->fbi.cx != 0 \|\| v->fbi.cy > 50);
	2495	v->fbi.sign = data;
	2496	cycles = triangle(v);
2435	2497	break;
2436	2498
2437	2499	case ftriangleCMD:
2438		vd->fbi.cheating_allowed = TRUE;
2439		vd->fbi.sign = data;
2440		cycles = triangle(vd);
	2500	v->fbi.cheating_allowed = TRUE;
	2501	v->fbi.sign = data;
	2502	cycles = triangle(v);
2441	2503	break;
2442	2504
2443	2505	case sBeginTriCMD:
2444		cycles = begin_triangle(vd);
	2506	cycles = begin_triangle(v);
2445	2507	break;
2446	2508
2447	2509	case sDrawTriCMD:
2448		cycles = draw_triangle(vd);
	2510	cycles = draw_triangle(v);
2449	2511	break;
2450	2512
2451	2513	/* other commands */
2452	2514	case nopCMD:
2453		poly_wait(vd->poly, vd->regnames[regnum]);
	2515	poly_wait(v->poly, v->regnames[regnum]);
2454	2516	if (data & 1)
2455		reset_counters(vd);
	2517	reset_counters(v);
2456	2518	if (data & 2)
2457		vd->reg[fbiTrianglesOut].u = 0;
	2519	v->reg[fbiTrianglesOut].u = 0;
2458	2520	break;
2459	2521
2460	2522	case fastfillCMD:
2461		cycles = fastfill(vd);
	2523	cycles = fastfill(v);
2462	2524	break;
2463	2525
2464	2526	case swapbufferCMD:
2465		poly_wait(vd->poly, vd->regnames[regnum]);
2466		cycles = swapbuffer(vd, data);
	2527	poly_wait(v->poly, v->regnames[regnum]);
	2528	cycles = swapbuffer(v, data);
2467	2529	break;
2468	2530
2469	2531	case userIntrCMD:
2470		poly_wait(vd->poly, vd->regnames[regnum]);
	2532	poly_wait(v->poly, v->regnames[regnum]);
2471	2533	//fatalerror("userIntrCMD\n");
2472	2534
2473		vd->reg[intrCtrl].u \|= 0x1800;
2474		vd->reg[intrCtrl].u &= ~0x80000000;
	2535	v->reg[intrCtrl].u \|= 0x1800;
	2536	v->reg[intrCtrl].u &= ~0x80000000;
2475	2537
2476	2538	// TODO: rename vblank_client for less confusion?
2477		if (!vd->device->m_vblank.isnull())
2478		vd->device->m_vblank(TRUE);
	2539	if (!v->device->m_vblank.isnull())
	2540	v->device->m_vblank(TRUE);
2479	2541	break;
2480	2542
2481	2543	/* gamma table access -- Voodoo/Voodoo2 only */
2482	2544	case clutData:
2483		if (vd->~~vd_~~type <= TYPE_VOODOO_2 && (chips & 1))
	2545	if (v->type <= TYPE_VOODOO_2 && (chips & 1))
2484	2546	{
2485		poly_wait(vd->poly, vd->regnames[regnum]);
2486		if (!FBIINIT1_VIDEO_TIMING_RESET(vd->reg[fbiInit1].u))
	2547	poly_wait(v->poly, v->regnames[regnum]);
	2548	if (!FBIINIT1_VIDEO_TIMING_RESET(v->reg[fbiInit1].u))
2487	2549	{
2488	2550	int index = data >> 24;
2489	2551	if (index <= 32)
2490	2552	{
2491		vd->fbi.clut[index] = data;
2492		vd->fbi.clut_dirty = TRUE;
	2553	v->fbi.clut[index] = data;
	2554	v->fbi.clut_dirty = TRUE;
2493	2555	}
2494	2556	}
2495	2557	else
2496		vd->device->logerror("clutData ignored because video timing reset = 1\n");
	2558	v->device->logerror("clutData ignored because video timing reset = 1\n");
2497	2559	}
2498	2560	break;
2499	2561
2500	2562	/* external DAC access -- Voodoo/Voodoo2 only */
2501	2563	case dacData:
2502		if (vd->~~vd_~~type <= TYPE_VOODOO_2 && (chips & 1))
	2564	if (v->type <= TYPE_VOODOO_2 && (chips & 1))
2503	2565	{
2504		poly_wait(vd->poly, vd->regnames[regnum]);
	2566	poly_wait(v->poly, v->regnames[regnum]);
2505	2567	if (!(data & 0x800))
2506		dacdata_w(&vd->dac, (data >> 8) & 7, data & 0xff);
	2568	dacdata_w(&v->dac, (data >> 8) & 7, data & 0xff);
2507	2569	else
2508		dacdata_r(&vd->dac, (data >> 8) & 7);
	2570	dacdata_r(&v->dac, (data >> 8) & 7);
2509	2571	}
2510	2572	break;
2511	2573
r253151	r253152
2514	2576	case vSync:
2515	2577	case backPorch:
2516	2578	case videoDimensions:
2517		if (vd->~~vd_~~type <= TYPE_VOODOO_2 && (chips & 1))
	2579	if (v->type <= TYPE_VOODOO_2 && (chips & 1))
2518	2580	{
2519		poly_wait(vd->poly, vd->regnames[regnum]);
2520		vd->reg[regnum].u = data;
2521		if (vd->reg[hSync].u != 0 && vd->reg[vSync].u != 0 && vd->reg[videoDimensions].u != 0)
	2581	poly_wait(v->poly, v->regnames[regnum]);
	2582	v->reg[regnum].u = data;
	2583	if (v->reg[hSync].u != 0 && v->reg[vSync].u != 0 && v->reg[videoDimensions].u != 0)
2522	2584	{
2523	2585	int hvis, vvis, htotal, vtotal, hbp, vbp;
2524		attoseconds_t refresh = vd->screen->frame_period().attoseconds();
	2586	attoseconds_t refresh = v->screen->frame_period().attoseconds();
2525	2587	attoseconds_t stdperiod, medperiod, vgaperiod;
2526	2588	attoseconds_t stddiff, meddiff, vgadiff;
2527	2589	rectangle visarea;
2528	2590
2529		if (vd->~~vd_~~type == TYPE_VOODOO_2)
	2591	if (v->type == TYPE_VOODOO_2)
2530	2592	{
2531		htotal = ((vd->reg[hSync].u >> 16) & 0x7ff) + 1 + (vd->reg[hSync].u & 0x1ff) + 1;
2532		vtotal = ((vd->reg[vSync].u >> 16) & 0x1fff) + (vd->reg[vSync].u & 0x1fff);
2533		hvis = vd->reg[videoDimensions].u & 0x7ff;
2534		vvis = (vd->reg[videoDimensions].u >> 16) & 0x7ff;
2535		hbp = (vd->reg[backPorch].u & 0x1ff) + 2;
2536		vbp = (vd->reg[backPorch].u >> 16) & 0x1ff;
	2593	htotal = ((v->reg[hSync].u >> 16) & 0x7ff) + 1 + (v->reg[hSync].u & 0x1ff) + 1;
	2594	vtotal = ((v->reg[vSync].u >> 16) & 0x1fff) + (v->reg[vSync].u & 0x1fff);
	2595	hvis = v->reg[videoDimensions].u & 0x7ff;
	2596	vvis = (v->reg[videoDimensions].u >> 16) & 0x7ff;
	2597	hbp = (v->reg[backPorch].u & 0x1ff) + 2;
	2598	vbp = (v->reg[backPorch].u >> 16) & 0x1ff;
2537	2599	}
2538	2600	else
2539	2601	{
2540		htotal = ((vd->reg[hSync].u >> 16) & 0x3ff) + 1 + (vd->reg[hSync].u & 0xff) + 1;
2541		vtotal = ((vd->reg[vSync].u >> 16) & 0xfff) + (vd->reg[vSync].u & 0xfff);
2542		hvis = vd->reg[videoDimensions].u & 0x3ff;
2543		vvis = (vd->reg[videoDimensions].u >> 16) & 0x3ff;
2544		hbp = (vd->reg[backPorch].u & 0xff) + 2;
2545		vbp = (vd->reg[backPorch].u >> 16) & 0xff;
	2602	htotal = ((v->reg[hSync].u >> 16) & 0x3ff) + 1 + (v->reg[hSync].u & 0xff) + 1;
	2603	vtotal = ((v->reg[vSync].u >> 16) & 0xfff) + (v->reg[vSync].u & 0xfff);
	2604	hvis = v->reg[videoDimensions].u & 0x3ff;
	2605	vvis = (v->reg[videoDimensions].u >> 16) & 0x3ff;
	2606	hbp = (v->reg[backPorch].u & 0xff) + 2;
	2607	vbp = (v->reg[backPorch].u >> 16) & 0xff;
2546	2608	}
2547	2609
2548	2610	/* create a new visarea */
r253151	r253152
2566	2628	if (vgadiff < 0) vgadiff = -vgadiff;
2567	2629
2568	2630	osd_printf_debug("hSync=%08X vSync=%08X backPorch=%08X videoDimensions=%08X\n",
2569		vd->reg[hSync].u, vd->reg[vSync].u, vd->reg[backPorch].u, vd->reg[videoDimensions].u);
	2631	v->reg[hSync].u, v->reg[vSync].u, v->reg[backPorch].u, v->reg[videoDimensions].u);
2570	2632	osd_printf_debug("Horiz: %d-%d (%d total) Vert: %d-%d (%d total) -- ", visarea.min_x, visarea.max_x, htotal, visarea.min_y, visarea.max_y, vtotal);
2571	2633
2572	2634	/* configure the screen based on which one matches the closest */
2573	2635	if (stddiff < meddiff && stddiff < vgadiff)
2574	2636	{
2575		vd->screen->configure(htotal, vtotal, visarea, stdperiod);
	2637	v->screen->configure(htotal, vtotal, visarea, stdperiod);
2576	2638	osd_printf_debug("Standard resolution, %f Hz\n", ATTOSECONDS_TO_HZ(stdperiod));
2577	2639	}
2578	2640	else if (meddiff < vgadiff)
2579	2641	{
2580		vd->screen->configure(htotal, vtotal, visarea, medperiod);
	2642	v->screen->configure(htotal, vtotal, visarea, medperiod);
2581	2643	osd_printf_debug("Medium resolution, %f Hz\n", ATTOSECONDS_TO_HZ(medperiod));
2582	2644	}
2583	2645	else
2584	2646	{
2585		vd->screen->configure(htotal, vtotal, visarea, vgaperiod);
	2647	v->screen->configure(htotal, vtotal, visarea, vgaperiod);
2586	2648	osd_printf_debug("VGA resolution, %f Hz\n", ATTOSECONDS_TO_HZ(vgaperiod));
2587	2649	}
2588	2650
2589	2651	/* configure the new framebuffer info */
2590		vd->fbi.width = hvis;
2591		vd->fbi.height = vvis;
2592		vd->fbi.xoffs = hbp;
2593		vd->fbi.yoffs = vbp;
2594		vd->fbi.vsyncscan = (vd->reg[vSync].u >> 16) & 0xfff;
	2652	v->fbi.width = hvis;
	2653	v->fbi.height = vvis;
	2654	v->fbi.xoffs = hbp;
	2655	v->fbi.yoffs = vbp;
	2656	v->fbi.vsyncscan = (v->reg[vSync].u >> 16) & 0xfff;
2595	2657
2596	2658	/* recompute the time of VBLANK */
2597		adjust_vblank_timer(vd);
	2659	adjust_vblank_timer(v);
2598	2660
2599	2661	/* if changing dimensions, update video memory layout */
2600	2662	if (regnum == videoDimensions)
2601		recompute_video_memory(vd);
	2663	recompute_video_memory(v);
2602	2664	}
2603	2665	}
2604	2666	break;
2605	2667
2606	2668	/* fbiInit0 can only be written if initEnable says we can -- Voodoo/Voodoo2 only */
2607	2669	case fbiInit0:
2608		poly_wait(vd->poly, vd->regnames[regnum]);
2609		if (vd->vd_type <= TYPE_VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(vd->pci.init_enable))
	2670	poly_wait(v->poly, v->regnames[regnum]);
	2671	if (v->type <= TYPE_VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(v->pci.init_enable))
2610	2672	{
2611		vd->reg[fbiInit0].u = data;
	2673	v->reg[fbiInit0].u = data;
2612	2674	if (FBIINIT0_GRAPHICS_RESET(data))
2613		soft_reset(vd);
	2675	soft_reset(v);
2614	2676	if (FBIINIT0_FIFO_RESET(data))
2615		fifo_reset(&vd->pci.fifo);
2616		recompute_video_memory(vd);
	2677	fifo_reset(&v->pci.fifo);
	2678	recompute_video_memory(v);
2617	2679	}
2618	2680	break;
2619	2681
2620	2682	/* fbiInit5-7 are Voodoo 2-only; ignore them on anything else */
2621	2683	case fbiInit5:
2622	2684	case fbiInit6:
2623		if (vd->~~vd_~~type < TYPE_VOODOO_2)
	2685	if (v->type < TYPE_VOODOO_2)
2624	2686	break;
2625	2687	/* else fall through... */
2626	2688
r253151	r253152
2629	2691	case fbiInit1:
2630	2692	case fbiInit2:
2631	2693	case fbiInit4:
2632		poly_wait(vd->poly, vd->regnames[regnum]);
2633		if (vd->vd_type <= TYPE_VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(vd->pci.init_enable))
	2694	poly_wait(v->poly, v->regnames[regnum]);
	2695	if (v->type <= TYPE_VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(v->pci.init_enable))
2634	2696	{
2635		vd->reg[regnum].u = data;
2636		recompute_video_memory(vd);
2637		vd->fbi.video_changed = TRUE;
	2697	v->reg[regnum].u = data;
	2698	recompute_video_memory(v);
	2699	v->fbi.video_changed = TRUE;
2638	2700	}
2639	2701	break;
2640	2702
2641	2703	case fbiInit3:
2642		poly_wait(vd->poly, vd->regnames[regnum]);
2643		if (vd->vd_type <= TYPE_VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(vd->pci.init_enable))
	2704	poly_wait(v->poly, v->regnames[regnum]);
	2705	if (v->type <= TYPE_VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(v->pci.init_enable))
2644	2706	{
2645		vd->reg[regnum].u = data;
2646		vd->alt_regmap = FBIINIT3_TRI_REGISTER_REMAP(data);
2647		vd->fbi.yorigin = FBIINIT3_YORIGIN_SUBTRACT(vd->reg[fbiInit3].u);
2648		recompute_video_memory(vd);
	2707	v->reg[regnum].u = data;
	2708	v->alt_regmap = FBIINIT3_TRI_REGISTER_REMAP(data);
	2709	v->fbi.yorigin = FBIINIT3_YORIGIN_SUBTRACT(v->reg[fbiInit3].u);
	2710	recompute_video_memory(v);
2649	2711	}
2650	2712	break;
2651	2713
2652	2714	case fbiInit7:
2653	2715	/* case swapPending: -- Banshee */
2654		if (vd->~~vd_~~type == TYPE_VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(vd->pci.init_enable))
	2716	if (v->type == TYPE_VOODOO_2 && (chips & 1) && INITEN_ENABLE_HW_INIT(v->pci.init_enable))
2655	2717	{
2656		poly_wait(vd->poly, vd->regnames[regnum]);
2657		vd->reg[regnum].u = data;
2658		vd->fbi.cmdfifo[0].enable = FBIINIT7_CMDFIFO_ENABLE(data);
2659		vd->fbi.cmdfifo[0].count_holes = !FBIINIT7_DISABLE_CMDFIFO_HOLES(data);
	2718	poly_wait(v->poly, v->regnames[regnum]);
	2719	v->reg[regnum].u = data;
	2720	v->fbi.cmdfifo[0].enable = FBIINIT7_CMDFIFO_ENABLE(data);
	2721	v->fbi.cmdfifo[0].count_holes = !FBIINIT7_DISABLE_CMDFIFO_HOLES(data);
2660	2722	}
2661		else if (vd->vd_type >= TYPE_VOODOO_BANSHEE)
2662		vd->fbi.swaps_pending++;
	2723	else if (v->type >= TYPE_VOODOO_BANSHEE)
	2724	v->fbi.swaps_pending++;
2663	2725	break;
2664	2726
2665	2727	/* cmdFifo -- Voodoo2 only */
2666	2728	case cmdFifoBaseAddr:
2667		if (vd->~~vd_~~type == TYPE_VOODOO_2 && (chips & 1))
	2729	if (v->type == TYPE_VOODOO_2 && (chips & 1))
2668	2730	{
2669		poly_wait(vd->poly, vd->regnames[regnum]);
2670		vd->reg[regnum].u = data;
2671		vd->fbi.cmdfifo[0].base = (data & 0x3ff) << 12;
2672		vd->fbi.cmdfifo[0].end = (((data >> 16) & 0x3ff) + 1) << 12;
	2731	poly_wait(v->poly, v->regnames[regnum]);
	2732	v->reg[regnum].u = data;
	2733	v->fbi.cmdfifo[0].base = (data & 0x3ff) << 12;
	2734	v->fbi.cmdfifo[0].end = (((data >> 16) & 0x3ff) + 1) << 12;
2673	2735	}
2674	2736	break;
2675	2737
2676	2738	case cmdFifoBump:
2677		if (vd->~~vd_~~type == TYPE_VOODOO_2 && (chips & 1))
	2739	if (v->type == TYPE_VOODOO_2 && (chips & 1))
2678	2740	fatalerror("cmdFifoBump\n");
2679	2741	break;
2680	2742
2681	2743	case cmdFifoRdPtr:
2682		if (vd->vd_type == TYPE_VOODOO_2 && (chips & 1))
2683		vd->fbi.cmdfifo[0].rdptr = data;
	2744	if (v->type == TYPE_VOODOO_2 && (chips & 1))
	2745	v->fbi.cmdfifo[0].rdptr = data;
2684	2746	break;
2685	2747
2686	2748	case cmdFifoAMin:
2687	2749	/* case colBufferAddr: -- Banshee */
2688		if (vd->vd_type == TYPE_VOODOO_2 && (chips & 1))
2689		vd->fbi.cmdfifo[0].amin = data;
2690		else if (vd->vd_type >= TYPE_VOODOO_BANSHEE && (chips & 1))
2691		vd->fbi.rgboffs[1] = data & vd->fbi.mask & ~0x0f;
	2750	if (v->type == TYPE_VOODOO_2 && (chips & 1))
	2751	v->fbi.cmdfifo[0].amin = data;
	2752	else if (v->type >= TYPE_VOODOO_BANSHEE && (chips & 1))
	2753	v->fbi.rgboffs[1] = data & v->fbi.mask & ~0x0f;
2692	2754	break;
2693	2755
2694	2756	case cmdFifoAMax:
2695	2757	/* case colBufferStride: -- Banshee */
2696		if (vd->vd_type == TYPE_VOODOO_2 && (chips & 1))
2697		vd->fbi.cmdfifo[0].amax = data;
2698		else if (vd->vd_type >= TYPE_VOODOO_BANSHEE && (chips & 1))
	2758	if (v->type == TYPE_VOODOO_2 && (chips & 1))
	2759	v->fbi.cmdfifo[0].amax = data;
	2760	else if (v->type >= TYPE_VOODOO_BANSHEE && (chips & 1))
2699	2761	{
2700	2762	if (data & 0x8000)
2701		vd->fbi.rowpixels = (data & 0x7f) << 6;
	2763	v->fbi.rowpixels = (data & 0x7f) << 6;
2702	2764	else
2703		vd->fbi.rowpixels = (data & 0x3fff) >> 1;
	2765	v->fbi.rowpixels = (data & 0x3fff) >> 1;
2704	2766	}
2705	2767	break;
2706	2768
2707	2769	case cmdFifoDepth:
2708	2770	/* case auxBufferAddr: -- Banshee */
2709		if (vd->vd_type == TYPE_VOODOO_2 && (chips & 1))
2710		vd->fbi.cmdfifo[0].depth = data;
2711		else if (vd->vd_type >= TYPE_VOODOO_BANSHEE && (chips & 1))
2712		vd->fbi.auxoffs = data & vd->fbi.mask & ~0x0f;
	2771	if (v->type == TYPE_VOODOO_2 && (chips & 1))
	2772	v->fbi.cmdfifo[0].depth = data;
	2773	else if (v->type >= TYPE_VOODOO_BANSHEE && (chips & 1))
	2774	v->fbi.auxoffs = data & v->fbi.mask & ~0x0f;
2713	2775	break;
2714	2776
2715	2777	case cmdFifoHoles:
2716	2778	/* case auxBufferStride: -- Banshee */
2717		if (vd->vd_type == TYPE_VOODOO_2 && (chips & 1))
2718		vd->fbi.cmdfifo[0].holes = data;
2719		else if (vd->vd_type >= TYPE_VOODOO_BANSHEE && (chips & 1))
	2779	if (v->type == TYPE_VOODOO_2 && (chips & 1))
	2780	v->fbi.cmdfifo[0].holes = data;
	2781	else if (v->type >= TYPE_VOODOO_BANSHEE && (chips & 1))
2720	2782	{
2721	2783	int rowpixels;
2722	2784
r253151	r253152
2724	2786	rowpixels = (data & 0x7f) << 6;
2725	2787	else
2726	2788	rowpixels = (data & 0x3fff) >> 1;
2727		if (vd->fbi.rowpixels != rowpixels)
	2789	if (v->fbi.rowpixels != rowpixels)
2728	2790	fatalerror("aux buffer stride differs from color buffer stride\n");
2729	2791	}
2730	2792	break;
r253151	r253152
2742	2804	case nccTable+9:
2743	2805	case nccTable+10:
2744	2806	case nccTable+11:
2745		poly_wait(vd->poly, vd->regnames[regnum]);
2746		if (chips & 2) ncc_table_write(&vd->tmu[0].ncc[0], regnum - nccTable, data);
2747		if (chips & 4) ncc_table_write(&vd->tmu[1].ncc[0], regnum - nccTable, data);
	2807	poly_wait(v->poly, v->regnames[regnum]);
	2808	if (chips & 2) ncc_table_write(&v->tmu[0].ncc[0], regnum - nccTable, data);
	2809	if (chips & 4) ncc_table_write(&v->tmu[1].ncc[0], regnum - nccTable, data);
2748	2810	break;
2749	2811
2750	2812	case nccTable+12:
r253151	r253152
2759	2821	case nccTable+21:
2760	2822	case nccTable+22:
2761	2823	case nccTable+23:
2762		poly_wait(vd->poly, vd->regnames[regnum]);
2763		if (chips & 2) ncc_table_write(&vd->tmu[0].ncc[1], regnum - (nccTable+12), data);
2764		if (chips & 4) ncc_table_write(&vd->tmu[1].ncc[1], regnum - (nccTable+12), data);
	2824	poly_wait(v->poly, v->regnames[regnum]);
	2825	if (chips & 2) ncc_table_write(&v->tmu[0].ncc[1], regnum - (nccTable+12), data);
	2826	if (chips & 4) ncc_table_write(&v->tmu[1].ncc[1], regnum - (nccTable+12), data);
2765	2827	break;
2766	2828
2767	2829	/* fogTable entries are processed and expanded immediately */
r253151	r253152
2797	2859	case fogTable+29:
2798	2860	case fogTable+30:
2799	2861	case fogTable+31:
2800		poly_wait(vd->poly, vd->regnames[regnum]);
	2862	poly_wait(v->poly, v->regnames[regnum]);
2801	2863	if (chips & 1)
2802	2864	{
2803	2865	int base = 2 * (regnum - fogTable);
2804		vd->fbi.fogdelta[base + 0] = (data >> 0) & 0xff;
2805		vd->fbi.fogblend[base + 0] = (data >> 8) & 0xff;
2806		vd->fbi.fogdelta[base + 1] = (data >> 16) & 0xff;
2807		vd->fbi.fogblend[base + 1] = (data >> 24) & 0xff;
	2866	v->fbi.fogdelta[base + 0] = (data >> 0) & 0xff;
	2867	v->fbi.fogblend[base + 0] = (data >> 8) & 0xff;
	2868	v->fbi.fogdelta[base + 1] = (data >> 16) & 0xff;
	2869	v->fbi.fogblend[base + 1] = (data >> 24) & 0xff;
2808	2870	}
2809	2871	break;
2810	2872
r253151	r253152
2816	2878	case texBaseAddr_1:
2817	2879	case texBaseAddr_2:
2818	2880	case texBaseAddr_3_8:
2819		poly_wait(vd->poly, vd->regnames[regnum]);
	2881	poly_wait(v->poly, v->regnames[regnum]);
2820	2882	if (chips & 2)
2821	2883	{
2822		vd->tmu[0].reg[regnum].u = data;
2823		vd->tmu[0].regdirty = TRUE;
	2884	v->tmu[0].reg[regnum].u = data;
	2885	v->tmu[0].regdirty = TRUE;
2824	2886	}
2825	2887	if (chips & 4)
2826	2888	{
2827		vd->tmu[1].reg[regnum].u = data;
2828		vd->tmu[1].regdirty = TRUE;
	2889	v->tmu[1].reg[regnum].u = data;
	2890	v->tmu[1].regdirty = TRUE;
2829	2891	}
2830	2892	break;
2831	2893
2832	2894	case trexInit1:
2833	2895	/* send tmu config data to the frame buffer */
2834		vd->send_config = (TREXINIT_SEND_TMU_CONFIG(data) > 0);
	2896	v->send_config = (TREXINIT_SEND_TMU_CONFIG(data) > 0);
2835	2897	goto default_case;
2836	2898
2837	2899	/* these registers are referenced in the renderer; we must wait for pending work before changing */
r253151	r253152
2845	2907	case color0:
2846	2908	case clipLowYHighY:
2847	2909	case clipLeftRight:
2848		poly_wait(vd->poly, vd->regnames[regnum]);
	2910	poly_wait(v->poly, v->regnames[regnum]);
2849	2911	/* fall through to default implementation */
2850	2912
2851	2913	/* by default, just feed the data to the chips */
2852	2914	default:
2853	2915	default_case:
2854		if (chips & 1) vd->reg[0x000 + regnum].u = data;
2855		if (chips & 2) vd->reg[0x100 + regnum].u = data;
2856		if (chips & 4) vd->reg[0x200 + regnum].u = data;
2857		if (chips & 8) vd->reg[0x300 + regnum].u = data;
	2916	if (chips & 1) v->reg[0x000 + regnum].u = data;
	2917	if (chips & 2) v->reg[0x100 + regnum].u = data;
	2918	if (chips & 4) v->reg[0x200 + regnum].u = data;
	2919	if (chips & 8) v->reg[0x300 + regnum].u = data;
2858	2920	break;
2859	2921	}
2860	2922
2861	2923	if (LOG_REGISTERS)
2862	2924	{
2863	2925	if (regnum < fvertexAx \|\| regnum > fdWdY)
2864		vd->device->logerror("VOODOO.%d.REG:%s(%d) write = %08X\n", vd->index, (regnum < 0x384/4) ? vd->regnames[regnum] : "oob", chips, origdata);
	2926	v->device->logerror("VOODOO.%d.REG:%s(%d) write = %08X\n", v->index, (regnum < 0x384/4) ? v->regnames[regnum] : "oob", chips, origdata);
2865	2927	else
2866		vd->device->logerror("VOODOO.%d.REG:%s(%d) write = %f\n", vd->index, (regnum < 0x384/4) ? vd->regnames[regnum] : "oob", chips, (double) u2f(origdata));
	2928	v->device->logerror("VOODOO.%d.REG:%s(%d) write = %f\n", v->index, (regnum < 0x384/4) ? v->regnames[regnum] : "oob", chips, (double) u2f(origdata));
2867	2929	}
2868	2930
2869	2931	return cycles;
r253151	r253152
2876	2938	* Voodoo LFB writes
2877	2939	*
2878	2940	*************************************/
2879		INT32 voodoo_device::lfb_direct_w(voodoo_device *vd, offs_t offset, UINT32 data, UINT32 mem_mask)
2880		{
	2941	static INT32 lfb_direct_w(voodoo_state *v, offs_t offset, UINT32 data, UINT32 mem_mask)
	2942	{
2881	2943	UINT16 *dest;
2882	2944	UINT32 destmax;
2883	2945	int x, y;
2884	2946	UINT32 bufoffs;
2885	2947
2886	2948	/* statistics */
2887		vd->stats.lfb_writes++;
	2949	v->stats.lfb_writes++;
2888	2950
2889	2951	/* byte swizzling */
2890		if (LFBMODE_BYTE_SWIZZLE_WRITES(vd->reg[lfbMode].u))
	2952	if (LFBMODE_BYTE_SWIZZLE_WRITES(v->reg[lfbMode].u))
2891	2953	{
2892	2954	data = FLIPENDIAN_INT32(data);
2893	2955	mem_mask = FLIPENDIAN_INT32(mem_mask);
2894	2956	}
2895	2957
2896	2958	/* word swapping */
2897		if (LFBMODE_WORD_SWAP_WRITES(vd->reg[lfbMode].u))
	2959	if (LFBMODE_WORD_SWAP_WRITES(v->reg[lfbMode].u))
2898	2960	{
2899	2961	data = (data << 16) \| (data >> 16);
2900	2962	mem_mask = (mem_mask << 16) \| (mem_mask >> 16);
r253151	r253152
2904	2966	// For direct lfb access just write the data
2905	2967	/* compute X,Y */
2906	2968	offset <<= 1;
2907		x = offset & ((1 << vd->fbi.lfb_stride) - 1);
2908		y = (offset >> vd->fbi.lfb_stride);
2909		dest = (UINT16 )(vd->fbi.ram + vd->fbi.lfb_base4);
2910		destmax = (vd->fbi.mask + 1 - vd->fbi.lfb_base*4) / 2;
2911		bufoffs = y * vd->fbi.rowpixels + x;
	2969	x = offset & ((1 << v->fbi.lfb_stride) - 1);
	2970	y = (offset >> v->fbi.lfb_stride);
	2971	dest = (UINT16 )(v->fbi.ram + v->fbi.lfb_base4);
	2972	destmax = (v->fbi.mask + 1 - v->fbi.lfb_base*4) / 2;
	2973	bufoffs = y * v->fbi.rowpixels + x;
2912	2974	if (bufoffs >= destmax) {
2913		vd->device->logerror("lfb_direct_w: Buffer offset out of bounds x=%i y=%i offset=%08X bufoffs=%08X data=%08X\n", x, y, offset, (UINT32) bufoffs, data);
	2975	v->device->logerror("lfb_direct_w: Buffer offset out of bounds x=%i y=%i offset=%08X bufoffs=%08X data=%08X\n", x, y, offset, (UINT32) bufoffs, data);
2914	2976	return 0;
2915	2977	}
2916	2978	if (ACCESSING_BITS_0_15)
2917	2979	dest[bufoffs + 0] = data&0xffff;
2918	2980	if (ACCESSING_BITS_16_31)
2919	2981	dest[bufoffs + 1] = data>>16;
2920		if (LOG_LFB) vd->device->logerror("VOODOO.%d.LFB:write direct (%d,%d) = %08X & %08X\n", vd->index, x, y, data, mem_mask);
	2982	if (LOG_LFB) v->device->logerror("VOODOO.%d.LFB:write direct (%d,%d) = %08X & %08X\n", v->index, x, y, data, mem_mask);
2921	2983	return 0;
2922	2984	}
2923	2985
2924		INT32 ~~voodoo_device::~~lfb_w(voodoo_device* vd, offs_t offset, UINT32 data, UINT32 mem_mask)
	2986	static INT32 lfb_w(voodoo_state *v, offs_t offset, UINT32 data, UINT32 mem_mask)
2925	2987	{
2926
2927	2988	UINT16 dest, depth;
2928	2989	UINT32 destmax, depthmax;
2929	2990	int sr[2], sg[2], sb[2], sa[2], sw[2];
r253151	r253152
2931	2992	int pix, destbuf;
2932	2993
2933	2994	/* statistics */
2934		vd->stats.lfb_writes++;
	2995	v->stats.lfb_writes++;
2935	2996
2936	2997	/* byte swizzling */
2937		if (LFBMODE_BYTE_SWIZZLE_WRITES(vd->reg[lfbMode].u))
	2998	if (LFBMODE_BYTE_SWIZZLE_WRITES(v->reg[lfbMode].u))
2938	2999	{
2939	3000	data = FLIPENDIAN_INT32(data);
2940	3001	mem_mask = FLIPENDIAN_INT32(mem_mask);
2941	3002	}
2942	3003
2943	3004	/* word swapping */
2944		if (LFBMODE_WORD_SWAP_WRITES(vd->reg[lfbMode].u))
	3005	if (LFBMODE_WORD_SWAP_WRITES(v->reg[lfbMode].u))
2945	3006	{
2946	3007	data = (data << 16) \| (data >> 16);
2947	3008	mem_mask = (mem_mask << 16) \| (mem_mask >> 16);
2948	3009	}
2949	3010
2950	3011	/* extract default depth and alpha values */
2951		sw[0] = sw[1] = vd->reg[zaColor].u & 0xffff;
2952		sa[0] = sa[1] = vd->reg[zaColor].u >> 24;
	3012	sw[0] = sw[1] = v->reg[zaColor].u & 0xffff;
	3013	sa[0] = sa[1] = v->reg[zaColor].u >> 24;
2953	3014
2954	3015	/* first extract A,R,G,B from the data */
2955		switch (LFBMODE_WRITE_FORMAT(vd->reg[lfbMode].u) + 16 * LFBMODE_RGBA_LANES(vd->reg[lfbMode].u))
	3016	switch (LFBMODE_WRITE_FORMAT(v->reg[lfbMode].u) + 16 * LFBMODE_RGBA_LANES(v->reg[lfbMode].u))
2956	3017	{
2957	3018	case 160 + 0: / ARGB, 16-bit RGB 5-6-5 */
2958	3019	case 162 + 0: / RGBA, 16-bit RGB 5-6-5 */
r253151	r253152
3119	3180	break;
3120	3181
3121	3182	default: /* reserved */
3122		vd->device->logerror("lfb_w: Unknown format\n");
	3183	v->device->logerror("lfb_w: Unknown format\n");
3123	3184	return 0;
3124	3185	}
3125	3186
3126	3187	/* compute X,Y */
3127		x = offset & ((1 << vd->fbi.lfb_stride) - 1);
3128		y = (offset >> vd->fbi.lfb_stride) & 0x3ff;
	3188	x = offset & ((1 << v->fbi.lfb_stride) - 1);
	3189	y = (offset >> v->fbi.lfb_stride) & 0x3ff;
3129	3190
3130	3191	/* adjust the mask based on which half of the data is written */
3131	3192	if (!ACCESSING_BITS_0_15)
r253151	r253152
3134	3195	mask &= ~(0xf0 + LFB_DEPTH_PRESENT_MSW);
3135	3196
3136	3197	/* select the target buffer */
3137		destbuf = (vd->~~vd_~~type >= TYPE_VOODOO_BANSHEE) ? 1 : LFBMODE_WRITE_BUFFER_SELECT(vd->reg[lfbMode].u);
	3198	destbuf = (v->type >= TYPE_VOODOO_BANSHEE) ? 1 : LFBMODE_WRITE_BUFFER_SELECT(v->reg[lfbMode].u);
3138	3199	switch (destbuf)
3139	3200	{
3140	3201	case 0: /* front buffer */
3141		dest = (UINT16 *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.frontbuf]);
3142		destmax = (vd->fbi.mask + 1 - vd->fbi.rgboffs[vd->fbi.frontbuf]) / 2;
3143		vd->fbi.video_changed = TRUE;
	3202	dest = (UINT16 *)(v->fbi.ram + v->fbi.rgboffs[v->fbi.frontbuf]);
	3203	destmax = (v->fbi.mask + 1 - v->fbi.rgboffs[v->fbi.frontbuf]) / 2;
	3204	v->fbi.video_changed = TRUE;
3144	3205	break;
3145	3206
3146	3207	case 1: /* back buffer */
3147		dest = (UINT16 *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.backbuf]);
3148		destmax = (vd->fbi.mask + 1 - vd->fbi.rgboffs[vd->fbi.backbuf]) / 2;
	3208	dest = (UINT16 *)(v->fbi.ram + v->fbi.rgboffs[v->fbi.backbuf]);
	3209	destmax = (v->fbi.mask + 1 - v->fbi.rgboffs[v->fbi.backbuf]) / 2;
3149	3210	break;
3150	3211
3151	3212	default: /* reserved */
3152	3213	return 0;
3153	3214	}
3154		depth = (UINT16 *)(vd->fbi.ram + vd->fbi.auxoffs);
3155		depthmax = (vd->fbi.mask + 1 - vd->fbi.auxoffs) / 2;
	3215	depth = (UINT16 *)(v->fbi.ram + v->fbi.auxoffs);
	3216	depthmax = (v->fbi.mask + 1 - v->fbi.auxoffs) / 2;
3156	3217
3157	3218	/* simple case: no pipeline */
3158		if (!LFBMODE_ENABLE_PIXEL_PIPELINE(vd->reg[lfbMode].u))
	3219	if (!LFBMODE_ENABLE_PIXEL_PIPELINE(v->reg[lfbMode].u))
3159	3220	{
3160	3221	DECLARE_DITHER_POINTERS_NO_DITHER_VAR;
3161	3222	UINT32 bufoffs;
3162	3223
3163		if (LOG_LFB) vd->device->logerror("VOODOO.%d.LFB:write raw mode %X (%d,%d) = %08X & %08X\n", vd->index, LFBMODE_WRITE_FORMAT(vd->reg[lfbMode].u), x, y, data, mem_mask);
	3224	if (LOG_LFB) v->device->logerror("VOODOO.%d.LFB:write raw mode %X (%d,%d) = %08X & %08X\n", v->index, LFBMODE_WRITE_FORMAT(v->reg[lfbMode].u), x, y, data, mem_mask);
3164	3225
3165	3226	/* determine the screen Y */
3166	3227	scry = y;
3167		if (LFBMODE_Y_ORIGIN(vd->reg[lfbMode].u))
3168		scry = (vd->fbi.yorigin - y) & 0x3ff;
	3228	if (LFBMODE_Y_ORIGIN(v->reg[lfbMode].u))
	3229	scry = (v->fbi.yorigin - y) & 0x3ff;
3169	3230
3170	3231	/* advance pointers to the proper row */
3171		bufoffs = scry * vd->fbi.rowpixels + x;
	3232	bufoffs = scry * v->fbi.rowpixels + x;
3172	3233
3173	3234	/* compute dithering */
3174		COMPUTE_DITHER_POINTERS_NO_DITHER_VAR(vd->reg[fbzMode].u, y);
	3235	COMPUTE_DITHER_POINTERS_NO_DITHER_VAR(v->reg[fbzMode].u, y);
3175	3236
3176	3237	/* wait for any outstanding work to finish */
3177		poly_wait(vd->poly, "LFB Write");
	3238	poly_wait(v->poly, "LFB Write");
3178	3239
3179	3240	/* loop over up to two pixels */
3180	3241	for (pix = 0; mask; pix++)
r253151	r253152
3186	3247	if ((mask & LFB_RGB_PRESENT) && bufoffs < destmax)
3187	3248	{
3188	3249	/* apply dithering and write to the screen */
3189		APPLY_DITHER(vd->reg[fbzMode].u, x, dither_lookup, sr[pix], sg[pix], sb[pix]);
	3250	APPLY_DITHER(v->reg[fbzMode].u, x, dither_lookup, sr[pix], sg[pix], sb[pix]);
3190	3251	dest[bufoffs] = (sr[pix] << 11) \| (sg[pix] << 5) \| sb[pix];
3191	3252	}
3192	3253
r253151	r253152
3194	3255	if (depth && bufoffs < depthmax)
3195	3256	{
3196	3257	/* write to the alpha buffer */
3197		if ((mask & LFB_ALPHA_PRESENT) && FBZMODE_ENABLE_ALPHA_PLANES(vd->reg[fbzMode].u))
	3258	if ((mask & LFB_ALPHA_PRESENT) && FBZMODE_ENABLE_ALPHA_PLANES(v->reg[fbzMode].u))
3198	3259	depth[bufoffs] = sa[pix];
3199	3260
3200	3261	/* write to the depth buffer */
3201		if ((mask & (LFB_DEPTH_PRESENT \| LFB_DEPTH_PRESENT_MSW)) && !FBZMODE_ENABLE_ALPHA_PLANES(vd->reg[fbzMode].u))
	3262	if ((mask & (LFB_DEPTH_PRESENT \| LFB_DEPTH_PRESENT_MSW)) && !FBZMODE_ENABLE_ALPHA_PLANES(v->reg[fbzMode].u))
3202	3263	depth[bufoffs] = sw[pix];
3203	3264	}
3204	3265
3205	3266	/* track pixel writes to the frame buffer regardless of mask */
3206		vd->reg[fbiPixelsOut].u++;
	3267	v->reg[fbiPixelsOut].u++;
3207	3268	}
3208	3269
3209	3270	/* advance our pointers */
r253151	r253152
3218	3279	{
3219	3280	DECLARE_DITHER_POINTERS;
3220	3281
3221		if (LOG_LFB) vd->device->logerror("VOODOO.%d.LFB:write pipelined mode %X (%d,%d) = %08X & %08X\n", vd->index, LFBMODE_WRITE_FORMAT(vd->reg[lfbMode].u), x, y, data, mem_mask);
	3282	if (LOG_LFB) v->device->logerror("VOODOO.%d.LFB:write pipelined mode %X (%d,%d) = %08X & %08X\n", v->index, LFBMODE_WRITE_FORMAT(v->reg[lfbMode].u), x, y, data, mem_mask);
3222	3283
3223	3284	/* determine the screen Y */
3224	3285	scry = y;
3225		if (FBZMODE_Y_ORIGIN(vd->reg[fbzMode].u))
3226		scry = (vd->fbi.yorigin - y) & 0x3ff;
	3286	if (FBZMODE_Y_ORIGIN(v->reg[fbzMode].u))
	3287	scry = (v->fbi.yorigin - y) & 0x3ff;
3227	3288
3228	3289	/* advance pointers to the proper row */
3229		dest += scry * vd->fbi.rowpixels;
	3290	dest += scry * v->fbi.rowpixels;
3230	3291	if (depth)
3231		depth += scry * vd->fbi.rowpixels;
	3292	depth += scry * v->fbi.rowpixels;
3232	3293
3233	3294	/* compute dithering */
3234		COMPUTE_DITHER_POINTERS(vd->reg[fbzMode].u, y);
	3295	COMPUTE_DITHER_POINTERS(v->reg[fbzMode].u, y);
3235	3296
3236	3297	/* loop over up to two pixels */
3237	3298	for (pix = 0; mask; pix++)
r253151	r253152
3239	3300	/* make sure we care about this pixel */
3240	3301	if (mask & 0x0f)
3241	3302	{
3242		stats_block *stats = &vd->fbi.lfb_stats;
	3303	stats_block *stats = &v->fbi.lfb_stats;
3243	3304	INT64 iterw;
3244		if (LFBMODE_WRITE_W_SELECT(vd->reg[lfbMode].u)) {
3245		iterw = (UINT32) vd->reg[zaColor].u << 16;
	3305	if (LFBMODE_WRITE_W_SELECT(v->reg[lfbMode].u)) {
	3306	iterw = (UINT32) v->reg[zaColor].u << 16;
3246	3307	} else {
3247	3308	// The most significant fractional bits of 16.32 W are set to z
3248	3309	iterw = (UINT32) sw[pix] << 16;
r253151	r253152
3250	3311	INT32 iterz = sw[pix] << 12;
3251	3312
3252	3313	/* apply clipping */
3253		if (FBZMODE_ENABLE_CLIPPING(vd->reg[fbzMode].u))
	3314	if (FBZMODE_ENABLE_CLIPPING(v->reg[fbzMode].u))
3254	3315	{
3255		if (x < ((vd->reg[clipLeftRight].u >> 16) & 0x3ff) \|\|
3256		x >= (vd->reg[clipLeftRight].u & 0x3ff) \|\|
3257		scry < ((vd->reg[clipLowYHighY].u >> 16) & 0x3ff) \|\|
3258		scry >= (vd->reg[clipLowYHighY].u & 0x3ff))
	3316	if (x < ((v->reg[clipLeftRight].u >> 16) & 0x3ff) \|\|
	3317	x >= (v->reg[clipLeftRight].u & 0x3ff) \|\|
	3318	scry < ((v->reg[clipLowYHighY].u >> 16) & 0x3ff) \|\|
	3319	scry >= (v->reg[clipLowYHighY].u & 0x3ff))
3259	3320	{
3260	3321	stats->pixels_in++;
3261	3322	stats->clip_fail++;
r253151	r253152
3268	3329
3269	3330
3270	3331	/* pixel pipeline part 1 handles depth testing and stippling */
3271		//PIXEL_PIPELINE_BEGIN(v, stats, x, y, vd->reg[fbzColorPath].u, vd->reg[fbzMode].u, iterz, iterw);
	3332	//PIXEL_PIPELINE_BEGIN(v, stats, x, y, v->reg[fbzColorPath].u, v->reg[fbzMode].u, iterz, iterw);
3272	3333	// Start PIXEL_PIPE_BEGIN copy
3273	3334	//#define PIXEL_PIPELINE_BEGIN(VV, STATS, XX, YY, FBZCOLORPATH, FBZMODE, ITERZ, ITERW)
3274	3335	INT32 fogdepth, biasdepth;
r253151	r253152
3280	3341	/* note that for perf reasons, we assume the caller has done clipping */
3281	3342
3282	3343	/* handle stippling */
3283		if (FBZMODE_ENABLE_STIPPLE(vd->reg[fbzMode].u))
	3344	if (FBZMODE_ENABLE_STIPPLE(v->reg[fbzMode].u))
3284	3345	{
3285	3346	/* rotate mode */
3286		if (FBZMODE_STIPPLE_PATTERN(vd->reg[fbzMode].u) == 0)
	3347	if (FBZMODE_STIPPLE_PATTERN(v->reg[fbzMode].u) == 0)
3287	3348	{
3288		vd->reg[stipple].u = (vd->reg[stipple].u << 1) \| (vd->reg[stipple].u >> 31);
3289		if ((vd->reg[stipple].u & 0x80000000) == 0)
	3349	v->reg[stipple].u = (v->reg[stipple].u << 1) \| (v->reg[stipple].u >> 31);
	3350	if ((v->reg[stipple].u & 0x80000000) == 0)
3290	3351	{
3291		vd->stats.total_stippled++;
	3352	v->stats.total_stippled++;
3292	3353	goto skipdrawdepth;
3293	3354	}
3294	3355	}
r253151	r253152
3297	3358	else
3298	3359	{
3299	3360	int stipple_index = ((y & 3) << 3) \| (~x & 7);
3300		if (((vd->reg[stipple].u >> stipple_index) & 1) == 0)
	3361	if (((v->reg[stipple].u >> stipple_index) & 1) == 0)
3301	3362	{
3302		vd->stats.total_stippled++;
	3363	v->stats.total_stippled++;
3303	3364	goto nextpixel;
3304	3365	}
3305	3366	}
r253151	r253152
3311	3372
3312	3373
3313	3374	/* Perform depth testing */
3314		if (!depthTest((UINT16) vd->reg[zaColor].u, stats, depth[x], vd->reg[fbzMode].u, biasdepth))
	3375	if (!depthTest((UINT16) v->reg[zaColor].u, stats, depth[x], v->reg[fbzMode].u, biasdepth))
3315	3376	goto nextpixel;
3316	3377
3317	3378	/* use the RGBA we stashed above */
3318	3379	color.set(sa[pix], sr[pix], sg[pix], sb[pix]);
3319	3380
3320	3381	/* handle chroma key */
3321		if (!chromaKeyTest(vd, stats, vd->reg[fbzMode].u, color))
	3382	if (!chromaKeyTest(v, stats, v->reg[fbzMode].u, color))
3322	3383	goto nextpixel;
3323	3384	/* handle alpha mask */
3324		if (!alphaMaskTest(stats, vd->reg[fbzMode].u, color.get_a()))
	3385	if (!alphaMaskTest(stats, v->reg[fbzMode].u, color.get_a()))
3325	3386	goto nextpixel;
3326	3387	/* handle alpha test */
3327		if (!alphaTest(vd, stats, vd->reg[alphaMode].u, color.get_a()))
	3388	if (!alphaTest(v, stats, v->reg[alphaMode].u, color.get_a()))
3328	3389	goto nextpixel;
3329	3390
3330	3391
3331	3392	/* wait for any outstanding work to finish */
3332		poly_wait(vd->poly, "LFB Write");
	3393	poly_wait(v->poly, "LFB Write");
3333	3394
3334	3395	/* pixel pipeline part 2 handles color combine, fog, alpha, and final output */
3335		PIXEL_PIPELINE_END(vd, stats, dither, dither4, dither_lookup, x, dest, depth,
3336		vd->reg[fbzMode].u, vd->reg[fbzColorPath].u, vd->reg[alphaMode].u, vd->reg[fogMode].u,
	3396	PIXEL_PIPELINE_END(v, stats, dither, dither4, dither_lookup, x, dest, depth,
	3397	v->reg[fbzMode].u, v->reg[fbzColorPath].u, v->reg[alphaMode].u, v->reg[fogMode].u,
3337	3398	iterz, iterw, iterargb) {};
3338	3399	nextpixel:
3339	3400	/* advance our pointers */
r253151	r253152
3353	3414	*
3354	3415	*************************************/
3355	3416
3356		INT32 ~~voodoo_device::~~texture_w(voodoo_de~~vice~~ *vd, offs_t offset, UINT32 data)
	3417	static INT32 texture_w(voodoo_state *v, offs_t offset, UINT32 data)
3357	3418	{
3358	3419	int tmunum = (offset >> 19) & 0x03;
3359	3420	tmu_state *t;
3360	3421
3361	3422	/* statistics */
3362		vd->stats.tex_writes++;
	3423	v->stats.tex_writes++;
3363	3424
3364	3425	/* point to the right TMU */
3365		if (!(vd->chipmask & (2 << tmunum)))
	3426	if (!(v->chipmask & (2 << tmunum)))
3366	3427	return 0;
3367		t = &vd->tmu[tmunum];
	3428	t = &v->tmu[tmunum];
3368	3429
3369	3430	if (TEXLOD_TDIRECT_WRITE(t->reg[tLOD].u))
3370	3431	fatalerror("Texture direct write!\n");
3371	3432
3372	3433	/* wait for any outstanding work to finish */
3373		poly_wait(vd->poly, "Texture write");
	3434	poly_wait(v->poly, "Texture write");
3374	3435
3375	3436	/* update texture info if dirty */
3376	3437	if (t->regdirty)
r253151	r253152
3390	3451	UINT8 *dest;
3391	3452
3392	3453	/* extract info */
3393		if (vd->~~vd_~~type <= TYPE_VOODOO_2)
	3454	if (v->type <= TYPE_VOODOO_2)
3394	3455	{
3395	3456	lod = (offset >> 15) & 0x0f;
3396	3457	tt = (offset >> 7) & 0xff;
3397	3458
3398	3459	/* old code has a bit about how this is broken in gauntleg unless we always look at TMU0 */
3399		if (TEXMODE_SEQ_8_DOWNLD(vd->tmu[0].reg/t->reg/[textureMode].u))
	3460	if (TEXMODE_SEQ_8_DOWNLD(v->tmu[0].reg/t->reg/[textureMode].u))
3400	3461	ts = (offset << 2) & 0xfc;
3401	3462	else
3402	3463	ts = (offset << 1) & 0xfc;
r253151	r253152
3409	3470	tbaseaddr = t->lodoffset[lod];
3410	3471	tbaseaddr += tt * ((t->wmask >> lod) + 1) + ts;
3411	3472
3412		if (LOG_TEXTURE_RAM) vd->device->logerror("Texture 8-bit w: lod=%d s=%d t=%d data=%08X\n", lod, ts, tt, data);
	3473	if (LOG_TEXTURE_RAM) v->device->logerror("Texture 8-bit w: lod=%d s=%d t=%d data=%08X\n", lod, ts, tt, data);
3413	3474	}
3414	3475	else
3415	3476	{
3416	3477	tbaseaddr = t->lodoffset[0] + offset*4;
3417	3478
3418		if (LOG_TEXTURE_RAM) vd->device->logerror("Texture 8-bit w: offset=%X data=%08X\n", offset*4, data);
	3479	if (LOG_TEXTURE_RAM) v->device->logerror("Texture 8-bit w: offset=%X data=%08X\n", offset*4, data);
3419	3480	}
3420	3481
3421	3482	/* write the four bytes in little-endian order */
r253151	r253152
3435	3496	UINT16 *dest;
3436	3497
3437	3498	/* extract info */
3438		if (vd->~~vd_~~type <= TYPE_VOODOO_2)
	3499	if (v->type <= TYPE_VOODOO_2)
3439	3500	{
3440	3501	lod = (offset >> 15) & 0x0f;
3441	3502	tt = (offset >> 7) & 0xff;
r253151	r253152
3449	3510	tbaseaddr = t->lodoffset[lod];
3450	3511	tbaseaddr += 2 * (tt * ((t->wmask >> lod) + 1) + ts);
3451	3512
3452		if (LOG_TEXTURE_RAM) vd->device->logerror("Texture 16-bit w: lod=%d s=%d t=%d data=%08X\n", lod, ts, tt, data);
	3513	if (LOG_TEXTURE_RAM) v->device->logerror("Texture 16-bit w: lod=%d s=%d t=%d data=%08X\n", lod, ts, tt, data);
3453	3514	}
3454	3515	else
3455	3516	{
3456	3517	tbaseaddr = t->lodoffset[0] + offset*4;
3457	3518
3458		if (LOG_TEXTURE_RAM) vd->device->logerror("Texture 16-bit w: offset=%X data=%08X\n", offset*4, data);
	3519	if (LOG_TEXTURE_RAM) v->device->logerror("Texture 16-bit w: offset=%X data=%08X\n", offset*4, data);
3459	3520	}
3460	3521
3461	3522	/* write the two words in little-endian order */
r253151	r253152
3477	3538	*
3478	3539	*************************************/
3479	3540
3480		void vo~~odoo_dev~~i~~ce::~~flush_fifos(voodoo_de~~vice~~ *vd, attotime current_time)
	3541	static void flush_fifos(voodoo_state *v, attotime current_time)
3481	3542	{
3482	3543	static UINT8 in_flush;
3483	3544
r253151	r253152
3486	3547	return;
3487	3548	in_flush = TRUE;
3488	3549
3489		if (!vd->pci.op_pending) fatalerror("flush_fifos called with no pending operation\n");
	3550	if (!v->pci.op_pending) fatalerror("flush_fifos called with no pending operation\n");
3490	3551
3491		if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:flush_fifos start -- pending=%d.%08X%08X cur=%d.%08X%08X\n", vd->index,
3492		vd->pci.op_end_time.seconds(), (UINT32)(vd->pci.op_end_time.attoseconds() >> 32), (UINT32)vd->pci.op_end_time.attoseconds(),
	3552	if (LOG_FIFO_VERBOSE) v->device->logerror("VOODOO.%d.FIFO:flush_fifos start -- pending=%d.%08X%08X cur=%d.%08X%08X\n", v->index,
	3553	v->pci.op_end_time.seconds(), (UINT32)(v->pci.op_end_time.attoseconds() >> 32), (UINT32)v->pci.op_end_time.attoseconds(),
3493	3554	current_time.seconds(), (UINT32)(current_time.attoseconds() >> 32), (UINT32)current_time.attoseconds());
3494	3555
3495	3556	/* loop while we still have cycles to burn */
3496		while (vd->pci.op_end_time <= current_time)
	3557	while (v->pci.op_end_time <= current_time)
3497	3558	{
3498	3559	INT32 extra_cycles = 0;
3499	3560	INT32 cycles;
r253151	r253152
3506	3567	UINT32 data;
3507	3568
3508	3569	/* we might be in CMDFIFO mode */
3509		if (vd->fbi.cmdfifo[0].enable)
	3570	if (v->fbi.cmdfifo[0].enable)
3510	3571	{
3511	3572	/* if we don't have anything to execute, we're done for now */
3512		cycles = cmdfifo_execute_if_ready(vd, &vd->fbi.cmdfifo[0]);
	3573	cycles = cmdfifo_execute_if_ready(v, &v->fbi.cmdfifo[0]);
3513	3574	if (cycles == -1)
3514	3575	{
3515		vd->pci.op_pending = FALSE;
	3576	v->pci.op_pending = FALSE;
3516	3577	in_flush = FALSE;
3517		if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- CMDFIFO empty\n", vd->index);
	3578	if (LOG_FIFO_VERBOSE) v->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- CMDFIFO empty\n", v->index);
3518	3579	return;
3519	3580	}
3520	3581	}
3521		else if (vd->fbi.cmdfifo[1].enable)
	3582	else if (v->fbi.cmdfifo[1].enable)
3522	3583	{
3523	3584	/* if we don't have anything to execute, we're done for now */
3524		cycles = cmdfifo_execute_if_ready(vd, &vd->fbi.cmdfifo[1]);
	3585	cycles = cmdfifo_execute_if_ready(v, &v->fbi.cmdfifo[1]);
3525	3586	if (cycles == -1)
3526	3587	{
3527		vd->pci.op_pending = FALSE;
	3588	v->pci.op_pending = FALSE;
3528	3589	in_flush = FALSE;
3529		if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- CMDFIFO empty\n", vd->index);
	3590	if (LOG_FIFO_VERBOSE) v->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- CMDFIFO empty\n", v->index);
3530	3591	return;
3531	3592	}
3532	3593	}
r253151	r253152
3535	3596	else
3536	3597	{
3537	3598	/* choose which FIFO to read from */
3538		if (!fifo_empty(&vd->fbi.fifo))
3539		fifo = &vd->fbi.fifo;
3540		else if (!fifo_empty(&vd->pci.fifo))
3541		fifo = &vd->pci.fifo;
	3599	if (!fifo_empty(&v->fbi.fifo))
	3600	fifo = &v->fbi.fifo;
	3601	else if (!fifo_empty(&v->pci.fifo))
	3602	fifo = &v->pci.fifo;
3542	3603	else
3543	3604	{
3544		vd->pci.op_pending = FALSE;
	3605	v->pci.op_pending = FALSE;
3545	3606	in_flush = FALSE;
3546		if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- FIFOs empty\n", vd->index);
	3607	if (LOG_FIFO_VERBOSE) v->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- FIFOs empty\n", v->index);
3547	3608	return;
3548	3609	}
3549	3610
r253151	r253152
3553	3614
3554	3615	/* target the appropriate location */
3555	3616	if ((address & (0xc00000/4)) == 0)
3556		cycles = register_w(vd, address, data);
	3617	cycles = register_w(v, address, data);
3557	3618	else if (address & (0x800000/4))
3558		cycles = texture_w(vd, address, data);
	3619	cycles = texture_w(v, address, data);
3559	3620	else
3560	3621	{
3561	3622	UINT32 mem_mask = 0xffffffff;
r253151	r253152
3567	3628	mem_mask &= 0xffff0000;
3568	3629	address &= 0xffffff;
3569	3630
3570		cycles = lfb_w(vd, address, data, mem_mask);
	3631	cycles = lfb_w(v, address, data, mem_mask);
3571	3632	}
3572	3633	}
3573	3634
r253151	r253152
3584	3645	cycles += extra_cycles;
3585	3646
3586	3647	/* account for those cycles */
3587		vd->pci.op_end_time += attotime(0, (attoseconds_t)cycles * vd->attoseconds_per_cycle);
	3648	v->pci.op_end_time += attotime(0, (attoseconds_t)cycles * v->attoseconds_per_cycle);
3588	3649
3589		if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:update -- pending=%d.%08X%08X cur=%d.%08X%08X\n", vd->index,
3590		vd->pci.op_end_time.seconds(), (UINT32)(vd->pci.op_end_time.attoseconds() >> 32), (UINT32)vd->pci.op_end_time.attoseconds(),
	3650	if (LOG_FIFO_VERBOSE) v->device->logerror("VOODOO.%d.FIFO:update -- pending=%d.%08X%08X cur=%d.%08X%08X\n", v->index,
	3651	v->pci.op_end_time.seconds(), (UINT32)(v->pci.op_end_time.attoseconds() >> 32), (UINT32)v->pci.op_end_time.attoseconds(),
3591	3652	current_time.seconds(), (UINT32)(current_time.attoseconds() >> 32), (UINT32)current_time.attoseconds());
3592	3653	}
3593	3654
3594		if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- pending command complete at %d.%08X%08X\n", vd->index,
3595		vd->pci.op_end_time.seconds(), (UINT32)(vd->pci.op_end_time.attoseconds() >> 32), (UINT32)vd->pci.op_end_time.attoseconds());
	3655	if (LOG_FIFO_VERBOSE) v->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- pending command complete at %d.%08X%08X\n", v->index,
	3656	v->pci.op_end_time.seconds(), (UINT32)(v->pci.op_end_time.attoseconds() >> 32), (UINT32)v->pci.op_end_time.attoseconds());
3596	3657
3597	3658	in_flush = FALSE;
3598	3659	}
r253151	r253152
3608	3669
3609	3670	WRITE32_MEMBER( voodoo_device::voodoo_w )
3610	3671	{
	3672	voodoo_state *v = get_safe_token(this);
3611	3673	int stall = FALSE;
3612	3674
3613	3675	g_profiler.start(PROFILER_USER1);
3614	3676
3615	3677	/* should not be getting accesses while stalled */
3616		if (pci.stall_state != NOT_STALLED)
	3678	if (v->pci.stall_state != NOT_STALLED)
3617	3679	logerror("voodoo_w while stalled!\n");
3618	3680
3619	3681	/* if we have something pending, flush the FIFOs up to the current time */
3620		if (pci.op_pending)
3621		flush_fifos(this, machine().time());
	3682	if (v->pci.op_pending)
	3683	flush_fifos(v, machine().time());
3622	3684
3623	3685	/* special handling for registers */
3624	3686	if ((offset & 0xc00000/4) == 0)
r253151	r253152
3626	3688	UINT8 access;
3627	3689
3628	3690	/* some special stuff for Voodoo 2 */
3629		if (vd_type >= TYPE_VOODOO_2)
	3691	if (v->type >= TYPE_VOODOO_2)
3630	3692	{
3631	3693	/* we might be in CMDFIFO mode */
3632		if (FBIINIT7_CMDFIFO_ENABLE(reg[fbiInit7].u))
	3694	if (FBIINIT7_CMDFIFO_ENABLE(v->reg[fbiInit7].u))
3633	3695	{
3634	3696	/* if bit 21 is set, we're writing to the FIFO */
3635	3697	if (offset & 0x200000/4)
r253151	r253152
3637	3699	/* check for byte swizzling (bit 18) */
3638	3700	if (offset & 0x40000/4)
3639	3701	data = FLIPENDIAN_INT32(data);
3640		cmdfifo_w(~~this~~, &fbi.cmdfifo[0], offset & 0xffff, data);
	3702	cmdfifo_w(v, &v->fbi.cmdfifo[0], offset & 0xffff, data);
3641	3703	g_profiler.stop();
3642	3704	return;
3643	3705	}
3644	3706
3645	3707	/* we're a register access; but only certain ones are allowed */
3646		access = regaccess[offset & 0xff];
	3708	access = v->regaccess[offset & 0xff];
3647	3709	if (!(access & REGISTER_WRITETHRU))
3648	3710	{
3649	3711	/* track swap buffers regardless */
3650	3712	if ((offset & 0xff) == swapbufferCMD)
3651		fbi.swaps_pending++;
	3713	v->fbi.swaps_pending++;
3652	3714
3653		logerror("Ignoring write to %s in CMDFIFO mode\n", regnames[offset & 0xff]);
	3715	logerror("Ignoring write to %s in CMDFIFO mode\n", v->regnames[offset & 0xff]);
3654	3716	g_profiler.stop();
3655	3717	return;
3656	3718	}
r253151	r253152
3663	3725
3664	3726	/* check the access behavior; note that the table works even if the */
3665	3727	/* alternate mapping is used */
3666		access = regaccess[offset & 0xff];
	3728	access = v->regaccess[offset & 0xff];
3667	3729
3668	3730	/* ignore if writes aren't allowed */
3669	3731	if (!(access & REGISTER_WRITE))
r253151	r253152
3678	3740
3679	3741	/* track swap buffers */
3680	3742	if ((offset & 0xff) == swapbufferCMD)
3681		fbi.swaps_pending++;
	3743	v->fbi.swaps_pending++;
3682	3744	}
3683	3745
3684	3746	/* if we don't have anything pending, or if FIFOs are disabled, just execute */
3685		if (!pci.op_pending \|\| !INITEN_ENABLE_PCI_FIFO(pci.init_enable))
	3747	if (!v->pci.op_pending \|\| !INITEN_ENABLE_PCI_FIFO(v->pci.init_enable))
3686	3748	{
3687	3749	int cycles;
3688	3750
3689	3751	/* target the appropriate location */
3690	3752	if ((offset & (0xc00000/4)) == 0)
3691		cycles = register_w(~~this~~, offset, data);
	3753	cycles = register_w(v, offset, data);
3692	3754	else if (offset & (0x800000/4))
3693		cycles = texture_w(~~this~~, offset, data);
	3755	cycles = texture_w(v, offset, data);
3694	3756	else
3695		cycles = lfb_w(~~this~~, offset, data, mem_mask);
	3757	cycles = lfb_w(v, offset, data, mem_mask);
3696	3758
3697	3759	/* if we ended up with cycles, mark the operation pending */
3698	3760	if (cycles)
3699	3761	{
3700		pci.op_pending = TRUE;
3701		pci.op_end_time = machine().time() + attotime(0, (attoseconds_t)cycles * attoseconds_per_cycle);
	3762	v->pci.op_pending = TRUE;
	3763	v->pci.op_end_time = machine().time() + attotime(0, (attoseconds_t)cycles * v->attoseconds_per_cycle);
3702	3764
3703		if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:direct write start at %d.%08X%08X end at %d.%08X%08X\n", index,
	3765	if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:direct write start at %d.%08X%08X end at %d.%08X%08X\n", v->index,
3704	3766	machine().time().seconds(), (UINT32)(machine().time().attoseconds() >> 32), (UINT32)machine().time().attoseconds(),
3705		pci.op_end_time.seconds(), (UINT32)(pci.op_end_time.attoseconds() >> 32), (UINT32)pci.op_end_time.attoseconds());
	3767	v->pci.op_end_time.seconds(), (UINT32)(v->pci.op_end_time.attoseconds() >> 32), (UINT32)v->pci.op_end_time.attoseconds());
3706	3768	}
3707	3769	g_profiler.stop();
3708	3770	return;
r253151	r253152
3718	3780	}
3719	3781
3720	3782	/* if there's room in the PCI FIFO, add there */
3721		if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:voodoo_w adding to PCI FIFO @ %08X=%08X\n", this, offset, data);
3722		if (!fifo_full(&pci.fifo))
	3783	if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:voodoo_w adding to PCI FIFO @ %08X=%08X\n", v->index, offset, data);
	3784	if (!fifo_full(&v->pci.fifo))
3723	3785	{
3724		fifo_add(&pci.fifo, offset);
3725		fifo_add(&pci.fifo, data);
	3786	fifo_add(&v->pci.fifo, offset);
	3787	fifo_add(&v->pci.fifo, data);
3726	3788	}
3727	3789	else
3728	3790	fatalerror("PCI FIFO full\n");
3729	3791
3730	3792	/* handle flushing to the memory FIFO */
3731		if (FBIINIT0_ENABLE_MEMORY_FIFO(reg[fbiInit0].u) &&
3732		fifo_space(&pci.fifo) <= 2 * FBIINIT4_MEMORY_FIFO_LWM(reg[fbiInit4].u))
	3793	if (FBIINIT0_ENABLE_MEMORY_FIFO(v->reg[fbiInit0].u) &&
	3794	fifo_space(&v->pci.fifo) <= 2 * FBIINIT4_MEMORY_FIFO_LWM(v->reg[fbiInit4].u))
3733	3795	{
3734	3796	UINT8 valid[4];
3735	3797
3736	3798	/* determine which types of data can go to the memory FIFO */
3737	3799	valid[0] = TRUE;
3738		valid[1] = FBIINIT0_LFB_TO_MEMORY_FIFO(reg[fbiInit0].u);
3739		valid[2] = valid[3] = FBIINIT0_TEXMEM_TO_MEMORY_FIFO(reg[fbiInit0].u);
	3800	valid[1] = FBIINIT0_LFB_TO_MEMORY_FIFO(v->reg[fbiInit0].u);
	3801	valid[2] = valid[3] = FBIINIT0_TEXMEM_TO_MEMORY_FIFO(v->reg[fbiInit0].u);
3740	3802
3741	3803	/* flush everything we can */
3742		if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:voodoo_w moving PCI FIFO to memory FIFO\n", index);
3743		while (!fifo_empty(&pci.fifo) && valid[(fifo_peek(&pci.fifo) >> 22) & 3])
	3804	if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:voodoo_w moving PCI FIFO to memory FIFO\n", v->index);
	3805	while (!fifo_empty(&v->pci.fifo) && valid[(fifo_peek(&v->pci.fifo) >> 22) & 3])
3744	3806	{
3745		fifo_add(&fbi.fifo, fifo_remove(&pci.fifo));
3746		fifo_add(&fbi.fifo, fifo_remove(&pci.fifo));
	3807	fifo_add(&v->fbi.fifo, fifo_remove(&v->pci.fifo));
	3808	fifo_add(&v->fbi.fifo, fifo_remove(&v->pci.fifo));
3747	3809	}
3748	3810
3749	3811	/* if we're above the HWM as a result, stall */
3750		if (FBIINIT0_STALL_PCIE_FOR_HWM(reg[fbiInit0].u) &&
3751		fifo_items(&fbi.fifo) >= 2 * 32 * FBIINIT0_MEMORY_FIFO_HWM(reg[fbiInit0].u))
	3812	if (FBIINIT0_STALL_PCIE_FOR_HWM(v->reg[fbiInit0].u) &&
	3813	fifo_items(&v->fbi.fifo) >= 2 * 32 * FBIINIT0_MEMORY_FIFO_HWM(v->reg[fbiInit0].u))
3752	3814	{
3753		if (LOG_FIFO) logerror("VOODOO.%d.FIFO:voodoo_w hit memory FIFO HWM -- stalling\n", index);
3754		stall_cpu(this, STALLED_UNTIL_FIFO_LWM, machine().time());
	3815	if (LOG_FIFO) logerror("VOODOO.%d.FIFO:voodoo_w hit memory FIFO HWM -- stalling\n", v->index);
	3816	stall_cpu(v, STALLED_UNTIL_FIFO_LWM, machine().time());
3755	3817	}
3756	3818	}
3757	3819
3758	3820	/* if we're at the LWM for the PCI FIFO, stall */
3759		if (FBIINIT0_STALL_PCIE_FOR_HWM(reg[fbiInit0].u) &&
3760		fifo_space(&pci.fifo) <= 2 * FBIINIT0_PCI_FIFO_LWM(reg[fbiInit0].u))
	3821	if (FBIINIT0_STALL_PCIE_FOR_HWM(v->reg[fbiInit0].u) &&
	3822	fifo_space(&v->pci.fifo) <= 2 * FBIINIT0_PCI_FIFO_LWM(v->reg[fbiInit0].u))
3761	3823	{
3762		if (LOG_FIFO) logerror("VOODOO.%d.FIFO:voodoo_w hit PCI FIFO free LWM -- stalling\n", index);
3763		stall_cpu(this, STALLED_UNTIL_FIFO_LWM, machine().time());
	3824	if (LOG_FIFO) logerror("VOODOO.%d.FIFO:voodoo_w hit PCI FIFO free LWM -- stalling\n", v->index);
	3825	stall_cpu(v, STALLED_UNTIL_FIFO_LWM, machine().time());
3764	3826	}
3765	3827
3766	3828	/* if we weren't ready, and this is a non-FIFO access, stall until the FIFOs are clear */
3767	3829	if (stall)
3768	3830	{
3769		if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:voodoo_w wrote non-FIFO register -- stalling until clear\n", index);
3770		stall_cpu(this, STALLED_UNTIL_FIFO_EMPTY, machine().time());
	3831	if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:voodoo_w wrote non-FIFO register -- stalling until clear\n", v->index);
	3832	stall_cpu(v, STALLED_UNTIL_FIFO_EMPTY, machine().time());
3771	3833	}
3772	3834
3773	3835	g_profiler.stop();
r253151	r253152
3781	3843	*
3782	3844	*************************************/
3783	3845
3784		static UINT32 register_r(voodoo_de~~vice~~ *vd, offs_t offset)
	3846	static UINT32 register_r(voodoo_state *v, offs_t offset)
3785	3847	{
3786
3787	3848	int regnum = offset & 0xff;
3788	3849	UINT32 result;
3789	3850
3790	3851	/* statistics */
3791		vd->stats.reg_reads++;
	3852	v->stats.reg_reads++;
3792	3853
3793	3854	/* first make sure this register is readable */
3794		if (!(vd->regaccess[regnum] & REGISTER_READ))
	3855	if (!(v->regaccess[regnum] & REGISTER_READ))
3795	3856	{
3796		vd->device->logerror("VOODOO.%d.ERROR:Invalid attempt to read %s\n", vd->index, regnum < 225 ? vd->regnames[regnum] : "unknown register");
	3857	v->device->logerror("VOODOO.%d.ERROR:Invalid attempt to read %s\n", v->index, regnum < 225 ? v->regnames[regnum] : "unknown register");
3797	3858	return 0xffffffff;
3798	3859	}
3799	3860
3800	3861	/* default result is the FBI register value */
3801		result = vd->reg[regnum].u;
	3862	result = v->reg[regnum].u;
3802	3863
3803	3864	/* some registers are dynamic; compute them */
3804	3865	switch (regnum)
3805	3866	{
3806		case vdstatus:
	3867	case status:
3807	3868
3808	3869	/* start with a blank slate */
3809	3870	result = 0;
3810	3871
3811	3872	/* bits 5:0 are the PCI FIFO free space */
3812		if (fifo_empty(&vd->pci.fifo))
	3873	if (fifo_empty(&v->pci.fifo))
3813	3874	result \|= 0x3f << 0;
3814	3875	else
3815	3876	{
3816		int temp = fifo_space(&vd->pci.fifo)/2;
	3877	int temp = fifo_space(&v->pci.fifo)/2;
3817	3878	if (temp > 0x3f)
3818	3879	temp = 0x3f;
3819	3880	result \|= temp << 0;
3820	3881	}
3821	3882
3822	3883	/* bit 6 is the vertical retrace */
3823		result \|= vd->fbi.vblank << 6;
	3884	result \|= v->fbi.vblank << 6;
3824	3885
3825	3886	/* bit 7 is FBI graphics engine busy */
3826		if (vd->pci.op_pending)
	3887	if (v->pci.op_pending)
3827	3888	result \|= 1 << 7;
3828	3889
3829	3890	/* bit 8 is TREX busy */
3830		if (vd->pci.op_pending)
	3891	if (v->pci.op_pending)
3831	3892	result \|= 1 << 8;
3832	3893
3833	3894	/* bit 9 is overall busy */
3834		if (vd->pci.op_pending)
	3895	if (v->pci.op_pending)
3835	3896	result \|= 1 << 9;
3836	3897
3837	3898	/* Banshee is different starting here */
3838		if (vd->~~vd_~~type < TYPE_VOODOO_BANSHEE)
	3899	if (v->type < TYPE_VOODOO_BANSHEE)
3839	3900	{
3840	3901	/* bits 11:10 specifies which buffer is visible */
3841		result \|= vd->fbi.frontbuf << 10;
	3902	result \|= v->fbi.frontbuf << 10;
3842	3903
3843	3904	/* bits 27:12 indicate memory FIFO freespace */
3844		if (!FBIINIT0_ENABLE_MEMORY_FIFO(vd->reg[fbiInit0].u) \|\| fifo_empty(&vd->fbi.fifo))
	3905	if (!FBIINIT0_ENABLE_MEMORY_FIFO(v->reg[fbiInit0].u) \|\| fifo_empty(&v->fbi.fifo))
3845	3906	result \|= 0xffff << 12;
3846	3907	else
3847	3908	{
3848		int temp = fifo_space(&vd->fbi.fifo)/2;
	3909	int temp = fifo_space(&v->fbi.fifo)/2;
3849	3910	if (temp > 0xffff)
3850	3911	temp = 0xffff;
3851	3912	result \|= temp << 12;
r253151	r253152
3856	3917	/* bit 10 is 2D busy */
3857	3918
3858	3919	/* bit 11 is cmd FIFO 0 busy */
3859		if (vd->fbi.cmdfifo[0].enable && vd->fbi.cmdfifo[0].depth > 0)
	3920	if (v->fbi.cmdfifo[0].enable && v->fbi.cmdfifo[0].depth > 0)
3860	3921	result \|= 1 << 11;
3861	3922
3862	3923	/* bit 12 is cmd FIFO 1 busy */
3863		if (vd->fbi.cmdfifo[1].enable && vd->fbi.cmdfifo[1].depth > 0)
	3924	if (v->fbi.cmdfifo[1].enable && v->fbi.cmdfifo[1].depth > 0)
3864	3925	result \|= 1 << 12;
3865	3926	}
3866	3927
3867	3928	/* bits 30:28 are the number of pending swaps */
3868		if (vd->fbi.swaps_pending > 7)
	3929	if (v->fbi.swaps_pending > 7)
3869	3930	result \|= 7 << 28;
3870	3931	else
3871		result \|= vd->fbi.swaps_pending << 28;
	3932	result \|= v->fbi.swaps_pending << 28;
3872	3933
3873	3934	/* bit 31 is not used */
3874	3935
3875	3936	/* eat some cycles since people like polling here */
3876		if (EAT_CYCLES) vd->cpu->execute().eat_cycles(1000);
	3937	if (EAT_CYCLES) v->cpu->execute().eat_cycles(1000);
3877	3938	break;
3878	3939
3879	3940	/* bit 2 of the initEnable register maps this to dacRead */
3880	3941	case fbiInit2:
3881		if (INITEN_REMAP_INIT_TO_DAC(vd->pci.init_enable))
3882		result = vd->dac.read_result;
	3942	if (INITEN_REMAP_INIT_TO_DAC(v->pci.init_enable))
	3943	result = v->dac.read_result;
3883	3944	break;
3884	3945
3885	3946	/* return the current scanline for now */
3886	3947	case vRetrace:
3887	3948
3888	3949	/* eat some cycles since people like polling here */
3889		if (EAT_CYCLES) vd->cpu->execute().eat_cycles(10);
3890		result = vd->screen->vpos();
	3950	if (EAT_CYCLES) v->cpu->execute().eat_cycles(10);
	3951	result = v->screen->vpos();
3891	3952	break;
3892	3953
3893	3954	/* reserved area in the TMU read by the Vegas startup sequence */
r253151	r253152
3898	3959
3899	3960	/* cmdFifo -- Voodoo2 only */
3900	3961	case cmdFifoRdPtr:
3901		result = vd->fbi.cmdfifo[0].rdptr;
	3962	result = v->fbi.cmdfifo[0].rdptr;
3902	3963
3903	3964	/* eat some cycles since people like polling here */
3904		if (EAT_CYCLES) vd->cpu->execute().eat_cycles(1000);
	3965	if (EAT_CYCLES) v->cpu->execute().eat_cycles(1000);
3905	3966	break;
3906	3967
3907	3968	case cmdFifoAMin:
3908		result = vd->fbi.cmdfifo[0].amin;
	3969	result = v->fbi.cmdfifo[0].amin;
3909	3970	break;
3910	3971
3911	3972	case cmdFifoAMax:
3912		result = vd->fbi.cmdfifo[0].amax;
	3973	result = v->fbi.cmdfifo[0].amax;
3913	3974	break;
3914	3975
3915	3976	case cmdFifoDepth:
3916		result = vd->fbi.cmdfifo[0].depth;
	3977	result = v->fbi.cmdfifo[0].depth;
3917	3978	break;
3918	3979
3919	3980	case cmdFifoHoles:
3920		result = vd->fbi.cmdfifo[0].holes;
	3981	result = v->fbi.cmdfifo[0].holes;
3921	3982	break;
3922	3983
3923	3984	/* all counters are 24-bit only */
r253151	r253152
3926	3987	case fbiZfuncFail:
3927	3988	case fbiAfuncFail:
3928	3989	case fbiPixelsOut:
3929		update_statistics(vd, TRUE);
	3990	update_statistics(v, TRUE);
3930	3991	case fbiTrianglesOut:
3931		result = vd->reg[regnum].u & 0xffffff;
	3992	result = v->reg[regnum].u & 0xffffff;
3932	3993	break;
3933	3994	}
3934	3995
r253151	r253152
3937	3998	int logit = TRUE;
3938	3999
3939	4000	/* don't log multiple identical status reads from the same address */
3940		if (regnum == vdstatus)
	4001	if (regnum == status)
3941	4002	{
3942		offs_t pc = vd->cpu->safe_pc();
3943		if (pc == vd->last_status_pc && result == vd->last_status_value)
	4003	offs_t pc = v->cpu->safe_pc();
	4004	if (pc == v->last_status_pc && result == v->last_status_value)
3944	4005	logit = FALSE;
3945		vd->last_status_pc = pc;
3946		vd->last_status_value = result;
	4006	v->last_status_pc = pc;
	4007	v->last_status_value = result;
3947	4008	}
3948	4009	if (regnum == cmdFifoRdPtr)
3949	4010	logit = FALSE;
3950	4011
3951	4012	if (logit)
3952		vd->device->logerror("VOODOO.%d.REG:%s read = %08X\n", vd->index, vd->regnames[regnum], result);
	4013	v->device->logerror("VOODOO.%d.REG:%s read = %08X\n", v->index, v->regnames[regnum], result);
3953	4014	}
3954	4015
3955	4016	return result;
r253151	r253152
3963	4024	*
3964	4025	*************************************/
3965	4026
3966		static UINT32 lfb_r(voodoo_de~~vice~~ *vd, offs_t offset, bool lfb_3d)
	4027	static UINT32 lfb_r(voodoo_state *v, offs_t offset, bool lfb_3d)
3967	4028	{
3968	4029	UINT16 *buffer;
3969	4030	UINT32 bufmax;
r253151	r253152
3972	4033	int x, y, scry, destbuf;
3973	4034
3974	4035	/* statistics */
3975		vd->stats.lfb_reads++;
	4036	v->stats.lfb_reads++;
3976	4037
3977	4038	/* compute X,Y */
3978	4039	offset <<= 1;
3979		x = offset & ((1 << vd->fbi.lfb_stride) - 1);
3980		y = (offset >> vd->fbi.lfb_stride);
	4040	x = offset & ((1 << v->fbi.lfb_stride) - 1);
	4041	y = (offset >> v->fbi.lfb_stride);
3981	4042
3982	4043	/* select the target buffer */
3983	4044	if (lfb_3d) {
3984	4045	y &= 0x3ff;
3985		destbuf = (vd->~~vd_~~type >= TYPE_VOODOO_BANSHEE) ? 1 : LFBMODE_READ_BUFFER_SELECT(vd->reg[lfbMode].u);
	4046	destbuf = (v->type >= TYPE_VOODOO_BANSHEE) ? 1 : LFBMODE_READ_BUFFER_SELECT(v->reg[lfbMode].u);
3986	4047	switch (destbuf)
3987	4048	{
3988	4049	case 0: /* front buffer */
3989		buffer = (UINT16 *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.frontbuf]);
3990		bufmax = (vd->fbi.mask + 1 - vd->fbi.rgboffs[vd->fbi.frontbuf]) / 2;
	4050	buffer = (UINT16 *)(v->fbi.ram + v->fbi.rgboffs[v->fbi.frontbuf]);
	4051	bufmax = (v->fbi.mask + 1 - v->fbi.rgboffs[v->fbi.frontbuf]) / 2;
3991	4052	break;
3992	4053
3993	4054	case 1: /* back buffer */
3994		buffer = (UINT16 *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.backbuf]);
3995		bufmax = (vd->fbi.mask + 1 - vd->fbi.rgboffs[vd->fbi.backbuf]) / 2;
	4055	buffer = (UINT16 *)(v->fbi.ram + v->fbi.rgboffs[v->fbi.backbuf]);
	4056	bufmax = (v->fbi.mask + 1 - v->fbi.rgboffs[v->fbi.backbuf]) / 2;
3996	4057	break;
3997	4058
3998	4059	case 2: /* aux buffer */
3999		if (vd->fbi.auxoffs == ~0)
	4060	if (v->fbi.auxoffs == ~0)
4000	4061	return 0xffffffff;
4001		buffer = (UINT16 *)(vd->fbi.ram + vd->fbi.auxoffs);
4002		bufmax = (vd->fbi.mask + 1 - vd->fbi.auxoffs) / 2;
	4062	buffer = (UINT16 *)(v->fbi.ram + v->fbi.auxoffs);
	4063	bufmax = (v->fbi.mask + 1 - v->fbi.auxoffs) / 2;
4003	4064	break;
4004	4065
4005	4066	default: /* reserved */
r253151	r253152
4008	4069
4009	4070	/* determine the screen Y */
4010	4071	scry = y;
4011		if (LFBMODE_Y_ORIGIN(vd->reg[lfbMode].u))
4012		scry = (vd->fbi.yorigin - y) & 0x3ff;
	4072	if (LFBMODE_Y_ORIGIN(v->reg[lfbMode].u))
	4073	scry = (v->fbi.yorigin - y) & 0x3ff;
4013	4074	} else {
4014	4075	// Direct lfb access
4015		buffer = (UINT16 )(vd->fbi.ram + vd->fbi.lfb_base4);
4016		bufmax = (vd->fbi.mask + 1 - vd->fbi.lfb_base*4) / 2;
	4076	buffer = (UINT16 )(v->fbi.ram + v->fbi.lfb_base4);
	4077	bufmax = (v->fbi.mask + 1 - v->fbi.lfb_base*4) / 2;
4017	4078	scry = y;
4018	4079	}
4019	4080
4020	4081	/* advance pointers to the proper row */
4021		bufoffs = scry * vd->fbi.rowpixels + x;
	4082	bufoffs = scry * v->fbi.rowpixels + x;
4022	4083	if (bufoffs >= bufmax) {
4023		vd->device->logerror("LFB_R: Buffer offset out of bounds x=%i y=%i lfb_3d=%i offset=%08X bufoffs=%08X\n", x, y, lfb_3d, offset, (UINT32) bufoffs);
	4084	v->device->logerror("LFB_R: Buffer offset out of bounds x=%i y=%i lfb_3d=%i offset=%08X bufoffs=%08X\n", x, y, lfb_3d, offset, (UINT32) bufoffs);
4024	4085	return 0xffffffff;
4025	4086	}
4026	4087
4027	4088	/* wait for any outstanding work to finish */
4028		poly_wait(vd->poly, "LFB read");
	4089	poly_wait(v->poly, "LFB read");
4029	4090
4030	4091	/* compute the data */
4031	4092	data = buffer[bufoffs + 0] \| (buffer[bufoffs + 1] << 16);
4032	4093
4033	4094	/* word swapping */
4034		if (LFBMODE_WORD_SWAP_READS(vd->reg[lfbMode].u))
	4095	if (LFBMODE_WORD_SWAP_READS(v->reg[lfbMode].u))
4035	4096	data = (data << 16) \| (data >> 16);
4036	4097
4037	4098	/* byte swizzling */
4038		if (LFBMODE_BYTE_SWIZZLE_READS(vd->reg[lfbMode].u))
	4099	if (LFBMODE_BYTE_SWIZZLE_READS(v->reg[lfbMode].u))
4039	4100	data = FLIPENDIAN_INT32(data);
4040	4101
4041		if (LOG_LFB) vd->device->logerror("VOODOO.%d.LFB:read (%d,%d) = %08X\n", vd->index, x, y, data);
	4102	if (LOG_LFB) v->device->logerror("VOODOO.%d.LFB:read (%d,%d) = %08X\n", v->index, x, y, data);
4042	4103	return data;
4043	4104	}
4044	4105
r253151	r253152
4053	4114
4054	4115	READ32_MEMBER( voodoo_device::voodoo_r )
4055	4116	{
	4117	voodoo_state *v = get_safe_token(this);
4056	4118
4057	4119	/* if we have something pending, flush the FIFOs up to the current time */
4058		if (pci.op_pending)
4059		flush_fifos(this, machine().time());
	4120	if (v->pci.op_pending)
	4121	flush_fifos(v, machine().time());
4060	4122
4061	4123	/* target the appropriate location */
4062	4124	if (!(offset & (0xc00000/4)))
4063		return register_r(~~this~~, offset);
	4125	return register_r(v, offset);
4064	4126	else if (!(offset & (0x800000/4)))
4065		return lfb_r(~~this~~, offset, true);
	4127	return lfb_r(v, offset, true);
4066	4128
4067	4129	return 0xffffffff;
4068	4130	}
r253151	r253152
4078	4140
4079	4141	READ32_MEMBER( voodoo_banshee_device::banshee_agp_r )
4080	4142	{
	4143	voodoo_state *v = get_safe_token(this);
4081	4144	UINT32 result;
4082	4145
4083	4146	offset &= 0x1ff/4;
r253151	r253152
4086	4149	switch (offset)
4087	4150	{
4088	4151	case cmdRdPtrL0:
4089		result = fbi.cmdfifo[0].rdptr;
	4152	result = v->fbi.cmdfifo[0].rdptr;
4090	4153	break;
4091	4154
4092	4155	case cmdAMin0:
4093		result = fbi.cmdfifo[0].amin;
	4156	result = v->fbi.cmdfifo[0].amin;
4094	4157	break;
4095	4158
4096	4159	case cmdAMax0:
4097		result = fbi.cmdfifo[0].amax;
	4160	result = v->fbi.cmdfifo[0].amax;
4098	4161	break;
4099	4162
4100	4163	case cmdFifoDepth0:
4101		result = fbi.cmdfifo[0].depth;
	4164	result = v->fbi.cmdfifo[0].depth;
4102	4165	break;
4103	4166
4104	4167	case cmdHoleCnt0:
4105		result = fbi.cmdfifo[0].holes;
	4168	result = v->fbi.cmdfifo[0].holes;
4106	4169	break;
4107	4170
4108	4171	case cmdRdPtrL1:
4109		result = fbi.cmdfifo[1].rdptr;
	4172	result = v->fbi.cmdfifo[1].rdptr;
4110	4173	break;
4111	4174
4112	4175	case cmdAMin1:
4113		result = fbi.cmdfifo[1].amin;
	4176	result = v->fbi.cmdfifo[1].amin;
4114	4177	break;
4115	4178
4116	4179	case cmdAMax1:
4117		result = fbi.cmdfifo[1].amax;
	4180	result = v->fbi.cmdfifo[1].amax;
4118	4181	break;
4119	4182
4120	4183	case cmdFifoDepth1:
4121		result = fbi.cmdfifo[1].depth;
	4184	result = v->fbi.cmdfifo[1].depth;
4122	4185	break;
4123	4186
4124	4187	case cmdHoleCnt1:
4125		result = fbi.cmdfifo[1].holes;
	4188	result = v->fbi.cmdfifo[1].holes;
4126	4189	break;
4127	4190
4128	4191	default:
4129		result = banshee.agp[offset];
	4192	result = v->banshee.agp[offset];
4130	4193	break;
4131	4194	}
4132	4195
4133	4196	if (LOG_REGISTERS)
4134		logerror("%s:banshee_r(AGP:%s)\n", device->machine().describe_context(), banshee_agp_reg_name[offset]);
	4197	logerror("%s:banshee_r(AGP:%s)\n", v->device->machine().describe_context(), banshee_agp_reg_name[offset]);
4135	4198	return result;
4136	4199	}
4137	4200
4138	4201
4139	4202	READ32_MEMBER( voodoo_banshee_device::banshee_r )
4140	4203	{
	4204	voodoo_state *v = get_safe_token(this);
4141	4205	UINT32 result = 0xffffffff;
4142	4206
4143	4207	/* if we have something pending, flush the FIFOs up to the current time */
4144		if (pci.op_pending)
4145		flush_fifos(this, machine().time());
	4208	if (v->pci.op_pending)
	4209	flush_fifos(v, machine().time());
4146	4210
4147	4211	if (offset < 0x80000/4)
4148	4212	result = banshee_io_r(space, offset, mem_mask);
r253151	r253152
4151	4215	else if (offset < 0x200000/4)
4152	4216	logerror("%s:banshee_r(2D:%X)\n", machine().describe_context(), (offset*4) & 0xfffff);
4153	4217	else if (offset < 0x600000/4)
4154		result = register_r(~~this~~, offset & 0x1fffff/4);
	4218	result = register_r(v, offset & 0x1fffff/4);
4155	4219	else if (offset < 0x800000/4)
4156	4220	logerror("%s:banshee_r(TEX0:%X)\n", machine().describe_context(), (offset*4) & 0x1fffff);
4157	4221	else if (offset < 0xa00000/4)
r253151	r253152
4162	4226	logerror("%s:banshee_r(YUV:%X)\n", machine().describe_context(), (offset*4) & 0x3fffff);
4163	4227	else if (offset < 0x2000000/4)
4164	4228	{
4165		result = lfb_r(~~this~~, offset & 0xffffff/4, true);
	4229	result = lfb_r(v, offset & 0xffffff/4, true);
4166	4230	} else {
4167	4231	logerror("%s:banshee_r(%X) Access out of bounds\n", machine().describe_context(), offset*4);
4168	4232	}
r253151	r253152
4172	4236
4173	4237	READ32_MEMBER( voodoo_banshee_device::banshee_fb_r )
4174	4238	{
	4239	voodoo_state *v = get_safe_token(this);
4175	4240	UINT32 result = 0xffffffff;
4176	4241
4177	4242	/* if we have something pending, flush the FIFOs up to the current time */
4178		if (pci.op_pending)
4179		flush_fifos(this, machine().time());
	4243	if (v->pci.op_pending)
	4244	flush_fifos(v, machine().time());
4180	4245
4181		if (offset < fbi.lfb_base)
	4246	if (offset < v->fbi.lfb_base)
4182	4247	{
4183	4248	#if LOG_LFB
4184	4249	logerror("%s:banshee_fb_r(%X)\n", machine().describe_context(), offset*4);
4185	4250	#endif
4186		if (offset*4 <= fbi.mask)
4187		result = ((UINT32 *)fbi.ram)[offset];
	4251	if (offset*4 <= v->fbi.mask)
	4252	result = ((UINT32 *)v->fbi.ram)[offset];
4188	4253	else
4189	4254	logerror("%s:banshee_fb_r(%X) Access out of bounds\n", machine().describe_context(), offset*4);
4190	4255	}
4191	4256	else {
4192	4257	if (LOG_LFB)
4193		logerror("%s:banshee_fb_r(%X) to lfb_r: %08X lfb_base=%08X\n", machine().describe_context(), offset*4, offset - fbi.lfb_base, fbi.lfb_base);
4194		result = lfb_r(this, offset - fbi.lfb_base, false);
	4258	logerror("%s:banshee_fb_r(%X) to lfb_r: %08X lfb_base=%08X\n", machine().describe_context(), offset*4, offset - v->fbi.lfb_base, v->fbi.lfb_base);
	4259	result = lfb_r(v, offset - v->fbi.lfb_base, false);
4195	4260	}
4196	4261	return result;
4197	4262	}
r253151	r253152
4199	4264
4200	4265	READ8_MEMBER( voodoo_banshee_device::banshee_vga_r )
4201	4266	{
	4267	voodoo_state *v = get_safe_token(this);
4202	4268	UINT8 result = 0xff;
4203	4269
4204	4270	offset &= 0x1f;
r253151	r253152
4208	4274	{
4209	4275	/* attribute access */
4210	4276	case 0x3c0:
4211		if (banshee.vga[0x3c1 & 0x1f] < ARRAY_LENGTH(banshee.att))
4212		result = banshee.att[banshee.vga[0x3c1 & 0x1f]];
	4277	if (v->banshee.vga[0x3c1 & 0x1f] < ARRAY_LENGTH(v->banshee.att))
	4278	result = v->banshee.att[v->banshee.vga[0x3c1 & 0x1f]];
4213	4279	if (LOG_REGISTERS)
4214		logerror("%s:banshee_att_r(%X)\n", machine().describe_context(), banshee.vga[0x3c1 & 0x1f]);
	4280	logerror("%s:banshee_att_r(%X)\n", machine().describe_context(), v->banshee.vga[0x3c1 & 0x1f]);
4215	4281	break;
4216	4282
4217	4283	/* Input status 0 */
r253151	r253152
4229	4295
4230	4296	/* Sequencer access */
4231	4297	case 0x3c5:
4232		if (banshee.vga[0x3c4 & 0x1f] < ARRAY_LENGTH(banshee.seq))
4233		result = banshee.seq[banshee.vga[0x3c4 & 0x1f]];
	4298	if (v->banshee.vga[0x3c4 & 0x1f] < ARRAY_LENGTH(v->banshee.seq))
	4299	result = v->banshee.seq[v->banshee.vga[0x3c4 & 0x1f]];
4234	4300	if (LOG_REGISTERS)
4235		logerror("%s:banshee_seq_r(%X)\n", machine().describe_context(), banshee.vga[0x3c4 & 0x1f]);
	4301	logerror("%s:banshee_seq_r(%X)\n", machine().describe_context(), v->banshee.vga[0x3c4 & 0x1f]);
4236	4302	break;
4237	4303
4238	4304	/* Feature control */
4239	4305	case 0x3ca:
4240		result = banshee.vga[0x3da & 0x1f];
4241		banshee.attff = 0;
	4306	result = v->banshee.vga[0x3da & 0x1f];
	4307	v->banshee.attff = 0;
4242	4308	if (LOG_REGISTERS)
4243	4309	logerror("%s:banshee_vga_r(%X)\n", machine().describe_context(), 0x300+offset);
4244	4310	break;
4245	4311
4246	4312	/* Miscellaneous output */
4247	4313	case 0x3cc:
4248		result = banshee.vga[0x3c2 & 0x1f];
	4314	result = v->banshee.vga[0x3c2 & 0x1f];
4249	4315	if (LOG_REGISTERS)
4250	4316	logerror("%s:banshee_vga_r(%X)\n", machine().describe_context(), 0x300+offset);
4251	4317	break;
4252	4318
4253	4319	/* Graphics controller access */
4254	4320	case 0x3cf:
4255		if (banshee.vga[0x3ce & 0x1f] < ARRAY_LENGTH(banshee.gc))
4256		result = banshee.gc[banshee.vga[0x3ce & 0x1f]];
	4321	if (v->banshee.vga[0x3ce & 0x1f] < ARRAY_LENGTH(v->banshee.gc))
	4322	result = v->banshee.gc[v->banshee.vga[0x3ce & 0x1f]];
4257	4323	if (LOG_REGISTERS)
4258		logerror("%s:banshee_gc_r(%X)\n", machine().describe_context(), banshee.vga[0x3ce & 0x1f]);
	4324	logerror("%s:banshee_gc_r(%X)\n", machine().describe_context(), v->banshee.vga[0x3ce & 0x1f]);
4259	4325	break;
4260	4326
4261	4327	/* CRTC access */
4262	4328	case 0x3d5:
4263		if (banshee.vga[0x3d4 & 0x1f] < ARRAY_LENGTH(banshee.crtc))
4264		result = banshee.crtc[banshee.vga[0x3d4 & 0x1f]];
	4329	if (v->banshee.vga[0x3d4 & 0x1f] < ARRAY_LENGTH(v->banshee.crtc))
	4330	result = v->banshee.crtc[v->banshee.vga[0x3d4 & 0x1f]];
4265	4331	if (LOG_REGISTERS)
4266		logerror("%s:banshee_crtc_r(%X)\n", machine().describe_context(), banshee.vga[0x3d4 & 0x1f]);
	4332	logerror("%s:banshee_crtc_r(%X)\n", machine().describe_context(), v->banshee.vga[0x3d4 & 0x1f]);
4267	4333	break;
4268	4334
4269	4335	/* Input status 1 */
r253151	r253152
4283	4349	break;
4284	4350
4285	4351	default:
4286		result = banshee.vga[offset];
	4352	result = v->banshee.vga[offset];
4287	4353	if (LOG_REGISTERS)
4288	4354	logerror("%s:banshee_vga_r(%X)\n", machine().describe_context(), 0x300+offset);
4289	4355	break;
r253151	r253152
4294	4360
4295	4361	READ32_MEMBER( voodoo_banshee_device::banshee_io_r )
4296	4362	{
	4363	voodoo_state *v = get_safe_token(this);
4297	4364	UINT32 result;
4298	4365
4299	4366	offset &= 0xff/4;
r253151	r253152
4302	4369	switch (offset)
4303	4370	{
4304	4371	case io_status:
4305		result = register_r(~~this~~, 0);
	4372	result = register_r(v, 0);
4306	4373	break;
4307	4374
4308	4375	case io_dacData:
4309		result = fbi.clut[banshee.io[io_dacAddr] & 0x1ff] = banshee.io[offset];
	4376	result = v->fbi.clut[v->banshee.io[io_dacAddr] & 0x1ff] = v->banshee.io[offset];
4310	4377	if (LOG_REGISTERS)
4311		logerror("%s:banshee_dac_r(%X)\n", machine().describe_context(), banshee.io[io_dacAddr] & 0x1ff);
	4378	logerror("%s:banshee_dac_r(%X)\n", machine().describe_context(), v->banshee.io[io_dacAddr] & 0x1ff);
4312	4379	break;
4313	4380
4314	4381	case io_vgab0: case io_vgab4: case io_vgab8: case io_vgabc:
r253151	r253152
4326	4393	break;
4327	4394
4328	4395	default:
4329		result = banshee.io[offset];
	4396	result = v->banshee.io[offset];
4330	4397	if (LOG_REGISTERS)
4331	4398	logerror("%s:banshee_io_r(%s)\n", machine().describe_context(), banshee_io_reg_name[offset]);
4332	4399	break;
r253151	r253152
4342	4409	return 0xffffffff;
4343	4410	}
4344	4411
4345		static void blit_2d(voodoo_de~~vice~~ *vd, UINT32 data)
	4412	static void blit_2d(voodoo_state *v, UINT32 data)
4346	4413	{
4347		switch (vd->banshee.blt_cmd)
	4414	switch (v->banshee.blt_cmd)
4348	4415	{
4349	4416	case 0: // NOP - wait for idle
4350	4417	{
r253151	r253152
4367	4434
4368	4435	case 3: // Host-to-screen blit
4369	4436	{
4370		UINT32 addr = vd->banshee.blt_dst_base;
	4437	UINT32 addr = v->banshee.blt_dst_base;
4371	4438
4372		addr += (vd->banshee.blt_dst_y * vd->banshee.blt_dst_stride) + (vd->banshee.blt_dst_x * vd->banshee.blt_dst_bpp);
	4439	addr += (v->banshee.blt_dst_y * v->banshee.blt_dst_stride) + (v->banshee.blt_dst_x * v->banshee.blt_dst_bpp);
4373	4440
4374	4441	#if LOG_BANSHEE_2D
4375		logerror(" blit_2d:host_to_screen: %08x -> %08x, %d, %d\n", data, addr, vd->banshee.blt_dst_x, vd->banshee.blt_dst_y);
	4442	logerror(" blit_2d:host_to_screen: %08x -> %08x, %d, %d\n", data, addr, v->banshee.blt_dst_x, v->banshee.blt_dst_y);
4376	4443	#endif
4377	4444
4378		switch (vd->banshee.blt_dst_bpp)
	4445	switch (v->banshee.blt_dst_bpp)
4379	4446	{
4380	4447	case 1:
4381		vd->fbi.ram[addr+0] = data & 0xff;
4382		vd->fbi.ram[addr+1] = (data >> 8) & 0xff;
4383		vd->fbi.ram[addr+2] = (data >> 16) & 0xff;
4384		vd->fbi.ram[addr+3] = (data >> 24) & 0xff;
4385		vd->banshee.blt_dst_x += 4;
	4448	v->fbi.ram[addr+0] = data & 0xff;
	4449	v->fbi.ram[addr+1] = (data >> 8) & 0xff;
	4450	v->fbi.ram[addr+2] = (data >> 16) & 0xff;
	4451	v->fbi.ram[addr+3] = (data >> 24) & 0xff;
	4452	v->banshee.blt_dst_x += 4;
4386	4453	break;
4387	4454	case 2:
4388		vd->fbi.ram[addr+1] = data & 0xff;
4389		vd->fbi.ram[addr+0] = (data >> 8) & 0xff;
4390		vd->fbi.ram[addr+3] = (data >> 16) & 0xff;
4391		vd->fbi.ram[addr+2] = (data >> 24) & 0xff;
4392		vd->banshee.blt_dst_x += 2;
	4455	v->fbi.ram[addr+1] = data & 0xff;
	4456	v->fbi.ram[addr+0] = (data >> 8) & 0xff;
	4457	v->fbi.ram[addr+3] = (data >> 16) & 0xff;
	4458	v->fbi.ram[addr+2] = (data >> 24) & 0xff;
	4459	v->banshee.blt_dst_x += 2;
4393	4460	break;
4394	4461	case 3:
4395		vd->banshee.blt_dst_x += 1;
	4462	v->banshee.blt_dst_x += 1;
4396	4463	break;
4397	4464	case 4:
4398		vd->fbi.ram[addr+3] = data & 0xff;
4399		vd->fbi.ram[addr+2] = (data >> 8) & 0xff;
4400		vd->fbi.ram[addr+1] = (data >> 16) & 0xff;
4401		vd->fbi.ram[addr+0] = (data >> 24) & 0xff;
4402		vd->banshee.blt_dst_x += 1;
	4465	v->fbi.ram[addr+3] = data & 0xff;
	4466	v->fbi.ram[addr+2] = (data >> 8) & 0xff;
	4467	v->fbi.ram[addr+1] = (data >> 16) & 0xff;
	4468	v->fbi.ram[addr+0] = (data >> 24) & 0xff;
	4469	v->banshee.blt_dst_x += 1;
4403	4470	break;
4404	4471	}
4405	4472
4406		if (vd->banshee.blt_dst_x >= vd->banshee.blt_dst_width)
	4473	if (v->banshee.blt_dst_x >= v->banshee.blt_dst_width)
4407	4474	{
4408		vd->banshee.blt_dst_x = 0;
4409		vd->banshee.blt_dst_y++;
	4475	v->banshee.blt_dst_x = 0;
	4476	v->banshee.blt_dst_y++;
4410	4477	}
4411	4478	break;
4412	4479	}
r253151	r253152
4433	4500
4434	4501	default:
4435	4502	{
4436		fatalerror("blit_2d: unknown command %d\n", vd->banshee.blt_cmd);
	4503	fatalerror("blit_2d: unknown command %d\n", v->banshee.blt_cmd);
4437	4504	}
4438	4505	}
4439	4506	}
4440	4507
4441		INT32 ~~voodoo_device::~~banshee_2d_w(voodoo_de~~vice~~ *vd, offs_t offset, UINT32 data)
	4508	static INT32 banshee_2d_w(voodoo_state *v, offs_t offset, UINT32 data)
4442	4509	{
4443	4510	switch (offset)
4444	4511	{
r253151	r253152
4447	4514	logerror(" 2D:command: cmd %d, ROP0 %02X\n", data & 0xf, data >> 24);
4448	4515	#endif
4449	4516
4450		vd->banshee.blt_src_x = vd->banshee.blt_regs[banshee2D_srcXY] & 0xfff;
4451		vd->banshee.blt_src_y = (vd->banshee.blt_regs[banshee2D_srcXY] >> 16) & 0xfff;
4452		vd->banshee.blt_src_base = vd->banshee.blt_regs[banshee2D_srcBaseAddr] & 0xffffff;
4453		vd->banshee.blt_src_stride = vd->banshee.blt_regs[banshee2D_srcFormat] & 0x3fff;
4454		vd->banshee.blt_src_width = vd->banshee.blt_regs[banshee2D_srcSize] & 0xfff;
4455		vd->banshee.blt_src_height = (vd->banshee.blt_regs[banshee2D_srcSize] >> 16) & 0xfff;
	4517	v->banshee.blt_src_x = v->banshee.blt_regs[banshee2D_srcXY] & 0xfff;
	4518	v->banshee.blt_src_y = (v->banshee.blt_regs[banshee2D_srcXY] >> 16) & 0xfff;
	4519	v->banshee.blt_src_base = v->banshee.blt_regs[banshee2D_srcBaseAddr] & 0xffffff;
	4520	v->banshee.blt_src_stride = v->banshee.blt_regs[banshee2D_srcFormat] & 0x3fff;
	4521	v->banshee.blt_src_width = v->banshee.blt_regs[banshee2D_srcSize] & 0xfff;
	4522	v->banshee.blt_src_height = (v->banshee.blt_regs[banshee2D_srcSize] >> 16) & 0xfff;
4456	4523
4457		switch ((vd->banshee.blt_regs[banshee2D_srcFormat] >> 16) & 0xf)
	4524	switch ((v->banshee.blt_regs[banshee2D_srcFormat] >> 16) & 0xf)
4458	4525	{
4459		case 1: vd->banshee.blt_src_bpp = 1; break;
4460		case 3: vd->banshee.blt_src_bpp = 2; break;
4461		case 4: vd->banshee.blt_src_bpp = 3; break;
4462		case 5: vd->banshee.blt_src_bpp = 4; break;
4463		case 8: vd->banshee.blt_src_bpp = 2; break;
4464		case 9: vd->banshee.blt_src_bpp = 2; break;
4465		default: vd->banshee.blt_src_bpp = 1; break;
	4526	case 1: v->banshee.blt_src_bpp = 1; break;
	4527	case 3: v->banshee.blt_src_bpp = 2; break;
	4528	case 4: v->banshee.blt_src_bpp = 3; break;
	4529	case 5: v->banshee.blt_src_bpp = 4; break;
	4530	case 8: v->banshee.blt_src_bpp = 2; break;
	4531	case 9: v->banshee.blt_src_bpp = 2; break;
	4532	default: v->banshee.blt_src_bpp = 1; break;
4466	4533	}
4467	4534
4468		vd->banshee.blt_dst_x = vd->banshee.blt_regs[banshee2D_dstXY] & 0xfff;
4469		vd->banshee.blt_dst_y = (vd->banshee.blt_regs[banshee2D_dstXY] >> 16) & 0xfff;
4470		vd->banshee.blt_dst_base = vd->banshee.blt_regs[banshee2D_dstBaseAddr] & 0xffffff;
4471		vd->banshee.blt_dst_stride = vd->banshee.blt_regs[banshee2D_dstFormat] & 0x3fff;
4472		vd->banshee.blt_dst_width = vd->banshee.blt_regs[banshee2D_dstSize] & 0xfff;
4473		vd->banshee.blt_dst_height = (vd->banshee.blt_regs[banshee2D_dstSize] >> 16) & 0xfff;
	4535	v->banshee.blt_dst_x = v->banshee.blt_regs[banshee2D_dstXY] & 0xfff;
	4536	v->banshee.blt_dst_y = (v->banshee.blt_regs[banshee2D_dstXY] >> 16) & 0xfff;
	4537	v->banshee.blt_dst_base = v->banshee.blt_regs[banshee2D_dstBaseAddr] & 0xffffff;
	4538	v->banshee.blt_dst_stride = v->banshee.blt_regs[banshee2D_dstFormat] & 0x3fff;
	4539	v->banshee.blt_dst_width = v->banshee.blt_regs[banshee2D_dstSize] & 0xfff;
	4540	v->banshee.blt_dst_height = (v->banshee.blt_regs[banshee2D_dstSize] >> 16) & 0xfff;
4474	4541
4475		switch ((vd->banshee.blt_regs[banshee2D_dstFormat] >> 16) & 0x7)
	4542	switch ((v->banshee.blt_regs[banshee2D_dstFormat] >> 16) & 0x7)
4476	4543	{
4477		case 1: vd->banshee.blt_dst_bpp = 1; break;
4478		case 3: vd->banshee.blt_dst_bpp = 2; break;
4479		case 4: vd->banshee.blt_dst_bpp = 3; break;
4480		case 5: vd->banshee.blt_dst_bpp = 4; break;
4481		default: vd->banshee.blt_dst_bpp = 1; break;
	4544	case 1: v->banshee.blt_dst_bpp = 1; break;
	4545	case 3: v->banshee.blt_dst_bpp = 2; break;
	4546	case 4: v->banshee.blt_dst_bpp = 3; break;
	4547	case 5: v->banshee.blt_dst_bpp = 4; break;
	4548	default: v->banshee.blt_dst_bpp = 1; break;
4482	4549	}
4483	4550
4484		vd->banshee.blt_cmd = data & 0xf;
	4551	v->banshee.blt_cmd = data & 0xf;
4485	4552	break;
4486	4553
4487	4554	case banshee2D_colorBack:
4488	4555	#if LOG_BANSHEE_2D
4489	4556	logerror(" 2D:colorBack: %08X\n", data);
4490	4557	#endif
4491		vd->banshee.blt_regs[banshee2D_colorBack] = data;
	4558	v->banshee.blt_regs[banshee2D_colorBack] = data;
4492	4559	break;
4493	4560
4494	4561	case banshee2D_colorFore:
4495	4562	#if LOG_BANSHEE_2D
4496	4563	logerror(" 2D:colorFore: %08X\n", data);
4497	4564	#endif
4498		vd->banshee.blt_regs[banshee2D_colorFore] = data;
	4565	v->banshee.blt_regs[banshee2D_colorFore] = data;
4499	4566	break;
4500	4567
4501	4568	case banshee2D_srcBaseAddr:
4502	4569	#if LOG_BANSHEE_2D
4503	4570	logerror(" 2D:srcBaseAddr: %08X, %s\n", data & 0xffffff, data & 0x80000000 ? "tiled" : "non-tiled");
4504	4571	#endif
4505		vd->banshee.blt_regs[banshee2D_srcBaseAddr] = data;
	4572	v->banshee.blt_regs[banshee2D_srcBaseAddr] = data;
4506	4573	break;
4507	4574
4508	4575	case banshee2D_dstBaseAddr:
4509	4576	#if LOG_BANSHEE_2D
4510	4577	logerror(" 2D:dstBaseAddr: %08X, %s\n", data & 0xffffff, data & 0x80000000 ? "tiled" : "non-tiled");
4511	4578	#endif
4512		vd->banshee.blt_regs[banshee2D_dstBaseAddr] = data;
	4579	v->banshee.blt_regs[banshee2D_dstBaseAddr] = data;
4513	4580	break;
4514	4581
4515	4582	case banshee2D_srcSize:
4516	4583	#if LOG_BANSHEE_2D
4517	4584	logerror(" 2D:srcSize: %d, %d\n", data & 0xfff, (data >> 16) & 0xfff);
4518	4585	#endif
4519		vd->banshee.blt_regs[banshee2D_srcSize] = data;
	4586	v->banshee.blt_regs[banshee2D_srcSize] = data;
4520	4587	break;
4521	4588
4522	4589	case banshee2D_dstSize:
4523	4590	#if LOG_BANSHEE_2D
4524	4591	logerror(" 2D:dstSize: %d, %d\n", data & 0xfff, (data >> 16) & 0xfff);
4525	4592	#endif
4526		vd->banshee.blt_regs[banshee2D_dstSize] = data;
	4593	v->banshee.blt_regs[banshee2D_dstSize] = data;
4527	4594	break;
4528	4595
4529	4596	case banshee2D_srcXY:
4530	4597	#if LOG_BANSHEE_2D
4531	4598	logerror(" 2D:srcXY: %d, %d\n", data & 0xfff, (data >> 16) & 0xfff);
4532	4599	#endif
4533		vd->banshee.blt_regs[banshee2D_srcXY] = data;
	4600	v->banshee.blt_regs[banshee2D_srcXY] = data;
4534	4601	break;
4535	4602
4536	4603	case banshee2D_dstXY:
4537	4604	#if LOG_BANSHEE_2D
4538	4605	logerror(" 2D:dstXY: %d, %d\n", data & 0xfff, (data >> 16) & 0xfff);
4539	4606	#endif
4540		vd->banshee.blt_regs[banshee2D_dstXY] = data;
	4607	v->banshee.blt_regs[banshee2D_dstXY] = data;
4541	4608	break;
4542	4609
4543	4610	case banshee2D_srcFormat:
4544	4611	#if LOG_BANSHEE_2D
4545	4612	logerror(" 2D:srcFormat: str %d, fmt %d, packing %d\n", data & 0x3fff, (data >> 16) & 0xf, (data >> 22) & 0x3);
4546	4613	#endif
4547		vd->banshee.blt_regs[banshee2D_srcFormat] = data;
	4614	v->banshee.blt_regs[banshee2D_srcFormat] = data;
4548	4615	break;
4549	4616
4550	4617	case banshee2D_dstFormat:
4551	4618	#if LOG_BANSHEE_2D
4552	4619	logerror(" 2D:dstFormat: str %d, fmt %d\n", data & 0x3fff, (data >> 16) & 0xf);
4553	4620	#endif
4554		vd->banshee.blt_regs[banshee2D_dstFormat] = data;
	4621	v->banshee.blt_regs[banshee2D_dstFormat] = data;
4555	4622	break;
4556	4623
4557	4624	case banshee2D_clip0Min:
4558	4625	#if LOG_BANSHEE_2D
4559	4626	logerror(" 2D:clip0Min: %d, %d\n", data & 0xfff, (data >> 16) & 0xfff);
4560	4627	#endif
4561		vd->banshee.blt_regs[banshee2D_clip0Min] = data;
	4628	v->banshee.blt_regs[banshee2D_clip0Min] = data;
4562	4629	break;
4563	4630
4564	4631	case banshee2D_clip0Max:
4565	4632	#if LOG_BANSHEE_2D
4566	4633	logerror(" 2D:clip0Max: %d, %d\n", data & 0xfff, (data >> 16) & 0xfff);
4567	4634	#endif
4568		vd->banshee.blt_regs[banshee2D_clip0Max] = data;
	4635	v->banshee.blt_regs[banshee2D_clip0Max] = data;
4569	4636	break;
4570	4637
4571	4638	case banshee2D_clip1Min:
4572	4639	#if LOG_BANSHEE_2D
4573	4640	logerror(" 2D:clip1Min: %d, %d\n", data & 0xfff, (data >> 16) & 0xfff);
4574	4641	#endif
4575		vd->banshee.blt_regs[banshee2D_clip1Min] = data;
	4642	v->banshee.blt_regs[banshee2D_clip1Min] = data;
4576	4643	break;
4577	4644
4578	4645	case banshee2D_clip1Max:
4579	4646	#if LOG_BANSHEE_2D
4580	4647	logerror(" 2D:clip1Max: %d, %d\n", data & 0xfff, (data >> 16) & 0xfff);
4581	4648	#endif
4582		vd->banshee.blt_regs[banshee2D_clip1Max] = data;
	4649	v->banshee.blt_regs[banshee2D_clip1Max] = data;
4583	4650	break;
4584	4651
4585	4652	case banshee2D_rop:
4586	4653	#if LOG_BANSHEE_2D
4587	4654	logerror(" 2D:rop: %d, %d, %d\n", data & 0xff, (data >> 8) & 0xff, (data >> 16) & 0xff);
4588	4655	#endif
4589		vd->banshee.blt_regs[banshee2D_rop] = data;
	4656	v->banshee.blt_regs[banshee2D_rop] = data;
4590	4657	break;
4591	4658
4592	4659	default:
4593	4660	if (offset >= 0x20 && offset < 0x40)
4594	4661	{
4595		blit_2d(vd, data);
	4662	blit_2d(v, data);
4596	4663	}
4597	4664	else if (offset >= 0x40 && offset < 0x80)
4598	4665	{
r253151	r253152
4610	4677
4611	4678	WRITE32_MEMBER( voodoo_banshee_device::banshee_agp_w )
4612	4679	{
	4680	voodoo_state *v = get_safe_token(this);
4613	4681	offset &= 0x1ff/4;
4614	4682
4615	4683	/* switch off the offset */
4616	4684	switch (offset)
4617	4685	{
4618	4686	case cmdBaseAddr0:
4619		COMBINE_DATA(&banshee.agp[offset]);
4620		fbi.cmdfifo[0].base = (data & 0xffffff) << 12;
4621		fbi.cmdfifo[0].end = fbi.cmdfifo[0].base + (((banshee.agp[cmdBaseSize0] & 0xff) + 1) << 12);
	4687	COMBINE_DATA(&v->banshee.agp[offset]);
	4688	v->fbi.cmdfifo[0].base = (data & 0xffffff) << 12;
	4689	v->fbi.cmdfifo[0].end = v->fbi.cmdfifo[0].base + (((v->banshee.agp[cmdBaseSize0] & 0xff) + 1) << 12);
4622	4690	break;
4623	4691
4624	4692	case cmdBaseSize0:
4625		COMBINE_DATA(&banshee.agp[offset]);
4626		fbi.cmdfifo[0].end = fbi.cmdfifo[0].base + (((banshee.agp[cmdBaseSize0] & 0xff) + 1) << 12);
4627		fbi.cmdfifo[0].enable = (data >> 8) & 1;
4628		fbi.cmdfifo[0].count_holes = (~data >> 10) & 1;
	4693	COMBINE_DATA(&v->banshee.agp[offset]);
	4694	v->fbi.cmdfifo[0].end = v->fbi.cmdfifo[0].base + (((v->banshee.agp[cmdBaseSize0] & 0xff) + 1) << 12);
	4695	v->fbi.cmdfifo[0].enable = (data >> 8) & 1;
	4696	v->fbi.cmdfifo[0].count_holes = (~data >> 10) & 1;
4629	4697	break;
4630	4698
4631	4699	case cmdBump0:
4632	4700	fatalerror("cmdBump0\n");
4633	4701
4634	4702	case cmdRdPtrL0:
4635		fbi.cmdfifo[0].rdptr = data;
	4703	v->fbi.cmdfifo[0].rdptr = data;
4636	4704	break;
4637	4705
4638	4706	case cmdAMin0:
4639		fbi.cmdfifo[0].amin = data;
	4707	v->fbi.cmdfifo[0].amin = data;
4640	4708	break;
4641	4709
4642	4710	case cmdAMax0:
4643		fbi.cmdfifo[0].amax = data;
	4711	v->fbi.cmdfifo[0].amax = data;
4644	4712	break;
4645	4713
4646	4714	case cmdFifoDepth0:
4647		fbi.cmdfifo[0].depth = data;
	4715	v->fbi.cmdfifo[0].depth = data;
4648	4716	break;
4649	4717
4650	4718	case cmdHoleCnt0:
4651		fbi.cmdfifo[0].holes = data;
	4719	v->fbi.cmdfifo[0].holes = data;
4652	4720	break;
4653	4721
4654	4722	case cmdBaseAddr1:
4655		COMBINE_DATA(&banshee.agp[offset]);
4656		fbi.cmdfifo[1].base = (data & 0xffffff) << 12;
4657		fbi.cmdfifo[1].end = fbi.cmdfifo[1].base + (((banshee.agp[cmdBaseSize1] & 0xff) + 1) << 12);
	4723	COMBINE_DATA(&v->banshee.agp[offset]);
	4724	v->fbi.cmdfifo[1].base = (data & 0xffffff) << 12;
	4725	v->fbi.cmdfifo[1].end = v->fbi.cmdfifo[1].base + (((v->banshee.agp[cmdBaseSize1] & 0xff) + 1) << 12);
4658	4726	break;
4659	4727
4660	4728	case cmdBaseSize1:
4661		COMBINE_DATA(&banshee.agp[offset]);
4662		fbi.cmdfifo[1].end = fbi.cmdfifo[1].base + (((banshee.agp[cmdBaseSize1] & 0xff) + 1) << 12);
4663		fbi.cmdfifo[1].enable = (data >> 8) & 1;
4664		fbi.cmdfifo[1].count_holes = (~data >> 10) & 1;
	4729	COMBINE_DATA(&v->banshee.agp[offset]);
	4730	v->fbi.cmdfifo[1].end = v->fbi.cmdfifo[1].base + (((v->banshee.agp[cmdBaseSize1] & 0xff) + 1) << 12);
	4731	v->fbi.cmdfifo[1].enable = (data >> 8) & 1;
	4732	v->fbi.cmdfifo[1].count_holes = (~data >> 10) & 1;
4665	4733	break;
4666	4734
4667	4735	case cmdBump1:
4668	4736	fatalerror("cmdBump1\n");
4669	4737
4670	4738	case cmdRdPtrL1:
4671		fbi.cmdfifo[1].rdptr = data;
	4739	v->fbi.cmdfifo[1].rdptr = data;
4672	4740	break;
4673	4741
4674	4742	case cmdAMin1:
4675		fbi.cmdfifo[1].amin = data;
	4743	v->fbi.cmdfifo[1].amin = data;
4676	4744	break;
4677	4745
4678	4746	case cmdAMax1:
4679		fbi.cmdfifo[1].amax = data;
	4747	v->fbi.cmdfifo[1].amax = data;
4680	4748	break;
4681	4749
4682	4750	case cmdFifoDepth1:
4683		fbi.cmdfifo[1].depth = data;
	4751	v->fbi.cmdfifo[1].depth = data;
4684	4752	break;
4685	4753
4686	4754	case cmdHoleCnt1:
4687		fbi.cmdfifo[1].holes = data;
	4755	v->fbi.cmdfifo[1].holes = data;
4688	4756	break;
4689	4757
4690	4758	default:
4691		COMBINE_DATA(&banshee.agp[offset]);
	4759	COMBINE_DATA(&v->banshee.agp[offset]);
4692	4760	break;
4693	4761	}
4694	4762
r253151	r253152
4699	4767
4700	4768	WRITE32_MEMBER( voodoo_banshee_device::banshee_w )
4701	4769	{
	4770	voodoo_state *v = get_safe_token(this);
4702	4771
4703	4772	/* if we have something pending, flush the FIFOs up to the current time */
4704		if (pci.op_pending)
4705		flush_fifos(this, machine().time());
	4773	if (v->pci.op_pending)
	4774	flush_fifos(v, machine().time());
4706	4775
4707	4776	if (offset < 0x80000/4)
4708	4777	banshee_io_w(space, offset, data, mem_mask);
r253151	r253152
4711	4780	else if (offset < 0x200000/4)
4712	4781	logerror("%s:banshee_w(2D:%X) = %08X & %08X\n", machine().describe_context(), (offset*4) & 0xfffff, data, mem_mask);
4713	4782	else if (offset < 0x600000/4)
4714		register_w(~~this~~, offset & 0x1fffff/4, data);
	4783	register_w(v, offset & 0x1fffff/4, data);
4715	4784	else if (offset < 0x800000/4)
4716	4785	logerror("%s:banshee_w(TEX0:%X) = %08X & %08X\n", machine().describe_context(), (offset*4) & 0x1fffff, data, mem_mask);
4717	4786	else if (offset < 0xa00000/4)
r253151	r253152
4722	4791	logerror("%s:banshee_w(YUV:%X) = %08X & %08X\n", machine().describe_context(), (offset*4) & 0x3fffff, data, mem_mask);
4723	4792	else if (offset < 0x2000000/4)
4724	4793	{
4725		lfb_w(~~this~~, offset & 0xffffff/4, data, mem_mask);
	4794	lfb_w(v, offset & 0xffffff/4, data, mem_mask);
4726	4795	} else {
4727	4796	logerror("%s:banshee_w Address out of range %08X = %08X & %08X\n", machine().describe_context(), (offset*4), data, mem_mask);
4728	4797	}
r253151	r253152
4731	4800
4732	4801	WRITE32_MEMBER( voodoo_banshee_device::banshee_fb_w )
4733	4802	{
	4803	voodoo_state *v = get_safe_token(this);
4734	4804	UINT32 addr = offset*4;
4735	4805
4736	4806	/* if we have something pending, flush the FIFOs up to the current time */
4737		if (pci.op_pending)
4738		flush_fifos(this, machine().time());
	4807	if (v->pci.op_pending)
	4808	flush_fifos(v, machine().time());
4739	4809
4740		if (offset < fbi.lfb_base)
	4810	if (offset < v->fbi.lfb_base)
4741	4811	{
4742		if (fbi.cmdfifo[0].enable && addr >= fbi.cmdfifo[0].base && addr < fbi.cmdfifo[0].end)
4743		cmdfifo_w(this, &fbi.cmdfifo[0], (addr - fbi.cmdfifo[0].base) / 4, data);
4744		else if (fbi.cmdfifo[1].enable && addr >= fbi.cmdfifo[1].base && addr < fbi.cmdfifo[1].end)
4745		cmdfifo_w(this, &fbi.cmdfifo[1], (addr - fbi.cmdfifo[1].base) / 4, data);
	4812	if (v->fbi.cmdfifo[0].enable && addr >= v->fbi.cmdfifo[0].base && addr < v->fbi.cmdfifo[0].end)
	4813	cmdfifo_w(v, &v->fbi.cmdfifo[0], (addr - v->fbi.cmdfifo[0].base) / 4, data);
	4814	else if (v->fbi.cmdfifo[1].enable && addr >= v->fbi.cmdfifo[1].base && addr < v->fbi.cmdfifo[1].end)
	4815	cmdfifo_w(v, &v->fbi.cmdfifo[1], (addr - v->fbi.cmdfifo[1].base) / 4, data);
4746	4816	else
4747	4817	{
4748		if (offset*4 <= fbi.mask)
4749		COMBINE_DATA(&((UINT32 *)fbi.ram)[offset]);
	4818	if (offset*4 <= v->fbi.mask)
	4819	COMBINE_DATA(&((UINT32 *)v->fbi.ram)[offset]);
4750	4820	else
4751	4821	logerror("%s:banshee_fb_w Out of bounds (%X) = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
4752	4822	#if LOG_LFB
r253151	r253152
4755	4825	}
4756	4826	}
4757	4827	else
4758		lfb_direct_w(~~this~~, offset - fbi.lfb_base, data, mem_mask);
	4828	lfb_direct_w(v, offset - v->fbi.lfb_base, data, mem_mask);
4759	4829	}
4760	4830
4761	4831
4762	4832	WRITE8_MEMBER( voodoo_banshee_device::banshee_vga_w )
4763	4833	{
	4834	voodoo_state *v = get_safe_token(this);
4764	4835	offset &= 0x1f;
4765	4836
4766	4837	/* switch off the offset */
r253151	r253152
4769	4840	/* attribute access */
4770	4841	case 0x3c0:
4771	4842	case 0x3c1:
4772		if (banshee.attff == 0)
	4843	if (v->banshee.attff == 0)
4773	4844	{
4774		banshee.vga[0x3c1 & 0x1f] = data;
	4845	v->banshee.vga[0x3c1 & 0x1f] = data;
4775	4846	if (LOG_REGISTERS)
4776	4847	logerror("%s:banshee_vga_w(%X) = %02X\n", machine().describe_context(), 0x3c0+offset, data);
4777	4848	}
4778	4849	else
4779	4850	{
4780		if (banshee.vga[0x3c1 & 0x1f] < ARRAY_LENGTH(banshee.att))
4781		banshee.att[banshee.vga[0x3c1 & 0x1f]] = data;
	4851	if (v->banshee.vga[0x3c1 & 0x1f] < ARRAY_LENGTH(v->banshee.att))
	4852	v->banshee.att[v->banshee.vga[0x3c1 & 0x1f]] = data;
4782	4853	if (LOG_REGISTERS)
4783		logerror("%s:banshee_att_w(%X) = %02X\n", machine().describe_context(), banshee.vga[0x3c1 & 0x1f], data);
	4854	logerror("%s:banshee_att_w(%X) = %02X\n", machine().describe_context(), v->banshee.vga[0x3c1 & 0x1f], data);
4784	4855	}
4785		banshee.attff ^= 1;
	4856	v->banshee.attff ^= 1;
4786	4857	break;
4787	4858
4788	4859	/* Sequencer access */
4789	4860	case 0x3c5:
4790		if (banshee.vga[0x3c4 & 0x1f] < ARRAY_LENGTH(banshee.seq))
4791		banshee.seq[banshee.vga[0x3c4 & 0x1f]] = data;
	4861	if (v->banshee.vga[0x3c4 & 0x1f] < ARRAY_LENGTH(v->banshee.seq))
	4862	v->banshee.seq[v->banshee.vga[0x3c4 & 0x1f]] = data;
4792	4863	if (LOG_REGISTERS)
4793		logerror("%s:banshee_seq_w(%X) = %02X\n", machine().describe_context(), banshee.vga[0x3c4 & 0x1f], data);
	4864	logerror("%s:banshee_seq_w(%X) = %02X\n", machine().describe_context(), v->banshee.vga[0x3c4 & 0x1f], data);
4794	4865	break;
4795	4866
4796	4867	/* Graphics controller access */
4797	4868	case 0x3cf:
4798		if (banshee.vga[0x3ce & 0x1f] < ARRAY_LENGTH(banshee.gc))
4799		banshee.gc[banshee.vga[0x3ce & 0x1f]] = data;
	4869	if (v->banshee.vga[0x3ce & 0x1f] < ARRAY_LENGTH(v->banshee.gc))
	4870	v->banshee.gc[v->banshee.vga[0x3ce & 0x1f]] = data;
4800	4871	if (LOG_REGISTERS)
4801		logerror("%s:banshee_gc_w(%X) = %02X\n", machine().describe_context(), banshee.vga[0x3ce & 0x1f], data);
	4872	logerror("%s:banshee_gc_w(%X) = %02X\n", machine().describe_context(), v->banshee.vga[0x3ce & 0x1f], data);
4802	4873	break;
4803	4874
4804	4875	/* CRTC access */
4805	4876	case 0x3d5:
4806		if (banshee.vga[0x3d4 & 0x1f] < ARRAY_LENGTH(banshee.crtc))
4807		banshee.crtc[banshee.vga[0x3d4 & 0x1f]] = data;
	4877	if (v->banshee.vga[0x3d4 & 0x1f] < ARRAY_LENGTH(v->banshee.crtc))
	4878	v->banshee.crtc[v->banshee.vga[0x3d4 & 0x1f]] = data;
4808	4879	if (LOG_REGISTERS)
4809		logerror("%s:banshee_crtc_w(%X) = %02X\n", machine().describe_context(), banshee.vga[0x3d4 & 0x1f], data);
	4880	logerror("%s:banshee_crtc_w(%X) = %02X\n", machine().describe_context(), v->banshee.vga[0x3d4 & 0x1f], data);
4810	4881	break;
4811	4882
4812	4883	default:
4813		banshee.vga[offset] = data;
	4884	v->banshee.vga[offset] = data;
4814	4885	if (LOG_REGISTERS)
4815	4886	logerror("%s:banshee_vga_w(%X) = %02X\n", machine().describe_context(), 0x3c0+offset, data);
4816	4887	break;
r253151	r253152
4820	4891
4821	4892	WRITE32_MEMBER( voodoo_banshee_device::banshee_io_w )
4822	4893	{
	4894	voodoo_state *v = get_safe_token(this);
4823	4895	UINT32 old;
4824	4896
4825	4897	offset &= 0xff/4;
4826		old = banshee.io[offset];
	4898	old = v->banshee.io[offset];
4827	4899
4828	4900	/* switch off the offset */
4829	4901	switch (offset)
4830	4902	{
4831	4903	case io_vidProcCfg:
4832		COMBINE_DATA(&banshee.io[offset]);
4833		if ((banshee.io[offset] ^ old) & 0x2800)
4834		fbi.clut_dirty = TRUE;
	4904	COMBINE_DATA(&v->banshee.io[offset]);
	4905	if ((v->banshee.io[offset] ^ old) & 0x2800)
	4906	v->fbi.clut_dirty = TRUE;
4835	4907	if (LOG_REGISTERS)
4836	4908	logerror("%s:banshee_io_w(%s) = %08X & %08X\n", machine().describe_context(), banshee_io_reg_name[offset], data, mem_mask);
4837	4909	break;
4838	4910
4839	4911	case io_dacData:
4840		COMBINE_DATA(&banshee.io[offset]);
4841		if (banshee.io[offset] != fbi.clut[banshee.io[io_dacAddr] & 0x1ff])
	4912	COMBINE_DATA(&v->banshee.io[offset]);
	4913	if (v->banshee.io[offset] != v->fbi.clut[v->banshee.io[io_dacAddr] & 0x1ff])
4842	4914	{
4843		fbi.clut[banshee.io[io_dacAddr] & 0x1ff] = banshee.io[offset];
4844		fbi.clut_dirty = TRUE;
	4915	v->fbi.clut[v->banshee.io[io_dacAddr] & 0x1ff] = v->banshee.io[offset];
	4916	v->fbi.clut_dirty = TRUE;
4845	4917	}
4846	4918	if (LOG_REGISTERS)
4847		logerror("%s:banshee_dac_w(%X) = %08X & %08X\n", machine().describe_context(), banshee.io[io_dacAddr] & 0x1ff, data, mem_mask);
	4919	logerror("%s:banshee_dac_w(%X) = %08X & %08X\n", machine().describe_context(), v->banshee.io[io_dacAddr] & 0x1ff, data, mem_mask);
4848	4920	break;
4849	4921
4850	4922	case io_miscInit0:
4851		COMBINE_DATA(&banshee.io[offset]);
4852		fbi.yorigin = (data >> 18) & 0xfff;
	4923	COMBINE_DATA(&v->banshee.io[offset]);
	4924	v->fbi.yorigin = (data >> 18) & 0xfff;
4853	4925	if (LOG_REGISTERS)
4854	4926	logerror("%s:banshee_io_w(%s) = %08X & %08X\n", machine().describe_context(), banshee_io_reg_name[offset], data, mem_mask);
4855	4927	break;
4856	4928
4857	4929	case io_vidScreenSize:
4858	4930	if (data & 0xfff)
4859		fbi.width = data & 0xfff;
	4931	v->fbi.width = data & 0xfff;
4860	4932	if (data & 0xfff000)
4861		fbi.height = (data >> 12) & 0xfff;
	4933	v->fbi.height = (data >> 12) & 0xfff;
4862	4934	/* fall through */
4863	4935	case io_vidOverlayDudx:
4864	4936	case io_vidOverlayDvdy:
4865	4937	{
4866	4938	/* warning: this is a hack for now! We should really compute the screen size */
4867	4939	/* from the CRTC registers */
4868		COMBINE_DATA(&banshee.io[offset]);
	4940	COMBINE_DATA(&v->banshee.io[offset]);
4869	4941
4870		int width = fbi.width;
4871		int height = fbi.height;
	4942	int width = v->fbi.width;
	4943	int height = v->fbi.height;
4872	4944
4873		if (banshee.io[io_vidOverlayDudx] != 0)
4874		width = (fbi.width * banshee.io[io_vidOverlayDudx]) / 1048576;
4875		if (banshee.io[io_vidOverlayDvdy] != 0)
4876		height = (fbi.height * banshee.io[io_vidOverlayDvdy]) / 1048576;
	4945	if (v->banshee.io[io_vidOverlayDudx] != 0)
	4946	width = (v->fbi.width * v->banshee.io[io_vidOverlayDudx]) / 1048576;
	4947	if (v->banshee.io[io_vidOverlayDvdy] != 0)
	4948	height = (v->fbi.height * v->banshee.io[io_vidOverlayDvdy]) / 1048576;
4877	4949
4878		screen->set_visible_area(0, width - 1, 0, height - 1);
	4950	v->screen->set_visible_area(0, width - 1, 0, height - 1);
4879	4951
4880		adjust_vblank_timer(~~this~~);
	4952	adjust_vblank_timer(v);
4881	4953	if (LOG_REGISTERS)
4882	4954	logerror("%s:banshee_io_w(%s) = %08X & %08X\n", machine().describe_context(), banshee_io_reg_name[offset], data, mem_mask);
4883	4955	break;
4884	4956	}
4885	4957
4886	4958	case io_lfbMemoryConfig:
4887		fbi.lfb_base = (data & 0x1fff) << (12-2);
4888		fbi.lfb_stride = ((data >> 13) & 7) + 9;
	4959	v->fbi.lfb_base = (data & 0x1fff) << (12-2);
	4960	v->fbi.lfb_stride = ((data >> 13) & 7) + 9;
4889	4961	if (LOG_REGISTERS)
4890	4962	logerror("%s:banshee_io_w(%s) = %08X & %08X\n", machine().describe_context(), banshee_io_reg_name[offset], data, mem_mask);
4891	4963	break;
r253151	r253152
4904	4976	break;
4905	4977
4906	4978	default:
4907		COMBINE_DATA(&banshee.io[offset]);
	4979	COMBINE_DATA(&v->banshee.io[offset]);
4908	4980	if (LOG_REGISTERS)
4909	4981	logerror("%s:banshee_io_w(%s) = %08X & %08X\n", machine().describe_context(), banshee_io_reg_name[offset], data, mem_mask);
4910	4982	break;
r253151	r253152
4923	4995
4924	4996	void voodoo_device::common_start_voodoo(UINT8 type)
4925	4997	{
	4998	voodoo_state *v = get_safe_token(this);
4926	4999	const raster_info *info;
4927	5000	void fbmem, tmumem[2];
4928	5001	UINT32 tmumem0, tmumem1;
r253151	r253152
4934	5007	assert(m_fbmem > 0);
4935	5008
4936	5009	/* store a pointer back to the device */
4937		device = this;
4938		vd_type = type;
	5010	v->device = this;
	5011	v->type = type;
4939	5012
4940	5013	/* copy config data */
4941		freq = clock();
4942		device->m_vblank.resolve();
4943		device->m_stall.resolve();
	5014	v->freq = clock();
	5015	v->device->m_vblank.resolve();
	5016	v->device->m_stall.resolve();
4944	5017
4945	5018	/* create a multiprocessor work queue */
4946		poly = poly_alloc(machine(), 64, sizeof(poly_extra_data), 0);
4947		thread_stats = auto_alloc_array(machine(), stats_block, WORK_MAX_THREADS);
	5019	v->poly = poly_alloc(machine(), 64, sizeof(poly_extra_data), 0);
	5020	v->thread_stats = auto_alloc_array(machine(), stats_block, WORK_MAX_THREADS);
4948	5021
4949	5022	/* create a table of precomputed 1/n and log2(n) values */
4950	5023	/* n ranges from 1.0000 to 2.0000 */
r253151	r253152
4975	5048	}
4976	5049	}
4977	5050
4978		tmu_config = 0x11; // revision 1
	5051	v->tmu_config = 0x11; // revision 1
4979	5052
4980	5053	/* configure type-specific values */
4981		switch (vd_type)
	5054	switch (v->type)
4982	5055	{
4983	5056	case TYPE_VOODOO_1:
4984		regaccess = voodoo_register_access;
4985		regnames = voodoo_reg_name;
4986		alt_regmap = 0;
4987		fbi.lfb_stride = 10;
	5057	v->regaccess = voodoo_register_access;
	5058	v->regnames = voodoo_reg_name;
	5059	v->alt_regmap = 0;
	5060	v->fbi.lfb_stride = 10;
4988	5061	break;
4989	5062
4990	5063	case TYPE_VOODOO_2:
4991		regaccess = voodoo2_register_access;
4992		regnames = voodoo_reg_name;
4993		alt_regmap = 0;
4994		fbi.lfb_stride = 10;
4995		tmu_config \|= 0x800;
	5064	v->regaccess = voodoo2_register_access;
	5065	v->regnames = voodoo_reg_name;
	5066	v->alt_regmap = 0;
	5067	v->fbi.lfb_stride = 10;
	5068	v->tmu_config \|= 0x800;
4996	5069	break;
4997	5070
4998	5071	case TYPE_VOODOO_BANSHEE:
4999		regaccess = banshee_register_access;
5000		regnames = banshee_reg_name;
5001		alt_regmap = 1;
5002		fbi.lfb_stride = 11;
	5072	v->regaccess = banshee_register_access;
	5073	v->regnames = banshee_reg_name;
	5074	v->alt_regmap = 1;
	5075	v->fbi.lfb_stride = 11;
5003	5076	break;
5004	5077
5005	5078	case TYPE_VOODOO_3:
5006		regaccess = banshee_register_access;
5007		regnames = banshee_reg_name;
5008		alt_regmap = 1;
5009		fbi.lfb_stride = 11;
	5079	v->regaccess = banshee_register_access;
	5080	v->regnames = banshee_reg_name;
	5081	v->alt_regmap = 1;
	5082	v->fbi.lfb_stride = 11;
5010	5083	break;
5011	5084
5012	5085	default:
r253151	r253152
5015	5088
5016	5089	/* set the type, and initialize the chip mask */
5017	5090	device_iterator iter(machine().root_device());
5018		index = 0;
	5091	v->index = 0;
5019	5092	for (device_t *scan = iter.first(); scan != nullptr; scan = iter.next())
5020	5093	if (scan->type() == this->type())
5021	5094	{
5022	5095	if (scan == this)
5023	5096	break;
5024		index++;
	5097	v->index++;
5025	5098	}
5026		screen = downcast<screen_device *>(machine().device(m_screen));
5027		assert_always(screen != nullptr, "Unable to find screen attached to voodoo");
5028		cpu = machine().device(m_cputag);
5029		assert_always(cpu != nullptr, "Unable to find CPU attached to voodoo");
	5099	v->screen = downcast<screen_device *>(machine().device(m_screen));
	5100	assert_always(v->screen != nullptr, "Unable to find screen attached to voodoo");
	5101	v->cpu = machine().device(m_cputag);
	5102	assert_always(v->cpu != nullptr, "Unable to find CPU attached to voodoo");
5030	5103
5031	5104	if (m_tmumem1 != 0)
5032		tmu_config \|= 0xc0; // two TMUs
	5105	v->tmu_config \|= 0xc0; // two TMUs
5033	5106
5034		chipmask = 0x01;
5035		attoseconds_per_cycle = ATTOSECONDS_PER_SECOND / freq;
5036		trigger = 51324 + index;
	5107	v->chipmask = 0x01;
	5108	v->attoseconds_per_cycle = ATTOSECONDS_PER_SECOND / v->freq;
	5109	v->trigger = 51324 + v->index;
5037	5110
5038	5111	/* build the rasterizer table */
5039	5112	for (info = predef_raster_table; info->callback; info++)
5040		add_rasterizer(~~this~~, info);
	5113	add_rasterizer(v, info);
5041	5114
5042	5115	/* set up the PCI FIFO */
5043		pci.fifo.base = pci.fifo_mem;
5044		pci.fifo.size = 64*2;
5045		pci.fifo.in = pci.fifo.out = 0;
5046		pci.stall_state = NOT_STALLED;
5047		pci.continue_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(voodoo_device::stall_cpu_callback),this), nullptr);
5048
	5116	v->pci.fifo.base = v->pci.fifo_mem;
	5117	v->pci.fifo.size = 64*2;
	5118	v->pci.fifo.in = v->pci.fifo.out = 0;
	5119	v->pci.stall_state = NOT_STALLED;
	5120	v->pci.continue_timer = machine().scheduler().timer_alloc(FUNC(stall_cpu_callback), v);
	5121
5049	5122	/* allocate memory */
5050	5123	tmumem0 = m_tmumem0;
5051	5124	tmumem1 = m_tmumem1;
5052		if (vd_type <= TYPE_VOODOO_2)
	5125	if (v->type <= TYPE_VOODOO_2)
5053	5126	{
5054	5127	/* separate FB/TMU memory */
5055	5128	fbmem = auto_alloc_array(machine(), UINT8, m_fbmem << 20);
r253151	r253152
5061	5134	/* shared memory */
5062	5135	tmumem[0] = tmumem[1] = fbmem = auto_alloc_array(machine(), UINT8, m_fbmem << 20);
5063	5136	tmumem0 = m_fbmem;
5064		if (vd_type == TYPE_VOODOO_3)
	5137	if (v->type == TYPE_VOODOO_3)
5065	5138	tmumem1 = m_fbmem;
5066	5139	}
5067	5140
5068	5141	/* set up frame buffer */
5069		init_fbi(~~this~~, &fbi, fbmem, m_fbmem << 20);
	5142	init_fbi(v, &v->fbi, fbmem, m_fbmem << 20);
5070	5143
5071	5144	/* build shared TMU tables */
5072		init_tmu_shared(&tmushare);
	5145	init_tmu_shared(&v->tmushare);
5073	5146
5074	5147	/* set up the TMUs */
5075		init_tmu(this, &tmu[0], &reg[0x100], tmumem[0], tmumem0 << 20);
5076		chipmask \|= 0x02;
	5148	init_tmu(v, &v->tmu[0], &v->reg[0x100], tmumem[0], tmumem0 << 20);
	5149	v->chipmask \|= 0x02;
5077	5150	if (tmumem1 != 0)
5078	5151	{
5079		init_tmu(this, &tmu[1], &reg[0x200], tmumem[1], tmumem1 << 20);
5080		chipmask \|= 0x04;
5081		tmu_config \|= 0x40;
	5152	init_tmu(v, &v->tmu[1], &v->reg[0x200], tmumem[1], tmumem1 << 20);
	5153	v->chipmask \|= 0x04;
	5154	v->tmu_config \|= 0x40;
5082	5155	}
5083	5156
5084	5157	/* initialize some registers */
5085		memset(reg, 0, sizeof(reg));
5086		pci.init_enable = 0;
5087		reg[fbiInit0].u = (1 << 4) \| (0x10 << 6);
5088		reg[fbiInit1].u = (1 << 1) \| (1 << 8) \| (1 << 12) \| (2 << 20);
5089		reg[fbiInit2].u = (1 << 6) \| (0x100 << 23);
5090		reg[fbiInit3].u = (2 << 13) \| (0xf << 17);
5091		reg[fbiInit4].u = (1 << 0);
	5158	memset(v->reg, 0, sizeof(v->reg));
	5159	v->pci.init_enable = 0;
	5160	v->reg[fbiInit0].u = (1 << 4) \| (0x10 << 6);
	5161	v->reg[fbiInit1].u = (1 << 1) \| (1 << 8) \| (1 << 12) \| (2 << 20);
	5162	v->reg[fbiInit2].u = (1 << 6) \| (0x100 << 23);
	5163	v->reg[fbiInit3].u = (2 << 13) \| (0xf << 17);
	5164	v->reg[fbiInit4].u = (1 << 0);
5092	5165
5093	5166	/* initialize banshee registers */
5094		memset(banshee.io, 0, sizeof(banshee.io));
5095		banshee.io[io_pciInit0] = 0x01800040;
5096		banshee.io[io_sipMonitor] = 0x40000000;
5097		banshee.io[io_lfbMemoryConfig] = 0x000a2200;
5098		banshee.io[io_dramInit0] = 0x00579d29;
5099		banshee.io[io_dramInit0] \|= 0x08000000; // Konami Viper expects 16MBit SGRAMs
5100		banshee.io[io_dramInit1] = 0x00f02200;
5101		banshee.io[io_tmuGbeInit] = 0x00000bfb;
	5167	memset(v->banshee.io, 0, sizeof(v->banshee.io));
	5168	v->banshee.io[io_pciInit0] = 0x01800040;
	5169	v->banshee.io[io_sipMonitor] = 0x40000000;
	5170	v->banshee.io[io_lfbMemoryConfig] = 0x000a2200;
	5171	v->banshee.io[io_dramInit0] = 0x00579d29;
	5172	v->banshee.io[io_dramInit0] \|= 0x08000000; // Konami Viper expects 16MBit SGRAMs
	5173	v->banshee.io[io_dramInit1] = 0x00f02200;
	5174	v->banshee.io[io_tmuGbeInit] = 0x00000bfb;
5102	5175
5103	5176	/* do a soft reset to reset everything else */
5104		soft_reset(~~this~~);
	5177	soft_reset(v);
5105	5178
5106	5179	/* register for save states */
5107	5180	init_save_state(this);
r253151	r253152
5118	5191	command
5119	5192	-------------------------------------------------*/
5120	5193
5121		INT32 ~~voodoo_device::~~fastfill(voodoo_de~~vice~~ *vd)
	5194	static INT32 fastfill(voodoo_state *v)
5122	5195	{
5123		int sx = (vd->reg[clipLeftRight].u >> 16) & 0x3ff;
5124		int ex = (vd->reg[clipLeftRight].u >> 0) & 0x3ff;
5125		int sy = (vd->reg[clipLowYHighY].u >> 16) & 0x3ff;
5126		int ey = (vd->reg[clipLowYHighY].u >> 0) & 0x3ff;
	5196	int sx = (v->reg[clipLeftRight].u >> 16) & 0x3ff;
	5197	int ex = (v->reg[clipLeftRight].u >> 0) & 0x3ff;
	5198	int sy = (v->reg[clipLowYHighY].u >> 16) & 0x3ff;
	5199	int ey = (v->reg[clipLowYHighY].u >> 0) & 0x3ff;
5127	5200	poly_extent extents[64];
5128	5201	UINT16 dithermatrix[16];
5129	5202	UINT16 *drawbuf = nullptr;
r253151	r253152
5131	5204	int extnum, x, y;
5132	5205
5133	5206	/* if we're not clearing either, take no time */
5134		if (!FBZMODE_RGB_BUFFER_MASK(vd->reg[fbzMode].u) && !FBZMODE_AUX_BUFFER_MASK(vd->reg[fbzMode].u))
	5207	if (!FBZMODE_RGB_BUFFER_MASK(v->reg[fbzMode].u) && !FBZMODE_AUX_BUFFER_MASK(v->reg[fbzMode].u))
5135	5208	return 0;
5136	5209
5137	5210	/* are we clearing the RGB buffer? */
5138		if (FBZMODE_RGB_BUFFER_MASK(vd->reg[fbzMode].u))
	5211	if (FBZMODE_RGB_BUFFER_MASK(v->reg[fbzMode].u))
5139	5212	{
5140	5213	/* determine the draw buffer */
5141		int destbuf = (vd->~~vd_~~type >= TYPE_VOODOO_BANSHEE) ? 1 : FBZMODE_DRAW_BUFFER(vd->reg[fbzMode].u);
	5214	int destbuf = (v->type >= TYPE_VOODOO_BANSHEE) ? 1 : FBZMODE_DRAW_BUFFER(v->reg[fbzMode].u);
5142	5215	switch (destbuf)
5143	5216	{
5144	5217	case 0: /* front buffer */
5145		drawbuf = (UINT16 *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.frontbuf]);
	5218	drawbuf = (UINT16 *)(v->fbi.ram + v->fbi.rgboffs[v->fbi.frontbuf]);
5146	5219	break;
5147	5220
5148	5221	case 1: /* back buffer */
5149		drawbuf = (UINT16 *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.backbuf]);
	5222	drawbuf = (UINT16 *)(v->fbi.ram + v->fbi.rgboffs[v->fbi.backbuf]);
5150	5223	break;
5151	5224
5152	5225	default: /* reserved */
r253151	r253152
5157	5230	for (y = 0; y < 4; y++)
5158	5231	{
5159	5232	DECLARE_DITHER_POINTERS_NO_DITHER_VAR;
5160		COMPUTE_DITHER_POINTERS_NO_DITHER_VAR(vd->reg[fbzMode].u, y);
	5233	COMPUTE_DITHER_POINTERS_NO_DITHER_VAR(v->reg[fbzMode].u, y);
5161	5234	for (x = 0; x < 4; x++)
5162	5235	{
5163		int r = vd->reg[color1].rgb.r;
5164		int g = vd->reg[color1].rgb.g;
5165		int b = vd->reg[color1].rgb.b;
	5236	int r = v->reg[color1].rgb.r;
	5237	int g = v->reg[color1].rgb.g;
	5238	int b = v->reg[color1].rgb.b;
5166	5239
5167		APPLY_DITHER(vd->reg[fbzMode].u, x, dither_lookup, r, g, b);
	5240	APPLY_DITHER(v->reg[fbzMode].u, x, dither_lookup, r, g, b);
5168	5241	dithermatrix[y*4 + x] = (r << 11) \| (g << 5) \| b;
5169	5242	}
5170	5243	}
r253151	r253152
5179	5252	/* iterate over blocks of extents */
5180	5253	for (y = sy; y < ey; y += ARRAY_LENGTH(extents))
5181	5254	{
5182		poly_extra_data extra = (poly_extra_data )poly_get_extra_data(vd->poly);
	5255	poly_extra_data extra = (poly_extra_data )poly_get_extra_data(v->poly);
5183	5256	int count = MIN(ey - y, ARRAY_LENGTH(extents));
5184	5257
5185		extra->de~~vice~~= vd;
	5258	extra->state = v;
5186	5259	memcpy(extra->dither, dithermatrix, sizeof(extra->dither));
5187	5260
5188		pixels += poly_render_triangle_custom(vd->poly, drawbuf, global_cliprect, raster_fastfill, y, count, extents);
	5261	pixels += poly_render_triangle_custom(v->poly, drawbuf, global_cliprect, raster_fastfill, y, count, extents);
5189	5262	}
5190	5263
5191	5264	/* 2 pixels per clock */
r253151	r253152
5198	5271	command
5199	5272	-------------------------------------------------*/
5200	5273
5201		INT32 ~~voodoo_device::~~swapbuffer(voodoo_device* vd, UINT32 data)
	5274	static INT32 swapbuffer(voodoo_state *v, UINT32 data)
5202	5275	{
5203	5276	/* set the don't swap value for Voodoo 2 */
5204		vd->fbi.vblank_swap_pending = TRUE;
5205		vd->fbi.vblank_swap = (data >> 1) & 0xff;
5206		vd->fbi.vblank_dont_swap = (data >> 9) & 1;
	5277	v->fbi.vblank_swap_pending = TRUE;
	5278	v->fbi.vblank_swap = (data >> 1) & 0xff;
	5279	v->fbi.vblank_dont_swap = (data >> 9) & 1;
5207	5280
5208	5281	/* if we're not syncing to the retrace, process the command immediately */
5209	5282	if (!(data & 1))
5210	5283	{
5211		swap_buffers(vd);
	5284	swap_buffers(v);
5212	5285	return 0;
5213	5286	}
5214	5287
5215	5288	/* determine how many cycles to wait; we deliberately overshoot here because */
5216	5289	/* the final count gets updated on the VBLANK */
5217		return (vd->fbi.vblank_swap + 1) * vd->freq / 30;
	5290	return (v->fbi.vblank_swap + 1) * v->freq / 30;
5218	5291	}
5219	5292
5220	5293
r253151	r253152
5223	5296	command
5224	5297	-------------------------------------------------*/
5225	5298
5226		INT32 ~~voodoo_device::~~triangle(voodoo_de~~vice~~ *vd)
	5299	static INT32 triangle(voodoo_state *v)
5227	5300	{
5228	5301	int texcount;
5229	5302	UINT16 *drawbuf;
r253151	r253152
5234	5307
5235	5308	/* determine the number of TMUs involved */
5236	5309	texcount = 0;
5237		if (!FBIINIT3_DISABLE_TMUS(vd->reg[fbiInit3].u) && FBZCP_TEXTURE_ENABLE(vd->reg[fbzColorPath].u))
	5310	if (!FBIINIT3_DISABLE_TMUS(v->reg[fbiInit3].u) && FBZCP_TEXTURE_ENABLE(v->reg[fbzColorPath].u))
5238	5311	{
5239	5312	texcount = 1;
5240		if (vd->chipmask & 0x04)
	5313	if (v->chipmask & 0x04)
5241	5314	texcount = 2;
5242	5315	}
5243	5316
5244	5317	/* perform subpixel adjustments */
5245		if (FBZCP_CCA_SUBPIXEL_ADJUST(vd->reg[fbzColorPath].u))
	5318	if (FBZCP_CCA_SUBPIXEL_ADJUST(v->reg[fbzColorPath].u))
5246	5319	{
5247		INT32 dx = 8 - (vd->fbi.ax & 15);
5248		INT32 dy = 8 - (vd->fbi.ay & 15);
	5320	INT32 dx = 8 - (v->fbi.ax & 15);
	5321	INT32 dy = 8 - (v->fbi.ay & 15);
5249	5322
5250	5323	/* adjust iterated R,G,B,A and W/Z */
5251		vd->fbi.startr += (dy * vd->fbi.drdy + dx * vd->fbi.drdx) >> 4;
5252		vd->fbi.startg += (dy * vd->fbi.dgdy + dx * vd->fbi.dgdx) >> 4;
5253		vd->fbi.startb += (dy * vd->fbi.dbdy + dx * vd->fbi.dbdx) >> 4;
5254		vd->fbi.starta += (dy * vd->fbi.dady + dx * vd->fbi.dadx) >> 4;
5255		vd->fbi.startw += (dy * vd->fbi.dwdy + dx * vd->fbi.dwdx) >> 4;
5256		vd->fbi.startz += mul_32x32_shift(dy, vd->fbi.dzdy, 4) + mul_32x32_shift(dx, vd->fbi.dzdx, 4);
	5324	v->fbi.startr += (dy * v->fbi.drdy + dx * v->fbi.drdx) >> 4;
	5325	v->fbi.startg += (dy * v->fbi.dgdy + dx * v->fbi.dgdx) >> 4;
	5326	v->fbi.startb += (dy * v->fbi.dbdy + dx * v->fbi.dbdx) >> 4;
	5327	v->fbi.starta += (dy * v->fbi.dady + dx * v->fbi.dadx) >> 4;
	5328	v->fbi.startw += (dy * v->fbi.dwdy + dx * v->fbi.dwdx) >> 4;
	5329	v->fbi.startz += mul_32x32_shift(dy, v->fbi.dzdy, 4) + mul_32x32_shift(dx, v->fbi.dzdx, 4);
5257	5330
5258	5331	/* adjust iterated W/S/T for TMU 0 */
5259	5332	if (texcount >= 1)
5260	5333	{
5261		vd->tmu[0].startw += (dy * vd->tmu[0].dwdy + dx * vd->tmu[0].dwdx) >> 4;
5262		vd->tmu[0].starts += (dy * vd->tmu[0].dsdy + dx * vd->tmu[0].dsdx) >> 4;
5263		vd->tmu[0].startt += (dy * vd->tmu[0].dtdy + dx * vd->tmu[0].dtdx) >> 4;
	5334	v->tmu[0].startw += (dy * v->tmu[0].dwdy + dx * v->tmu[0].dwdx) >> 4;
	5335	v->tmu[0].starts += (dy * v->tmu[0].dsdy + dx * v->tmu[0].dsdx) >> 4;
	5336	v->tmu[0].startt += (dy * v->tmu[0].dtdy + dx * v->tmu[0].dtdx) >> 4;
5264	5337
5265	5338	/* adjust iterated W/S/T for TMU 1 */
5266	5339	if (texcount >= 2)
5267	5340	{
5268		vd->tmu[1].startw += (dy * vd->tmu[1].dwdy + dx * vd->tmu[1].dwdx) >> 4;
5269		vd->tmu[1].starts += (dy * vd->tmu[1].dsdy + dx * vd->tmu[1].dsdx) >> 4;
5270		vd->tmu[1].startt += (dy * vd->tmu[1].dtdy + dx * vd->tmu[1].dtdx) >> 4;
	5341	v->tmu[1].startw += (dy * v->tmu[1].dwdy + dx * v->tmu[1].dwdx) >> 4;
	5342	v->tmu[1].starts += (dy * v->tmu[1].dsdy + dx * v->tmu[1].dsdx) >> 4;
	5343	v->tmu[1].startt += (dy * v->tmu[1].dtdy + dx * v->tmu[1].dtdx) >> 4;
5271	5344	}
5272	5345	}
5273	5346	}
5274	5347
5275	5348	/* wait for any outstanding work to finish */
5276		// poly_wait(vd->poly, "triangle");
	5349	// poly_wait(v->poly, "triangle");
5277	5350
5278	5351	/* determine the draw buffer */
5279		destbuf = (vd->~~vd_~~type >= TYPE_VOODOO_BANSHEE) ? 1 : FBZMODE_DRAW_BUFFER(vd->reg[fbzMode].u);
	5352	destbuf = (v->type >= TYPE_VOODOO_BANSHEE) ? 1 : FBZMODE_DRAW_BUFFER(v->reg[fbzMode].u);
5280	5353	switch (destbuf)
5281	5354	{
5282	5355	case 0: /* front buffer */
5283		drawbuf = (UINT16 *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.frontbuf]);
5284		vd->fbi.video_changed = TRUE;
	5356	drawbuf = (UINT16 *)(v->fbi.ram + v->fbi.rgboffs[v->fbi.frontbuf]);
	5357	v->fbi.video_changed = TRUE;
5285	5358	break;
5286	5359
5287	5360	case 1: /* back buffer */
5288		drawbuf = (UINT16 *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.backbuf]);
	5361	drawbuf = (UINT16 *)(v->fbi.ram + v->fbi.rgboffs[v->fbi.backbuf]);
5289	5362	break;
5290	5363
5291	5364	default: /* reserved */
r253151	r253152
5293	5366	}
5294	5367
5295	5368	/* find a rasterizer that matches our current state */
5296		pixels = triangle_create_work_item(vd, drawbuf, texcount);
	5369	pixels = triangle_create_work_item(v, drawbuf, texcount);
5297	5370
5298	5371	/* update stats */
5299		vd->reg[fbiTrianglesOut].u++;
	5372	v->reg[fbiTrianglesOut].u++;
5300	5373
5301	5374	/* update stats */
5302		vd->stats.total_triangles++;
	5375	v->stats.total_triangles++;
5303	5376
5304	5377	g_profiler.stop();
5305	5378
5306	5379	/* 1 pixel per clock, plus some setup time */
5307		if (LOG_REGISTERS) vd->device->logerror("cycles = %d\n", TRIANGLE_SETUP_CLOCKS + pixels);
	5380	if (LOG_REGISTERS) v->device->logerror("cycles = %d\n", TRIANGLE_SETUP_CLOCKS + pixels);
5308	5381	return TRIANGLE_SETUP_CLOCKS + pixels;
5309	5382	}
5310	5383
r253151	r253152
5314	5387	command
5315	5388	-------------------------------------------------*/
5316	5389
5317		INT32 ~~voodoo_device::~~begin_triangle(voodoo_de~~vice~~ *vd)
	5390	static INT32 begin_triangle(voodoo_state *v)
5318	5391	{
5319		setup_vertex *sv = &vd->fbi.svert[2];
	5392	setup_vertex *sv = &v->fbi.svert[2];
5320	5393
5321	5394	/* extract all the data from registers */
5322		sv->x = vd->reg[sVx].f;
5323		sv->y = vd->reg[sVy].f;
5324		sv->wb = vd->reg[sWb].f;
5325		sv->w0 = vd->reg[sWtmu0].f;
5326		sv->s0 = vd->reg[sS_W0].f;
5327		sv->t0 = vd->reg[sT_W0].f;
5328		sv->w1 = vd->reg[sWtmu1].f;
5329		sv->s1 = vd->reg[sS_Wtmu1].f;
5330		sv->t1 = vd->reg[sT_Wtmu1].f;
5331		sv->a = vd->reg[sAlpha].f;
5332		sv->r = vd->reg[sRed].f;
5333		sv->g = vd->reg[sGreen].f;
5334		sv->b = vd->reg[sBlue].f;
	5395	sv->x = v->reg[sVx].f;
	5396	sv->y = v->reg[sVy].f;
	5397	sv->wb = v->reg[sWb].f;
	5398	sv->w0 = v->reg[sWtmu0].f;
	5399	sv->s0 = v->reg[sS_W0].f;
	5400	sv->t0 = v->reg[sT_W0].f;
	5401	sv->w1 = v->reg[sWtmu1].f;
	5402	sv->s1 = v->reg[sS_Wtmu1].f;
	5403	sv->t1 = v->reg[sT_Wtmu1].f;
	5404	sv->a = v->reg[sAlpha].f;
	5405	sv->r = v->reg[sRed].f;
	5406	sv->g = v->reg[sGreen].f;
	5407	sv->b = v->reg[sBlue].f;
5335	5408
5336	5409	/* spread it across all three verts and reset the count */
5337		vd->fbi.svert[0] = vd->fbi.svert[1] = vd->fbi.svert[2];
5338		vd->fbi.sverts = 1;
	5410	v->fbi.svert[0] = v->fbi.svert[1] = v->fbi.svert[2];
	5411	v->fbi.sverts = 1;
5339	5412
5340	5413	return 0;
5341	5414	}
r253151	r253152
5346	5419	command
5347	5420	-------------------------------------------------*/
5348	5421
5349		INT32 ~~voo~~d~~oo_device::d~~raw_triangle(voodoo_de~~vice~~ *vd)
	5422	static INT32 draw_triangle(voodoo_state *v)
5350	5423	{
5351		setup_vertex *sv = &vd->fbi.svert[2];
	5424	setup_vertex *sv = &v->fbi.svert[2];
5352	5425	int cycles = 0;
5353	5426
5354	5427	/* for strip mode, shuffle vertex 1 down to 0 */
5355		if (!(vd->reg[sSetupMode].u & (1 << 16)))
5356		vd->fbi.svert[0] = vd->fbi.svert[1];
	5428	if (!(v->reg[sSetupMode].u & (1 << 16)))
	5429	v->fbi.svert[0] = v->fbi.svert[1];
5357	5430
5358	5431	/* copy 2 down to 1 regardless */
5359		vd->fbi.svert[1] = vd->fbi.svert[2];
	5432	v->fbi.svert[1] = v->fbi.svert[2];
5360	5433
5361	5434	/* extract all the data from registers */
5362		sv->x = vd->reg[sVx].f;
5363		sv->y = vd->reg[sVy].f;
5364		sv->wb = vd->reg[sWb].f;
5365		sv->w0 = vd->reg[sWtmu0].f;
5366		sv->s0 = vd->reg[sS_W0].f;
5367		sv->t0 = vd->reg[sT_W0].f;
5368		sv->w1 = vd->reg[sWtmu1].f;
5369		sv->s1 = vd->reg[sS_Wtmu1].f;
5370		sv->t1 = vd->reg[sT_Wtmu1].f;
5371		sv->a = vd->reg[sAlpha].f;
5372		sv->r = vd->reg[sRed].f;
5373		sv->g = vd->reg[sGreen].f;
5374		sv->b = vd->reg[sBlue].f;
	5435	sv->x = v->reg[sVx].f;
	5436	sv->y = v->reg[sVy].f;
	5437	sv->wb = v->reg[sWb].f;
	5438	sv->w0 = v->reg[sWtmu0].f;
	5439	sv->s0 = v->reg[sS_W0].f;
	5440	sv->t0 = v->reg[sT_W0].f;
	5441	sv->w1 = v->reg[sWtmu1].f;
	5442	sv->s1 = v->reg[sS_Wtmu1].f;
	5443	sv->t1 = v->reg[sT_Wtmu1].f;
	5444	sv->a = v->reg[sAlpha].f;
	5445	sv->r = v->reg[sRed].f;
	5446	sv->g = v->reg[sGreen].f;
	5447	sv->b = v->reg[sBlue].f;
5375	5448
5376	5449	/* if we have enough verts, go ahead and draw */
5377		if (++vd->fbi.sverts >= 3)
5378		cycles = setup_and_draw_triangle(vd);
	5450	if (++v->fbi.sverts >= 3)
	5451	cycles = setup_and_draw_triangle(v);
5379	5452
5380	5453	return cycles;
5381	5454	}
r253151	r253152
5391	5464	parameters and render the triangle
5392	5465	-------------------------------------------------*/
5393	5466
5394		INT32 ~~voodoo_device::~~setup_and_draw_triangle(voodoo_de~~vice~~ *vd)
	5467	static INT32 setup_and_draw_triangle(voodoo_state *v)
5395	5468	{
5396	5469	float dx1, dy1, dx2, dy2;
5397	5470	float divisor, tdiv;
5398	5471
5399	5472	/* grab the X/Ys at least */
5400		vd->fbi.ax = (INT16)(vd->fbi.svert[0].x * 16.0f);
5401		vd->fbi.ay = (INT16)(vd->fbi.svert[0].y * 16.0f);
5402		vd->fbi.bx = (INT16)(vd->fbi.svert[1].x * 16.0f);
5403		vd->fbi.by = (INT16)(vd->fbi.svert[1].y * 16.0f);
5404		vd->fbi.cx = (INT16)(vd->fbi.svert[2].x * 16.0f);
5405		vd->fbi.cy = (INT16)(vd->fbi.svert[2].y * 16.0f);
	5473	v->fbi.ax = (INT16)(v->fbi.svert[0].x * 16.0f);
	5474	v->fbi.ay = (INT16)(v->fbi.svert[0].y * 16.0f);
	5475	v->fbi.bx = (INT16)(v->fbi.svert[1].x * 16.0f);
	5476	v->fbi.by = (INT16)(v->fbi.svert[1].y * 16.0f);
	5477	v->fbi.cx = (INT16)(v->fbi.svert[2].x * 16.0f);
	5478	v->fbi.cy = (INT16)(v->fbi.svert[2].y * 16.0f);
5406	5479
5407	5480	/* compute the divisor */
5408		divisor = 1.0f / ((vd->fbi.svert[0].x - vd->fbi.svert[1].x) * (vd->fbi.svert[0].y - vd->fbi.svert[2].y) -
5409		(vd->fbi.svert[0].x - vd->fbi.svert[2].x) * (vd->fbi.svert[0].y - vd->fbi.svert[1].y));
	5481	divisor = 1.0f / ((v->fbi.svert[0].x - v->fbi.svert[1].x) * (v->fbi.svert[0].y - v->fbi.svert[2].y) -
	5482	(v->fbi.svert[0].x - v->fbi.svert[2].x) * (v->fbi.svert[0].y - v->fbi.svert[1].y));
5410	5483
5411	5484	/* backface culling */
5412		if (vd->reg[sSetupMode].u & 0x20000)
	5485	if (v->reg[sSetupMode].u & 0x20000)
5413	5486	{
5414		int culling_sign = (vd->reg[sSetupMode].u >> 18) & 1;
	5487	int culling_sign = (v->reg[sSetupMode].u >> 18) & 1;
5415	5488	int divisor_sign = (divisor < 0);
5416	5489
5417	5490	/* if doing strips and ping pong is enabled, apply the ping pong */
5418		if ((vd->reg[sSetupMode].u & 0x90000) == 0x00000)
5419		culling_sign ^= (vd->fbi.sverts - 3) & 1;
	5491	if ((v->reg[sSetupMode].u & 0x90000) == 0x00000)
	5492	culling_sign ^= (v->fbi.sverts - 3) & 1;
5420	5493
5421	5494	/* if our sign matches the culling sign, we're done for */
5422	5495	if (divisor_sign == culling_sign)
r253151	r253152
5424	5497	}
5425	5498
5426	5499	/* compute the dx/dy values */
5427		dx1 = vd->fbi.svert[0].y - vd->fbi.svert[2].y;
5428		dx2 = vd->fbi.svert[0].y - vd->fbi.svert[1].y;
5429		dy1 = vd->fbi.svert[0].x - vd->fbi.svert[1].x;
5430		dy2 = vd->fbi.svert[0].x - vd->fbi.svert[2].x;
	5500	dx1 = v->fbi.svert[0].y - v->fbi.svert[2].y;
	5501	dx2 = v->fbi.svert[0].y - v->fbi.svert[1].y;
	5502	dy1 = v->fbi.svert[0].x - v->fbi.svert[1].x;
	5503	dy2 = v->fbi.svert[0].x - v->fbi.svert[2].x;
5431	5504
5432	5505	/* set up R,G,B */
5433	5506	tdiv = divisor * 4096.0f;
5434		if (vd->reg[sSetupMode].u & (1 << 0))
	5507	if (v->reg[sSetupMode].u & (1 << 0))
5435	5508	{
5436		vd->fbi.startr = (INT32)(vd->fbi.svert[0].r * 4096.0f);
5437		vd->fbi.drdx = (INT32)(((vd->fbi.svert[0].r - vd->fbi.svert[1].r) * dx1 - (vd->fbi.svert[0].r - vd->fbi.svert[2].r) * dx2) * tdiv);
5438		vd->fbi.drdy = (INT32)(((vd->fbi.svert[0].r - vd->fbi.svert[2].r) * dy1 - (vd->fbi.svert[0].r - vd->fbi.svert[1].r) * dy2) * tdiv);
5439		vd->fbi.startg = (INT32)(vd->fbi.svert[0].g * 4096.0f);
5440		vd->fbi.dgdx = (INT32)(((vd->fbi.svert[0].g - vd->fbi.svert[1].g) * dx1 - (vd->fbi.svert[0].g - vd->fbi.svert[2].g) * dx2) * tdiv);
5441		vd->fbi.dgdy = (INT32)(((vd->fbi.svert[0].g - vd->fbi.svert[2].g) * dy1 - (vd->fbi.svert[0].g - vd->fbi.svert[1].g) * dy2) * tdiv);
5442		vd->fbi.startb = (INT32)(vd->fbi.svert[0].b * 4096.0f);
5443		vd->fbi.dbdx = (INT32)(((vd->fbi.svert[0].b - vd->fbi.svert[1].b) * dx1 - (vd->fbi.svert[0].b - vd->fbi.svert[2].b) * dx2) * tdiv);
5444		vd->fbi.dbdy = (INT32)(((vd->fbi.svert[0].b - vd->fbi.svert[2].b) * dy1 - (vd->fbi.svert[0].b - vd->fbi.svert[1].b) * dy2) * tdiv);
	5509	v->fbi.startr = (INT32)(v->fbi.svert[0].r * 4096.0f);
	5510	v->fbi.drdx = (INT32)(((v->fbi.svert[0].r - v->fbi.svert[1].r) * dx1 - (v->fbi.svert[0].r - v->fbi.svert[2].r) * dx2) * tdiv);
	5511	v->fbi.drdy = (INT32)(((v->fbi.svert[0].r - v->fbi.svert[2].r) * dy1 - (v->fbi.svert[0].r - v->fbi.svert[1].r) * dy2) * tdiv);
	5512	v->fbi.startg = (INT32)(v->fbi.svert[0].g * 4096.0f);
	5513	v->fbi.dgdx = (INT32)(((v->fbi.svert[0].g - v->fbi.svert[1].g) * dx1 - (v->fbi.svert[0].g - v->fbi.svert[2].g) * dx2) * tdiv);
	5514	v->fbi.dgdy = (INT32)(((v->fbi.svert[0].g - v->fbi.svert[2].g) * dy1 - (v->fbi.svert[0].g - v->fbi.svert[1].g) * dy2) * tdiv);
	5515	v->fbi.startb = (INT32)(v->fbi.svert[0].b * 4096.0f);
	5516	v->fbi.dbdx = (INT32)(((v->fbi.svert[0].b - v->fbi.svert[1].b) * dx1 - (v->fbi.svert[0].b - v->fbi.svert[2].b) * dx2) * tdiv);
	5517	v->fbi.dbdy = (INT32)(((v->fbi.svert[0].b - v->fbi.svert[2].b) * dy1 - (v->fbi.svert[0].b - v->fbi.svert[1].b) * dy2) * tdiv);
5445	5518	}
5446	5519
5447	5520	/* set up alpha */
5448		if (vd->reg[sSetupMode].u & (1 << 1))
	5521	if (v->reg[sSetupMode].u & (1 << 1))
5449	5522	{
5450		vd->fbi.starta = (INT32)(vd->fbi.svert[0].a * 4096.0f);
5451		vd->fbi.dadx = (INT32)(((vd->fbi.svert[0].a - vd->fbi.svert[1].a) * dx1 - (vd->fbi.svert[0].a - vd->fbi.svert[2].a) * dx2) * tdiv);
5452		vd->fbi.dady = (INT32)(((vd->fbi.svert[0].a - vd->fbi.svert[2].a) * dy1 - (vd->fbi.svert[0].a - vd->fbi.svert[1].a) * dy2) * tdiv);
	5523	v->fbi.starta = (INT32)(v->fbi.svert[0].a * 4096.0f);
	5524	v->fbi.dadx = (INT32)(((v->fbi.svert[0].a - v->fbi.svert[1].a) * dx1 - (v->fbi.svert[0].a - v->fbi.svert[2].a) * dx2) * tdiv);
	5525	v->fbi.dady = (INT32)(((v->fbi.svert[0].a - v->fbi.svert[2].a) * dy1 - (v->fbi.svert[0].a - v->fbi.svert[1].a) * dy2) * tdiv);
5453	5526	}
5454	5527
5455	5528	/* set up Z */
5456		if (vd->reg[sSetupMode].u & (1 << 2))
	5529	if (v->reg[sSetupMode].u & (1 << 2))
5457	5530	{
5458		vd->fbi.startz = (INT32)(vd->fbi.svert[0].z * 4096.0f);
5459		vd->fbi.dzdx = (INT32)(((vd->fbi.svert[0].z - vd->fbi.svert[1].z) * dx1 - (vd->fbi.svert[0].z - vd->fbi.svert[2].z) * dx2) * tdiv);
5460		vd->fbi.dzdy = (INT32)(((vd->fbi.svert[0].z - vd->fbi.svert[2].z) * dy1 - (vd->fbi.svert[0].z - vd->fbi.svert[1].z) * dy2) * tdiv);
	5531	v->fbi.startz = (INT32)(v->fbi.svert[0].z * 4096.0f);
	5532	v->fbi.dzdx = (INT32)(((v->fbi.svert[0].z - v->fbi.svert[1].z) * dx1 - (v->fbi.svert[0].z - v->fbi.svert[2].z) * dx2) * tdiv);
	5533	v->fbi.dzdy = (INT32)(((v->fbi.svert[0].z - v->fbi.svert[2].z) * dy1 - (v->fbi.svert[0].z - v->fbi.svert[1].z) * dy2) * tdiv);
5461	5534	}
5462	5535
5463	5536	/* set up Wb */
5464	5537	tdiv = divisor * 65536.0f * 65536.0f;
5465		if (vd->reg[sSetupMode].u & (1 << 3))
	5538	if (v->reg[sSetupMode].u & (1 << 3))
5466	5539	{
5467		vd->fbi.startw = vd->tmu[0].startw = vd->tmu[1].startw = (INT64)(vd->fbi.svert[0].wb * 65536.0f * 65536.0f);
5468		vd->fbi.dwdx = vd->tmu[0].dwdx = vd->tmu[1].dwdx = ((vd->fbi.svert[0].wb - vd->fbi.svert[1].wb) * dx1 - (vd->fbi.svert[0].wb - vd->fbi.svert[2].wb) * dx2) * tdiv;
5469		vd->fbi.dwdy = vd->tmu[0].dwdy = vd->tmu[1].dwdy = ((vd->fbi.svert[0].wb - vd->fbi.svert[2].wb) * dy1 - (vd->fbi.svert[0].wb - vd->fbi.svert[1].wb) * dy2) * tdiv;
	5540	v->fbi.startw = v->tmu[0].startw = v->tmu[1].startw = (INT64)(v->fbi.svert[0].wb * 65536.0f * 65536.0f);
	5541	v->fbi.dwdx = v->tmu[0].dwdx = v->tmu[1].dwdx = ((v->fbi.svert[0].wb - v->fbi.svert[1].wb) * dx1 - (v->fbi.svert[0].wb - v->fbi.svert[2].wb) * dx2) * tdiv;
	5542	v->fbi.dwdy = v->tmu[0].dwdy = v->tmu[1].dwdy = ((v->fbi.svert[0].wb - v->fbi.svert[2].wb) * dy1 - (v->fbi.svert[0].wb - v->fbi.svert[1].wb) * dy2) * tdiv;
5470	5543	}
5471	5544
5472	5545	/* set up W0 */
5473		if (vd->reg[sSetupMode].u & (1 << 4))
	5546	if (v->reg[sSetupMode].u & (1 << 4))
5474	5547	{
5475		vd->tmu[0].startw = vd->tmu[1].startw = (INT64)(vd->fbi.svert[0].w0 * 65536.0f * 65536.0f);
5476		vd->tmu[0].dwdx = vd->tmu[1].dwdx = ((vd->fbi.svert[0].w0 - vd->fbi.svert[1].w0) * dx1 - (vd->fbi.svert[0].w0 - vd->fbi.svert[2].w0) * dx2) * tdiv;
5477		vd->tmu[0].dwdy = vd->tmu[1].dwdy = ((vd->fbi.svert[0].w0 - vd->fbi.svert[2].w0) * dy1 - (vd->fbi.svert[0].w0 - vd->fbi.svert[1].w0) * dy2) * tdiv;
	5548	v->tmu[0].startw = v->tmu[1].startw = (INT64)(v->fbi.svert[0].w0 * 65536.0f * 65536.0f);
	5549	v->tmu[0].dwdx = v->tmu[1].dwdx = ((v->fbi.svert[0].w0 - v->fbi.svert[1].w0) * dx1 - (v->fbi.svert[0].w0 - v->fbi.svert[2].w0) * dx2) * tdiv;
	5550	v->tmu[0].dwdy = v->tmu[1].dwdy = ((v->fbi.svert[0].w0 - v->fbi.svert[2].w0) * dy1 - (v->fbi.svert[0].w0 - v->fbi.svert[1].w0) * dy2) * tdiv;
5478	5551	}
5479	5552
5480	5553	/* set up S0,T0 */
5481		if (vd->reg[sSetupMode].u & (1 << 5))
	5554	if (v->reg[sSetupMode].u & (1 << 5))
5482	5555	{
5483		vd->tmu[0].starts = vd->tmu[1].starts = (INT64)(vd->fbi.svert[0].s0 * 65536.0f * 65536.0f);
5484		vd->tmu[0].dsdx = vd->tmu[1].dsdx = ((vd->fbi.svert[0].s0 - vd->fbi.svert[1].s0) * dx1 - (vd->fbi.svert[0].s0 - vd->fbi.svert[2].s0) * dx2) * tdiv;
5485		vd->tmu[0].dsdy = vd->tmu[1].dsdy = ((vd->fbi.svert[0].s0 - vd->fbi.svert[2].s0) * dy1 - (vd->fbi.svert[0].s0 - vd->fbi.svert[1].s0) * dy2) * tdiv;
5486		vd->tmu[0].startt = vd->tmu[1].startt = (INT64)(vd->fbi.svert[0].t0 * 65536.0f * 65536.0f);
5487		vd->tmu[0].dtdx = vd->tmu[1].dtdx = ((vd->fbi.svert[0].t0 - vd->fbi.svert[1].t0) * dx1 - (vd->fbi.svert[0].t0 - vd->fbi.svert[2].t0) * dx2) * tdiv;
5488		vd->tmu[0].dtdy = vd->tmu[1].dtdy = ((vd->fbi.svert[0].t0 - vd->fbi.svert[2].t0) * dy1 - (vd->fbi.svert[0].t0 - vd->fbi.svert[1].t0) * dy2) * tdiv;
	5556	v->tmu[0].starts = v->tmu[1].starts = (INT64)(v->fbi.svert[0].s0 * 65536.0f * 65536.0f);
	5557	v->tmu[0].dsdx = v->tmu[1].dsdx = ((v->fbi.svert[0].s0 - v->fbi.svert[1].s0) * dx1 - (v->fbi.svert[0].s0 - v->fbi.svert[2].s0) * dx2) * tdiv;
	5558	v->tmu[0].dsdy = v->tmu[1].dsdy = ((v->fbi.svert[0].s0 - v->fbi.svert[2].s0) * dy1 - (v->fbi.svert[0].s0 - v->fbi.svert[1].s0) * dy2) * tdiv;
	5559	v->tmu[0].startt = v->tmu[1].startt = (INT64)(v->fbi.svert[0].t0 * 65536.0f * 65536.0f);
	5560	v->tmu[0].dtdx = v->tmu[1].dtdx = ((v->fbi.svert[0].t0 - v->fbi.svert[1].t0) * dx1 - (v->fbi.svert[0].t0 - v->fbi.svert[2].t0) * dx2) * tdiv;
	5561	v->tmu[0].dtdy = v->tmu[1].dtdy = ((v->fbi.svert[0].t0 - v->fbi.svert[2].t0) * dy1 - (v->fbi.svert[0].t0 - v->fbi.svert[1].t0) * dy2) * tdiv;
5489	5562	}
5490	5563
5491	5564	/* set up W1 */
5492		if (vd->reg[sSetupMode].u & (1 << 6))
	5565	if (v->reg[sSetupMode].u & (1 << 6))
5493	5566	{
5494		vd->tmu[1].startw = (INT64)(vd->fbi.svert[0].w1 * 65536.0f * 65536.0f);
5495		vd->tmu[1].dwdx = ((vd->fbi.svert[0].w1 - vd->fbi.svert[1].w1) * dx1 - (vd->fbi.svert[0].w1 - vd->fbi.svert[2].w1) * dx2) * tdiv;
5496		vd->tmu[1].dwdy = ((vd->fbi.svert[0].w1 - vd->fbi.svert[2].w1) * dy1 - (vd->fbi.svert[0].w1 - vd->fbi.svert[1].w1) * dy2) * tdiv;
	5567	v->tmu[1].startw = (INT64)(v->fbi.svert[0].w1 * 65536.0f * 65536.0f);
	5568	v->tmu[1].dwdx = ((v->fbi.svert[0].w1 - v->fbi.svert[1].w1) * dx1 - (v->fbi.svert[0].w1 - v->fbi.svert[2].w1) * dx2) * tdiv;
	5569	v->tmu[1].dwdy = ((v->fbi.svert[0].w1 - v->fbi.svert[2].w1) * dy1 - (v->fbi.svert[0].w1 - v->fbi.svert[1].w1) * dy2) * tdiv;
5497	5570	}
5498	5571
5499	5572	/* set up S1,T1 */
5500		if (vd->reg[sSetupMode].u & (1 << 7))
	5573	if (v->reg[sSetupMode].u & (1 << 7))
5501	5574	{
5502		vd->tmu[1].starts = (INT64)(vd->fbi.svert[0].s1 * 65536.0f * 65536.0f);
5503		vd->tmu[1].dsdx = ((vd->fbi.svert[0].s1 - vd->fbi.svert[1].s1) * dx1 - (vd->fbi.svert[0].s1 - vd->fbi.svert[2].s1) * dx2) * tdiv;
5504		vd->tmu[1].dsdy = ((vd->fbi.svert[0].s1 - vd->fbi.svert[2].s1) * dy1 - (vd->fbi.svert[0].s1 - vd->fbi.svert[1].s1) * dy2) * tdiv;
5505		vd->tmu[1].startt = (INT64)(vd->fbi.svert[0].t1 * 65536.0f * 65536.0f);
5506		vd->tmu[1].dtdx = ((vd->fbi.svert[0].t1 - vd->fbi.svert[1].t1) * dx1 - (vd->fbi.svert[0].t1 - vd->fbi.svert[2].t1) * dx2) * tdiv;
5507		vd->tmu[1].dtdy = ((vd->fbi.svert[0].t1 - vd->fbi.svert[2].t1) * dy1 - (vd->fbi.svert[0].t1 - vd->fbi.svert[1].t1) * dy2) * tdiv;
	5575	v->tmu[1].starts = (INT64)(v->fbi.svert[0].s1 * 65536.0f * 65536.0f);
	5576	v->tmu[1].dsdx = ((v->fbi.svert[0].s1 - v->fbi.svert[1].s1) * dx1 - (v->fbi.svert[0].s1 - v->fbi.svert[2].s1) * dx2) * tdiv;
	5577	v->tmu[1].dsdy = ((v->fbi.svert[0].s1 - v->fbi.svert[2].s1) * dy1 - (v->fbi.svert[0].s1 - v->fbi.svert[1].s1) * dy2) * tdiv;
	5578	v->tmu[1].startt = (INT64)(v->fbi.svert[0].t1 * 65536.0f * 65536.0f);
	5579	v->tmu[1].dtdx = ((v->fbi.svert[0].t1 - v->fbi.svert[1].t1) * dx1 - (v->fbi.svert[0].t1 - v->fbi.svert[2].t1) * dx2) * tdiv;
	5580	v->tmu[1].dtdy = ((v->fbi.svert[0].t1 - v->fbi.svert[2].t1) * dy1 - (v->fbi.svert[0].t1 - v->fbi.svert[1].t1) * dy2) * tdiv;
5508	5581	}
5509	5582
5510	5583	/* draw the triangle */
5511		vd->fbi.cheating_allowed = 1;
5512		return triangle(vd);
	5584	v->fbi.cheating_allowed = 1;
	5585	return triangle(v);
5513	5586	}
5514	5587
5515	5588
r253151	r253152
5518	5591	setup and create the work item
5519	5592	-------------------------------------------------*/
5520	5593
5521		INT32 ~~voodoo_device::~~triangle_create_work_item(voodoo_device* vd, UINT16 *drawbuf, int texcount)
	5594	static INT32 triangle_create_work_item(voodoo_state v, UINT16 drawbuf, int texcount)
5522	5595	{
5523		poly_extra_data extra = (poly_extra_data )poly_get_extra_data(vd->poly);
5524
5525		raster_info *info = find_rasterizer(vd, texcount);
	5596	poly_extra_data extra = (poly_extra_data )poly_get_extra_data(v->poly);
	5597	raster_info *info = find_rasterizer(v, texcount);
5526	5598	poly_vertex vert[3];
5527	5599
5528	5600	/* fill in the vertex data */
5529		vert[0].x = (float)vd->fbi.ax * (1.0f / 16.0f);
5530		vert[0].y = (float)vd->fbi.ay * (1.0f / 16.0f);
5531		vert[1].x = (float)vd->fbi.bx * (1.0f / 16.0f);
5532		vert[1].y = (float)vd->fbi.by * (1.0f / 16.0f);
5533		vert[2].x = (float)vd->fbi.cx * (1.0f / 16.0f);
5534		vert[2].y = (float)vd->fbi.cy * (1.0f / 16.0f);
	5601	vert[0].x = (float)v->fbi.ax * (1.0f / 16.0f);
	5602	vert[0].y = (float)v->fbi.ay * (1.0f / 16.0f);
	5603	vert[1].x = (float)v->fbi.bx * (1.0f / 16.0f);
	5604	vert[1].y = (float)v->fbi.by * (1.0f / 16.0f);
	5605	vert[2].x = (float)v->fbi.cx * (1.0f / 16.0f);
	5606	vert[2].y = (float)v->fbi.cy * (1.0f / 16.0f);
5535	5607
5536	5608	/* fill in the extra data */
5537		extra->de~~vice~~ = vd;
	5609	extra->state = v;
5538	5610	extra->info = info;
5539	5611
5540	5612	/* fill in triangle parameters */
5541		extra->ax = vd->fbi.ax;
5542		extra->ay = vd->fbi.ay;
5543		extra->startr = vd->fbi.startr;
5544		extra->startg = vd->fbi.startg;
5545		extra->startb = vd->fbi.startb;
5546		extra->starta = vd->fbi.starta;
5547		extra->startz = vd->fbi.startz;
5548		extra->startw = vd->fbi.startw;
5549		extra->drdx = vd->fbi.drdx;
5550		extra->dgdx = vd->fbi.dgdx;
5551		extra->dbdx = vd->fbi.dbdx;
5552		extra->dadx = vd->fbi.dadx;
5553		extra->dzdx = vd->fbi.dzdx;
5554		extra->dwdx = vd->fbi.dwdx;
5555		extra->drdy = vd->fbi.drdy;
5556		extra->dgdy = vd->fbi.dgdy;
5557		extra->dbdy = vd->fbi.dbdy;
5558		extra->dady = vd->fbi.dady;
5559		extra->dzdy = vd->fbi.dzdy;
5560		extra->dwdy = vd->fbi.dwdy;
	5613	extra->ax = v->fbi.ax;
	5614	extra->ay = v->fbi.ay;
	5615	extra->startr = v->fbi.startr;
	5616	extra->startg = v->fbi.startg;
	5617	extra->startb = v->fbi.startb;
	5618	extra->starta = v->fbi.starta;
	5619	extra->startz = v->fbi.startz;
	5620	extra->startw = v->fbi.startw;
	5621	extra->drdx = v->fbi.drdx;
	5622	extra->dgdx = v->fbi.dgdx;
	5623	extra->dbdx = v->fbi.dbdx;
	5624	extra->dadx = v->fbi.dadx;
	5625	extra->dzdx = v->fbi.dzdx;
	5626	extra->dwdx = v->fbi.dwdx;
	5627	extra->drdy = v->fbi.drdy;
	5628	extra->dgdy = v->fbi.dgdy;
	5629	extra->dbdy = v->fbi.dbdy;
	5630	extra->dady = v->fbi.dady;
	5631	extra->dzdy = v->fbi.dzdy;
	5632	extra->dwdy = v->fbi.dwdy;
5561	5633
5562	5634	/* fill in texture 0 parameters */
5563	5635	if (texcount > 0)
5564	5636	{
5565		extra->starts0 = vd->tmu[0].starts;
5566		extra->startt0 = vd->tmu[0].startt;
5567		extra->startw0 = vd->tmu[0].startw;
5568		extra->ds0dx = vd->tmu[0].dsdx;
5569		extra->dt0dx = vd->tmu[0].dtdx;
5570		extra->dw0dx = vd->tmu[0].dwdx;
5571		extra->ds0dy = vd->tmu[0].dsdy;
5572		extra->dt0dy = vd->tmu[0].dtdy;
5573		extra->dw0dy = vd->tmu[0].dwdy;
5574		extra->lodbase0 = prepare_tmu(&vd->tmu[0]);
5575		vd->stats.texture_mode[TEXMODE_FORMAT(vd->tmu[0].reg[textureMode].u)]++;
	5637	extra->starts0 = v->tmu[0].starts;
	5638	extra->startt0 = v->tmu[0].startt;
	5639	extra->startw0 = v->tmu[0].startw;
	5640	extra->ds0dx = v->tmu[0].dsdx;
	5641	extra->dt0dx = v->tmu[0].dtdx;
	5642	extra->dw0dx = v->tmu[0].dwdx;
	5643	extra->ds0dy = v->tmu[0].dsdy;
	5644	extra->dt0dy = v->tmu[0].dtdy;
	5645	extra->dw0dy = v->tmu[0].dwdy;
	5646	extra->lodbase0 = prepare_tmu(&v->tmu[0]);
	5647	v->stats.texture_mode[TEXMODE_FORMAT(v->tmu[0].reg[textureMode].u)]++;
5576	5648
5577	5649	/* fill in texture 1 parameters */
5578	5650	if (texcount > 1)
5579	5651	{
5580		extra->starts1 = vd->tmu[1].starts;
5581		extra->startt1 = vd->tmu[1].startt;
5582		extra->startw1 = vd->tmu[1].startw;
5583		extra->ds1dx = vd->tmu[1].dsdx;
5584		extra->dt1dx = vd->tmu[1].dtdx;
5585		extra->dw1dx = vd->tmu[1].dwdx;
5586		extra->ds1dy = vd->tmu[1].dsdy;
5587		extra->dt1dy = vd->tmu[1].dtdy;
5588		extra->dw1dy = vd->tmu[1].dwdy;
5589		extra->lodbase1 = prepare_tmu(&vd->tmu[1]);
5590		vd->stats.texture_mode[TEXMODE_FORMAT(vd->tmu[1].reg[textureMode].u)]++;
	5652	extra->starts1 = v->tmu[1].starts;
	5653	extra->startt1 = v->tmu[1].startt;
	5654	extra->startw1 = v->tmu[1].startw;
	5655	extra->ds1dx = v->tmu[1].dsdx;
	5656	extra->dt1dx = v->tmu[1].dtdx;
	5657	extra->dw1dx = v->tmu[1].dwdx;
	5658	extra->ds1dy = v->tmu[1].dsdy;
	5659	extra->dt1dy = v->tmu[1].dtdy;
	5660	extra->dw1dy = v->tmu[1].dwdy;
	5661	extra->lodbase1 = prepare_tmu(&v->tmu[1]);
	5662	v->stats.texture_mode[TEXMODE_FORMAT(v->tmu[1].reg[textureMode].u)]++;
5591	5663	}
5592	5664	}
5593	5665
5594	5666	/* farm the rasterization out to other threads */
5595	5667	info->polys++;
5596		return poly_render_triangle(vd->poly, drawbuf, global_cliprect, info->callback, 0, &vert[0], &vert[1], &vert[2]);
	5668	return poly_render_triangle(v->poly, drawbuf, global_cliprect, info->callback, 0, &vert[0], &vert[1], &vert[2]);
5597	5669	}
5598	5670
5599	5671
r253151	r253152
5607	5679	hash table
5608	5680	-------------------------------------------------*/
5609	5681
5610		raster_info ~~voodoo_device::~~add_rasterizer(voodoo_de~~vice~~ vd, const raster_info *cinfo)
	5682	static raster_info add_rasterizer(voodoo_state v, const raster_info *cinfo)
5611	5683	{
5612		raster_info *info = &vd->rasterizer[vd->next_rasterizer++];
	5684	raster_info *info = &v->rasterizer[v->next_rasterizer++];
5613	5685	int hash = compute_raster_hash(cinfo);
5614	5686
5615		assert_always(vd->next_rasterizer <= MAX_RASTERIZERS, "Out of space for new rasterizers!");
	5687	assert_always(v->next_rasterizer <= MAX_RASTERIZERS, "Out of space for new rasterizers!");
5616	5688
5617	5689	/* make a copy of the info */
5618	5690	info = cinfo;
r253151	r253152
5623	5695	info->hash = hash;
5624	5696
5625	5697	/* hook us into the hash table */
5626		info->next = vd->raster_hash[hash];
5627		vd->raster_hash[hash] = info;
	5698	info->next = v->raster_hash[hash];
	5699	v->raster_hash[hash] = info;
5628	5700
5629	5701	if (LOG_RASTERIZERS)
5630	5702	printf("Adding rasterizer @ %p : cp=%08X am=%08X %08X fbzM=%08X tm0=%08X tm1=%08X (hash=%d)\n",
r253151	r253152
5642	5714	it, creating a new one if necessary
5643	5715	-------------------------------------------------*/
5644	5716
5645		raster_info ~~voodoo_device::~~find_rasterizer(voodoo_de~~vice~~ vd, int texcount)
	5717	static raster_info find_rasterizer(voodoo_state v, int texcount)
5646	5718	{
5647	5719	raster_info info, prev = nullptr;
5648	5720	raster_info curinfo;
5649	5721	int hash;
5650	5722
5651	5723	/* build an info struct with all the parameters */
5652		curinfo.eff_color_path = normalize_color_path(vd->reg[fbzColorPath].u);
5653		curinfo.eff_alpha_mode = normalize_alpha_mode(vd->reg[alphaMode].u);
5654		curinfo.eff_fog_mode = normalize_fog_mode(vd->reg[fogMode].u);
5655		curinfo.eff_fbz_mode = normalize_fbz_mode(vd->reg[fbzMode].u);
5656		curinfo.eff_tex_mode_0 = (texcount >= 1) ? normalize_tex_mode(vd->tmu[0].reg[textureMode].u) : 0xffffffff;
5657		curinfo.eff_tex_mode_1 = (texcount >= 2) ? normalize_tex_mode(vd->tmu[1].reg[textureMode].u) : 0xffffffff;
	5724	curinfo.eff_color_path = normalize_color_path(v->reg[fbzColorPath].u);
	5725	curinfo.eff_alpha_mode = normalize_alpha_mode(v->reg[alphaMode].u);
	5726	curinfo.eff_fog_mode = normalize_fog_mode(v->reg[fogMode].u);
	5727	curinfo.eff_fbz_mode = normalize_fbz_mode(v->reg[fbzMode].u);
	5728	curinfo.eff_tex_mode_0 = (texcount >= 1) ? normalize_tex_mode(v->tmu[0].reg[textureMode].u) : 0xffffffff;
	5729	curinfo.eff_tex_mode_1 = (texcount >= 2) ? normalize_tex_mode(v->tmu[1].reg[textureMode].u) : 0xffffffff;
5658	5730
5659	5731	/* compute the hash */
5660	5732	hash = compute_raster_hash(&curinfo);
5661	5733
5662	5734	/* find the appropriate hash entry */
5663		for (info = vd->raster_hash[hash]; info; prev = info, info = info->next)
	5735	for (info = v->raster_hash[hash]; info; prev = info, info = info->next)
5664	5736	if (info->eff_color_path == curinfo.eff_color_path &&
5665	5737	info->eff_alpha_mode == curinfo.eff_alpha_mode &&
5666	5738	info->eff_fog_mode == curinfo.eff_fog_mode &&
r253151	r253152
5672	5744	if (prev)
5673	5745	{
5674	5746	prev->next = info->next;
5675		info->next = vd->raster_hash[hash];
5676		vd->raster_hash[hash] = info;
	5747	info->next = v->raster_hash[hash];
	5748	v->raster_hash[hash] = info;
5677	5749	}
5678	5750
5679	5751	/* return the result */
r253151	r253152
5689	5761	curinfo.next = nullptr;
5690	5762	curinfo.hash = hash;
5691	5763
5692		return add_rasterizer(vd, &curinfo);
	5764	return add_rasterizer(v, &curinfo);
5693	5765	}
5694	5766
5695	5767
r253151	r253152
5698	5770	the current rasterizer usage patterns
5699	5771	-------------------------------------------------*/
5700	5772
5701		void vo~~odoo_dev~~i~~ce::~~dump_rasterizer_stats(voodoo_de~~vice~~ *vd)
	5773	static void dump_rasterizer_stats(voodoo_state *v)
5702	5774	{
5703	5775	static UINT8 display_index;
5704	5776	raster_info cur, best;
r253151	r253152
5714	5786
5715	5787	/* find the highest entry */
5716	5788	for (hash = 0; hash < RASTER_HASH_SIZE; hash++)
5717		for (cur = vd->raster_hash[hash]; cur; cur = cur->next)
	5789	for (cur = v->raster_hash[hash]; cur; cur = cur->next)
5718	5790	if (cur->display != display_index && (best == nullptr \|\| cur->hits > best->hits))
5719	5791	best = cur;
5720	5792
r253151	r253152
5750	5822	m_vblank(*this),
5751	5823	m_stall(*this)
5752	5824	{
	5825	m_token = global_alloc_clear<voodoo_state>();
5753	5826	}
5754	5827
5755	5828	voodoo_device::~voodoo_device()
5756	5829	{
	5830	global_free(m_token);
5757	5831	}
5758	5832
5759	5833	//-------------------------------------------------
r253151	r253152
5772	5846
5773	5847	void voodoo_device::device_reset()
5774	5848	{
5775		soft_reset(this);
	5849	voodoo_state *v = get_safe_token(this);
	5850	soft_reset(v);
5776	5851	}
5777	5852
5778	5853	//-------------------------------------------------
r253151	r253152
5781	5856
5782	5857	void voodoo_device::device_stop()
5783	5858	{
	5859	voodoo_state *v = get_safe_token(this);
	5860
5784	5861	/* release the work queue, ensuring all work is finished */
5785		if (poly != nullptr)
5786		poly_free(poly);
	5862	if (v->poly != nullptr)
	5863	poly_free(v->poly);
5787	5864	}
5788	5865
5789	5866
r253151	r253152
5870	5947	implementation of the 'fastfill' command
5871	5948	-------------------------------------------------*/
5872	5949
5873		void vo~~odoo_dev~~i~~ce::~~raster_fastfill(void destbase, INT32 y, const poly_extent extent, const void *extradata, int threadid)
	5950	static void raster_fastfill(void destbase, INT32 y, const poly_extent extent, const void *extradata, int threadid)
5874	5951	{
5875	5952	const poly_extra_data extra = (const poly_extra_data )extradata;
5876		voodoo_device* vd = extra->device;
5877		stats_block *stats = &vd->thread_stats[threadid];
	5953	voodoo_state *v = extra->state;
	5954	stats_block *stats = &v->thread_stats[threadid];
5878	5955	INT32 startx = extent->startx;
5879	5956	INT32 stopx = extent->stopx;
5880	5957	int scry, x;
5881	5958
5882	5959	/* determine the screen Y */
5883	5960	scry = y;
5884		if (FBZMODE_Y_ORIGIN(vd->reg[fbzMode].u))
5885		scry = (vd->fbi.yorigin - y) & 0x3ff;
	5961	if (FBZMODE_Y_ORIGIN(v->reg[fbzMode].u))
	5962	scry = (v->fbi.yorigin - y) & 0x3ff;
5886	5963
5887	5964	/* fill this RGB row */
5888		if (FBZMODE_RGB_BUFFER_MASK(vd->reg[fbzMode].u))
	5965	if (FBZMODE_RGB_BUFFER_MASK(v->reg[fbzMode].u))
5889	5966	{
5890	5967	const UINT16 ditherow = &extra->dither[(y & 3) 4];
5891	5968	UINT64 expanded = (UINT64 )ditherow;
5892		UINT16 dest = (UINT16 )destbase + scry * vd->fbi.rowpixels;
	5969	UINT16 dest = (UINT16 )destbase + scry * v->fbi.rowpixels;
5893	5970
5894	5971	for (x = startx; x < stopx && (x & 3) != 0; x++)
5895	5972	dest[x] = ditherow[x & 3];
r253151	r253152
5901	5978	}
5902	5979
5903	5980	/* fill this dest buffer row */
5904		if (FBZMODE_AUX_BUFFER_MASK(vd->reg[fbzMode].u) && vd->fbi.auxoffs != ~0)
	5981	if (FBZMODE_AUX_BUFFER_MASK(v->reg[fbzMode].u) && v->fbi.auxoffs != ~0)
5905	5982	{
5906		UINT16 color = vd->reg[zaColor].u;
	5983	UINT16 color = v->reg[zaColor].u;
5907	5984	UINT64 expanded = ((UINT64)color << 48) \| ((UINT64)color << 32) \| (color << 16) \| color;
5908		UINT16 dest = (UINT16 )(vd->fbi.ram + vd->fbi.auxoffs) + scry * vd->fbi.rowpixels;
	5985	UINT16 dest = (UINT16 )(v->fbi.ram + v->fbi.auxoffs) + scry * v->fbi.rowpixels;
5909	5986
5910	5987	for (x = startx; x < stopx && (x & 3) != 0; x++)
5911	5988	dest[x] = color;
r253151	r253152
5921	5998	generic_0tmu - generic rasterizer for 0 TMUs
5922	5999	-------------------------------------------------*/
5923	6000
5924		RASTERIZER(generic_0tmu, 0, vd->reg[fbzColorPath].u, vd->reg[fbzMode].u, vd->reg[alphaMode].u,
5925		vd->reg[fogMode].u, 0, 0)
	6001	RASTERIZER(generic_0tmu, 0, v->reg[fbzColorPath].u, v->reg[fbzMode].u, v->reg[alphaMode].u,
	6002	v->reg[fogMode].u, 0, 0)
5926	6003
5927	6004
5928	6005	/*-------------------------------------------------
5929	6006	generic_1tmu - generic rasterizer for 1 TMU
5930	6007	-------------------------------------------------*/
5931	6008
5932		RASTERIZER(generic_1tmu, 1, vd->reg[fbzColorPath].u, vd->reg[fbzMode].u, vd->reg[alphaMode].u,
5933		vd->reg[fogMode].u, vd->tmu[0].reg[textureMode].u, 0)
	6009	RASTERIZER(generic_1tmu, 1, v->reg[fbzColorPath].u, v->reg[fbzMode].u, v->reg[alphaMode].u,
	6010	v->reg[fogMode].u, v->tmu[0].reg[textureMode].u, 0)
5934	6011
5935	6012
5936	6013	/*-------------------------------------------------
5937	6014	generic_2tmu - generic rasterizer for 2 TMUs
5938	6015	-------------------------------------------------*/
5939	6016
5940		RASTERIZER(generic_2tmu, 2, vd->reg[fbzColorPath].u, vd->reg[fbzMode].u, vd->reg[alphaMode].u,
5941		vd->reg[fogMode].u, vd->tmu[0].reg[textureMode].u, vd->tmu[1].reg[textureMode].u)
	6017	RASTERIZER(generic_2tmu, 2, v->reg[fbzColorPath].u, v->reg[fbzMode].u, v->reg[alphaMode].u,
	6018	v->reg[fogMode].u, v->tmu[0].reg[textureMode].u, v->tmu[1].reg[textureMode].u)

trunk/src/devices/video/voodoo.h
r253151	r253152
11	11	#ifndef __VOODOO_H__
12	12	#define __VOODOO_H__
13	13
14		#include "video/polylgcy.h"
15
16	14	#pragma once
17	15
18	16
19		/*************************************
20		*
21		* Misc. constants
22		*
23		*************************************/
24	17
25		/* enumeration describing reasons we might be stalled */
26		enum
27		{
28		NOT_STALLED = 0,
29		STALLED_UNTIL_FIFO_LWM,
30		STALLED_UNTIL_FIFO_EMPTY
31		};
32
33
34
35		// Use old table lookup versus straight double divide
36		#define USE_FAST_RECIP 0
37
38		/* maximum number of TMUs */
39		#define MAX_TMU 2
40
41		/* accumulate operations less than this number of clocks */
42		#define ACCUMULATE_THRESHOLD 0
43
44		/* number of clocks to set up a triangle (just a guess) */
45		#define TRIANGLE_SETUP_CLOCKS 100
46
47		/* maximum number of rasterizers */
48		#define MAX_RASTERIZERS 1024
49
50		/* size of the rasterizer hash table */
51		#define RASTER_HASH_SIZE 97
52
53		/* flags for LFB writes */
54		#define LFB_RGB_PRESENT 1
55		#define LFB_ALPHA_PRESENT 2
56		#define LFB_DEPTH_PRESENT 4
57		#define LFB_DEPTH_PRESENT_MSW 8
58
59		/* flags for the register access array */
60		#define REGISTER_READ 0x01 /* reads are allowed */
61		#define REGISTER_WRITE 0x02 /* writes are allowed */
62		#define REGISTER_PIPELINED 0x04 /* writes are pipelined */
63		#define REGISTER_FIFO 0x08 /* writes go to FIFO */
64		#define REGISTER_WRITETHRU 0x10 /* writes are valid even for CMDFIFO */
65
66		/* shorter combinations to make the table smaller */
67		#define REG_R (REGISTER_READ)
68		#define REG_W (REGISTER_WRITE)
69		#define REG_WT (REGISTER_WRITE \| REGISTER_WRITETHRU)
70		#define REG_RW (REGISTER_READ \| REGISTER_WRITE)
71		#define REG_RWT (REGISTER_READ \| REGISTER_WRITE \| REGISTER_WRITETHRU)
72		#define REG_RP (REGISTER_READ \| REGISTER_PIPELINED)
73		#define REG_WP (REGISTER_WRITE \| REGISTER_PIPELINED)
74		#define REG_RWP (REGISTER_READ \| REGISTER_WRITE \| REGISTER_PIPELINED)
75		#define REG_RWPT (REGISTER_READ \| REGISTER_WRITE \| REGISTER_PIPELINED \| REGISTER_WRITETHRU)
76		#define REG_RF (REGISTER_READ \| REGISTER_FIFO)
77		#define REG_WF (REGISTER_WRITE \| REGISTER_FIFO)
78		#define REG_RWF (REGISTER_READ \| REGISTER_WRITE \| REGISTER_FIFO)
79		#define REG_RPF (REGISTER_READ \| REGISTER_PIPELINED \| REGISTER_FIFO)
80		#define REG_WPF (REGISTER_WRITE \| REGISTER_PIPELINED \| REGISTER_FIFO)
81		#define REG_RWPF (REGISTER_READ \| REGISTER_WRITE \| REGISTER_PIPELINED \| REGISTER_FIFO)
82
83		/* lookup bits is the log2 of the size of the reciprocal/log table */
84		#define RECIPLOG_LOOKUP_BITS 9
85
86		/* input precision is how many fraction bits the input value has; this is a 64-bit number */
87		#define RECIPLOG_INPUT_PREC 32
88
89		/* lookup precision is how many fraction bits each table entry contains */
90		#define RECIPLOG_LOOKUP_PREC 22
91
92		/* output precision is how many fraction bits the result should have */
93		#define RECIP_OUTPUT_PREC 15
94		#define LOG_OUTPUT_PREC 8
95
96
97
98		/*************************************
99		*
100		* Register constants
101		*
102		*************************************/
103
104		/* Codes to the right:
105		R = readable
106		W = writeable
107		P = pipelined
108		F = goes to FIFO
109		*/
110
111		/* 0x000 */
112		#define vdstatus (0x000/4) /* R P */
113		#define intrCtrl (0x004/4) /* RW P -- Voodoo2/Banshee only */
114		#define vertexAx (0x008/4) /* W PF */
115		#define vertexAy (0x00c/4) /* W PF */
116		#define vertexBx (0x010/4) /* W PF */
117		#define vertexBy (0x014/4) /* W PF */
118		#define vertexCx (0x018/4) /* W PF */
119		#define vertexCy (0x01c/4) /* W PF */
120		#define startR (0x020/4) /* W PF */
121		#define startG (0x024/4) /* W PF */
122		#define startB (0x028/4) /* W PF */
123		#define startZ (0x02c/4) /* W PF */
124		#define startA (0x030/4) /* W PF */
125		#define startS (0x034/4) /* W PF */
126		#define startT (0x038/4) /* W PF */
127		#define startW (0x03c/4) /* W PF */
128
129		/* 0x040 */
130		#define dRdX (0x040/4) /* W PF */
131		#define dGdX (0x044/4) /* W PF */
132		#define dBdX (0x048/4) /* W PF */
133		#define dZdX (0x04c/4) /* W PF */
134		#define dAdX (0x050/4) /* W PF */
135		#define dSdX (0x054/4) /* W PF */
136		#define dTdX (0x058/4) /* W PF */
137		#define dWdX (0x05c/4) /* W PF */
138		#define dRdY (0x060/4) /* W PF */
139		#define dGdY (0x064/4) /* W PF */
140		#define dBdY (0x068/4) /* W PF */
141		#define dZdY (0x06c/4) /* W PF */
142		#define dAdY (0x070/4) /* W PF */
143		#define dSdY (0x074/4) /* W PF */
144		#define dTdY (0x078/4) /* W PF */
145		#define dWdY (0x07c/4) /* W PF */
146
147		/* 0x080 */
148		#define triangleCMD (0x080/4) /* W PF */
149		#define fvertexAx (0x088/4) /* W PF */
150		#define fvertexAy (0x08c/4) /* W PF */
151		#define fvertexBx (0x090/4) /* W PF */
152		#define fvertexBy (0x094/4) /* W PF */
153		#define fvertexCx (0x098/4) /* W PF */
154		#define fvertexCy (0x09c/4) /* W PF */
155		#define fstartR (0x0a0/4) /* W PF */
156		#define fstartG (0x0a4/4) /* W PF */
157		#define fstartB (0x0a8/4) /* W PF */
158		#define fstartZ (0x0ac/4) /* W PF */
159		#define fstartA (0x0b0/4) /* W PF */
160		#define fstartS (0x0b4/4) /* W PF */
161		#define fstartT (0x0b8/4) /* W PF */
162		#define fstartW (0x0bc/4) /* W PF */
163
164		/* 0x0c0 */
165		#define fdRdX (0x0c0/4) /* W PF */
166		#define fdGdX (0x0c4/4) /* W PF */
167		#define fdBdX (0x0c8/4) /* W PF */
168		#define fdZdX (0x0cc/4) /* W PF */
169		#define fdAdX (0x0d0/4) /* W PF */
170		#define fdSdX (0x0d4/4) /* W PF */
171		#define fdTdX (0x0d8/4) /* W PF */
172		#define fdWdX (0x0dc/4) /* W PF */
173		#define fdRdY (0x0e0/4) /* W PF */
174		#define fdGdY (0x0e4/4) /* W PF */
175		#define fdBdY (0x0e8/4) /* W PF */
176		#define fdZdY (0x0ec/4) /* W PF */
177		#define fdAdY (0x0f0/4) /* W PF */
178		#define fdSdY (0x0f4/4) /* W PF */
179		#define fdTdY (0x0f8/4) /* W PF */
180		#define fdWdY (0x0fc/4) /* W PF */
181
182		/* 0x100 */
183		#define ftriangleCMD (0x100/4) /* W PF */
184		#define fbzColorPath (0x104/4) /* RW PF */
185		#define fogMode (0x108/4) /* RW PF */
186		#define alphaMode (0x10c/4) /* RW PF */
187		#define fbzMode (0x110/4) /* RW F */
188		#define lfbMode (0x114/4) /* RW F */
189		#define clipLeftRight (0x118/4) /* RW F */
190		#define clipLowYHighY (0x11c/4) /* RW F */
191		#define nopCMD (0x120/4) /* W F */
192		#define fastfillCMD (0x124/4) /* W F */
193		#define swapbufferCMD (0x128/4) /* W F */
194		#define fogColor (0x12c/4) /* W F */
195		#define zaColor (0x130/4) /* W F */
196		#define chromaKey (0x134/4) /* W F */
197		#define chromaRange (0x138/4) /* W F -- Voodoo2/Banshee only */
198		#define userIntrCMD (0x13c/4) /* W F -- Voodoo2/Banshee only */
199
200		/* 0x140 */
201		#define stipple (0x140/4) /* RW F */
202		#define color0 (0x144/4) /* RW F */
203		#define color1 (0x148/4) /* RW F */
204		#define fbiPixelsIn (0x14c/4) /* R */
205		#define fbiChromaFail (0x150/4) /* R */
206		#define fbiZfuncFail (0x154/4) /* R */
207		#define fbiAfuncFail (0x158/4) /* R */
208		#define fbiPixelsOut (0x15c/4) /* R */
209		#define fogTable (0x160/4) /* W F */
210
211		/* 0x1c0 */
212		#define cmdFifoBaseAddr (0x1e0/4) /* RW -- Voodoo2 only */
213		#define cmdFifoBump (0x1e4/4) /* RW -- Voodoo2 only */
214		#define cmdFifoRdPtr (0x1e8/4) /* RW -- Voodoo2 only */
215		#define cmdFifoAMin (0x1ec/4) /* RW -- Voodoo2 only */
216		#define colBufferAddr (0x1ec/4) /* RW -- Banshee only */
217		#define cmdFifoAMax (0x1f0/4) /* RW -- Voodoo2 only */
218		#define colBufferStride (0x1f0/4) /* RW -- Banshee only */
219		#define cmdFifoDepth (0x1f4/4) /* RW -- Voodoo2 only */
220		#define auxBufferAddr (0x1f4/4) /* RW -- Banshee only */
221		#define cmdFifoHoles (0x1f8/4) /* RW -- Voodoo2 only */
222		#define auxBufferStride (0x1f8/4) /* RW -- Banshee only */
223
224		/* 0x200 */
225		#define fbiInit4 (0x200/4) /* RW -- Voodoo/Voodoo2 only */
226		#define clipLeftRight1 (0x200/4) /* RW -- Banshee only */
227		#define vRetrace (0x204/4) /* R -- Voodoo/Voodoo2 only */
228		#define clipTopBottom1 (0x204/4) /* RW -- Banshee only */
229		#define backPorch (0x208/4) /* RW -- Voodoo/Voodoo2 only */
230		#define videoDimensions (0x20c/4) /* RW -- Voodoo/Voodoo2 only */
231		#define fbiInit0 (0x210/4) /* RW -- Voodoo/Voodoo2 only */
232		#define fbiInit1 (0x214/4) /* RW -- Voodoo/Voodoo2 only */
233		#define fbiInit2 (0x218/4) /* RW -- Voodoo/Voodoo2 only */
234		#define fbiInit3 (0x21c/4) /* RW -- Voodoo/Voodoo2 only */
235		#define hSync (0x220/4) /* W -- Voodoo/Voodoo2 only */
236		#define vSync (0x224/4) /* W -- Voodoo/Voodoo2 only */
237		#define clutData (0x228/4) /* W F -- Voodoo/Voodoo2 only */
238		#define dacData (0x22c/4) /* W -- Voodoo/Voodoo2 only */
239		#define maxRgbDelta (0x230/4) /* W -- Voodoo/Voodoo2 only */
240		#define hBorder (0x234/4) /* W -- Voodoo2 only */
241		#define vBorder (0x238/4) /* W -- Voodoo2 only */
242		#define borderColor (0x23c/4) /* W -- Voodoo2 only */
243
244		/* 0x240 */
245		#define hvRetrace (0x240/4) /* R -- Voodoo2 only */
246		#define fbiInit5 (0x244/4) /* RW -- Voodoo2 only */
247		#define fbiInit6 (0x248/4) /* RW -- Voodoo2 only */
248		#define fbiInit7 (0x24c/4) /* RW -- Voodoo2 only */
249		#define swapPending (0x24c/4) /* W -- Banshee only */
250		#define leftOverlayBuf (0x250/4) /* W -- Banshee only */
251		#define rightOverlayBuf (0x254/4) /* W -- Banshee only */
252		#define fbiSwapHistory (0x258/4) /* R -- Voodoo2/Banshee only */
253		#define fbiTrianglesOut (0x25c/4) /* R -- Voodoo2/Banshee only */
254		#define sSetupMode (0x260/4) /* W PF -- Voodoo2/Banshee only */
255		#define sVx (0x264/4) /* W PF -- Voodoo2/Banshee only */
256		#define sVy (0x268/4) /* W PF -- Voodoo2/Banshee only */
257		#define sARGB (0x26c/4) /* W PF -- Voodoo2/Banshee only */
258		#define sRed (0x270/4) /* W PF -- Voodoo2/Banshee only */
259		#define sGreen (0x274/4) /* W PF -- Voodoo2/Banshee only */
260		#define sBlue (0x278/4) /* W PF -- Voodoo2/Banshee only */
261		#define sAlpha (0x27c/4) /* W PF -- Voodoo2/Banshee only */
262
263		/* 0x280 */
264		#define sVz (0x280/4) /* W PF -- Voodoo2/Banshee only */
265		#define sWb (0x284/4) /* W PF -- Voodoo2/Banshee only */
266		#define sWtmu0 (0x288/4) /* W PF -- Voodoo2/Banshee only */
267		#define sS_W0 (0x28c/4) /* W PF -- Voodoo2/Banshee only */
268		#define sT_W0 (0x290/4) /* W PF -- Voodoo2/Banshee only */
269		#define sWtmu1 (0x294/4) /* W PF -- Voodoo2/Banshee only */
270		#define sS_Wtmu1 (0x298/4) /* W PF -- Voodoo2/Banshee only */
271		#define sT_Wtmu1 (0x29c/4) /* W PF -- Voodoo2/Banshee only */
272		#define sDrawTriCMD (0x2a0/4) /* W PF -- Voodoo2/Banshee only */
273		#define sBeginTriCMD (0x2a4/4) /* W PF -- Voodoo2/Banshee only */
274
275		/* 0x2c0 */
276		#define bltSrcBaseAddr (0x2c0/4) /* RW PF -- Voodoo2 only */
277		#define bltDstBaseAddr (0x2c4/4) /* RW PF -- Voodoo2 only */
278		#define bltXYStrides (0x2c8/4) /* RW PF -- Voodoo2 only */
279		#define bltSrcChromaRange (0x2cc/4) /* RW PF -- Voodoo2 only */
280		#define bltDstChromaRange (0x2d0/4) /* RW PF -- Voodoo2 only */
281		#define bltClipX (0x2d4/4) /* RW PF -- Voodoo2 only */
282		#define bltClipY (0x2d8/4) /* RW PF -- Voodoo2 only */
283		#define bltSrcXY (0x2e0/4) /* RW PF -- Voodoo2 only */
284		#define bltDstXY (0x2e4/4) /* RW PF -- Voodoo2 only */
285		#define bltSize (0x2e8/4) /* RW PF -- Voodoo2 only */
286		#define bltRop (0x2ec/4) /* RW PF -- Voodoo2 only */
287		#define bltColor (0x2f0/4) /* RW PF -- Voodoo2 only */
288		#define bltCommand (0x2f8/4) /* RW PF -- Voodoo2 only */
289		#define bltData (0x2fc/4) /* W PF -- Voodoo2 only */
290
291		/* 0x300 */
292		#define textureMode (0x300/4) /* W PF */
293		#define tLOD (0x304/4) /* W PF */
294		#define tDetail (0x308/4) /* W PF */
295		#define texBaseAddr (0x30c/4) /* W PF */
296		#define texBaseAddr_1 (0x310/4) /* W PF */
297		#define texBaseAddr_2 (0x314/4) /* W PF */
298		#define texBaseAddr_3_8 (0x318/4) /* W PF */
299		#define trexInit0 (0x31c/4) /* W F -- Voodoo/Voodoo2 only */
300		#define trexInit1 (0x320/4) /* W F */
301		#define nccTable (0x324/4) /* W F */
302
303
304
305		// 2D registers
306		#define banshee2D_clip0Min (0x008/4)
307		#define banshee2D_clip0Max (0x00c/4)
308		#define banshee2D_dstBaseAddr (0x010/4)
309		#define banshee2D_dstFormat (0x014/4)
310		#define banshee2D_srcColorkeyMin (0x018/4)
311		#define banshee2D_srcColorkeyMax (0x01c/4)
312		#define banshee2D_dstColorkeyMin (0x020/4)
313		#define banshee2D_dstColorkeyMax (0x024/4)
314		#define banshee2D_bresError0 (0x028/4)
315		#define banshee2D_bresError1 (0x02c/4)
316		#define banshee2D_rop (0x030/4)
317		#define banshee2D_srcBaseAddr (0x034/4)
318		#define banshee2D_commandExtra (0x038/4)
319		#define banshee2D_lineStipple (0x03c/4)
320		#define banshee2D_lineStyle (0x040/4)
321		#define banshee2D_pattern0Alias (0x044/4)
322		#define banshee2D_pattern1Alias (0x048/4)
323		#define banshee2D_clip1Min (0x04c/4)
324		#define banshee2D_clip1Max (0x050/4)
325		#define banshee2D_srcFormat (0x054/4)
326		#define banshee2D_srcSize (0x058/4)
327		#define banshee2D_srcXY (0x05c/4)
328		#define banshee2D_colorBack (0x060/4)
329		#define banshee2D_colorFore (0x064/4)
330		#define banshee2D_dstSize (0x068/4)
331		#define banshee2D_dstXY (0x06c/4)
332		#define banshee2D_command (0x070/4)
333
334
335		/*************************************
336		*
337		* Alias map of the first 64
338		* registers when remapped
339		*
340		*************************************/
341
342		static const UINT8 register_alias_map[0x40] =
343		{
344		vdstatus, 0x004/4, vertexAx, vertexAy,
345		vertexBx, vertexBy, vertexCx, vertexCy,
346		startR, dRdX, dRdY, startG,
347		dGdX, dGdY, startB, dBdX,
348		dBdY, startZ, dZdX, dZdY,
349		startA, dAdX, dAdY, startS,
350		dSdX, dSdY, startT, dTdX,
351		dTdY, startW, dWdX, dWdY,
352
353		triangleCMD,0x084/4, fvertexAx, fvertexAy,
354		fvertexBx, fvertexBy, fvertexCx, fvertexCy,
355		fstartR, fdRdX, fdRdY, fstartG,
356		fdGdX, fdGdY, fstartB, fdBdX,
357		fdBdY, fstartZ, fdZdX, fdZdY,
358		fstartA, fdAdX, fdAdY, fstartS,
359		fdSdX, fdSdY, fstartT, fdTdX,
360		fdTdY, fstartW, fdWdX, fdWdY
361		};
362
363
364
365		/*************************************
366		*
367		* Table of per-register access rights
368		*
369		*************************************/
370
371		static const UINT8 voodoo_register_access[0x100] =
372		{
373		/* 0x000 */
374		REG_RP, 0, REG_WPF, REG_WPF,
375		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
376		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
377		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
378
379		/* 0x040 */
380		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
381		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
382		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
383		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
384
385		/* 0x080 */
386		REG_WPF, 0, REG_WPF, REG_WPF,
387		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
388		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
389		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
390
391		/* 0x0c0 */
392		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
393		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
394		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
395		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
396
397		/* 0x100 */
398		REG_WPF, REG_RWPF, REG_RWPF, REG_RWPF,
399		REG_RWF, REG_RWF, REG_RWF, REG_RWF,
400		REG_WF, REG_WF, REG_WF, REG_WF,
401		REG_WF, REG_WF, 0, 0,
402
403		/* 0x140 */
404		REG_RWF, REG_RWF, REG_RWF, REG_R,
405		REG_R, REG_R, REG_R, REG_R,
406		REG_WF, REG_WF, REG_WF, REG_WF,
407		REG_WF, REG_WF, REG_WF, REG_WF,
408
409		/* 0x180 */
410		REG_WF, REG_WF, REG_WF, REG_WF,
411		REG_WF, REG_WF, REG_WF, REG_WF,
412		REG_WF, REG_WF, REG_WF, REG_WF,
413		REG_WF, REG_WF, REG_WF, REG_WF,
414
415		/* 0x1c0 */
416		REG_WF, REG_WF, REG_WF, REG_WF,
417		REG_WF, REG_WF, REG_WF, REG_WF,
418		0, 0, 0, 0,
419		0, 0, 0, 0,
420
421		/* 0x200 */
422		REG_RW, REG_R, REG_RW, REG_RW,
423		REG_RW, REG_RW, REG_RW, REG_RW,
424		REG_W, REG_W, REG_W, REG_W,
425		REG_W, 0, 0, 0,
426
427		/* 0x240 */
428		0, 0, 0, 0,
429		0, 0, 0, 0,
430		0, 0, 0, 0,
431		0, 0, 0, 0,
432
433		/* 0x280 */
434		0, 0, 0, 0,
435		0, 0, 0, 0,
436		0, 0, 0, 0,
437		0, 0, 0, 0,
438
439		/* 0x2c0 */
440		0, 0, 0, 0,
441		0, 0, 0, 0,
442		0, 0, 0, 0,
443		0, 0, 0, 0,
444
445		/* 0x300 */
446		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
447		REG_WPF, REG_WPF, REG_WPF, REG_WF,
448		REG_WF, REG_WF, REG_WF, REG_WF,
449		REG_WF, REG_WF, REG_WF, REG_WF,
450
451		/* 0x340 */
452		REG_WF, REG_WF, REG_WF, REG_WF,
453		REG_WF, REG_WF, REG_WF, REG_WF,
454		REG_WF, REG_WF, REG_WF, REG_WF,
455		REG_WF, REG_WF, REG_WF, REG_WF,
456
457		/* 0x380 */
458		REG_WF
459		};
460
461
462		static const UINT8 voodoo2_register_access[0x100] =
463		{
464		/* 0x000 */
465		REG_RP, REG_RWPT, REG_WPF, REG_WPF,
466		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
467		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
468		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
469
470		/* 0x040 */
471		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
472		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
473		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
474		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
475
476		/* 0x080 */
477		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
478		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
479		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
480		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
481
482		/* 0x0c0 */
483		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
484		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
485		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
486		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
487
488		/* 0x100 */
489		REG_WPF, REG_RWPF, REG_RWPF, REG_RWPF,
490		REG_RWF, REG_RWF, REG_RWF, REG_RWF,
491		REG_WF, REG_WF, REG_WF, REG_WF,
492		REG_WF, REG_WF, REG_WF, REG_WF,
493
494		/* 0x140 */
495		REG_RWF, REG_RWF, REG_RWF, REG_R,
496		REG_R, REG_R, REG_R, REG_R,
497		REG_WF, REG_WF, REG_WF, REG_WF,
498		REG_WF, REG_WF, REG_WF, REG_WF,
499
500		/* 0x180 */
501		REG_WF, REG_WF, REG_WF, REG_WF,
502		REG_WF, REG_WF, REG_WF, REG_WF,
503		REG_WF, REG_WF, REG_WF, REG_WF,
504		REG_WF, REG_WF, REG_WF, REG_WF,
505
506		/* 0x1c0 */
507		REG_WF, REG_WF, REG_WF, REG_WF,
508		REG_WF, REG_WF, REG_WF, REG_WF,
509		REG_RWT, REG_RWT, REG_RWT, REG_RWT,
510		REG_RWT, REG_RWT, REG_RWT, REG_RW,
511
512		/* 0x200 */
513		REG_RWT, REG_R, REG_RWT, REG_RWT,
514		REG_RWT, REG_RWT, REG_RWT, REG_RWT,
515		REG_WT, REG_WT, REG_WF, REG_WT,
516		REG_WT, REG_WT, REG_WT, REG_WT,
517
518		/* 0x240 */
519		REG_R, REG_RWT, REG_RWT, REG_RWT,
520		0, 0, REG_R, REG_R,
521		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
522		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
523
524		/* 0x280 */
525		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
526		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
527		REG_WPF, REG_WPF, 0, 0,
528		0, 0, 0, 0,
529
530		/* 0x2c0 */
531		REG_RWPF, REG_RWPF, REG_RWPF, REG_RWPF,
532		REG_RWPF, REG_RWPF, REG_RWPF, REG_RWPF,
533		REG_RWPF, REG_RWPF, REG_RWPF, REG_RWPF,
534		REG_RWPF, REG_RWPF, REG_RWPF, REG_WPF,
535
536		/* 0x300 */
537		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
538		REG_WPF, REG_WPF, REG_WPF, REG_WF,
539		REG_WF, REG_WF, REG_WF, REG_WF,
540		REG_WF, REG_WF, REG_WF, REG_WF,
541
542		/* 0x340 */
543		REG_WF, REG_WF, REG_WF, REG_WF,
544		REG_WF, REG_WF, REG_WF, REG_WF,
545		REG_WF, REG_WF, REG_WF, REG_WF,
546		REG_WF, REG_WF, REG_WF, REG_WF,
547
548		/* 0x380 */
549		REG_WF
550		};
551
552
553		static const UINT8 banshee_register_access[0x100] =
554		{
555		/* 0x000 */
556		REG_RP, REG_RWPT, REG_WPF, REG_WPF,
557		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
558		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
559		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
560
561		/* 0x040 */
562		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
563		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
564		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
565		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
566
567		/* 0x080 */
568		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
569		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
570		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
571		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
572
573		/* 0x0c0 */
574		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
575		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
576		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
577		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
578
579		/* 0x100 */
580		REG_WPF, REG_RWPF, REG_RWPF, REG_RWPF,
581		REG_RWF, REG_RWF, REG_RWF, REG_RWF,
582		REG_WF, REG_WF, REG_WF, REG_WF,
583		REG_WF, REG_WF, REG_WF, REG_WF,
584
585		/* 0x140 */
586		REG_RWF, REG_RWF, REG_RWF, REG_R,
587		REG_R, REG_R, REG_R, REG_R,
588		REG_WF, REG_WF, REG_WF, REG_WF,
589		REG_WF, REG_WF, REG_WF, REG_WF,
590
591		/* 0x180 */
592		REG_WF, REG_WF, REG_WF, REG_WF,
593		REG_WF, REG_WF, REG_WF, REG_WF,
594		REG_WF, REG_WF, REG_WF, REG_WF,
595		REG_WF, REG_WF, REG_WF, REG_WF,
596
597		/* 0x1c0 */
598		REG_WF, REG_WF, REG_WF, REG_WF,
599		REG_WF, REG_WF, REG_WF, REG_WF,
600		0, 0, 0, REG_RWF,
601		REG_RWF, REG_RWF, REG_RWF, 0,
602
603		/* 0x200 */
604		REG_RWF, REG_RWF, 0, 0,
605		0, 0, 0, 0,
606		0, 0, 0, 0,
607		0, 0, 0, 0,
608
609		/* 0x240 */
610		0, 0, 0, REG_WT,
611		REG_RWF, REG_RWF, REG_WPF, REG_WPF,
612		REG_WPF, REG_WPF, REG_R, REG_R,
613		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
614
615		/* 0x280 */
616		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
617		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
618		REG_WPF, REG_WPF, 0, 0,
619		0, 0, 0, 0,
620
621		/* 0x2c0 */
622		0, 0, 0, 0,
623		0, 0, 0, 0,
624		0, 0, 0, 0,
625		0, 0, 0, 0,
626
627		/* 0x300 */
628		REG_WPF, REG_WPF, REG_WPF, REG_WPF,
629		REG_WPF, REG_WPF, REG_WPF, 0,
630		REG_WF, REG_WF, REG_WF, REG_WF,
631		REG_WF, REG_WF, REG_WF, REG_WF,
632
633		/* 0x340 */
634		REG_WF, REG_WF, REG_WF, REG_WF,
635		REG_WF, REG_WF, REG_WF, REG_WF,
636		REG_WF, REG_WF, REG_WF, REG_WF,
637		REG_WF, REG_WF, REG_WF, REG_WF,
638
639		/* 0x380 */
640		REG_WF
641		};
642
643
644
645		/*************************************
646		*
647		* Register string table for debug
648		*
649		*************************************/
650
651		static const char *const voodoo_reg_name[] =
652		{
653		/* 0x000 */
654		"status", "{intrCtrl}", "vertexAx", "vertexAy",
655		"vertexBx", "vertexBy", "vertexCx", "vertexCy",
656		"startR", "startG", "startB", "startZ",
657		"startA", "startS", "startT", "startW",
658		/* 0x040 */
659		"dRdX", "dGdX", "dBdX", "dZdX",
660		"dAdX", "dSdX", "dTdX", "dWdX",
661		"dRdY", "dGdY", "dBdY", "dZdY",
662		"dAdY", "dSdY", "dTdY", "dWdY",
663		/* 0x080 */
664		"triangleCMD", "reserved084", "fvertexAx", "fvertexAy",
665		"fvertexBx", "fvertexBy", "fvertexCx", "fvertexCy",
666		"fstartR", "fstartG", "fstartB", "fstartZ",
667		"fstartA", "fstartS", "fstartT", "fstartW",
668		/* 0x0c0 */
669		"fdRdX", "fdGdX", "fdBdX", "fdZdX",
670		"fdAdX", "fdSdX", "fdTdX", "fdWdX",
671		"fdRdY", "fdGdY", "fdBdY", "fdZdY",
672		"fdAdY", "fdSdY", "fdTdY", "fdWdY",
673		/* 0x100 */
674		"ftriangleCMD", "fbzColorPath", "fogMode", "alphaMode",
675		"fbzMode", "lfbMode", "clipLeftRight","clipLowYHighY",
676		"nopCMD", "fastfillCMD", "swapbufferCMD","fogColor",
677		"zaColor", "chromaKey", "{chromaRange}","{userIntrCMD}",
678		/* 0x140 */
679		"stipple", "color0", "color1", "fbiPixelsIn",
680		"fbiChromaFail","fbiZfuncFail", "fbiAfuncFail", "fbiPixelsOut",
681		"fogTable160", "fogTable164", "fogTable168", "fogTable16c",
682		"fogTable170", "fogTable174", "fogTable178", "fogTable17c",
683		/* 0x180 */
684		"fogTable180", "fogTable184", "fogTable188", "fogTable18c",
685		"fogTable190", "fogTable194", "fogTable198", "fogTable19c",
686		"fogTable1a0", "fogTable1a4", "fogTable1a8", "fogTable1ac",
687		"fogTable1b0", "fogTable1b4", "fogTable1b8", "fogTable1bc",
688		/* 0x1c0 */
689		"fogTable1c0", "fogTable1c4", "fogTable1c8", "fogTable1cc",
690		"fogTable1d0", "fogTable1d4", "fogTable1d8", "fogTable1dc",
691		"{cmdFifoBaseAddr}","{cmdFifoBump}","{cmdFifoRdPtr}","{cmdFifoAMin}",
692		"{cmdFifoAMax}","{cmdFifoDepth}","{cmdFifoHoles}","reserved1fc",
693		/* 0x200 */
694		"fbiInit4", "vRetrace", "backPorch", "videoDimensions",
695		"fbiInit0", "fbiInit1", "fbiInit2", "fbiInit3",
696		"hSync", "vSync", "clutData", "dacData",
697		"maxRgbDelta", "{hBorder}", "{vBorder}", "{borderColor}",
698		/* 0x240 */
699		"{hvRetrace}", "{fbiInit5}", "{fbiInit6}", "{fbiInit7}",
700		"reserved250", "reserved254", "{fbiSwapHistory}","{fbiTrianglesOut}",
701		"{sSetupMode}", "{sVx}", "{sVy}", "{sARGB}",
702		"{sRed}", "{sGreen}", "{sBlue}", "{sAlpha}",
703		/* 0x280 */
704		"{sVz}", "{sWb}", "{sWtmu0}", "{sS/Wtmu0}",
705		"{sT/Wtmu0}", "{sWtmu1}", "{sS/Wtmu1}", "{sT/Wtmu1}",
706		"{sDrawTriCMD}","{sBeginTriCMD}","reserved2a8", "reserved2ac",
707		"reserved2b0", "reserved2b4", "reserved2b8", "reserved2bc",
708		/* 0x2c0 */
709		"{bltSrcBaseAddr}","{bltDstBaseAddr}","{bltXYStrides}","{bltSrcChromaRange}",
710		"{bltDstChromaRange}","{bltClipX}","{bltClipY}","reserved2dc",
711		"{bltSrcXY}", "{bltDstXY}", "{bltSize}", "{bltRop}",
712		"{bltColor}", "reserved2f4", "{bltCommand}", "{bltData}",
713		/* 0x300 */
714		"textureMode", "tLOD", "tDetail", "texBaseAddr",
715		"texBaseAddr_1","texBaseAddr_2","texBaseAddr_3_8","trexInit0",
716		"trexInit1", "nccTable0.0", "nccTable0.1", "nccTable0.2",
717		"nccTable0.3", "nccTable0.4", "nccTable0.5", "nccTable0.6",
718		/* 0x340 */
719		"nccTable0.7", "nccTable0.8", "nccTable0.9", "nccTable0.A",
720		"nccTable0.B", "nccTable1.0", "nccTable1.1", "nccTable1.2",
721		"nccTable1.3", "nccTable1.4", "nccTable1.5", "nccTable1.6",
722		"nccTable1.7", "nccTable1.8", "nccTable1.9", "nccTable1.A",
723		/* 0x380 */
724		"nccTable1.B"
725		};
726
727
728		static const char *const banshee_reg_name[] =
729		{
730		/* 0x000 */
731		"status", "intrCtrl", "vertexAx", "vertexAy",
732		"vertexBx", "vertexBy", "vertexCx", "vertexCy",
733		"startR", "startG", "startB", "startZ",
734		"startA", "startS", "startT", "startW",
735		/* 0x040 */
736		"dRdX", "dGdX", "dBdX", "dZdX",
737		"dAdX", "dSdX", "dTdX", "dWdX",
738		"dRdY", "dGdY", "dBdY", "dZdY",
739		"dAdY", "dSdY", "dTdY", "dWdY",
740		/* 0x080 */
741		"triangleCMD", "reserved084", "fvertexAx", "fvertexAy",
742		"fvertexBx", "fvertexBy", "fvertexCx", "fvertexCy",
743		"fstartR", "fstartG", "fstartB", "fstartZ",
744		"fstartA", "fstartS", "fstartT", "fstartW",
745		/* 0x0c0 */
746		"fdRdX", "fdGdX", "fdBdX", "fdZdX",
747		"fdAdX", "fdSdX", "fdTdX", "fdWdX",
748		"fdRdY", "fdGdY", "fdBdY", "fdZdY",
749		"fdAdY", "fdSdY", "fdTdY", "fdWdY",
750		/* 0x100 */
751		"ftriangleCMD", "fbzColorPath", "fogMode", "alphaMode",
752		"fbzMode", "lfbMode", "clipLeftRight","clipLowYHighY",
753		"nopCMD", "fastfillCMD", "swapbufferCMD","fogColor",
754		"zaColor", "chromaKey", "chromaRange", "userIntrCMD",
755		/* 0x140 */
756		"stipple", "color0", "color1", "fbiPixelsIn",
757		"fbiChromaFail","fbiZfuncFail", "fbiAfuncFail", "fbiPixelsOut",
758		"fogTable160", "fogTable164", "fogTable168", "fogTable16c",
759		"fogTable170", "fogTable174", "fogTable178", "fogTable17c",
760		/* 0x180 */
761		"fogTable180", "fogTable184", "fogTable188", "fogTable18c",
762		"fogTable190", "fogTable194", "fogTable198", "fogTable19c",
763		"fogTable1a0", "fogTable1a4", "fogTable1a8", "fogTable1ac",
764		"fogTable1b0", "fogTable1b4", "fogTable1b8", "fogTable1bc",
765		/* 0x1c0 */
766		"fogTable1c0", "fogTable1c4", "fogTable1c8", "fogTable1cc",
767		"fogTable1d0", "fogTable1d4", "fogTable1d8", "fogTable1dc",
768		"reserved1e0", "reserved1e4", "reserved1e8", "colBufferAddr",
769		"colBufferStride","auxBufferAddr","auxBufferStride","reserved1fc",
770		/* 0x200 */
771		"clipLeftRight1","clipTopBottom1","reserved208","reserved20c",
772		"reserved210", "reserved214", "reserved218", "reserved21c",
773		"reserved220", "reserved224", "reserved228", "reserved22c",
774		"reserved230", "reserved234", "reserved238", "reserved23c",
775		/* 0x240 */
776		"reserved240", "reserved244", "reserved248", "swapPending",
777		"leftOverlayBuf","rightOverlayBuf","fbiSwapHistory","fbiTrianglesOut",
778		"sSetupMode", "sVx", "sVy", "sARGB",
779		"sRed", "sGreen", "sBlue", "sAlpha",
780		/* 0x280 */
781		"sVz", "sWb", "sWtmu0", "sS/Wtmu0",
782		"sT/Wtmu0", "sWtmu1", "sS/Wtmu1", "sT/Wtmu1",
783		"sDrawTriCMD", "sBeginTriCMD", "reserved2a8", "reserved2ac",
784		"reserved2b0", "reserved2b4", "reserved2b8", "reserved2bc",
785		/* 0x2c0 */
786		"reserved2c0", "reserved2c4", "reserved2c8", "reserved2cc",
787		"reserved2d0", "reserved2d4", "reserved2d8", "reserved2dc",
788		"reserved2e0", "reserved2e4", "reserved2e8", "reserved2ec",
789		"reserved2f0", "reserved2f4", "reserved2f8", "reserved2fc",
790		/* 0x300 */
791		"textureMode", "tLOD", "tDetail", "texBaseAddr",
792		"texBaseAddr_1","texBaseAddr_2","texBaseAddr_3_8","reserved31c",
793		"trexInit1", "nccTable0.0", "nccTable0.1", "nccTable0.2",
794		"nccTable0.3", "nccTable0.4", "nccTable0.5", "nccTable0.6",
795		/* 0x340 */
796		"nccTable0.7", "nccTable0.8", "nccTable0.9", "nccTable0.A",
797		"nccTable0.B", "nccTable1.0", "nccTable1.1", "nccTable1.2",
798		"nccTable1.3", "nccTable1.4", "nccTable1.5", "nccTable1.6",
799		"nccTable1.7", "nccTable1.8", "nccTable1.9", "nccTable1.A",
800		/* 0x380 */
801		"nccTable1.B"
802		};
803
804
805
806		/*************************************
807		*
808		* Voodoo Banshee I/O space registers
809		*
810		*************************************/
811
812		/* 0x000 */
813		#define io_status (0x000/4) /* */
814		#define io_pciInit0 (0x004/4) /* */
815		#define io_sipMonitor (0x008/4) /* */
816		#define io_lfbMemoryConfig (0x00c/4) /* */
817		#define io_miscInit0 (0x010/4) /* */
818		#define io_miscInit1 (0x014/4) /* */
819		#define io_dramInit0 (0x018/4) /* */
820		#define io_dramInit1 (0x01c/4) /* */
821		#define io_agpInit (0x020/4) /* */
822		#define io_tmuGbeInit (0x024/4) /* */
823		#define io_vgaInit0 (0x028/4) /* */
824		#define io_vgaInit1 (0x02c/4) /* */
825		#define io_dramCommand (0x030/4) /* */
826		#define io_dramData (0x034/4) /* */
827
828		/* 0x040 */
829		#define io_pllCtrl0 (0x040/4) /* */
830		#define io_pllCtrl1 (0x044/4) /* */
831		#define io_pllCtrl2 (0x048/4) /* */
832		#define io_dacMode (0x04c/4) /* */
833		#define io_dacAddr (0x050/4) /* */
834		#define io_dacData (0x054/4) /* */
835		#define io_rgbMaxDelta (0x058/4) /* */
836		#define io_vidProcCfg (0x05c/4) /* */
837		#define io_hwCurPatAddr (0x060/4) /* */
838		#define io_hwCurLoc (0x064/4) /* */
839		#define io_hwCurC0 (0x068/4) /* */
840		#define io_hwCurC1 (0x06c/4) /* */
841		#define io_vidInFormat (0x070/4) /* */
842		#define io_vidInStatus (0x074/4) /* */
843		#define io_vidSerialParallelPort (0x078/4) /* */
844		#define io_vidInXDecimDeltas (0x07c/4) /* */
845
846		/* 0x080 */
847		#define io_vidInDecimInitErrs (0x080/4) /* */
848		#define io_vidInYDecimDeltas (0x084/4) /* */
849		#define io_vidPixelBufThold (0x088/4) /* */
850		#define io_vidChromaMin (0x08c/4) /* */
851		#define io_vidChromaMax (0x090/4) /* */
852		#define io_vidCurrentLine (0x094/4) /* */
853		#define io_vidScreenSize (0x098/4) /* */
854		#define io_vidOverlayStartCoords (0x09c/4) /* */
855		#define io_vidOverlayEndScreenCoord (0x0a0/4) /* */
856		#define io_vidOverlayDudx (0x0a4/4) /* */
857		#define io_vidOverlayDudxOffsetSrcWidth (0x0a8/4) /* */
858		#define io_vidOverlayDvdy (0x0ac/4) /* */
859		#define io_vgab0 (0x0b0/4) /* */
860		#define io_vgab4 (0x0b4/4) /* */
861		#define io_vgab8 (0x0b8/4) /* */
862		#define io_vgabc (0x0bc/4) /* */
863
864		/* 0x0c0 */
865		#define io_vgac0 (0x0c0/4) /* */
866		#define io_vgac4 (0x0c4/4) /* */
867		#define io_vgac8 (0x0c8/4) /* */
868		#define io_vgacc (0x0cc/4) /* */
869		#define io_vgad0 (0x0d0/4) /* */
870		#define io_vgad4 (0x0d4/4) /* */
871		#define io_vgad8 (0x0d8/4) /* */
872		#define io_vgadc (0x0dc/4) /* */
873		#define io_vidOverlayDvdyOffset (0x0e0/4) /* */
874		#define io_vidDesktopStartAddr (0x0e4/4) /* */
875		#define io_vidDesktopOverlayStride (0x0e8/4) /* */
876		#define io_vidInAddr0 (0x0ec/4) /* */
877		#define io_vidInAddr1 (0x0f0/4) /* */
878		#define io_vidInAddr2 (0x0f4/4) /* */
879		#define io_vidInStride (0x0f8/4) /* */
880		#define io_vidCurrOverlayStartAddr (0x0fc/4) /* */
881
882
883
884		/*************************************
885		*
886		* Register string table for debug
887		*
888		*************************************/
889
890		static const char *const banshee_io_reg_name[] =
891		{
892		/* 0x000 */
893		"status", "pciInit0", "sipMonitor", "lfbMemoryConfig",
894		"miscInit0", "miscInit1", "dramInit0", "dramInit1",
895		"agpInit", "tmuGbeInit", "vgaInit0", "vgaInit1",
896		"dramCommand", "dramData", "reserved38", "reserved3c",
897
898		/* 0x040 */
899		"pllCtrl0", "pllCtrl1", "pllCtrl2", "dacMode",
900		"dacAddr", "dacData", "rgbMaxDelta", "vidProcCfg",
901		"hwCurPatAddr", "hwCurLoc", "hwCurC0", "hwCurC1",
902		"vidInFormat", "vidInStatus", "vidSerialParallelPort","vidInXDecimDeltas",
903
904		/* 0x080 */
905		"vidInDecimInitErrs","vidInYDecimDeltas","vidPixelBufThold","vidChromaMin",
906		"vidChromaMax", "vidCurrentLine","vidScreenSize","vidOverlayStartCoords",
907		"vidOverlayEndScreenCoord","vidOverlayDudx","vidOverlayDudxOffsetSrcWidth","vidOverlayDvdy",
908		"vga[b0]", "vga[b4]", "vga[b8]", "vga[bc]",
909
910		/* 0x0c0 */
911		"vga[c0]", "vga[c4]", "vga[c8]", "vga[cc]",
912		"vga[d0]", "vga[d4]", "vga[d8]", "vga[dc]",
913		"vidOverlayDvdyOffset","vidDesktopStartAddr","vidDesktopOverlayStride","vidInAddr0",
914		"vidInAddr1", "vidInAddr2", "vidInStride", "vidCurrOverlayStartAddr"
915		};
916
917
918
919		/*************************************
920		*
921		* Voodoo Banshee AGP space registers
922		*
923		*************************************/
924
925		/* 0x000 */
926		#define agpReqSize (0x000/4) /* */
927		#define agpHostAddressLow (0x004/4) /* */
928		#define agpHostAddressHigh (0x008/4) /* */
929		#define agpGraphicsAddress (0x00c/4) /* */
930		#define agpGraphicsStride (0x010/4) /* */
931		#define agpMoveCMD (0x014/4) /* */
932		#define cmdBaseAddr0 (0x020/4) /* */
933		#define cmdBaseSize0 (0x024/4) /* */
934		#define cmdBump0 (0x028/4) /* */
935		#define cmdRdPtrL0 (0x02c/4) /* */
936		#define cmdRdPtrH0 (0x030/4) /* */
937		#define cmdAMin0 (0x034/4) /* */
938		#define cmdAMax0 (0x03c/4) /* */
939
940		/* 0x040 */
941		#define cmdFifoDepth0 (0x044/4) /* */
942		#define cmdHoleCnt0 (0x048/4) /* */
943		#define cmdBaseAddr1 (0x050/4) /* */
944		#define cmdBaseSize1 (0x054/4) /* */
945		#define cmdBump1 (0x058/4) /* */
946		#define cmdRdPtrL1 (0x05c/4) /* */
947		#define cmdRdPtrH1 (0x060/4) /* */
948		#define cmdAMin1 (0x064/4) /* */
949		#define cmdAMax1 (0x06c/4) /* */
950		#define cmdFifoDepth1 (0x074/4) /* */
951		#define cmdHoleCnt1 (0x078/4) /* */
952
953		/* 0x080 */
954		#define cmdFifoThresh (0x080/4) /* */
955		#define cmdHoleInt (0x084/4) /* */
956
957		/* 0x100 */
958		#define yuvBaseAddress (0x100/4) /* */
959		#define yuvStride (0x104/4) /* */
960		#define crc1 (0x120/4) /* */
961		#define crc2 (0x130/4) /* */
962
963
964
965		/*************************************
966		*
967		* Register string table for debug
968		*
969		*************************************/
970
971		static const char *const banshee_agp_reg_name[] =
972		{
973		/* 0x000 */
974		"agpReqSize", "agpHostAddressLow","agpHostAddressHigh","agpGraphicsAddress",
975		"agpGraphicsStride","agpMoveCMD","reserved18", "reserved1c",
976		"cmdBaseAddr0", "cmdBaseSize0", "cmdBump0", "cmdRdPtrL0",
977		"cmdRdPtrH0", "cmdAMin0", "reserved38", "cmdAMax0",
978
979		/* 0x040 */
980		"reserved40", "cmdFifoDepth0","cmdHoleCnt0", "reserved4c",
981		"cmdBaseAddr1", "cmdBaseSize1", "cmdBump1", "cmdRdPtrL1",
982		"cmdRdPtrH1", "cmdAMin1", "reserved68", "cmdAMax1",
983		"reserved70", "cmdFifoDepth1","cmdHoleCnt1", "reserved7c",
984
985		/* 0x080 */
986		"cmdFifoThresh","cmdHoleInt", "reserved88", "reserved8c",
987		"reserved90", "reserved94", "reserved98", "reserved9c",
988		"reserveda0", "reserveda4", "reserveda8", "reservedac",
989		"reservedb0", "reservedb4", "reservedb8", "reservedbc",
990
991		/* 0x0c0 */
992		"reservedc0", "reservedc4", "reservedc8", "reservedcc",
993		"reservedd0", "reservedd4", "reservedd8", "reserveddc",
994		"reservede0", "reservede4", "reservede8", "reservedec",
995		"reservedf0", "reservedf4", "reservedf8", "reservedfc",
996
997		/* 0x100 */
998		"yuvBaseAddress","yuvStride", "reserved108", "reserved10c",
999		"reserved110", "reserved114", "reserved118", "reserved11c",
1000		"crc1", "reserved124", "reserved128", "reserved12c",
1001		"crc2", "reserved134", "reserved138", "reserved13c"
1002		};
1003
1004
1005
1006		/*************************************
1007		*
1008		* Dithering tables
1009		*
1010		*************************************/
1011
1012		static const UINT8 dither_matrix_4x4[16] =
1013		{
1014		0, 8, 2, 10,
1015		12, 4, 14, 6,
1016		3, 11, 1, 9,
1017		15, 7, 13, 5
1018		};
1019
1020		static const UINT8 dither_matrix_2x2[16] =
1021		{
1022		2, 10, 2, 10,
1023		14, 6, 14, 6,
1024		2, 10, 2, 10,
1025		14, 6, 14, 6
1026		};
1027
1028
1029
1030		/*************************************
1031		*
1032		* Macros for extracting pixels
1033		*
1034		*************************************/
1035
1036		#define EXTRACT_565_TO_888(val, a, b, c) \
1037		(a) = (((val) >> 8) & 0xf8) \| (((val) >> 13) & 0x07); \
1038		(b) = (((val) >> 3) & 0xfc) \| (((val) >> 9) & 0x03); \
1039		(c) = (((val) << 3) & 0xf8) \| (((val) >> 2) & 0x07);
1040		#define EXTRACT_x555_TO_888(val, a, b, c) \
1041		(a) = (((val) >> 7) & 0xf8) \| (((val) >> 12) & 0x07); \
1042		(b) = (((val) >> 2) & 0xf8) \| (((val) >> 7) & 0x07); \
1043		(c) = (((val) << 3) & 0xf8) \| (((val) >> 2) & 0x07);
1044		#define EXTRACT_555x_TO_888(val, a, b, c) \
1045		(a) = (((val) >> 8) & 0xf8) \| (((val) >> 13) & 0x07); \
1046		(b) = (((val) >> 3) & 0xf8) \| (((val) >> 8) & 0x07); \
1047		(c) = (((val) << 2) & 0xf8) \| (((val) >> 3) & 0x07);
1048		#define EXTRACT_1555_TO_8888(val, a, b, c, d) \
1049		(a) = ((INT16)(val) >> 15) & 0xff; \
1050		EXTRACT_x555_TO_888(val, b, c, d)
1051		#define EXTRACT_5551_TO_8888(val, a, b, c, d) \
1052		EXTRACT_555x_TO_888(val, a, b, c) \
1053		(d) = ((val) & 0x0001) ? 0xff : 0x00;
1054		#define EXTRACT_x888_TO_888(val, a, b, c) \
1055		(a) = ((val) >> 16) & 0xff; \
1056		(b) = ((val) >> 8) & 0xff; \
1057		(c) = ((val) >> 0) & 0xff;
1058		#define EXTRACT_888x_TO_888(val, a, b, c) \
1059		(a) = ((val) >> 24) & 0xff; \
1060		(b) = ((val) >> 16) & 0xff; \
1061		(c) = ((val) >> 8) & 0xff;
1062		#define EXTRACT_8888_TO_8888(val, a, b, c, d) \
1063		(a) = ((val) >> 24) & 0xff; \
1064		(b) = ((val) >> 16) & 0xff; \
1065		(c) = ((val) >> 8) & 0xff; \
1066		(d) = ((val) >> 0) & 0xff;
1067		#define EXTRACT_4444_TO_8888(val, a, b, c, d) \
1068		(a) = (((val) >> 8) & 0xf0) \| (((val) >> 12) & 0x0f); \
1069		(b) = (((val) >> 4) & 0xf0) \| (((val) >> 8) & 0x0f); \
1070		(c) = (((val) >> 0) & 0xf0) \| (((val) >> 4) & 0x0f); \
1071		(d) = (((val) << 4) & 0xf0) \| (((val) >> 0) & 0x0f);
1072		#define EXTRACT_332_TO_888(val, a, b, c) \
1073		(a) = (((val) >> 0) & 0xe0) \| (((val) >> 3) & 0x1c) \| (((val) >> 6) & 0x03); \
1074		(b) = (((val) << 3) & 0xe0) \| (((val) >> 0) & 0x1c) \| (((val) >> 3) & 0x03); \
1075		(c) = (((val) << 6) & 0xc0) \| (((val) << 4) & 0x30) \| (((val) << 2) & 0x0c) \| (((val) << 0) & 0x03);
1076
1077
1078		/*************************************
1079		*
1080		* Misc. macros
1081		*
1082		*************************************/
1083
1084		/* macro for clamping a value between minimum and maximum values */
1085		#define CLAMP(val,min,max) do { if ((val) < (min)) { (val) = (min); } else if ((val) > (max)) { (val) = (max); } } while (0)
1086
1087		/* macro to compute the base 2 log for LOD calculations */
1088		#define LOGB2(x) (log((double)(x)) / log(2.0))
1089
1090
1091
1092		/*************************************
1093		*
1094		* Macros for extracting bitfields
1095		*
1096		*************************************/
1097
1098		#define INITEN_ENABLE_HW_INIT(val) (((val) >> 0) & 1)
1099		#define INITEN_ENABLE_PCI_FIFO(val) (((val) >> 1) & 1)
1100		#define INITEN_REMAP_INIT_TO_DAC(val) (((val) >> 2) & 1)
1101		#define INITEN_ENABLE_SNOOP0(val) (((val) >> 4) & 1)
1102		#define INITEN_SNOOP0_MEMORY_MATCH(val) (((val) >> 5) & 1)
1103		#define INITEN_SNOOP0_READWRITE_MATCH(val) (((val) >> 6) & 1)
1104		#define INITEN_ENABLE_SNOOP1(val) (((val) >> 7) & 1)
1105		#define INITEN_SNOOP1_MEMORY_MATCH(val) (((val) >> 8) & 1)
1106		#define INITEN_SNOOP1_READWRITE_MATCH(val) (((val) >> 9) & 1)
1107		#define INITEN_SLI_BUS_OWNER(val) (((val) >> 10) & 1)
1108		#define INITEN_SLI_ODD_EVEN(val) (((val) >> 11) & 1)
1109		#define INITEN_SECONDARY_REV_ID(val) (((val) >> 12) & 0xf) /* voodoo 2 only */
1110		#define INITEN_MFCTR_FAB_ID(val) (((val) >> 16) & 0xf) /* voodoo 2 only */
1111		#define INITEN_ENABLE_PCI_INTERRUPT(val) (((val) >> 20) & 1) /* voodoo 2 only */
1112		#define INITEN_PCI_INTERRUPT_TIMEOUT(val) (((val) >> 21) & 1) /* voodoo 2 only */
1113		#define INITEN_ENABLE_NAND_TREE_TEST(val) (((val) >> 22) & 1) /* voodoo 2 only */
1114		#define INITEN_ENABLE_SLI_ADDRESS_SNOOP(val) (((val) >> 23) & 1) /* voodoo 2 only */
1115		#define INITEN_SLI_SNOOP_ADDRESS(val) (((val) >> 24) & 0xff) /* voodoo 2 only */
1116
1117		#define FBZCP_CC_RGBSELECT(val) (((val) >> 0) & 3)
1118		#define FBZCP_CC_ASELECT(val) (((val) >> 2) & 3)
1119		#define FBZCP_CC_LOCALSELECT(val) (((val) >> 4) & 1)
1120		#define FBZCP_CCA_LOCALSELECT(val) (((val) >> 5) & 3)
1121		#define FBZCP_CC_LOCALSELECT_OVERRIDE(val) (((val) >> 7) & 1)
1122		#define FBZCP_CC_ZERO_OTHER(val) (((val) >> 8) & 1)
1123		#define FBZCP_CC_SUB_CLOCAL(val) (((val) >> 9) & 1)
1124		#define FBZCP_CC_MSELECT(val) (((val) >> 10) & 7)
1125		#define FBZCP_CC_REVERSE_BLEND(val) (((val) >> 13) & 1)
1126		#define FBZCP_CC_ADD_ACLOCAL(val) (((val) >> 14) & 3)
1127		#define FBZCP_CC_INVERT_OUTPUT(val) (((val) >> 16) & 1)
1128		#define FBZCP_CCA_ZERO_OTHER(val) (((val) >> 17) & 1)
1129		#define FBZCP_CCA_SUB_CLOCAL(val) (((val) >> 18) & 1)
1130		#define FBZCP_CCA_MSELECT(val) (((val) >> 19) & 7)
1131		#define FBZCP_CCA_REVERSE_BLEND(val) (((val) >> 22) & 1)
1132		#define FBZCP_CCA_ADD_ACLOCAL(val) (((val) >> 23) & 3)
1133		#define FBZCP_CCA_INVERT_OUTPUT(val) (((val) >> 25) & 1)
1134		#define FBZCP_CCA_SUBPIXEL_ADJUST(val) (((val) >> 26) & 1)
1135		#define FBZCP_TEXTURE_ENABLE(val) (((val) >> 27) & 1)
1136		#define FBZCP_RGBZW_CLAMP(val) (((val) >> 28) & 1) /* voodoo 2 only */
1137		#define FBZCP_ANTI_ALIAS(val) (((val) >> 29) & 1) /* voodoo 2 only */
1138
1139		#define ALPHAMODE_ALPHATEST(val) (((val) >> 0) & 1)
1140		#define ALPHAMODE_ALPHAFUNCTION(val) (((val) >> 1) & 7)
1141		#define ALPHAMODE_ALPHABLEND(val) (((val) >> 4) & 1)
1142		#define ALPHAMODE_ANTIALIAS(val) (((val) >> 5) & 1)
1143		#define ALPHAMODE_SRCRGBBLEND(val) (((val) >> 8) & 15)
1144		#define ALPHAMODE_DSTRGBBLEND(val) (((val) >> 12) & 15)
1145		#define ALPHAMODE_SRCALPHABLEND(val) (((val) >> 16) & 15)
1146		#define ALPHAMODE_DSTALPHABLEND(val) (((val) >> 20) & 15)
1147		#define ALPHAMODE_ALPHAREF(val) (((val) >> 24) & 0xff)
1148
1149		#define FOGMODE_ENABLE_FOG(val) (((val) >> 0) & 1)
1150		#define FOGMODE_FOG_ADD(val) (((val) >> 1) & 1)
1151		#define FOGMODE_FOG_MULT(val) (((val) >> 2) & 1)
1152		#define FOGMODE_FOG_ZALPHA(val) (((val) >> 3) & 3)
1153		#define FOGMODE_FOG_CONSTANT(val) (((val) >> 5) & 1)
1154		#define FOGMODE_FOG_DITHER(val) (((val) >> 6) & 1) /* voodoo 2 only */
1155		#define FOGMODE_FOG_ZONES(val) (((val) >> 7) & 1) /* voodoo 2 only */
1156
1157		#define FBZMODE_ENABLE_CLIPPING(val) (((val) >> 0) & 1)
1158		#define FBZMODE_ENABLE_CHROMAKEY(val) (((val) >> 1) & 1)
1159		#define FBZMODE_ENABLE_STIPPLE(val) (((val) >> 2) & 1)
1160		#define FBZMODE_WBUFFER_SELECT(val) (((val) >> 3) & 1)
1161		#define FBZMODE_ENABLE_DEPTHBUF(val) (((val) >> 4) & 1)
1162		#define FBZMODE_DEPTH_FUNCTION(val) (((val) >> 5) & 7)
1163		#define FBZMODE_ENABLE_DITHERING(val) (((val) >> 8) & 1)
1164		#define FBZMODE_RGB_BUFFER_MASK(val) (((val) >> 9) & 1)
1165		#define FBZMODE_AUX_BUFFER_MASK(val) (((val) >> 10) & 1)
1166		#define FBZMODE_DITHER_TYPE(val) (((val) >> 11) & 1)
1167		#define FBZMODE_STIPPLE_PATTERN(val) (((val) >> 12) & 1)
1168		#define FBZMODE_ENABLE_ALPHA_MASK(val) (((val) >> 13) & 1)
1169		#define FBZMODE_DRAW_BUFFER(val) (((val) >> 14) & 3)
1170		#define FBZMODE_ENABLE_DEPTH_BIAS(val) (((val) >> 16) & 1)
1171		#define FBZMODE_Y_ORIGIN(val) (((val) >> 17) & 1)
1172		#define FBZMODE_ENABLE_ALPHA_PLANES(val) (((val) >> 18) & 1)
1173		#define FBZMODE_ALPHA_DITHER_SUBTRACT(val) (((val) >> 19) & 1)
1174		#define FBZMODE_DEPTH_SOURCE_COMPARE(val) (((val) >> 20) & 1)
1175		#define FBZMODE_DEPTH_FLOAT_SELECT(val) (((val) >> 21) & 1) /* voodoo 2 only */
1176
1177		#define LFBMODE_WRITE_FORMAT(val) (((val) >> 0) & 0xf)
1178		#define LFBMODE_WRITE_BUFFER_SELECT(val) (((val) >> 4) & 3)
1179		#define LFBMODE_READ_BUFFER_SELECT(val) (((val) >> 6) & 3)
1180		#define LFBMODE_ENABLE_PIXEL_PIPELINE(val) (((val) >> 8) & 1)
1181		#define LFBMODE_RGBA_LANES(val) (((val) >> 9) & 3)
1182		#define LFBMODE_WORD_SWAP_WRITES(val) (((val) >> 11) & 1)
1183		#define LFBMODE_BYTE_SWIZZLE_WRITES(val) (((val) >> 12) & 1)
1184		#define LFBMODE_Y_ORIGIN(val) (((val) >> 13) & 1)
1185		#define LFBMODE_WRITE_W_SELECT(val) (((val) >> 14) & 1)
1186		#define LFBMODE_WORD_SWAP_READS(val) (((val) >> 15) & 1)
1187		#define LFBMODE_BYTE_SWIZZLE_READS(val) (((val) >> 16) & 1)
1188
1189		#define CHROMARANGE_BLUE_EXCLUSIVE(val) (((val) >> 24) & 1)
1190		#define CHROMARANGE_GREEN_EXCLUSIVE(val) (((val) >> 25) & 1)
1191		#define CHROMARANGE_RED_EXCLUSIVE(val) (((val) >> 26) & 1)
1192		#define CHROMARANGE_UNION_MODE(val) (((val) >> 27) & 1)
1193		#define CHROMARANGE_ENABLE(val) (((val) >> 28) & 1)
1194
1195		#define FBIINIT0_VGA_PASSTHRU(val) (((val) >> 0) & 1)
1196		#define FBIINIT0_GRAPHICS_RESET(val) (((val) >> 1) & 1)
1197		#define FBIINIT0_FIFO_RESET(val) (((val) >> 2) & 1)
1198		#define FBIINIT0_SWIZZLE_REG_WRITES(val) (((val) >> 3) & 1)
1199		#define FBIINIT0_STALL_PCIE_FOR_HWM(val) (((val) >> 4) & 1)
1200		#define FBIINIT0_PCI_FIFO_LWM(val) (((val) >> 6) & 0x1f)
1201		#define FBIINIT0_LFB_TO_MEMORY_FIFO(val) (((val) >> 11) & 1)
1202		#define FBIINIT0_TEXMEM_TO_MEMORY_FIFO(val) (((val) >> 12) & 1)
1203		#define FBIINIT0_ENABLE_MEMORY_FIFO(val) (((val) >> 13) & 1)
1204		#define FBIINIT0_MEMORY_FIFO_HWM(val) (((val) >> 14) & 0x7ff)
1205		#define FBIINIT0_MEMORY_FIFO_BURST(val) (((val) >> 25) & 0x3f)
1206
1207		#define FBIINIT1_PCI_DEV_FUNCTION(val) (((val) >> 0) & 1)
1208		#define FBIINIT1_PCI_WRITE_WAIT_STATES(val) (((val) >> 1) & 1)
1209		#define FBIINIT1_MULTI_SST1(val) (((val) >> 2) & 1) /* not on voodoo 2 */
1210		#define FBIINIT1_ENABLE_LFB(val) (((val) >> 3) & 1)
1211		#define FBIINIT1_X_VIDEO_TILES(val) (((val) >> 4) & 0xf)
1212		#define FBIINIT1_VIDEO_TIMING_RESET(val) (((val) >> 8) & 1)
1213		#define FBIINIT1_SOFTWARE_OVERRIDE(val) (((val) >> 9) & 1)
1214		#define FBIINIT1_SOFTWARE_HSYNC(val) (((val) >> 10) & 1)
1215		#define FBIINIT1_SOFTWARE_VSYNC(val) (((val) >> 11) & 1)
1216		#define FBIINIT1_SOFTWARE_BLANK(val) (((val) >> 12) & 1)
1217		#define FBIINIT1_DRIVE_VIDEO_TIMING(val) (((val) >> 13) & 1)
1218		#define FBIINIT1_DRIVE_VIDEO_BLANK(val) (((val) >> 14) & 1)
1219		#define FBIINIT1_DRIVE_VIDEO_SYNC(val) (((val) >> 15) & 1)
1220		#define FBIINIT1_DRIVE_VIDEO_DCLK(val) (((val) >> 16) & 1)
1221		#define FBIINIT1_VIDEO_TIMING_VCLK(val) (((val) >> 17) & 1)
1222		#define FBIINIT1_VIDEO_CLK_2X_DELAY(val) (((val) >> 18) & 3)
1223		#define FBIINIT1_VIDEO_TIMING_SOURCE(val) (((val) >> 20) & 3)
1224		#define FBIINIT1_ENABLE_24BPP_OUTPUT(val) (((val) >> 22) & 1)
1225		#define FBIINIT1_ENABLE_SLI(val) (((val) >> 23) & 1)
1226		#define FBIINIT1_X_VIDEO_TILES_BIT5(val) (((val) >> 24) & 1) /* voodoo 2 only */
1227		#define FBIINIT1_ENABLE_EDGE_FILTER(val) (((val) >> 25) & 1)
1228		#define FBIINIT1_INVERT_VID_CLK_2X(val) (((val) >> 26) & 1)
1229		#define FBIINIT1_VID_CLK_2X_SEL_DELAY(val) (((val) >> 27) & 3)
1230		#define FBIINIT1_VID_CLK_DELAY(val) (((val) >> 29) & 3)
1231		#define FBIINIT1_DISABLE_FAST_READAHEAD(val) (((val) >> 31) & 1)
1232
1233		#define FBIINIT2_DISABLE_DITHER_SUB(val) (((val) >> 0) & 1)
1234		#define FBIINIT2_DRAM_BANKING(val) (((val) >> 1) & 1)
1235		#define FBIINIT2_ENABLE_TRIPLE_BUF(val) (((val) >> 4) & 1)
1236		#define FBIINIT2_ENABLE_FAST_RAS_READ(val) (((val) >> 5) & 1)
1237		#define FBIINIT2_ENABLE_GEN_DRAM_OE(val) (((val) >> 6) & 1)
1238		#define FBIINIT2_ENABLE_FAST_READWRITE(val) (((val) >> 7) & 1)
1239		#define FBIINIT2_ENABLE_PASSTHRU_DITHER(val) (((val) >> 8) & 1)
1240		#define FBIINIT2_SWAP_BUFFER_ALGORITHM(val) (((val) >> 9) & 3)
1241		#define FBIINIT2_VIDEO_BUFFER_OFFSET(val) (((val) >> 11) & 0x1ff)
1242		#define FBIINIT2_ENABLE_DRAM_BANKING(val) (((val) >> 20) & 1)
1243		#define FBIINIT2_ENABLE_DRAM_READ_FIFO(val) (((val) >> 21) & 1)
1244		#define FBIINIT2_ENABLE_DRAM_REFRESH(val) (((val) >> 22) & 1)
1245		#define FBIINIT2_REFRESH_LOAD_VALUE(val) (((val) >> 23) & 0x1ff)
1246
1247		#define FBIINIT3_TRI_REGISTER_REMAP(val) (((val) >> 0) & 1)
1248		#define FBIINIT3_VIDEO_FIFO_THRESH(val) (((val) >> 1) & 0x1f)
1249		#define FBIINIT3_DISABLE_TMUS(val) (((val) >> 6) & 1)
1250		#define FBIINIT3_FBI_MEMORY_TYPE(val) (((val) >> 8) & 7)
1251		#define FBIINIT3_VGA_PASS_RESET_VAL(val) (((val) >> 11) & 1)
1252		#define FBIINIT3_HARDCODE_PCI_BASE(val) (((val) >> 12) & 1)
1253		#define FBIINIT3_FBI2TREX_DELAY(val) (((val) >> 13) & 0xf)
1254		#define FBIINIT3_TREX2FBI_DELAY(val) (((val) >> 17) & 0x1f)
1255		#define FBIINIT3_YORIGIN_SUBTRACT(val) (((val) >> 22) & 0x3ff)
1256
1257		#define FBIINIT4_PCI_READ_WAITS(val) (((val) >> 0) & 1)
1258		#define FBIINIT4_ENABLE_LFB_READAHEAD(val) (((val) >> 1) & 1)
1259		#define FBIINIT4_MEMORY_FIFO_LWM(val) (((val) >> 2) & 0x3f)
1260		#define FBIINIT4_MEMORY_FIFO_START_ROW(val) (((val) >> 8) & 0x3ff)
1261		#define FBIINIT4_MEMORY_FIFO_STOP_ROW(val) (((val) >> 18) & 0x3ff)
1262		#define FBIINIT4_VIDEO_CLOCKING_DELAY(val) (((val) >> 29) & 7) /* voodoo 2 only */
1263
1264		#define FBIINIT5_DISABLE_PCI_STOP(val) (((val) >> 0) & 1) /* voodoo 2 only */
1265		#define FBIINIT5_PCI_SLAVE_SPEED(val) (((val) >> 1) & 1) /* voodoo 2 only */
1266		#define FBIINIT5_DAC_DATA_OUTPUT_WIDTH(val) (((val) >> 2) & 1) /* voodoo 2 only */
1267		#define FBIINIT5_DAC_DATA_17_OUTPUT(val) (((val) >> 3) & 1) /* voodoo 2 only */
1268		#define FBIINIT5_DAC_DATA_18_OUTPUT(val) (((val) >> 4) & 1) /* voodoo 2 only */
1269		#define FBIINIT5_GENERIC_STRAPPING(val) (((val) >> 5) & 0xf) /* voodoo 2 only */
1270		#define FBIINIT5_BUFFER_ALLOCATION(val) (((val) >> 9) & 3) /* voodoo 2 only */
1271		#define FBIINIT5_DRIVE_VID_CLK_SLAVE(val) (((val) >> 11) & 1) /* voodoo 2 only */
1272		#define FBIINIT5_DRIVE_DAC_DATA_16(val) (((val) >> 12) & 1) /* voodoo 2 only */
1273		#define FBIINIT5_VCLK_INPUT_SELECT(val) (((val) >> 13) & 1) /* voodoo 2 only */
1274		#define FBIINIT5_MULTI_CVG_DETECT(val) (((val) >> 14) & 1) /* voodoo 2 only */
1275		#define FBIINIT5_SYNC_RETRACE_READS(val) (((val) >> 15) & 1) /* voodoo 2 only */
1276		#define FBIINIT5_ENABLE_RHBORDER_COLOR(val) (((val) >> 16) & 1) /* voodoo 2 only */
1277		#define FBIINIT5_ENABLE_LHBORDER_COLOR(val) (((val) >> 17) & 1) /* voodoo 2 only */
1278		#define FBIINIT5_ENABLE_BVBORDER_COLOR(val) (((val) >> 18) & 1) /* voodoo 2 only */
1279		#define FBIINIT5_ENABLE_TVBORDER_COLOR(val) (((val) >> 19) & 1) /* voodoo 2 only */
1280		#define FBIINIT5_DOUBLE_HORIZ(val) (((val) >> 20) & 1) /* voodoo 2 only */
1281		#define FBIINIT5_DOUBLE_VERT(val) (((val) >> 21) & 1) /* voodoo 2 only */
1282		#define FBIINIT5_ENABLE_16BIT_GAMMA(val) (((val) >> 22) & 1) /* voodoo 2 only */
1283		#define FBIINIT5_INVERT_DAC_HSYNC(val) (((val) >> 23) & 1) /* voodoo 2 only */
1284		#define FBIINIT5_INVERT_DAC_VSYNC(val) (((val) >> 24) & 1) /* voodoo 2 only */
1285		#define FBIINIT5_ENABLE_24BIT_DACDATA(val) (((val) >> 25) & 1) /* voodoo 2 only */
1286		#define FBIINIT5_ENABLE_INTERLACING(val) (((val) >> 26) & 1) /* voodoo 2 only */
1287		#define FBIINIT5_DAC_DATA_18_CONTROL(val) (((val) >> 27) & 1) /* voodoo 2 only */
1288		#define FBIINIT5_RASTERIZER_UNIT_MODE(val) (((val) >> 30) & 3) /* voodoo 2 only */
1289
1290		#define FBIINIT6_WINDOW_ACTIVE_COUNTER(val) (((val) >> 0) & 7) /* voodoo 2 only */
1291		#define FBIINIT6_WINDOW_DRAG_COUNTER(val) (((val) >> 3) & 0x1f) /* voodoo 2 only */
1292		#define FBIINIT6_SLI_SYNC_MASTER(val) (((val) >> 8) & 1) /* voodoo 2 only */
1293		#define FBIINIT6_DAC_DATA_22_OUTPUT(val) (((val) >> 9) & 3) /* voodoo 2 only */
1294		#define FBIINIT6_DAC_DATA_23_OUTPUT(val) (((val) >> 11) & 3) /* voodoo 2 only */
1295		#define FBIINIT6_SLI_SYNCIN_OUTPUT(val) (((val) >> 13) & 3) /* voodoo 2 only */
1296		#define FBIINIT6_SLI_SYNCOUT_OUTPUT(val) (((val) >> 15) & 3) /* voodoo 2 only */
1297		#define FBIINIT6_DAC_RD_OUTPUT(val) (((val) >> 17) & 3) /* voodoo 2 only */
1298		#define FBIINIT6_DAC_WR_OUTPUT(val) (((val) >> 19) & 3) /* voodoo 2 only */
1299		#define FBIINIT6_PCI_FIFO_LWM_RDY(val) (((val) >> 21) & 0x7f) /* voodoo 2 only */
1300		#define FBIINIT6_VGA_PASS_N_OUTPUT(val) (((val) >> 28) & 3) /* voodoo 2 only */
1301		#define FBIINIT6_X_VIDEO_TILES_BIT0(val) (((val) >> 30) & 1) /* voodoo 2 only */
1302
1303		#define FBIINIT7_GENERIC_STRAPPING(val) (((val) >> 0) & 0xff) /* voodoo 2 only */
1304		#define FBIINIT7_CMDFIFO_ENABLE(val) (((val) >> 8) & 1) /* voodoo 2 only */
1305		#define FBIINIT7_CMDFIFO_MEMORY_STORE(val) (((val) >> 9) & 1) /* voodoo 2 only */
1306		#define FBIINIT7_DISABLE_CMDFIFO_HOLES(val) (((val) >> 10) & 1) /* voodoo 2 only */
1307		#define FBIINIT7_CMDFIFO_READ_THRESH(val) (((val) >> 11) & 0x1f) /* voodoo 2 only */
1308		#define FBIINIT7_SYNC_CMDFIFO_WRITES(val) (((val) >> 16) & 1) /* voodoo 2 only */
1309		#define FBIINIT7_SYNC_CMDFIFO_READS(val) (((val) >> 17) & 1) /* voodoo 2 only */
1310		#define FBIINIT7_RESET_PCI_PACKER(val) (((val) >> 18) & 1) /* voodoo 2 only */
1311		#define FBIINIT7_ENABLE_CHROMA_STUFF(val) (((val) >> 19) & 1) /* voodoo 2 only */
1312		#define FBIINIT7_CMDFIFO_PCI_TIMEOUT(val) (((val) >> 20) & 0x7f) /* voodoo 2 only */
1313		#define FBIINIT7_ENABLE_TEXTURE_BURST(val) (((val) >> 27) & 1) /* voodoo 2 only */
1314
1315		#define TEXMODE_ENABLE_PERSPECTIVE(val) (((val) >> 0) & 1)
1316		#define TEXMODE_MINIFICATION_FILTER(val) (((val) >> 1) & 1)
1317		#define TEXMODE_MAGNIFICATION_FILTER(val) (((val) >> 2) & 1)
1318		#define TEXMODE_CLAMP_NEG_W(val) (((val) >> 3) & 1)
1319		#define TEXMODE_ENABLE_LOD_DITHER(val) (((val) >> 4) & 1)
1320		#define TEXMODE_NCC_TABLE_SELECT(val) (((val) >> 5) & 1)
1321		#define TEXMODE_CLAMP_S(val) (((val) >> 6) & 1)
1322		#define TEXMODE_CLAMP_T(val) (((val) >> 7) & 1)
1323		#define TEXMODE_FORMAT(val) (((val) >> 8) & 0xf)
1324		#define TEXMODE_TC_ZERO_OTHER(val) (((val) >> 12) & 1)
1325		#define TEXMODE_TC_SUB_CLOCAL(val) (((val) >> 13) & 1)
1326		#define TEXMODE_TC_MSELECT(val) (((val) >> 14) & 7)
1327		#define TEXMODE_TC_REVERSE_BLEND(val) (((val) >> 17) & 1)
1328		#define TEXMODE_TC_ADD_ACLOCAL(val) (((val) >> 18) & 3)
1329		#define TEXMODE_TC_INVERT_OUTPUT(val) (((val) >> 20) & 1)
1330		#define TEXMODE_TCA_ZERO_OTHER(val) (((val) >> 21) & 1)
1331		#define TEXMODE_TCA_SUB_CLOCAL(val) (((val) >> 22) & 1)
1332		#define TEXMODE_TCA_MSELECT(val) (((val) >> 23) & 7)
1333		#define TEXMODE_TCA_REVERSE_BLEND(val) (((val) >> 26) & 1)
1334		#define TEXMODE_TCA_ADD_ACLOCAL(val) (((val) >> 27) & 3)
1335		#define TEXMODE_TCA_INVERT_OUTPUT(val) (((val) >> 29) & 1)
1336		#define TEXMODE_TRILINEAR(val) (((val) >> 30) & 1)
1337		#define TEXMODE_SEQ_8_DOWNLD(val) (((val) >> 31) & 1)
1338
1339		#define TEXLOD_LODMIN(val) (((val) >> 0) & 0x3f)
1340		#define TEXLOD_LODMAX(val) (((val) >> 6) & 0x3f)
1341		#define TEXLOD_LODBIAS(val) (((val) >> 12) & 0x3f)
1342		#define TEXLOD_LOD_ODD(val) (((val) >> 18) & 1)
1343		#define TEXLOD_LOD_TSPLIT(val) (((val) >> 19) & 1)
1344		#define TEXLOD_LOD_S_IS_WIDER(val) (((val) >> 20) & 1)
1345		#define TEXLOD_LOD_ASPECT(val) (((val) >> 21) & 3)
1346		#define TEXLOD_LOD_ZEROFRAC(val) (((val) >> 23) & 1)
1347		#define TEXLOD_TMULTIBASEADDR(val) (((val) >> 24) & 1)
1348		#define TEXLOD_TDATA_SWIZZLE(val) (((val) >> 25) & 1)
1349		#define TEXLOD_TDATA_SWAP(val) (((val) >> 26) & 1)
1350		#define TEXLOD_TDIRECT_WRITE(val) (((val) >> 27) & 1) /* Voodoo 2 only */
1351
1352		#define TEXDETAIL_DETAIL_MAX(val) (((val) >> 0) & 0xff)
1353		#define TEXDETAIL_DETAIL_BIAS(val) (((val) >> 8) & 0x3f)
1354		#define TEXDETAIL_DETAIL_SCALE(val) (((val) >> 14) & 7)
1355		#define TEXDETAIL_RGB_MIN_FILTER(val) (((val) >> 17) & 1) /* Voodoo 2 only */
1356		#define TEXDETAIL_RGB_MAG_FILTER(val) (((val) >> 18) & 1) /* Voodoo 2 only */
1357		#define TEXDETAIL_ALPHA_MIN_FILTER(val) (((val) >> 19) & 1) /* Voodoo 2 only */
1358		#define TEXDETAIL_ALPHA_MAG_FILTER(val) (((val) >> 20) & 1) /* Voodoo 2 only */
1359		#define TEXDETAIL_SEPARATE_RGBA_FILTER(val) (((val) >> 21) & 1) /* Voodoo 2 only */
1360
1361		#define TREXINIT_SEND_TMU_CONFIG(val) (((val) >> 18) & 1)
1362
1363
1364
1365		struct voodoo_state;
1366		struct poly_extra_data;
1367		class voodoo_device;
1368
1369		struct rgba
1370		{
1371		#ifdef LSB_FIRST
1372		UINT8 b, g, r, a;
1373		#else
1374		UINT8 a, r, g, b;
1375		#endif
1376		};
1377
1378
1379		union voodoo_reg
1380		{
1381		INT32 i;
1382		UINT32 u;
1383		float f;
1384		rgba rgb;
1385		};
1386
1387
1388
1389		struct voodoo_stats
1390		{
1391		UINT8 lastkey; /* last key state */
1392		UINT8 display; /* display stats? */
1393		INT32 swaps; /* total swaps */
1394		INT32 stalls; /* total stalls */
1395		INT32 total_triangles; /* total triangles */
1396		INT32 total_pixels_in; /* total pixels in */
1397		INT32 total_pixels_out; /* total pixels out */
1398		INT32 total_chroma_fail; /* total chroma fail */
1399		INT32 total_zfunc_fail; /* total z func fail */
1400		INT32 total_afunc_fail; /* total a func fail */
1401		INT32 total_clipped; /* total clipped */
1402		INT32 total_stippled; /* total stippled */
1403		INT32 lfb_writes; /* LFB writes */
1404		INT32 lfb_reads; /* LFB reads */
1405		INT32 reg_writes; /* register writes */
1406		INT32 reg_reads; /* register reads */
1407		INT32 tex_writes; /* texture writes */
1408		INT32 texture_mode[16]; /* 16 different texture modes */
1409		UINT8 render_override; /* render override */
1410		char buffer[1024]; /* string */
1411		};
1412
1413
1414		/* note that this structure is an even 64 bytes long */
1415		struct stats_block
1416		{
1417		INT32 pixels_in; /* pixels in statistic */
1418		INT32 pixels_out; /* pixels out statistic */
1419		INT32 chroma_fail; /* chroma test fail statistic */
1420		INT32 zfunc_fail; /* z function test fail statistic */
1421		INT32 afunc_fail; /* alpha function test fail statistic */
1422		INT32 clip_fail; /* clipping fail statistic */
1423		INT32 stipple_count; /* stipple statistic */
1424		INT32 filler[64/4 - 7]; /* pad this structure to 64 bytes */
1425		};
1426
1427
1428		struct fifo_state
1429		{
1430		UINT32 * base; /* base of the FIFO */
1431		INT32 size; /* size of the FIFO */
1432		INT32 in; /* input pointer */
1433		INT32 out; /* output pointer */
1434		};
1435
1436
1437		struct cmdfifo_info
1438		{
1439		UINT8 enable; /* enabled? */
1440		UINT8 count_holes; /* count holes? */
1441		UINT32 base; /* base address in framebuffer RAM */
1442		UINT32 end; /* end address in framebuffer RAM */
1443		UINT32 rdptr; /* current read pointer */
1444		UINT32 amin; /* minimum address */
1445		UINT32 amax; /* maximum address */
1446		UINT32 depth; /* current depth */
1447		UINT32 holes; /* number of holes */
1448		};
1449
1450
1451		struct pci_state
1452		{
1453		fifo_state fifo; /* PCI FIFO */
1454		UINT32 init_enable; /* initEnable value */
1455		UINT8 stall_state; /* state of the system if we're stalled */
1456		UINT8 op_pending; /* true if an operation is pending */
1457		attotime op_end_time; /* time when the pending operation ends */
1458		emu_timer * continue_timer; /* timer to use to continue processing */
1459		UINT32 fifo_mem[642]; / memory backing the PCI FIFO */
1460		};
1461
1462
1463		struct ncc_table
1464		{
1465		UINT8 dirty; /* is the texel lookup dirty? */
1466		voodoo_reg * reg; /* pointer to our registers */
1467		INT32 ir[4], ig[4], ib[4]; /* I values for R,G,B */
1468		INT32 qr[4], qg[4], qb[4]; /* Q values for R,G,B */
1469		INT32 y[16]; /* Y values */
1470		rgb_t * palette; /* pointer to associated RGB palette */
1471		rgb_t * palettea; /* pointer to associated ARGB palette */
1472		rgb_t texel[256]; /* texel lookup */
1473		};
1474
1475
1476		struct tmu_state
1477		{
1478		UINT8 * ram; /* pointer to our RAM */
1479		UINT32 mask; /* mask to apply to pointers */
1480		voodoo_reg * reg; /* pointer to our register base */
1481		UINT32 regdirty; /* true if the LOD/mode/base registers have changed */
1482
1483		UINT32 texaddr_mask; /* mask for texture address */
1484		UINT8 texaddr_shift; /* shift for texture address */
1485
1486		INT64 starts, startt; /* starting S,T (14.18) */
1487		INT64 startw; /* starting W (2.30) */
1488		INT64 dsdx, dtdx; /* delta S,T per X */
1489		INT64 dwdx; /* delta W per X */
1490		INT64 dsdy, dtdy; /* delta S,T per Y */
1491		INT64 dwdy; /* delta W per Y */
1492
1493		INT32 lodmin, lodmax; /* min, max LOD values */
1494		INT32 lodbias; /* LOD bias */
1495		UINT32 lodmask; /* mask of available LODs */
1496		UINT32 lodoffset[9]; /* offset of texture base for each LOD */
1497		INT32 detailmax; /* detail clamp */
1498		INT32 detailbias; /* detail bias */
1499		UINT8 detailscale; /* detail scale */
1500
1501		UINT32 wmask; /* mask for the current texture width */
1502		UINT32 hmask; /* mask for the current texture height */
1503
1504		UINT32 bilinear_mask; /* mask for bilinear resolution (0xf0 for V1, 0xff for V2) */
1505
1506		ncc_table ncc[2]; /* two NCC tables */
1507
1508		rgb_t * lookup; /* currently selected lookup */
1509		rgb_t * texel[16]; /* texel lookups for each format */
1510
1511		rgb_t palette[256]; /* palette lookup table */
1512		rgb_t palettea[256]; /* palette+alpha lookup table */
1513		};
1514
1515
1516		struct tmu_shared_state
1517		{
1518		rgb_t rgb332[256]; /* RGB 3-3-2 lookup table */
1519		rgb_t alpha8[256]; /* alpha 8-bit lookup table */
1520		rgb_t int8[256]; /* intensity 8-bit lookup table */
1521		rgb_t ai44[256]; /* alpha, intensity 4-4 lookup table */
1522
1523		rgb_t rgb565[65536]; /* RGB 5-6-5 lookup table */
1524		rgb_t argb1555[65536]; /* ARGB 1-5-5-5 lookup table */
1525		rgb_t argb4444[65536]; /* ARGB 4-4-4-4 lookup table */
1526		};
1527
1528
1529		struct setup_vertex
1530		{
1531		float x, y; /* X, Y coordinates */
1532		float a, r, g, b; /* A, R, G, B values */
1533		float z, wb; /* Z and broadcast W values */
1534		float w0, s0, t0; /* W, S, T for TMU 0 */
1535		float w1, s1, t1; /* W, S, T for TMU 1 */
1536		};
1537
1538
1539		struct fbi_state
1540		{
1541		UINT8 * ram; /* pointer to frame buffer RAM */
1542		UINT32 mask; /* mask to apply to pointers */
1543		UINT32 rgboffs[3]; /* word offset to 3 RGB buffers */
1544		UINT32 auxoffs; /* word offset to 1 aux buffer */
1545
1546		UINT8 frontbuf; /* front buffer index */
1547		UINT8 backbuf; /* back buffer index */
1548		UINT8 swaps_pending; /* number of pending swaps */
1549		UINT8 video_changed; /* did the frontbuffer video change? */
1550
1551		UINT32 yorigin; /* Y origin subtract value */
1552		UINT32 lfb_base; /* base of LFB in memory */
1553		UINT8 lfb_stride; /* stride of LFB accesses in bits */
1554
1555		UINT32 width; /* width of current frame buffer */
1556		UINT32 height; /* height of current frame buffer */
1557		UINT32 xoffs; /* horizontal offset (back porch) */
1558		UINT32 yoffs; /* vertical offset (back porch) */
1559		UINT32 vsyncscan; /* vertical sync scanline */
1560		UINT32 rowpixels; /* pixels per row */
1561		UINT32 tile_width; /* width of video tiles */
1562		UINT32 tile_height; /* height of video tiles */
1563		UINT32 x_tiles; /* number of tiles in the X direction */
1564
1565		emu_timer * vblank_timer; /* VBLANK timer */
1566		UINT8 vblank; /* VBLANK state */
1567		UINT8 vblank_count; /* number of VBLANKs since last swap */
1568		UINT8 vblank_swap_pending; /* a swap is pending, waiting for a vblank */
1569		UINT8 vblank_swap; /* swap when we hit this count */
1570		UINT8 vblank_dont_swap; /* don't actually swap when we hit this point */
1571
1572		/* triangle setup info */
1573		UINT8 cheating_allowed; /* allow cheating? */
1574		INT32 sign; /* triangle sign */
1575		INT16 ax, ay; /* vertex A x,y (12.4) */
1576		INT16 bx, by; /* vertex B x,y (12.4) */
1577		INT16 cx, cy; /* vertex C x,y (12.4) */
1578		INT32 startr, startg, startb, starta; /* starting R,G,B,A (12.12) */
1579		INT32 startz; /* starting Z (20.12) */
1580		INT64 startw; /* starting W (16.32) */
1581		INT32 drdx, dgdx, dbdx, dadx; /* delta R,G,B,A per X */
1582		INT32 dzdx; /* delta Z per X */
1583		INT64 dwdx; /* delta W per X */
1584		INT32 drdy, dgdy, dbdy, dady; /* delta R,G,B,A per Y */
1585		INT32 dzdy; /* delta Z per Y */
1586		INT64 dwdy; /* delta W per Y */
1587
1588		stats_block lfb_stats; /* LFB-access statistics */
1589
1590		UINT8 sverts; /* number of vertices ready */
1591		setup_vertex svert[3]; /* 3 setup vertices */
1592
1593		fifo_state fifo; /* framebuffer memory fifo */
1594		cmdfifo_info cmdfifo[2]; /* command FIFOs */
1595
1596		UINT8 fogblend[64]; /* 64-entry fog table */
1597		UINT8 fogdelta[64]; /* 64-entry fog table */
1598		UINT8 fogdelta_mask; /* mask for for delta (0xff for V1, 0xfc for V2) */
1599
1600		rgb_t pen[65536]; /* mapping from pixels to pens */
1601		rgb_t clut[512]; /* clut gamma data */
1602		UINT8 clut_dirty; /* do we need to recompute? */
1603		};
1604
1605
1606		struct dac_state
1607		{
1608		UINT8 reg[8]; /* 8 registers */
1609		UINT8 read_result; /* pending read result */
1610		};
1611
1612
1613		struct raster_info
1614		{
1615		raster_info * next; /* pointer to next entry with the same hash */
1616		poly_draw_scanline_func callback; /* callback pointer */
1617		UINT8 is_generic; /* TRUE if this is one of the generic rasterizers */
1618		UINT8 display; /* display index */
1619		UINT32 hits; /* how many hits (pixels) we've used this for */
1620		UINT32 polys; /* how many polys we've used this for */
1621		UINT32 eff_color_path; /* effective fbzColorPath value */
1622		UINT32 eff_alpha_mode; /* effective alphaMode value */
1623		UINT32 eff_fog_mode; /* effective fogMode value */
1624		UINT32 eff_fbz_mode; /* effective fbzMode value */
1625		UINT32 eff_tex_mode_0; /* effective textureMode value for TMU #0 */
1626		UINT32 eff_tex_mode_1; /* effective textureMode value for TMU #1 */
1627		UINT32 hash;
1628		};
1629
1630
1631		struct poly_extra_data
1632		{
1633		voodoo_device * device;
1634		raster_info * info; /* pointer to rasterizer information */
1635
1636		INT16 ax, ay; /* vertex A x,y (12.4) */
1637		INT32 startr, startg, startb, starta; /* starting R,G,B,A (12.12) */
1638		INT32 startz; /* starting Z (20.12) */
1639		INT64 startw; /* starting W (16.32) */
1640		INT32 drdx, dgdx, dbdx, dadx; /* delta R,G,B,A per X */
1641		INT32 dzdx; /* delta Z per X */
1642		INT64 dwdx; /* delta W per X */
1643		INT32 drdy, dgdy, dbdy, dady; /* delta R,G,B,A per Y */
1644		INT32 dzdy; /* delta Z per Y */
1645		INT64 dwdy; /* delta W per Y */
1646
1647		INT64 starts0, startt0; /* starting S,T (14.18) */
1648		INT64 startw0; /* starting W (2.30) */
1649		INT64 ds0dx, dt0dx; /* delta S,T per X */
1650		INT64 dw0dx; /* delta W per X */
1651		INT64 ds0dy, dt0dy; /* delta S,T per Y */
1652		INT64 dw0dy; /* delta W per Y */
1653		INT32 lodbase0; /* used during rasterization */
1654
1655		INT64 starts1, startt1; /* starting S,T (14.18) */
1656		INT64 startw1; /* starting W (2.30) */
1657		INT64 ds1dx, dt1dx; /* delta S,T per X */
1658		INT64 dw1dx; /* delta W per X */
1659		INT64 ds1dy, dt1dy; /* delta S,T per Y */
1660		INT64 dw1dy; /* delta W per Y */
1661		INT32 lodbase1; /* used during rasterization */
1662
1663		UINT16 dither[16]; /* dither matrix, for fastfill */
1664		};
1665
1666
1667		struct banshee_info
1668		{
1669		UINT32 io[0x40]; /* I/O registers */
1670		UINT32 agp[0x80]; /* AGP registers */
1671		UINT8 vga[0x20]; /* VGA registers */
1672		UINT8 crtc[0x27]; /* VGA CRTC registers */
1673		UINT8 seq[0x05]; /* VGA sequencer registers */
1674		UINT8 gc[0x05]; /* VGA graphics controller registers */
1675		UINT8 att[0x15]; /* VGA attribute registers */
1676		UINT8 attff; /* VGA attribute flip-flop */
1677
1678		UINT32 blt_regs[0x20]; /* 2D Blitter registers */
1679		UINT32 blt_dst_base;
1680		UINT32 blt_dst_x;
1681		UINT32 blt_dst_y;
1682		UINT32 blt_dst_width;
1683		UINT32 blt_dst_height;
1684		UINT32 blt_dst_stride;
1685		UINT32 blt_dst_bpp;
1686		UINT32 blt_cmd;
1687		UINT32 blt_src_base;
1688		UINT32 blt_src_x;
1689		UINT32 blt_src_y;
1690		UINT32 blt_src_width;
1691		UINT32 blt_src_height;
1692		UINT32 blt_src_stride;
1693		UINT32 blt_src_bpp;
1694		};
1695
1696
1697		typedef voodoo_reg rgb_union;
1698
1699
1700
1701
1702
1703	18	/***************************************************************************
1704	19	CONSTANTS
1705	20	***************************************************************************/
r253151	r253152
1746	61	FUNCTION PROTOTYPES
1747	62	***************************************************************************/
1748	63
1749		struct stats_block;
	64	int voodoo_update(device_t *device, bitmap_rgb32 &bitmap, const rectangle &cliprect);
	65	int voodoo_get_type(device_t *device);
	66	int voodoo_is_stalled(device_t *device);
	67	void voodoo_set_init_enable(device_t *device, UINT32 newval);
1750	68
1751	69	/* ----- device interface ----- */
1752	70
r253151	r253152
1768	86	DECLARE_WRITE32_MEMBER( voodoo_w );
1769	87
1770	88	// access to legacy token
	89	struct voodoo_state *token() const { assert(m_token != nullptr); return m_token; }
1771	90	void common_start_voodoo(UINT8 type);
1772	91
1773	92	UINT8 m_fbmem;
r253151	r253152
1777	96	const char * m_cputag;
1778	97	devcb_write_line m_vblank;
1779	98	devcb_write_line m_stall;
1780
1781		TIMER_CALLBACK_MEMBER( vblank_off_callback );
1782		TIMER_CALLBACK_MEMBER( stall_cpu_callback );
1783		TIMER_CALLBACK_MEMBER( vblank_callback );
1784	99
1785		static void voodoo_postload(voodoo_device *vd);
1786
1787		int voodoo_update(bitmap_rgb32 &bitmap, const rectangle &cliprect);
1788		int voodoo_get_type();
1789		int voodoo_is_stalled();
1790		void voodoo_set_init_enable(UINT32 newval);
1791
1792		// not all of these need to be static, review.
1793
1794		static void check_stalled_cpu(voodoo_device* vd, attotime current_time);
1795		static void flush_fifos( voodoo_device* vd, attotime current_time);
1796		static void init_fbi(voodoo_device vd, fbi_state f, void *memory, int fbmem);
1797		static INT32 register_w(voodoo_device *vd, offs_t offset, UINT32 data);
1798		static INT32 swapbuffer(voodoo_device *vd, UINT32 data);
1799		static void init_tmu(voodoo_device vd, tmu_state t, voodoo_reg reg, void memory, int tmem);
1800		static INT32 lfb_w(voodoo_device *vd, offs_t offset, UINT32 data, UINT32 mem_mask);
1801		static INT32 texture_w(voodoo_device *vd, offs_t offset, UINT32 data);
1802		static INT32 lfb_direct_w(voodoo_device *vd, offs_t offset, UINT32 data, UINT32 mem_mask);
1803		static INT32 banshee_2d_w(voodoo_device *vd, offs_t offset, UINT32 data);
1804		static void stall_cpu(voodoo_device *vd, int state, attotime current_time);
1805		static void soft_reset(voodoo_device *vd);
1806		static void recompute_video_memory(voodoo_device *vd);
1807		static INT32 fastfill(voodoo_device *vd);
1808		static INT32 triangle(voodoo_device *vd);
1809		static INT32 begin_triangle(voodoo_device *vd);
1810		static INT32 draw_triangle(voodoo_device *vd);
1811		static INT32 setup_and_draw_triangle(voodoo_device *vd);
1812		static INT32 triangle_create_work_item(voodoo_device* vd,UINT16 *drawbuf, int texcount);
1813		static raster_info add_rasterizer(voodoo_device vd, const raster_info *cinfo);
1814		static raster_info find_rasterizer(voodoo_device vd, int texcount);
1815		static void dump_rasterizer_stats(voodoo_device *vd);
1816		static void init_tmu_shared(tmu_shared_state *s);
1817
1818		static void swap_buffers(voodoo_device *vd);
1819		static UINT32 cmdfifo_execute(voodoo_device vd, cmdfifo_info f);
1820		static INT32 cmdfifo_execute_if_ready(voodoo_device* vd, cmdfifo_info *f);
1821		static void cmdfifo_w(voodoo_device vd, cmdfifo_info f, offs_t offset, UINT32 data);
1822
1823		static void raster_fastfill(void dest, INT32 scanline, const poly_extent extent, const void *extradata, int threadid);
1824		static void raster_generic_0tmu(void dest, INT32 scanline, const poly_extent extent, const void *extradata, int threadid);
1825		static void raster_generic_1tmu(void dest, INT32 scanline, const poly_extent extent, const void *extradata, int threadid);
1826		static void raster_generic_2tmu(void dest, INT32 scanline, const poly_extent extent, const void *extradata, int threadid);
1827
1828		#define RASTERIZER_HEADER(name) \
1829		static void raster_##name(void destbase, INT32 y, const poly_extent extent, const void *extradata, int threadid); \
1830
1831		#define RASTERIZER_ENTRY(fbzcp, alpha, fog, fbz, tex0, tex1) \
1832		RASTERIZER_HEADER(fbzcp##_##alpha##_##fog##_##fbz##_##tex0##_##tex1) \
1833
1834		#include "voodoo_rast.inc"
1835
1836		#undef RASTERIZER_ENTRY
1837
1838
1839
1840	100	protected:
1841	101	// device-level overrides
1842	102	virtual void device_config_complete() override;
1843	103	virtual void device_stop() override;
1844	104	virtual void device_reset() override;
1845		public:
1846		// voodoo_state
1847		UINT8 index; /* index of board */
1848		voodoo_device device; / pointer to our containing device */
1849		screen_device screen; / the screen we are acting on */
1850		device_t cpu; / the CPU we interact with */
1851		UINT8 vd_type; /* type of system */
1852		UINT8 chipmask; /* mask for which chips are available */
1853		UINT32 freq; /* operating frequency */
1854		attoseconds_t attoseconds_per_cycle; /* attoseconds per cycle */
1855		UINT32 extra_cycles; /* extra cycles not yet accounted for */
1856		int trigger; /* trigger used for stalling */
1857
1858		voodoo_reg reg[0x400]; /* raw registers */
1859		const UINT8 * regaccess; /* register access array */
1860		const char const regnames; /* register names array */
1861		UINT8 alt_regmap; /* enable alternate register map? */
1862
1863		pci_state pci; /* PCI state */
1864		dac_state dac; /* DAC state */
1865
1866		fbi_state fbi; /* FBI states */
1867		tmu_state tmu[MAX_TMU]; /* TMU states */
1868		tmu_shared_state tmushare; /* TMU shared state */
1869		banshee_info banshee; /* Banshee state */
1870
1871		legacy_poly_manager * poly; /* polygon manager */
1872		stats_block * thread_stats; /* per-thread statistics */
1873
1874		voodoo_stats stats; /* internal statistics */
1875
1876		offs_t last_status_pc; /* PC of last status description (for logging) */
1877		UINT32 last_status_value; /* value of last status read (for logging) */
1878
1879		int next_rasterizer; /* next rasterizer index */
1880		raster_info rasterizer[MAX_RASTERIZERS]; /* array of rasterizers */
1881		raster_info * raster_hash[RASTER_HASH_SIZE]; /* hash table of rasterizers */
1882
1883		bool send_config;
1884		UINT32 tmu_config;
1885
	105	private:
	106	// internal state
	107	struct voodoo_state *m_token;
1886	108	};
1887	109
1888	110	class voodoo_1_device : public voodoo_device

trunk/src/devices/video/voodoo_pci.cpp
r253151	r253152
153	153
154	154	UINT32 voodoo_pci_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
155	155	{
156		return m_voodoo~~->voodoo~~_update(bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
	156	return voodoo_update(m_voodoo, bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
157	157	}
158	158
159	159	// PCI bus control
r253151	r253152
170	170	switch (offset) {
171	171	case 0x0/4: // The address map starts at 0x40
172	172	// HW initEnable
173		m_voodoo~~->voodoo~~_set_init_enable(data);
	173	voodoo_set_init_enable(m_voodoo, data);
174	174	logerror("%06X:voodoo_pci_device pcictrl_w to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
175	175	break;
176	176	default:

trunk/src/emu/emuopts.cpp
r253151	r253152
262	262	{
263	263	std::string featurename = std::string(name).append("_default");
264	264	const char *value = swpart->feature(featurename.c_str());
265		if (value != nullptr ~~&& (*value == '\0' \|\| slot->option(value) != nullptr)~~)
	265	if (value != nullptr)
266	266	set_default_value(name, value);
267	267	}
268	268	}

trunk/src/mame/arcade.lst
r253151	r253152
5143	5143	vmahjong // 1997.02 Virtual Mahjong (Micronet)
5144	5144	pclub2kc // 1997.02 Print Club Kome Kome Club
5145	5145	pclub2fc // 1997.04 Print Club 2 Felix The Cat
5146		pclub2pe //
5147		pclub2pf //
5148		pclub26w //
5149		pclub27s //
5150		pclubyo2 //
5151	5146	groovef // 1997.05 Groove on Fight (Atlus)
5152	5147	nclubv3 // 1997.07 Name Club Ver. 3
5153		nclubv2 //
5154		nameclub //
5155	5148	pclb2elk // 1997.07 Print Club Custom
5156	5149	pclub2 // 1997.09 Print Club 2
5157	5150	thunt // 1997.09 Puzzle & Action Treasure Hunt (Sega (Deniam License))
r253151	r253152
5159	5152	winterht // 1997.10 Winter Heat (Data East)
5160	5153	pclb297w // 1997.10 Print Club 2 '97 Winter Ver
5161	5154	pclub298 // 1997.10 Print Club 2 '98 Spring Ver
5162		pclove
5163	5155	cotton2 // 1997.11 Cotton 2 (Success)
5164	5156	hanagumi // 1997.11 Sakura Taisen Hanagumi Taisen Columns
5165	5157	findlove // 1997.12 Find Love (Daiki / FCF)
r253151	r253152
9278	9270	bonkadv // (c) 1994 Kaneko
9279	9271	gtmr // (c) 1994 Kaneko
9280	9272	gtmra // (c) 1994 Kaneko
9281		gtmrb // (c) 1994 Kaneko
9282	9273	gtmro // (c) 1994 Kaneko
9283	9274	gtmre // (c) 1994 Kaneko
9284	9275	gtmrusa // (c) 1994 Kaneko (US)
r253151	r253152
9861	9852
9862	9853	// ESD games
9863	9854	// http://www.esdgame.co.kr/english/
9864		multchmp // (c) 1999 (World)
	9855	multchmp // (c) 1998 (World)
9865	9856	multchmpk // (c) 1998 (Korea)
9866		multchmpa // (c) 1998 (World)
9867	9857	mchampdx // (c) 1999 ESD
9868	9858	mchampdxa // (c) 1999 ESD
9869	9859	mchampdxb // (c) 1999 ESD
r253151	r253152
10869	10859	dorachan // (c) 1980 Craul Denshi
10870	10860	ladyfrog // (c) 1990 Mondial Games
10871	10861	toucheme
10872		touchemea
10873	10862	rabbit // (c) 1997 Electronic Arts
10874	10863	tmmjprd // (c) 1997 Media / Sonnet
10875	10864	tmpdoki // (c) 1998 Media Syouji

trunk/src/mame/drivers/arkanoid.cpp
r253151	r253152
1245	1245
1246	1246	void arkanoid_state::machine_start()
1247	1247	{
1248		// allocate the MCU timer, even if we have no MCU, and set it to fire NEVER.
1249		m_68705_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(arkanoid_state::timer_68705_increment),this));
1250		m_68705_timer->adjust(attotime::never);
1251
1252	1248	save_item(NAME(m_gfxbank));
1253	1249	save_item(NAME(m_palettebank));
1254	1250
r253151	r253152
1288	1284	m_z80HasWritten = 0;
1289	1285	m_68705HasWritten = 0;
1290	1286	if (m_mcu.found()) m_mcu->set_input_line(M68705_IRQ_LINE, CLEAR_LINE);
1291		if (m_mcu.found()) m_68705_timer->adjust(attotime::from_hz(((XTAL_12MHz/4)/4)/(1<<7)));
1292	1287
1293	1288	m_port_a_in = 0;
1294	1289	m_port_a_out = 0;

trunk/src/mame/drivers/esd16.cpp
r253151	r253152
826	826	ROM_LOAD( "esd4.su10", 0x00000, 0x20000, CRC(6e741fcd) SHA1(742e0952916c00f67dd9f8d01e721a9a538d2fc4) )
827	827	ROM_END
828	828
829		ROM_START( multchmpa )
830		ROM_REGION( 0x080000, "maincpu", 0 ) /* 68000 Code */
831		ROM_LOAD16_BYTE( "esd2.cu02", 0x000000, 0x040000, CRC(bfd39198) SHA1(11c0cb7a865daa1be9301ddfa5f5d2014e8f9908) )
832		ROM_LOAD16_BYTE( "esd1.cu03", 0x000001, 0x040000, CRC(cd769077) SHA1(741cca679393dab031691834874c96fee791241e) )
833
834		ROM_REGION( 0x40000, "audiocpu", 0 ) /* Z80 Code */
835		ROM_LOAD( "esd3.su01", 0x00000, 0x20000, CRC(7c178bd7) SHA1(8754d3c70d9b2bf369a5ce0cce4cc0696ed22750) )
836
837		ROM_REGION( 0x180000, "spr", 0 ) /* Sprites, 16x16x5 */
838		ROM_LOAD16_BYTE( "esd17.ju06", 0x000000, 0x040000, CRC(51f01067) SHA1(d5ebbc7d358b63724d2f24da8b2ce4a202be37a5) )
839		ROM_LOAD16_BYTE( "esd16.ju05", 0x000001, 0x040000, CRC(88e252e8) SHA1(07d898379798c6be42b636762b0af61b9111a480) )
840		ROM_LOAD16_BYTE( "esd15.ju04", 0x080000, 0x040000, CRC(b1ae7f08) SHA1(37dd9d4cef8b9e1d09d7b46a9794fb2b777c9a01) )
841		ROM_LOAD16_BYTE( "esd14.ju03", 0x080001, 0x040000, CRC(d8f06fa8) SHA1(f76912f93f99578529612a7f01d82ac7229a8e41) )
842		ROM_LOAD16_BYTE( "esd13.ju07", 0x100000, 0x040000, CRC(9d1590a6) SHA1(35f634dbf0df06ec62359c7bae43c7f5d14b0ab2) )
843
844		ROM_REGION( 0x400000, "bgs", 0 ) /* Layers, 16x16x8 */
845		ROM_LOAD32_BYTE( "esd9.fu28", 0x000000, 0x080000, CRC(a3cfe895) SHA1(a8dc0d5d9e64d4c5112177b8f20b5bdb86ca73af) )
846		ROM_LOAD32_BYTE( "esd11.fu29", 0x000001, 0x080000, CRC(d3c1855e) SHA1(bb547d4a45a745e9ae4a6727087cdf325105de90) )
847		ROM_LOAD32_BYTE( "esd7.fu26", 0x000002, 0x080000, CRC(042d59ff) SHA1(8e45a4757e07d8aaf50b151d8849c1a27424e64b) )
848		ROM_LOAD32_BYTE( "esd5.fu27", 0x000003, 0x080000, CRC(ed5b4e58) SHA1(82c3ee9e2525c0b370a29d5560c21ec6380d1a43) )
849		ROM_LOAD32_BYTE( "esd10.fu31", 0x200000, 0x080000, CRC(396d77b6) SHA1(f22449a7f9f50e172e36db4f399c14e527409884) )
850		ROM_LOAD32_BYTE( "esd12.fu33", 0x200001, 0x080000, CRC(a68848a8) SHA1(915239a961d76af6a1a567eb89b1569f158e714e) )
851		ROM_LOAD32_BYTE( "esd8.fu30", 0x200002, 0x080000, CRC(fa8cd2d3) SHA1(ddc1b98867e6d2eee458bf35a933e7cdc59f4c7e) )
852		ROM_LOAD32_BYTE( "esd6.fu32", 0x200003, 0x080000, CRC(97fde7b1) SHA1(b3610f6fcc1367ff079dc01121c86bc1e1f4c7a2) )
853
854		ROM_REGION( 0x40000, "oki", 0 ) /* Samples */
855		ROM_LOAD( "esd4.su08", 0x00000, 0x20000, CRC(6e741fcd) SHA1(742e0952916c00f67dd9f8d01e721a9a538d2fc4) )
856		ROM_END
857
858
859
860	829	/*
861	830
862	831	Multi Champ Deluxe
r253151	r253152
1561	1530
1562	1531	/* ESD 11-09-98 */
1563	1532	GAME( 1999, multchmp, 0, esd16, multchmp, driver_device, 0, ROT0, "ESD", "Multi Champ (World, ver. 2.5)", MACHINE_SUPPORTS_SAVE )
1564		GAME( 1998, multchmpk,multchmp, esd16, multchmp, driver_device, 0, ROT0, "ESD", "Multi Champ (Korea, older)", MACHINE_SUPPORTS_SAVE )
1565		GAME( 1998, multchmpa,multchmp, esd16, multchmp, driver_device, 0, ROT0, "ESD", "Multi Champ (World, older)", MACHINE_SUPPORTS_SAVE )
1566
	1533	GAME( 1998, multchmpk,multchmp, esd16, multchmp, driver_device, 0, ROT0, "ESD", "Multi Champ (Korea)", MACHINE_SUPPORTS_SAVE )
1567	1534	GAME( 2001, jumppop, 0, jumppop, jumppop, driver_device, 0, ROT0, "ESD", "Jumping Pop (set 1)", MACHINE_SUPPORTS_SAVE ) /* Redesigned(?) ESD 11-09-98 with no ID# */
1568	1535	GAME( 2001, jumppope, jumppop, jumppop, jumppop, driver_device, 0, ROT0, "Emag Soft", "Jumping Pop (set 2)", MACHINE_SUPPORTS_SAVE )
1569	1536

trunk/src/mame/drivers/fidelz80.cpp
r253151	r253152
1537	1537	Machine Drivers
1538	1538	******************************************************************************/
1539	1539
1540		static MACHINE_CONFIG_START( cc7, fidelz80_state )
1541
1542		/* basic machine hardware */
1543		MCFG_CPU_ADD("maincpu", Z80, XTAL_3_579545MHz)
1544		MCFG_CPU_PROGRAM_MAP(cc10_map)
1545		//MCFG_CPU_IO_MAP(vcc_io)
1546
1547		MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", fidelz80base_state, display_decay_tick, attotime::from_msec(1))
1548		MCFG_DEFAULT_LAYOUT(layout_fidel_cc)
1549
1550		/* sound hardware */
1551		MCFG_SPEAKER_STANDARD_MONO("mono")
1552		MCFG_SOUND_ADD("beeper", BEEP, 0)
1553		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
1554		MACHINE_CONFIG_END
1555
1556	1540	static MACHINE_CONFIG_START( cc10, fidelz80_state )
1557	1541
1558	1542	/* basic machine hardware */
r253151	r253152
1657	1641	ROM Definitions
1658	1642	******************************************************************************/
1659	1643
1660		ROM_START( cc7 )
1661		ROM_REGION( 0x10000, "maincpu", 0 )
1662		ROM_LOAD( "cn19103n_bcc-revb", 0x0000, 0x1000, CRC(a397d471) SHA1(9b12bc442fccee40f4d8500c792bc9d886c5e1a5) ) // 2332
1663		ROM_END
1664
1665	1644	ROM_START( cc10 )
1666	1645	ROM_REGION( 0x10000, "maincpu", 0 )
1667	1646	ROM_LOAD( "cc10b", 0x0000, 0x1000, CRC(afd3ca99) SHA1(870d09b2b52ccb8572d69642c59b5215d5fb26ab) ) // 2332
r253151	r253152
1825	1804	******************************************************************************/
1826	1805
1827	1806	/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY, FULLNAME, FLAGS */
1828		COMP( 1978, cc10, 0, 0, cc10, cc10, driver_device, 0, "Fidelity Electronics", "Chess Challenger 10 (rev. B)", MACHINE_SUPPORTS_SAVE )
1829		COMP( 1979, cc7, 0, 0, cc7, cc10, driver_device, 0, "Fidelity Electronics", "Chess Challenger 7 (rev. B)", MACHINE_SUPPORTS_SAVE \| MACHINE_NOT_WORKING )
	1807	COMP( 1978, cc10, 0, 0, cc10, cc10, driver_device, 0, "Fidelity Electronics", "Chess Challenger 10 (version B)", MACHINE_SUPPORTS_SAVE )
1830	1808
1831	1809	COMP( 1979, vcc, 0, 0, vcc, vcc, driver_device, 0, "Fidelity Electronics", "Voice Chess Challenger (English)", MACHINE_SUPPORTS_SAVE )
1832	1810	COMP( 1979, vccsp, vcc, 0, vcc, vccsp, driver_device, 0, "Fidelity Electronics", "Voice Chess Challenger (Spanish)", MACHINE_SUPPORTS_SAVE )

trunk/src/mame/drivers/funkball.cpp
r253151	r253152
142	142
143	143	UINT32 funkball_state::screen_update( screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect )
144	144	{
145		return m_voodoo~~->voodoo~~_update(bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
	145	return voodoo_update(m_voodoo, bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
146	146	}
147	147
148	148	static UINT32 voodoo_0_pci_r(device_t busdevice, device_t device, int function, int reg, UINT32 mem_mask)
r253151	r253152
186	186	break;
187	187	case 0x40:
188	188	state->m_voodoo_pci_regs.init_enable = data;
189		~~state->m_~~voodoo~~->voodoo~~_set_init_enable(data);
	189	voodoo_set_init_enable(state->m_voodoo, data);
190	190	break;
191	191	}
192	192	}

trunk/src/mame/drivers/gticlub.cpp
r253151	r253152
910	910
911	911	if (strcmp(screen.tag(), ":lscreen") == 0)
912	912	{
913		~~voo~~d~~oo_d~~evice voodoo = ~~(voodoo_device)~~machine().device("voodoo0");
	913	device_t *voodoo = machine().device("voodoo0");
914	914
915	915	// m_k001604_1->draw_back_layer(bitmap, cliprect);
916	916
917		voodoo~~->voodoo~~_update(bitmap, cliprect);
	917	voodoo_update(voodoo, bitmap, cliprect);
918	918
919	919	m_k001604_1->draw_front_layer(screen, bitmap, cliprect);
920	920	}
921	921	else if (strcmp(screen.tag(), ":rscreen") == 0)
922	922	{
923		~~voo~~d~~oo_d~~evice voodoo = ~~(voodoo_device)~~machine().device("voodoo1");
	923	device_t *voodoo = machine().device("voodoo1");
924	924
925	925	// m_k001604_2->draw_back_layer(bitmap, cliprect);
926	926
927		voodoo~~->voodoo~~_update(bitmap, cliprect);
	927	voodoo_update(voodoo, bitmap, cliprect);
928	928
929	929	m_k001604_2->draw_front_layer(screen, bitmap, cliprect);
930	930	}

trunk/src/mame/drivers/hornet.cpp
r253151	r253152
478	478
479	479	UINT32 hornet_state::screen_update_hornet(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
480	480	{
481		~~voo~~d~~oo_d~~evice* voodoo = ~~(voodoo_device*)~~machine().device("voodoo0");
	481	device_t *voodoo = machine().device("voodoo0");
482	482
483		voodoo~~->voodoo~~_update(bitmap, cliprect);
	483	voodoo_update(voodoo, bitmap, cliprect);
484	484
485	485	m_k037122_1->tile_draw(screen, bitmap, cliprect);
486	486
r253151	r253152
493	493	{
494	494	if (strcmp(screen.tag(), ":lscreen") == 0)
495	495	{
496		voodoo_device voodoo = (voodoo_device)machine().device("voodoo0");
497		voodoo->voodoo_update(bitmap, cliprect);
	496	device_t *voodoo = machine().device("voodoo0");
	497	voodoo_update(voodoo, bitmap, cliprect);
498	498
499	499	/* TODO: tilemaps per screen */
500	500	m_k037122_1->tile_draw(screen, bitmap, cliprect);
501	501	}
502	502	else if (strcmp(screen.tag(), ":rscreen") == 0)
503	503	{
504		voodoo_device voodoo = (voodoo_device)machine().device("voodoo1");
505		voodoo->voodoo_update(bitmap, cliprect);
	504	device_t *voodoo = machine().device("voodoo1");
	505	voodoo_update(voodoo, bitmap, cliprect);
506	506
507	507	/* TODO: tilemaps per screen */
508	508	m_k037122_2->tile_draw(screen, bitmap, cliprect);

trunk/src/mame/drivers/kaneko16.cpp
r253151	r253152
3342	3342	/* Not present on this board */
3343	3343	ROM_END
3344	3344
3345		ROM_START( gtmrb )
3346		ROM_REGION( 0x100000, "maincpu", 0 ) /* 68000 Code */
3347		ROM_LOAD16_BYTE( "mmp0x1.u514", 0x000000, 0x080000, CRC(6c163f12) SHA1(7f33d1475dcb754c83f68b5fb686fb236ba81256) )
3348		ROM_LOAD16_BYTE( "mmp1x1.u513", 0x000001, 0x080000, CRC(424dc7e1) SHA1(a9cb8d1fd0549c8c77462552c649c180c30eef89) )
3349	3345
3350		ROM_REGION( 0x020000, "mcudata", 0 ) /* MCU Code */
3351		ROM_LOAD16_WORD_SWAP( "mmd0x1.u124", 0x000000, 0x020000, CRC(3d7cb329) SHA1(053106acde642a414fde0b01105fe6762b6a10f6) ) // == mmd0x2
3352
3353		ROM_REGION( 0x840000, "gfx1", 0 ) /* Sprites */
3354		ROM_LOAD( "mm-200-402-s0.bin", 0x000000, 0x200000, CRC(c0ab3efc) SHA1(e6cd15480977b036234d91e6f3a6e21b7f0a3c3e) )
3355		ROM_LOAD( "mm-201-403-s1.bin", 0x200000, 0x200000, CRC(cf6b23dc) SHA1(ccfd0b17507e091e55c169361cd6a6b19641b717) )
3356		ROM_LOAD( "mm-202-404-s2.bin", 0x400000, 0x200000, CRC(8f27f5d3) SHA1(219a86446ce2556682009d8aff837480f040a01e) )
3357		ROM_LOAD( "mm-203-405-s3.bin", 0x600000, 0x080000, CRC(e9747c8c) SHA1(2507102ec34755c6f110eadb3444e6d3a3474051) )
3358		ROM_LOAD16_BYTE( "mms1x1.u30", 0x800001, 0x020000, CRC(9463825c) SHA1(696bbfc816b564b3cff1487e1b848d375951f923) )
3359		ROM_LOAD16_BYTE( "mms0x1.u29", 0x800000, 0x020000, CRC(bd22b7d2) SHA1(ef82d00d72439590c71aed33ecfabc6ee71a6ff9) ) // == mms0x2
3360
3361		ROM_REGION( 0x200000, "gfx2", 0 ) /* Tiles (scrambled) */
3362		ROM_LOAD( "mm-300-406-a0.bin", 0x000000, 0x200000, CRC(b15f6b7f) SHA1(5e84919d788add53fc87f4d85f437df413b1dbc5) )
3363
3364		ROM_REGION( 0x200000, "gfx3", 0 ) /* Tiles (scrambled) */
3365		ROM_COPY("gfx2",0x000000,0,0x200000) // it isn't on the board twice.
3366
3367		ROM_REGION( 0x400000, "oki1", 0 ) /* Samples, plus room for expansion */
3368		ROM_LOAD( "mm-100-401-e0.bin", 0x000000, 0x100000, CRC(b9cbfbee) SHA1(051d48a68477ef9c29bd5cc0bb7955d513a0ab94) ) // 16 x $10000
3369
3370		ROM_REGION( 0x100000, "oki2", ROMREGION_ERASE00 ) /* Samples */
3371		/* Not present on this board */
3372		ROM_END
3373
3374
3375	3346	ROM_START( gtmro )
3376	3347	ROM_REGION( 0x100000, "maincpu", 0 ) /* 68000 Code */
3377	3348	ROM_LOAD16_BYTE( "u514.bin", 0x000000, 0x080000, CRC(2e857685) SHA1(43b6d88df51a3b4fb0cb910f63a5ec26b06e216a) )
r253151	r253152
4409	4380	GAME( 1994, bonkadv, 0, bonkadv , bonkadv, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "B.C. Kid / Bonk's Adventure / Kyukyoku!! PC Genjin", MACHINE_SUPPORTS_SAVE )
4410	4381	GAME( 1994, bloodwar, 0, bloodwar, bloodwar, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "Blood Warrior", MACHINE_SUPPORTS_SAVE )
4411	4382	GAME( 1994, oedfight, bloodwar, bloodwar, bloodwar, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "Oedo Fight (Japan Bloodshed Ver.)", MACHINE_SUPPORTS_SAVE )
4412		GAME( 1994, gtmr, 0, gtmr, gtmr, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "1000 Miglia: Great 1000 Miles Rally (94/07/18)", MACHINE_SUPPORTS_SAVE ) ~~// this set shows 'PCB by Jinwei Co Ltd. ROC'~~
	4383	GAME( 1994, gtmr, 0, gtmr, gtmr, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "1000 Miglia: Great 1000 Miles Rally (94/07/18)", MACHINE_SUPPORTS_SAVE )
4413	4384	GAME( 1994, gtmra, gtmr, gtmr, gtmr, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "1000 Miglia: Great 1000 Miles Rally (94/06/13)", MACHINE_SUPPORTS_SAVE )
4414		GAME( 1994, gtmrb, gtmr, gtmr, gtmr, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "1000 Miglia: Great 1000 Miles Rally (94/05/26)", MACHINE_SUPPORTS_SAVE )
4415	4385	GAME( 1994, gtmro, gtmr, gtmr, gtmr, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "1000 Miglia: Great 1000 Miles Rally (94/05/10)", MACHINE_SUPPORTS_SAVE ) // possible prototype
4416	4386	GAME( 1994, gtmre, gtmr, gtmre, gtmr, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "Great 1000 Miles Rally: Evolution Model!!! (94/09/06)", MACHINE_SUPPORTS_SAVE )
4417	4387	GAME( 1994, gtmrusa, gtmr, gtmre, gtmr, kaneko16_gtmr_state, gtmr, ROT0, "Kaneko", "Great 1000 Miles Rally: U.S.A Version! (94/09/06)", MACHINE_SUPPORTS_SAVE ) // U.S.A version seems part of the title, rather than region

trunk/src/mame/drivers/ladyfrog.cpp
r253151	r253152
365	365	ROM_LOAD( "8.ic10", 0x20000, 0x10000, CRC(fc6808bf) SHA1(f1f1b75a79dfdb500012f9b52c6364f0a13dce2d) )
366	366	ROM_END
367	367
368		ROM_START( touchemea )
369		ROM_REGION( 0x10000, "maincpu", 0 )
370		ROM_LOAD( "2.ic107", 0x0000, 0x10000, CRC(4e72312d) SHA1(a7d178608f05c87a53c650298b903bcf34b3b755) ) // sldh
371
372		ROM_REGION( 0x10000, "audiocpu", 0 )
373		ROM_LOAD( "1.ic115", 0x0000, 0x8000, CRC(902589aa) SHA1(d60088fc31a67fec91f908f671af77bb87a5e59c) )
374
375		ROM_REGION( 0x60000, "gfx1", ROMREGION_INVERT )
376		ROM_LOAD( "3.ic32", 0x30000, 0x10000, CRC(223b4435) SHA1(fb5a4096012093bae5fda213a5de317e63a88ec3) )
377		ROM_LOAD( "4.ic33", 0x40000, 0x10000, CRC(96dcc2f3) SHA1(9c61f8161771e40ca41b6e102bc04583dc97cd0d) )
378		ROM_LOAD( "5.ic34", 0x50000, 0x10000, CRC(b8667a6b) SHA1(288a5cbd8fc01b24822e89fbc1e6d7f45c181483) )
379		ROM_LOAD( "6.ic8", 0x00000, 0x10000, CRC(d257382f) SHA1(9c459b90c9ddfe90de4a252f29a7bee809412b46) )
380		ROM_LOAD( "7.ic9", 0x10000, 0x10000, CRC(feb1b974) SHA1(ffd4527472cdf655fbebebf4d3abb61962e54457) )
381		ROM_LOAD( "8.ic10", 0x20000, 0x10000, CRC(fc6808bf) SHA1(f1f1b75a79dfdb500012f9b52c6364f0a13dce2d) )
382		ROM_END
383
384	368	GAME( 1990, ladyfrog, 0, ladyfrog, ladyfrog, driver_device, 0, ORIENTATION_SWAP_XY, "Mondial Games", "Lady Frog", MACHINE_SUPPORTS_SAVE )
385	369
386	370	// toucheme art style is similar to ladyfrog, so it's probably the same manufacturer
387		GAME( 19??, toucheme, 0, toucheme, toucheme, driver_device, 0, ORIENTATION_SWAP_XY, "<unknown>", "Touche Me (set 1)", MACHINE_SUPPORTS_SAVE )
388		GAME( 19??, touchemea,toucheme, toucheme, toucheme, driver_device, 0, ORIENTATION_SWAP_XY, "<unknown>", "Touche Me (set 2, harder)", MACHINE_SUPPORTS_SAVE )
	371	GAME( 19??, toucheme, 0, toucheme, toucheme, driver_device, 0, ORIENTATION_SWAP_XY, "<unknown>", "Touche Me", MACHINE_SUPPORTS_SAVE )

trunk/src/mame/drivers/magictg.cpp
r253151	r253152
180	180
181	181
182	182	/* 3Dfx Voodoo */
183		~~voo~~d~~oo_d~~evice* m_voodoo[2];
	183	device_t* m_voodoo[2];
184	184
185	185	struct
186	186	{
r253151	r253152
241	241
242	242	void magictg_state::machine_start()
243	243	{
244		m_voodoo[0] = (voodoo_device*)machine().device("voodoo_0");
245		m_voodoo[1] = (voodoo_device*)machine().device("voodoo_1");
	244	m_voodoo[0] = machine().device("voodoo_0");
	245	m_voodoo[1] = machine().device("voodoo_1");
246	246	}
247	247
248	248
r253151	r253152
278	278
279	279	UINT32 magictg_state::screen_update_magictg(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
280	280	{
281		return m_voodoo~~[0]->voodoo~~_update(bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
	281	return voodoo_update(m_voodoo[0], bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
282	282	}
283	283
284	284
r253151	r253152
338	338	break;
339	339	case 0x40:
340	340	state->m_voodoo_pci_regs[0].init_enable = data;
341		~~state->m_~~voodoo~~[0]->voodoo~~_set_init_enable(data);
	341	voodoo_set_init_enable(state->m_voodoo[0], data);
342	342	break;
343	343
344	344	default:
r253151	r253152
601	601	UINT32 dst_addr = m_dma_ch[ch].dst_addr;
602	602	//device_t *voodoo = dst_addr > 0xa000000 voodoo0 : voodoo1;
603	603
604		assert((src_addr & 3) == 0);
605		assert((dst_addr & 3) == 0);
	604	assert(DWORD_ALIGNED(src_addr));
	605	assert(DWORD_ALIGNED(dst_addr));
606	606
607	607	while (m_dma_ch[ch].count > 3)
608	608	{

trunk/src/mame/drivers/nibble.cpp
r253151	r253152
2	2	// copyright-holders:Roberto Fresca
3	3	/*************************************************************************
4	4
5		Lucky 9, Nibble.
	5	Unknown 'Nibble' game
	6
	7	Preliminary driver by Roberto Fresca.
6	8
7		Driver by Roberto Fresca.
8
9		Seems some sort of gambling game with playing cards (no poker)
10		and girls graphics...
11
12
13	9	**************************************************************************
14	10
15	11	Specs:
16	12
17		1x UM6845 (U67).
18		1x AY38910A/p (U75).
	13	1x UM6845
	14	1x AY38910A/p
19	15
20		3x HY6264P-12 (U153, U154, U25).
21		2x IMSG171P-50G (U32, U104).
	16	3x HY6264P-12
	17	2x IMSG171P-50G
22	18
23	19	2 Chips with no markings!
24	20
25		8x 64K Graphics ROMs (U139, U141, U149, U147, U137, U143, U145, U152).
26		1x 64K Program ROM (U123).
27		1x 128K unknown ROM (U138).
	21	8x 64K Graphics ROMs.
	22	1x 64K Program ROM.
	23	1x 128K unknown ROM.
28	24
29		1x TI LF347N (U158) Operational Amplifier.
30		1x LM380N (U82) 2.5W Audio Power Amplifier.
31
32	25	2x XTAL - 11.98135 KDS9C
33	26	2x 8 DIP switches banks.
34		1x 3.6V lithium battery.
35	27
36	28
37	29	**************************************************************************
r253151	r253152
39	31	Tech notes...
40	32
41	33	About the unknown ICs:
42		DIP64 (U101) CPU with Xtal tied to pins 30 % 31. --> TMS9900? (ROM 9)
43		DIP40 (U64) CPU or sound IC driving 128k (ROM 10) data? (pin 20 tied to GND)
	34	DIP64 CPU with Xtal tied to pins 30 % 31. --> TMS9900? (ROM 9)
	35	DIP40 CPU or sound IC driving 128k (ROM 10) data? (pin 20 tied to GND)
44	36
45	37
46	38	*************************************************************************/
47	39
48
49	40	#define MASTER_CLOCK XTAL_12MHz
50	41
51	42	#include "emu.h"
52		#include "cpu/tms9900/tms9980a.h"
53		//#include "cpu/tms9900/tms9900.h"
54	43	#include "sound/ay8910.h"
55	44	#include "video/mc6845.h"
56	45
r253151	r253152
59	48	{
60	49	public:
61	50	nibble_state(const machine_config &mconfig, device_type type, const char *tag)
62		: driver_device(mconfig, type, tag),
63		m_videoram(*this, "videoram"),
64		m_maincpu(*this, "maincpu"),
65		m_gfxdecode(*this, "gfxdecode") { }
	51	: driver_device(mconfig, type, tag)
	52	// ,m_maincpu(*this, "maincpu")
	53	{ }
66	54
67		required_shared_ptr<UINT8> m_videoram;
68		tilemap_t *m_bg_tilemap;
69		DECLARE_WRITE8_MEMBER(nibble_videoram_w);
70		TILE_GET_INFO_MEMBER(get_bg_tile_info);
71
72	55	virtual void machine_start() override;
73	56	virtual void machine_reset() override;
74		virtual void video_start() override;
75		DECLARE_PALETTE_INIT(nibble);
76		UINT32 screen_update_nibble(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
77		INTERRUPT_GEN_MEMBER(nibble_interrupt);
78		required_device<cpu_device> m_maincpu;
79		required_device<gfxdecode_device> m_gfxdecode;
80		};
81	57
	58	// required_device<cpu_device> m_maincpu;
82	59
83		/*************************
84		* Video Hardware *
85		*************************/
	60	};
86	61
87		WRITE8_MEMBER(nibble_state::nibble_videoram_w)
88		{
89		m_videoram[offset] = data;
90		m_bg_tilemap->mark_tile_dirty(offset);
91		}
	62	static INPUT_PORTS_START( nibble )
	63	INPUT_PORTS_END
92	64
93	65
94		TILE_GET_INFO_MEMBER(nibble_state::get_bg_tile_info)
95		{
96		/* - bits -
97		7654 3210
98		---- ---- bank select.
99		---- ---- color code.
100		---- ---- seems unused.
101		*/
102		int code = m_videoram[tile_index];
103
104		SET_TILE_INFO_MEMBER(0 /* bank /, code, 0 / color */, 0);
105		}
106
107		void nibble_state::video_start()
108		{
109		m_bg_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(nibble_state::get_bg_tile_info),this), TILEMAP_SCAN_ROWS, 8, 8, 32, 32);
110		}
111
112		UINT32 nibble_state::screen_update_nibble(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
113		{
114		m_bg_tilemap->draw(screen, bitmap, cliprect, 0, 0);
115		return 0;
116		}
117
118		PALETTE_INIT_MEMBER(nibble_state, nibble)
119		{
120		}
121
122
123		/**************************
124		* Read / Write Handlers *
125		**************************/
126
127		INTERRUPT_GEN_MEMBER(nibble_state::nibble_interrupt)
128		{
129		}
130
131
132		/************************
133		* Start & Reset *
134		************************/
135
136	66	void nibble_state::machine_start()
137	67	{
138	68	}
139	69
140
141	70	void nibble_state::machine_reset()
142	71	{
143	72	}
144	73
145	74
146		/*************************
147		* Memory Map Information *
148		*************************/
149
150		static ADDRESS_MAP_START( nibble_map, AS_PROGRAM, 8, nibble_state )
151		ADDRESS_MAP_GLOBAL_MASK(0x3fff)
152		AM_RANGE(0x0000, 0xbfff) AM_ROM
153		AM_RANGE(0xc000, 0xc3ff) AM_WRITE(nibble_videoram_w) AM_SHARE("videoram") // placeholder
154		// AM_RANGE(0xff00, 0xff01) AM_DEVWRITE("crtc", mc6845_device, address_w)
155		// AM_RANGE(0xff02, 0xff03) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
156		ADDRESS_MAP_END
157
158
159		static ADDRESS_MAP_START( nibble_cru_map, AS_IO, 8, nibble_state )
160		ADDRESS_MAP_END
161
162
163		/*************************
164		* Input Ports *
165		*************************/
166
167		static INPUT_PORTS_START( nibble )
168		PORT_START("IN0")
169		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_1) PORT_NAME("IN0-1")
170		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_2) PORT_NAME("IN0-2")
171		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_3) PORT_NAME("IN0-3")
172		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_4) PORT_NAME("IN0-4")
173		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_5) PORT_NAME("IN0-5")
174		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_6) PORT_NAME("IN0-6")
175		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_7) PORT_NAME("IN0-7")
176		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_8) PORT_NAME("IN0-8")
177
178		PORT_START("IN1")
179		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Q) PORT_NAME("IN1-1")
180		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_W) PORT_NAME("IN1-2")
181		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_E) PORT_NAME("IN1-3")
182		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_R) PORT_NAME("IN1-4")
183		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_T) PORT_NAME("IN1-5")
184		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Y) PORT_NAME("IN1-6")
185		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_U) PORT_NAME("IN1-7")
186		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_I) PORT_NAME("IN1-8")
187
188		PORT_START("IN2")
189		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_A) PORT_NAME("IN2-1")
190		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_S) PORT_NAME("IN2-2")
191		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_D) PORT_NAME("IN2-3")
192		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_F) PORT_NAME("IN2-4")
193		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_G) PORT_NAME("IN2-5")
194		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_H) PORT_NAME("IN2-6")
195		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_J) PORT_NAME("IN2-7")
196		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_K) PORT_NAME("IN2-8")
197
198		PORT_START("IN3")
199		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Z) PORT_NAME("IN3-1")
200		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_X) PORT_NAME("IN3-2")
201		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_C) PORT_NAME("IN3-3")
202		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_V) PORT_NAME("IN3-4")
203		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_B) PORT_NAME("IN3-5")
204		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_N) PORT_NAME("IN3-6")
205		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_M) PORT_NAME("IN3-7")
206		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_L) PORT_NAME("IN3-8")
207
208		PORT_START("IN4")
209		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_1_PAD) PORT_NAME("IN4-1")
210		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_2_PAD) PORT_NAME("IN4-2")
211		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_3_PAD) PORT_NAME("IN4-3")
212		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_4_PAD) PORT_NAME("IN4-4")
213		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_5_PAD) PORT_NAME("IN4-5")
214		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("IN4-6")
215		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("IN4-7")
216		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("IN4-8")
217
218		PORT_START("DSW1")
219		PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
220		PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
221		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
222		PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
223		PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
224		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
225		PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
226		PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
227		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
228		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
229		PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
230		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
231		PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
232		PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
233		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
234		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
235		PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
236		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
237		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
238		PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
239		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
240		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
241		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
242		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
243
244		PORT_START("DSW2")
245		PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
246		PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
247		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
248		PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
249		PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
250		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
251		PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
252		PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
253		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
254		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
255		PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
256		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
257		PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
258		PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
259		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
260		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
261		PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
262		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
263		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
264		PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
265		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
266		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
267		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
268		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
269
270		INPUT_PORTS_END
271
272
273		/*************************
274		* Graphics Layouts *
275		*************************/
276
277		static const gfx_layout charlayout =
278		{
279		8,8,
280		RGN_FRAC(1,8),
281		8,
282		{ RGN_FRAC(0,8), RGN_FRAC(1,8), RGN_FRAC(2,8), RGN_FRAC(3,8), RGN_FRAC(4,8), RGN_FRAC(5,8), RGN_FRAC(6,8), RGN_FRAC(7,8) },
283		{ 0, 1, 2, 3, 4, 5, 6, 7 },
284		{ 08, 18, 28, 38, 48, 58, 68, 78 },
285		8*8
286		};
287
288
289		/******************************
290		* Graphics Decode Information *
291		******************************/
292
293		static GFXDECODE_START( nibble )
294		GFXDECODE_ENTRY( "gfx", 0, charlayout, 0, 16 )
295		GFXDECODE_END
296
297
298		/*************************
299		* Machine Drivers *
300		*************************/
301
302	75	static MACHINE_CONFIG_START( nibble, nibble_state )
303	76
304		// CPU should be switched to TMS9900
305		MCFG_TMS99xx_ADD("maincpu", TMS9980A, MASTER_CLOCK/4, nibble_map, nibble_cru_map)
306		MCFG_CPU_VBLANK_INT_DRIVER("screen", nibble_state, nibble_interrupt)
	77	/* basic machine hardware */
	78	// MCFG_CPU_ADD("maincpu", ??, 3000000) // unknown DIP64 CPU
	79	// MCFG_CPU_PROGRAM_MAP(nibble_map)
	80	// MCFG_CPU_IO_MAP(nibble_io)
	81	// MCFG_CPU_VBLANK_INT_DRIVER("screen", nibble_state, irq0_line_hold)
307	82
308		/* video hardware */
309		MCFG_SCREEN_ADD("screen", RASTER)
310		MCFG_SCREEN_REFRESH_RATE(60)
311		MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
312		MCFG_SCREEN_SIZE(328, 328)
313		MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 08, 328-1)
314		MCFG_SCREEN_UPDATE_DRIVER(nibble_state, screen_update_nibble)
315		MCFG_SCREEN_PALETTE("palette")
	83	/* sound hardware */
	84	// MCFG_SPEAKER_STANDARD_MONO("mono")
316	85
317		MCFG_GFXDECODE_ADD("gfxdecode", "palette", nibble)
318
319		MCFG_PALETTE_ADD("palette", 256)
320		MCFG_PALETTE_INIT_OWNER(nibble_state, nibble)
321
322		MCFG_MC6845_ADD("crtc", MC6845, "screen", MASTER_CLOCK/8) /* guess */
323		MCFG_MC6845_SHOW_BORDER_AREA(false)
324		MCFG_MC6845_CHAR_WIDTH(8)
325
	86	// MCFG_SOUND_ADD("aysnd", AY8910, MASTER_CLOCK/8)
	87	// MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
326	88	MACHINE_CONFIG_END
327	89
328	90
329		/*************************
330		* Rom Load *
331		*************************/
332
333	91	ROM_START( l9nibble )
334	92	ROM_REGION( 0x10000, "maincpu", 0 )
335		ROM_LOAD( "09.U123", 0x00000, 0x10000, CRC(dfef685d) SHA1(0aeb4257e408e8549df629a0cdb5f2b6790e32de) ) // ~~tms9900 c~~o~~de?~~
	93	ROM_LOAD( "09.U123", 0x00000, 0x10000, CRC(dfef685d) SHA1(0aeb4257e408e8549df629a0cdb5f2b6790e32de) ) // unknown
336	94
337		ROM_REGION( 0x80000, "gfx", 0 )
338		ROM_LOAD( "01.u139", 0x00000, 0x10000, CRC(aba06e58) SHA1(5841beec122613eed2ba9f48cb1d51bfa0ff450c) )
339		ROM_LOAD( "02.u141", 0x10000, 0x10000, CRC(a1e5d6d1) SHA1(8ec85b0544dd75bcb13600bae503ad2b20978281) )
340		ROM_LOAD( "03.u149", 0x20000, 0x10000, CRC(ae66f77c) SHA1(6c9e98cc00b72252cb238f14686c0faef47134df) )
341		ROM_LOAD( "04.u147", 0x30000, 0x10000, CRC(f1864094) SHA1(b439f9e8c2cc4575f9edbda45b9e724257015a73) )
342		ROM_LOAD( "05.u137", 0x40000, 0x10000, CRC(2e8ae9de) SHA1(5f2831f71b351e34df82af37041c9aa815eb372c) )
343		ROM_LOAD( "06.u143", 0x50000, 0x10000, CRC(8a56f324) SHA1(68790a12ca57c999bd7b7f26adc206aab3c06976) )
344		ROM_LOAD( "07.u145", 0x60000, 0x10000, CRC(4f757912) SHA1(63e5fc2672552463060680b7a5a94df45f3d4b68) )
345		ROM_LOAD( "08.u152", 0x70000, 0x10000, CRC(4f878ee4) SHA1(215f3ead0c358cc09c21515981cbb0a1e58c2ca6) )
	95	ROM_REGION( 0x80000, "oki", 0 )
	96	ROM_LOAD( "01.U139", 0x00000, 0x10000, CRC(aba06e58) SHA1(5841beec122613eed2ba9f48cb1d51bfa0ff450c) )
	97	ROM_LOAD( "02.U141", 0x00000, 0x10000, CRC(a1e5d6d1) SHA1(8ec85b0544dd75bcb13600bae503ad2b20978281) )
	98	ROM_LOAD( "03.U149", 0x00000, 0x10000, CRC(ae66f77c) SHA1(6c9e98cc00b72252cb238f14686c0faef47134df) )
	99	ROM_LOAD( "04.U147", 0x00000, 0x10000, CRC(f1864094) SHA1(b439f9e8c2cc4575f9edbda45b9e724257015a73) )
	100	ROM_LOAD( "05.U137", 0x00000, 0x10000, CRC(2e8ae9de) SHA1(5f2831f71b351e34df82af37041c9aa815eb372c) )
	101	ROM_LOAD( "06.U143", 0x00000, 0x10000, CRC(8a56f324) SHA1(68790a12ca57c999bd7b7f26adc206aab3c06976) )
	102	ROM_LOAD( "07.U145", 0x00000, 0x10000, CRC(4f757912) SHA1(63e5fc2672552463060680b7a5a94df45f3d4b68) )
	103	ROM_LOAD( "08.U152", 0x00000, 0x10000, CRC(4f878ee4) SHA1(215f3ead0c358cc09c21515981cbb0a1e58c2ca6) )
346	104
347	105	ROM_REGION( 0x20000, "user", 0 )
348		ROM_LOAD( "10.u138", 0x00000, 0x20000, CRC(ed831d2a) SHA1(ce5c3b24979d220215d7f0e8d50f45550aec15bd) ) ~~// unknown data...~~
	106	ROM_LOAD( "10.U138", 0x00000, 0x20000, CRC(ed831d2a) SHA1(ce5c3b24979d220215d7f0e8d50f45550aec15bd) )
349	107
350		ROM_REGION( 0x0400, "plds", 0 )
351		ROM_LOAD( "pal16l8acn.u23", 0x0000, 0x0104, NO_DUMP )
352		ROM_LOAD( "pal16l8acn.uxx", 0x0200, 0x0104, NO_DUMP )
353
354	108	ROM_END
355	109
356	110
357		/*************************
358		* Game Drivers *
359		*************************/
360
361		/* YEAR NAME PARENT MACHINE INPUT STATE INIT ROT COMPANY FULLNAME FLAGS... */
362		GAME( 19??, l9nibble, 0, nibble, nibble, driver_device, 0, ROT0, "Nibble", "Lucky 9", MACHINE_NO_SOUND \| MACHINE_NOT_WORKING )
	111	/* YEAR NAME PARENT MACHINE INPUT STATE INIT ROT COMPANY FULLNAME FLAGS... */
	112	GAME( 19??, l9nibble, 0, nibble, nibble, driver_device, 0, ROT0, "Nibble?", "Unknown Nibble game", MACHINE_IS_SKELETON )

trunk/src/mame/drivers/nwk-tr.cpp
r253151	r253152
304	304	int m_fpga_uploaded;
305	305	int m_lanc2_ram_r;
306	306	int m_lanc2_ram_w;
307		UINT8 m_lanc2_reg[3];
308	307	std::unique_ptr<UINT8[]> m_lanc2_ram;
309	308	std::unique_ptr<UINT32[]> m_sharc_dataram;
310	309	DECLARE_WRITE32_MEMBER(paletteram32_w);
r253151	r253152
347	346
348	347	UINT32 nwktr_state::screen_update_nwktr(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
349	348	{
350		~~voo~~d~~oo_d~~evice voodoo = ~~(voodoo_device)~~machine().device("voodoo0");
	349	device_t *voodoo = machine().device("voodoo0");
351	350
352	351	bitmap.fill(m_palette->pen(0), cliprect);
353	352
354		voodoo~~->voodoo~~_update(bitmap, cliprect);
	353	voodoo_update(voodoo, bitmap, cliprect);
355	354
356	355	const rectangle &visarea = screen.visible_area();
357	356	const rectangle tilemap_rect(visarea.min_x, visarea.max_x, visarea.min_y+16, visarea.max_y);
r253151	r253152
522	521	((value << 7) & 0x80);
523	522
524	523	m_fpga_uploaded = 1;
525		m_lanc2_reg[0] = (UINT8)(data >> 24);
526	524
527	525	//printf("lanc2_fpga_w: %02X at %08X\n", value, space.device().safe_pc());
528	526	}
r253151	r253152
530	528	{
531	529	m_lanc2_ram_r = 0;
532	530	m_lanc2_ram_w = 0;
533		m_lanc2_reg[1] = (UINT8)(data >> 8);
534	531	}
535	532	else if (ACCESSING_BITS_16_23)
536	533	{
537		if (m_lanc2_reg[0] != 0)
538		{
539		m_lanc2_ram[2] = (data >> 20) & 0xf;
540		m_lanc2_ram[3] = 0;
541		}
542		m_lanc2_reg[2] = (UINT8)(data >> 16);
	534	m_lanc2_ram[2] = (data >> 20) & 0xf;
	535	m_lanc2_ram[3] = 0;
543	536	}
544	537	else if (ACCESSING_BITS_0_7)
545	538	{

trunk/src/mame/drivers/overdriv.cpp
r253151	r253152
82	82	{
83	83	// m_screen->frame_number() & 1
84	84	m_maincpu->set_input_line(4, HOLD_LINE);
	85	m_subcpu->set_input_line(4, HOLD_LINE); // likely wrong
85	86	}
86	87	else if(m_fake_timer >= timer_threshold) // timer irq
87	88	{
r253151	r253152
90	91	}
91	92	}
92	93
93		#ifdef UNUSED_FUNCTION
94	94	INTERRUPT_GEN_MEMBER(overdriv_state::cpuB_interrupt)
95	95	{
96	96	// this doesn't get turned on until the irq has happened? wrong irq?
	97	if (m_k053246->k053246_is_irq_enabled())
	98	m_subcpu->set_input_line(6, HOLD_LINE); // likely wrong
97	99	}
98		#endif
99	100
	101
100	102	WRITE16_MEMBER(overdriv_state::cpuA_ctrl_w)
101	103	{
102	104	if (ACCESSING_BITS_0_7)
r253151	r253152
140	142	}
141	143
142	144
143
144
145		WRITE16_MEMBER(overdriv_state::slave_irq4_assert_w)
	145	WRITE16_MEMBER(overdriv_state::overdriv_cpuB_irq_x_w)
146	146	{
147		// used in-game
148		m_subcpu->set_input_line(4, HOLD_LINE);
	147	m_subcpu->set_input_line(5, HOLD_LINE); // likely wrong
149	148	}
150	149
151		WRITE16_MEMBER(overdriv_state::~~sla~~ve_irq5_~~assert~~_w)
	150	WRITE16_MEMBER(overdriv_state::overdriv_cpuB_irq_y_w)
152	151	{
153		// tests GFX ROMs with this irq (indeed enabled only in test mode)
154		m_subcpu->set_input_line(5, HOLD_LINE);
155	152	}
156	153
157	154	static ADDRESS_MAP_START( overdriv_master_map, AS_PROGRAM, 16, overdriv_state )
r253151	r253152
177	174	AM_RANGE(0x218000, 0x218fff) AM_DEVREADWRITE8("k051316_2", k051316_device, read, write, 0xff00)
178	175	AM_RANGE(0x220000, 0x220fff) AM_DEVREAD8("k051316_1", k051316_device, rom_r, 0xff00)
179	176	AM_RANGE(0x228000, 0x228fff) AM_DEVREAD8("k051316_2", k051316_device, rom_r, 0xff00)
180		AM_RANGE(0x230000, 0x230001) AM_WRITE(slave_irq4_assert_w)
181		AM_RANGE(0x238000, 0x238001) AM_WRITE(slave_irq5_assert_w)
	177	AM_RANGE(0x230000, 0x230001) AM_WRITE(overdriv_cpuB_irq_y_w)
	178	AM_RANGE(0x238000, 0x238001) AM_WRITE(overdriv_cpuB_irq_x_w)
182	179	ADDRESS_MAP_END
183	180
184	181	#ifdef UNUSED_FUNCTION
r253151	r253152
206	203	}
207	204	#endif
208	205
209		TIMER_CALLBACK_MEMBER(overdriv_state::objdma_end_cb )
210		{
211		m_subcpu->set_input_line(6, HOLD_LINE);
212		}
213
214		WRITE16_MEMBER(overdriv_state::objdma_w)
215		{
216		if(data & 0x10)
217		machine().scheduler().timer_set(attotime::from_usec(100), timer_expired_delegate(FUNC(overdriv_state::objdma_end_cb), this));
218
219		m_k053246->k053246_w(space,5,data,mem_mask);
220		}
221
222	206	static ADDRESS_MAP_START( overdriv_slave_map, AS_PROGRAM, 16, overdriv_state )
223	207	AM_RANGE(0x000000, 0x03ffff) AM_ROM
224	208	AM_RANGE(0x080000, 0x083fff) AM_RAM /* work RAM */
r253151	r253152
228	212	AM_RANGE(0x118000, 0x118fff) AM_DEVREADWRITE("k053246", k053247_device, k053247_word_r, k053247_word_w) // data gets copied to sprite chip with DMA..
229	213	AM_RANGE(0x120000, 0x120001) AM_DEVREAD("k053246", k053247_device, k053246_word_r)
230	214	AM_RANGE(0x128000, 0x128001) AM_READWRITE(cpuB_ctrl_r, cpuB_ctrl_w) /* enable K053247 ROM reading, plus something else */
231		AM_RANGE(0x130004, 0x130005) AM_WRITE(objdma_w)
232	215	AM_RANGE(0x130000, 0x130007) AM_DEVREADWRITE8("k053246", k053247_device, k053246_r,k053246_w,0xffff)
233		//AM_RANGE(0x140000, 0x140001) used in later stages~~, set after writes at 0x208000-0x20bfff range~~
	216	//AM_RANGE(0x140000, 0x140001) used in later stages
234	217	AM_RANGE(0x200000, 0x203fff) AM_RAM AM_SHARE("share1")
235		AM_RANGE(0x208000, 0x20bfff) AM_RAM ~~// sprite indirect table?~~
	218	AM_RANGE(0x208000, 0x20bfff) AM_RAM
236	219	AM_RANGE(0x218000, 0x219fff) AM_DEVREAD("k053250_1", k053250_device, rom_r)
237	220	AM_RANGE(0x220000, 0x221fff) AM_DEVREAD("k053250_2", k053250_device, rom_r)
238	221	ADDRESS_MAP_END
r253151	r253152
320	303
321	304	MCFG_CPU_ADD("sub", M68000, XTAL_24MHz/2) /* 12 MHz */
322	305	MCFG_CPU_PROGRAM_MAP(overdriv_slave_map)
323		//MCFG_CPU_VBLANK_INT_DRIVER("screen", overdriv_state, cpuB_interrupt)
324		/* IRQ 5 and 6 are generated by the main CPU. */
325		/* IRQ 5 is used only in test mode, to request the checksums of the gfx ROMs. */
	306	MCFG_CPU_VBLANK_INT_DRIVER("screen", overdriv_state, cpuB_interrupt) /* IRQ 5 and 6 are generated by the main CPU. */
	307	/* IRQ 5 is used only in test mode, to request the checksums of the gfx ROMs. */
326	308
327	309	MCFG_CPU_ADD("audiocpu", M6809, XTAL_3_579545MHz) /* 1.789 MHz?? This might be the right speed, but ROM testing */
328	310	MCFG_CPU_PROGRAM_MAP(overdriv_sound_map) /* takes a little too much (the counter wraps from 0000 to 9999). */

trunk/src/mame/drivers/pc9801.cpp
r253151	r253152
425	425	#include "machine/pc9801_118.h"
426	426	#include "machine/pc9801_cbus.h"
427	427	#include "machine/pc9801_kbd.h"
428		#include "machine/pc9801_cd.h"
429	428
430	429	#include "machine/idectrl.h"
431	430	#include "machine/idehd.h"
r253151	r253152
3219	3218	}
3220	3219	}
3221	3220
3222		SLOT_INTERFACE_START(pc9801_atapi_devices)
3223		SLOT_INTERFACE("pc9801_cd", PC9801_CD)
3224		SLOT_INTERFACE_END
3225
3226	3221	static MACHINE_CONFIG_FRAGMENT( pc9801_keyboard )
3227	3222	MCFG_DEVICE_ADD("keyb", PC9801_KBD, 53)
3228	3223	MCFG_PC9801_KBD_IRQ_CALLBACK(DEVWRITELINE("pic8259_master", pic8259_device, ir1_w))
r253151	r253152
3271	3266	static MACHINE_CONFIG_FRAGMENT( pc9801_ide )
3272	3267	MCFG_ATA_INTERFACE_ADD("ide1", ata_devices, "hdd", nullptr, false)
3273	3268	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(pc9801_state, ide1_irq_w))
3274		MCFG_ATA_INTERFACE_ADD("ide2", ~~pc9801_~~atapi_devices, "pc~~9801_c~~d", nullptr, false)
	3269	MCFG_ATA_INTERFACE_ADD("ide2", ata_devices, "cdrom", nullptr, false)
3275	3270	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(pc9801_state, ide2_irq_w))
3276	3271	MACHINE_CONFIG_END
3277	3272

trunk/src/mame/drivers/r9751.cpp
r253151	r253152
67	67
68	68	DECLARE_READ32_MEMBER(r9751_mmio_5ff_r);
69	69	DECLARE_WRITE32_MEMBER(r9751_mmio_5ff_w);
	70	DECLARE_READ32_MEMBER(r9751_mmio_ff01_r);
	71	DECLARE_WRITE32_MEMBER(r9751_mmio_ff01_w);
70	72	DECLARE_READ32_MEMBER(r9751_mmio_ff05_r);
71	73	DECLARE_WRITE32_MEMBER(r9751_mmio_ff05_w);
72	74	DECLARE_READ32_MEMBER(r9751_mmio_fff8_r);
r253151	r253152
90	92	UINT32 fdd_dest_address; // 5FF080B0
91	93	UINT32 fdd_cmd_complete;
92	94	UINT32 smioc_out_addr;
	95	UINT32 smioc_dma_bank;
	96	UINT32 fdd_dma_bank;
93	97	attotime timer_32khz_last;
94	98	// End registers
95	99
r253151	r253152
110	114
111	115	READ8_MEMBER(r9751_state::pdc_dma_r)
112	116	{
113		return m_maincpu->space(AS_PROGRAM).read_byte(offset);
	117	/* This callback function takes the value written to 0xFF01000C as the bank offset */
	118	UINT32 address = (fdd_dma_bank & 0x7FFFF800) + (offset&0xFFFF);
	119	return m_maincpu->space(AS_PROGRAM).read_byte(address);
114	120	}
115	121
116	122	WRITE8_MEMBER(r9751_state::pdc_dma_w)
117	123	{
118		m_maincpu->space(AS_PROGRAM).write_byte(m_pdc->fdd_68k_dma_address,data);
	124	/* This callback function takes the value written to 0xFF01000C as the bank offset */
	125	UINT32 address = (fdd_dma_bank & 0x7FFFF800) + (data&0xFFFF);
	126	m_maincpu->space(AS_PROGRAM).write_byte(m_pdc->fdd_68k_dma_address,address);
119	127	}
120	128
121	129	DRIVER_INIT_MEMBER(r9751_state,r9751)
r253151	r253152
123	131	reg_ff050004 = 0;
124	132	reg_fff80040 = 0;
125	133	fdd_dest_address = 0;
126		// fdd_scsi_command = 0;
127	134	fdd_cmd_complete = 0;
	135	fdd_dma_bank = 0;
128	136	smioc_out_addr = 0;
	137	smioc_dma_bank = 0;
129	138	m_mem = &m_maincpu->space(AS_PROGRAM);
130	139
131	140	}
r253151	r253152
199	208	switch(data)
200	209	{
201	210	case 0x4100: /* Send byte to serial */
202		if(TRACE_SMIOC) logerror("Serial byte: %02X\n", m_mem->read_dword(smioc_out_addr));
	211	if(TRACE_SMIOC) logerror("Serial byte: %02X PC: %08X\n", m_mem->read_dword(smioc_out_addr), space.machine().firstcpu->pc());
203	212	m_terminal->write(space,0,m_mem->read_dword(smioc_out_addr));
204	213	break;
205	214	default:
r253151	r253152
207	216	}
208	217	break;
209	218	case 0x5FF0C098: /* Serial DMA output address */
210		smioc_out_addr = data * 2;
	219	//smioc_out_addr = data * 2;
	220	smioc_out_addr = (smioc_dma_bank & 0x7FFFF800) \| ((data&0x3FF)<<1);
	221	if(TRACE_SMIOC) logerror("Serial output address: %08X PC: %08X\n", smioc_out_addr, space.machine().firstcpu->pc());
211	222	break;
212	223	/* PDC FDD region (0xB0, device 44 */
213	224	case 0x5FF001B0: /* FDD SCSI read command */
r253151	r253152
216	227	case 0x5FF002B0: /* FDD SCSI read command */
217	228	if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
218	229	break;
	230	case 0x5FF004B0: /* FDD RESET PDC */
	231	if(TRACE_FDC) logerror("PDC RESET, PC: %08X\n", space.machine().firstcpu->pc());
	232	m_pdc->reset();
	233	break;
219	234	case 0x5FF008B0: /* FDD SCSI read command */
220	235	if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
221	236	break;
222	237	case 0x5FF041B0: /* Unknown - Probably old style commands */
223	238	if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
224	239
225		/* Clear FDD Command completion status 0x5FF030B0 (PDC 0x4, 0x5)*/
	240	/* Clear FDD Command completion status 0x5FF030B0 (PDC 0x4, 0x5) */
226	241	m_pdc->reg_p4 = 0;
227	242	m_pdc->reg_p5 = 0;
228	243
r253151	r253152
248	263	unsigned char c_fdd_scsi_command[8]; // Array for SCSI command
249	264	int scsi_lba; // FDD LBA location here, extracted from command
250	265
251		/* Clear FDD Command completion status 0x5FF030B0 (PDC 0x4, 0x5)*/
	266	/* Clear FDD Command completion status 0x5FF030B0 (PDC 0x4, 0x5) */
252	267	m_pdc->reg_p4 = 0;
253	268	m_pdc->reg_p5 = 0;
254	269
r253151	r253152
286	301	}
287	302
288	303	/******************************************************************************
289		CPU board registers [0xFF050000 - 0xFF06FFFF]
	304	CPU board registers [0xFF010000 - 0xFF06FFFF]
290	305	******************************************************************************/
	306	READ32_MEMBER( r9751_state::r9751_mmio_ff01_r )
	307	{
	308	//UINT32 data;
	309	UINT32 address = offset * 4 + 0xFF010000;
	310
	311	switch(address)
	312	{
	313	default:
	314	//return data;
	315	return 0;
	316	}
	317	}
	318
	319	WRITE32_MEMBER( r9751_state::r9751_mmio_ff01_w )
	320	{
	321	UINT32 address = offset * 4 + 0xFF010000;
	322
	323	switch(address)
	324	{
	325	case 0xFF01000C: /* FDD DMA Offset */
	326	fdd_dma_bank = data;
	327	return;
	328	case 0xFF010010: /* SMIOC DMA Offset */
	329	smioc_dma_bank = data;
	330	return;
	331	default:
	332	return;
	333	}
	334	}
	335
291	336	READ32_MEMBER( r9751_state::r9751_mmio_ff05_r )
292	337	{
293	338	UINT32 data;
294		UINT32 address = offset * 4 + 0xFF050000;
	339	UINT32 address = offset * 4 + 0xFF050000;
295	340
296	341	switch(address)
297	342	{
r253151	r253152
373	418	AM_RANGE(0x00000000,0x00ffffff) AM_RAM AM_SHARE("main_ram") // 16MB
374	419	AM_RANGE(0x08000000,0x0800ffff) AM_ROM AM_REGION("prom", 0)
375	420	AM_RANGE(0x5FF00000,0x5FFFFFFF) AM_READWRITE(r9751_mmio_5ff_r, r9751_mmio_5ff_w)
	421	AM_RANGE(0xFF010000,0xFF01FFFF) AM_READWRITE(r9751_mmio_ff01_r, r9751_mmio_ff01_w)
376	422	AM_RANGE(0xFF050000,0xFF06FFFF) AM_READWRITE(r9751_mmio_ff05_r, r9751_mmio_ff05_w)
377	423	AM_RANGE(0xFFF80000,0xFFF8FFFF) AM_READWRITE(r9751_mmio_fff8_r, r9751_mmio_fff8_w)
378	424	//AM_RANGE(0xffffff00,0xffffffff) AM_RAM // Unknown area

trunk/src/mame/drivers/savquest.cpp
r253151	r253152
336	336	m_pci_3dfx_regs[0x08 / 4] = 2; // revision ID
337	337	m_pci_3dfx_regs[0x10 / 4] = 0xff000000;
338	338	m_pci_3dfx_regs[0x40 / 4] = 0x4000; //INITEN_SECONDARY_REV_ID
339		m_voodoo~~->voodoo~~_set_init_enable(0x4000); //INITEN_SECONDARY_REV_ID
	339	voodoo_set_init_enable(m_voodoo, 0x4000); //INITEN_SECONDARY_REV_ID
340	340	}
341	341
342	342	static UINT32 pci_3dfx_r(device_t busdevice, device_t device, int function, int reg, UINT32 mem_mask)
r253151	r253152
358	358	}
359	359	else if (reg == 0x40)
360	360	{
361		~~state->m_~~voodoo~~->voodoo~~_set_init_enable(data);
	361	voodoo_set_init_enable(state->m_voodoo, data);
362	362	}
363	363	else if (reg == 0x54)
364	364	{

trunk/src/mame/drivers/seattle.cpp
r253151	r253152
540	540
541	541	UINT32 seattle_state::screen_update_seattle(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
542	542	{
543		return m_voodoo~~->voodoo~~_update(bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
	543	return voodoo_update(m_voodoo, bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
544	544	}
545	545
546	546
r253151	r253152
876	876	break;
877	877
878	878	case 0x10: /* initEnable register */
879		m_voodoo~~->voodoo~~_set_init_enable(data);
	879	voodoo_set_init_enable(m_voodoo, data);
880	880	break;
881	881	}
882	882	if (LOG_PCI)

trunk/src/mame/drivers/stv.cpp
r253151	r253152
2901	2901	ROM_END
2902	2902
2903	2903
2904		ROM_START( pclub2pf ) // set to 1p
2905		STV_BIOS
2906
2907		ROM_REGION32_BE( 0x3000000, "cart", ROMREGION_ERASE00 ) /* SH2 code */
2908
2909		ROM_LOAD16_WORD_SWAP( "pclb2puf.IC22", 0x0200000, 0x0200000, CRC(a14282f2) SHA1(b96e70693d8e71b090e20efdd3aa6228e7289fa4) ) // OK
2910		ROM_LOAD16_WORD_SWAP( "pclb2puf.IC24", 0x0400000, 0x0200000, CRC(4fb4dc74) SHA1(1f174512c9cd5420d7f935cbc6b5875836f6e825) ) // OK
2911		ROM_LOAD16_WORD_SWAP( "pclb2puf.IC26", 0x0600000, 0x0200000, CRC(d20bbfb5) SHA1(5f2768e0e306bd0e3ed9b4e1d234aac8fd7155e6) ) // OK
2912		ROM_LOAD16_WORD_SWAP( "pclb2puf.IC28", 0x0800000, 0x0200000, CRC(da658ae9) SHA1(24293c2b23b3009956fc05df5177a27415754301) ) // OK
2913		ROM_LOAD16_WORD_SWAP( "pclb2puf.IC30", 0x0a00000, 0x0200000, CRC(cafc0e6b) SHA1(fa2ac54260336d5dd1ced7ccaf87115511ece1f8) ) // OK
2914
2915		ROM_REGION16_BE( 0x80, "eeprom", 0 ) // preconfigured to 1 player
2916		ROM_LOAD( "pclub2pf.nv", 0x0000, 0x0080, CRC(447bb3bd) SHA1(9fefec09849bfa0c14b49e73ff13e2a538dff511) )
2917		ROM_END
2918
2919	2904	ROM_START( pclb297w ) // set to 1p
2920	2905	STV_BIOS
2921	2906
r253151	r253152
2955	2940	ROM_LOAD( "pclub298.nv", 0x0000, 0x0080, CRC(a23dd0f2) SHA1(457282b5d40a17477b95330bba91e05c603f951e) )
2956	2941	ROM_END
2957	2942
2958
2959		ROM_START( pclub26w ) // set to 1p
2960		STV_BIOS
2961
2962		ROM_REGION32_BE( 0x3000000, "cart", ROMREGION_ERASE00 ) /* SH2 code */
2963
2964		ROM_LOAD16_WORD_SWAP( "pclbvol6w_IC22", 0x0200000, 0x0200000, CRC(72aa320c) SHA1(09bc30e8cb00a5a4014c44e468cc64f6c3425d92) )
2965		ROM_LOAD16_WORD_SWAP( "pclbvol6w_IC24", 0x0400000, 0x0200000, CRC(d98371e2) SHA1(813ac5f3c5b57d07cc319c73560bc0719ddcfe6b) )
2966		ROM_LOAD16_WORD_SWAP( "pclbvol6w_IC26", 0x0600000, 0x0200000, CRC(e6bbe3a5) SHA1(b2f642b8ca0779ad66cfbbadece40f4e3dc41fd1) )
2967		ROM_LOAD16_WORD_SWAP( "pclbvol6w_IC28", 0x0800000, 0x0200000, CRC(3c330c9b) SHA1(92f8e8d4f43db7c4ce431d17501492a7f8d8a867) )
2968		ROM_LOAD16_WORD_SWAP( "pclbvol6w_IC30", 0x0a00000, 0x0200000, CRC(67646090) SHA1(ed6402a22acafa0203c587b871edc547f0ec5277) )
2969
2970		ROM_REGION16_BE( 0x80, "eeprom", 0 ) // preconfigured to 1 player
2971		ROM_LOAD( "pclub26w.nv", 0x0000, 0x0080, CRC(448f770d) SHA1(5f966c511c4c8e9d5b2d257c41c2c88a453b4944) )
2972		ROM_END
2973
2974		ROM_START( pclub27s ) // set to 1p
2975		STV_BIOS
2976
2977		ROM_REGION32_BE( 0x3000000, "cart", ROMREGION_ERASE00 ) /* SH2 code */
2978
2979		ROM_LOAD16_WORD_SWAP( "pclub2v7.IC22", 0x0200000, 0x0200000, CRC(44c8ab27) SHA1(65e2705b2918da32ea40375707df4e148b311159) )
2980		ROM_LOAD16_WORD_SWAP( "pclub2v7.IC24", 0x0400000, 0x0200000, CRC(24818437) SHA1(5293d45b53680301abaf0b32a62596aaaa2552d6) )
2981		ROM_LOAD16_WORD_SWAP( "pclub2v7.IC26", 0x0600000, 0x0200000, CRC(076c1d44) SHA1(d597ed4524bb03eb0ef8ada08d49f3dc0fc8136d) )
2982		ROM_LOAD16_WORD_SWAP( "pclub2v7.IC28", 0x0800000, 0x0200000, CRC(ff9643ca) SHA1(3309f970f87324b06cc48add386019f769abcd89) )
2983		ROM_LOAD16_WORD_SWAP( "pclub2v7.IC30", 0x0a00000, 0x0200000, CRC(03b9eacf) SHA1(d69c10f7613d9f52042dd6cce64e74e2b1ecc2d8) )
2984
2985		ROM_REGION16_BE( 0x80, "eeprom", 0 ) // preconfigured to 1 player
2986		ROM_LOAD( "pclub27s.nv", 0x0000, 0x0080, CRC(e58c7167) SHA1(d88b1648c5d86a90615a8c6a1bf87bc9e75dc320) )
2987		ROM_END
2988
2989		ROM_START( pclub2pe ) // set to 1p
2990		STV_BIOS
2991
2992		ROM_REGION32_BE( 0x3000000, "cart", ROMREGION_ERASE00 ) /* SH2 code */
2993
2994		ROM_LOAD16_WORD_SWAP( "pclb2psi_IC22", 0x0200000, 0x0200000, CRC(caadc660) SHA1(f2e84bee96266bb03d8f9009249c17c27935f82e) )
2995		ROM_LOAD16_WORD_SWAP( "pclb2psi_IC24", 0x0400000, 0x0200000, CRC(ece82698) SHA1(b17b1ea8adc13c3722067c9854d1b7fdf3917090) )
2996		ROM_LOAD16_WORD_SWAP( "pclb2psi_IC26", 0x0600000, 0x0200000, CRC(c8a1e335) SHA1(a95ddfc41fdd9f720c11208f45ef5db4bee6cb97) )
2997		ROM_LOAD16_WORD_SWAP( "pclb2psi_IC28", 0x0800000, 0x0200000, CRC(52f09627) SHA1(e2ffc321bb0f2a650d0c0b39c3ec68226e1ca7f4) )
2998		ROM_LOAD16_WORD_SWAP( "pclb2psi_IC30", 0x0a00000, 0x0200000, CRC(03b9eacf) SHA1(d69c10f7613d9f52042dd6cce64e74e2b1ecc2d8) )
2999
3000		ROM_REGION16_BE( 0x80, "eeprom", 0 ) // preconfigured to 1 player
3001		ROM_LOAD( "pclub2pe.nv", 0x0000, 0x0080, CRC(447bb3bd) SHA1(9fefec09849bfa0c14b49e73ff13e2a538dff511))
3002		ROM_END
3003
3004
3005		ROM_START( pclubyo2 ) // set to 1p
3006		STV_BIOS
3007
3008		ROM_REGION32_BE( 0x3000000, "cart", ROMREGION_ERASE00 ) /* SH2 code */
3009
3010		ROM_LOAD16_WORD_SWAP( "pclbyov2.IC22", 0x0200000, 0x0200000, CRC(719a4d27) SHA1(328dfb8debea02e8660e636e953982d381529945) )
3011		ROM_LOAD16_WORD_SWAP( "pclbyov2.IC24", 0x0400000, 0x0200000, CRC(790dc7b5) SHA1(829ead39930779617a9bef41d8615362ca86c4c7) )
3012		ROM_LOAD16_WORD_SWAP( "pclbyov2.IC26", 0x0600000, 0x0200000, CRC(12ae1606) SHA1(9534fb2dbf6fd2c258ba2716783cc5bab8bd8dc0) )
3013		ROM_LOAD16_WORD_SWAP( "pclbyov2.IC28", 0x0800000, 0x0200000, CRC(ff9643ca) SHA1(3309f970f87324b06cc48add386019f769abcd89) )
3014		ROM_LOAD16_WORD_SWAP( "pclbyov2.IC30", 0x0a00000, 0x0200000, CRC(03b9eacf) SHA1(d69c10f7613d9f52042dd6cce64e74e2b1ecc2d8) )
3015
3016		ROM_REGION16_BE( 0x80, "eeprom", 0 ) // preconfigured to 1 player
3017		ROM_LOAD( "pclubyo2.nv", 0x0000, 0x0080, CRC(2b26a8f7) SHA1(32f34096cac05a37c492ee389ed8e4c02694c268) )
3018		ROM_END
3019
3020
3021	2943	ROM_START( pclb298a ) // set to 1p
3022	2944	STV_BIOS
3023	2945
r253151	r253152
3136	3058	ROM_LOAD( "pclb2elk.nv", 0x0000, 0x0080, CRC(54c7564f) SHA1(574dcc5e8fe4aac091fee1476347485ed660eddd) )
3137	3059	ROM_END
3138	3060
3139		ROM_START( pclove )
3140		STV_BIOS
3141	3061
3142		ROM_REGION32_BE( 0x3000000, "cart", ROMREGION_ERASE00 ) /* SH2 code */
3143		// note, 'IC2' in service mode (the test of IC24/IC26) fails once you map the protection device because it occupies the same memory address as the rom at IC26
3144		// there must be a way to enable / disable it.
3145		ROM_LOAD16_WORD_SWAP( "pclbLove.ic22", 0x0200000, 0x0200000, CRC(8cd25a0f) SHA1(c938d5f4f800db019abc2e17cce1e780e93f3d02) ) // OK (tested as IC7)
3146		ROM_LOAD16_WORD_SWAP( "pclbLove.ic24", 0x0400000, 0x0200000, CRC(85583e2c) SHA1(7f407d1bce40317fc10433dafcd82ee41be05839) ) // OK (tested as IC2)
3147		ROM_LOAD16_WORD_SWAP( "pclbLove.ic26", 0x0600000, 0x0200000, CRC(7efcabcc) SHA1(b99a67ab2053c3be5ce37530b65f9693c2a4eef8) ) // OK (tested as IC2)
3148		ROM_LOAD16_WORD_SWAP( "pclbLove.ic28", 0x0800000, 0x0200000, CRC(a1336da7) SHA1(ba26810067a13968a54a8867025b8d8e96384ae7) ) // OK (tested as IC3)
3149		ROM_LOAD16_WORD_SWAP( "pclbLove.ic30", 0x0a00000, 0x0200000, CRC(ec5b5e28) SHA1(89bcddb52c176c86ad4bdb9f4f052be5b75bcd1b) ) // OK (tested as IC3)
3150		ROM_LOAD16_WORD_SWAP( "pclbLove.ic32", 0x0c00000, 0x0200000, CRC(9a4109e5) SHA1(ba59caac5f5a80fc52c507d8a47f322a380aa9a1) ) // FF fill? (not tested either)
3151
3152		// protection device used to decrypt some startup code
3153
3154		ROM_REGION16_BE( 0x80, "eeprom", 0 ) // preconfigured to 1 player
3155		ROM_LOAD( "pclove.nv", 0x0000, 0x0080, CRC(3c78e3bd) SHA1(6d5fe8545f434b4cc1e8229549adb0a49ac45bd1) )
3156		ROM_END
3157
3158		// Name Club / Name Club vol.2
3159		// have an unusual rom mapping compared to other games, the cartridge is a little different too, with a large PALCE16V8H-10 marked 315-6026
3160		// For Name Club vol. 2, the protection device (317-0229 on both) is checked in the 'each game test' menu as 'RCDD2'
3161		// For the service mode test the game just passes a large block of compressed data and checksums the result, it doesn't even look like it's
3162		// passing 100% valid data, just an entire section of ROM, checking the result against a pre-calculated checksum.
3163
3164		// The device is accessed by the game when you choose to print, it looks like it's decompressing the full-size graphics for the printer rather
3165		// than anything you see onscreen. It makes quite extensive use of the device, with lots of different dictionaries, unlike Decathlete where
3166		// there are only 2 that cover all the data.
3167
3168		ROM_START( nameclub )
3169		STV_BIOS
3170
3171		ROM_REGION32_BE( 0x3000000, "cart", ROMREGION_ERASEFF ) /* SH2 code */
3172		ROM_LOAD16_WORD_SWAP( "ic22", 0x0200000, 0x0200000, CRC(ac23c648) SHA1(4dd099a92ff162082eb24a61a277ca907b3f9892) ) // OK
3173		ROM_LOAD16_WORD_SWAP( "ic24", 0x0600000, 0x0200000, CRC(a16902e3) SHA1(85c582cb0d02ef028a8ae32688c20a5b5aeeaae8) ) // OK
3174		ROM_LOAD16_WORD_SWAP( "ic26", 0x0a00000, 0x0200000, CRC(a5eab3f3) SHA1(1b7263639bb8f4aa644cc46133988ef4d2b6c9de) ) // OK
3175		ROM_LOAD16_WORD_SWAP( "ic28", 0x0e00000, 0x0200000, CRC(34ed677a) SHA1(ff2c4dd8fae33ac618f6e3e28ba71c4ecb4ca88f) ) // OK
3176
3177		ROM_REGION16_BE( 0x80, "eeprom", 0 ) // preconfigured to 1 player
3178		ROM_LOAD( "nameclub.nv", 0x0000, 0x0080, CRC(680a64bc) SHA1(45194bbe4a7e67f0e44f858589881967884f63a6) )
3179		ROM_END
3180
3181		ROM_START( nclubv2 )
3182		STV_BIOS
3183
3184		ROM_REGION32_BE( 0x3000000, "cart", ROMREGION_ERASEFF ) /* SH2 code */
3185		ROM_LOAD16_WORD_SWAP( "nclubv2.ic22", 0x0200000, 0x0200000, CRC(7e81676d) SHA1(fc0f0dcdb4aaf71218d7c1dd0e4ddc5381e8b13b) ) // OK
3186		ROM_LOAD16_WORD_SWAP( "nclubv2.ic24", 0x0600000, 0x0200000, CRC(1b7637de) SHA1(43c3094f60a6582298a45bad923fef57e98c5b2b) ) // OK
3187		ROM_LOAD16_WORD_SWAP( "nclubv2.ic26", 0x0a00000, 0x0200000, CRC(630be99d) SHA1(ac7fbaae98b126fad5228b0ebffa91a0f0a94516) ) // OK
3188		ROM_LOAD16_WORD_SWAP( "nclubv2.ic28", 0x0e00000, 0x0200000, CRC(1a3ca5e2) SHA1(4d3aed51d29c54e71175d828f648c9feb813ac04) ) // OK
3189
3190		ROM_REGION16_BE( 0x80, "eeprom", 0 ) // preconfigured to 1 player
3191		ROM_LOAD( "nclubv2.nv", 0x0000, 0x0080, CRC(96d55fa9) SHA1(b3c821d6cd4ed52d0e20565e12a06d8f81a08dbc) )
3192		ROM_END
3193
3194
3195
3196	3062	GAME( 1996, stvbios, 0, stv_slot, stv, stv_state, stv, ROT0, "Sega", "ST-V Bios", MACHINE_IS_BIOS_ROOT )
3197	3063
3198	3064	//GAME YEAR, NAME, PARENT, MACH, INP, INIT, MONITOR
r253151	r253152
3248	3114	GAME( 1997, znpwfv, stvbios, stv, stv, stv_state, znpwfv, ROT0, "Sega", "Zen Nippon Pro-Wrestling Featuring Virtua (J 971123 V1.000)", MACHINE_IMPERFECT_SOUND \| MACHINE_IMPERFECT_GRAPHICS )
3249	3115
3250	3116	/* Unemulated printer / camera devices */
3251		// USA sets
3252		GAME( 1997, pclub2, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 (U 970921 V1.000)", MACHINE_NOT_WORKING )
3253		GAME( 1999, pclub2v3, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Vol. 3 (U 990310 V1.000)", MACHINE_NOT_WORKING ) // Hello Kitty themed
3254		GAME( 1999, pclubpok, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club Pokemon B (U 991126 V1.000)", MACHINE_NOT_WORKING )
3255		// Japan sets
	3117	GAME( 1998, stress, stvbios, stv, stv, stv_state, stv, ROT0, "Sega", "Stress Busters (J 981020 V1.000)", MACHINE_NOT_WORKING \| MACHINE_IMPERFECT_GRAPHICS \| MACHINE_IMPERFECT_SOUND )
	3118	GAME( 1997, nclubv3, stvbios, stv, stv, stv_state, nameclv3, ROT0, "Sega", "Name Club Ver.3 (J 970723 V1.000)", MACHINE_IMPERFECT_SOUND \| MACHINE_IMPERFECT_GRAPHICS \| MACHINE_NOT_WORKING )
	3119	GAME( 1997, pclub2, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 (U 970921 V1.000)", MACHINE_NOT_WORKING )
3256	3120	GAME( 1999, pclub2fc, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Felix The Cat (Rev. A) (J 970415 V1.100)", MACHINE_NOT_WORKING )
3257		GAME( 1998, pclub2pf, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Puffy (Japan)", MACHINE_NOT_WORKING ) // version info is blank
3258		GAME( 1997, pclb2elk, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Earth Limited Kobe (Print Club Custom) (J 970808 V1.000)", MACHINE_NOT_WORKING )
3259		GAME( 1997, pclub2pe, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Pepsiman (J 970618 V1.100)", MACHINE_NOT_WORKING )
3260
3261		GAME( 1997, pclub26w, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Vol. 6 Winter (J 961210 V1.000)", MACHINE_NOT_WORKING ) // internal string is 'PURIKURA2 97FUYU' (but in reality it seems to be an end of 96 Winter version)
3262		GAME( 1997, pclub27s, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Vol. 7 Spring (J 970313 V1.100)", MACHINE_NOT_WORKING )
3263		// Summer 97?
3264		// Autumn 97?
3265		GAME( 1997, pclb297w, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 '97 Winter Ver (J 971017 V1.100)", MACHINE_NOT_WORKING ) // internal string is '97WINTER' (3 roms bad / missing tho, need new dump)
3266		GAME( 1997, pclub298, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 '98 Spring Ver (J 971017 V1.100)", MACHINE_NOT_WORKING ) // date is the same as previous version, surely incorrect / not updated when the game was
3267		// Summer 98?
	3121	GAME( 1997, pclb297w, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 '97 Winter Ver (J 971017 V1.100)", MACHINE_NOT_WORKING )
	3122	GAME( 1997, pclub298, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 '98 Spring Ver (J 971017 V1.100)", MACHINE_NOT_WORKING )
3268	3123	GAME( 1998, pclb298a, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 '98 Autumn Ver (J 980827 V1.000)", MACHINE_NOT_WORKING )
3269
3270
3271	3124	GAME( 1999, pclubor, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club Goukakenran (J 991104 V1.000)", MACHINE_NOT_WORKING )
3272	3125	GAME( 1999, pclubol, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club Olive (J 980717 V1.000)", MACHINE_NOT_WORKING )
	3126	GAME( 1999, pclub2v3, pclub2, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Vol. 3 (U 990310 V1.000)", MACHINE_NOT_WORKING )
	3127	GAME( 1999, pclubpok, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club Pokemon B (U 991126 V1.000)", MACHINE_NOT_WORKING )
3273	3128	GAME( 1997, pclub2kc, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club Kome Kome Club (J 970203 V1.000)", MACHINE_NOT_WORKING )
3274		GAME( 1997, pclove, stvbios, stv_5838, stv, stv_state, decathlt, ROT0, "Atlus", "Print Club LoveLove (J 970421 V1.000)", MACHINE_NOT_WORKING ) // uses the same type of protection as decathlete!!
3275		GAME( 1997, pclubyo2, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club Yoshimoto V2 (J 970422 V1.100)", MACHINE_NOT_WORKING )
	3129	GAME( 1997, pclb2elk, stvbios, stv, stv, stv_state, stv, ROT0, "Atlus", "Print Club 2 Earth Limited Kobe (Print Club Custom) (J 970808 V1.000)", MACHINE_NOT_WORKING )
3276	3130
3277		GAME( 1998, stress, stvbios, stv, stv, stv_state, stv, ROT0, "Sega", "Stress Busters (J 981020 V1.000)", MACHINE_NOT_WORKING \| MACHINE_IMPERFECT_GRAPHICS \| MACHINE_IMPERFECT_SOUND )
3278	3131
3279		GAME( 1996, nameclub, stvbios, stv_5838, stv, stv_state, decathlt, ROT0, "Sega", "Name Club (J 960315 V1.000)", MACHINE_NOT_WORKING ) // uses the same type of protection as decathlete!!
3280		GAME( 1996, nclubv2, stvbios, stv_5838, stv, stv_state, decathlt, ROT0, "Sega", "Name Club Ver.2 (J 960315 V1.000)", MACHINE_NOT_WORKING ) // ^ (has the same datecode as nameclub, probably incorrect unless both were released today)
3281		GAME( 1997, nclubv3, stvbios, stv, stv, stv_state, nameclv3, ROT0, "Sega", "Name Club Ver.3 (J 970723 V1.000)", MACHINE_IMPERFECT_SOUND \| MACHINE_IMPERFECT_GRAPHICS \| MACHINE_NOT_WORKING ) // no protection
3282
3283
3284
3285	3132	/* Doing something.. but not enough yet */
3286	3133	GAME( 1995, vfremix, stvbios, stv, stv, stv_state, vfremix, ROT0, "Sega", "Virtua Fighter Remix (JUETBKAL 950428 V1.000)", MACHINE_IMPERFECT_SOUND \| MACHINE_IMPERFECT_GRAPHICS \| MACHINE_NOT_WORKING )
3287	3134	GAME( 1996, decathlt, stvbios, stv_5838, stv, stv_state, decathlt, ROT0, "Sega", "Decathlete (JUET 960709 V1.001)", MACHINE_NO_SOUND \| MACHINE_NOT_WORKING \| MACHINE_UNEMULATED_PROTECTION )

trunk/src/mame/drivers/tispeak.cpp
r253151	r253152
80	80	- notes: this one has a dedicated voice actor
81	81
82	82	Speak & Spell (France) "La Dictee Magique", 1980
83		- MCU: CD2702~~, labeled CD2702AN2L (die labeled TMC0270F 2702A)~~
	83	- MCU: CD2702*
84	84	- TMS51xx: CD2801
85	85	- VSM: 16KB CD2352
86	86
r253151	r253152
143	143	Speak & Math:
144	144
145	145	Speak & Math (US), 1980 (renamed to "Speak & Maths" in UK, but is the same product)
146		- MCU: CD2704~~, labeled CD2704B-N2L (die labeled TMC0270F 2704B) - 2nd revision?(mid-1982)~~
	146	- MCU: CD2704*
147	147	- TMS51xx: CD2801
148	148	- VSM(1/2): 16KB CD2392
149	149	- VSM(2/2): 16KB CD2393
r253151	r253152
170	170	Speak & Read:
171	171
172	172	Speak & Read (US), 1980
173		- MCU: CD2705, labeled CD2705B-N2L (die labeled TMC0270E 2705B) - 2nd revision?~~(late-1981)~~
	173	- MCU: CD2705, labeled CD2705B-N2L (die labeled TMC0270E 2705B) - 2nd revision?
174	174	- TMS51xx: CD2801
175	175	- VSM(1/2): 16KB CD2394(rev.A)
176	176	- VSM(2/2): 16KB CD2395(rev.A)
r253151	r253152
1242	1242	ROM_REGION( 2127, "maincpu:mpla", 0 )
1243	1243	ROM_LOAD( "tms0270_common2_micro.pla", 0, 2127, CRC(86737ac1) SHA1(4aa0444f3ddf88738ea74aec404c684bf54eddba) )
1244	1244	ROM_REGION( 1246, "maincpu:opla", 0 )
1245		ROM_LOAD( "tms0270_tmc0271_output.pla", 0, 1246, CRC(9ebe12ab) SHA1(acb4e07ba26f2daca5f1c234885ac0371c7ce87f) ) // using the one from 1st version
	1245	ROM_LOAD( "tms0270_tmc0271_output.pla", 0, 1246, CRC(9ebe12ab) SHA1(acb4e07ba26f2daca5f1c234885ac0371c7ce87f) ) // using the one from 1978 version
1246	1246
1247	1247	ROM_REGION( 0x10000, "tms6100", ROMREGION_ERASEFF ) // 8000-bfff = space reserved for cartridge
1248		ROM_LOAD( "tmc0351nl.vsm", 0x0000, 0x4000, CRC(beea3373) SHA1(8b0f7586d2f12c3d4a885fdb528cf23feffa1a3b) ) // using the one from 1st version
	1248	ROM_LOAD( "tmc0351nl.vsm", 0x0000, 0x4000, CRC(beea3373) SHA1(8b0f7586d2f12c3d4a885fdb528cf23feffa1a3b) ) // using the one from 1978 version
1249	1249	ROM_LOAD( "tmc0352nl.vsm", 0x4000, 0x4000, CRC(d51f0587) SHA1(ddaa484be1bba5fef46b481cafae517e4acaa8ed) ) // "
1250	1250	ROM_END
1251	1251
r253151	r253152
1256	1256	ROM_REGION( 1246, "maincpu:ipla", 0 )
1257	1257	ROM_LOAD( "tms0980_common1_instr.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
1258	1258	ROM_REGION( 2127, "maincpu:mpla", 0 )
1259		ROM_LOAD( "tms0270_common2_micro.pla", 0, 2127, CRC(86737ac1) SHA1(4aa0444f3ddf88738ea74aec404c684bf54eddba) )
	1259	ROM_LOAD( "tms0270_common2_micro.pla", 0, 2127, BAD_DUMP CRC(86737ac1) SHA1(4aa0444f3ddf88738ea74aec404c684bf54eddba) ) // not verified
1260	1260	ROM_REGION( 1246, "maincpu:opla", 0 )
1261	1261	ROM_LOAD( "tms0270_tmc0271_output.pla", 0, 1246, CRC(9ebe12ab) SHA1(acb4e07ba26f2daca5f1c234885ac0371c7ce87f) )
1262	1262
r253151	r253152
1287	1287	ROM_REGION( 1246, "maincpu:ipla", 0 )
1288	1288	ROM_LOAD( "tms0980_common1_instr.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
1289	1289	ROM_REGION( 2127, "maincpu:mpla", 0 )
1290		ROM_LOAD( "tms0270_common2_micro.pla", 0, 2127, CRC(86737ac1) SHA1(4aa0444f3ddf88738ea74aec404c684bf54eddba) )
	1290	ROM_LOAD( "tms0270_common2_micro.pla", 0, 2127, BAD_DUMP CRC(86737ac1) SHA1(4aa0444f3ddf88738ea74aec404c684bf54eddba) ) // not verified
1291	1291	ROM_REGION( 1246, "maincpu:opla", 0 )
1292	1292	ROM_LOAD( "tms0270_tmc0271_output.pla", 0, 1246, CRC(9ebe12ab) SHA1(acb4e07ba26f2daca5f1c234885ac0371c7ce87f) )
1293	1293
r253151	r253152
1329	1329
1330	1330	ROM_START( snspellfr )
1331	1331	ROM_REGION( 0x1000, "maincpu", 0 )
1332		ROM_LOAD( "c~~d27~~02an2l", 0x0000, 0x1000, CRC(895d~~6a4e~~) SHA1(~~a8bc~~118c83a~~842~~6003373419~~1dc~~a~~a71a93d~~f~~a52b~~) )
	1332	ROM_LOAD( "tmc0271h-n2l", 0x0000, 0x1000, BAD_DUMP CRC(f83b5d2d) SHA1(10155b0b7f7f1583c7def8a693553cd35944ea6f) ) // placeholder, use the one we have
1333	1333
1334	1334	ROM_REGION( 1246, "maincpu:ipla", 0 )
1335	1335	ROM_LOAD( "tms0980_common1_instr.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
1336	1336	ROM_REGION( 2127, "maincpu:mpla", 0 )
1337		ROM_LOAD( "tms0270_common1_micro.pla", 0, 2127, CRC(~~504b9~~6bb) SHA1(~~67b691e7c~~0b9723~~94105~~87e50~~e5182bf~~46475b43) )
	1337	ROM_LOAD( "tms0270_common2_micro.pla", 0, 2127, BAD_DUMP CRC(86737ac1) SHA1(4aa0444f3ddf88738ea74aec404c684bf54eddba) ) // not verified
1338	1338	ROM_REGION( 1246, "maincpu:opla", 0 )
1339		ROM_LOAD( "tms0270_c~~d27~~02_output.pla", 0, 1246, CRC(2478c595) SHA1(9a8ac690902731e1e01533279a1c9223011e1537) )
	1339	ROM_LOAD( "tms0270_tmc0271h_output.pla", 0, 1246, BAD_DUMP CRC(2478c595) SHA1(9a8ac690902731e1e01533279a1c9223011e1537) ) // placeholder, use the one we have
1340	1340
1341	1341	ROM_REGION( 0x10000, "tms6100", ROMREGION_ERASEFF ) // uses only 1 rom, 8000-bfff = space reserved for cartridge
1342	1342	ROM_LOAD( "cd2352.vsm", 0x0000, 0x4000, CRC(181a239e) SHA1(e16043766c385e152b7005c1c010be4c5fccdd9b) )
r253151	r253152
1344	1344
1345	1345	ROM_START( snspellit )
1346	1346	ROM_REGION( 0x1000, "maincpu", 0 )
1347		ROM_LOAD( "c~~d27~~02an2l", 0x0000, 0x1000, CRC(895d~~6a4e~~) SHA1(~~a8bc~~118c83a~~842~~6003373419~~1dc~~a~~a71a93d~~f~~a52b~~) )
	1347	ROM_LOAD( "tmc0271h-n2l", 0x0000, 0x1000, BAD_DUMP CRC(f83b5d2d) SHA1(10155b0b7f7f1583c7def8a693553cd35944ea6f) ) // placeholder, use the one we have
1348	1348
1349	1349	ROM_REGION( 1246, "maincpu:ipla", 0 )
1350	1350	ROM_LOAD( "tms0980_common1_instr.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
1351	1351	ROM_REGION( 2127, "maincpu:mpla", 0 )
1352		ROM_LOAD( "tms0270_common1_micro.pla", 0, 2127, CRC(~~504b9~~6bb) SHA1(~~67b691e7c~~0b9723~~94105~~87e50~~e5182bf~~46475b43) )
	1352	ROM_LOAD( "tms0270_common2_micro.pla", 0, 2127, BAD_DUMP CRC(86737ac1) SHA1(4aa0444f3ddf88738ea74aec404c684bf54eddba) ) // not verified
1353	1353	ROM_REGION( 1246, "maincpu:opla", 0 )
1354		ROM_LOAD( "tms0270_c~~d27~~02_output.pla", 0, 1246, CRC(2478c595) SHA1(9a8ac690902731e1e01533279a1c9223011e1537) )
	1354	ROM_LOAD( "tms0270_tmc0271h_output.pla", 0, 1246, BAD_DUMP CRC(2478c595) SHA1(9a8ac690902731e1e01533279a1c9223011e1537) ) // placeholder, use the one we have
1355	1355
1356	1356	ROM_REGION( 0x10000, "tms6100", ROMREGION_ERASEFF ) // uses only 1 rom, 8000-bfff = space reserved for cartridge
1357	1357	ROM_LOAD( "cd62190.vsm", 0x0000, 0x4000, CRC(63832002) SHA1(ea8124b2bf0f5908c5f1a56d60063f2468a10143) )
r253151	r253152
1400	1400
1401	1401	ROM_START( snmath )
1402	1402	ROM_REGION( 0x1000, "maincpu", 0 )
1403		ROM_LOAD( "cd270~~4b-~~n2l", 0x0000, 0x1000, CRC(7e06~~c7c5~~) SHA1(d60a3~~5a81~~63ab593c~~31afc84~~0~~a0d8a~~9b3a7~~62f2~~9) )
	1403	ROM_LOAD( "cd2708n2l", 0x0000, 0x1000, CRC(35937360) SHA1(69c362c75bb459056c09c7fab37c91040485474b) )
1404	1404
1405	1405	ROM_REGION( 1246, "maincpu:ipla", 0 )
1406	1406	ROM_LOAD( "tms0980_common1_instr.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
1407	1407	ROM_REGION( 2127, "maincpu:mpla", 0 )
1408	1408	ROM_LOAD( "tms0270_common1_micro.pla", 0, 2127, CRC(504b96bb) SHA1(67b691e7c0b97239410587e50e5182bf46475b43) )
1409	1409	ROM_REGION( 1246, "maincpu:opla", 0 )
1410		ROM_LOAD( "tms0270_cd2704_output.pla", 0, 1246, CRC(5a2eb949) SHA1(8bb161d4884f229af65f8d155e59b9d8966fe3d1) )
1411
1412		ROM_REGION( 0x8000, "tms6100", ROMREGION_ERASEFF )
1413		ROM_LOAD( "cd2392.vsm", 0x0000, 0x4000, CRC(4ed2e920) SHA1(8896f29e25126c1e4d9a47c9a325b35dddecc61f) )
1414		ROM_LOAD( "cd2393.vsm", 0x4000, 0x4000, CRC(571d5b5a) SHA1(83284755d9b77267d320b5b87fdc39f352433715) )
1415		ROM_END
1416
1417		ROM_START( snmatha )
1418		ROM_REGION( 0x1000, "maincpu", 0 )
1419		ROM_LOAD( "cd2708-n2l", 0x0000, 0x1000, CRC(35937360) SHA1(69c362c75bb459056c09c7fab37c91040485474b) )
1420
1421		ROM_REGION( 1246, "maincpu:ipla", 0 )
1422		ROM_LOAD( "tms0980_common1_instr.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
1423		ROM_REGION( 2127, "maincpu:mpla", 0 )
1424		ROM_LOAD( "tms0270_common1_micro.pla", 0, 2127, CRC(504b96bb) SHA1(67b691e7c0b97239410587e50e5182bf46475b43) )
1425		ROM_REGION( 1246, "maincpu:opla", 0 )
1426	1410	ROM_LOAD( "tms0270_cd2708_output.pla", 0, 1246, CRC(1abad753) SHA1(53d20b519ed73ce248368047a056836afbe3cd46) )
1427	1411
1428	1412	ROM_REGION( 0x8000, "tms6100", ROMREGION_ERASEFF )
r253151	r253152
1442	1426	ROM_REGION( 1246, "maincpu:ipla", 0 )
1443	1427	ROM_LOAD( "tms0980_common1_instr.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
1444	1428	ROM_REGION( 2127, "maincpu:mpla", 0 )
1445		ROM_LOAD( "tms0270_common1_micro.pla", 0, 2127, CRC(504b96bb) SHA1(67b691e7c0b97239410587e50e5182bf46475b43) )
	1429	ROM_LOAD( "tms0270_common1_micro.pla", 0, 2127, BAD_DUMP CRC(504b96bb) SHA1(67b691e7c0b97239410587e50e5182bf46475b43) ) // not verified
1446	1430	ROM_REGION( 1246, "maincpu:opla", 0 )
1447		ROM_LOAD( "tms0270_cd2704_output.pla", 0, 1246, CRC(5a2eb~~949~~) SHA1(8bb161d4884~~f229~~af65f8~~d155e59b9d89~~66fe3d1) ) // ~~using~~ the one from 1st version
	1431	ROM_LOAD( "tms0270_cd2708_output.pla", 0, 1246, BAD_DUMP CRC(1abad753) SHA1(53d20b519ed73ce248368047a056836afbe3cd46) ) // taken from cd2708, need to verify if it's same as cd2704
1448	1432
1449	1433	ROM_REGION( 0x8000, "tms6100", ROMREGION_ERASEFF )
1450		ROM_LOAD( "cd2392.vsm", 0x0000, 0x4000, CRC(4ed2e920) SHA1(8896f29e25126c1e4d9a47c9a325b35dddecc61f) ) // using the one from 1st version
1451		ROM_LOAD( "cd2393.vsm", 0x4000, 0x4000, CRC(571d5b5a) SHA1(83284755d9b77267d320b5b87fdc39f352433715) ) // "
	1434	ROM_LOAD( "cd2392.vsm", 0x0000, 0x4000, CRC(4ed2e920) SHA1(8896f29e25126c1e4d9a47c9a325b35dddecc61f) )
	1435	ROM_LOAD( "cd2393.vsm", 0x4000, 0x4000, CRC(571d5b5a) SHA1(83284755d9b77267d320b5b87fdc39f352433715) )
1452	1436	ROM_END
1453	1437
1454	1438
r253151	r253152
1553	1537
1554	1538
1555	1539	/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY, FULLNAME, FLAGS */
1556		COMP( 1979, snspell, 0, 0, sns_tmc0281, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (US, 1979 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
	1540	COMP( 1978, snspell, 0, 0, sns_tmc0281, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (US, 1979 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1557	1541	COMP( 1978, snspellp, snspell, 0, sns_tmc0281, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (US, patent)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1558	1542	COMP( 1980, snspellub, snspell, 0, sns_tmc0281d, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (US, 1980 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1559		COMP( 1978, snspellua, snspell, 0, sns_tmc0281, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (US, 1978 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND ) // incomplete dump, using 1979 MCU ROM instead
1560		COMP( 1978, snspelluk, snspell, 0, sns_tmc0281, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (UK, 1978 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND ) // "
	1543	COMP( 1979, snspellua, snspell, 0, sns_tmc0281, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (US, 1978 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_NOT_WORKING ) // incomplete dump, using 1979 MCU ROM instead
	1544	COMP( 1978, snspelluk, snspell, 0, sns_tmc0281, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (UK, 1978 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_NOT_WORKING ) // "
1561	1545	COMP( 1981, snspelluka, snspell, 0, sns_cd2801, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (UK, 1981 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1562	1546	COMP( 1979, snspelljp, snspell, 0, sns_tmc0281, snspell, tispeak_state, snspell, "Texas Instruments", "Speak & Spell (Japan)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1563		COMP( 1980, snspellfr, snspell, 0, sns_cd2801, snspellfr, tispeak_state, snspell, "Texas Instruments", "La Dictee Magique (France)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1564		COMP( 1982, snspellit, snspell, 0, sns_cd2801_m, snspellit, tispeak_state, snspell, "Texas Instruments", "Grillo Parlante (Italy)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
	1547	COMP( 1980, snspellfr, snspell, 0, sns_cd2801, snspellfr, tispeak_state, snspell, "Texas Instruments", "La Dictee Magique (France)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_NOT_WORKING ) // doesn't work due to missing CD2702 MCU dump, German/Italian version has CD2702 too
	1548	COMP( 1982, snspellit, snspell, 0, sns_cd2801_m, snspellit, tispeak_state, snspell, "Texas Instruments", "Grillo Parlante (Italy)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_NOT_WORKING ) // "
1565	1549
1566	1550	COMP( 1981, snspellc, 0, 0, snspellc, snspellc, tispeak_state, snspell, "Texas Instruments", "Speak & Spell Compact (US, 1981 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1567	1551	COMP( 1982, snspellca, snspellc, 0, snspellc, snspellc, tispeak_state, snspell, "Texas Instruments", "Speak & Spell Compact (US, 1982 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1568	1552	COMP( 1982, snspellcuk, snspellc, 0, snspellcuk, snspellcuk, tispeak_state, snspell, "Texas Instruments", "Speak & Write (UK)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1569	1553
1570		COMP( 1980, snmath, 0, 0, snmath, snmath, driver_device, 0, "Texas Instruments", "Speak & Math (US, 1980 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1571		COMP( 1986, snmatha, snmath, 0, snmath, snmath, driver_device, 0, "Texas Instruments", "Speak & Math (US, 1986 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1572		COMP( 1980, snmathp, snmath, 0, snmath, snmath, driver_device, 0, "Texas Instruments", "Speak & Math (US, patent)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_IS_INCOMPLETE )
	1554	COMP( 1986, snmath, 0, 0, snmath, snmath, driver_device, 0, "Texas Instruments", "Speak & Math (US, 1986 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
	1555	COMP( 1980, snmathp, snmath, 0, snmath, snmath, driver_device, 0, "Texas Instruments", "Speak & Math (US, 1980 version/patent)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_NOT_WORKING )
1573	1556
1574	1557	COMP( 1980, snread, 0, 0, snread, snread, tispeak_state, snspell, "Texas Instruments", "Speak & Read (US)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND )
1575	1558
1576	1559	COMP( 1979, lantutor, 0, 0, lantutor, lantutor, tispeak_state, lantutor, "Texas Instruments", "Language Tutor (patent)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_NOT_WORKING )
1577	1560
1578		COMP( 1981, tntell, 0, 0, tntell, tntell, tispeak_state, tntell, "Texas Instruments", "Touch & Tell (US)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_CLICKABLE_ARTWORK \| MACHINE_REQUIRES_ARTWORK )
1579		COMP( 1980, tntellp, tntell, 0, tntell, tntell, tispeak_state, tntell, "Texas Instruments", "Touch & Tell (US, patent)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_CLICKABLE_ARTWORK \| MACHINE_REQUIRES_ARTWORK \| MACHINE_NOT_WORKING )
	1561	COMP( 1981, tntell, 0, 0, tntell, tntell, tispeak_state, tntell, "Texas Instruments", "Touch & Tell (US, 1981 version)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_CLICKABLE_ARTWORK \| MACHINE_REQUIRES_ARTWORK ) // assume there is an older version too, with CD8010 MCU
	1562	COMP( 1980, tntellp, tntell, 0, tntell, tntell, tispeak_state, tntell, "Texas Instruments", "Touch & Tell (patent)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_CLICKABLE_ARTWORK \| MACHINE_REQUIRES_ARTWORK \| MACHINE_NOT_WORKING )
1580	1563	COMP( 1981, tntelluk, tntell, 0, tntell, tntell, tispeak_state, tntell, "Texas Instruments", "Touch & Tell (UK)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_CLICKABLE_ARTWORK \| MACHINE_REQUIRES_ARTWORK )
1581	1564	COMP( 1981, tntellfr, tntell, 0, tntell, tntell, tispeak_state, tntell, "Texas Instruments", "Le Livre Magique (France)", MACHINE_SUPPORTS_SAVE \| MACHINE_IMPERFECT_SOUND \| MACHINE_CLICKABLE_ARTWORK \| MACHINE_REQUIRES_ARTWORK )
1582	1565

trunk/src/mame/drivers/vc4000.cpp
r253151	r253152
722	722	CONS(1979, krvnjvtv, 0, vc4000, vc4000, vc4000, driver_device, 0, "SOE", "OC Jeu Video TV Karvan", MACHINE_IMPERFECT_GRAPHICS ) /* France */
723	723	CONS(1979, oc2000, krvnjvtv, 0, vc4000, vc4000, driver_device, 0, "SOE", "OC-2000", MACHINE_IMPERFECT_GRAPHICS ) /* France */
724	724	CONS(1980, mpt05, 0, vc4000, vc4000, vc4000, driver_device, 0, "ITMC", "MPT-05", MACHINE_IMPERFECT_GRAPHICS ) /* France */
725		CONS(1982, h21, 0, ~~vc4~~000, h21, vc4000, driver_device, 0, "TRQ", "Video Computer H-21", MACHINE_IMPERFECT_GRAPHICS) // Spain
	725	CONS(1982, h21, 0, 0, h21, vc4000, driver_device, 0, "TRQ", "Video Computer H-21", MACHINE_IMPERFECT_GRAPHICS) // Spain
726	726	CONS(1979, elektor, 0, 0, elektor, elektor, driver_device, 0, "Elektor", "Elektor TV Games Computer", MACHINE_IMPERFECT_GRAPHICS )

trunk/src/mame/drivers/vegas.cpp
r253151	r253152
493	493	UINT8 m_sio_led_state;
494	494	UINT8 m_pending_analog_read;
495	495	UINT8 m_cmos_unlocked;
496		~~voo~~d~~oo_d~~evice *m_voodoo;
	496	device_t *m_voodoo;
497	497	UINT8 m_dcs_idma_cs;
498	498	int m_count;
499	499	int m_dynamic_count;
r253151	r253152
567	567
568	568	UINT32 vegas_state::screen_update_vegas(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
569	569	{
570		return m_voodoo~~->voodoo~~_update(bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
	570	return voodoo_update(m_voodoo, bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
571	571	}
572	572
573	573
r253151	r253152
579	579
580	580	void vegas_state::machine_start()
581	581	{
582		m_voodoo = ~~(voodoo_device*)~~machine().device("voodoo");
	582	m_voodoo = machine().device("voodoo");
583	583
584	584	/* allocate timers for the NILE */
585	585	m_timer[0] = machine().scheduler().timer_alloc(FUNC_NULL);
r253151	r253152
797	797
798	798	READ32_MEMBER( vegas_state::pci_3dfx_r )
799	799	{
800		int voodoo_type = m_voodoo~~->voodoo~~_get_type();
	800	int voodoo_type = voodoo_get_type(m_voodoo);
801	801	UINT32 result = m_pci_3dfx_regs[offset];
802	802
803	803	switch (offset)
r253151	r253152
830	830
831	831	WRITE32_MEMBER( vegas_state::pci_3dfx_w )
832	832	{
833		int voodoo_type = m_voodoo~~->voodoo~~_get_type();
	833	int voodoo_type = voodoo_get_type(m_voodoo);
834	834
835	835	m_pci_3dfx_regs[offset] = data;
836	836
r253151	r253152
869	869	break;
870	870
871	871	case 0x10: /* initEnable register */
872		m_voodoo~~->voodoo~~_set_init_enable(data);
	872	voodoo_set_init_enable(m_voodoo, data);
873	873	break;
874	874
875	875	}
r253151	r253152
1555	1555	void vegas_state::remap_dynamic_addresses()
1556	1556	{
1557	1557	dynamic_address *dynamic = m_dynamic;
1558		int voodoo_type = m_voodoo~~->voodoo~~_get_type();
	1558	int voodoo_type = voodoo_get_type(m_voodoo);
1559	1559	offs_t base;
1560	1560	int addr;
1561	1561

trunk/src/mame/drivers/viper.cpp
r253151	r253152
435	435
436	436	UINT32 viper_state::screen_update_viper(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
437	437	{
438		voodoo_device voodoo = (voodoo_device)machine().device("voodoo");
439		return voodoo->voodoo_update(bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
	438	device_t *device = machine().device("voodoo");
	439	return voodoo_update(device, bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
440	440	}
441	441
442	442	UINT32 m_mpc8240_regs[256/4];

trunk/src/mame/includes/arkanoid.h
r253151	r253152
62	62	UINT8 m_ddr_c;
63	63	UINT8 m_tdr;
64	64	UINT8 m_tcr;
65		emu_timer *m_68705_timer;
66	65
	66
67	67	/* hexaa */
68	68	UINT8 m_hexaa_from_main;
69	69	UINT8 m_hexaa_from_sub;

trunk/src/mame/includes/chihiro.h
r253151	r253152
346	346	B8 = 9,
347	347	G8B8 = 10
348	348	};
349		enum class NV2A_GL_FRONT_FACE {
350		CW = 0x0900,
351		CCW = 0x0901
352		};
353		enum class NV2A_GL_CULL_FACE {
354		FRONT = 0x0404,
355		BACK = 0x0405,
356		FRONT_AND_BACK = 0x0408
357		};
358	349
359	350	nv2a_renderer(running_machine &machine) : poly_manager<float, nvidia_object_data, 13, 8192>(machine)
360	351	{
r253151	r253152
372	363	indexesleft_count = 0;
373	364	vertex_pipeline = 4;
374	365	color_mask = 0xffffffff;
375		backface_culling_enabled = false;
376		backface_culling_winding = NV2A_GL_FRONT_FACE::CCW;
377		backface_culling_culled = NV2A_GL_CULL_FACE::BACK;
378	366	alpha_test_enabled = false;
379	367	alpha_reference = 0;
380	368	alpha_func = NV2A_COMPARISON_OP::ALWAYS;
r253151	r253152
476	464	int read_vertices_0x1810(address_space & space, vertex_nv *destination, int offset, int limit);
477	465	int read_vertices_0x1818(address_space & space, vertex_nv *destination, UINT32 address, int limit);
478	466	void convert_vertices_poly(vertex_nv source, vertex_t destination, int count);
479		UINT32 render_triangle_culling(const rectangle &cliprect, render_delegate callback, int paramcount, const vertex_t &_v1, const vertex_t &_v2, const vertex_t &_v3);
480	467	void clear_render_target(int what, UINT32 value);
481	468	void clear_depth_buffer(int what, UINT32 value);
482	469	inline UINT8 *direct_access_ptr(offs_t address);
r253151	r253152
643	630	std::mutex lock;
644	631	} combiner;
645	632	UINT32 color_mask;
646		bool backface_culling_enabled;
647		NV2A_GL_FRONT_FACE backface_culling_winding;
648		NV2A_GL_CULL_FACE backface_culling_culled;
649	633	bool alpha_test_enabled;
650	634	NV2A_COMPARISON_OP alpha_func;
651	635	int alpha_reference;

trunk/src/mame/includes/overdriv.h
r253151	r253152
51	51	DECLARE_WRITE16_MEMBER(cpuB_ctrl_w);
52	52	DECLARE_WRITE16_MEMBER(overdriv_soundirq_w);
53	53	DECLARE_WRITE8_MEMBER(sound_ack_w);
54		DECLARE_WRITE16_MEMBER(slave_irq4_assert_w);
55		DECLARE_WRITE16_MEMBER(slave_irq5_assert_w);
56		DECLARE_WRITE16_MEMBER(objdma_w);
57		TIMER_CALLBACK_MEMBER(objdma_end_cb);
58
	54	DECLARE_WRITE16_MEMBER(overdriv_cpuB_irq_x_w);
	55	DECLARE_WRITE16_MEMBER(overdriv_cpuB_irq_y_w);
59	56	virtual void machine_start() override;
60	57	virtual void machine_reset() override;
61	58	UINT32 screen_update_overdriv(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
62		//INTERRUPT_GEN_MEMBER(cpuB_interrupt);
	59	INTERRUPT_GEN_MEMBER(cpuB_interrupt);
63	60	TIMER_DEVICE_CALLBACK_MEMBER(overdriv_cpuA_scanline);
64	61	int m_fake_timer;
65	62

trunk/src/mame/machine/315-5838_317-0229_comp.cpp
r253151	r253152
4	4
5	5	315-5838 - Decathlete (ST-V)
6	6	317-0229 - Dead or Alive (Model 2A)
7		317-0229 - Name Club Ver 2 (ST-V) (tested as RCDD2 in the service menu!)
8		317-0231 - Print Club Love Love (ST-V)
9	7
10		Several Print Club (ST-V) carts have
11		an unpopulated space marked '317-0229' on the PCB
12
13	8	Package Type: TQFP100
14	9
15		Decathlete accesses the chip at 2 different addresses, however, I don't think there
16		are 2 channels / sets of registers, instead the 2nd set of addresses are just a
17		mirror that allows access to a different set of source roms; the tables etc. are
18		re-uploaded before every transfer.
	10	This appears to be a dual channel compression chip, used in 1996, predating the 5881.
	11	Decathlete uses it to compress ALL the game graphics, Dead or Alive uses it for a
	12	dumb security check, decompressing a single string.
19	13
20		Dead of Alive has the source data in RAM, not ROM.
	14	Each channel appears to be connected to a different set of ROMs, however there is
	15	defintiely only a single 315-5838 chip. (could the different channels actually just
	16	be mirror addresses, with part of the address determining the ROMs to use?)
	17
	18	Dead of Alive only uses a single channel, and has the source data in RAM, not ROM.
21	19	This is similar to how some 5881 games were set up, with the ST-V versions decrypting
22	20	data directly from ROM and the Model 2 ones using a RAM source buffer.
23	21
r253151	r253152
51	49
52	50	void sega_315_5838_comp_device::device_start()
53	51	{
54		m_decathlt_lastcount = 0;
55		m_decathlt_prot_uploadmode = 0;
56		m_decathlt_prot_uploadoffset = 0;
57
58	52	for (auto & elem : m_channel)
59	53	{
	54	elem.m_decathlt_lastcount = 0;
	55	elem.m_decathlt_prot_uploadmode = 0;
	56	elem.m_decathlt_prot_uploadoffset = 0;
60	57	elem.m_read_ch.bind_relative_to(*owner());
61	58
62	59	}
r253151	r253152
64	61
65	62	void sega_315_5838_comp_device::device_reset()
66	63	{
67		m_srcoffset = 0;
68		m_decathlt_lastcount = 0;
69		m_decathlt_prot_uploadmode = 0;
70		m_decathlt_prot_uploadoffset = 0;
	64	for (auto & elem : m_channel)
	65	{
	66	elem.m_srcoffset = 0;
	67	elem.m_decathlt_lastcount = 0;
	68	elem.m_decathlt_prot_uploadmode = 0;
	69	elem.m_decathlt_prot_uploadoffset = 0;
	70	}
	71
71	72	m_protstate = 0;
72	73	}
73	74
r253151	r253152
99	100	// UINT32 fake0 = (UINT32)memregion( ":fake0" )->base();
100	101	// UINT32 retvalue = 0xffff;
101	102
102		switch (m_srcoffset)
	103	switch (m_channel[channel].m_srcoffset)
103	104	{
104	105	default:
105	106
106		m_decathlt_lastcount++;
	107	m_channel[channel].m_decathlt_lastcount++;
107	108
108	109	UINT32 tempdata = 0;
109		tempdata \|= m_channel[channel].m_read_ch(m_srcoffset) << 0;
110		m_srcoffset++;
111		tempdata \|= m_channel[channel].m_read_ch(m_srcoffset) << 16;
112		m_srcoffset++;
	110	tempdata \|= m_channel[channel].m_read_ch(m_channel[channel].m_srcoffset) << 0;
	111	m_channel[channel].m_srcoffset++;
	112	tempdata \|= m_channel[channel].m_read_ch(m_channel[channel].m_srcoffset) << 16;
	113	m_channel[channel].m_srcoffset++;
113	114
114	115
115	116	#ifdef DEBUG_DATA_DUMP
116		//printf("read addr %08x, blah_r %08x - read count count %08x\n", m_srcoffset2, tempdata, m_decathlt_lastcount4);
	117	//printf("read addr %08x, blah_r %08x - read count count %08x\n", m_channel[channel].m_srcoffset2, tempdata, m_channel[channel].m_decathlt_lastcount4);
117	118	fwrite(&tempdata, 1, 4, tempfile);
118	119	#else
119		logerror("read addr %08x, blah_r %08x - read count count %08x\n", m_srcoffset2, tempdata, m_decathlt_lastcount4);
	120	logerror("read addr %08x, blah_r %08x - read count count %08x\n", m_channel[channel].m_srcoffset2, tempdata, m_channel[channel].m_decathlt_lastcount4);
120	121	#endif
121	122
122	123	return tempdata;
123	124	#if 0
124	125	case 0x03228e4:
125		if (fake0) retvalue = fake0[(((0x20080/4)+m_decathlt_lastcount))];
126		m_decathlt_lastcount++;
	126	if (fake0) retvalue = fake0[(((0x20080/4)+m_channel[channel].m_decathlt_lastcount))];
	127	m_channel[channel].m_decathlt_lastcount++;
127	128	return retvalue;
128	129
129	130	case 0x00a9f3a:
130		if (fake0) retvalue = fake0[(((0x00000/4)+m_decathlt_lastcount))];
131		m_decathlt_lastcount++;
	131	if (fake0) retvalue = fake0[(((0x00000/4)+m_channel[channel].m_decathlt_lastcount))];
	132	m_channel[channel].m_decathlt_lastcount++;
132	133	return retvalue;
133	134
134	135	case 0x0213ab4:
135		if (fake0) retvalue = fake0[(((0x40000/4)+m_decathlt_lastcount))];
136		m_decathlt_lastcount++;
	136	if (fake0) retvalue = fake0[(((0x40000/4)+m_channel[channel].m_decathlt_lastcount))];
	137	m_channel[channel].m_decathlt_lastcount++;
137	138	return retvalue;
138	139
139	140	case 0x01efaf0:
140		if (fake0) retvalue = fake0[(((0x60000/4)+m_decathlt_lastcount))];
141		m_decathlt_lastcount++;
	141	if (fake0) retvalue = fake0[(((0x60000/4)+m_channel[channel].m_decathlt_lastcount))];
	142	m_channel[channel].m_decathlt_lastcount++;
142	143	return retvalue;
143	144
144	145	case 0x033f16c:
r253151	r253152
179	180	void sega_315_5838_comp_device::set_prot_addr(UINT32 data, UINT32 mem_mask, int channel)
180	181	{
181	182	// printf("set_prot_addr\n");
182		COMBINE_DATA(&m_srcoffset);
	183	COMBINE_DATA(&m_channel[channel].m_srcoffset);
183	184
184		//if (m_decathlt_part==0) logerror("%d, last read count was %06x\n",channel, m_decathlt_lastcount*4);
185		m_decathlt_lastcount = 0;
	185	//if (m_decathlt_part==0) logerror("%d, last read count was %06x\n",channel, m_channel[channel].m_decathlt_lastcount*4);
	186	m_channel[channel].m_decathlt_lastcount = 0;
186	187
187	188	if (mem_mask == 0x0000ffff)
188	189	{
189		printf("set source address to %08x (channel %d)\n", m_srcoffset, channel);
	190	printf("set source address to %08x (channel %d)\n", m_channel[channel].m_srcoffset, channel);
190	191	}
191	192
192	193
r253151	r253152
197	198	fclose(tempfile);
198	199
199	200	char filename[256];
200		sprintf(filename, "%d_compressed_%08x", channel, m_srcoffset * 2);
	201	sprintf(filename, "%d_compressed_%08x", channel, m_channel[channel].m_srcoffset * 2);
201	202	tempfile = fopen(filename, "w+b");
202	203
203	204	// the table and dictionary are uploaded repeatedly, usually before groups of data transfers but
204	205	// it's always the same tables (one pair for each channel)
205	206	{
206	207	FILE* fp;
207		sprintf(filename, "%d_compressed_table1~~_%08x~~", channel~~, m_srcoffset * 2~~);
	208	sprintf(filename, "%d_compressed_table1", channel);
208	209	fp = fopen(filename, "w+b");
209		fwrite(&m_decathlt_prottable1, 24, 2, fp);
	210	fwrite(&m_channel[channel].m_decathlt_prottable1, 24, 2, fp);
210	211	fclose(fp);
211	212	}
212	213
213	214	{
214	215	FILE* fp;
215		sprintf(filename, "%d_compressed_dictionary~~_%08x~~", channel~~, m_srcoffset * 2~~);
	216	sprintf(filename, "%d_compressed_dictionary", channel);
216	217	fp = fopen(filename, "w+b");
217		fwrite(&m_decathlt_dictionaryy, 128, 2, fp);
	218	fwrite(&m_channel[channel].m_decathlt_dictionary, 128, 2, fp);
218	219	fclose(fp);
219	220	}
220	221	}
r253151	r253152
227	228	if ((data == 0x8000) \|\| (data == 0x0000))
228	229	{
229	230	// logerror("changed to upload mode 1\n");
230		m_decathlt_prot_uploadmode = 1;
231		m_decathlt_prot_uploadoffset = 0;
	231	m_channel[channel].m_decathlt_prot_uploadmode = 1;
	232	m_channel[channel].m_decathlt_prot_uploadoffset = 0;
232	233	}
233	234	else if ((data == 0x8080) \|\| (data == 0x0080))
234	235	{
235		m_decathlt_prot_uploadmode = 2;
236		m_decathlt_prot_uploadoffset = 0;
	236	m_channel[channel].m_decathlt_prot_uploadmode = 2;
	237	m_channel[channel].m_decathlt_prot_uploadoffset = 0;
237	238	}
238	239	else
239	240	{
r253151	r253152
243	244
244	245	void sega_315_5838_comp_device::upload_table_data(UINT16 data, int channel)
245	246	{
246		if (m_decathlt_prot_uploadmode == 1)
	247	if (m_channel[channel].m_decathlt_prot_uploadmode == 1)
247	248	{
248		if (m_decathlt_prot_uploadoffset >= 24)
	249	if (m_channel[channel].m_decathlt_prot_uploadoffset >= 24)
249	250	{
250	251	fatalerror("upload mode 1 error, too big\n");
251	252	return;
252	253	}
253	254
254		//logerror("uploading table 1 %04x %04x\n",m_decathlt_prot_uploadoffset, data&0xffff);
255		m_decathlt_prottable1[m_decathlt_prot_uploadoffset] = data & 0xffff;
256		m_decathlt_prot_uploadoffset++;
	255	//logerror("uploading table 1 %04x %04x\n",m_channel[channel].m_decathlt_prot_uploadoffset, data&0xffff);
	256	m_channel[channel].m_decathlt_prottable1[m_channel[channel].m_decathlt_prot_uploadoffset] = data & 0xffff;
	257	m_channel[channel].m_decathlt_prot_uploadoffset++;
257	258	printf("unk table 1 %04x (channel %d)\n", data & 0xffff, channel);
258	259	}
259		else if (m_decathlt_prot_uploadmode == 2)
	260	else if (m_channel[channel].m_decathlt_prot_uploadmode == 2)
260	261	{
261		if (m_decathlt_prot_uploadoffset >= 128)
	262	if (m_channel[channel].m_decathlt_prot_uploadoffset >= 128)
262	263	{
263	264	fatalerror("upload mode 2 error, too big\n");
264	265	return;
265	266	}
266	267
267		//logerror("uploading table 2 %04x %04x\n",m_decathlt_prot_uploadoffset, data&0xffff);
268		m_decathlt_dictionaryy[m_decathlt_prot_uploadoffset] = data & 0xffff;
269		m_decathlt_prot_uploadoffset++;
	268	//logerror("uploading table 2 %04x %04x\n",m_channel[channel].m_decathlt_prot_uploadoffset, data&0xffff);
	269	m_channel[channel].m_decathlt_dictionary[m_channel[channel].m_decathlt_prot_uploadoffset] = data & 0xffff;
	270	m_channel[channel].m_decathlt_prot_uploadoffset++;
270	271	printf("dictionary %04x (channel %d)\n", data & 0xffff, channel);
271	272	}
272	273	}

trunk/src/mame/machine/315-5838_317-0229_comp.h
r253151	r253152
65	65	virtual void device_reset() override;
66	66
67	67	private:
68		UINT16 m_decathlt_prottable1[24];
69		UINT16 m_decathlt_dictionaryy[128];
70	68
71		UINT32 m_srcoffset;
72
73		UINT32 m_decathlt_lastcount;
74		UINT32 m_decathlt_prot_uploadmode;
75		UINT32 m_decathlt_prot_uploadoffset;
76
77
78	69	// Decathlete specific variables and functions (see machine/decathlt.c)
79	70	struct channel_type
80	71	{
	72	UINT32 m_srcoffset;
	73	UINT16 m_decathlt_prottable1[24];
	74	UINT16 m_decathlt_dictionary[128];
	75
	76	UINT32 m_decathlt_lastcount;
	77	UINT32 m_decathlt_prot_uploadmode;
	78	UINT32 m_decathlt_prot_uploadoffset;
81	79	sega_dec_read_delegate m_read_ch;
82	80
83	81	};

trunk/src/mame/machine/arkanoid.cpp
r253151	r253152
82	82	if ((m_tcr^data)&0x20)// check if TIN state changed
83	83	{
84	84	/* logerror("timer enable state changed!\n"); */
85		if (data&0x20) m_68705_timer->adjust(attotime::never, TIMER_68705_PRESCALER_EXPIRED);
86		else m_68705_timer->adjust(attotime::from_hz(((XTAL_12MHz/4)/4)/(1<<(data&0x7))), TIMER_68705_PRESCALER_EXPIRED);
	85	if (data&0x20) timer_set(attotime::never, TIMER_68705_PRESCALER_EXPIRED);
	86	else timer_set(attotime::from_hz(((XTAL_12MHz/4)/4)/(1<<(data&0x7))), TIMER_68705_PRESCALER_EXPIRED);
87	87	}
88	88	// prescaler check: if timer prescaler has changed, or the PSC bit is set, adjust the timer length for the prescaler expired timer, but only if the timer would be running
89	89	if ( (((m_tcr&0x07)!=(data&0x07))\|\|(data&0x08)) && ((data&0x20)==0) )
90	90	{
91	91	/* logerror("timer reset due to PSC or prescaler change!\n"); */
92		~~m_68705_~~timer~~->adju~~st(attotime::from_hz(((XTAL_12MHz/4)/4)/(1<<(data&0x7))), TIMER_68705_PRESCALER_EXPIRED);
	92	timer_set(attotime::from_hz(((XTAL_12MHz/4)/4)/(1<<(data&0x7))), TIMER_68705_PRESCALER_EXPIRED);
93	93	}
94	94	m_tcr = data;
95	95	// if int state is set, and TIM is unmasked, assert an interrupt. otherwise clear it.
r253151	r253152
120	120	m_mcu->set_input_line(M68705_INT_TIMER, ASSERT_LINE);
121	121	else
122	122	m_mcu->set_input_line(M68705_INT_TIMER, CLEAR_LINE);
123		~~m_68705_~~timer~~->adju~~st(attotime::from_hz(((XTAL_12MHz/4)/4)/(1<<(m_tcr&0x7))), TIMER_68705_PRESCALER_EXPIRED);
	123	timer_set(attotime::from_hz(((XTAL_12MHz/4)/4)/(1<<(m_tcr&0x7))), TIMER_68705_PRESCALER_EXPIRED);
124	124	}
125	125
126	126	READ8_MEMBER(arkanoid_state::arkanoid_68705_port_c_r)

trunk/src/mame/machine/pc9801_cd.cpp
r253151	r253152
1		// license:BSD-3-Clause
2		// copyright-holders:smf
3		#include "pc9801_cd.h"
4
5		// device type definition
6		const device_type PC9801_CD = &device_creator<pc9801_cd_device>;
7
8		pc9801_cd_device::pc9801_cd_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
9		atapi_cdrom_device(mconfig, PC9801_CD, "PC9801 CD-ROM Drive", tag, owner, clock, "pc9801_cd", __FILE__)
10		{
11		}
12
13		void pc9801_cd_device::fill_buffer()
14		{
15		atapi_hle_device::fill_buffer();
16		m_status \|= IDE_STATUS_DRDY \| IDE_STATUS_SERV;
17		}
18
19		void pc9801_cd_device::process_buffer()
20		{
21		atapi_hle_device::process_buffer();
22		m_status \|= IDE_STATUS_DRDY \| IDE_STATUS_SERV;
23		}
24
25		void pc9801_cd_device::process_command()
26		{
27		atapi_hle_device::process_command();
28		switch(m_command)
29		{
30		case IDE_COMMAND_CHECK_POWER_MODE:
31		m_status = IDE_STATUS_DRDY \| IDE_STATUS_SERV;
32		break;
33		}
34		}

trunk/src/mame/machine/pc9801_cd.h
r253151	r253152
1		// license:BSD-3-Clause
2		// copyright-holders:smf
3
4		#ifndef __PC9801_CD_H__
5		#define __PC9801_CD_H__
6
7		#include "machine/atapicdr.h"
8
9		class pc9801_cd_device : public atapi_cdrom_device
10		{
11		public:
12		pc9801_cd_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
13
14		protected:
15		virtual void fill_buffer() override;
16		virtual void process_command() override;
17		virtual void process_buffer() override;
18		};
19
20		// device type definition
21		extern const device_type PC9801_CD;
22
23		#endif

trunk/src/mame/machine/pc9801_kbd.cpp
r253151	r253152
257	257
258	258	m_keyb_tx = 0xff;
259	259	m_keyb_rx = 0;
260		m_key_avail = false;
261	260	}
262	261
263	262	//-------------------------------------------------
r253151	r253152
277	276	{
278	277	m_keyb_tx = i \| 0x80;
279	278	m_write_irq(ASSERT_LINE);
280		m_key_avail = true;
281	279	m_rx_buf[i] = 0;
282	280	return;
283	281	}
r253151	r253152
290	288	{
291	289	m_keyb_tx = i;
292	290	m_write_irq(ASSERT_LINE);
293		m_key_avail = true;
294	291	m_rx_buf[i] = 0;
295	292	return;
296	293	}
r253151	r253152
306	303	{
307	304	m_write_irq(CLEAR_LINE);
308	305	if(!offset)
309		{
310		m_key_avail = false;
311	306	return m_keyb_tx;
312		}
313		return 1 \| 4 \| (m_key_avail ? 2 : 0);
	307	return 1 \| 4 \| 2;
314	308	}
315	309
316	310	WRITE8_MEMBER( pc9801_kbd_device::tx_w )

trunk/src/mame/machine/pc9801_kbd.h
r253151	r253152
55	55	UINT8 m_rx_buf[0x80];
56	56	UINT8 m_keyb_tx;
57	57	UINT8 m_keyb_rx;
58		bool m_key_avail;
59	58	};
60	59
61	60

trunk/src/mame/mess.lst
r253151	r253152
2142	2142
2143	2143	// Fidelity
2144	2144	cc10
2145		cc7
2146	2145	vcc // VCC: Voice Chess Challenger (English)
2147	2146	vccg // * Spanish
2148	2147	vccfr // * German
r253151	r253152
2345	2344	snspellca
2346	2345	snspellcuk
2347	2346	snmath
2348		snmatha
2349	2347	snmathp
2350	2348	snread
2351	2349	lantutor

trunk/src/mame/video/chihiro.cpp
r253151	r253152
2549	2549	}
2550	2550	}
2551	2551
2552		UINT32 nv2a_renderer::render_triangle_culling(const rectangle &cliprect, render_delegate callback, int paramcount, const vertex_t &_v1, const vertex_t &_v2, const vertex_t &_v3)
2553		{
2554		float areax2;
2555
2556		if (backface_culling_enabled == false)
2557		return render_triangle(cliprect, callback, paramcount, _v1, _v2, _v3);
2558		if (backface_culling_culled == NV2A_GL_CULL_FACE::FRONT_AND_BACK)
2559		return 0;
2560		areax2 = _v1.x(_v2.y - _v3.y) + _v2.x(_v3.y - _v1.y) + _v3.x*(_v1.y - _v2.y);
2561		if (backface_culling_winding == NV2A_GL_FRONT_FACE::CCW)
2562		areax2 = -areax2;
2563		// if areax2 >= 0 then front faced else back faced
2564		if ((backface_culling_culled == NV2A_GL_CULL_FACE::FRONT) && (areax2 >= 0))
2565		return 0;
2566		if ((backface_culling_culled == NV2A_GL_CULL_FACE::BACK) && (areax2 < 0))
2567		return 0;
2568		return render_triangle(cliprect, callback, paramcount, _v1, _v2, _v3);
2569		}
2570
2571	2552	int nv2a_renderer::geforce_exec_method(address_space & space, UINT32 chanel, UINT32 subchannel, UINT32 method, UINT32 address, int &countlen)
2572	2553	{
2573	2554	UINT32 maddress;
r253151	r253152
2611	2592	for (n = 0; n <= count; n += 4) {
2612	2593	read_vertices_0x1810(space, vertex_software + vertex_first, n + offset, 4);
2613	2594	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 4);
2614		//render_polygon<4>(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy + vertex_first); // 4 rgba, 4 texture units 2 uv
2615		render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[vertex_first + 1], vertex_xy[vertex_first + 2]);
2616		render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[vertex_first + 2], vertex_xy[vertex_first + 3]);
	2595	render_polygon<4>(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy + vertex_first); // 4 rgba, 4 texture units 2 uv
2617	2596	vertex_first = (vertex_first + 4) & 1023;
2618	2597	vertex_count = vertex_count + 4;
2619	2598	wait();
r253151	r253152
2623	2602	for (n = 0; n <= count; n += 3) {
2624	2603	read_vertices_0x1810(space, vertex_software + vertex_first, n + offset, 3);
2625	2604	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 3);
2626		render_triangle~~_culling~~(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[(vertex_first + 1) & 1023], vertex_xy[(vertex_first + 2) & 1023]); // 4 rgba, 4 texture units 2 uv
	2605	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[(vertex_first + 1) & 1023], vertex_xy[(vertex_first + 2) & 1023]); // 4 rgba, 4 texture units 2 uv
2627	2606	vertex_first = (vertex_first + 3) & 1023;
2628	2607	vertex_count = vertex_count + 3;
2629	2608	wait();
r253151	r253152
2645	2624	for (n = 0; n <= count; n++) {
2646	2625	read_vertices_0x1810(space, vertex_software + vertex_first, offset + n, 1);
2647	2626	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 1);
2648		render_triangle~~_culling~~(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[1024], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
	2627	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[1024], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
2649	2628	vertex_first = (vertex_first + 1) & 1023;
2650	2629	vertex_count = vertex_count + 1;
2651	2630	wait();
r253151	r253152
2666	2645	read_vertices_0x1810(space, vertex_software + vertex_first, offset + n, 1);
2667	2646	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 1);
2668	2647	if ((vertex_count & 1) == 0)
2669		render_triangle~~_culling~~(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
	2648	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
2670	2649	else
2671		render_triangle~~_culling~~(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[vertex_first], vertex_xy[(vertex_first - 1) & 1023]);
	2650	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[vertex_first], vertex_xy[(vertex_first - 1) & 1023]);
2672	2651	vertex_first = (vertex_first + 1) & 1023;
2673	2652	vertex_count = vertex_count + 1;
2674	2653	wait();
r253151	r253152
2712	2691	address = address + c * 4;
2713	2692	countlen = countlen - c;
2714	2693	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 4);
2715		//render_polygon<4>(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy + vertex_first); // 4 rgba, 4 texture units 2 uv
2716		render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[vertex_first + 1], vertex_xy[vertex_first + 2]);
2717		render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[vertex_first + 2], vertex_xy[vertex_first + 3]);
	2694	render_polygon<4>(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy + vertex_first); // 4 rgba, 4 texture units 2 uv
2718	2695	vertex_first = (vertex_first + 4) & 1023;
2719	2696	vertex_count = vertex_count + 4;
2720	2697	wait();
r253151	r253152
2756	2733	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 1);
2757	2734	address = address + c * 4;
2758	2735	countlen = countlen - c;
2759		render_triangle~~_culling~~(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[1024], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
	2736	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[1024], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
2760	2737	vertex_first = (vertex_first + 1) & 1023;
2761	2738	vertex_count = vertex_count + 1;
2762	2739	wait();
r253151	r253152
2776	2753	address = address + c * 4;
2777	2754	countlen = countlen - c;
2778	2755	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 3);
2779		render_triangle~~_culling~~(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[(vertex_first + 1) & 1023], vertex_xy[(vertex_first + 2) & 1023]); // 4 rgba, 4 texture units 2 uv
	2756	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[(vertex_first + 1) & 1023], vertex_xy[(vertex_first + 2) & 1023]); // 4 rgba, 4 texture units 2 uv
2780	2757	vertex_first = (vertex_first + 3) & 1023;
2781	2758	vertex_count = vertex_count + 3;
2782	2759	wait();
r253151	r253152
2812	2789	countlen = countlen - c;
2813	2790	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 1);
2814	2791	if ((vertex_count & 1) == 0)
2815		render_triangle~~_culling~~(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
	2792	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
2816	2793	else
2817		render_triangle~~_culling~~(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[vertex_first], vertex_xy[(vertex_first - 1) & 1023]);
	2794	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[vertex_first], vertex_xy[(vertex_first - 1) & 1023]);
2818	2795	vertex_first = (vertex_first + 1) & 1023;
2819	2796	vertex_count = vertex_count + 1;
2820	2797	wait();
r253151	r253152
2872	2849	break;
2873	2850	}
2874	2851	address = address + c * 4;
2875		//render_polygon<4>(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy); // 4 rgba, 4 texture units 2 uv
2876		render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[vertex_first + 1], vertex_xy[vertex_first + 2]);
2877		render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[vertex_first + 2], vertex_xy[vertex_first + 3]);
	2852	render_polygon<4>(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy); // 4 rgba, 4 texture units 2 uv
2878	2853	vertex_first = (vertex_first + 4) & 1023;
2879	2854	vertex_count = vertex_count + 4;
2880	2855	wait();
r253151	r253152
2902	2877	return 0;
2903	2878	}
2904	2879	address = address + c * 4;
2905		render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[n & 3], vertex_xy[(n + 1) & 3], vertex_xy[(n + 2) & 3]);
2906		render_triangle_culling(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(n + 2) & 3], vertex_xy[(n + 1) & 3], vertex_xy[(n + 3) & 3]);
	2880	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[n & 3], vertex_xy[(n + 1) & 3], vertex_xy[(n + 2) & 3]);
	2881	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(n + 2) & 3], vertex_xy[(n + 1) & 3], vertex_xy[(n + 3) & 3]);
2907	2882	wait();
2908	2883	}
2909	2884	}
r253151	r253152
2939	2914	}
2940	2915	address = address + c * 4;
2941	2916	convert_vertices_poly(vertex_software + vertex_first, vertex_xy + vertex_first, 1);
2942		render_triangle~~_culling~~(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[1024], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
	2917	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[1024], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
2943	2918	vertex_first = (vertex_first + 1) & 1023;
2944	2919	vertex_count = vertex_count + 1;
2945	2920	wait();
r253151	r253152
2958	2933	break;
2959	2934	}
2960	2935	address = address + c * 4;
2961		render_triangle~~_culling~~(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[(vertex_first + 1) & 1023], vertex_xy[(vertex_first + 2) & 1023]); // 4 rgba, 4 texture units 2 uv
	2936	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[vertex_first], vertex_xy[(vertex_first + 1) & 1023], vertex_xy[(vertex_first + 2) & 1023]); // 4 rgba, 4 texture units 2 uv
2962	2937	vertex_first = (vertex_first + 3) & 1023;
2963	2938	vertex_count = vertex_count + 3;
2964	2939	wait();
r253151	r253152
2993	2968	}
2994	2969	address = address + c * 4;
2995	2970	if ((vertex_count & 1) == 0)
2996		render_triangle~~_culling~~(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
	2971	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[(vertex_first - 1) & 1023], vertex_xy[vertex_first]);
2997	2972	else
2998		render_triangle~~_culling~~(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[vertex_first], vertex_xy[(vertex_first - 1) & 1023]);
	2973	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, vertex_xy[(vertex_first - 2) & 1023], vertex_xy[vertex_first], vertex_xy[(vertex_first - 1) & 1023]);
2999	2974	vertex_first = (vertex_first + 1) & 1023;
3000	2975	vertex_count = vertex_count + 1;
3001	2976	wait();
r253151	r253152
3053	3028	}
3054	3029	if ((maddress == 0x1d6c) \|\| (maddress == 0x1d70) \|\| (maddress == 0x1a4))
3055	3030	countlen--;
3056		if (maddress == 0x0308) {
3057		backface_culling_enabled = data != 0 ? true : false;
3058		}
3059		if (maddress == 0x03a0) {
3060		backface_culling_winding = (NV2A_GL_FRONT_FACE)data;
3061		}
3062		if (maddress == 0x039c) {
3063		backface_culling_culled = (NV2A_GL_CULL_FACE)data;
3064		}
3065	3031	if (maddress == 0x019c) {
3066	3032	geforce_read_dma_object(data, dma_offset[0], dma_size[0]);
3067	3033	}

https://github.com/mamedev/mame/commit/b222e6257453b3ca77cee403535e6a5becf4d5ee

199869 Revisions