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r37121 Saturday 11th April, 2015 at 18:54:51 UTC by hap
undo the intrusive personal-style changes i did a while ago, make Sarayan feel home again =)

[src/mame/drivers]

namcos23.c

trunk/src/mame/drivers/namcos23.c

r245632	r245633
1590	1590	{
1591	1591	if(id == 0x8000)
1592	1592	return m_light_vector;
1593		if(id >= 0x100)
1594		{
	1593	if(id >= 0x100) {
1595	1594	memset(m_spv, 0, sizeof(m_spv));
1596	1595	return m_spv;
1597	1596	}
r245632	r245633
1600	1599
1601	1600	INT16 *namcos23_state::c435_getm(UINT16 id)
1602	1601	{
1603		if(id >= 0x100)
1604		{
	1602	if(id >= 0x100) {
1605	1603	memset(m_spm, 0, sizeof(m_spm));
1606	1604	return m_spm;
1607	1605	}
r245632	r245633
1610	1608
1611	1609	void namcos23_state::c435_matrix_matrix_mul() // 0.0
1612	1610	{
1613		if((m_c435_buffer[0] & 0xf) != 4)
1614		{
	1611	if((m_c435_buffer[0] & 0xf) != 4) {
1615	1612	logerror("WARNING: c435_matrix_matrix_mul with size %d\n", m_c435_buffer[0] & 0xf);
1616	1613	return;
1617	1614	}
r245632	r245633
1635	1632
1636	1633	void namcos23_state::c435_matrix_vector_mul() // 0.1
1637	1634	{
1638		if((m_c435_buffer[0] & 0xf) != 4)
1639		{
	1635	if((m_c435_buffer[0] & 0xf) != 4) {
1640	1636	logerror("WARNING: c435_matrix_vector_mul with size %d\n", m_c435_buffer[0] & 0xf);
1641	1637	return;
1642	1638	}
r245632	r245633
1664	1660
1665	1661	void namcos23_state::c435_matrix_set() // 0.4
1666	1662	{
1667		if((m_c435_buffer[0] & 0xf) != 10)
1668		{
	1663	if((m_c435_buffer[0] & 0xf) != 10) {
1669	1664	logerror("WARNING: c435_matrix_set with size %d\n", m_c435_buffer[0] & 0xf);
1670	1665	return;
1671	1666	}
r245632	r245633
1676	1671
1677	1672	void namcos23_state::c435_vector_set() // 0.5
1678	1673	{
1679		if((m_c435_buffer[0] & 0xf) != 7)
1680		{
	1674	if((m_c435_buffer[0] & 0xf) != 7) {
1681	1675	logerror("WARNING: c435_vector_set with size %d\n", m_c435_buffer[0] & 0xf);
1682	1676	return;
1683	1677	}
r245632	r245633
1688	1682
1689	1683	void namcos23_state::c435_scaling_set() // 4.4
1690	1684	{
1691		if((m_c435_buffer[0] & 0xff) != 1)
1692		{
	1685	if((m_c435_buffer[0] & 0xff) != 1) {
1693	1686	logerror("WARNING: c435_scaling_set with size %d\n", m_c435_buffer[0] & 0xff);
1694	1687	return;
1695	1688	}
r245632	r245633
1698	1691
1699	1692	void namcos23_state::c435_state_set_interrupt() // 4.f.0001
1700	1693	{
1701		if(m_c435_buffer[0] != 0x4f02)
1702		{
	1694	if(m_c435_buffer[0] != 0x4f02) {
1703	1695	logerror("WARNING: c435_state_set_interrupt with size %d\n", m_c435_buffer[0] & 0xff);
1704	1696	return;
1705	1697	}
r245632	r245633
1711	1703
1712	1704	void namcos23_state::c435_state_set() // 4.f
1713	1705	{
1714		if((m_c435_buffer[0] & 0xff) == 0)
1715		{
	1706	if((m_c435_buffer[0] & 0xff) == 0) {
1716	1707	logerror("WARNING: c435_state_set with size %d\n", m_c435_buffer[0] & 0xff);
1717	1708	return;
1718	1709	}
r245632	r245633
1726	1717
1727	1718	void namcos23_state::c435_render() // 8
1728	1719	{
1729		if((m_c435_buffer[0] & 0xf) != 3)
1730		{
	1720	if((m_c435_buffer[0] & 0xf) != 3) {
1731	1721	logerror("WARNING: c435_render with size %d, header %04x", m_c435_buffer[0] & 0xf, m_c435_buffer[0]);
1732	1722	return;
1733	1723	}
r245632	r245633
1737	1727
1738	1728	logerror("render model %x %swith matrix %x and vector %x\n", m_c435_buffer[1], use_scaling ? "scaled " : "", m_c435_buffer[2], m_c435_buffer[3]);
1739	1729
1740		if(render.count[render.cur] >= RENDER_MAX_ENTRIES)
1741		{
	1730	if(render.count[render.cur] >= RENDER_MAX_ENTRIES) {
1742	1731	logerror("WARNING: render buffer full\n");
1743	1732	return;
1744	1733	}
r245632	r245633
1766	1755
1767	1756	void namcos23_state::c435_flush() // c
1768	1757	{
1769		if((m_c435_buffer[0] & 0xf) != 0)
1770		{
	1758	if((m_c435_buffer[0] & 0xf) != 0) {
1771	1759	logerror("WARNING: c435_flush with size %d\n", m_c435_buffer[0] & 0xf);
1772	1760	return;
1773	1761	}
r245632	r245633
1835	1823
1836	1824	READ32_MEMBER(namcos23_state::c435_r)
1837	1825	{
1838		switch (offset)
1839		{
1840		case 0xa:
1841		return 1; // Busy flag
	1826	switch(offset) {
	1827	case 0xa:
	1828	return 1; // Busy flag
1842	1829	}
1843	1830
1844	1831	logerror("c435_r %02x @ %08x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
r245632	r245633
1847	1834
1848	1835	WRITE32_MEMBER(namcos23_state::c435_w)
1849	1836	{
1850		switch (offset)
1851		{
1852		case 0x7:
1853		COMBINE_DATA(&m_c435_address);
1854		break;
1855		case 0x8:
1856		COMBINE_DATA(&m_c435_size);
1857		break;
1858		case 0x9:
1859		if (data & 1)
1860		c435_dma(space, m_c435_address, m_c435_size);
1861		break;
1862		default:
1863		logerror("c435_w %02x, %08x @ %08x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
1864		break;
	1837	switch(offset) {
	1838	case 0x7:
	1839	COMBINE_DATA(&m_c435_address);
	1840	break;
	1841	case 0x8:
	1842	COMBINE_DATA(&m_c435_size);
	1843	break;
	1844	case 0x9:
	1845	if(data & 1)
	1846	c435_dma(space, m_c435_address, m_c435_size);
	1847	break;
	1848	default:
	1849	logerror("c435_w %02x, %08x @ %08x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	1850	break;
1865	1851	}
1866	1852	}
1867	1853
r245632	r245633
1883	1869	bitmap_rgb32 *bitmap = (bitmap_rgb32 *)dest;
1884	1870	UINT32 *img = &bitmap->pix32(scanline, extent->startx);
1885	1871
1886		for(int x = extent->startx; x < extent->stopx; x++)
1887		{
	1872	for(int x = extent->startx; x < extent->stopx; x++) {
1888	1873	float z = w ? 1/w : 0;
1889	1874	UINT32 pcol = rd->texture_lookup(*rd->machine, rd->pens, u*z, v*z);
1890	1875	float ll = l*z;
r245632	r245633
1948	1933	{
1949	1934	render_t &render = m_render;
1950	1935	UINT32 adr = m_ptrom[re->model.model];
1951		if(adr >= m_ptrom_limit)
1952		{
	1936	if(adr >= m_ptrom_limit) {
1953	1937	logerror("WARNING: model %04x base address %08x out-of-bounds - pointram?\n", re->model.model, adr);
1954	1938	return;
1955	1939	}
1956	1940
1957		while(adr < m_ptrom_limit)
1958		{
	1941	while(adr < m_ptrom_limit) {
1959	1942	poly_vertex pv[15];
1960	1943
1961	1944	UINT32 type = m_ptrom[adr++];
r245632	r245633
1973	1956	UINT32 light = 0;
1974	1957	UINT32 extptr = 0;
1975	1958
1976		if(lmode == 3)
1977		{
	1959	if(lmode == 3) {
1978	1960	extptr = adr;
1979	1961	adr += ne;
1980	1962	}
r245632	r245633
1984	1966	float minz = FLT_MAX;
1985	1967	float maxz = FLT_MIN;
1986	1968
1987		for(int i=0; i<ne; i++)
1988		{
	1969	for(int i=0; i<ne; i++) {
1989	1970	UINT32 v1 = m_ptrom[adr++];
1990	1971	UINT32 v2 = m_ptrom[adr++];
1991	1972	UINT32 v3 = m_ptrom[adr++];
r245632	r245633
1999	1980	if(pv[i].p[0] < minz)
2000	1981	minz = pv[i].p[0];
2001	1982
2002		switch(lmode)
2003		{
	1983	switch(lmode) {
2004	1984	case 0:
2005	1985	pv[i].p[3] = ((light >> (8*(3-i))) & 0xff) / 64.0;
2006	1986	break;
r245632	r245633
2010	1990	case 2:
2011	1991	pv[i].p[3] = 1.0;
2012	1992	break;
2013		case 3:
2014		{
	1993	case 3: {
2015	1994	UINT32 norm = m_ptrom[extptr++];
2016	1995	INT32 nx = u32_to_s10(norm >> 20);
2017	1996	INT32 ny = u32_to_s10(norm >> 10);
r245632	r245633
2033	2012
2034	2013	p->vertex_count = poly_zclip_if_less(ne, pv, p->pv, 4, 0.001f);
2035	2014
2036		if(p->vertex_count >= 3)
2037		{
2038		for(int i=0; i<p->vertex_count; i++)
2039		{
	2015	if(p->vertex_count >= 3) {
	2016	for(int i=0; i<p->vertex_count; i++) {
2040	2017	render_project(p->pv[i]);
2041	2018	float w = p->pv[i].p[0];
2042	2019	p->pv[i].p[1] *= w;
r245632	r245633
2081	2058
2082	2059	const static rectangle scissor(0, 639, 0, 479);
2083	2060
2084		for(int i=0; i<render.poly_count; i++)
2085		{
	2061	for(int i=0; i<render.poly_count; i++) {
2086	2062	const namcos23_poly_entry *p = render.poly_order[i];
2087	2063	namcos23_render_data *rd = (namcos23_render_data *)poly_get_extra_data(render.polymgr);
2088	2064	*rd = p->rd;
r245632	r245633
2097	2073	const namcos23_render_entry *re = render.entries[!render.cur];
2098	2074
2099	2075	render.poly_count = 0;
2100		for(int i=0; i<render.count[!render.cur]; i++)
2101		{
2102		switch(re->type)
2103		{
	2076	for(int i=0; i<render.count[!render.cur]; i++) {
	2077	switch(re->type) {
2104	2078	case MODEL:
2105	2079	render_one_model(re);
2106	2080	break;
r245632	r245633
2137	2111	COMBINE_DATA(&m_generic_paletteram_32[offset]);
2138	2112
2139	2113	// each LONGWORD is 2 colors, each OFFSET is 2 colors
2140		for (int i = 0; i < 2; i++)
2141		{
	2114	for(int i = 0; i < 2; i++) {
2142	2115	int which = (offset << 2 | i << 1) & 0xfffe;
2143	2116	int r = nthbyte(m_generic_paletteram_32, which|0x00001);
2144	2117	int g = nthbyte(m_generic_paletteram_32, which|0x10001);
r245632	r245633
2197	2170	render_run(bitmap);
2198	2171
2199	2172	m_bgtilemap->set_palette_offset(m_c404.palbase);
2200		if (m_c404.layer & 4)
	2173	if(m_c404.layer & 4)
2201	2174	m_bgtilemap->draw(screen, bitmap, cliprect, 0, 0);
2202	2175
2203	2176	m_vblank_count++;
r245632	r245633
2224	2197	m_main_irqcause = cause;
2225	2198
2226	2199	// level 2: vblank
2227		if (changed & MAIN_VBLANK_IRQ)
	2200	if(changed & MAIN_VBLANK_IRQ)
2228	2201	m_maincpu->set_input_line(MIPS3_IRQ0, (cause & MAIN_VBLANK_IRQ) ? ASSERT_LINE : CLEAR_LINE);
2229	2202
2230	2203	// level 3: C361/subcpu
2231		if (changed & (MAIN_C361_IRQ | MAIN_SUBCPU_IRQ))
	2204	if(changed & (MAIN_C361_IRQ | MAIN_SUBCPU_IRQ))
2232	2205	m_maincpu->set_input_line(MIPS3_IRQ1, (cause & (MAIN_C361_IRQ | MAIN_SUBCPU_IRQ)) ? ASSERT_LINE : CLEAR_LINE);
2233	2206
2234	2207	// level 4: C435
2235		if (changed & MAIN_C435_IRQ)
	2208	if(changed & MAIN_C435_IRQ)
2236	2209	m_maincpu->set_input_line(MIPS3_IRQ2, (cause & MAIN_C435_IRQ) ? ASSERT_LINE : CLEAR_LINE);
2237	2210
2238	2211	// level 5: C422
2239		if (changed & MAIN_C422_IRQ)
	2212	if(changed & MAIN_C422_IRQ)
2240	2213	m_maincpu->set_input_line(MIPS3_IRQ3, (cause & MAIN_C422_IRQ) ? ASSERT_LINE : CLEAR_LINE);
2241	2214
2242	2215	// crszone(sys23ev2) has a different configuration, are they hardwired or configured by software? (where?)..
r245632	r245633
2248	2221
2249	2222	INTERRUPT_GEN_MEMBER(namcos23_state::interrupt)
2250	2223	{
2251		if (!m_ctl_vbl_active)
2252		{
	2224	if(!m_ctl_vbl_active) {
2253	2225	m_ctl_vbl_active = true;
2254	2226	update_main_interrupts(m_main_irqcause | MAIN_VBLANK_IRQ);
2255	2227	}
r245632	r245633
2270	2242
2271	2243	READ16_MEMBER(namcos23_state::c417_r)
2272	2244	{
2273		switch (offset)
2274		{
2275		/* According to timecrs2v4a, +0 is the status word with bits being:
2276		15: test mode flag (huh?)
2277		10: fifo data ready
2278		9:  cmd ram data ready
2279		8:  matrix busy
2280		7:  output unit busy (inverted)
2281		6:  hokan/tenso unit busy
2282		5:  point unit busy
2283		4:  access unit busy
2284		3:  c403 busy, called c444 in 500gp (inverted)
2285		2:  2nd c435 busy (inverted)
2286		1:  1st c435 busy (inverted)
2287		0:  xcpreq
2288		*/
2289		case 0:
2290		return 0x8e | (m_screen->vblank() ? 0x0000 : 0x8000);
2291		case 1:
2292		return m_c417.adr;
2293		case 4:
2294		//logerror("c417_r %04x = %04x (%08x, %08x)\n", c417.adr, c417.ram[c417.adr], space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
2295		return m_c417.ram[m_c417.adr];
2296		case 5:
2297		if (m_c417.pointrom_adr >= m_ptrom_limit)
2298		return 0xffff;
2299		return m_ptrom[m_c417.pointrom_adr] >> 16;
2300		case 6:
2301		if (m_c417.pointrom_adr >= m_ptrom_limit)
2302		return 0xffff;
2303		return m_ptrom[m_c417.pointrom_adr];
	2245	switch(offset) {
	2246	/* According to timecrs2v4a, +0 is the status word with bits being:
	2247	15: test mode flag (huh?)
	2248	10: fifo data ready
	2249	9:  cmd ram data ready
	2250	8:  matrix busy
	2251	7:  output unit busy (inverted)
	2252	6:  hokan/tenso unit busy
	2253	5:  point unit busy
	2254	4:  access unit busy
	2255	3:  c403 busy, called c444 in 500gp (inverted)
	2256	2:  2nd c435 busy (inverted)
	2257	1:  1st c435 busy (inverted)
	2258	0:  xcpreq
	2259	*/
	2260	case 0:
	2261	return 0x8e | (m_screen->vblank() ? 0x0000 : 0x8000);
	2262	case 1:
	2263	return m_c417.adr;
	2264	case 4:
	2265	//logerror("c417_r %04x = %04x (%08x, %08x)\n", c417.adr, c417.ram[c417.adr], space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2266	return m_c417.ram[m_c417.adr];
	2267	case 5:
	2268	if(m_c417.pointrom_adr >= m_ptrom_limit)
	2269	return 0xffff;
	2270	return m_ptrom[m_c417.pointrom_adr] >> 16;
	2271	case 6:
	2272	if(m_c417.pointrom_adr >= m_ptrom_limit)
	2273	return 0xffff;
	2274	return m_ptrom[m_c417.pointrom_adr];
2304	2275	}
2305	2276
2306	2277	logerror("c417_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
r245632	r245633
2309	2280
2310	2281	WRITE16_MEMBER(namcos23_state::c417_w)
2311	2282	{
2312		switch (offset)
2313		{
2314		case 0:
2315		c435_pio_w(data);
2316		break;
2317		case 1:
2318		COMBINE_DATA(&m_c417.adr);
2319		break;
2320		case 2:
2321		m_c417.pointrom_adr = (m_c417.pointrom_adr << 16) | data;
2322		break;
2323		case 3:
2324		m_c417.pointrom_adr = 0;
2325		break;
2326		case 4:
2327		//logerror("c417_w %04x = %04x (%08x, %08x)\n", m_c417.adr, data, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
2328		COMBINE_DATA(m_c417.ram + m_c417.adr);
2329		break;
2330		case 7:
2331		logerror("c417_w: ack IRQ 2 (%x)\n", data);
2332		update_main_interrupts(m_main_irqcause & ~MAIN_C435_IRQ);
2333		break;
2334		default:
2335		logerror("c417_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
2336		break;
	2283	switch(offset) {
	2284	case 0:
	2285	c435_pio_w(data);
	2286	break;
	2287	case 1:
	2288	COMBINE_DATA(&m_c417.adr);
	2289	break;
	2290	case 2:
	2291	m_c417.pointrom_adr = (m_c417.pointrom_adr << 16) | data;
	2292	break;
	2293	case 3:
	2294	m_c417.pointrom_adr = 0;
	2295	break;
	2296	case 4:
	2297	//logerror("c417_w %04x = %04x (%08x, %08x)\n", m_c417.adr, data, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2298	COMBINE_DATA(m_c417.ram + m_c417.adr);
	2299	break;
	2300	case 7:
	2301	logerror("c417_w: ack IRQ 2 (%x)\n", data);
	2302	update_main_interrupts(m_main_irqcause & ~MAIN_C435_IRQ);
	2303	break;
	2304	default:
	2305	logerror("c417_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2306	break;
2337	2307	}
2338	2308	}
2339	2309
r245632	r245633
2371	2341
2372	2342	READ16_MEMBER(namcos23_state::c412_r)
2373	2343	{
2374		switch (offset)
2375		{
2376		case 0x3:
2377		return 0x0002; // 0001 = busy, 0002 = game uploads things
2378		case 0x8:
2379		return m_c412.adr;
2380		case 0x9:
2381		return m_c412.adr >> 16;
2382		case 0xa:
2383		return c412_ram_r(space, m_c412.adr, mem_mask);
2384		case 0xc:
2385		// unknown status, 500gp reads it and waits for a transition
2386		// no other games use it?
2387		m_c412.status_c ^= 1;
2388		return m_c412.status_c;
	2344	switch(offset) {
	2345	case 0x3:
	2346	return 0x0002; // 0001 = busy, 0002 = game uploads things
	2347	case 0x8:
	2348	return m_c412.adr;
	2349	case 0x9:
	2350	return m_c412.adr >> 16;
	2351	case 0xa:
	2352	return c412_ram_r(space, m_c412.adr, mem_mask);
	2353	case 0xc:
	2354	// unknown status, 500gp reads it and waits for a transition
	2355	// no other games use it?
	2356	m_c412.status_c ^= 1;
	2357	return m_c412.status_c;
2389	2358	}
2390	2359
2391	2360	logerror("c412_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
r245632	r245633
2394	2363
2395	2364	WRITE16_MEMBER(namcos23_state::c412_w)
2396	2365	{
2397		switch (offset)
2398		{
2399		case 0x2:
2400		// d0: cz on
2401		// other bits: no function?
2402		break;
2403		case 0x8:
2404		m_c412.adr = (data & mem_mask) | (m_c412.adr & (0xffffffff ^ mem_mask));
2405		break;
2406		case 0x9:
2407		m_c412.adr = ((data & mem_mask) << 16) | (m_c412.adr & (0xffffffff ^ (mem_mask << 16)));
2408		break;
2409		case 0xa:
2410		c412_ram_w(space, m_c412.adr, data, mem_mask);
2411		m_c412.adr += 2;
2412		break;
2413		default:
2414		logerror("c412_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
2415		break;
	2366	switch(offset) {
	2367	case 0x2:
	2368	// d0: cz on
	2369	// other bits: no function?
	2370	break;
	2371	case 0x8:
	2372	m_c412.adr = (data & mem_mask) | (m_c412.adr & (0xffffffff ^ mem_mask));
	2373	break;
	2374	case 0x9:
	2375	m_c412.adr = ((data & mem_mask) << 16) | (m_c412.adr & (0xffffffff ^ (mem_mask << 16)));
	2376	break;
	2377	case 0xa:
	2378	c412_ram_w(space, m_c412.adr, data, mem_mask);
	2379	m_c412.adr += 2;
	2380	break;
	2381	default:
	2382	logerror("c412_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2383	break;
2416	2384	}
2417	2385	}
2418	2386
r245632	r245633
2446	2414
2447	2415	READ16_MEMBER(namcos23_state::c421_r)
2448	2416	{
2449		switch (offset)
2450		{
2451		case 0:
2452		return c421_ram_r(space, m_c421.adr & 0xfffff, mem_mask);
	2417	switch(offset) {
	2418	case 0:
	2419	return c421_ram_r(space, m_c421.adr & 0xfffff, mem_mask);
2453	2420
2454		case 2:
2455		return m_c421.adr >> 16;
2456		case 3:
2457		return m_c421.adr;
	2421	case 2:
	2422	return m_c421.adr >> 16;
	2423	case 3:
	2424	return m_c421.adr;
2458	2425	}
2459	2426
2460	2427	logerror("c421_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
r245632	r245633
2463	2430
2464	2431	WRITE16_MEMBER(namcos23_state::c421_w)
2465	2432	{
2466		switch (offset)
2467		{
2468		case 0:
2469		c421_ram_w(space, m_c421.adr & 0xfffff, data, mem_mask);
2470		m_c421.adr += 2;
2471		break;
2472		case 2:
2473		m_c421.adr = ((data & mem_mask) << 16) | (m_c421.adr & (0xffffffff ^ (mem_mask << 16)));
2474		break;
2475		case 3:
2476		m_c421.adr = (data & mem_mask) | (m_c421.adr & (0xffffffff ^ mem_mask));
2477		break;
2478		default:
2479		logerror("c421_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
2480		break;
	2433	switch(offset) {
	2434	case 0:
	2435	c421_ram_w(space, m_c421.adr & 0xfffff, data, mem_mask);
	2436	m_c421.adr += 2;
	2437	break;
	2438	case 2:
	2439	m_c421.adr = ((data & mem_mask) << 16) | (m_c421.adr & (0xffffffff ^ (mem_mask << 16)));
	2440	break;
	2441	case 3:
	2442	m_c421.adr = (data & mem_mask) | (m_c421.adr & (0xffffffff ^ mem_mask));
	2443	break;
	2444	default:
	2445	logerror("c421_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2446	break;
2481	2447	}
2482	2448	}
2483	2449
r245632	r245633
2492	2458
2493	2459	WRITE16_MEMBER(namcos23_state::c422_w)
2494	2460	{
2495		switch (offset)
2496		{
2497		case 1:
2498		if (data == 0xfffb)
2499		{
2500		logerror("c422_w: raise IRQ 3\n");
2501		update_main_interrupts(m_main_irqcause | MAIN_C422_IRQ);
2502		}
2503		else if (data == 0x000f)
2504		{
2505		logerror("c422_w: ack IRQ 3\n");
2506		update_main_interrupts(m_main_irqcause & ~MAIN_C422_IRQ);
2507		}
2508		break;
	2461	switch(offset) {
	2462	case 1:
	2463	if(data == 0xfffb) {
	2464	logerror("c422_w: raise IRQ 3\n");
	2465	update_main_interrupts(m_main_irqcause | MAIN_C422_IRQ);
	2466	}
	2467	else if(data == 0x000f) {
	2468	logerror("c422_w: ack IRQ 3\n");
	2469	update_main_interrupts(m_main_irqcause & ~MAIN_C422_IRQ);
	2470	}
	2471	break;
2509	2472
2510		default:
2511		logerror("c422_w: %04x @ %x\n", data, offset);
2512		break;
	2473	default:
	2474	logerror("c422_w: %04x @ %x\n", data, offset);
	2475	break;
2513	2476	}
2514	2477
2515	2478	COMBINE_DATA(&m_c422.regs[offset]);
r245632	r245633
2521	2484
2522	2485	TIMER_CALLBACK_MEMBER(namcos23_state::c361_timer_cb)
2523	2486	{
2524		if (m_c361.scanline != 0x1ff)
2525		{
	2487	if(m_c361.scanline != 0x1ff) {
2526	2488	// need to do a partial update here, but doesn't work properly yet
2527	2489	//m_screen->update_partial(m_screen->vpos());
2528	2490	update_main_interrupts(m_main_irqcause | MAIN_C361_IRQ);
r245632	r245633
2536	2498
2537	2499	WRITE16_MEMBER(namcos23_state::c361_w)
2538	2500	{
2539		switch (offset)
2540		{
2541		case 0:
2542		m_bgtilemap->set_scrollx(0, data&0xfff);
2543		break;
	2501	switch(offset) {
	2502	case 0:
	2503	m_bgtilemap->set_scrollx(0, data&0xfff);
	2504	break;
2544	2505
2545		case 1:
2546		m_bgtilemap->set_scrolly(0, data&0xfff);
2547		break;
	2506	case 1:
	2507	m_bgtilemap->set_scrolly(0, data&0xfff);
	2508	break;
2548	2509
2549		case 4: // interrupt control
2550		m_c361.scanline = data & 0x1ff;
2551		m_c361.timer->adjust(m_screen->time_until_pos(m_c361.scanline));
2552		break;
	2510	case 4: // interrupt control
	2511	m_c361.scanline = data & 0x1ff;
	2512	m_c361.timer->adjust(m_screen->time_until_pos(m_c361.scanline));
	2513	break;
2553	2514
2554		default:
2555		logerror("c361_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
2556		break;
	2515	default:
	2516	logerror("c361_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2517	break;
2557	2518	}
2558	2519	}
2559	2520
2560	2521	READ16_MEMBER(namcos23_state::c361_r)
2561	2522	{
2562		switch (offset)
2563		{
2564		// current raster position
2565		// how does it work exactly? it's not understood in namcos22 either (also has a c361)
2566		case 5:
2567		update_main_interrupts(m_main_irqcause & ~MAIN_C361_IRQ);
2568		return (m_screen->vpos()*2) | (m_screen->vblank() ? 1 : 0);
2569		case 6:
2570		update_main_interrupts(m_main_irqcause & ~MAIN_C361_IRQ);
2571		return m_screen->vblank() ? 1 : 0;
	2523	switch(offset) {
	2524	// current raster position
	2525	// how does it work exactly? it's not understood in namcos22 either (also has a c361)
	2526	case 5:
	2527	update_main_interrupts(m_main_irqcause & ~MAIN_C361_IRQ);
	2528	return (m_screen->vpos()*2) | (m_screen->vblank() ? 1 : 0);
	2529	case 6:
	2530	update_main_interrupts(m_main_irqcause & ~MAIN_C361_IRQ);
	2531	return m_screen->vblank() ? 1 : 0;
2572	2532	}
2573	2533
2574	2534	logerror("c361_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
r245632	r245633
2581	2541
2582	2542	WRITE16_MEMBER(namcos23_state::ctl_w)
2583	2543	{
2584		switch (offset)
2585		{
2586		case 0:
2587		if (m_ctl_led != (data & 0xff))
2588		{
2589		m_ctl_led = data & 0xff;
2590		for (int i = 0; i < 8; i++)
2591		output_set_lamp_value(i, (~data<<i & 0x80) ? 0 : 1);
2592		}
2593		break;
	2544	switch(offset) {
	2545	case 0:
	2546	if(m_ctl_led != (data & 0xff)) {
	2547	m_ctl_led = data & 0xff;
	2548	for(int i = 0; i < 8; i++)
	2549	output_set_lamp_value(i, (~data<<i & 0x80) ? 0 : 1);
	2550	}
	2551	break;
2594	2552
2595		case 2: case 3:
2596		// These may be coming from another CPU, in particular the I/O one
2597		m_ctl_inp_buffer[offset-2] = (offset == 2 ? m_p1 : m_p2)->read();
2598		break;
2599		case 5:
2600		if(m_ctl_vbl_active)
2601		{
2602		m_ctl_vbl_active = false;
2603		update_main_interrupts(m_main_irqcause & ~MAIN_VBLANK_IRQ);
2604		}
2605		break;
	2553	case 2: case 3:
	2554	// These may be coming from another CPU, in particular the I/O one
	2555	m_ctl_inp_buffer[offset-2] = (offset == 2 ? m_p1 : m_p2)->read();
	2556	break;
	2557	case 5:
	2558	if(m_ctl_vbl_active) {
	2559	m_ctl_vbl_active = false;
	2560	update_main_interrupts(m_main_irqcause & ~MAIN_VBLANK_IRQ);
	2561	}
	2562	break;
2606	2563
2607		case 6: // gmen wars spams this heavily with 0 prior to starting the GMEN board test
2608		if (data != 0)
2609		logerror("ctl_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
2610		break;
2611
2612		default:
	2564	case 6: // gmen wars spams this heavily with 0 prior to starting the GMEN board test
	2565	if(data != 0)
2613	2566	logerror("ctl_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
2614		break;
	2567	break;
	2568
	2569	default:
	2570	logerror("ctl_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
	2571	break;
2615	2572	}
2616	2573	}
2617	2574
2618	2575	READ16_MEMBER(namcos23_state::ctl_r)
2619	2576	{
2620		switch (offset)
2621		{
2622		// 0100 set freezes gorgon (polygon fifo flag)
2623		case 1:
2624		return 0x0000 | ioport("DSW")->read() | ((m_main_irqcause & MAIN_C361_IRQ) ? 0x400 : 0);
2625		case 2: case 3:
2626		{
2627		UINT16 res = m_ctl_inp_buffer[offset-2] & 0x800 ? 0xffff : 0x0000;
2628		m_ctl_inp_buffer[offset-2] = (m_ctl_inp_buffer[offset-2] << 1) | 1;
2629		return res;
2630		}
	2577	switch(offset) {
	2578	// 0100 set freezes gorgon (polygon fifo flag)
	2579	case 1:
	2580	return 0x0000 | ioport("DSW")->read() | ((m_main_irqcause & MAIN_C361_IRQ) ? 0x400 : 0);
	2581	case 2: case 3: {
	2582	UINT16 res = m_ctl_inp_buffer[offset-2] & 0x800 ? 0xffff : 0x0000;
	2583	m_ctl_inp_buffer[offset-2] = (m_ctl_inp_buffer[offset-2] << 1) | 1;
	2584	return res;
2631	2585	}
	2586	}
2632	2587
2633	2588	logerror("ctl_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
2634	2589	return 0xffff;
r245632	r245633
2640	2595
2641	2596	WRITE16_MEMBER(namcos23_state::mcuen_w)
2642	2597	{
2643		switch (offset)
2644		{
2645		case 2:
2646		// subcpu irq ack
2647		update_main_interrupts(m_main_irqcause & ~MAIN_SUBCPU_IRQ);
2648		break;
	2598	switch(offset) {
	2599	case 2:
	2600	// subcpu irq ack
	2601	update_main_interrupts(m_main_irqcause & ~MAIN_SUBCPU_IRQ);
	2602	break;
2649	2603
2650		case 5:
2651		// boot/start the audio mcu
2652		if (data)
2653		{
2654		logerror("mcuen_w: booting H8/3002\n");
	2604	case 5:
	2605	// boot/start the audio mcu
	2606	if(data) {
	2607	logerror("mcuen_w: booting H8/3002\n");
2655	2608
2656		// Panic Park: writing 1 when it's already running means reboot?
2657		if (m_subcpu_running)
2658		{
2659		m_subcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
2660		}
2661
2662		m_subcpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
2663		m_subcpu_running = true;
2664		}
2665		else
2666		{
2667		logerror("mcuen_w: stopping H8/3002\n");
	2609	// Panic Park: writing 1 when it's already running means reboot?
	2610	if(m_subcpu_running) {
2668	2611	m_subcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
2669		m_subcpu_running = false;
2670	2612	}
2671		break;
2672	2613
2673		default:
2674		logerror("mcuen_w: mask %04x, data %04x @ %x\n", mem_mask, data, offset);
2675		break;
	2614	m_subcpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
	2615	m_subcpu_running = true;
	2616	} else {
	2617	logerror("mcuen_w: stopping H8/3002\n");
	2618	m_subcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
	2619	m_subcpu_running = false;
	2620	}
	2621	break;
	2622
	2623	default:
	2624	logerror("mcuen_w: mask %04x, data %04x @ %x\n", mem_mask, data, offset);
	2625	break;
2676	2626	}
2677	2627	}
2678	2628
r245632	r245633
2798	2748	UINT16 *shared16 = reinterpret_cast<UINT16 *>(m_shared_ram.target());
2799	2749
2800	2750	// fake that an I/O board is connected for games w/o a dump or that aren't properly communicating with it yet
2801		if (!m_has_jvsio)
2802		{
2803		if ((offset == 0x4052/2) && (data == 0x78))
2804		{
	2751	if(!m_has_jvsio) {
	2752	if((offset == 0x4052/2) && (data == 0x78)) {
2805	2753	data = 0;
2806	2754	}
2807	2755	}
r245632	r245633
2819	2767
2820	2768	WRITE16_MEMBER(namcos23_state::sub_interrupt_main_w)
2821	2769	{
2822		if  ((mem_mask == 0xffff) && (data == 0x3170))
2823		{
	2770	if((mem_mask == 0xffff) && (data == 0x3170)) {
2824	2771	update_main_interrupts(m_main_irqcause | MAIN_SUBCPU_IRQ);
2825		}
2826		else
2827		{
	2772	} else {
2828	2773	logerror("Unknown write %x to sub_interrupt_main_w!\n", data);
2829	2774	}
2830	2775	}
r245632	r245633
2993	2938	UINT16 ypos = m_lighty->read();
2994	2939	// ypos is not completely understood yet, there should be a difference between case 1/4 and 2/5
2995	2940
2996		switch(offset)
2997		{
	2941	switch(offset) {
2998	2942	case 0: return xpos&0xff;
2999	2943	case 1: return ypos&0xff;
3000	2944	case 2: return ypos&0xff;
r245632	r245633
3265	3209	m_render.count[0] = m_render.count[1] = 0;
3266	3210	m_render.cur = 0;
3267	3211
3268		if ((!strcmp(machine().system().name, "motoxgo")) ||
	3212	if((!strcmp(machine().system().name, "motoxgo")) ||
3269	3213	(!strcmp(machine().system().name, "panicprk")) ||
3270	3214	(!strcmp(machine().system().name, "panicprkj")) ||
3271	3215	(!strcmp(machine().system().name, "rapidrvr")) ||
r245632	r245633
3285	3229	(!strcmp(machine().system().name, "crszonev3a")) ||
3286	3230	(!strcmp(machine().system().name, "crszonev2a")) ||
3287	3231	(!strcmp(machine().system().name, "timecrs2v2b")) ||
3288		(!strcmp(machine().system().name, "timecrs2")))
3289		{
	3232	(!strcmp(machine().system().name, "timecrs2"))) {
3290	3233	m_has_jvsio = 1;
3291		}
3292		else
3293		{
	3234	} else {
3294	3235	m_has_jvsio = 0;
3295	3236	}
3296	3237	}

https://github.com/mamedev/mame/commit/6feb9ac5cac5e352d9509783a55303b5482ff175

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