Previous

199869 Revisions

Next

r37122 Saturday 11th April, 2015 at 19:56:21 UTC by Ted Green
Update iteagle files

[src/emu/machine]	vrc4373.c vrc4373.h
[src/emu/sound]	es1373.c es1373.h
[src/emu/video]	voodoo_pci.c voodoo_pci.h
[src/mame]	mame.lst
[src/mame/drivers]	iteagle.c
[src/mame/machine]	iteagle_fpga.c iteagle_fpga.h

trunk/src/emu/machine/vrc4373.c

r245633	r245634
60	60	m_simm_size = 1<<21;
61	61	m_simm_base = 0;
62	62	regenerate_config_mapping();
	63
63	64	}
64	65
65	66	void vrc4373_device::device_reset()

trunk/src/emu/machine/vrc4373.h

r245633	r245634
120	120
121	121	UINT32 m_pci1_laddr, m_pci2_laddr, m_pci_io_laddr;
122	122	UINT32 m_target1_laddr, m_target2_laddr;
	123
123	124	};
124	125
125	126

trunk/src/emu/sound/es1373.c

r245633	r245634
1	1	#include "es1373.h"
2	2
3		#define LOG_ES            (1)
	3	#define LOG_ES            (0)
4	4	#define LOG_ES_REG        (0)
	5	#define LOG_ES_FILE         (0)
5	6
	7
6	8	static MACHINE_CONFIG_FRAGMENT( es1373 )
7		MCFG_TIMER_DRIVER_ADD_PERIODIC("sound_timer", es1373_device, es_timer_callback,  attotime::from_hz(44100/16384))
	9	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
8	10	MACHINE_CONFIG_END
9	11
10	12	machine_config_constructor es1373_device::device_mconfig_additions() const
r245633	r245634
20	22
21	23	es1373_device::es1373_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
22	24	: pci_device(mconfig, ES1373, "Creative Labs Ensoniq AudioPCI97 ES1373", tag, owner, clock, "es1373", __FILE__),
	25	device_sound_interface(mconfig, *this),
	26	m_eslog(NULL),
23	27	m_irq_num(-1)
24	28	{
25	29	}
r245633	r245634
30	34	m_irq_num = irq_num;
31	35	}
32	36
	37	//-------------------------------------------------
	38	//  device_stop - device-specific stop
	39	//-------------------------------------------------
	40	void es1373_device::device_stop()
	41	{
	42	/* debugging */
	43	if (LOG_ES_FILE && m_eslog)
	44	{
	45	fclose(m_eslog);
	46	m_eslog = NULL;
	47	}
	48	}
	49
	50	//-------------------------------------------------
	51	//  device_start - device-specific startup
	52	//-------------------------------------------------
33	53	void es1373_device::device_start()
34	54	{
35		//m_cpu = machine().device<cpu_device>(":maincpu");
36	55	m_cpu = machine().device<cpu_device>(m_cpu_tag);
37	56	pci_device::device_start();
38	57	add_map(0x40, M_IO, FUNC(es1373_device::map));
	58
	59	// create the stream
	60	m_stream = machine().sound().stream_alloc(*this, 0, 2, 44100/2);
	61
	62	m_timer = timer_alloc(0, NULL);
	63	m_timer->adjust(attotime::zero, 0, attotime::from_hz(44100/2/16));
	64
39	65	}
40	66
41	67	void es1373_device::device_reset()
42	68	{
	69	// debugging
	70	m_tempCount = 0;
	71	if (LOG_ES_FILE && m_eslog)
	72	{
	73	fclose(m_eslog);
	74	m_eslog = NULL;
	75	}
	76	if (LOG_ES_FILE && !m_eslog)
	77	m_eslog = fopen("es.log", "w");
	78
43	79	pci_device::device_reset();
44	80	memset(m_es_regs, 0, sizeof(m_es_regs));
45	81	memset(m_ac97_regs, 0, sizeof(m_ac97_regs));
46	82	m_ac97_regs[0] = 0x0800;
47	83	// Reset ADC channel info
	84	m_adc.number = 0;
48	85	m_adc.enable = false;
49		m_adc.int_en = false;
50		m_adc.loop_en = false;
51	86	m_adc.initialized = false;
52		m_adc.buf_count = 0;
53		m_adc.buf_size = 0;
54	87	m_adc.buf_rptr = 0x20;
55	88	m_adc.buf_wptr = 0x20;
56	89	// Reset DAC1 channel info
	90	m_dac1.number = 1;
57	91	m_dac1.enable = false;
58		m_dac1.int_en = false;
59		m_dac1.loop_en = false;
60	92	m_dac1.initialized = false;
61		m_dac1.buf_count = 0;
62		m_dac1.buf_size = 0;
63	93	m_dac1.buf_rptr = 0x0;
64	94	m_dac1.buf_wptr = 0x0;
65	95	// Reset DAC2 channel info
	96	m_dac2.number = 2;
66	97	m_dac2.enable = false;
67		m_dac2.int_en = false;
68		m_dac2.loop_en = false;
69	98	m_dac2.initialized = false;
70		m_dac2.buf_count = 0;
71		m_dac2.buf_size = 0;
72	99	m_dac2.buf_rptr = 0x10;
73		m_dac2.buf_wptr = 0x10;
	100	m_dac2.buf_wptr = 0x10;  // Start PCI writing to bottom half of buffer
	101
	102	m_stream->update();
74	103	}
75	104
76	105	void es1373_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
r245633	r245634
79	108	m_memory_space = memory_space;
80	109	}
81	110
82		TIMER_DEVICE_CALLBACK_MEMBER(es1373_device::es_timer_callback)
	111	//-------------------------------------------------
	112	//  device_timer - called when our device timer expires
	113	//-------------------------------------------------
	114	void es1373_device::device_timer(emu_timer &timer, device_timer_id tid, int param, void *ptr)
83	115	{
84		// Only transfer PCI data if bus mastering is enabled
85		if (command & 0x4) {
86		if (m_dac2.enable && (!(m_dac2.buf_rptr&0x7))) {
87		transfer_pci_audio(m_dac2, ES_PCI_READ);
88		}
89		if (m_dac2.pci_count>8) {
90		m_dac2.initialized = true;
91		}
	116	m_stream->update();
	117	}
	118
	119	//-------------------------------------------------
	120	//  sound_stream_update - handle update requests for
	121	//  our sound stream
	122	//-------------------------------------------------
	123	void es1373_device::sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples)
	124	{
	125
	126	if (m_dac1.enable) {
	127	logerror("%s: sound_stream_update DAC1 not implemented yet\n", tag());
92	128	}
	129
93	130	if (m_dac2.enable) {
94		// The initalized is to signal that inital buffer has been written
95		if (m_dac2.buf_count<=m_dac2.buf_size && m_dac2.initialized) {
96		// Send data to sound???
97		// sound = m_sound_cache[chan.buf_rptr]
98		if (0 && LOG_ES)
99		logerror("%X: DAC2 buf_count: %i buf_size: %X buf_rptr: %X buf_wptr: %X\n", machine().device("maincpu")->safe_pc(),
100		m_dac2.buf_count, m_dac2.buf_size, m_dac2.buf_rptr, m_dac2.buf_wptr);
101		if (m_dac2.buf_count==m_dac2.buf_size) {
102		if (m_dac2.int_en) {
103		m_es_regs[ES_INT_CS_STATUS] |= ICSTATUS_DAC2_INT_MASK;
	131	send_audio_out(m_dac2, ICSTATUS_DAC2_INT_MASK, outputs[0], outputs[1], samples);
	132	}
	133
	134	if (m_adc.enable) {
	135	if (m_adc.format!=SCTRL_16BIT_MONO) {
	136	logerror("%s: sound_stream_update Only SCTRL_16BIT_MONO recorded supported\n", tag());
	137	} else {
	138	for (int i=0; i<samples; i++) {
	139	if (m_adc.buf_count<=m_adc.buf_size) {
104	140	if (LOG_ES)
105		logerror("%X: es_timer_callback Setting DAC2 interrupt\n", machine().device("maincpu")->safe_pc());
	141	logerror("%s: ADC buf_count: %i buf_size: %i buf_rptr: %i buf_wptr: %i\n", machine().describe_context(),
	142	m_adc.buf_count, m_adc.buf_size, m_adc.buf_rptr, m_adc.buf_wptr);
	143	if ((m_adc.buf_count&0x1)) {
	144	m_adc.buf_wptr++;
	145	}
	146	m_adc.buf_count++;
	147	if (m_adc.buf_count>m_adc.buf_size) {
	148	if (m_adc.loop_en) {
	149	// Keep playing
	150	m_adc.buf_count = 0;
	151	if (LOG_ES)
	152	logerror("%X: send_audio_out ADC clearing buf_count\n", machine().device("maincpu")->safe_pc());
	153	}
	154	if (m_adc.int_en) {
	155	m_es_regs[ES_INT_CS_STATUS] |= ICSTATUS_ADC_INT_MASK;
	156	if (LOG_ES)
	157	logerror("%X: send_audio_out Setting ADC interrupt\n", machine().device("maincpu")->safe_pc());
	158	}
	159	}
	160	if (!(m_adc.buf_count&1) && !(m_adc.buf_wptr&0xf)) {
	161	m_adc.buf_wptr -= 0x10;
	162	}
	163	// PCI Write Transfer
	164	if (command & 0x4) {
	165	if ((m_adc.buf_rptr&8)^(m_adc.buf_wptr&8)) {
	166	transfer_pci_audio(m_adc, ES_PCI_WRITE);
	167	}
	168	}
106	169	}
107		if (m_dac2.loop_en) {
108		// Keep playing
109		m_dac2.buf_count = m_dac2.buf_count + 1 - 4;  // Should check SCTRL_P2_END_MASK
110		} else {
111		// Stop
112		//m_dac2.enable = false;
113		}
114		} else {
115		m_dac2.buf_count++;
116	170	}
117		m_dac2.buf_rptr++;
118		if (!(m_dac2.buf_rptr&0xf)) {
119		m_dac2.buf_rptr -= 0x10;
120		}
121	171	}
122	172	}
123		if (m_adc.enable) {
124		if (m_adc.buf_count<=m_adc.buf_size) {
125		if (LOG_ES)
126		logerror("%s: ADC buf_count: %i buf_size: %i buf_rptr: %i buf_wptr: %i\n", machine().describe_context(),
127		m_adc.buf_count, m_adc.buf_size, m_adc.buf_rptr, m_adc.buf_wptr);
128		if (m_adc.int_en && m_adc.buf_count==m_adc.buf_size) {
129		m_es_regs[ES_INT_CS_STATUS] |= ICSTATUS_ADC_INT_MASK;
130		if (LOG_ES)
131		logerror("%s: es_timer_callback Setting ADC interrupt\n", tag());
132		}
133		m_adc.buf_count++;
134		m_adc.buf_wptr++;
135		if (!(m_adc.buf_wptr&0xf)) {
136		m_adc.buf_wptr -= 0x10;
137		}
138		}
139		}
140		// PCI Write Transfer
141		if (command & 0x4) {
142		if (m_adc.enable && (!(m_adc.buf_wptr&0x7))) {
143		transfer_pci_audio(m_adc, ES_PCI_WRITE);
144		}
145		}
146	173	if (m_es_regs[ES_INT_CS_STATUS]&(ICSTATUS_DAC1_INT_MASK|ICSTATUS_DAC2_INT_MASK|ICSTATUS_ADC_INT_MASK)) {
147	174	m_es_regs[ES_INT_CS_STATUS] |= ICSTATUS_INTR_MASK;
148	175	// Assert interrupt
r245633	r245634
153	180	}
154	181	}
155	182
	183	//-------------------------------------------------
	184	//  send_audio_out - Sends channel audio output data
	185	//-------------------------------------------------
	186	void es1373_device::send_audio_out(chan_info& chan, UINT32 intr_mask, stream_sample_t *outL, stream_sample_t *outR, int samples)
	187	{
	188	// Only transfer PCI data if bus mastering is enabled
	189	// Fill initial half buffer
	190	if (1 && (command & 0x4) && (!chan.initialized)) {
	191	chan.initialized = true;
	192	transfer_pci_audio(chan, ES_PCI_READ);
	193	}
	194	//UINT32 sample_size = calc_size(chan.format);
	195	// Send data to sound stream
	196	bool buf_row_done;
	197	for (int i=0; i<samples; i++) {
	198	buf_row_done = false;
	199	if (chan.buf_count<=chan.buf_size) {
	200	// Only transfer PCI data if bus mastering is enabled
	201	// Fill half-buffer when read pointer is at start of next half
	202	//if ((command & 0x4) && ((chan.buf_rptr&8)^(chan.buf_wptr&8)) && !(m_es_regs[ES_INT_CS_STATUS] & intr_mask)) {
	203	if ((command & 0x4) && ((chan.buf_rptr&8)^(chan.buf_wptr&8))) {
	204	transfer_pci_audio(chan, ES_PCI_READ);
	205	}
	206	if (LOG_ES && i==0)
	207	logerror("%X: chan: %X samples: %i buf_count: %X buf_size: %X buf_rptr: %X buf_wptr: %X\n",
	208	machine().device("maincpu")->safe_pc(), chan.number, samples, chan.buf_count, chan.buf_size, chan.buf_rptr, chan.buf_wptr);
	209	// Buffer is 4 bytes per location, need to switch on sample mode
	210	switch (chan.format) {
	211	case SCTRL_8BIT_MONO:
	212	logerror("es1373_device::send_audio_out SCTRL_8BIT_MONO not implemented yet\n");
	213	break;
	214	case SCTRL_8BIT_STEREO:
	215	logerror("es1373_device::send_audio_out SCTRL_8BIT_STEREO not implemented yet\n");
	216	break;
	217	case SCTRL_16BIT_MONO:
	218	// The sound cache is 32 bit wide fifo, so each entry is two mono 16 bit samples
	219	if ((chan.buf_count&0x1)) {
	220	// Read high 16 bits
	221	outL[i] = outR[i] = (INT16)(m_sound_cache[chan.buf_rptr]>>16);
	222	chan.buf_rptr++;
	223	buf_row_done = true;
	224	} else {
	225	// Read low 16 bits
	226	outL[i] = outR[i] = (INT16)(m_sound_cache[chan.buf_rptr]&0xffff);
	227	}
	228	break;
	229	case SCTRL_16BIT_STEREO:
	230	// The sound cache is 32 bit wide fifo, so each entry is one stereo 16 bit sample
	231	outL[i] = (INT16) m_sound_cache[chan.buf_rptr]&0xffff;
	232	outR[i] = (INT16) m_sound_cache[chan.buf_rptr]>>16;
	233	chan.buf_rptr++;
	234	buf_row_done = true;
	235	break;
	236	}
	237	if (LOG_ES_FILE && m_tempCount<1000000) {
	238	m_tempCount++;
	239	//logerror("es1373_device::sound_stream_update count: %i samp16: %X\n", i, samp16);
	240	//if (LOG_ES_FILE && m_eslog)
	241	//fprintf(m_eslog, "%i\n", samp16);
	242	}
	243	chan.buf_count++;
	244	if (chan.buf_count > chan.buf_size) {
	245	if (chan.loop_en) {
	246	// Keep playing
	247	//chan.buf_count -= 1;  // Should check SCTRL_P2_END_MASK
	248	chan.buf_count = 0;
	249	//chan.buf_rptr -= 1;
	250	if (LOG_ES)
	251	logerror("%X: send_audio_out DAC2 clearing buf_count\n", machine().device("maincpu")->safe_pc());
	252	}
	253	if (chan.int_en) {
	254	m_es_regs[ES_INT_CS_STATUS] |= intr_mask;
	255	if (LOG_ES)
	256	logerror("%X: send_audio_out Setting DAC2 interrupt\n", machine().device("maincpu")->safe_pc());
	257	}
	258	}
	259	if (buf_row_done && !(chan.buf_rptr&0xf)) {
	260	chan.buf_rptr -= 0x10;
	261	}
	262	} else {
	263	// Send zeros?
	264	outL[i] = outR[i] = 0;
	265	}
	266	}
	267	}
	268
156	269	void es1373_device::transfer_pci_audio(chan_info& chan, int type)
157	270	{
158	271	UINT32 pci_addr, data;
159	272	pci_addr = chan.pci_addr + (chan.pci_count<<2);
160		if (type==ES_PCI_READ) {
161		// Transfer from PCI to sound cache
162		// Always transfer 8 longwords
163		for (int i=0; i<8 && (chan.pci_count<=chan.pci_size); i++) {
	273	if (LOG_ES)
	274	logerror("%s: transfer_pci_audio start chan: %X pci_addr: %08X pci_count: %X pci_size: %X buf_rptr: %X buf_wptr: %X\n",
	275	machine().describe_context(), chan.number, pci_addr, chan.pci_count, chan.pci_size, chan.buf_rptr, chan.buf_wptr);
	276	// Always transfer 8 longwords
	277	for (int i=0; i<8; i++) {
	278	pci_addr = chan.pci_addr + (chan.pci_count<<2);
	279	if (type==ES_PCI_READ) {
164	280	data = m_memory_space->read_dword(pci_addr, 0xffffffff);
165	281	m_sound_cache[chan.buf_wptr++] = data;
166	282	if (!(chan.buf_wptr&0xf)) {
167	283	chan.buf_wptr -= 0x10;
168	284	}
169		chan.pci_count++;
170		pci_addr += 4;
171		}
172		} else {
173		// Transfer from sound cache to PCI
174		// Always transfer 8 longwords
175		for (int i=0; i<8 && chan.pci_count<=chan.pci_size; i++) {
	285	} else {
176	286	data = m_sound_cache[chan.buf_rptr++];
177	287	m_memory_space->write_dword(pci_addr, data);
178	288	if (!(chan.buf_rptr&0xf)) {
179	289	chan.buf_rptr -= 0x10;
180	290	}
	291	}
	292	if (chan.pci_count==chan.pci_size) {
	293	chan.pci_count = 0;
	294	} else {
181	295	chan.pci_count++;
182		pci_addr += 4;
183	296	}
184	297	}
185	298	}
186	299
	300	UINT32 es1373_device::calc_size(const UINT8 &format)
	301	{
	302	switch (format) {
	303	case SCTRL_8BIT_MONO:
	304	return 1;
	305	break;
	306	case SCTRL_8BIT_STEREO:
	307	return 2;
	308	break;
	309	case SCTRL_16BIT_MONO:
	310	return 2;
	311	break;
	312	case SCTRL_16BIT_STEREO:
	313	return 4;
	314	break;
	315	}
	316	logerror("%s: calc_size Invalid format = %X specified\n", tag(), format);
	317	return 0;
	318	}
	319
187	320	READ32_MEMBER (es1373_device::reg_r)
188	321	{
189	322	UINT32 result = m_es_regs[offset];
r245633	r245634
281	414	m_adc.int_en  = m_es_regs[ES_SERIAL_CTRL] & SCTRL_R1_INT_EN_MASK;
282	415	m_dac2.int_en = m_es_regs[ES_SERIAL_CTRL] & SCTRL_P2_INT_EN_MASK;
283	416	m_dac1.int_en = m_es_regs[ES_SERIAL_CTRL] & SCTRL_P1_INT_EN_MASK;
	417	m_adc.format = (m_es_regs[ES_SERIAL_CTRL] & SCTRL_R1_S_MASK)>>4;
	418	m_dac2.format = (m_es_regs[ES_SERIAL_CTRL] & SCTRL_P2_S_MASK)>>2;
	419	m_dac1.format = (m_es_regs[ES_SERIAL_CTRL] & SCTRL_P1_S_MASK)>>0;
284	420	if (!m_adc.int_en) m_es_regs[ES_INT_CS_STATUS]  &= ~ICSTATUS_ADC_INT_MASK;
285	421	if (!m_dac1.int_en) m_es_regs[ES_INT_CS_STATUS] &= ~ICSTATUS_DAC1_INT_MASK;
286	422	if (!m_dac2.int_en) m_es_regs[ES_INT_CS_STATUS] &= ~ICSTATUS_DAC2_INT_MASK;
r245633	r245634
290	426	if (m_es_regs[ES_INT_CS_STATUS]&ICSTATUS_INTR_MASK && m_irq_num!=-1) {
291	427	m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
292	428	m_es_regs[ES_INT_CS_STATUS] &= ~ICSTATUS_INTR_MASK;
293		if (LOG_ES)
	429	if (0 && LOG_ES_REG)
294	430	logerror("%X: es1373_device::reg_w Clearing interrupt\n", machine().device("maincpu")->safe_pc());
295	431	}
296	432	}
297		if (LOG_ES_REG)
	433	if (0 && LOG_ES_REG)
298	434	logerror("%s: es1373_device::reg_w adc_int_en: %i dac1_int_en: %i dac2_int_en: %i\n", tag(), m_adc.int_en, m_dac1.int_en, m_dac2.int_en);
299	435	break;
300	436	case ES_DAC2_CNT:
r245633	r245634
345	481	case 0xc:
346	482	m_dac2.pci_count = (data>>16)&0xffff;
347	483	m_dac2.pci_size = data&0xffff;
	484	if (LOG_ES_REG)
	485	logerror("%08X:ES1373 write to offset %02X = %08X & %08X\n", machine().device("maincpu")->safe_pc(), offset*4, data, mem_mask);
348	486	break;
349	487	default:
350	488	break;

trunk/src/emu/sound/es1373.h

r245633	r245634
1	1	// Creative Labs Ensonic AudioPCI97 ES1373
2	2
	3	#pragma once
	4
3	5	#ifndef ES1373_H
4	6	#define ES1373_H
5	7
r245633	r245634
64	66	#define SCTRL_P2_S_MASK       0x0000000C
65	67	#define SCTRL_P1_S_MASK       0x00000003
66	68
	69	#define SCTRL_8BIT_MONO            0x0
	70	#define SCTRL_8BIT_STEREO         0x1
	71	#define SCTRL_16BIT_MONO         0x2
	72	#define SCTRL_16BIT_STEREO      0x3
	73
67	74	#define ES_PCI_READ 0
68	75	#define ES_PCI_WRITE 1
69	76
70	77	struct chan_info {
	78	int number;
71	79	bool enable;
72	80	bool int_en;
73	81	bool loop_en;
74	82	bool initialized;
75		UINT32 samp_size;    // Size of one sample in log2(bytes)
	83	UINT8 format;       // Format of channel
76	84	UINT32 buf_wptr;     // Address to sample cache memory
77	85	UINT32 buf_rptr;     // Address to sample cache memory
78	86	UINT16 buf_count;    // Number of samples that have been played
r245633	r245634
82	90	UINT16 pci_size;     // Total number of words (32 bits) minus one in system memory
83	91	};
84	92
85		class es1373_device : public pci_device {
	93	class es1373_device : public pci_device, public device_sound_interface
	94	{
86	95	public:
87	96	es1373_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
88	97	virtual void map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
r245633	r245634
92	101
93	102	DECLARE_READ32_MEMBER (reg_r);
94	103	DECLARE_WRITE32_MEMBER(reg_w);
95		TIMER_DEVICE_CALLBACK_MEMBER(es_timer_callback);
	104
96	105	// optional information overrides
97	106	virtual machine_config_constructor device_mconfig_additions() const;
	107
	108	// Sound stream
	109	sound_stream *m_stream;
	110
98	111	protected:
99	112	virtual void device_start();
	113	virtual void device_stop();
100	114	virtual void device_reset();
101		address_space *m_memory_space;
102		//virtual const address_space_config *memory_space_config(address_spacenum spacenum) const;
	115	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	116	virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples);
103	117
	118	FILE *m_eslog;
	119
104	120	private:
	121	UINT32 m_tempCount;
	122	emu_timer *m_timer;
	123	address_space *m_memory_space;
105	124	const char *m_cpu_tag;
106	125	cpu_device *m_cpu;
107	126	int m_irq_num;
r245633	r245634
114	133	chan_info m_dac2;
115	134	chan_info m_adc;
116	135	void transfer_pci_audio(chan_info& chan, int type);
	136	UINT32 calc_size(const UINT8 &format);
	137	void send_audio_out(chan_info& chan, UINT32 intr_mask, stream_sample_t *outL, stream_sample_t *outR, int samples);
	138
117	139	};
118	140
119	141	extern const device_type ES1373;

trunk/src/emu/video/voodoo_pci.c

r245633	r245634
1	1	#include "voodoo_pci.h"
2	2
3	3	static MACHINE_CONFIG_FRAGMENT( voodoo_pci )
4		MCFG_DEVICE_ADD("voodoo", VOODOO_BANSHEE, STD_VOODOO_BANSHEE_CLOCK)
	4	MCFG_DEVICE_ADD("voodoo", VOODOO_3, STD_VOODOO_3_CLOCK)
5	5	MCFG_VOODOO_FBMEM(16)
6	6	MCFG_VOODOO_SCREEN_TAG("screen")
7		MCFG_VOODOO_CPU_TAG(":maincpu")
8	7	MACHINE_CONFIG_END
9	8
10	9	machine_config_constructor voodoo_pci_device::device_mconfig_additions() const
r245633	r245634
18	17	AM_RANGE(0x0, 0x01ffffff) AM_DEVREADWRITE("voodoo", voodoo_banshee_device, banshee_r, banshee_w)
19	18	ADDRESS_MAP_END
20	19	DEVICE_ADDRESS_MAP_START(lfb_map, 32, voodoo_pci_device)
21		AM_RANGE(0x0, 0x00ffffff) AM_DEVREADWRITE("voodoo", voodoo_banshee_device, banshee_fb_r, banshee_fb_w)
	20	AM_RANGE(0x0, 0x01ffffff) AM_DEVREADWRITE("voodoo", voodoo_banshee_device, banshee_fb_r, banshee_fb_w)
22	21	ADDRESS_MAP_END
23	22	DEVICE_ADDRESS_MAP_START(io_map, 32, voodoo_pci_device)
24	23	AM_RANGE(0x000, 0x0ff) AM_DEVREADWRITE("voodoo", voodoo_banshee_device, banshee_io_r, banshee_io_w)
r245633	r245634
30	29	{
31	30	}
32	31
	32	void voodoo_pci_device::set_cpu_tag(const char *_cpu_tag)
	33	{
	34	cpu_tag = _cpu_tag;
	35	}
	36
33	37	void voodoo_pci_device::device_start()
34	38	{
	39	voodoo_device::static_set_cpu_tag(m_voodoo, cpu_tag);
35	40	pci_device::device_start();
36	41	add_map(32*1024*1024, M_MEM, FUNC(voodoo_pci_device::reg_map));
37		add_map(16*1024*1024, M_MEM, FUNC(voodoo_pci_device::lfb_map));
	42	add_map(32*1024*1024, M_MEM, FUNC(voodoo_pci_device::lfb_map));
38	43	add_map(256, M_IO, FUNC(voodoo_pci_device::io_map));
39	44	}
40	45

trunk/src/emu/video/voodoo_pci.h

r245633	r245634
6	6	#include "machine/pci.h"
7	7	#include "voodoo.h"
8	8
9		#define MCFG_VOODOO_ADD(_tag) \
10		MCFG_PCI_DEVICE_ADD(_tag, VOODOO_PCI, 0x121a0005, 0x02, 0x000003, 0x000000)
	9	#define MCFG_VOODOO_ADD(_tag,  _cpu_tag) \
	10	MCFG_PCI_DEVICE_ADD(_tag, VOODOO_PCI, 0x121a0005, 0x02, 0x000003, 0x000000) \
	11	downcast<voodoo_pci_device *>(device)->set_cpu_tag(_cpu_tag);
11	12
12	13	class voodoo_pci_device : public pci_device {
13	14	public:
r245633	r245634
18	19	virtual machine_config_constructor device_mconfig_additions() const;
19	20	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
20	21
	22	void set_cpu_tag(const char *tag);
	23
21	24	protected:
22	25	virtual void device_start();
23	26	virtual void device_reset();
24	27
25	28	private:
26	29	required_device<voodoo_banshee_device> m_voodoo;
	30	const char *cpu_tag;
27	31
28	32	DECLARE_ADDRESS_MAP(reg_map, 32);
29	33	DECLARE_ADDRESS_MAP(lfb_map, 32);

trunk/src/mame/drivers/iteagle.c

r245633	r245634
118	118	{
119	119	/* set the fastest DRC options */
120	120	m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS);
	121
	122	/* configure fast RAM regions for DRC */
	123	//m_maincpu->mips3drc_add_fastram(0x00000000, 16*1024*1024-1, FALSE, m_rambase);
	124	//m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase);
121	125	}
	126
122	127	void iteagle_state::machine_reset()
123	128	{
124	129	}
r245633	r245634
134	139	MCFG_VRC4373_ADD(                 ":pci:00.0", ":maincpu")
135	140	MCFG_ITEAGLE_FPGA_ADD(            ":pci:06.0")
136	141	MCFG_ITEAGLE_IDE_ADD(             ":pci:06.1")
	142	MCFG_ITEAGLE_IDE_IRQ_ADD(         ":maincpu", MIPS3_IRQ2)
137	143	MCFG_ES1373_ADD(                  ":pci:07.0")
	144	MCFG_SOUND_ROUTE(0, ":pci:07.0:lspeaker", 1.0)
	145	MCFG_SOUND_ROUTE(1, ":pci:07.0:rspeaker", 1.0)
138	146	MCFG_ES1373_IRQ_ADD(              ":maincpu", MIPS3_IRQ3)
139		MCFG_VOODOO_ADD(                  ":pci:09.0")
	147	MCFG_VOODOO_ADD(                  ":pci:09.0", ":maincpu")
140	148	MCFG_ITEAGLE_EEPROM_ADD(          ":pci:0a.0")
141	149
	150
142	151	MCFG_SCREEN_ADD("screen", RASTER)
143	152	MCFG_SCREEN_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
144		MCFG_SCREEN_REFRESH_RATE(56.644)
145		MCFG_SCREEN_SIZE(640, 350)
146		MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 349)
	153	MCFG_SCREEN_REFRESH_RATE(59)
	154	MCFG_SCREEN_SIZE(512, 384)
	155	MCFG_SCREEN_VISIBLE_AREA(0, 511, 0, 383)
147	156	MCFG_SCREEN_UPDATE_DEVICE(":pci:09.0", voodoo_pci_device, screen_update)
148	157
149	158
r245633	r245634
158	167	static INPUT_PORTS_START( iteagle )
159	168
160	169	PORT_START("SW5")
161		PORT_DIPNAME( 0x3, 0x1, "Resolution" )
	170	PORT_DIPNAME( 0xf, 0x1, "Resolution" )
162	171	PORT_DIPSETTING(0x1, "Medium" )
163	172	PORT_DIPSETTING(0x0, "Low" )
164	173	PORT_DIPSETTING(0x2, "Low_Alt" )
165	174
166		PORT_START("SW51")
167		PORT_DIPNAME( 0x3, 0x0, "Mode" )
168		PORT_DIPSETTING(0x0, "Normal" )
169		PORT_DIPSETTING(0x1, "Operator" )
170
171	175	PORT_START("IN1")
172	176	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
173	177	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_START1 )
174	178	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME( "Left" )
175		PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME( "Right" )
176		PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME( "Fly By" )
177		PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME( "Backspin" )
	179	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME( "Right" )
	180	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME( "Fly By" )
	181	PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME( "Backspin" )
178	182	PORT_BIT( 0x00c0, IP_ACTIVE_HIGH, IPT_UNUSED )
179	183	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_COIN2 )
180	184	PORT_BIT( 0xfe00, IP_ACTIVE_HIGH, IPT_UNUSED )
181	185
182	186	PORT_START("SYSTEM")
183	187	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_SERVICE )
184		PORT_SERVICE_NO_TOGGLE( 0x0002, IP_ACTIVE_HIGH )
185		PORT_BIT( 0x00fc, IP_ACTIVE_HIGH, IPT_UNUSED )
	188	PORT_SERVICE_NO_TOGGLE( 0x0002, IP_ACTIVE_LOW )
	189	PORT_BIT( 0x000c, IP_ACTIVE_LOW, IPT_UNUSED )
	190	PORT_DIPNAME( 0x00f0, 0x00, "SW51" )
	191	PORT_DIPSETTING(0x00, "Normal" )
	192	PORT_DIPSETTING(0x10, "Operator Mode" )
186	193	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_VOLUME_UP )
187	194	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_VOLUME_DOWN )
188	195	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BILL1 )
r245633	r245634
227	234
228	235	INPUT_PORTS_END
229	236
230		static INPUT_PORTS_START( gtfore02o )
	237	static INPUT_PORTS_START( gtfore02 )
231	238	PORT_INCLUDE(iteagle)
232	239
233	240	PORT_MODIFY("VERSION")
r245633	r245634
237	244
238	245	INPUT_PORTS_END
239	246
240		static INPUT_PORTS_START( gtfore02 )
	247	static INPUT_PORTS_START( gtfore06 )
241	248	PORT_INCLUDE(iteagle)
242	249
243	250	PORT_MODIFY("VERSION")
r245633	r245634
288	295	ROM_START( iteagle )
289	296	EAGLE_BIOS
290	297
291		DISK_REGION( ":pci:06.1:ide:0:hdd:image" )
	298	DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
292	299	ROM_END
293		ROM_START( gtfore02 )
	300	ROM_START( gtfore06 )
294	301	EAGLE_BIOS
295	302
296	303	ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
297	304	ROM_LOAD( "g42-us-u.u53", 0x0000, 0x0880, CRC(06e0b452) SHA1(f6b865799cb94941e0e77453b9d556d5988b0194) )
298	305
299		DISK_REGION( ":pci:06.1:ide:0:hdd:image" )
	306	DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
300	307	DISK_IMAGE( "golf_fore_2002_v2.01.04_umv", 0, SHA1(e902b91bd739daee0b95b10e5cf33700dd63a76b) ) /* Labeled Golf Fore! V2.01.04 UMV */
301	308	//DISK_REGION( "ide:1:cdrom" ) // program CD-ROM
302	309
303	310	ROM_END
304	311
305		ROM_START( gtfore02o )
	312	ROM_START( gtfore02 )
306	313	EAGLE_BIOS
307	314
308	315	ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
309	316	ROM_LOAD( "g42-us-u.u53", 0x0000, 0x0880, CRC(06e0b452) SHA1(f6b865799cb94941e0e77453b9d556d5988b0194) )
310	317
311		DISK_REGION( ":pci:06.1:ide:0:hdd:image" )
	318	DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
312	319	DISK_IMAGE( "golf_fore_2002_v2.00.00", 0, SHA1(d789ef86837a5012beb224c487537dd563d93886) ) /* Labeled Golf Fore! 2002 V2.00.00 */
313	320	ROM_END
314	321
r245633	r245634
318	325	ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
319	326	ROM_LOAD( "ck1-us.u53", 0x0000, 0x0880, NO_DUMP )
320	327
321		DISK_REGION( ":pci:06.1:ide:0:hdd:image" )
	328	DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
322	329	DISK_IMAGE( "carnival_king_v_1.00.11", 0, SHA1(c819af66d36df173ab17bf42f4045c7cca3203d8) ) /* Labeled Carnival King V 1.00.11 */
323	330	ROM_END
324	331
r245633	r245634
328	335	ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
329	336	ROM_LOAD( "g44-us-u.u53", 0x0000, 0x0880, NO_DUMP )
330	337
331		DISK_REGION( ":pci:06.1:ide:0:hdd:image" )
	338	DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
332	339	DISK_IMAGE( "gt2004", 0, SHA1(739a52d6ce13bb6ac7a543ee0e8086fb66be19b9) )
333	340	ROM_END
334	341
r245633	r245634
338	345	ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
339	346	ROM_LOAD( "g45-us-u.u53", 0x0000, 0x0880, NO_DUMP )
340	347
341		DISK_REGION( ":pci:06.1:ide:0:hdd:image" )
	348	DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
342	349	DISK_IMAGE( "gt2005", 0, SHA1(d8de569d8cf97b5aaada10ce896eb3c75f1b37f1) )
343	350	ROM_END
344	351
r245633	r245634
349	356	*************************************/
350	357
351	358	GAME( 2000, iteagle,          0, gtfore, iteagle,   driver_device, 0, ROT0, "Incredible Technologies", "Eagle BIOS", GAME_IS_BIOS_ROOT )
352		GAME( 2001, gtfore02,   iteagle, gtfore, gtfore02,  driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2002 (v2.01.04 UMV)", GAME_NOT_WORKING | GAME_NO_SOUND )
353		GAME( 2001, gtfore02o, gtfore02, gtfore, gtfore02o, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2002 (v2.00.00)", GAME_NOT_WORKING | GAME_NO_SOUND )
	359	GAME( 2001, gtfore02,   iteagle, gtfore, gtfore02,  driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2002 (v2.00.00)", GAME_NOT_WORKING | GAME_NO_SOUND )
354	360	GAME( 2002, carnking,   iteagle, gtfore, iteagle,   driver_device, 0, ROT0, "Incredible Technologies", "Carnival King (v1.00.11)", GAME_NOT_WORKING | GAME_NO_SOUND )
355	361	GAME( 2003, gtfore04,   iteagle, gtfore, gtfore04,  driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2004", GAME_NOT_WORKING | GAME_NO_SOUND )
356	362	GAME( 2004, gtfore05,   iteagle, gtfore, gtfore05,  driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005", GAME_NOT_WORKING | GAME_NO_SOUND )
	363	GAME( 2005, gtfore06,   iteagle, gtfore, gtfore06,  driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2006 Complete", GAME_NOT_WORKING | GAME_NO_SOUND )

trunk/src/mame/machine/iteagle_fpga.c

r245633	r245634
1	1	#include "iteagle_fpga.h"
2	2	#include "coreutil.h"
3	3
4		#define LOG_FPGA            (1)
	4	#define LOG_FPGA            (0)
5	5	#define LOG_RTC             (0)
6		#define LOG_EEPROM          (1)
	6	#define LOG_EEPROM          (0)
7	7	#define LOG_IDE             (0)
8	8	#define LOG_IDE_CTRL        (0)
9	9
10	10
11	11	const device_type ITEAGLE_FPGA = &device_creator<iteagle_fpga_device>;
12	12
13		DEVICE_ADDRESS_MAP_START(ctrl_map, 32, iteagle_fpga_device)
14		AM_RANGE(0x000, 0x02f) AM_READWRITE(ctrl_r, ctrl_w)
15		ADDRESS_MAP_END
16
17	13	DEVICE_ADDRESS_MAP_START(fpga_map, 32, iteagle_fpga_device)
18	14	AM_RANGE(0x000, 0x01f) AM_READWRITE(fpga_r, fpga_w)
19	15	ADDRESS_MAP_END
20	16
21	17	DEVICE_ADDRESS_MAP_START(rtc_map, 32, iteagle_fpga_device)
22		AM_RANGE(0x000, 0x800) AM_READWRITE(rtc_r, rtc_w)
	18	AM_RANGE(0x000, 0x7ff) AM_READWRITE(rtc_r, rtc_w)
23	19	ADDRESS_MAP_END
24	20
25	21	iteagle_fpga_device::iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
26		: pci_device(mconfig, ITEAGLE_FPGA, "ITEagle FPGA", tag, owner, clock, "iteagle_fpga", __FILE__)
	22	: pci_device(mconfig, ITEAGLE_FPGA, "ITEagle FPGA", tag, owner, clock, "iteagle_fpga", __FILE__),
	23	device_nvram_interface(mconfig, *this)
27	24	{
28	25	}
29	26
r245633	r245634
33	30	status = 0x5555;
34	31	command = 0x5555;
35	32
36		add_map(sizeof(m_ctrl_regs), M_IO, FUNC(iteagle_fpga_device::ctrl_map));
37		// ctrl defaults to base address 0x00000000
38		bank_infos[0].adr = 0x00000000 & (~(bank_infos[0].size - 1));
39
40	33	add_map(sizeof(m_fpga_regs), M_IO, FUNC(iteagle_fpga_device::fpga_map));
41	34	// fpga defaults to base address 0x00000300
42		bank_infos[1].adr = 0x00000300 & (~(bank_infos[1].size - 1));
	35	bank_infos[0].adr = 0x00000300 & (~(bank_infos[0].size - 1));
43	36
44	37	add_map(sizeof(m_rtc_regs), M_MEM, FUNC(iteagle_fpga_device::rtc_map));
45	38	// RTC defaults to base address 0x000c0000
46		bank_infos[2].adr = 0x000c0000 & (~(bank_infos[2].size - 1));
	39	bank_infos[1].adr = 0x000c0000 & (~(bank_infos[1].size - 1));
47	40	}
48	41
49	42	void iteagle_fpga_device::device_reset()
50	43	{
51	44	pci_device::device_reset();
52		memset(m_ctrl_regs, 0, sizeof(m_ctrl_regs));
53	45	memset(m_fpga_regs, 0, sizeof(m_fpga_regs));
54		memset(m_rtc_regs, 0, sizeof(m_rtc_regs));
55		// 0x23 & 0x20 = IDE LED
56		m_ctrl_regs[0x10/4] =  0x00000000; // 0xFFFFFFFF causes a write of 0xFFFEFFFF then 0xFFFFFFFF  // Not sure
	46	//memset(m_rtc_regs, 0, sizeof(m_rtc_regs));
	47	//m_rtc_regs[0] = 0x11223344;
	48	switch ((machine().root_device().ioport("VERSION")->read()>>4)&0xF) {
	49	case 3:
	50	m_seq = 0x0a0b0a; // gt02o
	51	break;
	52	case 4:
	53	m_seq = 0x0a020b; // gt04
	54	break;
	55	case 5:
	56	m_seq = 0x0b0a0c; // gt05
	57	break;
	58	default:
	59	m_seq = 0x0c0b0d; // gt02
	60	break;
	61	}
	62
	63	m_seq_rem1 = 0;
	64	m_seq_rem2 = 0;
	65
57	66	// 0x00&0x2 == 1 for boot
58		m_fpga_regs[0x00/4] =  0xC0000002; // 0xCF000002;// byte 3 is voltage sensor? high = 0x40 good = 0xC0 0xF0 0xFF; //0x80 0x30 0x00FF = voltage low
59		//m_fpga_regs[0x308/4]=0x0000ffff; // Low 16 bits gets read a lot?
60		m_fpga_regs[0x08/4]=0x00000000; // Low 16 bits gets read a lot?
	67	//m_fpga_regs[0x00/4] =  0xC1110002; // 0xCF000002;// byte 3 is voltage sensor? high = 0x40 good = 0xC0 0xF0 0xFF; //0x80 0x30 0x00FF = voltage low
	68	//m_fpga_regs[0x00/4] =  0xC010ffff;
	69	// byte 3 is voltage sensor? high = 0x40 good = 0xC0 0xF0 0xFF; //0x80 0x30 0x00FF = voltage low
	70	// Bit 20 seems to be sw51 (operator mode) 0 = Normal, 1 = Operator Mode
	71	//m_fpga_regs[0x04/4] =  0x06060044; // Nibble starting at bit 20 is resolution, byte 0 is atmel response
	72	m_fpga_regs[0x04/4] =  0x00000000; // Nibble starting at bit 20 is resolution, byte 0 is atmel response
	73	//m_fpga_regs[0x308/4]=0x0000ffff; // Low 16 bits gets read alot?
	74	//m_fpga_regs[0x08/4]=0x0000ffff; // Low 16 bits is trackball
61	75	m_prev_reg = 0;
62	76	}
63	77
64		READ32_MEMBER( iteagle_fpga_device::ctrl_r )
	78	void iteagle_fpga_device::update_sequence(UINT32 data)
65	79	{
66		UINT32 result = m_fpga_regs[offset];
67		switch (offset) {
68		case 0x0/4:
69		if (LOG_FPGA)
70		logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
71		break;
72		default:
73		if (LOG_FPGA)
74		logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
75		break;
	80	UINT32 offset = 0x04/4;
	81	if (data & 0x80) {
	82	switch (data&0x3) {
	83	case 0:
	84	m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>4)&0xF);
	85	break;
	86	case 1:
	87	m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>8)&0xF);
	88	break;
	89	case 2:
	90	m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>12)&0xF);
	91	break;
	92	case 3:
	93	m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>0)&0xF);
	94	break;
	95	}
	96	} else {
	97	UINT32 val1, feed;
	98	feed = ((m_seq<<4) ^ m_seq)>>7;
	99	if (data & 0x1) {
	100	val1 = ((m_seq & 0x2)<<1) | ((m_seq & 0x4)>>1) | ((m_seq & 0x8)>>3);
	101	m_seq_rem1 = ((m_seq & 0x10)) | ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4);
	102	m_seq_rem2 = ((m_seq & 0x80)>>1) | ((m_seq & 0x100)>>3) | ((m_seq & 0x200)>>5);
	103	m_seq = (m_seq>>9) | ((feed&0x1ff)<<15);
	104	m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2)&0xFF);
	105	} else if (data & 0x2) {
	106	val1 = ((m_seq & 0x2)<<1) | ((m_seq & 0x4)>>1) | ((m_seq & 0x8)>>3);
	107	m_seq_rem1 = ((m_seq & 0x10)) | ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4);
	108	m_seq = (m_seq>>6) | ((feed&0x3f)<<18);
	109	m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2)&0xFF);
	110	} else {
	111	val1 = ((m_seq & 0x2)<<6) | ((m_seq & 0x4)<<4) | ((m_seq & 0x8)<<2) | ((m_seq & 0x10)<<0)
	112	| ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4) | ((m_seq & 0x80)>>6) | ((m_seq & 0x100)>>8);
	113	m_seq = (m_seq>>8) | ((feed&0xff)<<16);
	114	m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2) & 0xff);
	115	}
	116	if (0 && LOG_FPGA)
	117	logerror("%s:fpga update_sequence In: %02X Seq: %06X Out: %02X\n", machine().describe_context(), data, m_seq, m_fpga_regs[offset]&0xff);
76	118	}
77		return result;
78	119	}
79	120
80		WRITE32_MEMBER( iteagle_fpga_device::ctrl_w )
81		{
82		COMBINE_DATA(&m_fpga_regs[offset]);
83		switch (offset) {
84		case 0x20/4: // IDE LED and ??
85		if (ACCESSING_BITS_16_23) {
86		// Probably watchdog
87		} else if (ACCESSING_BITS_24_31) {
88		// Bit 1 is IDE LED
89		} else {
90		if (LOG_FPGA)
91		logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
92		}
93		break;
94		default:
95		if (LOG_FPGA)
96		logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
97		break;
98		}
99		}
100
101	121	READ32_MEMBER( iteagle_fpga_device::fpga_r )
102	122	{
103	123	UINT32 result = m_fpga_regs[offset];
104	124	switch (offset) {
105	125	case 0x00/4:
106		if (LOG_FPGA && (m_prev_reg != offset && m_prev_reg != (0x08/4)))
107		logerror("%s:fpga read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
	126	result = ((machine().root_device().ioport("SYSTEM")->read()&0xffff)<<16) | (machine().root_device().ioport("IN1")->read()&0xffff);
	127	if (1 && LOG_FPGA)
	128	logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
108	129	break;
109	130	case 0x04/4:
110		result =  (result & 0xFF0FFFFF) | (machine().root_device().ioport("SW5")->read()<<20); // Resolution
111		if (LOG_FPGA)
112		logerror("%s:fpga read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
	131	result =  (result & 0xFF0FFFFF) | ((machine().root_device().ioport("SW5")->read()&0xf)<<20);
	132	//if (0 && LOG_FPGA  && ACCESSING_BITS_0_7)
	133	if (1 && LOG_FPGA)
	134	logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
113	135	break;
114	136
115	137	case 0x08/4:
116		if (LOG_FPGA && (m_prev_reg != offset && m_prev_reg != (0x00/4)))
117		logerror("%s:fpga read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
	138	result = (result & 0xffff0000) | ((machine().root_device().ioport("TRACKY1")->read()&0xff)<<8) | (machine().root_device().ioport("TRACKX1")->read()&0xff);
	139	if (1 && LOG_FPGA && m_prev_reg != offset)
	140	logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
118	141	break;
	142	case 0x1c/4: // 1d = modem byte
	143	result =  (result & 0xFFFFFF00) | 0x04;
	144	if (LOG_FPGA)
	145	logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
	146	break;
119	147	default:
120	148	if (LOG_FPGA)
121		logerror("%s:fpga read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
	149	logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
122	150	break;
123	151	}
124	152	m_prev_reg = offset;
r245633	r245634
127	155
128	156	WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
129	157	{
130		UINT8 byte;
131	158
132	159	COMBINE_DATA(&m_fpga_regs[offset]);
133	160	switch (offset) {
134	161	case 0x04/4:
135	162	if (ACCESSING_BITS_0_7) {
136	163	// ATMEL Chip access.  Returns version id's when bit 7 is set.
137		byte = data & 0xFF;
138		if (byte & 0x80) {
139		switch (byte&0x3) {
140		case 0:
141		m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>4)&0xF);
142		break;
143		case 1:
144		m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>8)&0xF);
145		break;
146		case 2:
147		m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>12)&0xF);
148		break;
149		case 3:
150		m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>0)&0xF);
151		break;
152		}
153		} // Else???
	164	update_sequence(data & 0xff);
	165	if (0 && LOG_FPGA)
	166	logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
	167	} else {
	168	if (LOG_FPGA)
	169	logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
154	170	}
155		if (LOG_FPGA)
156		logerror("%s:fpga write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
157	171	break;
158	172	default:
159	173	if (LOG_FPGA)
160		logerror("%s:fpga write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
	174	logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
161	175	break;
162	176	}
163	177	}
164	178	//*************************************
165	179	//*  RTC M48T02
166	180	//*************************************
	181
	182	//-------------------------------------------------
	183	//  nvram_default - called to initialize NVRAM to
	184	//  its default state
	185	//-------------------------------------------------
	186
	187	void iteagle_fpga_device::nvram_default()
	188	{
	189	memset(m_rtc_regs, 0, sizeof(m_rtc_regs));
	190	}
	191
	192	//-------------------------------------------------
	193	//  nvram_read - called to read NVRAM from the
	194	//  .nv file
	195	//-------------------------------------------------
	196	void iteagle_fpga_device::nvram_read(emu_file &file)
	197	{
	198	file.read(m_rtc_regs, sizeof(m_rtc_regs));
	199	}
	200
	201	//-------------------------------------------------
	202	//  nvram_write - called to write NVRAM to the
	203	//  .nv file
	204	//-------------------------------------------------
	205	void iteagle_fpga_device::nvram_write(emu_file &file)
	206	{
	207	file.write(m_rtc_regs, sizeof(m_rtc_regs));
	208	}
	209
167	210	READ32_MEMBER( iteagle_fpga_device::rtc_r )
168	211	{
169	212	UINT32 result = m_rtc_regs[offset];
r245633	r245634
176	219	}
177	220	return result;
178	221	}
	222
179	223	WRITE32_MEMBER( iteagle_fpga_device::rtc_w )
180	224	{
181	225	system_time systime;
r245633	r245634
197	241	raw[6] = dec_2_bcd(systime.local_time.month + 1);
198	242	raw[7] = dec_2_bcd(systime.local_time.year - 1900); // Epoch is 1900
199	243	m_rtc_regs[0x7F8/4] = (raw[3]<<24) | (raw[2]<<16) | (raw[1]<<8) | (raw[0] <<0);
200		//m_rtc_regs[0x7FC/4] = (raw[7]<<24) | (raw[6]<<16) | (raw[5]<<8) | (raw[4] <<0);
201		m_rtc_regs[0x7FC/4] = (0x95<<24) | (raw[6]<<16) | (raw[5]<<8) | (raw[4] <<0);
	244	m_rtc_regs[0x7FC/4] = (raw[7]<<24) | (raw[6]<<16) | (raw[5]<<8) | (raw[4] <<0);
	245	//m_rtc_regs[0x7FC/4] = (0x95<<24) | (raw[6]<<16) | (raw[5]<<8) | (raw[4] <<0);
202	246	}
203	247	if (LOG_RTC)
204	248	logerror("%s:RTC write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
r245633	r245634
222	266	AM_RANGE(0x0000, 0x000F) AM_READWRITE(eeprom_r, eeprom_w) AM_SHARE("eeprom")
223	267	ADDRESS_MAP_END
224	268
	269	// When corrupt writes 0x3=2, 0x3e=2, 0xa=0, 0x30=0
	270	// 0x4 = HW Version
	271	// 0x5 = Serial Num + top byte of 0x4
	272	// 0x6 = OperID
	273	// 0xe = SW Version
	274	// 0x7f = checksum
	275	static const UINT16 iteagle_default_eeprom[0x40] =
	276	{
	277	0x0011,0x0022,0x0033,0x0002,0x1206,0x1111,0x2222,0x1234,
	278	0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
	279	0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
	280	0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
	281	0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
	282	0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
	283	0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
	284	0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0002,0x0000
	285	};
	286
225	287	static MACHINE_CONFIG_FRAGMENT( iteagle_eeprom )
226	288	MCFG_EEPROM_SERIAL_93C46_ADD("eeprom")
	289	MCFG_EEPROM_SERIAL_DATA(iteagle_default_eeprom, 0x80)
227	290	MACHINE_CONFIG_END
228	291
229	292	machine_config_constructor iteagle_eeprom_device::device_mconfig_additions() const
r245633	r245634
246	309
247	310	void iteagle_eeprom_device::device_reset()
248	311	{
	312	// Set software version and calc crc
	313	m_eeprom->write(0xe, (machine().root_device().ioport("VERSION")->read()&0xFF00) |
	314	(((machine().root_device().ioport("VERSION")->read()>>4)&0x0F)));
	315	UINT16 checkSum = 0;
	316	for (int i=0; i<0x3f; i++) {
	317	checkSum += m_eeprom->read(i);
	318	//logerror("eeprom init i: %x data: %04x\n", i, m_eeprom->read(i));
	319	}
	320	m_eeprom->write(0x3f, checkSum);
249	321	pci_device::device_reset();
250	322	}
251	323
r245633	r245634
257	329	case 0xC/4: // I2C Handler
258	330	if (ACCESSING_BITS_16_23) {
259	331	result = m_eeprom->do_read()<<(16+3);
260		}   else {
261	332	if (LOG_EEPROM)
262	333	logerror("%s:eeprom read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
	334	}   else {
	335	logerror("%s:eeprom read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
263	336	}
264	337	break;
265	338	default:
266		if (LOG_EEPROM)
267	339	logerror("%s:eeprom read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
268	340	break;
269	341	}
r245633	r245634
278	350	m_eeprom->di_write((data  & 0x040000) >> (16+2));
279	351	m_eeprom->cs_write((data  & 0x020000) ? ASSERT_LINE : CLEAR_LINE);
280	352	m_eeprom->clk_write((data & 0x010000) ? ASSERT_LINE : CLEAR_LINE);
281		}   else {
282	353	if (LOG_EEPROM)
283	354	logerror("%s:eeprom write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
	355	}   else {
	356	//if (LOG_EEPROM)
	357	logerror("%s:eeprom write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
284	358	}
285	359	break;
286	360	default:
287		if (LOG_EEPROM)
	361	//if (LOG_EEPROM)
288	362	logerror("%s:eeprom write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
289	363	break;
290	364	}
r245633	r245634
296	370
297	371	const device_type ITEAGLE_IDE = &device_creator<iteagle_ide_device>;
298	372
	373	DEVICE_ADDRESS_MAP_START(ctrl_map, 32, iteagle_ide_device)
	374	AM_RANGE(0x000, 0x02f) AM_READWRITE(ctrl_r, ctrl_w)
	375	ADDRESS_MAP_END
	376
	377
299	378	DEVICE_ADDRESS_MAP_START(ide_map, 32, iteagle_ide_device)
300		AM_RANGE(0x0, 0xf) AM_READWRITE(ide_r, ide_w)
	379	AM_RANGE(0x0, 0x7) AM_READWRITE(ide_r, ide_w)
301	380	ADDRESS_MAP_END
302	381
303	382	DEVICE_ADDRESS_MAP_START(ide_ctrl_map, 32, iteagle_ide_device)
304	383	AM_RANGE(0x0, 0x3) AM_READWRITE(ide_ctrl_r, ide_ctrl_w)
305	384	ADDRESS_MAP_END
306	385
	386	DEVICE_ADDRESS_MAP_START(ide2_map, 32, iteagle_ide_device)
	387	AM_RANGE(0x0, 0x7) AM_READWRITE(ide2_r, ide2_w)
	388	ADDRESS_MAP_END
307	389
	390	DEVICE_ADDRESS_MAP_START(ide2_ctrl_map, 32, iteagle_ide_device)
	391	AM_RANGE(0x0, 0x3) AM_READWRITE(ide2_ctrl_r, ide2_ctrl_w)
	392	ADDRESS_MAP_END
	393
	394
308	395	static MACHINE_CONFIG_FRAGMENT( iteagle_ide )
309		MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	396	MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, NULL, "cdrom", true)
	397	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(iteagle_ide_device, ide_interrupt))
310	398	MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM)
	399	MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide2", ata_devices, "hdd", NULL, true)
	400	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(iteagle_ide_device, ide2_interrupt))
	401	MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM)
311	402	MACHINE_CONFIG_END
312	403
313	404	machine_config_constructor iteagle_ide_device::device_mconfig_additions() const
314	405	{
315	406	return MACHINE_CONFIG_NAME( iteagle_ide );
316	407	}
	408
317	409	iteagle_ide_device::iteagle_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
318	410	: pci_device(mconfig, ITEAGLE_IDE, "ITEagle IDE Controller", tag, owner, clock, "ide", __FILE__),
319		m_ide(*this, "ide")
	411	m_ide(*this, "ide"),
	412	m_ide2(*this, "ide2"),
	413	m_irq_num(-1)
320	414	{
321	415	}
322	416
	417	void iteagle_ide_device::set_irq_info(const char *tag, const int irq_num)
	418	{
	419	m_cpu_tag = tag;
	420	m_irq_num = irq_num;
	421	}
	422
323	423	void iteagle_ide_device::device_start()
324	424	{
	425	m_cpu = machine().device<cpu_device>(m_cpu_tag);
325	426	pci_device::device_start();
326		add_map(0x10, M_IO, FUNC(iteagle_ide_device::ide_map));
327		bank_infos[0].adr = 0x1f0;
	427	add_map(sizeof(m_ctrl_regs), M_IO, FUNC(ctrl_map));
	428	// ctrl defaults to base address 0x00000000
	429	bank_infos[0].adr = 0x000;
	430
	431	add_map(0x8, M_IO, FUNC(iteagle_ide_device::ide_map));
	432	bank_infos[1].adr = 0x170;
328	433	add_map(0x4, M_IO, FUNC(iteagle_ide_device::ide_ctrl_map));
329		bank_infos[1].adr = 0x3f4;
	434	bank_infos[2].adr = 0x374;
	435	add_map(0x8, M_IO, FUNC(iteagle_ide_device::ide2_map));
	436	bank_infos[3].adr = 0x1f0;
	437	add_map(0x4, M_IO, FUNC(iteagle_ide_device::ide2_ctrl_map));
	438	bank_infos[4].adr = 0x3f4;
330	439	}
331	440
332	441	void iteagle_ide_device::device_reset()
333	442	{
334	443	pci_device::device_reset();
	444	memset(m_ctrl_regs, 0, sizeof(m_ctrl_regs));
	445	// 0x23 & 0x20 = IDE LED
	446	m_ctrl_regs[0x10/4] =  0x00000000; // 0x6=No SIMM, 0x2, 0x0 = SIMM
335	447	}
336		//*************************************
337		//*  IDE
338		//*************************************
	448
	449	READ32_MEMBER( iteagle_ide_device::ctrl_r )
	450	{
	451	UINT32 result = m_ctrl_regs[offset];
	452	switch (offset) {
	453	case 0x0/4:
	454	if (LOG_IDE_CTRL)
	455	logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
	456	break;
	457	default:
	458	if (LOG_IDE_CTRL)
	459	logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
	460	break;
	461	}
	462	return result;
	463	}
	464
	465	WRITE32_MEMBER( iteagle_ide_device::ctrl_w )
	466	{
	467	COMBINE_DATA(&m_ctrl_regs[offset]);
	468	switch (offset) {
	469	case 0x20/4: // IDE LED and ??
	470	if (ACCESSING_BITS_16_23) {
	471	// Probably watchdog
	472	if (1 && LOG_IDE_CTRL)
	473	logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
	474	} else if (ACCESSING_BITS_24_31) {
	475	// Bit 25 is IDE LED
	476	if (1 && LOG_IDE_CTRL)
	477	logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
	478	} else {
	479	if (LOG_IDE_CTRL)
	480	logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
	481	}
	482	break;
	483	default:
	484	if (LOG_IDE_CTRL)
	485	logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
	486	break;
	487	}
	488	}
	489
339	490	READ32_MEMBER( iteagle_ide_device::ide_r )
340	491	{
341	492	UINT32 result = m_ide->read_cs0(space, offset, mem_mask);
	493	if (offset==0x4/4 && ACCESSING_BITS_24_31) {
	494	//result = 0;
	495	if ((m_irq_num!=-1) && m_ctrl_regs[0x20/4]&0x80000000) {
	496	m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
	497	if (LOG_IDE)
	498	logerror("%s:ide_interrupt Clearing interrupt\n", machine().describe_context());
	499	}
	500	}
342	501	if (LOG_IDE)
343	502	logerror("%s:ide_r read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
344	503	return result;
r245633	r245634
362	521	if (LOG_IDE_CTRL)
363	522	logerror("%s:ide_ctrl_w write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
364	523	}
	524	WRITE_LINE_MEMBER(iteagle_ide_device::ide_interrupt)
	525	{
	526	//cpu_device *m_cpu = machine().device<cpu_device>(":maincpu");
	527	if ((m_irq_num!=-1) && m_ctrl_regs[0x20/4]&0x80000000) {
	528	m_cpu->set_input_line(m_irq_num, ASSERT_LINE);
	529	if (LOG_IDE_CTRL)
	530	logerror("%s:ide_interrupt Setting interrupt\n", machine().describe_context());
	531	}
	532	}
	533
	534	READ32_MEMBER( iteagle_ide_device::ide2_r )
	535	{
	536	UINT32 result = m_ide2->read_cs0(space, offset, mem_mask);
	537	if (offset==0x4/4 && ACCESSING_BITS_24_31) {
	538	if ((m_irq_num!=-1) && m_ctrl_regs[0x20/4]&0x40000000) {
	539	m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
	540	if (LOG_IDE_CTRL)
	541	logerror("%s:ide2_interrupt Clearing interrupt\n", machine().describe_context());
	542	}
	543	}
	544	if (LOG_IDE)
	545	logerror("%s:ide2_r read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
	546	return result;
	547	}
	548	WRITE32_MEMBER( iteagle_ide_device::ide2_w )
	549	{
	550	m_ide2->write_cs0(space, offset, data, mem_mask);
	551	if (LOG_IDE)
	552	logerror("%s:ide2_w write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
	553	}
	554	READ32_MEMBER( iteagle_ide_device::ide2_ctrl_r )
	555	{
	556	UINT32 result = m_ide2->read_cs1(space, offset+1, mem_mask);
	557	if (LOG_IDE_CTRL)
	558	logerror("%s:ide2_ctrl_r read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
	559	return result;
	560	}
	561	WRITE32_MEMBER( iteagle_ide_device::ide2_ctrl_w )
	562	{
	563	m_ide2->write_cs1(space, offset+1, data, mem_mask);
	564	if (LOG_IDE_CTRL)
	565	logerror("%s:ide2_ctrl_w write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
	566	}
	567	WRITE_LINE_MEMBER(iteagle_ide_device::ide2_interrupt)
	568	{
	569	if ((m_irq_num!=-1) &&m_ctrl_regs[0x20/4]&0x40000000) {
	570	m_cpu->set_input_line(m_irq_num, ASSERT_LINE);
	571	if (LOG_IDE_CTRL)
	572	logerror("%s:ide2_interrupt Setting interrupt\n", machine().describe_context());
	573	}
	574	}

trunk/src/mame/machine/iteagle_fpga.h

r245633	r245634
17	17	#define MCFG_ITEAGLE_IDE_ADD(_tag) \
18	18	MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_IDE, 0x11223344, 0x00, 0x010100, 0x00)
19	19
20		class iteagle_fpga_device : public pci_device {
	20	#define MCFG_ITEAGLE_IDE_IRQ_ADD(_cpu_tag, _irq_num) \
	21	downcast<iteagle_ide_device *>(device)->set_irq_info(_cpu_tag, _irq_num);
	22
	23	class iteagle_fpga_device : public pci_device,
	24	public device_nvram_interface
	25	{
21	26	public:
22	27	iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
23	28
r245633	r245634
25	30	virtual void device_start();
26	31	virtual void device_reset();
27	32
	33	// device_nvram_interface overrides
	34	virtual void nvram_default();
	35	virtual void nvram_read(emu_file &file);
	36	virtual void nvram_write(emu_file &file);
	37
28	38	private:
29	39
30		UINT32 m_ctrl_regs[0x30];
31	40	UINT32 m_fpga_regs[0x20];
32		UINT32 m_rtc_regs[0x800];
	41	UINT32 m_rtc_regs[0x200];
33	42	UINT32 m_prev_reg;
34	43
	44	UINT32 m_seq;
	45	UINT32 m_seq_rem1, m_seq_rem2;
	46	void update_sequence(UINT32 data);
	47
35	48	DECLARE_ADDRESS_MAP(rtc_map, 32);
36	49	DECLARE_ADDRESS_MAP(fpga_map, 32);
37		DECLARE_ADDRESS_MAP(ctrl_map, 32);
38	50
39		DECLARE_READ32_MEMBER( ctrl_r );
40		DECLARE_WRITE32_MEMBER( ctrl_w );
41	51	DECLARE_READ32_MEMBER( fpga_r );
42	52	DECLARE_WRITE32_MEMBER( fpga_w );
43	53	DECLARE_READ32_MEMBER( rtc_r );
r245633	r245634
67	77	iteagle_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
68	78	// optional information overrides
69	79	virtual machine_config_constructor device_mconfig_additions() const;
	80	void set_irq_info(const char *tag, const int irq_num);
70	81
71	82	required_device<bus_master_ide_controller_device> m_ide;
	83	required_device<bus_master_ide_controller_device> m_ide2;
	84	DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
	85	DECLARE_WRITE_LINE_MEMBER(ide2_interrupt);
72	86
73	87	protected:
74	88	virtual void device_start();
75	89	virtual void device_reset();
76	90
77	91	private:
	92	const char *m_cpu_tag;
	93	cpu_device *m_cpu;
	94	int m_irq_num;
	95
	96	UINT32 m_ctrl_regs[0x30];
	97
	98	DECLARE_ADDRESS_MAP(ctrl_map, 32);
78	99	DECLARE_ADDRESS_MAP(ide_map, 32);
79	100	DECLARE_ADDRESS_MAP(ide_ctrl_map, 32);
	101	DECLARE_ADDRESS_MAP(ide2_map, 32);
	102	DECLARE_ADDRESS_MAP(ide2_ctrl_map, 32);
80	103
	104	DECLARE_READ32_MEMBER( ctrl_r );
	105	DECLARE_WRITE32_MEMBER( ctrl_w );
	106
81	107	DECLARE_READ32_MEMBER( ide_r );
82	108	DECLARE_WRITE32_MEMBER( ide_w );
83	109	DECLARE_READ32_MEMBER( ide_ctrl_r );
84	110	DECLARE_WRITE32_MEMBER( ide_ctrl_w );
	111
	112	DECLARE_READ32_MEMBER( ide2_r );
	113	DECLARE_WRITE32_MEMBER( ide2_w );
	114	DECLARE_READ32_MEMBER( ide2_ctrl_r );
	115	DECLARE_WRITE32_MEMBER( ide2_ctrl_w );
	116
85	117	};
86	118
87	119	extern const device_type ITEAGLE_FPGA;

trunk/src/mame/mame.lst

r245633	r245634
4237	4237	gtclasscp       // (c) 2001 Incredible Technologies
4238	4238	gtclasscs       // (c) 2001 Incredible Technologies
4239	4239	gtfore02        // (c) 2001 Incredible Technologies
4240		gtfore02o       // (c) 2001 Incredible Technologies
4241	4240	carnking        // (c) 2002 Incredible Technologies
4242	4241	gtfore04        // (c) 2003 Incredible Technologies
4243	4242	gtfore05        // (c) 2004 Incredible Technologies
	4243	gtfore06        // (c) 2005 Incredible Technologies
4244	4244
4245	4245	// Leland games
4246	4246	cerberus        // (c) 1985 Cinematronics

https://github.com/mamedev/mame/commit/da682be22152aede4091423e7b4697561fc7a5fa

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team