trunk/src/emu/bus/ieee488/c2040fdc.c
| r245631 | r245632 | |
| 28 | 28 | |
| 29 | 29 | #define LOG 0 |
| 30 | 30 | |
| 31 | #define GCR_DECODE(_e, _i) \ |
| 32 | ((BIT(_e, 6) << 7) | (BIT(_i, 7) << 6) | (_e & 0x33) | (BIT(_e, 2) << 3) | (_i & 0x04)) |
| 31 | 33 | |
| 34 | #define GCR_ENCODE(_e, _i) \ |
| 35 | ((_e & 0xc0) << 2 | (_i & 0x80) | (_e & 0x3c) << 1 | (_i & 0x04) | (_e & 0x03)) |
| 32 | 36 | |
| 37 | |
| 38 | |
| 33 | 39 | //************************************************************************** |
| 34 | 40 | // DEVICE DEFINITIONS |
| 35 | 41 | //************************************************************************** |
| r245631 | r245632 | |
| 349 | 355 | |
| 350 | 356 | if (!ready) { |
| 351 | 357 | // load write shift register |
| 352 | | // E7 E6 I7 E5 E4 E3 E2 I2 E1 E0 |
| 353 | | UINT8 e = cur_live.e; |
| 354 | | offs_t i = cur_live.i; |
| 358 | cur_live.shift_reg_write = GCR_ENCODE(cur_live.e, cur_live.i); |
| 355 | 359 | |
| 356 | | cur_live.shift_reg_write = BIT(e,7)<<9 | BIT(e,6)<<8 | BIT(i,7)<<7 | BIT(e,5)<<6 | BIT(e,4)<<5 | BIT(e,3)<<4 | BIT(e,2)<<3 | BIT(i,2)<<2 | (e & 0x03); |
| 357 | | |
| 358 | 360 | if (LOG) logerror("%s load write shift register %03x\n",cur_live.tm.as_string(),cur_live.shift_reg_write); |
| 359 | 361 | } else if (BIT(cell_counter, 1) && !BIT(cur_live.cell_counter, 1)) { |
| 360 | 362 | // clock write shift register |
| r245631 | r245632 | |
| 433 | 435 | UINT8 e = checkpoint_live.e; |
| 434 | 436 | offs_t i = checkpoint_live.i; |
| 435 | 437 | |
| 436 | | UINT8 data = (BIT(e, 6) << 7) | (BIT(i, 7) << 6) | (e & 0x33) | (BIT(e, 2) << 3) | (i & 0x04); |
| 438 | UINT8 data = GCR_DECODE(e, i); |
| 437 | 439 | |
| 438 | 440 | if (LOG) logerror("%s %s VIA reads data %02x (%03x)\n", machine().time().as_string(), machine().describe_context(), data, checkpoint_live.shift_reg); |
| 439 | 441 | |
trunk/src/emu/bus/ieee488/c8050.c
| r245631 | r245632 | |
| 550 | 550 | MCFG_MOS6530n_OUT_PB1_CB(DEVWRITELINE(FDC_TAG, c8050_fdc_t, ds0_w)) |
| 551 | 551 | MCFG_MOS6530n_OUT_PB2_CB(DEVWRITELINE(FDC_TAG, c8050_fdc_t, ds1_w)) |
| 552 | 552 | MCFG_MOS6530n_IN_PB3_CB(DEVREADLINE(FDC_TAG, c8050_fdc_t, wps_r)) |
| 553 | | MCFG_MOS6530n_IN_PB6_CB(VCC) // SINGLE SIDED |
| 554 | 553 | |
| 555 | 554 | MCFG_DEVICE_ADD(FDC_TAG, C8050_FDC, XTAL_12MHz/2) |
| 556 | 555 | MCFG_C8050_SYNC_CALLBACK(DEVWRITELINE(M6522_TAG, via6522_device, write_pb7)) |
trunk/src/emu/bus/ieee488/c8050fdc.c
| r245631 | r245632 | |
| 230 | 230 | |
| 231 | 231 | cur_live.shift_reg = 0; |
| 232 | 232 | cur_live.shift_reg_write = 0; |
| 233 | | cur_live.cycle_counter = 0; |
| 234 | | cur_live.cell_counter = 0; |
| 235 | 233 | cur_live.bit_counter = 0; |
| 236 | 234 | cur_live.ds = m_ds; |
| 237 | 235 | cur_live.drv_sel = m_drv_sel; |
| r245631 | r245632 | |
| 395 | 393 | |
| 396 | 394 | // GCR decoder |
| 397 | 395 | if (cur_live.rw_sel) { |
| 398 | | cur_live.i = cur_live.shift_reg; |
| 396 | cur_live.i = (cur_live.rw_sel << 10) | cur_live.shift_reg; |
| 399 | 397 | } else { |
| 400 | | cur_live.i = ((cur_live.pi & 0xf0) << 1) | (cur_live.mode_sel << 4) | (cur_live.pi & 0x0f); |
| 398 | cur_live.i = (cur_live.rw_sel << 10) | ((cur_live.pi & 0xf0) << 1) | (cur_live.mode_sel << 4) | (cur_live.pi & 0x0f); |
| 401 | 399 | } |
| 402 | 400 | |
| 403 | | cur_live.e = m_gcr_rom->base()[cur_live.rw_sel << 10 | cur_live.i]; |
| 401 | cur_live.e = m_gcr_rom->base()[cur_live.i]; |
| 404 | 402 | |
| 405 | 403 | if (LOG) logerror("%s cyl %u bit %u sync %u bc %u sr %03x i %03x e %02x\n",cur_live.tm.as_string(),get_floppy()->get_cyl(),bit,sync,cur_live.bit_counter,cur_live.shift_reg,cur_live.i,cur_live.e); |
| 406 | 404 | |
trunk/src/mess/machine/victor9k_fdc.c
| r245631 | r245632 | |
| 1245 | 1245 | |
| 1246 | 1246 | // GCR decoder |
| 1247 | 1247 | if (cur_live.drw) { |
| 1248 | | cur_live.i = cur_live.shift_reg; |
| 1248 | cur_live.i = cur_live.drw << 10 | cur_live.shift_reg; |
| 1249 | 1249 | } else { |
| 1250 | | cur_live.i = 0x200 | ((cur_live.wd & 0xf0) << 1) | cur_live.wrsync << 4 | (cur_live.wd & 0x0f); |
| 1250 | cur_live.i = cur_live.drw << 10 | 0x200 | ((cur_live.wd & 0xf0) << 1) | cur_live.wrsync << 4 | (cur_live.wd & 0x0f); |
| 1251 | 1251 | } |
| 1252 | 1252 | |
| 1253 | | cur_live.e = m_gcr_rom->base()[cur_live.drw << 10 | cur_live.i]; |
| 1253 | cur_live.e = m_gcr_rom->base()[cur_live.i]; |
| 1254 | 1254 | |
| 1255 | 1255 | attotime next = cur_live.tm + m_period; |
| 1256 | 1256 | if (LOG) logerror("%s:%s cyl %u bit %u sync %u bc %u sr %03x sbc %u sBC %u syn %u i %03x e %02x\n",cur_live.tm.as_string(),next.as_string(),get_floppy()->get_cyl(),bit,sync,cur_live.bit_counter,cur_live.shift_reg,cur_live.sync_bit_counter,cur_live.sync_byte_counter,syn,cur_live.i,cur_live.e); |