trunk/src/emu/cpu/nec/v53.c
| r244828 | r244829 | |
|---|
| 1 | 1 | /* V53 */ |
| 2 | 2 | |
| 3 | // V33 / V33A cores with onboard peripherals |
| 4 | |
| 5 | // Interrupt Controller is uPD71059 equivalent |
| 6 | // DMA Controller can operate in modes providing a subset of the uPD71071 or uPD71037 functionality (some modes unavailable / settings ignored) |
| 7 | // Serial Controller is based on the uPD71051 but with some changes |
| 8 | // Timer Unit is functionally identical to uPD71054 |
| 9 | |
| 3 | 10 | #include "emu.h" |
| 4 | 11 | #include "v53.h" |
| 5 | 12 | |
| r244828 | r244829 | |
|---|
| 193 | 200 | |
| 194 | 201 | if (m_OPSEL & 0x01) // DMA Unit available |
| 195 | 202 | { |
| 196 | | if (IOAG) // 8-bit |
| 203 | if (m_SCTL & 0x02) // uPD71037 mode |
| 197 | 204 | { |
| 205 | if (IOAG) // 8-bit |
| 206 | { |
| 198 | 207 | |
| 208 | } |
| 209 | else |
| 210 | { |
| 211 | |
| 212 | } |
| 199 | 213 | } |
| 200 | 214 | else |
| 201 | 215 | { |
| 202 | | |
| 216 | |
| 203 | 217 | } |
| 204 | 218 | } |
| 205 | 219 | |
| 206 | 220 | if (m_OPSEL & 0x02) // Interupt Control Unit available |
| 207 | 221 | { |
| 222 | UINT16 base = (m_OPHA << 8) | m_IULA; |
| 223 | |
| 208 | 224 | if (IOAG) // 8-bit |
| 209 | 225 | { |
| 210 | 226 | |
| 211 | 227 | } |
| 212 | 228 | else |
| 213 | 229 | { |
| 230 | space(AS_IO).install_readwrite_handler(base+0x00, base+0x01, read8_delegate(FUNC(v53_base_device::icu_0_r), this), write8_delegate(FUNC(v53_base_device::icu_0_w), this), 0x00ff); |
| 231 | space(AS_IO).install_readwrite_handler(base+0x02, base+0x03, read8_delegate(FUNC(v53_base_device::icu_1_r), this), write8_delegate(FUNC(v53_base_device::icu_1_w), this), 0x00ff); |
| 214 | 232 | |
| 215 | 233 | } |
| 216 | 234 | } |
| r244828 | r244829 | |
|---|
| 218 | 236 | if (m_OPSEL & 0x04) // Timer Control Unit available |
| 219 | 237 | { |
| 220 | 238 | UINT16 base = (m_OPHA << 8) | m_TULA; |
| 221 | | printf("installing TCU to %04x\n", base); |
| 239 | //printf("installing TCU to %04x\n", base); |
| 222 | 240 | |
| 223 | 241 | if (IOAG) // 8-bit |
| 224 | 242 | { |
| r244828 | r244829 | |
|---|
| 235 | 253 | |
| 236 | 254 | if (m_OPSEL & 0x08) // Serial Control Unit available |
| 237 | 255 | { |
| 238 | | |
| 256 | UINT16 base = (m_OPHA << 8) | m_SULA; |
| 239 | 257 | if (IOAG) // 8-bit |
| 240 | 258 | { |
| 241 | 259 | |
| 242 | 260 | } |
| 243 | 261 | else |
| 244 | 262 | { |
| 263 | space(AS_IO).install_readwrite_handler(base+0x00, base+0x01, read8_delegate(FUNC(v53_base_device::scu_srb_r), this), write8_delegate(FUNC(v53_base_device::scu_stb_w), this), 0x00ff); |
| 264 | space(AS_IO).install_readwrite_handler(base+0x02, base+0x03, read8_delegate(FUNC(v53_base_device::scu_sst_r), this), write8_delegate(FUNC(v53_base_device::scu_scm_w), this), 0x00ff); |
| 265 | space(AS_IO).install_write_handler(base+0x04, base+0x05, write8_delegate(FUNC(v53_base_device::scu_smd_w), this), 0x00ff); |
| 266 | space(AS_IO).install_readwrite_handler(base+0x06, base+0x07, read8_delegate(FUNC(v53_base_device::scu_simk_r), this), write8_delegate(FUNC(v53_base_device::scu_simk_w), this), 0x00ff); |
| 245 | 267 | |
| 246 | 268 | } |
| 247 | 269 | } |
| 248 | 270 | |
| 249 | 271 | } |
| 250 | 272 | |
| 273 | /*** ICU ***/ |
| 274 | |
| 275 | |
| 276 | |
| 277 | READ8_MEMBER(v53_base_device::icu_0_r) |
| 278 | { |
| 279 | printf("v53: icu_0_r\n"); |
| 280 | return 0; |
| 281 | } |
| 282 | |
| 283 | WRITE8_MEMBER(v53_base_device::icu_0_w) |
| 284 | { |
| 285 | printf("v53: icu_0_w %02x\n", data); |
| 286 | } |
| 287 | |
| 288 | READ8_MEMBER(v53_base_device::icu_1_r) |
| 289 | { |
| 290 | printf("v53: icu_1_r\n"); |
| 291 | return 0; |
| 292 | } |
| 293 | |
| 294 | WRITE8_MEMBER(v53_base_device::icu_1_w) |
| 295 | { |
| 296 | printf("v53: icu_1_w %02x\n", data); |
| 297 | } |
| 298 | |
| 299 | /*** SCU ***/ |
| 300 | |
| 301 | READ8_MEMBER(v53_base_device::scu_srb_r) |
| 302 | { |
| 303 | printf("v53: scu_srb_r\n"); |
| 304 | return 0; |
| 305 | } |
| 306 | |
| 307 | WRITE8_MEMBER(v53_base_device::scu_stb_w) |
| 308 | { |
| 309 | printf("v53: scu_stb_w %02x\n", data); |
| 310 | } |
| 311 | |
| 312 | READ8_MEMBER(v53_base_device::scu_sst_r) |
| 313 | { |
| 314 | printf("v53: scu_sst_r\n"); |
| 315 | return 0; |
| 316 | } |
| 317 | |
| 318 | WRITE8_MEMBER(v53_base_device::scu_scm_w) |
| 319 | { |
| 320 | printf("v53: scu_scm_w %02x\n", data); |
| 321 | } |
| 322 | |
| 323 | WRITE8_MEMBER(v53_base_device::scu_smd_w) |
| 324 | { |
| 325 | printf("v53: scu_smd_w %02x\n", data); |
| 326 | } |
| 327 | |
| 328 | READ8_MEMBER(v53_base_device::scu_simk_r) |
| 329 | { |
| 330 | printf("v53: scu_simk_r\n"); |
| 331 | return 0; |
| 332 | } |
| 333 | |
| 334 | WRITE8_MEMBER(v53_base_device::scu_simk_w) |
| 335 | { |
| 336 | printf("v53: scu_simk_w %02x\n", data); |
| 337 | } |
| 338 | |
| 339 | |
| 251 | 340 | /*** TCU ***/ |
| 252 | 341 | |
| 253 | 342 | READ8_MEMBER(v53_base_device::tmu_tst0_r) |
trunk/src/emu/cpu/nec/v53.h
| r244828 | r244829 | |
|---|
| 48 | 48 | DECLARE_WRITE8_MEMBER(tmu_tct2_w); |
| 49 | 49 | DECLARE_WRITE8_MEMBER(tmu_tmd_w); |
| 50 | 50 | |
| 51 | // SCU |
| 52 | DECLARE_READ8_MEMBER(scu_srb_r); |
| 53 | DECLARE_WRITE8_MEMBER(scu_stb_w); |
| 54 | DECLARE_READ8_MEMBER(scu_sst_r); |
| 55 | DECLARE_WRITE8_MEMBER(scu_scm_w); |
| 56 | DECLARE_WRITE8_MEMBER(scu_smd_w); |
| 57 | DECLARE_READ8_MEMBER(scu_simk_r); |
| 58 | DECLARE_WRITE8_MEMBER(scu_simk_w); |
| 59 | |
| 60 | // ICU |
| 61 | DECLARE_READ8_MEMBER(icu_0_r); |
| 62 | DECLARE_WRITE8_MEMBER(icu_0_w); |
| 63 | DECLARE_READ8_MEMBER(icu_1_r); |
| 64 | DECLARE_WRITE8_MEMBER(icu_1_w); |
| 65 | |
| 51 | 66 | void install_peripheral_io(); |
| 52 | 67 | |
| 53 | 68 | const address_space_config m_io_space_config; |