trunk/src/emu/cpu/nec/v53.c
| r244827 | r244828 | |
|---|
| 79 | 79 | WRITE8_MEMBER(v53_base_device::SULA_w) |
| 80 | 80 | { |
| 81 | 81 | printf("v53: SULA_w %02x\n", data); |
| 82 | m_SULA = data; |
| 83 | install_peripheral_io(); |
| 82 | 84 | } |
| 83 | 85 | |
| 84 | 86 | WRITE8_MEMBER(v53_base_device::TULA_w) |
| 85 | 87 | { |
| 86 | 88 | printf("v53: TULA_w %02x\n", data); |
| 89 | m_TULA = data; |
| 90 | install_peripheral_io(); |
| 87 | 91 | } |
| 88 | 92 | |
| 89 | 93 | WRITE8_MEMBER(v53_base_device::IULA_w) |
| 90 | 94 | { |
| 91 | 95 | printf("v53: IULA_w %02x\n", data); |
| 96 | m_IULA = data; |
| 97 | install_peripheral_io(); |
| 92 | 98 | } |
| 93 | 99 | |
| 94 | 100 | WRITE8_MEMBER(v53_base_device::DULA_w) |
| 95 | 101 | { |
| 96 | 102 | printf("v53: DULA_w %02x\n", data); |
| 103 | m_DULA = data; |
| 104 | install_peripheral_io(); |
| 97 | 105 | } |
| 98 | 106 | |
| 99 | 107 | WRITE8_MEMBER(v53_base_device::OPHA_w) |
| 100 | 108 | { |
| 101 | 109 | printf("v53: OPHA_w %02x\n", data); |
| 110 | m_OPHA = data; |
| 111 | install_peripheral_io(); |
| 102 | 112 | } |
| 103 | 113 | |
| 104 | 114 | WRITE8_MEMBER(v53_base_device::OPSEL_w) |
| 105 | 115 | { |
| 106 | 116 | printf("v53: OPSEL_w %02x\n", data); |
| 117 | m_OPSEL = data; |
| 118 | install_peripheral_io(); |
| 107 | 119 | } |
| 108 | 120 | |
| 109 | 121 | WRITE8_MEMBER(v53_base_device::SCTL_w) |
| 110 | 122 | { |
| 123 | // bit 7: unused |
| 124 | // bit 6: unused |
| 125 | // bit 5: unused |
| 126 | // bit 4: SCU input clock source |
| 127 | // bit 3: uPD71037 DMA mode - Carry A20 |
| 128 | // bit 2: uPD71037 DMA mode - Carry A16 |
| 129 | // bit 1: uPD71037 DMA mode enable (otherwise in uPD71071 mode) |
| 130 | // bit 0: Onboard pripheral I/O maps to 8-bit boundaries? (otherwise 16-bit) |
| 131 | |
| 111 | 132 | printf("v53: SCTL_w %02x\n", data); |
| 133 | m_SCTL = data; |
| 134 | install_peripheral_io(); |
| 112 | 135 | } |
| 136 | /* |
| 137 | m_WCY0 = 0x07; |
| 138 | m_WCY1 = 0x77; |
| 139 | m_WCY2 = 0x77; |
| 140 | m_WCY3 = 0x77; |
| 141 | m_WCY4 = 0x77; |
| 142 | m_WMB0 = 0x77; |
| 143 | m_WMB1 = 0x77; |
| 144 | m_WAC = 0x00; |
| 145 | m_TCKS = 0x00; |
| 146 | m_RFC = 0x80; |
| 147 | m_SBCR = 0x00; |
| 148 | m_BRC = 0x00; |
| 149 | // SCU |
| 150 | m_SMD = 0x4b; |
| 151 | m_SCM = 0x00; |
| 152 | m_SIMK = 0x03; |
| 153 | m_SST = 0x04; |
| 154 | // DMA |
| 155 | m_DCH = 0x01; |
| 156 | m_DMD = 0x00; |
| 157 | m_DCC = 0x0000; |
| 158 | m_DST = 0x00; |
| 159 | m_DMK = 0x0f; |
| 160 | */ |
| 113 | 161 | |
| 162 | void v53_base_device::device_reset() |
| 163 | { |
| 164 | nec_common_device::device_reset(); |
| 165 | |
| 166 | m_SCTL = 0x00; |
| 167 | m_OPSEL= 0x00; |
| 168 | |
| 169 | // peripheral addresses |
| 170 | m_SULA = 0x00; |
| 171 | m_TULA = 0x00; |
| 172 | m_IULA = 0x00; |
| 173 | m_DULA = 0x00; |
| 174 | m_OPHA = 0x00; |
| 175 | |
| 176 | } |
| 177 | |
| 178 | void v53_base_device::device_start() |
| 179 | { |
| 180 | nec_common_device::device_start(); |
| 181 | } |
| 182 | |
| 183 | void v53_base_device::install_peripheral_io() |
| 184 | { |
| 185 | // unmap everything in I/O space up to the fixed position registers (we avoid overwriting them, it isn't a valid config) |
| 186 | space(AS_IO).unmap_readwrite(0x0000, 0xfeff); |
| 187 | |
| 188 | // IOAG determines if the handlers used 8-bit or 16-bit access |
| 189 | // the hng64.c games first set everything up in 8-bit mode, then |
| 190 | // do the procedure again in 16-bit mode before using them?! |
| 191 | |
| 192 | int IOAG = m_SCTL & 1; |
| 193 | |
| 194 | if (m_OPSEL & 0x01) // DMA Unit available |
| 195 | { |
| 196 | if (IOAG) // 8-bit |
| 197 | { |
| 198 | |
| 199 | } |
| 200 | else |
| 201 | { |
| 202 | |
| 203 | } |
| 204 | } |
| 205 | |
| 206 | if (m_OPSEL & 0x02) // Interupt Control Unit available |
| 207 | { |
| 208 | if (IOAG) // 8-bit |
| 209 | { |
| 210 | |
| 211 | } |
| 212 | else |
| 213 | { |
| 214 | |
| 215 | } |
| 216 | } |
| 217 | |
| 218 | if (m_OPSEL & 0x04) // Timer Control Unit available |
| 219 | { |
| 220 | UINT16 base = (m_OPHA << 8) | m_TULA; |
| 221 | printf("installing TCU to %04x\n", base); |
| 222 | |
| 223 | if (IOAG) // 8-bit |
| 224 | { |
| 225 | |
| 226 | } |
| 227 | else |
| 228 | { |
| 229 | space(AS_IO).install_readwrite_handler(base+0x00, base+0x01, read8_delegate(FUNC(v53_base_device::tmu_tst0_r), this), write8_delegate(FUNC(v53_base_device::tmu_tct0_w), this), 0x00ff); |
| 230 | space(AS_IO).install_readwrite_handler(base+0x02, base+0x03, read8_delegate(FUNC(v53_base_device::tmu_tst1_r), this), write8_delegate(FUNC(v53_base_device::tmu_tct1_w), this), 0x00ff); |
| 231 | space(AS_IO).install_readwrite_handler(base+0x04, base+0x05, read8_delegate(FUNC(v53_base_device::tmu_tst2_r), this), write8_delegate(FUNC(v53_base_device::tmu_tct2_w), this), 0x00ff); |
| 232 | space(AS_IO).install_write_handler(base+0x06, base+0x07, write8_delegate(FUNC(v53_base_device::tmu_tmd_w), this), 0x00ff); |
| 233 | } |
| 234 | } |
| 235 | |
| 236 | if (m_OPSEL & 0x08) // Serial Control Unit available |
| 237 | { |
| 238 | |
| 239 | if (IOAG) // 8-bit |
| 240 | { |
| 241 | |
| 242 | } |
| 243 | else |
| 244 | { |
| 245 | |
| 246 | } |
| 247 | } |
| 248 | |
| 249 | } |
| 250 | |
| 251 | /*** TCU ***/ |
| 252 | |
| 253 | READ8_MEMBER(v53_base_device::tmu_tst0_r) |
| 254 | { |
| 255 | printf("v53: tmu_tst0_r\n"); |
| 256 | return 0; |
| 257 | } |
| 258 | |
| 259 | WRITE8_MEMBER(v53_base_device::tmu_tct0_w) |
| 260 | { |
| 261 | printf("v53: tmu_tct0_w %02x\n", data); |
| 262 | } |
| 263 | |
| 264 | READ8_MEMBER(v53_base_device::tmu_tst1_r) |
| 265 | { |
| 266 | printf("v53: tmu_tst1_r\n"); |
| 267 | return 0; |
| 268 | } |
| 269 | |
| 270 | WRITE8_MEMBER(v53_base_device::tmu_tct1_w) |
| 271 | { |
| 272 | printf("v53: tmu_tct1_w %02x\n", data); |
| 273 | } |
| 274 | |
| 275 | READ8_MEMBER(v53_base_device::tmu_tst2_r) |
| 276 | { |
| 277 | printf("v53: tmu_tst2_r\n"); |
| 278 | return 0; |
| 279 | } |
| 280 | |
| 281 | WRITE8_MEMBER(v53_base_device::tmu_tct2_w) |
| 282 | { |
| 283 | printf("v53: tmu_tct2_w %02x\n", data); |
| 284 | } |
| 285 | |
| 286 | WRITE8_MEMBER(v53_base_device::tmu_tmd_w) |
| 287 | { |
| 288 | printf("v53: tmu_tmd_w %02x\n", data); |
| 289 | } |
| 290 | |
| 291 | /* General stuff */ |
| 292 | |
| 114 | 293 | static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device ) |
| 115 | | AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BSEL_w, 0x00ff) // 0xffe0 |
| 116 | | AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BADR_w, 0xff00) // 0xffe1 |
| 294 | AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BSEL_w, 0x00ff) // 0xffe0 // uPD71037 DMA mode bank selection register |
| 295 | AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BADR_w, 0xff00) // 0xffe1 // uPD71037 DMA mode bank register peripheral mapping (also uses OPHA) |
| 117 | 296 | // AM_RANGE(0xffe2, 0xffe3) // (reserved , 0x00ff) // 0xffe2 |
| 118 | 297 | // AM_RANGE(0xffe2, 0xffe3) // (reserved , 0xff00) // 0xffe3 |
| 119 | 298 | // AM_RANGE(0xffe4, 0xffe5) // (reserved , 0x00ff) // 0xffe4 |
| r244827 | r244828 | |
|---|
| 121 | 300 | // AM_RANGE(0xffe6, 0xffe7) // (reserved , 0x00ff) // 0xffe6 |
| 122 | 301 | // AM_RANGE(0xffe6, 0xffe7) // (reserved , 0xff00) // 0xffe7 |
| 123 | 302 | // AM_RANGE(0xffe8, 0xffe9) // (reserved , 0x00ff) // 0xffe8 |
| 124 | | AM_RANGE(0xffe8, 0xffe9) AM_WRITE8( BRC_w , 0xff00) // 0xffe9 |
| 125 | | AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WMB0_w, 0x00ff) // 0xffea |
| 126 | | AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WCY1_w, 0xff00) // 0xffeb |
| 127 | | AM_RANGE(0xffec, 0xffed) AM_WRITE8( WCY0_w, 0x00ff) // 0xffec |
| 128 | | AM_RANGE(0xffec, 0xffed) AM_WRITE8( WAC_w, 0xff00) // 0xffed |
| 303 | AM_RANGE(0xffe8, 0xffe9) AM_WRITE8( BRC_w , 0xff00) // 0xffe9 // baud rate counter (used for serial peripheral) |
| 304 | AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WMB0_w, 0x00ff) // 0xffea // waitstate control |
| 305 | AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WCY1_w, 0xff00) // 0xffeb // waitstate control |
| 306 | AM_RANGE(0xffec, 0xffed) AM_WRITE8( WCY0_w, 0x00ff) // 0xffec // waitstate control |
| 307 | AM_RANGE(0xffec, 0xffed) AM_WRITE8( WAC_w, 0xff00) // 0xffed // waitstate control |
| 129 | 308 | // AM_RANGE(0xffee, 0xffef) // (reserved , 0x00ff) // 0xffee |
| 130 | 309 | // AM_RANGE(0xffee, 0xffef) // (reserved , 0xff00) // 0xffef |
| 131 | | AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( TCKS_w, 0x00ff) // 0xfff0 |
| 132 | | AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( SBCR_w, 0xff00) // 0xfff1 |
| 133 | | AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( REFC_w, 0x00ff) // 0xfff2 |
| 134 | | AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( WMB1_w, 0xff00) // 0xfff3 |
| 135 | | AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY2_w, 0x00ff) // 0xfff4 |
| 136 | | AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY3_w, 0xff00) // 0xfff5 |
| 137 | | AM_RANGE(0xfff6, 0xfff7) AM_WRITE8( WCY4_w, 0x00ff) // 0xfff6 |
| 310 | AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( TCKS_w, 0x00ff) // 0xfff0 // timer clocks |
| 311 | AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( SBCR_w, 0xff00) // 0xfff1 // internal clock divider, halt behavior etc. |
| 312 | AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( REFC_w, 0x00ff) // 0xfff2 // ram refresh control |
| 313 | AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( WMB1_w, 0xff00) // 0xfff3 // waitstate control |
| 314 | AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY2_w, 0x00ff) // 0xfff4 // waitstate control |
| 315 | AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY3_w, 0xff00) // 0xfff5 // waitstate control |
| 316 | AM_RANGE(0xfff6, 0xfff7) AM_WRITE8( WCY4_w, 0x00ff) // 0xfff6 // waitstate control |
| 138 | 317 | // AM_RANGE(0xfff6, 0xfff7) // (reserved , 0xff00) // 0xfff7 |
| 139 | | AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( SULA_w, 0x00ff) // 0xfff8 |
| 140 | | AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( TULA_w, 0xff00) // 0xfff9 |
| 141 | | AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( IULA_w, 0x00ff) // 0xfffa |
| 142 | | AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( DULA_w, 0xff00) // 0xfffb |
| 143 | | AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPHA_w, 0x00ff) // 0xfffc |
| 144 | | AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPSEL_w, 0xff00) // 0xfffd |
| 145 | | AM_RANGE(0xfffe, 0xffff) AM_WRITE8( SCTL_w, 0x00ff) // 0xfffe |
| 318 | AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( SULA_w, 0x00ff) // 0xfff8 // peripheral mapping |
| 319 | AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( TULA_w, 0xff00) // 0xfff9 // peripheral mapping |
| 320 | AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( IULA_w, 0x00ff) // 0xfffa // peripheral mapping |
| 321 | AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( DULA_w, 0xff00) // 0xfffb // peripheral mapping |
| 322 | AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPHA_w, 0x00ff) // 0xfffc // peripheral mapping (upper bits, common) |
| 323 | AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPSEL_w, 0xff00) // 0xfffd // peripheral enabling |
| 324 | AM_RANGE(0xfffe, 0xffff) AM_WRITE8( SCTL_w, 0x00ff) // 0xfffe // peripheral configuration (& byte / word mapping) |
| 146 | 325 | // AM_RANGE(0xfffe, 0xffff) // (reserved , 0xff00) // 0xffff |
| 147 | 326 | ADDRESS_MAP_END |
| 148 | 327 | |