branches/alto2/src/emu/cpu/alto2/a2disp.c
r26331 | r26332 | |
96 | 96 | * </PRE> |
97 | 97 | */ |
98 | 98 | |
| 99 | //!< test the HBLANK (horizontal blanking) signal in PROM a63 being high |
| 100 | #define A63_HBLANK_HI(a) ((a & A63_HBLANK) ? true : false) |
| 101 | |
| 102 | //!< test the HSYNC (horizontal synchonisation) signal in PROM a63 being high |
| 103 | #define A63_HSYNC_HI(a) ((a & A63_HSYNC) ? true : false) |
| 104 | |
| 105 | //!< test the SCANEND (scanline end) signal in PROM a63 being high |
| 106 | #define A63_SCANEND_HI(a) ((a & A63_SCANEND) ? true : false) |
| 107 | |
| 108 | //!< test the HLCGATE (horz. line counter gate) signal in PROM a63 being high |
| 109 | #define A63_HLCGATE_HI(a) ((a & A63_HLCGATE) ? true : false) |
| 110 | |
99 | 111 | /** |
100 | 112 | * @brief PROM a66 is a 256x4 bit (type 3601) |
101 | 113 | * <PRE> |
r26331 | r26332 | |
109 | 121 | * </PRE> |
110 | 122 | */ |
111 | 123 | |
| 124 | //! test the VSYNC (vertical synchronisation) signal in PROM a66 being high |
| 125 | #define A66_VSYNC(a) (a & (HLC1024 ? A66_VSYNC_ODD : A66_VSYNC_EVEN) ? false : true) |
| 126 | |
| 127 | //! test the VBLANK (vertical blanking) signal in PROM a66 being high |
| 128 | #define A66_VBLANK(a) (a & (HLC1024 ? A66_VBLANK_ODD : A66_VBLANK_EVEN) ? false : true) |
| 129 | |
112 | 130 | /** |
113 | 131 | * @brief double the bits for a byte (left and right of display word) to a word |
114 | 132 | */ |
r26331 | r26332 | |
150 | 168 | //! update the internal bitmap to a byte array |
151 | 169 | void alto2_cpu_device::update_bitmap_word(int x, int y, UINT16 word) |
152 | 170 | { |
153 | | const UINT8 white = 0; |
154 | | const UINT8 black = 1; |
155 | 171 | UINT8* pix = m_dsp.scanline[y] + x; |
156 | | *pix++ = (word & 0100000) ? black : white; |
157 | | *pix++ = (word & 0040000) ? black : white; |
158 | | *pix++ = (word & 0020000) ? black : white; |
159 | | *pix++ = (word & 0010000) ? black : white; |
160 | | *pix++ = (word & 0004000) ? black : white; |
161 | | *pix++ = (word & 0002000) ? black : white; |
162 | | *pix++ = (word & 0001000) ? black : white; |
163 | | *pix++ = (word & 0000400) ? black : white; |
164 | | *pix++ = (word & 0000200) ? black : white; |
165 | | *pix++ = (word & 0000100) ? black : white; |
166 | | *pix++ = (word & 0000040) ? black : white; |
167 | | *pix++ = (word & 0000020) ? black : white; |
168 | | *pix++ = (word & 0000010) ? black : white; |
169 | | *pix++ = (word & 0000004) ? black : white; |
170 | | *pix++ = (word & 0000002) ? black : white; |
171 | | *pix++ = (word & 0000001) ? black : white; |
| 172 | *pix++ = (word >> 15) & 1; |
| 173 | *pix++ = (word >> 14) & 1; |
| 174 | *pix++ = (word >> 13) & 1; |
| 175 | *pix++ = (word >> 12) & 1; |
| 176 | *pix++ = (word >> 11) & 1; |
| 177 | *pix++ = (word >> 10) & 1; |
| 178 | *pix++ = (word >> 9) & 1; |
| 179 | *pix++ = (word >> 8) & 1; |
| 180 | *pix++ = (word >> 7) & 1; |
| 181 | *pix++ = (word >> 6) & 1; |
| 182 | *pix++ = (word >> 5) & 1; |
| 183 | *pix++ = (word >> 4) & 1; |
| 184 | *pix++ = (word >> 3) & 1; |
| 185 | *pix++ = (word >> 2) & 1; |
| 186 | *pix++ = (word >> 1) & 1; |
| 187 | *pix++ = (word >> 0) & 1; |
172 | 188 | } |
173 | 189 | |
174 | 190 | #define HLC1 ((m_dsp.hlc >> 0) & 1) //!< horizontal line counter bit 0 |
r26331 | r26332 | |
189 | 205 | //!< helper to extract A3-A0 from a PROM a63 value |
190 | 206 | #define A63_NEXT(n) ((n >> 2) & 017) |
191 | 207 | |
192 | | //!< test the HBLANK (horizontal blanking) signal in PROM a63 being high |
193 | | #define A63_HBLANK_HI(a) ((a & A63_HBLANK) ? true : false) |
194 | | //!< test the HBLANK (horizontal blanking) signal in PROM a63 being low |
195 | | #define A63_HBLANK_LO(a) ((a & A63_HBLANK) ? false : true) |
196 | | //!< test the HSYNC (horizontal synchonisation) signal in PROM a63 being high |
197 | | #define A63_HSYNC_HI(a) ((a & A63_HSYNC) ? true : false) |
198 | | //!< test the HSYNC (horizontal synchonisation) signal in PROM a63 being low |
199 | | #define A63_HSYNC_LO(a) ((a & A63_HSYNC) ? false : true) |
200 | | //!< test the SCANEND (scanline end) signal in PROM a63 being high |
201 | | #define A63_SCANEND_HI(a) ((a & A63_SCANEND) ? true : false) |
202 | | //!< test the SCANEND (scanline end) signal in PROM a63 being low |
203 | | #define A63_SCANEND_LO(a) ((a & A63_SCANEND) ? false : true) |
204 | | //!< test the HLCGATE (horz. line counter gate) signal in PROM a63 being high |
205 | | #define A63_HLCGATE_HI(a) ((a & A63_HLCGATE) ? true : false) |
206 | | //!< test the HLCGATE (horz. line counter gate) signal in PROM a63 being low |
207 | | #define A63_HLCGATE_LO(a) ((a & A63_HLCGATE) ? false : true) |
208 | | |
209 | 208 | /** |
210 | 209 | * @brief unload the next word from the display FIFO and shift it to the screen |
211 | 210 | */ |
r26331 | r26332 | |
302 | 301 | m_task_wakeup |= 1 << task_ether; |
303 | 302 | } |
304 | 303 | } |
305 | | UINT8 a66 = 017; |
306 | | if (HLC256 || HLC512) { |
307 | | // PROM a66 is disabled, if any of HLC256 or HLC512 are high |
308 | | } else { |
309 | | // PROM a66 address lines are connected the HLC1 to HLC128 signals |
310 | | a66 = m_disp_a66[m_dsp.hlc & 0377]; |
311 | | } |
| 304 | // PROM a66 is disabled, if any of HLC256 or HLC512 are high |
| 305 | UINT8 a66 = (HLC256 || HLC512) ? 017 : m_disp_a66[m_dsp.hlc & 0377]; |
312 | 306 | |
313 | 307 | // next address from PROM a63, use A4 from HLC1 |
314 | 308 | UINT8 next = ((HLC1 ^ 1) << 4) | A63_NEXT(a63); |
315 | 309 | |
316 | | if (A66_VBLANK_HI(a66, HLC1024)) { |
| 310 | if (A66_VBLANK(a66)) { |
317 | 311 | /* VBLANK: remember hlc */ |
318 | | m_dsp.vblank = m_dsp.hlc | 1; |
| 312 | m_dsp.vblank = m_dsp.hlc & ~02000; |
319 | 313 | |
320 | 314 | LOG((LOG_DISPL,1, " VBLANK")); |
321 | 315 | |
322 | 316 | /* VSYNC is always within VBLANK */ |
323 | | if (A66_VSYNC_HI(a66, HLC1024)) { |
324 | | if (A66_VSYNC_LO(m_dsp.a66, HLC1024)) { |
| 317 | if (A66_VSYNC(a66)) { |
| 318 | if (!A66_VSYNC(m_dsp.a66)) { |
325 | 319 | LOG((LOG_DISPL,1, " VSYNC/ (wake DVT)")); |
326 | 320 | /* |
327 | 321 | * The display vertical task DVT is awakened once per field, |
r26331 | r26332 | |
334 | 328 | } |
335 | 329 | } |
336 | 330 | } else { |
337 | | if (A66_VBLANK_HI(m_dsp.a66, HLC1024)) { |
| 331 | if (A66_VBLANK(m_dsp.a66)) { |
338 | 332 | /** |
339 | 333 | * VBLANKPULSE: |
340 | 334 | * The display horizontal task DHT is awakened once at the |
r26331 | r26332 | |
345 | 339 | * next field. |
346 | 340 | */ |
347 | 341 | LOG((LOG_DISPL,1, " VBLANKPULSE (wake DHT)")); |
348 | | m_dsp.dht_blocks = 0; |
349 | | m_dsp.dwt_blocks = 0; |
| 342 | m_dsp.dht_blocks = false; |
| 343 | m_dsp.dwt_blocks = false; |
350 | 344 | m_task_wakeup |= 1 << task_dht; |
351 | 345 | /* |
352 | 346 | * VBLANKPULSE also resets the cursor task block flip flop, |
353 | 347 | * which is built from two NAND gates a40c and a40d (74H01). |
354 | 348 | */ |
355 | | m_dsp.curt_blocks = 0; |
| 349 | m_dsp.curt_blocks = false; |
356 | 350 | } |
357 | | if (A63_HBLANK_LO(a63) && A63_HBLANK_HI(m_dsp.a63)) { |
| 351 | if (!A63_HBLANK_HI(a63) && A63_HBLANK_HI(m_dsp.a63)) { |
358 | 352 | /* falling edge of a63 HBLANK starts unload */ |
359 | 353 | LOG((LOG_DISPL,1, " HBLANK\\ UNLOAD")); |
360 | 354 | m_unload_time = ALTO2_DISPLAY_BITTIME(m_dsp.halfclock ? 32 : 16); |
r26331 | r26332 | |
374 | 368 | * are generated. |
375 | 369 | */ |
376 | 370 | if (!m_dsp.dwt_blocks && !m_dsp.dht_blocks && FIFO_STOPWAKE_0() != 0) { |
377 | | if (!(m_task_wakeup & (1 << task_dwt))) { |
378 | | m_task_wakeup |= 1 << task_dwt; |
379 | | LOG((LOG_DISPL,1, " (wake DWT)")); |
380 | | } |
| 371 | m_task_wakeup |= 1 << task_dwt; |
| 372 | LOG((LOG_DISPL,1, " (wake DWT)")); |
381 | 373 | } |
382 | 374 | |
383 | 375 | if (A63_SCANEND_HI(a63)) { |
r26331 | r26332 | |
385 | 377 | m_task_wakeup &= ~(1 << task_dwt); |
386 | 378 | } |
387 | 379 | |
388 | | LOG((LOG_DISPL,1, "%s", (a63 & A63_HBLANK) ? " HBLANK": "")); |
| 380 | LOG((LOG_DISPL,1, "%s", A63_HBLANK_HI(a63) ? " HBLANK": "")); |
389 | 381 | |
390 | 382 | if (A63_HSYNC_HI(a63)) { |
391 | | if (A63_HSYNC_LO(m_dsp.a63)) { |
| 383 | if (!A63_HSYNC_HI(m_dsp.a63)) { |
392 | 384 | LOG((LOG_DISPL,1, " HSYNC/ (CLRBUF)")); |
393 | 385 | /* |
394 | 386 | * The hardware sets the buffer empty and clears the DWT block |
r26331 | r26332 | |
397 | 389 | */ |
398 | 390 | m_dsp.fifo_wr = 0; |
399 | 391 | m_dsp.fifo_rd = 0; |
400 | | m_dsp.dwt_blocks = 0; |
| 392 | m_dsp.dwt_blocks = false; |
401 | 393 | /* now take the new values from the last setmode */ |
402 | 394 | m_dsp.inverse = GET_SETMODE_INVERSE(m_dsp.setmode) ? 0xffff : 0x0000; |
403 | 395 | m_dsp.halfclock = GET_SETMODE_SPEEDY(m_dsp.setmode); |
r26331 | r26332 | |
406 | 398 | } else { |
407 | 399 | LOG((LOG_DISPL,1, " HSYNC")); |
408 | 400 | } |
409 | | } else if (A63_SCANEND_HI(a63)) { |
410 | | /* |
411 | | * CLRBUF' also resets the 2nd cursor task block flip flop, |
412 | | * which is built from two NAND gates a30c and a30d (74H00). |
413 | | * If both flip flops are reset, the NOR gate a20d (74S02) |
414 | | * decodes this as WAKECURT signal. |
415 | | */ |
416 | | m_dsp.curt_wakeup = 1; |
417 | 401 | } |
| 402 | // FIXME: try at the end of HSYNC |
| 403 | if (A63_HSYNC_HI(m_dsp.a63) && !A63_HSYNC_HI(a63)) { |
| 404 | /* |
| 405 | * CLRBUF' also resets the 2nd cursor task block flip flop, |
| 406 | * which is built from two NAND gates a30c and a30d (74H00). |
| 407 | * If both flip flops are reset, the NOR gate a20d (74S02) |
| 408 | * decodes this as WAKECURT signal. |
| 409 | */ |
| 410 | m_dsp.curt_wakeup = true; |
| 411 | } |
418 | 412 | |
419 | 413 | |
420 | 414 | LOG((LOG_DISPL,1, " NEXT:%03o\n", next)); |
branches/alto2/src/emu/cpu/alto2/a2disp.h
r26331 | r26332 | |
185 | 185 | UINT16 fifo[ALTO2_DISPLAY_FIFO]; //!< display word fifo |
186 | 186 | UINT8 fifo_wr; //!< fifo input pointer (4-bit) |
187 | 187 | UINT8 fifo_rd; //!< fifo output pointer (4-bit) |
188 | | UINT8 dht_blocks; //!< set non-zero, if the DHT executed BLOCK |
189 | | UINT8 dwt_blocks; //!< set non-zero, if the DWT executed BLOCK |
190 | | UINT8 curt_blocks; //!< set non-zero, if the CURT executed BLOCK |
191 | | UINT8 curt_wakeup; //!< set non-zero, if CURT wakeups are generated |
| 188 | bool dht_blocks; //!< set non-zero, if the DHT executed BLOCK |
| 189 | bool dwt_blocks; //!< set non-zero, if the DWT executed BLOCK |
| 190 | bool curt_blocks; //!< set non-zero, if the CURT executed BLOCK |
| 191 | bool curt_wakeup; //!< set non-zero, if CURT wakeups are generated |
192 | 192 | UINT16 vblank; //!< most recent HLC with VBLANK still high (11-bit) |
193 | 193 | UINT16 xpreg; //!< cursor cursor x position register (10-bit) |
194 | 194 | UINT16 csr; //!< cursor shift register (16-bit) |
r26331 | r26332 | |
297 | 297 | A66_VBLANK_EVEN = (1 << 3) |
298 | 298 | }; |
299 | 299 | |
300 | | //! test the VSYNC (vertical synchronisation) signal in PROM a66 being high |
301 | | static inline bool A66_VSYNC_HI(UINT8 a, int hlc1024) { return a & (hlc1024 ? A66_VSYNC_ODD : A66_VSYNC_EVEN) ? false : true; } |
302 | | //! test the VSYNC (vertical synchronisation) signal in PROM a66 being low |
303 | | static inline bool A66_VSYNC_LO(UINT8 a, int hlc1024) { return a & (hlc1024 ? A66_VSYNC_ODD : A66_VSYNC_EVEN) ? true : false; } |
304 | | //! test the VBLANK (vertical blanking) signal in PROM a66 being high |
305 | | static inline bool A66_VBLANK_HI(UINT8 a, int hlc1024) { return a & (hlc1024 ? A66_VBLANK_ODD : A66_VBLANK_EVEN) ? false : true; } |
306 | | //! test the VBLANK (vertical blanking) signal in PROM a66 being low |
307 | | static inline bool A66_VBLANK_LO(UINT8 a, int hlc1024) { return a & (hlc1024 ? A66_VBLANK_ODD : A66_VBLANK_EVEN) ? true : false; } |
308 | | |
309 | 300 | void update_bitmap_word(int x, int y, UINT16 word); //!< update a word in the screen bitmap |
310 | 301 | void unload_word(); //!< unload the next word from the display FIFO and shift it to the screen |
311 | 302 | void display_state_machine(); //!< function called by the CPU to enter the next display state |
branches/alto2/src/emu/cpu/alto2/alto2cpu.c
r26331 | r26332 | |
606 | 606 | /* dmap */ DMAP_DEFAULT, |
607 | 607 | /* dand */ KEEP, |
608 | 608 | /* type */ sizeof(UINT32) |
609 | | } |
| 609 | } |
610 | 610 | #endif // (UCODE_ROM_PAGES > 1) |
611 | 611 | }; |
612 | 612 | |
r26331 | r26332 | |
1297 | 1297 | // FIXME |
1298 | 1298 | void alto2_cpu_device::device_reset() |
1299 | 1299 | { |
1300 | | soft_reset(); |
| 1300 | soft_reset(); |
1301 | 1301 | } |
1302 | 1302 | |
1303 | 1303 | /** |
r26331 | r26332 | |
1640 | 1640 | */ |
1641 | 1641 | WRITE16_MEMBER( alto2_cpu_device::noop_w ) |
1642 | 1642 | { |
1643 | | LOG((LOG_CPU,0," MMIO wr %s\n", memory_range_name(offset))); |
| 1643 | LOG((LOG_CPU,0," MMIO wr %s\n", memory_range_name(offset))); |
1644 | 1644 | } |
1645 | 1645 | |
1646 | 1646 | /** |
r26331 | r26332 | |
2475 | 2475 | /** @brief flag that tells whether to load the T register from BUS or ALU */ |
2476 | 2476 | #define TSELECT A10_TSELECT |
2477 | 2477 | |
2478 | | /** @brief flag that tells wheter operation was 0: logic (M=1) or 1: arithmetic (M=0) */ |
2479 | | #define ALUM2 A10_ALUM |
| 2478 | /** @brief flag that tells wheter operation was 0: arithmetic (M=0) or 1: logic (M=1) */ |
| 2479 | #define ALUM A10_ALUM |
2480 | 2480 | |
2481 | 2481 | /** @brief execute the CPU for at most nsecs nano seconds */ |
2482 | 2482 | void alto2_cpu_device::execute_run() |
r26331 | r26332 | |
2487 | 2487 | do { |
2488 | 2488 | int do_bs, flags; |
2489 | 2489 | |
2490 | | /* |
2491 | | * Subtract the microcycle time from the display time accu. |
2492 | | * If it underflows, call the display state machine and add |
2493 | | * the time for 24 pixel clocks to the accu. |
2494 | | * This is very close to every seventh CPU cycle. |
2495 | | */ |
2496 | | m_dsp_time -= ALTO2_UCYCLE; |
2497 | | if (m_dsp_time < 0) { |
2498 | | display_state_machine(); |
2499 | | m_dsp_time += ALTO2_DISPLAY_BITTIME(24); |
2500 | | } |
2501 | | if (m_unload_time >= 0) { |
2502 | | /* |
2503 | | * Subtract the microcycle time from the unload time accu. |
2504 | | * If it underflows, call the unload word function which adds |
2505 | | * the time for 16 or 32 pixel clocks to the accu, or ends |
2506 | | * the unloading by leaving m_unload_time at -1. |
2507 | | */ |
2508 | | m_unload_time -= ALTO2_UCYCLE; |
2509 | | if (m_unload_time < 0) |
2510 | | unload_word(); |
2511 | | } |
2512 | | #if (USE_BITCLK_TIMER == 0) |
2513 | | if (m_bitclk_time >= 0) { |
2514 | | /* |
2515 | | * Subtract the microcycle time from the bitclk time accu. |
2516 | | * If it underflows, call the disk bitclk function which adds |
2517 | | * the time for one bit as clocks to the accu, or ends |
2518 | | * the bitclk sequence by leaving m_bitclk_time at -1. |
2519 | | */ |
2520 | | m_bitclk_time -= ALTO2_UCYCLE; |
2521 | | disk_bitclk(0, m_bitclk_index); |
2522 | | } |
2523 | | #endif |
2524 | | |
2525 | 2490 | m_cycle++; |
2526 | 2491 | /* nano seconds per cycle */ |
2527 | 2492 | m_pico_time[m_task] += ALTO2_UCYCLE; |
r26331 | r26332 | |
2616 | 2581 | UINT8 a10 = m_alu_a10[(m_emu.skip << 4) | m_d_aluf]; |
2617 | 2582 | UINT32 alu = alu_74181(m_bus, m_t, a10); |
2618 | 2583 | m_aluc0 = (alu >> 16) & 1; |
2619 | | flags = (a10 ^ ALUM2) & (TSELECT | ALUM2); |
| 2584 | flags = a10 & (TSELECT | ALUM); |
2620 | 2585 | m_alu = static_cast<UINT16>(alu); |
2621 | 2586 | #else |
2622 | 2587 | UINT32 alu; |
r26331 | r26332 | |
2631 | 2596 | case aluf_bus__alut: |
2632 | 2597 | alu = m_bus; |
2633 | 2598 | m_aluc0 = 1; |
2634 | | flags = 0; |
| 2599 | flags = ALUM; |
2635 | 2600 | LOG((LOG_CPU,2," ALU← BUS (%#o := %#o)\n", alu, m_bus)); |
2636 | 2601 | break; |
2637 | 2602 | |
r26331 | r26332 | |
2644 | 2609 | case aluf_treg: |
2645 | 2610 | alu = m_t; |
2646 | 2611 | m_aluc0 = 1; |
2647 | | flags = 0; |
| 2612 | flags = ALUM; |
2648 | 2613 | LOG((LOG_CPU,2," ALU← T (%#o := %#o)\n", alu, m_t)); |
2649 | 2614 | break; |
2650 | 2615 | |
r26331 | r26332 | |
2657 | 2622 | case aluf_bus_or_t__alut: |
2658 | 2623 | alu = m_bus | m_t; |
2659 | 2624 | m_aluc0 = 1; |
2660 | | flags = TSELECT; |
| 2625 | flags = ALUM | TSELECT; |
2661 | 2626 | LOG((LOG_CPU,2," ALU← BUS OR T (%#o := %#o | %#o)\n", alu, m_bus, m_t)); |
2662 | 2627 | break; |
2663 | 2628 | |
r26331 | r26332 | |
2670 | 2635 | case aluf_bus_and_t: |
2671 | 2636 | alu = m_bus & m_t; |
2672 | 2637 | m_aluc0 = 1; |
2673 | | flags = 0; |
| 2638 | flags = ALUM; |
2674 | 2639 | LOG((LOG_CPU,2," ALU← BUS AND T (%#o := %#o & %#o)\n", alu, m_bus, m_t)); |
2675 | 2640 | break; |
2676 | 2641 | |
r26331 | r26332 | |
2683 | 2648 | case aluf_bus_xor_t: |
2684 | 2649 | alu = m_bus ^ m_t; |
2685 | 2650 | m_aluc0 = 1; |
2686 | | flags = 0; |
| 2651 | flags = ALUM; |
2687 | 2652 | LOG((LOG_CPU,2," ALU← BUS XOR T (%#o := %#o ^ %#o)\n", alu, m_bus, m_t)); |
2688 | 2653 | break; |
2689 | 2654 | |
r26331 | r26332 | |
2696 | 2661 | case aluf_bus_plus_1__alut: |
2697 | 2662 | alu = m_bus + 1; |
2698 | 2663 | m_aluc0 = (alu >> 16) & 1; |
2699 | | flags = ALUM2 | TSELECT; |
| 2664 | flags = TSELECT; |
2700 | 2665 | LOG((LOG_CPU,2," ALU← BUS + 1 (%#o := %#o + 1)\n", alu, m_bus)); |
2701 | 2666 | break; |
2702 | 2667 | |
r26331 | r26332 | |
2709 | 2674 | case aluf_bus_minus_1__alut: |
2710 | 2675 | alu = m_bus + 0177777; |
2711 | 2676 | m_aluc0 = (~alu >> 16) & 1; |
2712 | | flags = ALUM2 | TSELECT; |
| 2677 | flags = TSELECT; |
2713 | 2678 | LOG((LOG_CPU,2," ALU← BUS - 1 (%#o := %#o - 1)\n", alu, m_bus)); |
2714 | 2679 | break; |
2715 | 2680 | |
r26331 | r26332 | |
2722 | 2687 | case aluf_bus_plus_t: |
2723 | 2688 | alu = m_bus + m_t; |
2724 | 2689 | m_aluc0 = (alu >> 16) & 1; |
2725 | | flags = ALUM2; |
| 2690 | flags = 0; |
2726 | 2691 | LOG((LOG_CPU,2," ALU← BUS + T (%#o := %#o + %#o)\n", alu, m_bus, m_t)); |
2727 | 2692 | break; |
2728 | 2693 | |
r26331 | r26332 | |
2735 | 2700 | case aluf_bus_minus_t: |
2736 | 2701 | alu = m_bus + ~m_t + 1; |
2737 | 2702 | m_aluc0 = (~alu >> 16) & 1; |
2738 | | flags = ALUM2; |
| 2703 | flags = 0; |
2739 | 2704 | LOG((LOG_CPU,2," ALU← BUS - T (%#o := %#o - %#o)\n", alu, m_bus, m_t)); |
2740 | 2705 | break; |
2741 | 2706 | |
r26331 | r26332 | |
2748 | 2713 | case aluf_bus_minus_t_minus_1: |
2749 | 2714 | alu = m_bus + ~m_t; |
2750 | 2715 | m_aluc0 = (~alu >> 16) & 1; |
2751 | | flags = ALUM2; |
| 2716 | flags = 0; |
2752 | 2717 | LOG((LOG_CPU,2," ALU← BUS - T - 1 (%#o := %#o - %#o - 1)\n", alu, m_bus, m_t)); |
2753 | 2718 | break; |
2754 | 2719 | |
r26331 | r26332 | |
2761 | 2726 | case aluf_bus_plus_t_plus_1__alut: |
2762 | 2727 | alu = m_bus + m_t + 1; |
2763 | 2728 | m_aluc0 = (alu >> 16) & 1; |
2764 | | flags = ALUM2 | TSELECT; |
| 2729 | flags = TSELECT; |
2765 | 2730 | LOG((LOG_CPU,2," ALU← BUS + T + 1 (%#o := %#o + %#o + 1)\n", alu, m_bus, m_t)); |
2766 | 2731 | break; |
2767 | 2732 | |
r26331 | r26332 | |
2774 | 2739 | case aluf_bus_plus_skip__alut: |
2775 | 2740 | alu = m_bus + m_emu.skip; |
2776 | 2741 | m_aluc0 = (alu >> 16) & 1; |
2777 | | flags = ALUM2 | TSELECT; |
| 2742 | flags = TSELECT; |
2778 | 2743 | LOG((LOG_CPU,2," ALU← BUS + SKIP (%#o := %#o + %#o)\n", alu, m_bus, m_emu.skip)); |
2779 | 2744 | break; |
2780 | 2745 | |
r26331 | r26332 | |
2787 | 2752 | case aluf_bus_and_t__alut: |
2788 | 2753 | alu = m_bus & m_t; |
2789 | 2754 | m_aluc0 = 1; |
2790 | | flags = TSELECT; |
| 2755 | flags = ALUM | TSELECT; |
2791 | 2756 | LOG((LOG_CPU,2," ALU← BUS,T (%#o := %#o & %#o)\n", alu, m_bus, m_t)); |
2792 | 2757 | break; |
2793 | 2758 | |
r26331 | r26332 | |
2800 | 2765 | case aluf_bus_and_not_t: |
2801 | 2766 | alu = m_bus & ~m_t; |
2802 | 2767 | m_aluc0 = 1; |
2803 | | flags = 0; |
| 2768 | flags = ALUM; |
2804 | 2769 | LOG((LOG_CPU,2," ALU← BUS AND NOT T (%#o := %#o & ~%#o)\n", alu, m_bus, m_t)); |
2805 | 2770 | break; |
2806 | 2771 | |
r26331 | r26332 | |
2813 | 2778 | case aluf_undef_16: |
2814 | 2779 | alu = m_bus; |
2815 | 2780 | m_aluc0 = 1; |
2816 | | flags = TSELECT; |
| 2781 | flags = ALUM | TSELECT; |
2817 | 2782 | LOG((LOG_CPU,0," ALU← 0 (illegal aluf in task %s, mpc:%05o aluf:%02o)\n", task_name(m_task), m_mpc, aluf)); |
2818 | 2783 | break; |
2819 | 2784 | |
r26331 | r26332 | |
2827 | 2792 | default: |
2828 | 2793 | alu = m_bus; |
2829 | 2794 | m_aluc0 = 1; |
2830 | | flags = TSELECT; |
| 2795 | flags = ALUM | TSELECT; |
2831 | 2796 | LOG((LOG_CPU,0," ALU← 0 (illegal aluf in task %s, mpc:%05o aluf:%02o)\n", task_name(m_task), m_mpc, aluf)); |
2832 | 2797 | } |
2833 | 2798 | m_alu = static_cast<UINT16>(alu); |
r26331 | r26332 | |
2853 | 2818 | // update L register and LALUC0, and also M register, if a RAM related task is active |
2854 | 2819 | if (m_d_loadl) { |
2855 | 2820 | m_l = m_alu; // load L from ALU |
2856 | | if (flags & ALUM2) { |
2857 | | m_laluc0 = m_aluc0; |
| 2821 | if (flags & ALUM) { |
| 2822 | m_laluc0 = 0; // logic operation - latch 0 |
| 2823 | LOG((LOG_CPU,2, " L← ALU (%#o); LALUC0← %o\n", m_alu, 0)); |
| 2824 | } else { |
| 2825 | m_laluc0 = m_aluc0; // logic operation - latch carry |
2858 | 2826 | LOG((LOG_CPU,2, " L← ALU (%#o); LALUC0← ALUC0 (%o)\n", m_alu, m_aluc0)); |
2859 | | } else { |
2860 | | m_laluc0 = 0; |
2861 | | LOG((LOG_CPU,2, " L← ALU (%#o); LALUC0← %o\n", m_alu, 0)); |
2862 | 2827 | } |
2863 | 2828 | if (m_ram_related[m_task]) { |
2864 | 2829 | m_m = m_alu; // load M from ALU, if 'GOODTASK' |
r26331 | r26332 | |
2867 | 2832 | } |
2868 | 2833 | } |
2869 | 2834 | |
2870 | | // update T register, if LOADT is set |
2871 | | if (m_d_loadt) { |
2872 | | m_cram_addr = m_alu; // latch CRAM address |
2873 | | if (flags & TSELECT) { |
2874 | | m_t = m_alu; // T source is ALU |
2875 | | LOG((LOG_CPU,2, " T← ALU (%#o)\n", m_alu)); |
2876 | | } else { |
2877 | | m_t = m_bus; // T source is BUS |
2878 | | LOG((LOG_CPU,2, " T← BUS (%#o)\n", m_bus)); |
2879 | | } |
2880 | | } |
2881 | | |
2882 | 2835 | if (m_task != m_next2_task) { |
2883 | 2836 | /* switch now? */ |
2884 | 2837 | if (m_task == m_next_task) { |
r26331 | r26332 | |
2897 | 2850 | ((*this).*m_active_callback[m_task])(); |
2898 | 2851 | } |
2899 | 2852 | } |
| 2853 | |
| 2854 | // update T register, if LOADT is set |
| 2855 | if (m_d_loadt) { |
| 2856 | m_cram_addr = m_alu; // latch CRAM address |
| 2857 | if (flags & TSELECT) { |
| 2858 | m_t = m_alu; // T source is ALU |
| 2859 | LOG((LOG_CPU,2, " T← ALU (%#o)\n", m_alu)); |
| 2860 | } else { |
| 2861 | m_t = m_bus; // T source is BUS |
| 2862 | LOG((LOG_CPU,2, " T← BUS (%#o)\n", m_bus)); |
| 2863 | } |
| 2864 | } |
| 2865 | |
| 2866 | /* |
| 2867 | * Subtract the microcycle time from the display time accu. |
| 2868 | * If it underflows, call the display state machine and add |
| 2869 | * the time for 24 pixel clocks to the accu. |
| 2870 | * This is very close to every seventh CPU cycle. |
| 2871 | */ |
| 2872 | m_dsp_time -= ALTO2_UCYCLE; |
| 2873 | if (m_dsp_time < 0) { |
| 2874 | display_state_machine(); |
| 2875 | m_dsp_time += ALTO2_DISPLAY_BITTIME(24); |
| 2876 | } |
| 2877 | if (m_unload_time >= 0) { |
| 2878 | /* |
| 2879 | * Subtract the microcycle time from the unload time accu. |
| 2880 | * If it underflows, call the unload word function which adds |
| 2881 | * the time for 16 or 32 pixel clocks to the accu, or ends |
| 2882 | * the unloading by leaving m_unload_time at -1. |
| 2883 | */ |
| 2884 | m_unload_time -= ALTO2_UCYCLE; |
| 2885 | if (m_unload_time < 0) |
| 2886 | unload_word(); |
| 2887 | } |
| 2888 | #if (USE_BITCLK_TIMER == 0) |
| 2889 | if (m_bitclk_time >= 0) { |
| 2890 | /* |
| 2891 | * Subtract the microcycle time from the bitclk time accu. |
| 2892 | * If it underflows, call the disk bitclk function which adds |
| 2893 | * the time for one bit as clocks to the accu, or ends |
| 2894 | * the bitclk sequence by leaving m_bitclk_time at -1. |
| 2895 | */ |
| 2896 | m_bitclk_time -= ALTO2_UCYCLE; |
| 2897 | disk_bitclk(0, m_bitclk_index); |
| 2898 | } |
| 2899 | #endif |
2900 | 2900 | } while (m_icount-- > 0); |
2901 | 2901 | |
2902 | 2902 | /* save this task's mpc and address modifier */ |
branches/alto2/src/emu/cpu/alto2/a2disk.c
r26331 | r26332 | |
927 | 927 | */ |
928 | 928 | void alto2_cpu_device::disk_block(int task) |
929 | 929 | { |
930 | | kwd_timing(m_dsk.bitclk, m_dsk.datin, task); |
| 930 | kwd_timing(m_dsk.bitclk, m_dsk.datin, task); |
931 | 931 | } |
932 | 932 | |
933 | 933 | /** |
r26331 | r26332 | |
1529 | 1529 | * </PRE> |
1530 | 1530 | */ |
1531 | 1531 | if (m_dsk.krwc & RWC_WRITE) { |
1532 | | bit = (m_dsk.shiftout >> 15) & 1; |
1533 | | kwd_timing(clk, bit, 0); |
1534 | 1532 | if (GET_KCOM_XFEROFF(m_dsk.kcom)) { |
1535 | 1533 | /* do anything, if the transfer is off? */ |
| 1534 | kwd_timing(clk, 1, 0); |
1536 | 1535 | } else { |
| 1536 | bit = (m_dsk.shiftout >> 15) & 1; |
| 1537 | kwd_timing(clk, bit, 0); |
1537 | 1538 | LOG((LOG_DISK,7," BITCLK#%d bit:%d (write) @%lldns\n", arg, bit, ntime())); |
1538 | 1539 | if (clk) |
1539 | 1540 | dhd->wr_data(arg, bit); |
r26331 | r26332 | |
1566 | 1567 | } |
1567 | 1568 | #else |
1568 | 1569 | if (++arg < dhd->bits_per_sector()) { |
1569 | | if (!m_dsk.bitclk_time) { |
1570 | | // get bit time in pico seconds |
1571 | | m_dsk.bitclk_time = static_cast<int>(dhd->bit_time().as_attoseconds() / 1000000); |
1572 | | } |
1573 | | m_bitclk_time += m_dsk.bitclk_time; |
| 1570 | m_bitclk_time += m_dsk.bitclk_time[m_dsk.drive]; |
1574 | 1571 | m_bitclk_index = arg; |
1575 | 1572 | } else { |
1576 | 1573 | // stop the bitclock timer |
r26331 | r26332 | |
1588 | 1585 | { |
1589 | 1586 | diablo_hd_device* dhd = m_drive[unit]; |
1590 | 1587 | LOG((LOG_DISK,0,"%s dhd=%p\n", __FUNCTION__, dhd)); |
| 1588 | // get bit time in pico seconds |
| 1589 | m_dsk.bitclk_time[unit] = static_cast<int>(dhd->bit_time().as_attoseconds() / 1000000); |
1591 | 1590 | #if USE_BITCLK_TIMER |
1592 | 1591 | LOG((LOG_DISK,0," unit #%d stop bitclk\n", unit)); |
1593 | 1592 | m_dsk.bitclk_timer->enable(false); |
r26331 | r26332 | |
1684 | 1683 | |
1685 | 1684 | m_dsk.ready_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(alto2_cpu_device::disk_ready_mf31a),this)); |
1686 | 1685 | m_dsk.ready_timer->reset(); |
| 1686 | |
| 1687 | m_dsk.bitclk_time[0] = static_cast<int>(attotime::from_nsec(300).as_attoseconds() / 1000000); |
| 1688 | m_dsk.bitclk_time[1] = static_cast<int>(attotime::from_nsec(300).as_attoseconds() / 1000000); |
1687 | 1689 | } |
1688 | 1690 | |
1689 | 1691 | /** |
r26331 | r26332 | |
1691 | 1693 | */ |
1692 | 1694 | void alto2_cpu_device::exit_disk() |
1693 | 1695 | { |
1694 | | // nothing to do yet |
| 1696 | // nothing to do yet |
1695 | 1697 | } |
1696 | 1698 | |