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r26333 Thursday 21st November, 2013 at 15:47:34 UTC by Jürgen Buchmüller
Fix comments and reorder T and L flag handling. Update display state machine logging. Fix ALTO2_DEBUG=1 build.
[/branches/alto2/src/emu/cpu/alto2]a2curt.c a2disk.c a2disp.c a2jkff.c a2jkff.h a2ram.c alto2cpu.c
[/branches/alto2/src/emu/machine]diablo_hd.h

branches/alto2/src/emu/cpu/alto2/a2disp.c
r26332r26333
313313
314314      LOG((LOG_DISPL,1, " VBLANK"));
315315
316      /* VSYNC is always within VBLANK */
316      // VSYNC is always within VBLANK, thus we handle it only here
317317      if (A66_VSYNC(a66)) {
318318         if (!A66_VSYNC(m_dsp.a66)) {
319            LOG((LOG_DISPL,1, " VSYNC/ (wake DVT)"));
319            LOG((LOG_DISPL,1, " VSYNC↗ (wake DVT)"));
320320            /*
321321             * The display vertical task DVT is awakened once per field,
322322             * at the beginning of vertical retrace.
323323             */
324324            m_task_wakeup |= 1 << task_dvt;
325            // sdl_update(HLC1024()); // FIXME: upade odd or even field
325            // TODO: upade odd or even field of the internal bitmap
326326         } else {
327327            LOG((LOG_DISPL,1, " VSYNC"));
328328         }
329329      }
330330   } else {
331331      if (A66_VBLANK(m_dsp.a66)) {
332         /**
332         /*
333333          * VBLANKPULSE:
334334          * The display horizontal task DHT is awakened once at the
335335          * beginning of each field, and thereafter whenever the
r26332r26333
349349         m_dsp.curt_blocks = false;
350350      }
351351      if (!A63_HBLANK_HI(a63) && A63_HBLANK_HI(m_dsp.a63)) {
352         /* falling edge of a63 HBLANK starts unload */
353         LOG((LOG_DISPL,1, " HBLANK\\ UNLOAD"));
352         // falling edge of a63 HBLANK starts unloading of FIFO words
353         LOG((LOG_DISPL,1, " HBLANK↘ UNLOAD"));
354354         m_unload_time = ALTO2_DISPLAY_BITTIME(m_dsp.halfclock ? 32 : 16);
355355         m_unload_word = 0;
356356#if   DEBUG_DISPLAY_TIMING
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363363
364364   /*
365365    * The wakeup request for the display word task (DWT) is controlled by
366    * the state of the 16 word buffer. If DWT has not executed a BLOCK,
366    * the state of the 16 word FIFO. If DWT has not executed a BLOCK,
367367    * if DHT is not blocked, and if the buffer is not full, DWT wakeups
368368    * are generated.
369369    */
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372372      LOG((LOG_DISPL,1, " (wake DWT)"));
373373   }
374374
375   // Stop waking the display word task at SCANEND time
375376   if (A63_SCANEND_HI(a63)) {
376377      LOG((LOG_DISPL,1, " SCANEND"));
377378      m_task_wakeup &= ~(1 << task_dwt);
r26332r26333
381382
382383   if (A63_HSYNC_HI(a63)) {
383384      if (!A63_HSYNC_HI(m_dsp.a63)) {
384         LOG((LOG_DISPL,1, " HSYNC/ (CLRBUF)"));
385         LOG((LOG_DISPL,1, " HSYNC↗ (CLRBUF)"));
385386         /*
386387          * The hardware sets the buffer empty and clears the DWT block
387388          * flip-flop at the beginning of horizontal retrace for
r26332r26333
390391         m_dsp.fifo_wr = 0;
391392         m_dsp.fifo_rd = 0;
392393         m_dsp.dwt_blocks = false;
393         /* now take the new values from the last setmode */
394         // now take the new values from the last SETMODE←
394395         m_dsp.inverse = GET_SETMODE_INVERSE(m_dsp.setmode) ? 0xffff : 0x0000;
395396         m_dsp.halfclock = GET_SETMODE_SPEEDY(m_dsp.setmode);
396         /* stop the CPU from calling unload_word() */
397         // stop the CPU from calling unload_word()
397398         m_unload_time = -1;
398399      } else {
399400         LOG((LOG_DISPL,1, " HSYNC"));
400401      }
401402   }
402   // FIXME: try at the end of HSYNC
403   // FIXME: jiggly cursor issue; try to wake up CURT at the end of HSYNC
403404   if (A63_HSYNC_HI(m_dsp.a63) && !A63_HSYNC_HI(a63)) {
404         /*
405          * CLRBUF' also resets the 2nd cursor task block flip flop,
406          * which is built from two NAND gates a30c and a30d (74H00).
407          * If both flip flops are reset, the NOR gate a20d (74S02)
408          * decodes this as WAKECURT signal.
409          */
410         m_dsp.curt_wakeup = true;
405      /*
406       * CLRBUF' also resets the 2nd cursor task block flip flop,
407       * which is built from two NAND gates a30c and a30d (74H00).
408       * If both flip flops are reset, the NOR gate a20d (74S02)
409       * decodes this as WAKECURT signal.
410       */
411      m_dsp.curt_wakeup = true;
411412   }
412413
413414
branches/alto2/src/emu/cpu/alto2/alto2cpu.c
r26332r26333
8686alto2_cpu_device::alto2_cpu_device(const machine_config& mconfig, const char* tag, device_t* owner, UINT32 clock) :
8787   cpu_device(mconfig, ALTO2, "Xerox Alto-II", tag, owner, clock, "alto2", __FILE__),
8888#if   ALTO2_DEBUG
89   m_log_types(LOG_ETH),
89   m_log_types(LOG_DISK),
9090   m_log_level(8),
9191   m_log_newline(true),
9292#endif
r26332r26333
25052505      m_next = X_RDBITS(m_mir, 32, NEXT0, NEXT9) | m_next2;
25062506      m_next2 = X_RDBITS(RD_CROM(m_next), 32, NEXT0, NEXT9) | (m_next2 & ~ALTO2_UCODE_PAGE_MASK);
25072507      LOG((LOG_CPU,2,"%s-%04o: %011o r:%02o aluf:%02o bs:%02o f1:%02o f2:%02o t:%o l:%o next:%05o next2:%05o\n",
2508         task_name(m_task), m_mpc, m_mir, m_rsel, m_d_aluf, m_d_bs, m_d_f1, m_d_f2, MIR_T(m_mir), MIR_L(m_mir), m_next, m_next2));
2508         task_name(m_task), m_mpc, m_mir, m_rsel, m_d_aluf, m_d_bs, m_d_f1, m_d_f2, m_d_loadt, m_d_loadl, m_next, m_next2));
25092509      debugger_instruction_hook(this, m_mpc);
25102510
25112511      /*
r26332r26333
28152815      if (do_bs)
28162816         ((*this).*m_bs[1][m_task][m_d_bs])();
28172817
2818      // update L register and LALUC0, and also M register, if a RAM related task is active
2818      // update T register, if LOADT is set
2819      if (m_d_loadt) {
2820         m_cram_addr = m_alu;   // latch CRAM address
2821         if (flags & TSELECT) {
2822            m_t = m_alu;      // T source is ALU
2823            LOG((LOG_CPU,2, "   T← ALU (%#o)\n", m_alu));
2824         } else {
2825            m_t = m_bus;      // T source is BUS
2826            LOG((LOG_CPU,2, "   T← BUS (%#o)\n", m_bus));
2827         }
2828      }
2829
2830      // update L register and LALUC0
28192831      if (m_d_loadl) {
28202832         m_l = m_alu;         // load L from ALU
28212833         if (flags & ALUM) {
28222834            m_laluc0 = 0;      // logic operation - latch 0
28232835            LOG((LOG_CPU,2, "   L← ALU (%#o); LALUC0← %o\n", m_alu, 0));
28242836         } else {
2825            m_laluc0 = m_aluc0;   // logic operation - latch carry
2837            m_laluc0 = m_aluc0;   // arithmethic operation - latch carry
28262838            LOG((LOG_CPU,2, "   L← ALU (%#o); LALUC0← ALUC0 (%o)\n", m_alu, m_aluc0));
28272839         }
2840         // update M (MYL) register, if a RAM related task is active
28282841         if (m_ram_related[m_task]) {
28292842            m_m = m_alu;      // load M from ALU, if 'GOODTASK'
28302843            m_s[m_s_reg_bank[m_task]][0] = m_alu;   // also writes to S[bank][0], which can't be read
r26332r26333
28322845         }
28332846      }
28342847
2848      // handle task switching
28352849      if (m_task != m_next2_task) {
28362850         /* switch now? */
28372851         if (m_task == m_next_task) {
r26332r26333
28512865         }
28522866      }
28532867
2854      // update T register, if LOADT is set
2855      if (m_d_loadt) {
2856         m_cram_addr = m_alu;   // latch CRAM address
2857         if (flags & TSELECT) {
2858            m_t = m_alu;      // T source is ALU
2859            LOG((LOG_CPU,2, "   T← ALU (%#o)\n", m_alu));
2860         } else {
2861            m_t = m_bus;      // T source is BUS
2862            LOG((LOG_CPU,2, "   T← BUS (%#o)\n", m_bus));
2863         }
2864      }
2865
28662868      /*
28672869       * Subtract the microcycle time from the display time accu.
28682870       * If it underflows, call the display state machine and add
branches/alto2/src/emu/cpu/alto2/a2curt.c
r26332r26333
2525void alto2_cpu_device::f2_late_load_xpreg()
2626{
2727   m_dsp.xpreg = X_RDBITS(m_bus,16,6,15);
28   LOG((LOG_CURT,2,"   XPREG← BUS[6-15] (%#o)\n", m_dsp.xpreg));
28   LOG((LOG_CURT, 9,"   XPREG← BUS[6-15] (%#o)\n", m_dsp.xpreg));
2929}
3030
3131/**
r26332r26333
4848void alto2_cpu_device::f2_late_load_csr()
4949{
5050   m_dsp.csr = m_bus;
51   LOG((LOG_CURT,2,"   CSR← BUS (%#o)\n", m_dsp.csr));
52   int x = 1023 - m_dsp.xpreg; \
53   m_dsp.curdata = m_dsp.csr << (16 - (x & 15)); \
54   m_dsp.curword = x / 16; \
51   LOG((LOG_CURT, m_dsp.csr ? 2 : 9,"   CSR← BUS (%#o)\n", m_dsp.csr));
5552}
5653
5754/**
r26332r26333
6158{
6259   m_task_wakeup &= ~(1 << m_task);
6360   m_dsp.curt_wakeup = false;
61   int x = 01777 - m_dsp.xpreg;
62   m_dsp.curdata = m_dsp.csr << (16 - (x & 15));
63   m_dsp.curword = x / 16;
6464}
6565
6666/** @brief initialize the cursor task F1 and F2 functions */
branches/alto2/src/emu/cpu/alto2/a2jkff.c
r26332r26333
99 *****************************************************************************/
1010#include "alto2cpu.h"
1111
12#if   ALTO2_DEBUG
13static const char* raise_lower[2] = {"↗","↘"};
14#endif
15const char* jkff_name;
16
1217#if   JKFF_FUNCTION
1318
1419/**
branches/alto2/src/emu/cpu/alto2/a2jkff.h
r26332r26333
4545}   jkff_t;
4646
4747#if   ALTO2_DEBUG
48static const char* raise_lower[2] = {"↗","↘"};
49static const char* jkff_name;
5048/** @brief macro to set the name of a FF in DEBUG=1 builds only */
49extern const char* jkff_name;
5150#define   DEBUG_NAME(x)   jkff_name = x
5251#else
5352#define   DEBUG_NAME(x)
r26332r26333
5857#ifndef _A2JKFF_H_
5958#define _A2JKFF_H_
6059
61static jkff_t update_jkff(UINT8 s0, UINT8 s1);   //!< simulate a 74109 J-K flip-flop with set and reset inputs
60jkff_t update_jkff(UINT8 s0, UINT8 s1);   //!< simulate a 74109 J-K flip-flop with set and reset inputs
6261
6362#endif   // _A2JKFF_H_
6463#endif   // ALTO2_DEFINE_CONSTANTS
branches/alto2/src/emu/cpu/alto2/a2ram.c
r26332r26333
1616
1717//! direct write access to the microcode CRAM
1818#define   WR_CRAM(addr,data) do { \
19    *reinterpret_cast<UINT32 *>(m_ucode_cram + addr * 4) = data; \
19   *reinterpret_cast<UINT32 *>(m_ucode_cram + addr * 4) = data; \
2020} while (0)
2121
2222/**
r26332r26333
158158   if (m_d_rsel) {
159159      UINT8 bank = m_s_reg_bank[m_task];
160160      r = m_s[bank][m_d_rsel];
161      LOG((LOG_RAM,2,"   ←S%02o; bus &= S[%o][%02o] (%#o)\n", reg, bank, reg, r));
161      LOG((LOG_RAM,2,"   ←S%02o; bus &= S[%o][%02o] (%#o)\n", m_d_rsel, bank, m_d_rsel, r));
162162   } else {
163163      r = m_m;
164      LOG((LOG_RAM,2,"   ←S%02o; bus &= M (%#o)\n", reg, r));
164      LOG((LOG_RAM,2,"   ←S%02o; bus &= M (%#o)\n", m_d_rsel, r));
165165   }
166166   m_bus &= r;
167167}
r26332r26333
172172void alto2_cpu_device::bs_early_load_sreg()
173173{
174174   int r = 0;   /* ??? */
175   LOG((LOG_RAM,2,"   S%02o← BUS &= garbage (%#o)\n", MIR_RSEL(m_mir), r));
175   LOG((LOG_RAM,2,"   S%02o← BUS &= garbage (%#o)\n", m_d_rsel, r));
176176   m_bus &= r;
177177}
178178
r26332r26333
183183{
184184   UINT8 bank = m_s_reg_bank[m_task];
185185   m_s[bank][m_d_rsel] = m_m;
186   LOG((LOG_RAM,2,"   S%02o← S[%o][%02o] := %#o\n", reg, bank, reg, m_m));
186   LOG((LOG_RAM,2,"   S%02o← S[%o][%02o] := %#o\n", m_d_rsel, bank, m_d_rsel, m_m));
187187}
188188
189189/**
branches/alto2/src/emu/cpu/alto2/a2disk.c
r26332r26333
9191#if   ALTO2_DEBUG
9292/** @brief human readable names for the KADR← modes */
9393static const char *rwc_name[4] = {"read", "check", "write", "write2"};
94static const char* raise_lower[2] = {"↗","↘"};
9495#endif
9596
9697/**
branches/alto2/src/emu/machine/diablo_hd.h
r26332r26333
1313#include "imagedev/diablo.h"
1414
1515#ifndef   DIABLO_DEBUG
16#define   DIABLO_DEBUG   1                         //!< set to 1 to enable debug log output
16#define   DIABLO_DEBUG   0                         //!< set to 1 to enable debug log output
1717#endif
1818
1919#define DIABLO_HD_0 "diablo0"

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