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r24087 Friday 5th July, 2013 at 13:17:11 UTC by David Haywood
now that we're modern treat the 68307 like other modern CPUs by using a derived type with the peripherals in emu/machine instead of being glued into the CPU core.

[src/emu/cpu]	cpu.mak
[src/emu/cpu/m68000]	68307bus.c 68307bus.h 68307ser.c 68307ser.h 68307sim.c 68307sim.h 68307tmu.c 68307tmu.h m68000.h m68kcpu.c
[src/emu/machine]	68307.c* 68307.h* 68307bus.c* 68307bus.h* 68307ser.c* 68307ser.h* 68307sim.c* 68307sim.h* 68307tmu.c* 68307tmu.h* machine.mak
[src/mame]	mame.mak
[src/mame/drivers]	bfm_sc4h.c
[src/mame/includes]	bfm_sc45.h bfm_sc5.h

trunk/src/mame/drivers/bfm_sc4h.c

r24086	r24087
33	33
34	34	#include "emu.h"
35	35	#include "cpu/m68000/m68000.h"
	36	#include "machine/68307.h"
36	37	#include "includes/bfm_sc45.h"
37	38	#include "bfm_sc4.lh"
38	39	#include "video/awpvid.h"

trunk/src/mame/includes/bfm_sc45.h

r24086	r24087
9	9	#include "sound/ymz280b.h"
10	10	#include "machine/68681.h"
11	11	#include "machine/nvram.h"
12		#include "cpu/m68000/m68000.h"
	12	#include "machine/68307.h"
13	13
14	14	// common base class for things shared between sc4 and sc5
15	15	class bfm_sc45_state : public driver_device
r24086	r24087
17	17	public:
18	18	bfm_sc45_state(const machine_config &mconfig, device_type type, const char *tag)
19	19	: driver_device(mconfig, type, tag),
20		m_maincpu(*this, "maincpu"),
21	20	m_duart(*this, "duart68681"),
22	21	m_vfd0(*this, "vfd0"),
23	22	m_ymz(*this, "ymz")
r24086	r24087
25	24	}
26	25
27	26	public:
28		required_device<m68000_base_device> m_maincpu;
	27
29	28	required_device<duart68681_device> m_duart;
30	29	optional_device<bfm_bda_t> m_vfd0;
31	30	required_device<ymz280b_device> m_ymz;
r24086	r24087
50	49	public:
51	50	sc4_state(const machine_config &mconfig, device_type type, const char *tag)
52	51	: bfm_sc45_state(mconfig, type, tag),
	52	m_maincpu(*this, "maincpu"),
53	53	m_cpuregion(*this, "maincpu"),
54	54	m_nvram(*this, "nvram"),
55	55	m_io1(*this, "IN-0"),
r24086	r24087
69	69	m_dochk41 = false;
70	70	}
71	71
	72	required_device<m68307cpu_device> m_maincpu;
72	73	required_memory_region m_cpuregion;
73	74	// devices
74	75	required_device<nvram_device> m_nvram;

trunk/src/mame/includes/bfm_sc5.h

r24086	r24087
5	5	{
6	6	public:
7	7	bfm_sc5_state(const machine_config &mconfig, device_type type, const char *tag)
8		: bfm_sc45_state(mconfig, type, tag)
	8	: bfm_sc45_state(mconfig, type, tag),
	9	m_maincpu(*this, "maincpu")
9	10	{ }
10	11
11	12	protected:
12	13
13	14
14	15	public:
	16	required_device<m68000_base_device> m_maincpu;
	17
15	18	DECLARE_DRIVER_INIT(sc5);
16	19	DECLARE_WRITE_LINE_MEMBER(bfm_sc5_ym_irqhandler);
17	20	DECLARE_READ8_MEMBER( sc5_10202F0_r );

trunk/src/mame/mame.mak

r24086	r24087
408	408	MACHINES += MC6854
409	409	MACHINES += MC68901
410	410	MACHINES += MCCS1850
	411	MACHINES += M68307
411	412	MACHINES += MCF5206E
412	413	MACHINES += MICROTOUCH
413	414	MACHINES += MM58274C

trunk/src/emu/cpu/m68000/68307sim.c

r24086	r24087
1		/* 68307 SIM module */
2
3		#include "emu.h"
4		#include "m68kcpu.h"
5
6
7		READ16_MEMBER( m68000_base_device::m68307_internal_sim_r )
8		{
9		m68000_base_device *m68k = this;
10		m68307_sim* sim = m68k->m68307SIM;
11		assert(sim != NULL);
12
13		int pc = space.device().safe_pc();
14
15		if (sim)
16		{
17		switch (offset<<1)
18		{
19		case m68307SIM_PADAT: return sim->read_padat(this, space, mem_mask);
20		case m68307SIM_PBDAT: return sim->read_pbdat(this, space, mem_mask);
21
22		case m68307SIM_LICR2: return  (sim->m_licr2);
23
24		case m68307SIM_BR0: return (sim->m_br[0]);
25		case m68307SIM_OR0: return (sim->m_or[0]);
26		case m68307SIM_BR1: return (sim->m_br[1]);
27		case m68307SIM_OR1: return (sim->m_or[1]);
28		case m68307SIM_BR2: return (sim->m_br[2]);
29		case m68307SIM_OR2: return (sim->m_or[2]);
30		case m68307SIM_BR3: return (sim->m_br[3]);
31		case m68307SIM_OR3: return (sim->m_or[3]);
32
33		default:
34		logerror("%08x m68307_internal_sim_r %08x, (%04x)\n", pc, offset*2,mem_mask);
35		return 0xff;
36
37		}
38		}
39
40		return 0x0000;
41		}
42
43
44		WRITE16_MEMBER( m68000_base_device::m68307_internal_sim_w )
45		{
46		m68000_base_device *m68k = this;
47		m68307_sim* sim = m68k->m68307SIM;
48		assert(sim != NULL);
49
50		int pc = space.device().safe_pc();
51
52		if (sim)
53		{
54		switch (offset<<1)
55		{
56		case m68307SIM_PACNT:
57		logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Control Register - PACNT)\n", pc, offset*2,data,mem_mask);
58		sim->write_pacnt(data,mem_mask);
59		break;
60
61		case m68307SIM_PADDR:
62		logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Direction Register - PADDR)\n", pc, offset*2,data,mem_mask);
63		sim->write_paddr(data,mem_mask);
64		break;
65
66		case m68307SIM_PADAT:
67		sim->write_padat(this, space, data,mem_mask);
68		break;
69
70		case m68307SIM_PBCNT:
71		logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Control Register - PBCNT)\n", pc, offset*2,data,mem_mask);
72		sim->write_pbcnt(data,mem_mask);
73		break;
74
75		case m68307SIM_PBDDR:
76		logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Direction Register - PBDDR)\n", pc, offset*2,data,mem_mask);
77		sim->write_pbddr(data,mem_mask);
78		break;
79
80		case m68307SIM_PBDAT:
81		sim->write_pbdat(this, space, data, mem_mask);
82		break;
83
84
85		case m68307SIM_LICR1:
86		logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 1 - LICR1)\n", pc, offset*2,data,mem_mask);
87		sim->write_licr1(data,mem_mask);
88		break;
89
90		case m68307SIM_LICR2:
91		logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 2 - LICR2)\n", pc, offset*2,data,mem_mask);
92		sim->write_licr2(data,mem_mask);
93		break;
94
95		case m68307SIM_PICR:
96		logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Control Register - PICR)\n", pc, offset*2,data,mem_mask);
97		sim->write_picr(data,mem_mask);
98		break;
99
100		case m68307SIM_PIVR:
101		logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Vector Register - PIVR)\n", pc, offset*2,data,mem_mask);
102		sim->write_pivr(data,mem_mask);
103		break;
104
105		case m68307SIM_BR0:
106		COMBINE_DATA(&sim->m_br[0]);
107		break;
108		case m68307SIM_OR0:
109		COMBINE_DATA(&sim->m_or[0]);
110		break;
111		case m68307SIM_BR1:
112		COMBINE_DATA(&sim->m_br[1]);
113		break;
114		case m68307SIM_OR1:
115		COMBINE_DATA(&sim->m_or[1]);
116		break;
117		case m68307SIM_BR2:
118		COMBINE_DATA(&sim->m_br[2]);
119		break;
120		case m68307SIM_OR2:
121		COMBINE_DATA(&sim->m_or[2]);
122		break;
123		case m68307SIM_BR3:
124		COMBINE_DATA(&sim->m_br[3]);
125		break;
126		case m68307SIM_OR3:
127		COMBINE_DATA(&sim->m_or[3]);
128		break;
129
130
131
132		default :
133		logerror("%08x m68307_internal_sim_w %08x, %04x (%04x)\n", pc, offset*2,data,mem_mask);
134		break;
135
136		}
137		}
138		}
139
140
141		void m68307_sim::write_pacnt(UINT16 data, UINT16 mem_mask)
142		{
143		COMBINE_DATA(&m_pacnt);
144		}
145
146		void m68307_sim::write_paddr(UINT16 data, UINT16 mem_mask)
147		{
148		COMBINE_DATA(&m_paddr);
149		}
150
151
152		UINT16 m68307_sim::read_padat(m68000_base_device* m68k, address_space &space, UINT16 mem_mask)
153		{
154		int pc = space.device().safe_pc();
155
156		if (m68k->m_m68307_porta_r)
157		{
158		// for general purpose bits, if configured as 'output' then anything output gets latched
159		// and anything configured as input is read from the port
160		UINT8 outputbits = m_paddr;
161		UINT8 inputbits = ~m_paddr;
162		UINT8 general_purpose_bits = ~m_pacnt;
163		UINT8 indat = m68k->m_m68307_porta_r(space, false, (inputbits & general_purpose_bits)&mem_mask) & ((inputbits & general_purpose_bits) & mem_mask); // read general purpose input lines
164		indat |= m68k->m_m68307_porta_r(space, true, (inputbits & ~general_purpose_bits)&mem_mask) & ((inputbits & ~general_purpose_bits)& mem_mask); // read dedicated input lines
165		UINT8 outdat = (m_padat & outputbits) & general_purpose_bits; // read general purpose output lines (reads latched data)
166
167		return (indat | outdat);
168
169		}
170		else
171		{
172		logerror("%08x m68307_internal_sim_r (%04x) (Port A (8-bit) Data Register - PADAT)\n", pc, mem_mask);
173		}
174		return 0xffff;
175		}
176
177
178		void m68307_sim::write_padat(m68000_base_device* m68k, address_space &space, UINT16 data, UINT16 mem_mask)
179		{
180		int pc = space.device().safe_pc();
181		COMBINE_DATA(&m_padat);
182
183		if (m68k->m_m68307_porta_w)
184		{
185		m68k->m_m68307_porta_w(space, false, data, 0xff);
186		}
187		else
188		{
189		logerror("%08x m68307_internal_sim_w %04x (%04x) (Port A (8-bit) Data Register - PADAT)\n", pc, data,mem_mask);
190		}
191		}
192
193		void m68307_sim::write_pbcnt(UINT16 data, UINT16 mem_mask)
194		{
195		COMBINE_DATA(&m_pbcnt);
196		}
197
198		void m68307_sim::write_pbddr(UINT16 data, UINT16 mem_mask)
199		{
200		COMBINE_DATA(&m_pbddr);
201		}
202
203		UINT16 m68307_sim::read_pbdat(m68000_base_device* m68k, address_space &space, UINT16 mem_mask)
204		{
205		int pc = space.device().safe_pc();
206
207		if (m68k->m_m68307_portb_r)
208		{
209		// for general purpose bits, if configured as 'output' then anything output gets latched
210		// and anything configured as input is read from the port
211		UINT16 outputbits = m_pbddr;
212		UINT16 inputbits = ~m_pbddr;
213		UINT16 general_purpose_bits = ~m_pbcnt;
214
215		UINT16 indat = m68k->m_m68307_portb_r(space, false, (inputbits & general_purpose_bits)&mem_mask) & ((inputbits & general_purpose_bits) & mem_mask); // read general purpose input lines
216		indat |= m68k->m_m68307_portb_r(space, true, (inputbits & ~general_purpose_bits)&mem_mask) & ((inputbits & ~general_purpose_bits)& mem_mask); // read dedicated input lines
217		UINT16 outdat = (m_pbdat & outputbits) & general_purpose_bits; // read general purpose output lines (reads latched data)
218
219		return (indat | outdat);
220		}
221		else
222		{
223		logerror("%08x m68307_internal_sim_r (%04x) (Port B (16-bit) Data Register - PBDAT)\n", pc, mem_mask);
224		}
225		return 0xffff;
226		}
227
228
229		void m68307_sim::write_pbdat(m68000_base_device* m68k, address_space &space, UINT16 data, UINT16 mem_mask)
230		{
231		int pc = space.device().safe_pc();
232		COMBINE_DATA(&m_pbdat);
233
234		if (m68k->m_m68307_portb_w)
235		{
236		m68k->m_m68307_portb_w(space, false, data, mem_mask);
237		}
238		else
239		{
240		logerror("%08x m68307_internal_sim_w %04x (%04x) (Port B (16-bit) Data Register - PBDAT)\n", pc, data,mem_mask);
241		}
242		}
243
244		void m68307_sim::write_licr1(UINT16 data, UINT16 mem_mask)
245		{
246		COMBINE_DATA(&m_licr1);
247		data = m_licr1;
248		logerror("m_licr1 value %04x : Details :\n", data);
249		logerror("int4ipl %01x\n", (data>>0)&7);
250		logerror("pir4    %01x\n", (data>>3)&1);
251		logerror("int3ipl %01x\n", (data>>4)&7);
252		logerror("pir3    %01x\n", (data>>7)&1);
253		logerror("int2ipl %01x\n", (data>>8)&7);
254		logerror("pir2    %01x\n", (data>>11)&1);
255		logerror("int1ipl %01x\n", (data>>12)&7);
256		logerror("pir1    %01x\n", (data>>15)&1);
257		logerror("\n");
258		}
259
260		void m68307_sim::write_licr2(UINT16 data, UINT16 mem_mask)
261		{
262		COMBINE_DATA(&m_licr2);
263		UINT16 newdata = m_licr2;
264		logerror("m_licr2 value %04x : Details :\n", newdata);
265		logerror("int8ipl %01x\n", (newdata>>0)&7);
266		logerror("pir8    %01x\n", (newdata>>3)&1);
267		logerror("int7ipl %01x\n", (newdata>>4)&7);
268		logerror("pir7    %01x\n", (newdata>>7)&1);
269		logerror("int6ipl %01x\n", (newdata>>8)&7);
270		logerror("pir6    %01x\n", (newdata>>11)&1);
271		logerror("int5ipl %01x\n", (newdata>>12)&7);
272		logerror("pir5    %01x\n", (newdata>>15)&1);
273		logerror("\n");
274
275		if (data & 0x0008) m_licr2 = m_licr2 & ~0x0008;
276		if (data & 0x0080) m_licr2 = m_licr2 & ~0x0080;
277		if (data & 0x0800) m_licr2 = m_licr2 & ~0x0800;
278		if (data & 0x8000) m_licr2 = m_licr2 & ~0x8000;
279
280
281		}
282
283
284		void m68307_sim::write_picr(UINT16 data, UINT16 mem_mask)
285		{
286		COMBINE_DATA(&m_picr);
287		data = m_picr;
288		logerror("picr value %04x : Details :\n", data);
289		logerror("mbipl %01x\n", (data>>0)&7);
290		logerror("uaipl %01x\n", (data>>4)&7);
291		logerror("t2ipl %01x\n", (data>>8)&7);
292		logerror("t1ipl %01x\n", (data>>12)&7);
293		logerror("\n");
294		}
295
296		void m68307_sim::write_pivr(UINT16 data, UINT16 mem_mask)
297		{
298		COMBINE_DATA(&m_pivr);
299		data = m_pivr;
300		logerror("pivr value %04x : Details :\n", data);
301		logerror("unused %01x\n", (data>>0)&0xf);
302		logerror("high vector %01x\n", (data>>4)&0xf);
303		}
304
305		void m68307_sim::reset(void)
306		{
307		for (int i=0;i<4;i++)
308		{
309		m_br[i] = 0xc001;
310		m_or[i] = 0xdffd;
311		}
312		}

trunk/src/emu/cpu/m68000/68307ser.c

r24086	r24087
1		/* 68307 SERIAL Module */
2		/* all ports on this are 8-bit? */
3
4		/* this is a 68681 'compatible' chip but with only a single channel implemented
5		(writes to the other channel have no effects)
6
7		for now at least we piggyback on the existing 68307 emulation rather than having
8		a custom verson here, that may change later if subtle differences exist.
9
10		*/
11
12		#include "emu.h"
13		#include "m68kcpu.h"
14
15
16		READ8_MEMBER( m68000_base_device::m68307_internal_serial_r )
17		{
18		m68000_base_device *m68k = this;
19		m68307_serial* serial = m68k->m68307SERIAL;
20		assert(serial != NULL);
21
22		if (serial)
23		{
24		// if we're piggybacking on the existing 68681 implementation...
25		if (serial->m_duart68681)
26		{
27		if (offset&1) return duart68681_r(serial->m_duart68681, *m68k->program, offset>>1);
28		}
29		else
30		{
31		int pc = space.device().safe_pc();
32
33		switch (offset)
34		{
35		case m68307SER_UMR1_UMR2:
36		logerror("%08x m68307_internal_serial_r %08x (UMR1, UMR2 - UART Mode Register)\n", pc, offset);
37		return space.machine().rand();
38
39		case m68307SER_USR_UCSR:
40		logerror("%08x m68307_internal_serial_r %08x (USR, UCSR - UART Status/Clock Select Register)\n", pc, offset);
41		return space.machine().rand();
42
43		case m68307SER_UCR:
44		logerror("%08x m68307_internal_serial_r %08x (UCR - UART Command Register)\n", pc, offset);
45		return space.machine().rand();
46
47		case m68307SER_URB_UTB:
48		logerror("%08x m68307_internal_serial_r %08x (URB, UTB - UART Recieve/Transmit Buffer)\n", pc, offset);
49		return 0xff;//space.machine().rand();
50
51		case m68307SER_UIPCR_UACR:
52		logerror("%08x m68307_internal_serial_r %08x (UIPCR, UACR - UART Input Port Change Register / UART Control Register)\n", pc, offset);
53		return 0xff;//space.machine().rand();
54
55		case m68307SER_UISR_UIMR:
56		logerror("%08x m68307_internal_serial_r %08x (UISR, UIMR - UART Interrupt Status Register / UART Interrupt Mask Register)\n", pc, offset);
57		return space.machine().rand() & 0x87;
58
59		case m68307SER_UBG1:
60		logerror("%08x m68307_internal_serial_r %08x (UBG1 - UART Baud Rate Gen. Precaler MSB)\n", pc, offset);
61		return space.machine().rand() & 0x87;
62
63		case m68307SER_UBG2:
64		logerror("%08x m68307_internal_serial_r %08x (UBG1 - UART Baud Rate Gen. Precaler LSB)\n", pc, offset);
65		return space.machine().rand() & 0x87;
66
67		case m68307SER_UIVR:
68		logerror("%08x m68307_internal_serial_r %08x (UIVR - UART Interrupt Vector Register)\n", pc, offset);
69		return space.machine().rand() & 0x87;
70
71		case m68307SER_UIP:
72		logerror("%08x m68307_internal_serial_r %08x (UIP - UART Register Input Port)\n", pc, offset);
73		return space.machine().rand() & 0x87;
74
75		case m68307SER_UOP1:
76		logerror("%08x m68307_internal_serial_r %08x (UOP1 - UART Output Port Bit Set Cmd)\n", pc, offset);
77		return space.machine().rand() & 0x87;
78
79		case m68307SER_UOP0:
80		logerror("%08x m68307_internal_serial_r %08x (UOP0 - UART Output Port Bit Reset Cmd)\n", pc, offset);
81		return space.machine().rand() & 0x87;
82
83		default:
84		logerror("%08x m68307_internal_serial_r %08x (UNKNOWN / ILLEGAL)\n", pc, offset);
85		break;
86		}
87		}
88		}
89
90		return 0x0000;
91		}
92
93		WRITE8_MEMBER( m68000_base_device::m68307_internal_serial_w )
94		{
95		m68000_base_device *m68k = this;
96		m68307_serial* serial = m68k->m68307SERIAL;
97		assert(serial != NULL);
98
99		int pc = space.device().safe_pc();
100
101		if (serial)
102		{
103		// if we're piggybacking on the existing 68681 implementation...
104		if (serial->m_duart68681)
105		{
106		if (offset&1) duart68681_w(serial->m_duart68681, *m68k->program, offset>>1, data);
107		}
108		else
109		{
110		switch (offset)
111		{
112		case m68307SER_UMR1_UMR2:
113		logerror("%08x m68307_internal_serial_w %08x, %02x (UMR1, UMR2 - UART Mode Register)\n", pc, offset,data);
114		break;
115
116		case m68307SER_USR_UCSR:
117		logerror("%08x m68307_internal_serial_w %08x, %02x (UCSR - Clock Select Register)\n", pc, offset,data);
118		break;
119
120		case m68307SER_UCR:
121		logerror("%08x m68307_internal_serial_w %08x, %02x (UCR - UART Command Register)\n", pc, offset,data);
122		break;
123
124		case m68307SER_URB_UTB:
125		logerror("%08x m68307_internal_serial_w %08x, %02x (UTB - Transmit Buffer)\n", pc, offset,data);
126		break;
127
128		case m68307SER_UIPCR_UACR:
129		logerror("%08x m68307_internal_serial_w %08x, %02x (UIPCR, UACR - UART Input Port Change Register / UART Control Register)\n", pc, offset,data);
130		break;
131
132		case m68307SER_UISR_UIMR:
133		logerror("%08x m68307_internal_serial_w %08x, %02x (UIMR - Interrupt Mask Register)\n", pc, offset,data);
134		break;
135
136		case m68307SER_UBG1:
137		logerror("%08x m68307_internal_serial_w %08x, %02x (UBG1 - UART Baud Rate Gen. Precaler MSB)\n", pc, offset,data);
138		break;
139
140		case m68307SER_UBG2:
141		logerror("%08x m68307_internal_serial_w %08x, %02x (UBG1 - UART Baud Rate Gen. Precaler LSB)\n", pc, offset,data);
142		break;
143
144		case m68307SER_UIVR:
145		logerror("%08x m68307_internal_serial_w %08x, %02x (UIVR - Interrupt Vector Register)\n", pc, offset,data);
146		serial->m_uivr = data;
147		break;
148
149		case m68307SER_UIP:
150		logerror("%08x m68307_internal_serial_w %08x, %02x (UIP - UART Register Input Port)\n", pc, offset,data);
151		break;
152
153		case m68307SER_UOP1:
154		logerror("%08x m68307_internal_serial_w %08x, %02x (UOP1 - UART Output Port Bit Set Cmd)\n", pc, offset,data);
155		break;
156
157		case m68307SER_UOP0:
158		logerror("%08x m68307_internal_serial_w %08x, %02x (UOP0 - UART Output Port Bit Reset Cmd)\n", pc, offset,data);
159		break;
160
161
162		default:
163		logerror("%08x m68307_internal_serial_w %08x, %02x (UNKNOWN / ILLEGAL)\n", pc, offset,data);
164		break;
165		}
166		}
167		}
168		}
169
170		void m68307_serial::reset(void)
171		{
172		}

trunk/src/emu/cpu/m68000/68307bus.c

r24086	r24087
1		/* 68307 MBUS module */
2		/* all ports on this are 8-bit? */
3
4		#include "emu.h"
5		#include "m68kcpu.h"
6
7
8		READ8_MEMBER( m68000_base_device::m68307_internal_mbus_r )
9		{
10		m68000_base_device *m68k = this;
11		m68307_mbus* mbus = m68k->m68307MBUS;
12		assert(mbus != NULL);
13		UINT8 retval;
14
15		if (mbus)
16		{
17		int pc = space.device().safe_pc();
18
19
20		switch (offset)
21		{
22		case m68307BUS_MADR:
23		logerror("%08x m68307_internal_mbus_r %08x (MADR - M-Bus Address Register)\n", pc, offset);
24		return space.machine().rand();
25
26		case m68307BUS_MFDR:
27		logerror("%08x m68307_internal_mbus_r %08x (MFDR - M-Bus Frequency Divider Register)\n", pc, offset);
28		return space.machine().rand();
29
30		case m68307BUS_MBCR:
31		logerror("%08x m68307_internal_mbus_r %08x (MFCR - M-Bus Control Register)\n", pc, offset);
32		return mbus->m_MFCR;//space.machine().rand();
33
34		case m68307BUS_MBSR:
35		logerror("%08x m68307_internal_mbus_r %08x (MBSR - M-Bus Status Register)\n", pc, offset);
36		retval = 0;
37		if (mbus->m_busy) retval |= 0x20;
38		if (mbus->m_intpend) retval |= 0x02;
39
40		return retval;
41
42		case m68307BUS_MBDR:
43		logerror("%08x m68307_internal_mbus_r %08x (MBDR - M-Bus Data I/O Register)\n", pc, offset);
44		mbus->m_intpend = true;
45		return 0xff;//space.machine().rand();
46
47		default:
48		logerror("%08x m68307_internal_mbus_r %08x (UNKNOWN / ILLEGAL)\n", pc, offset);
49		return 0x00;
50		}
51		}
52
53		return 0xff;
54		}
55
56		WRITE8_MEMBER( m68000_base_device::m68307_internal_mbus_w )
57		{
58		m68000_base_device *m68k = this;
59		m68307_mbus* mbus = m68k->m68307MBUS;
60		assert(mbus != NULL);
61
62		if (mbus)
63		{
64		int pc = space.device().safe_pc();
65
66		switch (offset)
67		{
68		case m68307BUS_MADR:
69		logerror("%08x m68307_internal_mbus_w %08x, %02x (MADR - M-Bus Address Register)\n", pc, offset,data);
70		break;
71
72		case m68307BUS_MFDR:
73		logerror("%08x m68307_internal_mbus_w %08x, %02x (MFDR - M-Bus Frequency Divider Register)\n", pc, offset,data);
74		break;
75
76		case m68307BUS_MBCR:
77		logerror("%08x m68307_internal_mbus_w %08x, %02x (MFCR - M-Bus Control Register)\n", pc, offset,data);
78
79		mbus->m_MFCR = data;
80		if (data & 0x80)
81		{
82		mbus->m_busy = false;
83		mbus->m_intpend = false;
84		}
85		if (data & 0x20) mbus->m_busy = true;
86
87		break;
88
89		case m68307BUS_MBSR:
90		logerror("%08x m68307_internal_mbus_w %08x, %02x (MBSR - M-Bus Status Register)\n", pc, offset,data);
91		break;
92
93		case m68307BUS_MBDR:
94		logerror("%08x m68307_internal_mbus_w %08x, %02x (MBDR - M-Bus Data I/O Register)\n", pc, offset,data);
95
96		mbus->m_intpend = true;
97
98		break;
99
100		default:
101		logerror("%08x m68307_internal_mbus_w %08x, %02x (UNKNOWN / ILLEGAL)\n", pc, offset,data);
102		break;
103		}
104		}
105		}
106
107		void m68307_mbus::reset(void)
108		{
109		m_busy = false;
110		}

trunk/src/emu/cpu/m68000/68307sim.h

r24086	r24087
1		/* 68307 SIM module */
2
3		#include "m68000.h"
4
5		class m68000_base_device;
6
7
8		/* ports */
9		#define m68307SIM_PACNT (0x10)
10		#define m68307SIM_PADDR (0x12)
11		#define m68307SIM_PADAT (0x14)
12		#define m68307SIM_PBCNT (0x16)
13		#define m68307SIM_PBDDR (0x18)
14		#define m68307SIM_PBDAT (0x1a)
15
16
17		/* interrupt logic */
18		#define m68307SIM_LICR1 (0x20)
19		#define m68307SIM_LICR2 (0x22)
20		#define m68307SIM_PICR  (0x24)
21		#define m68307SIM_PIVR  (0x26)
22
23		/* used for the CS logic */
24		#define m68307SIM_BR0 (0x40)
25		#define m68307SIM_OR0 (0x42)
26		#define m68307SIM_BR1 (0x44)
27		#define m68307SIM_OR1 (0x46)
28		#define m68307SIM_BR2 (0x48)
29		#define m68307SIM_OR2 (0x4a)
30		#define m68307SIM_BR3 (0x4c)
31		#define m68307SIM_OR3 (0x4e)
32
33		class m68307_sim
34		{
35		public:
36
37		UINT16 m_pacnt; // 8-bit
38		UINT16 m_paddr; // 8-bit
39		UINT16 m_padat; // 8-bit
40
41		UINT16 m_pbcnt;
42		UINT16 m_pbddr;
43		UINT16 m_pbdat;
44
45		UINT16 m_pivr; // 8-bit
46
47		UINT16 m_br[4];
48		UINT16 m_or[4];
49		UINT16 m_picr;
50		UINT16 m_licr1;
51		UINT16 m_licr2;
52
53
54		void write_pacnt(UINT16 data, UINT16 mem_mask);
55		void write_paddr(UINT16 data, UINT16 mem_mask);
56		UINT16 read_padat(m68000_base_device* m68k, address_space &space, UINT16 mem_mask);
57		void write_padat(m68000_base_device* m68k, address_space &space, UINT16 data, UINT16 mem_mask);
58
59		void write_pbcnt(UINT16 data, UINT16 mem_mask);
60		void write_pbddr(UINT16 data, UINT16 mem_mask);
61		UINT16 read_pbdat(m68000_base_device* m68k, address_space &space, UINT16 mem_mask);
62		void write_pbdat(m68000_base_device* m68k, address_space &space, UINT16 data, UINT16 mem_mask);
63
64
65
66		void write_licr1(UINT16 data, UINT16 mem_mask);
67		void write_licr2(UINT16 data, UINT16 mem_mask);
68		void write_picr(UINT16 data, UINT16 mem_mask);
69		void write_pivr(UINT16 data, UINT16 mem_mask);
70
71		void reset(void);
72		};

trunk/src/emu/cpu/m68000/68307bus.h

r24086	r24087
1		#include "m68000.h"
2
3		#define m68307BUS_MADR (0x01)
4		#define m68307BUS_MFDR (0x03)
5		#define m68307BUS_MBCR (0x05)
6		#define m68307BUS_MBSR (0x07)
7		#define m68307BUS_MBDR (0x09)
8
9
10		class m68307_mbus
11		{
12		public:
13
14		UINT16 m_MFCR;
15
16		bool m_busy;
17		bool m_intpend;
18
19		void reset(void);
20		};

trunk/src/emu/cpu/m68000/68307ser.h

r24086	r24087
1		#include "m68000.h"
2		#include "machine/68681.h"
3
4		#define m68307SER_UMR1_UMR2  (0x01)
5		#define m68307SER_USR_UCSR   (0x03)
6		#define m68307SER_UCR        (0x05)
7		#define m68307SER_URB_UTB    (0x07)
8		#define m68307SER_UIPCR_UACR (0x09)
9		#define m68307SER_UISR_UIMR  (0x0b)
10		#define m68307SER_UBG1       (0x0d)
11		#define m68307SER_UBG2       (0x0f)
12		//                           (0x11)
13		//                           (0x13)
14		//                           (0x15)
15		//                           (0x17)
16		#define m68307SER_UIVR       (0x19)
17		#define m68307SER_UIP        (0x1b)
18		#define m68307SER_UOP1       (0x1d)
19		#define m68307SER_UOP0       (0x1f)
20
21		class m68307_serial
22		{
23		public:
24		void reset(void);
25		UINT8 m_uivr;
26
27		void m68307ser_set_duart68681(device_t* duart68681)
28		{
29		m_duart68681 = duart68681;
30		}
31
32		device_t* m_duart68681;
33		};

trunk/src/emu/cpu/m68000/68307tmu.c

r24086	r24087
1		/* 68307 TIMER module */
2		// 2x timers
3
4		#include "emu.h"
5		#include "m68kcpu.h"
6
7		READ16_MEMBER( m68000_base_device::m68307_internal_timer_r )
8		{
9		m68000_base_device *m68k = this;
10		m68307_timer* timer = m68k->m68307TIMER;
11		assert(timer != NULL);
12
13		if (timer)
14		{
15		int pc = space.device().safe_pc();
16		int which = offset & 0x8;
17
18		switch (offset&0x7)
19		{
20		case m68307TIMER_TCN: /* 0x3 (0x126 / 0x136) */
21		//if (pc!=0x2182e) logerror("%08x m68307_internal_timer_r %08x (%04x) (TCN - Timer Counter for timer %d)\n", pc, offset*2,mem_mask, which);
22		return timer->read_tcn(mem_mask, which);
23		break;
24
25
26		default:
27		logerror("%08x m68307_internal_timer_r %08x, (%04x)\n", pc, offset*2,mem_mask);
28		break;
29		}
30		}
31
32		return 0x0000;
33		}
34
35		WRITE16_MEMBER( m68000_base_device::m68307_internal_timer_w )
36		{
37		m68000_base_device *m68k = this;
38		m68307_timer* timer = m68k->m68307TIMER;
39		assert(timer != NULL);
40
41		if (timer)
42		{
43		int pc = space.device().safe_pc();
44		int which = offset & 0x8;
45
46		switch (offset&0x7)
47		{
48		case m68307TIMER_TMR: /* 0x0 (0x120 / 0x130) */
49		logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TMR - Timer Mode Register for timer %d)\n", pc, offset*2,data,mem_mask, which);
50		timer->write_tmr(data, mem_mask, which);
51		break;
52
53		case m68307TIMER_TRR: /* 0x1 (0x122 / 0x132) */
54		logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TRR - Timer Reference Register for timer %d)\n", pc, offset*2,data,mem_mask, which);
55		timer->write_trr(data, mem_mask, which);
56		break;
57
58		case m68307TIMER_TCR: /* 0x2 (0x124 / 0x134) */
59		logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TCR - Timer Capture Register for timer %d) (illegal, read-only)\n", pc, offset*2,data,mem_mask, which);
60		break;
61
62		case m68307TIMER_TCN: /* 0x3 (0x126 / 0x136) */
63		logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TCN - Timer Counter for timer %d)\n", pc, offset*2,data,mem_mask, which);
64		break;
65
66		case m68307TIMER_TER: /* 0x4 (0x128 / 0x138) */
67		/* 8-bit only!! */
68		//logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TER - Timer Event Register for timer %d)\n", pc, offset*2,data,mem_mask, which);
69		timer->write_ter(data, mem_mask, which);
70		break;
71
72		case m68307TIMER_WRR: /* 0x5 (0x12a / 0x13a) */
73		if (which==0)
74		{
75		logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (WRR - Watchdog Reference Register)\n", pc, offset*2,data,mem_mask);
76		}
77		else
78		{
79		logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", pc, offset*2,data,mem_mask);
80		}
81		break;
82
83		case m68307TIMER_WCR: /* 0x6 (0x12c / 0x13c) */
84		if (which==0)
85		{
86		logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (WRR - Watchdog Counter Register)\n", pc, offset*2,data,mem_mask);
87		}
88		else
89		{
90		logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", pc, offset*2,data,mem_mask);
91		}
92		break;
93
94		case m68307TIMER_XXX: /* 0x7 (0x12e / 0x13e) */
95		logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", pc, offset*2,data,mem_mask);
96		break;
97
98		}
99		}
100		}
101
102		static TIMER_CALLBACK( m68307_timer0_callback )
103		{
104		m68000_base_device* m68k = (m68000_base_device *)ptr;
105		m68307_single_timer* tptr = &m68k->m68307TIMER->singletimer[0];
106		tptr->regs[m68307TIMER_TMR] |= 0x2;
107
108		m68307_timer0_interrupt(m68k);
109
110		tptr->mametimer->adjust(m68k->cycles_to_attotime(20000));
111		}
112
113		static TIMER_CALLBACK( m68307_timer1_callback )
114		{
115		m68000_base_device* m68k = (m68000_base_device *)ptr;
116		m68307_single_timer* tptr = &m68k->m68307TIMER->singletimer[1];
117		tptr->regs[m68307TIMER_TMR] |= 0x2;
118
119		m68307_timer1_interrupt(m68k);
120
121		tptr->mametimer->adjust(m68k->cycles_to_attotime(20000));
122
123		}
124
125		static TIMER_CALLBACK( m68307_wd_timer_callback )
126		{
127		printf("wd timer\n");
128		}
129
130		void m68307_timer::init(m68000_base_device *device)
131		{
132		parent = device;
133
134		m68307_single_timer* tptr;
135
136		tptr = &singletimer[0];
137		tptr->mametimer = device->machine().scheduler().timer_alloc(FUNC(m68307_timer0_callback), parent);
138
139		tptr = &singletimer[1];
140		tptr->mametimer = device->machine().scheduler().timer_alloc(FUNC(m68307_timer1_callback), parent);
141
142
143		wd_mametimer = device->machine().scheduler().timer_alloc(FUNC(m68307_wd_timer_callback), parent);
144
145
146		}
147
148		UINT16 m68307_timer::read_tcn(UINT16 mem_mask, int which)
149		{
150		// we should return the current timer value by
151		// calculating what it should be based on the time
152		// since it was last set
153		return 0x3a98;
154		}
155
156		void m68307_timer::write_ter(UINT16 data, UINT16 mem_mask, int which)
157		{
158		m68307_single_timer* tptr = &singletimer[which];
159		if (data & 0x2) tptr->regs[m68307TIMER_TMR] &= ~0x2;
160		}
161
162		void m68307_timer::write_tmr(UINT16 data, UINT16 mem_mask, int which)
163		{
164		m68000_base_device* m68k = parent;
165		m68307_single_timer* tptr = &singletimer[which];
166
167		COMBINE_DATA(&tptr->regs[m68307TIMER_TMR]);
168
169		data = tptr->regs[m68307TIMER_TMR];
170
171		int ps   = data & (0xff00)>>8;
172		int ce   = data & (0x00c0)>>6;
173		int om   = data & (0x0020)>>5;
174		int ori  = data & (0x0010)>>4;
175		int frr  = data & (0x0008)>>3;
176		int iclk = data & (0x0006)>>1;
177		int rst  = data & (0x0001)>>0;
178
179
180		logerror("tmr value %04x : Details :\n", data);
181		logerror("prescale %d\n", ps);
182		logerror("(clock divided by %d)\n", ps+1);
183		logerror("capture edge / enable interrupt %d\n", ce);
184		if (ce==0x0) logerror("(disable interrupt on capture event)\n");
185		if (ce==0x1) logerror("(capture on rising edge only + enable capture interrupt)\n");
186		if (ce==0x2) logerror("(capture on falling edge only + enable capture interrupt)\n");
187		if (ce==0x3) logerror("(capture on any edge + enable capture interrupt)\n");
188		logerror("output mode %d\n", om);
189		if (om==0x0) logerror("(active-low pulse for one cycle))\n");
190		if (om==0x1) logerror("(toggle output)\n");
191		logerror("output reference interrupt %d\n", ori);
192		if (ori==0x0) logerror("(disable reference interrupt)\n");
193		if (ori==0x1) logerror("(enable interrupt on reaching reference value))\n");
194		logerror("free running %d\n", frr);
195		if (frr==0x0) logerror("(free running mode, counter continues after value reached)\n");
196		if (frr==0x1) logerror("(restart mode, counter resets after value reached)\n");
197		logerror("interrupt clock source %d\n", iclk);
198		if (iclk==0x0) logerror("(stop count)\n");
199		if (iclk==0x1) logerror("(master system clock)\n");
200		if (iclk==0x2) logerror("(master system clock divided by 16)\n");
201		if (iclk==0x3) logerror("(TIN Pin)\n");
202		logerror("reset %d\n", rst);
203		if (rst==0x0) logerror("(timer is reset)\n");
204		if (rst==0x1) logerror("(timer is running)\n");
205
206		tptr->mametimer->adjust(m68k->cycles_to_attotime(100000));
207
208		logerror("\n");
209
210		}
211
212		void m68307_timer::write_trr(UINT16 data, UINT16 mem_mask, int which)
213		{
214		m68307_single_timer* tptr = &singletimer[which];
215
216		COMBINE_DATA(&tptr->regs[m68307TIMER_TRR]);
217		}
218
219
220
221		void m68307_timer::reset(void)
222		{
223		for (int i=0;i<2;i++)
224		{
225		m68307_single_timer* tptr = &singletimer[i];
226
227		tptr->regs[m68307TIMER_TMR] = 0x0000;
228		tptr->regs[m68307TIMER_TRR] = 0xffff;
229		tptr->regs[m68307TIMER_TCR] = 0x0000;
230		tptr->regs[m68307TIMER_TCN] = 0x0000;
231		tptr->regs[m68307TIMER_TER] = 0x0000;
232		tptr->regs[m68307TIMER_WRR] = 0xffff;
233		tptr->regs[m68307TIMER_WCR] = 0xffff;
234		tptr->regs[m68307TIMER_XXX] = 0;
235		tptr->enabled = false;
236		tptr->mametimer->adjust(attotime::never);
237		}
238
239		wd_mametimer->adjust(attotime::never);
240
241
242		}

trunk/src/emu/cpu/m68000/68307tmu.h

r24086	r24087
1
2		#include "m68000.h"
3
4		class m68000_base_device;
5
6
7		#define m68307TIMER_TMR (0x0)
8		#define m68307TIMER_TRR (0x1)
9		#define m68307TIMER_TCR (0x2)
10		#define m68307TIMER_TCN (0x3)
11		#define m68307TIMER_TER (0x4)
12		#define m68307TIMER_WRR (0x5)
13		#define m68307TIMER_WCR (0x6)
14		#define m68307TIMER_XXX (0x7)
15
16		struct m68307_single_timer
17		{
18		UINT16 regs[0x8];
19		bool enabled;
20		emu_timer *mametimer;
21		};
22
23
24		class m68307_timer
25		{
26		public:
27		m68307_single_timer singletimer[2];
28
29		emu_timer *wd_mametimer;
30		m68000_base_device *parent;
31
32		void write_tmr(UINT16 data, UINT16 mem_mask, int which);
33		void write_trr(UINT16 data, UINT16 mem_mask, int which);
34		void write_ter(UINT16 data, UINT16 mem_mask, int which);
35		UINT16 read_tcn(UINT16 mem_mask, int which);
36
37		void init(m68000_base_device *device);
38		void reset(void);
39		};

trunk/src/emu/cpu/m68000/m68kcpu.c

r24086	r24087
1008	1008	// disable instruction hook
1009	1009	instruction_hook = NULL;
1010	1010
1011		if (m68307SIM) m68307SIM->reset();
1012		if (m68307MBUS) m68307MBUS->reset();
1013		if (m68307SERIAL) m68307SERIAL->reset();
1014		if (m68307TIMER) m68307TIMER->reset();
1015	1011
1016		m68307_base = 0xbfff;
1017		m68307_scrhigh = 0x0007;
1018		m68307_scrlow = 0xf010;
1019	1012	}
1020	1013
1021	1014
r24086	r24087
1235	1228	write32 = m68k_write32_delegate(FUNC(address_space::write_dword), &space);
1236	1229	}
1237	1230
1238		/* todo: is it possible to calculate the address map based on CS when they change
1239		and install handlers?  Going through this logic for every memory access is
1240		very slow */
1241	1231
1242		int m68307_calc_cs(m68000_base_device *m68k, offs_t address)
1243		{
1244		m68307_sim* sim = m68k->m68307SIM;
1245
1246		for (int i=0;i<4;i++)
1247		{
1248		int br,amask,bra;
1249		br = sim->m_br[i] & 1;
1250		amask = ((sim->m_or[i]&0x1ffc)<<11);
1251		bra = ((sim->m_br[i] & 0x1ffc)<<11);
1252		if ((br) && ((address & amask) == bra)) return i+1;
1253		}
1254		return 0;
1255		}
1256
1257		/* see note above */
1258
1259	1232	int m68340_calc_cs(m68000_base_device *m68k, offs_t address)
1260	1233	{
1261	1234	m68340_sim* sim = m68k->m68340SIM;
r24086	r24087
1282	1255
1283	1256
1284	1257
1285		UINT16 m68000_base_device::simple_read_immediate_16_m68307(offs_t address)
1286		{
1287		//  m68307_currentcs = m68307_calc_cs(this, address);
1288		return m_direct->read_decrypted_word(address);
1289		}
1290	1258
1291		UINT8 m68000_base_device::read_byte_m68307(offs_t address)
1292		{
1293		//  m68307_currentcs = m68307_calc_cs(this, address);
1294		return m_space->read_byte(address);
1295		}
1296
1297		UINT16 m68000_base_device::read_word_m68307(offs_t address)
1298		{
1299		//  m68307_currentcs = m68307_calc_cs(this, address);
1300		return m_space->read_word(address);
1301		}
1302
1303		UINT32 m68000_base_device::read_dword_m68307(offs_t address)
1304		{
1305		//  m68307_currentcs = m68307_calc_cs(this, address);
1306		return m_space->read_dword(address);
1307		}
1308
1309		void m68000_base_device::write_byte_m68307(offs_t address, UINT8 data)
1310		{
1311		//  m68307_currentcs = m68307_calc_cs(this, address);
1312		m_space->write_byte(address, data);
1313		}
1314
1315		void m68000_base_device::write_word_m68307(offs_t address, UINT16 data)
1316		{
1317		//  m68307_currentcs = m68307_calc_cs(this, address);
1318		m_space->write_word(address, data);
1319		}
1320
1321		void m68000_base_device::write_dword_m68307(offs_t address, UINT32 data)
1322		{
1323		//  m68307_currentcs = m68307_calc_cs(this, address);
1324		m_space->write_dword(address, data);
1325		}
1326
1327
1328
1329
1330		void m68000_base_device::init16_m68307(address_space &space)
1331		{
1332		m_space = &space;
1333		m_direct = &space.direct();
1334		opcode_xor = 0;
1335
1336		readimm16 = m68k_readimm16_delegate(FUNC(m68000_base_device::simple_read_immediate_16_m68307), this);
1337		read8 = m68k_read8_delegate(FUNC(m68000_base_device::read_byte_m68307), this);
1338		read16 = m68k_read16_delegate(FUNC(m68000_base_device::read_word_m68307), this);
1339		read32 = m68k_read32_delegate(FUNC(m68000_base_device::read_dword_m68307), this);
1340		write8 = m68k_write8_delegate(FUNC(m68000_base_device::write_byte_m68307), this);
1341		write16 = m68k_write16_delegate(FUNC(m68000_base_device::write_word_m68307), this);
1342		write32 = m68k_write32_delegate(FUNC(m68000_base_device::write_dword_m68307), this);
1343		}
1344
1345	1259	/****************************************************************************
1346	1260	* 32-bit data memory interface
1347	1261	****************************************************************************/
r24086	r24087
1730	1644	return device->mmu_tmp_fc;
1731	1645	}
1732	1646
1733		void m68307_set_port_callbacks(m68000_base_device *device, m68307_porta_read_callback porta_r, m68307_porta_write_callback porta_w, m68307_portb_read_callback portb_r, m68307_portb_write_callback portb_w)
1734		{
1735		device->m_m68307_porta_r = porta_r;
1736		device->m_m68307_porta_w = porta_w;
1737		device->m_m68307_portb_r = portb_r;
1738		device->m_m68307_portb_w = portb_w;
1739		}
1740	1647
1741		void m68307_set_duart68681(m68000_base_device* cpudev, device_t* duart68681)
1742		{
1743		if (cpudev->m68307SERIAL)
1744		cpudev->m68307SERIAL->m68307ser_set_duart68681(duart68681);
1745		}
1746
1747
1748
1749
1750		UINT16 m68307_get_cs(m68000_base_device *device, offs_t address)
1751		{
1752		device->m68307_currentcs = m68307_calc_cs(device, address);
1753
1754		return device->m68307_currentcs;
1755		}
1756
1757	1648	UINT16 m68340_get_cs(m68000_base_device *device, offs_t address)
1758	1649	{
1759		device->m68307_currentcs = m68340_calc_cs(device, address);
	1650	device->m68340_currentcs = m68340_calc_cs(device, address);
1760	1651
1761		return device->m68307_currentcs;
	1652	return device->m68340_currentcs;
1762	1653	}
1763	1654
1764	1655	/****************************************************************************
r24086	r24087
1813	1704	}
1814	1705
1815	1706
1816		/* 68307 specifics - MOVE */
1817
1818		void m68307_set_interrupt(device_t *device, int level, int vector)
1819		{
1820		device->execute().set_input_line_and_vector(level, HOLD_LINE, vector);
1821		}
1822
1823		void m68307_timer0_interrupt(m68000_base_device *cpudev)
1824		{
1825		int prioritylevel = (cpudev->m68307SIM->m_picr & 0x7000)>>12;
1826		int vector        = (cpudev->m68307SIM->m_pivr & 0x00f0) | 0xa;
1827		m68307_set_interrupt(cpudev, prioritylevel, vector);
1828		}
1829
1830		void m68307_timer1_interrupt(m68000_base_device *cpudev)
1831		{
1832		int prioritylevel = (cpudev->m68307SIM->m_picr & 0x0700)>>8;
1833		int vector        = (cpudev->m68307SIM->m_pivr & 0x00f0) | 0xb;
1834		m68307_set_interrupt(cpudev, prioritylevel, vector);
1835		}
1836
1837		void m68307_serial_interrupt(m68000_base_device *cpudev, int vector)
1838		{
1839		int prioritylevel = (cpudev->m68307SIM->m_picr & 0x0070)>>4;
1840		m68307_set_interrupt(cpudev, prioritylevel, vector);
1841		}
1842
1843		void m68307_mbus_interrupt(m68000_base_device *cpudev)
1844		{
1845		int prioritylevel = (cpudev->m68307SIM->m_picr & 0x0007)>>0;
1846		int vector        = (cpudev->m68307SIM->m_pivr & 0x00f0) | 0xd;
1847		m68307_set_interrupt(cpudev, prioritylevel, vector);
1848		}
1849
1850		void m68307_licr2_interrupt(m68000_base_device *cpudev)
1851		{
1852		int prioritylevel = (cpudev->m68307SIM->m_licr2 & 0x0007)>>0;
1853		int vector        = (cpudev->m68307SIM->m_pivr & 0x00f0) | 0x9;
1854		cpudev->m68307SIM->m_licr2 |= 0x8;
1855
1856
1857		m68307_set_interrupt(cpudev, prioritylevel, vector);
1858		}
1859
1860		void m68000_base_device::init_cpu_m68307(void)
1861		{
1862		init_cpu_m68000();
1863
1864		/* basic CS logic, timers, mbus, serial logic
1865		set via remappable register
1866		*/
1867
1868		init16_m68307(*program);
1869
1870		m68307SIM    = new m68307_sim();
1871		m68307MBUS   = new m68307_mbus();
1872		m68307SERIAL = new m68307_serial();
1873		m68307TIMER  = new m68307_timer();
1874
1875		m68307TIMER->init(this);
1876
1877		m68307SIM->reset();
1878		m68307MBUS->reset();
1879		m68307SERIAL->reset();
1880		m68307TIMER->reset();
1881
1882		internal = &this->space(AS_PROGRAM);
1883		m68307_base = 0xbfff;
1884		m68307_scrhigh = 0x0007;
1885		m68307_scrlow = 0xf010;
1886
1887		m68307_set_port_callbacks(this, 0,0,0,0);
1888		}
1889
1890
1891
1892		READ16_MEMBER( m68000_base_device::m68307_internal_base_r )
1893		{
1894		m68000_base_device *m68k = this;
1895
1896		int pc = space.device().safe_pc();
1897		logerror("%08x m68307_internal_base_r %08x, (%04x)\n", pc, offset*2,mem_mask);
1898
1899		switch (offset<<1)
1900		{
1901		case 0x2: return m68k->m68307_base;
1902		case 0x4: return m68k->m68307_scrhigh;
1903		case 0x6: return m68k->m68307_scrlow;
1904		}
1905
1906		logerror("(read was illegal?)\n");
1907
1908		return 0x0000;
1909		}
1910
1911		WRITE16_MEMBER( m68000_base_device::m68307_internal_base_w )
1912		{
1913		m68000_base_device *m68k = this;
1914
1915		int pc = space.device().safe_pc();
1916		logerror("%08x m68307_internal_base_w %08x, %04x (%04x)\n", pc, offset*2,data,mem_mask);
1917		int base = 0;
1918		//int mask = 0;
1919
1920		switch (offset<<1)
1921		{
1922		case 0x2:
1923		/* remove old internal handler */
1924		base = (m68k->m68307_base & 0x0fff) << 12;
1925		//mask = (m68k->m68307_base & 0xe000) >> 13;
1926		//if ( m68k->m68307_base & 0x1000 ) mask |= 7;
1927		m68k->internal->unmap_readwrite(base+0x000, base+0x04f);
1928		m68k->internal->unmap_readwrite(base+0x100, base+0x11f);
1929		m68k->internal->unmap_readwrite(base+0x120, base+0x13f);
1930		m68k->internal->unmap_readwrite(base+0x140, base+0x149);
1931
1932		/* store new base address */
1933		COMBINE_DATA(&m68k->m68307_base);
1934
1935		/* install new internal handler */
1936		base = (m68k->m68307_base & 0x0fff) << 12;
1937		//mask = (m68k->m68307_base & 0xe000) >> 13;
1938		//if ( m68k->m68307_base & 0x1000 ) mask |= 7;
1939		m68k->internal->install_readwrite_handler(base + 0x000, base + 0x04f, read16_delegate(FUNC(m68000_base_device::m68307_internal_sim_r),this),    write16_delegate(FUNC(m68000_base_device::m68307_internal_sim_w),this));
1940		m68k->internal->install_readwrite_handler(base + 0x100, base + 0x11f, read8_delegate(FUNC(m68000_base_device::m68307_internal_serial_r),this), write8_delegate(FUNC(m68000_base_device::m68307_internal_serial_w),this), 0xffff);
1941		m68k->internal->install_readwrite_handler(base + 0x120, base + 0x13f, read16_delegate(FUNC(m68000_base_device::m68307_internal_timer_r),this),  write16_delegate(FUNC(m68000_base_device::m68307_internal_timer_w),this));
1942		m68k->internal->install_readwrite_handler(base + 0x140, base + 0x149, read8_delegate(FUNC(m68000_base_device::m68307_internal_mbus_r),this),   write8_delegate(FUNC(m68000_base_device::m68307_internal_mbus_w),this), 0xffff);
1943
1944
1945		break;
1946
1947		case 0x4:
1948		COMBINE_DATA(&m68k->m68307_scrhigh);
1949		break;
1950
1951		case 0x6:
1952		COMBINE_DATA(&m68k->m68307_scrlow);
1953		break;
1954
1955		default:
1956		logerror("(write was illegal?)\n");
1957		break;
1958		}
1959		}
1960
1961		static ADDRESS_MAP_START( m68307_internal_map, AS_PROGRAM, 16, m68000_base_device )
1962		AM_RANGE(0x000000f0, 0x000000ff) AM_READWRITE(m68307_internal_base_r, m68307_internal_base_w)
1963		ADDRESS_MAP_END
1964
1965	1707	/* 68340 specifics - MOVE */
1966	1708
1967	1709	READ32_MEMBER( m68000_base_device::m68340_internal_base_r )
r24086	r24087
2511	2253	offs_t m68000_base_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68000)(this, buffer, pc, oprom, opram, options); };
2512	2254	offs_t m68000_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68000)(this, buffer, pc, oprom, opram, options); };
2513	2255	offs_t m68301_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68000)(this, buffer, pc, oprom, opram, options); };
2514		offs_t m68307_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68000)(this, buffer, pc, oprom, opram, options); };
2515	2256	offs_t m68008_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68008)(this, buffer, pc, oprom, opram, options); };
2516	2257	offs_t m68008plcc_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68008)(this, buffer, pc, oprom, opram, options); };
2517	2258	offs_t m68010_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68010)(this, buffer, pc, oprom, opram, options); };
r24086	r24087
2756	2497	for (int i=0;i<M68K_IC_SIZE;i++)
2757	2498	ic_data[i] = 0;
2758	2499
2759		m68307SIM = 0;
2760		m68307MBUS = 0;
2761		m68307SERIAL = 0;
2762		m68307TIMER = 0;
2763		m68307_base = 0;
2764		m68307_scrhigh = 0;
2765		m68307_scrlow = 0;
2766		m68307_currentcs = 0;
2767	2500	m68340SIM = 0;
2768	2501	m68340DMA = 0;
2769	2502	m68340SERIAL = 0;
2770	2503	m68340TIMER = 0;
2771	2504	m68340_base = 0;
2772	2505	internal = 0;
2773		m_m68307_porta_r = 0;
2774		m_m68307_porta_w = 0;
2775		m_m68307_portb_r = 0;
2776		m_m68307_portb_w = 0;
	2506
2777	2507	instruction_hook = 0;
2778	2508	}
2779	2509
r24086	r24087
2842	2572
2843	2573	const device_type M68000 = &device_creator<m68000_device>;
2844	2574	const device_type M68301 = &device_creator<m68301_device>;
2845		const device_type M68307 = &device_creator<m68307_device>;
2846	2575	const device_type M68008 = &device_creator<m68008_device>;
2847	2576	const device_type M68008PLCC = &device_creator<m68008plcc_device>;
2848	2577	const device_type M68010 = &device_creator<m68010_device>;
r24086	r24087
2870	2599	init_cpu_m68000();
2871	2600	}
2872	2601
	2602	m68000_device::m68000_device(const machine_config &mconfig, const char *name, const char *tag, device_t *owner, UINT32 clock,
	2603	const device_type type, UINT32 prg_data_width, UINT32 prg_address_bits, address_map_constructor internal_map, const char *shortname, const char *source)
	2604	: m68000_base_device(mconfig, name, tag, owner, clock, type, prg_data_width, prg_address_bits, internal_map, shortname, source)
	2605	{
2873	2606
	2607	}
2874	2608
2875	2609
	2610
	2611
	2612
2876	2613	m68301_device::m68301_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
2877	2614	: m68000_base_device(mconfig, "M68301", tag, owner, clock, M68301, 16,24, "m68301", __FILE__)
2878	2615	{
r24086	r24087
2888	2625
2889	2626
2890	2627
2891		m68307_device::m68307_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
2892		: m68000_base_device(mconfig, "M68307", tag, owner, clock, M68307, 16,24, ADDRESS_MAP_NAME(m68307_internal_map), "m68307", __FILE__)
2893		{
2894	2628
2895		}
2896	2629
2897		void m68307_device::device_start()
2898		{
2899		init_cpu_m68307();
2900		}
2901
2902	2630	/* m68008_device */
2903	2631
2904	2632	m68008_device::m68008_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)

trunk/src/emu/cpu/m68000/m68000.h

r24086	r24087
4	4	#define __M68000_H__
5	5
6	6
7		#include "68307sim.h"
8		#include "68307bus.h"
9		#include "68307ser.h"
10		#include "68307tmu.h"
11	7
12	8	#include "68340sim.h"
13	9	#include "68340dma.h"
r24086	r24087
125	121	typedef void (*m68k_rte_func)(device_t *device);
126	122	typedef int (*m68k_tas_func)(device_t *device);
127	123
128		typedef UINT8 (*m68307_porta_read_callback)(address_space &space, bool dedicated, UINT8 line_mask);
129		typedef void (*m68307_porta_write_callback)(address_space &space, bool dedicated, UINT8 data, UINT8 line_mask);
130		typedef UINT16 (*m68307_portb_read_callback)(address_space &space, bool dedicated, UINT16 line_mask);
131		typedef void (*m68307_portb_write_callback)(address_space &space, bool dedicated, UINT16 data, UINT16 line_mask);
132	124
133	125
134	126
135	127
136	128	unsigned int m68k_disassemble_raw(char* str_buff, unsigned int pc, const unsigned char* opdata, const unsigned char* argdata, unsigned int cpu_type);
137	129
	130	class m68000_base_device;
138	131
139	132
	133	extern UINT16 m68340_get_cs(m68000_base_device *device, offs_t address);
	134
140	135	typedef int (*instruction_hook_t)(m68000_base_device *device, offs_t curpc);
141	136
142	137
r24086	r24087
287	282	public:
288	283	void init8(address_space &space);
289	284	void init16(address_space &space);
290		void init16_m68307(address_space &space);
291	285	void init32(address_space &space);
292	286	void init32mmu(address_space &space);
293	287	void init32hmmu(address_space &space);
r24086	r24087
306	300	UINT16 read_immediate_16(offs_t address);
307	301	UINT16 simple_read_immediate_16(offs_t address);
308	302
309		UINT16 simple_read_immediate_16_m68307(offs_t address);
310		UINT8 read_byte_m68307(offs_t address);
311		UINT16 read_word_m68307(offs_t address);
312		UINT32 read_dword_m68307(offs_t address);
313		void write_byte_m68307(offs_t address, UINT8 data);
314		void write_word_m68307(offs_t address, UINT16 data);
315		void write_dword_m68307(offs_t address, UINT32 data);
316	303
317	304	UINT8 read_byte_32_mmu(offs_t address);
318	305	void write_byte_32_mmu(offs_t address, UINT8 data);
r24086	r24087
330	317	UINT32 readlong_d32_hmmu(offs_t address);
331	318	void writelong_d32_hmmu(offs_t address, UINT32 data);
332	319
333		address_space *m_space;
334		direct_read_data *m_direct;
335	320	//      m68000_base_device *m_cpustate;
336	321	//   };
337	322
338	323	public:
339	324	//   m68k_memory_interface memory;
	325
	326	address_space *m_space;
	327	direct_read_data *m_direct;
	328
340	329	offs_t encrypted_start;
341	330	offs_t encrypted_end;
342	331
r24086	r24087
371	360	UINT32 ic_address[M68K_IC_SIZE];   /* instruction cache address data */
372	361	UINT16 ic_data[M68K_IC_SIZE];      /* instruction cache content data */
373	362
374		/* 68307 peripheral modules */
375		m68307_sim*    m68307SIM;
376		m68307_mbus*   m68307MBUS;
377		m68307_serial* m68307SERIAL;
378		m68307_timer*  m68307TIMER;
379	363
380		UINT16 m68307_base;
381		UINT16 m68307_scrhigh;
382		UINT16 m68307_scrlow;
	364	int m68340_currentcs;
383	365
384		int m68307_currentcs;
385
386	366	/* 68340 peripheral modules */
387	367	m68340_sim*    m68340SIM;
388	368	m68340_dma*    m68340DMA;
r24086	r24087
392	372	UINT32 m68340_base;
393	373
394	374
395		DECLARE_READ16_MEMBER( m68307_internal_base_r );
396		DECLARE_WRITE16_MEMBER( m68307_internal_base_w );
397		DECLARE_READ16_MEMBER( m68307_internal_timer_r );
398		DECLARE_WRITE16_MEMBER( m68307_internal_timer_w );
399		DECLARE_READ16_MEMBER( m68307_internal_sim_r );
400		DECLARE_WRITE16_MEMBER( m68307_internal_sim_w );
401		DECLARE_READ8_MEMBER( m68307_internal_serial_r );
402		DECLARE_WRITE8_MEMBER( m68307_internal_serial_w );
403		DECLARE_READ8_MEMBER( m68307_internal_mbus_r );
404		DECLARE_WRITE8_MEMBER( m68307_internal_mbus_w );
405	375
406	376	READ32_MEMBER( m68340_internal_base_r );
407	377	WRITE32_MEMBER( m68340_internal_base_w );
r24086	r24087
419	389	WRITE32_MEMBER( m68340_internal_timer_w );
420	390
421	391
422		/* 68308 / 68340 internal address map */
	392	/* 68307 / 68340 internal address map */
423	393	address_space *internal;
424	394
425		/* callbacks for internal ports */
426		m68307_porta_read_callback m_m68307_porta_r;
427		m68307_porta_write_callback m_m68307_porta_w;
428		m68307_portb_read_callback m_m68307_portb_r;
429		m68307_portb_write_callback m_m68307_portb_w;
430	395
431	396
432
433	397	/* external instruction hook (does not depend on debug mode) */
434	398	instruction_hook_t instruction_hook;
435	399
r24086	r24087
437	401
438	402	void init_cpu_common(void);
439	403	void init_cpu_m68000(void);
440		void init_cpu_m68307(void);
441	404	void init_cpu_m68008(void);
442	405	void init_cpu_m68010(void);
443	406	void init_cpu_m68020(void);
r24086	r24087
476	439	// construction/destruction
477	440	m68000_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
478	441
	442	m68000_device(const machine_config &mconfig, const char *name, const char *tag, device_t *owner, UINT32 clock,
	443	const device_type type, UINT32 prg_data_width, UINT32 prg_address_bits, address_map_constructor internal_map, const char *shortname, const char *source);
	444
	445
	446
479	447	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
480	448	virtual UINT32 disasm_max_opcode_bytes() const { return 10; };
481	449	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
r24086	r24087
511	479	};
512	480
513	481
514		class m68307_device : public m68000_base_device
515		{
516		public:
517		// construction/destruction
518		m68307_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
519	482
520		virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
521		virtual UINT32 disasm_max_opcode_bytes() const { return 10; };
522		virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
523	483
524		virtual UINT32 execute_min_cycles() const { return 4; };
525		virtual UINT32 execute_max_cycles() const { return 158; };
526
527		virtual UINT32 execute_default_irq_vector() const { return -1; };
528
529		// device-level overrides
530		virtual void device_start();
531		protected:
532		};
533
534	484	class m68008_device : public m68000_base_device
535	485	{
536	486	public:
r24086	r24087
842	792
843	793	extern const device_type M68000;
844	794	extern const device_type M68301;
845		extern const device_type M68307;
846	795	extern const device_type M68008;
847	796	extern const device_type M68008PLCC;
848	797	extern const device_type M68010;
r24086	r24087
864	813	extern void m68k_set_rte_callback(m68000_base_device *device, m68k_rte_func callback);
865	814	extern void m68k_set_tas_callback(m68000_base_device *device, m68k_tas_func callback);
866	815	extern UINT16 m68k_get_fc(m68000_base_device *device);
867		extern void m68307_set_port_callbacks(m68000_base_device *device, m68307_porta_read_callback porta_r, m68307_porta_write_callback porta_w, m68307_portb_read_callback portb_r, m68307_portb_write_callback portb_w);
868		extern void m68307_set_duart68681(m68000_base_device* cpudev, device_t* duart68681);
869		extern UINT16 m68307_get_cs(m68000_base_device *device, offs_t address);
870		extern UINT16 m68340_get_cs(m68000_base_device *device, offs_t address);
871		extern void m68307_timer0_interrupt(m68000_base_device *cpudev);
872		extern void m68307_timer1_interrupt(m68000_base_device *cpudev);
873		extern void m68307_serial_interrupt(m68000_base_device *cpudev, int vector);
874		extern void m68307_mbus_interrupt(m68000_base_device *cpudev);
875		extern void m68307_licr2_interrupt(m68000_base_device *cpudev);
876	816	extern void m68k_set_encrypted_opcode_range(m68000_base_device *device, offs_t start, offs_t end);
877	817	extern void m68k_set_hmmu_enable(m68000_base_device *device, int enable);
878	818	extern void m68k_set_instruction_hook(m68000_base_device *device, instruction_hook_t ihook);

trunk/src/emu/cpu/cpu.mak

r24086	r24087
1354	1354	ifneq ($(filter M680X0,$(CPUS)),)
1355	1355	OBJDIRS += $(CPUOBJ)/m68000
1356	1356	CPUOBJS += $(CPUOBJ)/m68000/m68kcpu.o $(CPUOBJ)/m68000/m68kops.o \
1357		$(CPUOBJ)/m68000/68307sim.o \
1358		$(CPUOBJ)/m68000/68307bus.o \
1359		$(CPUOBJ)/m68000/68307ser.o \
1360		$(CPUOBJ)/m68000/68307tmu.o \
1361	1357	$(CPUOBJ)/m68000/68340sim.o \
1362	1358	$(CPUOBJ)/m68000/68340dma.o \
1363	1359	$(CPUOBJ)/m68000/68340ser.o \
r24086	r24087
1400	1396
1401	1397	# m68kcpu.h now includes m68kops.h; m68kops.h won't exist until m68kops.c has been made
1402	1398	$(CPUSRC)/m68000/m68kcpu.h: $(CPUOBJ)/m68000/m68kops.c
1403		$(CPUSRC)/m68000/68307sim.c: $(CPUOBJ)/m68000/m68kops.c
1404		$(CPUSRC)/m68000/68307bus.c: $(CPUOBJ)/m68000/m68kops.c
1405		$(CPUSRC)/m68000/68307ser.c: $(CPUOBJ)/m68000/m68kops.c
1406		$(CPUSRC)/m68000/68307tmu.c: $(CPUOBJ)/m68000/m68kops.c
1407	1399	$(CPUSRC)/m68000/68340sim.c: $(CPUOBJ)/m68000/m68kops.c
	1400
1408	1401	$(CPUSRC)/m68000/68340dma.c: $(CPUOBJ)/m68000/m68kops.c
	1402
1409	1403	$(CPUSRC)/m68000/68340ser.c: $(CPUOBJ)/m68000/m68kops.c
1410	1404	$(CPUSRC)/m68000/68340tmu.c: $(CPUOBJ)/m68000/m68kops.c
1411	1405

trunk/src/emu/machine/68307ser.h

r0	r24087
	1	#include "cpu/m68000/m68000.h"
	2	#include "machine/68681.h"
	3
	4	#define m68307SER_UMR1_UMR2  (0x01)
	5	#define m68307SER_USR_UCSR   (0x03)
	6	#define m68307SER_UCR        (0x05)
	7	#define m68307SER_URB_UTB    (0x07)
	8	#define m68307SER_UIPCR_UACR (0x09)
	9	#define m68307SER_UISR_UIMR  (0x0b)
	10	#define m68307SER_UBG1       (0x0d)
	11	#define m68307SER_UBG2       (0x0f)
	12	//                           (0x11)
	13	//                           (0x13)
	14	//                           (0x15)
	15	//                           (0x17)
	16	#define m68307SER_UIVR       (0x19)
	17	#define m68307SER_UIP        (0x1b)
	18	#define m68307SER_UOP1       (0x1d)
	19	#define m68307SER_UOP0       (0x1f)
	20
	21	class m68307_serial
	22	{
	23	public:
	24	void reset(void);
	25	UINT8 m_uivr;
	26
	27	void m68307ser_set_duart68681(device_t* duart68681)
	28	{
	29	m_duart68681 = duart68681;
	30	}
	31
	32	device_t* m_duart68681;
	33	};

Property changes on: trunk/src/emu/machine/68307ser.h

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/emu/machine/68307sim.c

r0	r24087
	1	/* 68307 SIM module */
	2
	3	#include "emu.h"
	4	#include "68307.h"
	5
	6
	7	READ16_MEMBER( m68307cpu_device::m68307_internal_sim_r )
	8	{
	9	m68307cpu_device *m68k = this;
	10	m68307_sim* sim = m68k->m68307SIM;
	11	assert(sim != NULL);
	12
	13	int pc = space.device().safe_pc();
	14
	15	if (sim)
	16	{
	17	switch (offset<<1)
	18	{
	19	case m68307SIM_PADAT: return sim->read_padat(this, space, mem_mask);
	20	case m68307SIM_PBDAT: return sim->read_pbdat(this, space, mem_mask);
	21
	22	case m68307SIM_LICR2: return  (sim->m_licr2);
	23
	24	case m68307SIM_BR0: return (sim->m_br[0]);
	25	case m68307SIM_OR0: return (sim->m_or[0]);
	26	case m68307SIM_BR1: return (sim->m_br[1]);
	27	case m68307SIM_OR1: return (sim->m_or[1]);
	28	case m68307SIM_BR2: return (sim->m_br[2]);
	29	case m68307SIM_OR2: return (sim->m_or[2]);
	30	case m68307SIM_BR3: return (sim->m_br[3]);
	31	case m68307SIM_OR3: return (sim->m_or[3]);
	32
	33	default:
	34	logerror("%08x m68307_internal_sim_r %08x, (%04x)\n", pc, offset*2,mem_mask);
	35	return 0xff;
	36
	37	}
	38	}
	39
	40	return 0x0000;
	41	}
	42
	43
	44	WRITE16_MEMBER( m68307cpu_device::m68307_internal_sim_w )
	45	{
	46	m68307cpu_device *m68k = this;
	47	m68307_sim* sim = m68k->m68307SIM;
	48	assert(sim != NULL);
	49
	50	int pc = space.device().safe_pc();
	51
	52	if (sim)
	53	{
	54	switch (offset<<1)
	55	{
	56	case m68307SIM_PACNT:
	57	logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Control Register - PACNT)\n", pc, offset*2,data,mem_mask);
	58	sim->write_pacnt(data,mem_mask);
	59	break;
	60
	61	case m68307SIM_PADDR:
	62	logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Direction Register - PADDR)\n", pc, offset*2,data,mem_mask);
	63	sim->write_paddr(data,mem_mask);
	64	break;
	65
	66	case m68307SIM_PADAT:
	67	sim->write_padat(this, space, data,mem_mask);
	68	break;
	69
	70	case m68307SIM_PBCNT:
	71	logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Control Register - PBCNT)\n", pc, offset*2,data,mem_mask);
	72	sim->write_pbcnt(data,mem_mask);
	73	break;
	74
	75	case m68307SIM_PBDDR:
	76	logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Direction Register - PBDDR)\n", pc, offset*2,data,mem_mask);
	77	sim->write_pbddr(data,mem_mask);
	78	break;
	79
	80	case m68307SIM_PBDAT:
	81	sim->write_pbdat(this, space, data, mem_mask);
	82	break;
	83
	84
	85	case m68307SIM_LICR1:
	86	logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 1 - LICR1)\n", pc, offset*2,data,mem_mask);
	87	sim->write_licr1(data,mem_mask);
	88	break;
	89
	90	case m68307SIM_LICR2:
	91	logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 2 - LICR2)\n", pc, offset*2,data,mem_mask);
	92	sim->write_licr2(data,mem_mask);
	93	break;
	94
	95	case m68307SIM_PICR:
	96	logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Control Register - PICR)\n", pc, offset*2,data,mem_mask);
	97	sim->write_picr(data,mem_mask);
	98	break;
	99
	100	case m68307SIM_PIVR:
	101	logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Vector Register - PIVR)\n", pc, offset*2,data,mem_mask);
	102	sim->write_pivr(data,mem_mask);
	103	break;
	104
	105	case m68307SIM_BR0:
	106	COMBINE_DATA(&sim->m_br[0]);
	107	break;
	108	case m68307SIM_OR0:
	109	COMBINE_DATA(&sim->m_or[0]);
	110	break;
	111	case m68307SIM_BR1:
	112	COMBINE_DATA(&sim->m_br[1]);
	113	break;
	114	case m68307SIM_OR1:
	115	COMBINE_DATA(&sim->m_or[1]);
	116	break;
	117	case m68307SIM_BR2:
	118	COMBINE_DATA(&sim->m_br[2]);
	119	break;
	120	case m68307SIM_OR2:
	121	COMBINE_DATA(&sim->m_or[2]);
	122	break;
	123	case m68307SIM_BR3:
	124	COMBINE_DATA(&sim->m_br[3]);
	125	break;
	126	case m68307SIM_OR3:
	127	COMBINE_DATA(&sim->m_or[3]);
	128	break;
	129
	130
	131
	132	default :
	133	logerror("%08x m68307_internal_sim_w %08x, %04x (%04x)\n", pc, offset*2,data,mem_mask);
	134	break;
	135
	136	}
	137	}
	138	}
	139
	140
	141	void m68307_sim::write_pacnt(UINT16 data, UINT16 mem_mask)
	142	{
	143	COMBINE_DATA(&m_pacnt);
	144	}
	145
	146	void m68307_sim::write_paddr(UINT16 data, UINT16 mem_mask)
	147	{
	148	COMBINE_DATA(&m_paddr);
	149	}
	150
	151
	152	UINT16 m68307_sim::read_padat(m68307cpu_device* m68k, address_space &space, UINT16 mem_mask)
	153	{
	154	int pc = space.device().safe_pc();
	155
	156	if (m68k->m_m68307_porta_r)
	157	{
	158	// for general purpose bits, if configured as 'output' then anything output gets latched
	159	// and anything configured as input is read from the port
	160	UINT8 outputbits = m_paddr;
	161	UINT8 inputbits = ~m_paddr;
	162	UINT8 general_purpose_bits = ~m_pacnt;
	163	UINT8 indat = m68k->m_m68307_porta_r(space, false, (inputbits & general_purpose_bits)&mem_mask) & ((inputbits & general_purpose_bits) & mem_mask); // read general purpose input lines
	164	indat |= m68k->m_m68307_porta_r(space, true, (inputbits & ~general_purpose_bits)&mem_mask) & ((inputbits & ~general_purpose_bits)& mem_mask); // read dedicated input lines
	165	UINT8 outdat = (m_padat & outputbits) & general_purpose_bits; // read general purpose output lines (reads latched data)
	166
	167	return (indat | outdat);
	168
	169	}
	170	else
	171	{
	172	logerror("%08x m68307_internal_sim_r (%04x) (Port A (8-bit) Data Register - PADAT)\n", pc, mem_mask);
	173	}
	174	return 0xffff;
	175	}
	176
	177
	178	void m68307_sim::write_padat(m68307cpu_device* m68k, address_space &space, UINT16 data, UINT16 mem_mask)
	179	{
	180	int pc = space.device().safe_pc();
	181	COMBINE_DATA(&m_padat);
	182
	183	if (m68k->m_m68307_porta_w)
	184	{
	185	m68k->m_m68307_porta_w(space, false, data, 0xff);
	186	}
	187	else
	188	{
	189	logerror("%08x m68307_internal_sim_w %04x (%04x) (Port A (8-bit) Data Register - PADAT)\n", pc, data,mem_mask);
	190	}
	191	}
	192
	193	void m68307_sim::write_pbcnt(UINT16 data, UINT16 mem_mask)
	194	{
	195	COMBINE_DATA(&m_pbcnt);
	196	}
	197
	198	void m68307_sim::write_pbddr(UINT16 data, UINT16 mem_mask)
	199	{
	200	COMBINE_DATA(&m_pbddr);
	201	}
	202
	203	UINT16 m68307_sim::read_pbdat(m68307cpu_device* m68k, address_space &space, UINT16 mem_mask)
	204	{
	205	int pc = space.device().safe_pc();
	206
	207	if (m68k->m_m68307_portb_r)
	208	{
	209	// for general purpose bits, if configured as 'output' then anything output gets latched
	210	// and anything configured as input is read from the port
	211	UINT16 outputbits = m_pbddr;
	212	UINT16 inputbits = ~m_pbddr;
	213	UINT16 general_purpose_bits = ~m_pbcnt;
	214
	215	UINT16 indat = m68k->m_m68307_portb_r(space, false, (inputbits & general_purpose_bits)&mem_mask) & ((inputbits & general_purpose_bits) & mem_mask); // read general purpose input lines
	216	indat |= m68k->m_m68307_portb_r(space, true, (inputbits & ~general_purpose_bits)&mem_mask) & ((inputbits & ~general_purpose_bits)& mem_mask); // read dedicated input lines
	217	UINT16 outdat = (m_pbdat & outputbits) & general_purpose_bits; // read general purpose output lines (reads latched data)
	218
	219	return (indat | outdat);
	220	}
	221	else
	222	{
	223	logerror("%08x m68307_internal_sim_r (%04x) (Port B (16-bit) Data Register - PBDAT)\n", pc, mem_mask);
	224	}
	225	return 0xffff;
	226	}
	227
	228
	229	void m68307_sim::write_pbdat(m68307cpu_device* m68k, address_space &space, UINT16 data, UINT16 mem_mask)
	230	{
	231	int pc = space.device().safe_pc();
	232	COMBINE_DATA(&m_pbdat);
	233
	234	if (m68k->m_m68307_portb_w)
	235	{
	236	m68k->m_m68307_portb_w(space, false, data, mem_mask);
	237	}
	238	else
	239	{
	240	logerror("%08x m68307_internal_sim_w %04x (%04x) (Port B (16-bit) Data Register - PBDAT)\n", pc, data,mem_mask);
	241	}
	242	}
	243
	244	void m68307_sim::write_licr1(UINT16 data, UINT16 mem_mask)
	245	{
	246	COMBINE_DATA(&m_licr1);
	247	data = m_licr1;
	248	logerror("m_licr1 value %04x : Details :\n", data);
	249	logerror("int4ipl %01x\n", (data>>0)&7);
	250	logerror("pir4    %01x\n", (data>>3)&1);
	251	logerror("int3ipl %01x\n", (data>>4)&7);
	252	logerror("pir3    %01x\n", (data>>7)&1);
	253	logerror("int2ipl %01x\n", (data>>8)&7);
	254	logerror("pir2    %01x\n", (data>>11)&1);
	255	logerror("int1ipl %01x\n", (data>>12)&7);
	256	logerror("pir1    %01x\n", (data>>15)&1);
	257	logerror("\n");
	258	}
	259
	260	void m68307_sim::write_licr2(UINT16 data, UINT16 mem_mask)
	261	{
	262	COMBINE_DATA(&m_licr2);
	263	UINT16 newdata = m_licr2;
	264	logerror("m_licr2 value %04x : Details :\n", newdata);
	265	logerror("int8ipl %01x\n", (newdata>>0)&7);
	266	logerror("pir8    %01x\n", (newdata>>3)&1);
	267	logerror("int7ipl %01x\n", (newdata>>4)&7);
	268	logerror("pir7    %01x\n", (newdata>>7)&1);
	269	logerror("int6ipl %01x\n", (newdata>>8)&7);
	270	logerror("pir6    %01x\n", (newdata>>11)&1);
	271	logerror("int5ipl %01x\n", (newdata>>12)&7);
	272	logerror("pir5    %01x\n", (newdata>>15)&1);
	273	logerror("\n");
	274
	275	if (data & 0x0008) m_licr2 = m_licr2 & ~0x0008;
	276	if (data & 0x0080) m_licr2 = m_licr2 & ~0x0080;
	277	if (data & 0x0800) m_licr2 = m_licr2 & ~0x0800;
	278	if (data & 0x8000) m_licr2 = m_licr2 & ~0x8000;
	279
	280
	281	}
	282
	283
	284	void m68307_sim::write_picr(UINT16 data, UINT16 mem_mask)
	285	{
	286	COMBINE_DATA(&m_picr);
	287	data = m_picr;
	288	logerror("picr value %04x : Details :\n", data);
	289	logerror("mbipl %01x\n", (data>>0)&7);
	290	logerror("uaipl %01x\n", (data>>4)&7);
	291	logerror("t2ipl %01x\n", (data>>8)&7);
	292	logerror("t1ipl %01x\n", (data>>12)&7);
	293	logerror("\n");
	294	}
	295
	296	void m68307_sim::write_pivr(UINT16 data, UINT16 mem_mask)
	297	{
	298	COMBINE_DATA(&m_pivr);
	299	data = m_pivr;
	300	logerror("pivr value %04x : Details :\n", data);
	301	logerror("unused %01x\n", (data>>0)&0xf);
	302	logerror("high vector %01x\n", (data>>4)&0xf);
	303	}
	304
	305	void m68307_sim::reset(void)
	306	{
	307	for (int i=0;i<4;i++)
	308	{
	309	m_br[i] = 0xc001;
	310	m_or[i] = 0xdffd;
	311	}
	312	}

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trunk/src/emu/machine/68307sim.h

r0	r24087
	1	/* 68307 SIM module */
	2
	3	#include "cpu/m68000/m68000.h"
	4
	5	class m68307cpu_device;
	6
	7
	8	/* ports */
	9	#define m68307SIM_PACNT (0x10)
	10	#define m68307SIM_PADDR (0x12)
	11	#define m68307SIM_PADAT (0x14)
	12	#define m68307SIM_PBCNT (0x16)
	13	#define m68307SIM_PBDDR (0x18)
	14	#define m68307SIM_PBDAT (0x1a)
	15
	16
	17	/* interrupt logic */
	18	#define m68307SIM_LICR1 (0x20)
	19	#define m68307SIM_LICR2 (0x22)
	20	#define m68307SIM_PICR  (0x24)
	21	#define m68307SIM_PIVR  (0x26)
	22
	23	/* used for the CS logic */
	24	#define m68307SIM_BR0 (0x40)
	25	#define m68307SIM_OR0 (0x42)
	26	#define m68307SIM_BR1 (0x44)
	27	#define m68307SIM_OR1 (0x46)
	28	#define m68307SIM_BR2 (0x48)
	29	#define m68307SIM_OR2 (0x4a)
	30	#define m68307SIM_BR3 (0x4c)
	31	#define m68307SIM_OR3 (0x4e)
	32
	33	class m68307_sim
	34	{
	35	public:
	36
	37	UINT16 m_pacnt; // 8-bit
	38	UINT16 m_paddr; // 8-bit
	39	UINT16 m_padat; // 8-bit
	40
	41	UINT16 m_pbcnt;
	42	UINT16 m_pbddr;
	43	UINT16 m_pbdat;
	44
	45	UINT16 m_pivr; // 8-bit
	46
	47	UINT16 m_br[4];
	48	UINT16 m_or[4];
	49	UINT16 m_picr;
	50	UINT16 m_licr1;
	51	UINT16 m_licr2;
	52
	53
	54	void write_pacnt(UINT16 data, UINT16 mem_mask);
	55	void write_paddr(UINT16 data, UINT16 mem_mask);
	56	UINT16 read_padat(m68307cpu_device* m68k, address_space &space, UINT16 mem_mask);
	57	void write_padat(m68307cpu_device* m68k, address_space &space, UINT16 data, UINT16 mem_mask);
	58
	59	void write_pbcnt(UINT16 data, UINT16 mem_mask);
	60	void write_pbddr(UINT16 data, UINT16 mem_mask);
	61	UINT16 read_pbdat(m68307cpu_device* m68k, address_space &space, UINT16 mem_mask);
	62	void write_pbdat(m68307cpu_device* m68k, address_space &space, UINT16 data, UINT16 mem_mask);
	63
	64
	65
	66	void write_licr1(UINT16 data, UINT16 mem_mask);
	67	void write_licr2(UINT16 data, UINT16 mem_mask);
	68	void write_picr(UINT16 data, UINT16 mem_mask);
	69	void write_pivr(UINT16 data, UINT16 mem_mask);
	70
	71	void reset(void);
	72	};

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trunk/src/emu/machine/68307tmu.c

r0	r24087
	1	/* 68307 TIMER module */
	2	// 2x timers
	3
	4	#include "emu.h"
	5	#include "68307.h"
	6
	7	READ16_MEMBER( m68307cpu_device::m68307_internal_timer_r )
	8	{
	9	m68307cpu_device *m68k = this;
	10	m68307_timer* timer = m68k->m68307TIMER;
	11	assert(timer != NULL);
	12
	13	if (timer)
	14	{
	15	int pc = space.device().safe_pc();
	16	int which = offset & 0x8;
	17
	18	switch (offset&0x7)
	19	{
	20	case m68307TIMER_TCN: /* 0x3 (0x126 / 0x136) */
	21	//if (pc!=0x2182e) logerror("%08x m68307_internal_timer_r %08x (%04x) (TCN - Timer Counter for timer %d)\n", pc, offset*2,mem_mask, which);
	22	return timer->read_tcn(mem_mask, which);
	23	break;
	24
	25
	26	default:
	27	logerror("%08x m68307_internal_timer_r %08x, (%04x)\n", pc, offset*2,mem_mask);
	28	break;
	29	}
	30	}
	31
	32	return 0x0000;
	33	}
	34
	35	WRITE16_MEMBER( m68307cpu_device::m68307_internal_timer_w )
	36	{
	37	m68307cpu_device *m68k = this;
	38	m68307_timer* timer = m68k->m68307TIMER;
	39	assert(timer != NULL);
	40
	41	if (timer)
	42	{
	43	int pc = space.device().safe_pc();
	44	int which = offset & 0x8;
	45
	46	switch (offset&0x7)
	47	{
	48	case m68307TIMER_TMR: /* 0x0 (0x120 / 0x130) */
	49	logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TMR - Timer Mode Register for timer %d)\n", pc, offset*2,data,mem_mask, which);
	50	timer->write_tmr(data, mem_mask, which);
	51	break;
	52
	53	case m68307TIMER_TRR: /* 0x1 (0x122 / 0x132) */
	54	logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TRR - Timer Reference Register for timer %d)\n", pc, offset*2,data,mem_mask, which);
	55	timer->write_trr(data, mem_mask, which);
	56	break;
	57
	58	case m68307TIMER_TCR: /* 0x2 (0x124 / 0x134) */
	59	logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TCR - Timer Capture Register for timer %d) (illegal, read-only)\n", pc, offset*2,data,mem_mask, which);
	60	break;
	61
	62	case m68307TIMER_TCN: /* 0x3 (0x126 / 0x136) */
	63	logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TCN - Timer Counter for timer %d)\n", pc, offset*2,data,mem_mask, which);
	64	break;
	65
	66	case m68307TIMER_TER: /* 0x4 (0x128 / 0x138) */
	67	/* 8-bit only!! */
	68	//logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TER - Timer Event Register for timer %d)\n", pc, offset*2,data,mem_mask, which);
	69	timer->write_ter(data, mem_mask, which);
	70	break;
	71
	72	case m68307TIMER_WRR: /* 0x5 (0x12a / 0x13a) */
	73	if (which==0)
	74	{
	75	logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (WRR - Watchdog Reference Register)\n", pc, offset*2,data,mem_mask);
	76	}
	77	else
	78	{
	79	logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", pc, offset*2,data,mem_mask);
	80	}
	81	break;
	82
	83	case m68307TIMER_WCR: /* 0x6 (0x12c / 0x13c) */
	84	if (which==0)
	85	{
	86	logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (WRR - Watchdog Counter Register)\n", pc, offset*2,data,mem_mask);
	87	}
	88	else
	89	{
	90	logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", pc, offset*2,data,mem_mask);
	91	}
	92	break;
	93
	94	case m68307TIMER_XXX: /* 0x7 (0x12e / 0x13e) */
	95	logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", pc, offset*2,data,mem_mask);
	96	break;
	97
	98	}
	99	}
	100	}
	101
	102	static TIMER_CALLBACK( m68307_timer0_callback )
	103	{
	104	m68307cpu_device* m68k = (m68307cpu_device *)ptr;
	105	m68307_single_timer* tptr = &m68k->m68307TIMER->singletimer[0];
	106	tptr->regs[m68307TIMER_TMR] |= 0x2;
	107
	108	m68307_timer0_interrupt(m68k);
	109
	110	tptr->mametimer->adjust(m68k->cycles_to_attotime(20000));
	111	}
	112
	113	static TIMER_CALLBACK( m68307_timer1_callback )
	114	{
	115	m68307cpu_device* m68k = (m68307cpu_device *)ptr;
	116	m68307_single_timer* tptr = &m68k->m68307TIMER->singletimer[1];
	117	tptr->regs[m68307TIMER_TMR] |= 0x2;
	118
	119	m68307_timer1_interrupt(m68k);
	120
	121	tptr->mametimer->adjust(m68k->cycles_to_attotime(20000));
	122
	123	}
	124
	125	static TIMER_CALLBACK( m68307_wd_timer_callback )
	126	{
	127	printf("wd timer\n");
	128	}
	129
	130	void m68307_timer::init(m68307cpu_device *device)
	131	{
	132	parent = device;
	133
	134	m68307_single_timer* tptr;
	135
	136	tptr = &singletimer[0];
	137	tptr->mametimer = device->machine().scheduler().timer_alloc(FUNC(m68307_timer0_callback), parent);
	138
	139	tptr = &singletimer[1];
	140	tptr->mametimer = device->machine().scheduler().timer_alloc(FUNC(m68307_timer1_callback), parent);
	141
	142
	143	wd_mametimer = device->machine().scheduler().timer_alloc(FUNC(m68307_wd_timer_callback), parent);
	144
	145
	146	}
	147
	148	UINT16 m68307_timer::read_tcn(UINT16 mem_mask, int which)
	149	{
	150	// we should return the current timer value by
	151	// calculating what it should be based on the time
	152	// since it was last set
	153	return 0x3a98;
	154	}
	155
	156	void m68307_timer::write_ter(UINT16 data, UINT16 mem_mask, int which)
	157	{
	158	m68307_single_timer* tptr = &singletimer[which];
	159	if (data & 0x2) tptr->regs[m68307TIMER_TMR] &= ~0x2;
	160	}
	161
	162	void m68307_timer::write_tmr(UINT16 data, UINT16 mem_mask, int which)
	163	{
	164	m68307cpu_device* m68k = parent;
	165	m68307_single_timer* tptr = &singletimer[which];
	166
	167	COMBINE_DATA(&tptr->regs[m68307TIMER_TMR]);
	168
	169	data = tptr->regs[m68307TIMER_TMR];
	170
	171	int ps   = data & (0xff00)>>8;
	172	int ce   = data & (0x00c0)>>6;
	173	int om   = data & (0x0020)>>5;
	174	int ori  = data & (0x0010)>>4;
	175	int frr  = data & (0x0008)>>3;
	176	int iclk = data & (0x0006)>>1;
	177	int rst  = data & (0x0001)>>0;
	178
	179
	180	logerror("tmr value %04x : Details :\n", data);
	181	logerror("prescale %d\n", ps);
	182	logerror("(clock divided by %d)\n", ps+1);
	183	logerror("capture edge / enable interrupt %d\n", ce);
	184	if (ce==0x0) logerror("(disable interrupt on capture event)\n");
	185	if (ce==0x1) logerror("(capture on rising edge only + enable capture interrupt)\n");
	186	if (ce==0x2) logerror("(capture on falling edge only + enable capture interrupt)\n");
	187	if (ce==0x3) logerror("(capture on any edge + enable capture interrupt)\n");
	188	logerror("output mode %d\n", om);
	189	if (om==0x0) logerror("(active-low pulse for one cycle))\n");
	190	if (om==0x1) logerror("(toggle output)\n");
	191	logerror("output reference interrupt %d\n", ori);
	192	if (ori==0x0) logerror("(disable reference interrupt)\n");
	193	if (ori==0x1) logerror("(enable interrupt on reaching reference value))\n");
	194	logerror("free running %d\n", frr);
	195	if (frr==0x0) logerror("(free running mode, counter continues after value reached)\n");
	196	if (frr==0x1) logerror("(restart mode, counter resets after value reached)\n");
	197	logerror("interrupt clock source %d\n", iclk);
	198	if (iclk==0x0) logerror("(stop count)\n");
	199	if (iclk==0x1) logerror("(master system clock)\n");
	200	if (iclk==0x2) logerror("(master system clock divided by 16)\n");
	201	if (iclk==0x3) logerror("(TIN Pin)\n");
	202	logerror("reset %d\n", rst);
	203	if (rst==0x0) logerror("(timer is reset)\n");
	204	if (rst==0x1) logerror("(timer is running)\n");
	205
	206	tptr->mametimer->adjust(m68k->cycles_to_attotime(100000));
	207
	208	logerror("\n");
	209
	210	}
	211
	212	void m68307_timer::write_trr(UINT16 data, UINT16 mem_mask, int which)
	213	{
	214	m68307_single_timer* tptr = &singletimer[which];
	215
	216	COMBINE_DATA(&tptr->regs[m68307TIMER_TRR]);
	217	}
	218
	219
	220
	221	void m68307_timer::reset(void)
	222	{
	223	for (int i=0;i<2;i++)
	224	{
	225	m68307_single_timer* tptr = &singletimer[i];
	226
	227	tptr->regs[m68307TIMER_TMR] = 0x0000;
	228	tptr->regs[m68307TIMER_TRR] = 0xffff;
	229	tptr->regs[m68307TIMER_TCR] = 0x0000;
	230	tptr->regs[m68307TIMER_TCN] = 0x0000;
	231	tptr->regs[m68307TIMER_TER] = 0x0000;
	232	tptr->regs[m68307TIMER_WRR] = 0xffff;
	233	tptr->regs[m68307TIMER_WCR] = 0xffff;
	234	tptr->regs[m68307TIMER_XXX] = 0;
	235	tptr->enabled = false;
	236	tptr->mametimer->adjust(attotime::never);
	237	}
	238
	239	wd_mametimer->adjust(attotime::never);
	240
	241
	242	}

Property changes on: trunk/src/emu/machine/68307tmu.c

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trunk/src/emu/machine/68307tmu.h

r0	r24087
	1
	2	#include "cpu/m68000/m68000.h"
	3
	4	class m68307cpu_device;
	5
	6
	7	#define m68307TIMER_TMR (0x0)
	8	#define m68307TIMER_TRR (0x1)
	9	#define m68307TIMER_TCR (0x2)
	10	#define m68307TIMER_TCN (0x3)
	11	#define m68307TIMER_TER (0x4)
	12	#define m68307TIMER_WRR (0x5)
	13	#define m68307TIMER_WCR (0x6)
	14	#define m68307TIMER_XXX (0x7)
	15
	16	struct m68307_single_timer
	17	{
	18	UINT16 regs[0x8];
	19	bool enabled;
	20	emu_timer *mametimer;
	21	};
	22
	23
	24	class m68307_timer
	25	{
	26	public:
	27	m68307_single_timer singletimer[2];
	28
	29	emu_timer *wd_mametimer;
	30	m68307cpu_device *parent;
	31
	32	void write_tmr(UINT16 data, UINT16 mem_mask, int which);
	33	void write_trr(UINT16 data, UINT16 mem_mask, int which);
	34	void write_ter(UINT16 data, UINT16 mem_mask, int which);
	35	UINT16 read_tcn(UINT16 mem_mask, int which);
	36
	37	void init(m68307cpu_device *device);
	38	void reset(void);
	39	};

Property changes on: trunk/src/emu/machine/68307tmu.h

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trunk/src/emu/machine/machine.mak

r24086	r24087
805	805
806	806	#-------------------------------------------------
807	807	#
	808	#@src/emu/machine/68307.h,MACHINES += M68307
	809	#-------------------------------------------------
	810
	811	ifneq ($(filter M68307,$(MACHINES)),)
	812	MACHINEOBJS += $(MACHINEOBJ)/68307.o
	813	MACHINEOBJS += $(MACHINEOBJ)/68307sim.o
	814	MACHINEOBJS += $(MACHINEOBJ)/68307bus.o
	815	MACHINEOBJS += $(MACHINEOBJ)/68307ser.o
	816	MACHINEOBJS += $(MACHINEOBJ)/68307tmu.o
	817	endif
	818
	819	#-------------------------------------------------
	820	#
808	821	#@src/emu/machine/mcf5206e.h,MACHINES += MCF5206E
809	822	#-------------------------------------------------
810	823

trunk/src/emu/machine/68307.c

r0	r24087
	1	/* 68307 */
	2
	3	#include "68307.h"
	4
	5	static ADDRESS_MAP_START( m68307_internal_map, AS_PROGRAM, 16, m68307cpu_device )
	6	AM_RANGE(0x000000f0, 0x000000ff) AM_READWRITE(m68307_internal_base_r, m68307_internal_base_w)
	7	ADDRESS_MAP_END
	8
	9
	10	m68307cpu_device::m68307cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	11	: m68000_device(mconfig, "MC68307", tag, owner, clock, M68307, 16,24, ADDRESS_MAP_NAME(m68307_internal_map), "mc68307", __FILE__)
	12	{
	13	m68307SIM = 0;
	14	m68307MBUS = 0;
	15	m68307SERIAL = 0;
	16	m68307TIMER = 0;
	17	m68307_base = 0;
	18	m68307_scrhigh = 0;
	19	m68307_scrlow = 0;
	20	m68307_currentcs = 0;
	21
	22	m_m68307_porta_r = 0;
	23	m_m68307_porta_w = 0;
	24	m_m68307_portb_r = 0;
	25	m_m68307_portb_w = 0;
	26	}
	27
	28
	29
	30
	31
	32
	33	void m68307cpu_device::device_reset()
	34	{
	35	m68000_device::device_reset();
	36
	37	if (m68307SIM) m68307SIM->reset();
	38	if (m68307MBUS) m68307MBUS->reset();
	39	if (m68307SERIAL) m68307SERIAL->reset();
	40	if (m68307TIMER) m68307TIMER->reset();
	41
	42	m68307_base = 0xbfff;
	43	m68307_scrhigh = 0x0007;
	44	m68307_scrlow = 0xf010;
	45
	46	}
	47
	48
	49	/* todo: is it possible to calculate the address map based on CS when they change
	50	and install handlers?  Going through this logic for every memory access is
	51	very slow */
	52
	53	int m68307_calc_cs(m68307cpu_device *m68k, offs_t address)
	54	{
	55	m68307_sim* sim = m68k->m68307SIM;
	56
	57	for (int i=0;i<4;i++)
	58	{
	59	int br,amask,bra;
	60	br = sim->m_br[i] & 1;
	61	amask = ((sim->m_or[i]&0x1ffc)<<11);
	62	bra = ((sim->m_br[i] & 0x1ffc)<<11);
	63	if ((br) && ((address & amask) == bra)) return i+1;
	64	}
	65	return 0;
	66	}
	67
	68
	69
	70	UINT16 m68307cpu_device::simple_read_immediate_16_m68307(offs_t address)
	71	{
	72	//  m68307_currentcs = m68307_calc_cs(this, address);
	73	return m_direct->read_decrypted_word(address);
	74	}
	75
	76	UINT8 m68307cpu_device::read_byte_m68307(offs_t address)
	77	{
	78	//  m68307_currentcs = m68307_calc_cs(this, address);
	79	return m_space->read_byte(address);
	80	}
	81
	82	UINT16 m68307cpu_device::read_word_m68307(offs_t address)
	83	{
	84	//  m68307_currentcs = m68307_calc_cs(this, address);
	85	return m_space->read_word(address);
	86	}
	87
	88	UINT32 m68307cpu_device::read_dword_m68307(offs_t address)
	89	{
	90	//  m68307_currentcs = m68307_calc_cs(this, address);
	91	return m_space->read_dword(address);
	92	}
	93
	94	void m68307cpu_device::write_byte_m68307(offs_t address, UINT8 data)
	95	{
	96	//  m68307_currentcs = m68307_calc_cs(this, address);
	97	m_space->write_byte(address, data);
	98	}
	99
	100	void m68307cpu_device::write_word_m68307(offs_t address, UINT16 data)
	101	{
	102	//  m68307_currentcs = m68307_calc_cs(this, address);
	103	m_space->write_word(address, data);
	104	}
	105
	106	void m68307cpu_device::write_dword_m68307(offs_t address, UINT32 data)
	107	{
	108	//  m68307_currentcs = m68307_calc_cs(this, address);
	109	m_space->write_dword(address, data);
	110	}
	111
	112
	113
	114
	115	void m68307cpu_device::init16_m68307(address_space &space)
	116	{
	117	m_space = &space;
	118	m_direct = &space.direct();
	119	opcode_xor = 0;
	120
	121	readimm16 = m68k_readimm16_delegate(FUNC(m68307cpu_device::simple_read_immediate_16_m68307), this);
	122	read8 = m68k_read8_delegate(FUNC(m68307cpu_device::read_byte_m68307), this);
	123	read16 = m68k_read16_delegate(FUNC(m68307cpu_device::read_word_m68307), this);
	124	read32 = m68k_read32_delegate(FUNC(m68307cpu_device::read_dword_m68307), this);
	125	write8 = m68k_write8_delegate(FUNC(m68307cpu_device::write_byte_m68307), this);
	126	write16 = m68k_write16_delegate(FUNC(m68307cpu_device::write_word_m68307), this);
	127	write32 = m68k_write32_delegate(FUNC(m68307cpu_device::write_dword_m68307), this);
	128	}
	129
	130
	131
	132	void m68307_set_port_callbacks(m68307cpu_device *device, m68307_porta_read_callback porta_r, m68307_porta_write_callback porta_w, m68307_portb_read_callback portb_r, m68307_portb_write_callback portb_w)
	133	{
	134	device->m_m68307_porta_r = porta_r;
	135	device->m_m68307_porta_w = porta_w;
	136	device->m_m68307_portb_r = portb_r;
	137	device->m_m68307_portb_w = portb_w;
	138	}
	139
	140	void m68307_set_duart68681(m68307cpu_device* cpudev, device_t* duart68681)
	141	{
	142	if (cpudev->m68307SERIAL)
	143	cpudev->m68307SERIAL->m68307ser_set_duart68681(duart68681);
	144	}
	145
	146
	147
	148
	149	UINT16 m68307_get_cs(m68307cpu_device *device, offs_t address)
	150	{
	151	device->m68307_currentcs = m68307_calc_cs(device, address);
	152
	153	return device->m68307_currentcs;
	154	}
	155
	156
	157	/* 68307 specifics - MOVE */
	158
	159	void m68307_set_interrupt(device_t *device, int level, int vector)
	160	{
	161	device->execute().set_input_line_and_vector(level, HOLD_LINE, vector);
	162	}
	163
	164	void m68307_timer0_interrupt(m68307cpu_device *cpudev)
	165	{
	166	int prioritylevel = (cpudev->m68307SIM->m_picr & 0x7000)>>12;
	167	int vector        = (cpudev->m68307SIM->m_pivr & 0x00f0) | 0xa;
	168	m68307_set_interrupt(cpudev, prioritylevel, vector);
	169	}
	170
	171	void m68307_timer1_interrupt(m68307cpu_device *cpudev)
	172	{
	173	int prioritylevel = (cpudev->m68307SIM->m_picr & 0x0700)>>8;
	174	int vector        = (cpudev->m68307SIM->m_pivr & 0x00f0) | 0xb;
	175	m68307_set_interrupt(cpudev, prioritylevel, vector);
	176	}
	177
	178	void m68307_serial_interrupt(m68307cpu_device *cpudev, int vector)
	179	{
	180	int prioritylevel = (cpudev->m68307SIM->m_picr & 0x0070)>>4;
	181	m68307_set_interrupt(cpudev, prioritylevel, vector);
	182	}
	183
	184	void m68307_mbus_interrupt(m68307cpu_device *cpudev)
	185	{
	186	int prioritylevel = (cpudev->m68307SIM->m_picr & 0x0007)>>0;
	187	int vector        = (cpudev->m68307SIM->m_pivr & 0x00f0) | 0xd;
	188	m68307_set_interrupt(cpudev, prioritylevel, vector);
	189	}
	190
	191	void m68307_licr2_interrupt(m68307cpu_device *cpudev)
	192	{
	193	int prioritylevel = (cpudev->m68307SIM->m_licr2 & 0x0007)>>0;
	194	int vector        = (cpudev->m68307SIM->m_pivr & 0x00f0) | 0x9;
	195	cpudev->m68307SIM->m_licr2 |= 0x8;
	196
	197
	198	m68307_set_interrupt(cpudev, prioritylevel, vector);
	199	}
	200
	201	void m68307cpu_device::device_start()
	202	{
	203	init_cpu_m68000();
	204
	205	/* basic CS logic, timers, mbus, serial logic
	206	set via remappable register
	207	*/
	208
	209	init16_m68307(*program);
	210
	211	m68307SIM    = new m68307_sim();
	212	m68307MBUS   = new m68307_mbus();
	213	m68307SERIAL = new m68307_serial();
	214	m68307TIMER  = new m68307_timer();
	215
	216	m68307TIMER->init(this);
	217
	218	m68307SIM->reset();
	219	m68307MBUS->reset();
	220	m68307SERIAL->reset();
	221	m68307TIMER->reset();
	222
	223	internal = &this->space(AS_PROGRAM);
	224	m68307_base = 0xbfff;
	225	m68307_scrhigh = 0x0007;
	226	m68307_scrlow = 0xf010;
	227
	228	m68307_set_port_callbacks(this, 0,0,0,0);
	229	}
	230
	231
	232
	233	READ16_MEMBER( m68307cpu_device::m68307_internal_base_r )
	234	{
	235	m68307cpu_device *m68k = this;
	236
	237	int pc = space.device().safe_pc();
	238	logerror("%08x m68307_internal_base_r %08x, (%04x)\n", pc, offset*2,mem_mask);
	239
	240	switch (offset<<1)
	241	{
	242	case 0x2: return m68k->m68307_base;
	243	case 0x4: return m68k->m68307_scrhigh;
	244	case 0x6: return m68k->m68307_scrlow;
	245	}
	246
	247	logerror("(read was illegal?)\n");
	248
	249	return 0x0000;
	250	}
	251
	252	WRITE16_MEMBER( m68307cpu_device::m68307_internal_base_w )
	253	{
	254	m68307cpu_device *m68k = this;
	255
	256	int pc = space.device().safe_pc();
	257	logerror("%08x m68307_internal_base_w %08x, %04x (%04x)\n", pc, offset*2,data,mem_mask);
	258	int base = 0;
	259	//int mask = 0;
	260
	261	switch (offset<<1)
	262	{
	263	case 0x2:
	264	/* remove old internal handler */
	265	base = (m68k->m68307_base & 0x0fff) << 12;
	266	//mask = (m68k->m68307_base & 0xe000) >> 13;
	267	//if ( m68k->m68307_base & 0x1000 ) mask |= 7;
	268	m68k->internal->unmap_readwrite(base+0x000, base+0x04f);
	269	m68k->internal->unmap_readwrite(base+0x100, base+0x11f);
	270	m68k->internal->unmap_readwrite(base+0x120, base+0x13f);
	271	m68k->internal->unmap_readwrite(base+0x140, base+0x149);
	272
	273	/* store new base address */
	274	COMBINE_DATA(&m68k->m68307_base);
	275
	276	/* install new internal handler */
	277	base = (m68k->m68307_base & 0x0fff) << 12;
	278	//mask = (m68k->m68307_base & 0xe000) >> 13;
	279	//if ( m68k->m68307_base & 0x1000 ) mask |= 7;
	280	m68k->internal->install_readwrite_handler(base + 0x000, base + 0x04f, read16_delegate(FUNC(m68307cpu_device::m68307_internal_sim_r),this),    write16_delegate(FUNC(m68307cpu_device::m68307_internal_sim_w),this));
	281	m68k->internal->install_readwrite_handler(base + 0x100, base + 0x11f, read8_delegate(FUNC(m68307cpu_device::m68307_internal_serial_r),this), write8_delegate(FUNC(m68307cpu_device::m68307_internal_serial_w),this), 0xffff);
	282	m68k->internal->install_readwrite_handler(base + 0x120, base + 0x13f, read16_delegate(FUNC(m68307cpu_device::m68307_internal_timer_r),this),  write16_delegate(FUNC(m68307cpu_device::m68307_internal_timer_w),this));
	283	m68k->internal->install_readwrite_handler(base + 0x140, base + 0x149, read8_delegate(FUNC(m68307cpu_device::m68307_internal_mbus_r),this),   write8_delegate(FUNC(m68307cpu_device::m68307_internal_mbus_w),this), 0xffff);
	284
	285
	286	break;
	287
	288	case 0x4:
	289	COMBINE_DATA(&m68k->m68307_scrhigh);
	290	break;
	291
	292	case 0x6:
	293	COMBINE_DATA(&m68k->m68307_scrlow);
	294	break;
	295
	296	default:
	297	logerror("(write was illegal?)\n");
	298	break;
	299	}
	300	}

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trunk/src/emu/machine/68307.h

r0	r24087
	1	/* 68307 */
	2
	3
	4	#pragma once
	5	#ifndef __M68307_H__
	6	#define __M68307_H__
	7
	8	#include "emu.h"
	9	#include "cpu/m68000/m68000.h"
	10
	11	#include "68307sim.h"
	12	#include "68307bus.h"
	13	#include "68307ser.h"
	14	#include "68307tmu.h"
	15
	16
	17
	18
	19	typedef UINT8 (*m68307_porta_read_callback)(address_space &space, bool dedicated, UINT8 line_mask);
	20	typedef void (*m68307_porta_write_callback)(address_space &space, bool dedicated, UINT8 data, UINT8 line_mask);
	21	typedef UINT16 (*m68307_portb_read_callback)(address_space &space, bool dedicated, UINT16 line_mask);
	22	typedef void (*m68307_portb_write_callback)(address_space &space, bool dedicated, UINT16 data, UINT16 line_mask);
	23
	24
	25
	26	class m68307cpu_device : public m68000_device {
	27	public:
	28	m68307cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	29
	30
	31	UINT16 simple_read_immediate_16_m68307(offs_t address);
	32
	33
	34	UINT8 read_byte_m68307(offs_t address);
	35	UINT16 read_word_m68307(offs_t address);
	36	UINT32 read_dword_m68307(offs_t address);
	37	void write_byte_m68307(offs_t address, UINT8 data);
	38	void write_word_m68307(offs_t address, UINT16 data);
	39	void write_dword_m68307(offs_t address, UINT32 data);
	40
	41
	42	/* 68307 peripheral modules */
	43	m68307_sim*    m68307SIM;
	44	m68307_mbus*   m68307MBUS;
	45	m68307_serial* m68307SERIAL;
	46	m68307_timer*  m68307TIMER;
	47
	48	UINT16 m68307_base;
	49	UINT16 m68307_scrhigh;
	50	UINT16 m68307_scrlow;
	51
	52	int m68307_currentcs;
	53
	54
	55	DECLARE_READ16_MEMBER( m68307_internal_base_r );
	56	DECLARE_WRITE16_MEMBER( m68307_internal_base_w );
	57	DECLARE_READ16_MEMBER( m68307_internal_timer_r );
	58	DECLARE_WRITE16_MEMBER( m68307_internal_timer_w );
	59	DECLARE_READ16_MEMBER( m68307_internal_sim_r );
	60	DECLARE_WRITE16_MEMBER( m68307_internal_sim_w );
	61	DECLARE_READ8_MEMBER( m68307_internal_serial_r );
	62	DECLARE_WRITE8_MEMBER( m68307_internal_serial_w );
	63	DECLARE_READ8_MEMBER( m68307_internal_mbus_r );
	64	DECLARE_WRITE8_MEMBER( m68307_internal_mbus_w );
	65
	66
	67	/* callbacks for internal ports */
	68	m68307_porta_read_callback m_m68307_porta_r;
	69	m68307_porta_write_callback m_m68307_porta_w;
	70	m68307_portb_read_callback m_m68307_portb_r;
	71	m68307_portb_write_callback m_m68307_portb_w;
	72
	73	void init16_m68307(address_space &space);
	74	void init_cpu_m68307(void);
	75
	76	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	77	virtual UINT32 disasm_max_opcode_bytes() const { return 10; };
	78
	79	virtual UINT32 execute_min_cycles() const { return 4; };
	80	virtual UINT32 execute_max_cycles() const { return 158; };
	81	protected:
	82
	83	virtual void device_start();
	84	virtual void device_reset();
	85
	86	};
	87
	88	static const device_type M68307 = &device_creator<m68307cpu_device>;
	89
	90	extern void m68307_set_port_callbacks(m68307cpu_device *device, m68307_porta_read_callback porta_r, m68307_porta_write_callback porta_w, m68307_portb_read_callback portb_r, m68307_portb_write_callback portb_w);
	91	extern void m68307_set_duart68681(m68307cpu_device* cpudev, device_t* duart68681);
	92	extern UINT16 m68307_get_cs(m68307cpu_device *device, offs_t address);
	93	extern void m68307_timer0_interrupt(m68307cpu_device *cpudev);
	94	extern void m68307_timer1_interrupt(m68307cpu_device *cpudev);
	95	extern void m68307_serial_interrupt(m68307cpu_device *cpudev, int vector);
	96	extern void m68307_mbus_interrupt(m68307cpu_device *cpudev);
	97	extern void m68307_licr2_interrupt(m68307cpu_device *cpudev);
	98
	99	#endif
		No newline at end of file

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trunk/src/emu/machine/68307bus.c

r0	r24087
	1	/* 68307 MBUS module */
	2	/* all ports on this are 8-bit? */
	3
	4	#include "emu.h"
	5	#include "68307.h"
	6
	7
	8	READ8_MEMBER( m68307cpu_device::m68307_internal_mbus_r )
	9	{
	10	m68307cpu_device *m68k = this;
	11	m68307_mbus* mbus = m68k->m68307MBUS;
	12	assert(mbus != NULL);
	13	UINT8 retval;
	14
	15	if (mbus)
	16	{
	17	int pc = space.device().safe_pc();
	18
	19
	20	switch (offset)
	21	{
	22	case m68307BUS_MADR:
	23	logerror("%08x m68307_internal_mbus_r %08x (MADR - M-Bus Address Register)\n", pc, offset);
	24	return space.machine().rand();
	25
	26	case m68307BUS_MFDR:
	27	logerror("%08x m68307_internal_mbus_r %08x (MFDR - M-Bus Frequency Divider Register)\n", pc, offset);
	28	return space.machine().rand();
	29
	30	case m68307BUS_MBCR:
	31	logerror("%08x m68307_internal_mbus_r %08x (MFCR - M-Bus Control Register)\n", pc, offset);
	32	return mbus->m_MFCR;//space.machine().rand();
	33
	34	case m68307BUS_MBSR:
	35	logerror("%08x m68307_internal_mbus_r %08x (MBSR - M-Bus Status Register)\n", pc, offset);
	36	retval = 0;
	37	if (mbus->m_busy) retval |= 0x20;
	38	if (mbus->m_intpend) retval |= 0x02;
	39
	40	return retval;
	41
	42	case m68307BUS_MBDR:
	43	logerror("%08x m68307_internal_mbus_r %08x (MBDR - M-Bus Data I/O Register)\n", pc, offset);
	44	mbus->m_intpend = true;
	45	return 0xff;//space.machine().rand();
	46
	47	default:
	48	logerror("%08x m68307_internal_mbus_r %08x (UNKNOWN / ILLEGAL)\n", pc, offset);
	49	return 0x00;
	50	}
	51	}
	52
	53	return 0xff;
	54	}
	55
	56	WRITE8_MEMBER( m68307cpu_device::m68307_internal_mbus_w )
	57	{
	58	m68307cpu_device *m68k = this;
	59	m68307_mbus* mbus = m68k->m68307MBUS;
	60	assert(mbus != NULL);
	61
	62	if (mbus)
	63	{
	64	int pc = space.device().safe_pc();
	65
	66	switch (offset)
	67	{
	68	case m68307BUS_MADR:
	69	logerror("%08x m68307_internal_mbus_w %08x, %02x (MADR - M-Bus Address Register)\n", pc, offset,data);
	70	break;
	71
	72	case m68307BUS_MFDR:
	73	logerror("%08x m68307_internal_mbus_w %08x, %02x (MFDR - M-Bus Frequency Divider Register)\n", pc, offset,data);
	74	break;
	75
	76	case m68307BUS_MBCR:
	77	logerror("%08x m68307_internal_mbus_w %08x, %02x (MFCR - M-Bus Control Register)\n", pc, offset,data);
	78
	79	mbus->m_MFCR = data;
	80	if (data & 0x80)
	81	{
	82	mbus->m_busy = false;
	83	mbus->m_intpend = false;
	84	}
	85	if (data & 0x20) mbus->m_busy = true;
	86
	87	break;
	88
	89	case m68307BUS_MBSR:
	90	logerror("%08x m68307_internal_mbus_w %08x, %02x (MBSR - M-Bus Status Register)\n", pc, offset,data);
	91	break;
	92
	93	case m68307BUS_MBDR:
	94	logerror("%08x m68307_internal_mbus_w %08x, %02x (MBDR - M-Bus Data I/O Register)\n", pc, offset,data);
	95
	96	mbus->m_intpend = true;
	97
	98	break;
	99
	100	default:
	101	logerror("%08x m68307_internal_mbus_w %08x, %02x (UNKNOWN / ILLEGAL)\n", pc, offset,data);
	102	break;
	103	}
	104	}
	105	}
	106
	107	void m68307_mbus::reset(void)
	108	{
	109	m_busy = false;
	110	}

Property changes on: trunk/src/emu/machine/68307bus.c

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trunk/src/emu/machine/68307bus.h

r0	r24087
	1	#include "cpu/m68000/m68000.h"
	2
	3	#define m68307BUS_MADR (0x01)
	4	#define m68307BUS_MFDR (0x03)
	5	#define m68307BUS_MBCR (0x05)
	6	#define m68307BUS_MBSR (0x07)
	7	#define m68307BUS_MBDR (0x09)
	8
	9
	10	class m68307_mbus
	11	{
	12	public:
	13
	14	UINT16 m_MFCR;
	15
	16	bool m_busy;
	17	bool m_intpend;
	18
	19	void reset(void);
	20	};

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trunk/src/emu/machine/68307ser.c

r0	r24087
	1	/* 68307 SERIAL Module */
	2	/* all ports on this are 8-bit? */
	3
	4	/* this is a 68681 'compatible' chip but with only a single channel implemented
	5	(writes to the other channel have no effects)
	6
	7	for now at least we piggyback on the existing 68307 emulation rather than having
	8	a custom verson here, that may change later if subtle differences exist.
	9
	10	*/
	11
	12	#include "emu.h"
	13	#include "68307.h"
	14
	15
	16	READ8_MEMBER( m68307cpu_device::m68307_internal_serial_r )
	17	{
	18	m68307cpu_device *m68k = this;
	19	m68307_serial* serial = m68k->m68307SERIAL;
	20	assert(serial != NULL);
	21
	22	if (serial)
	23	{
	24	// if we're piggybacking on the existing 68681 implementation...
	25	if (serial->m_duart68681)
	26	{
	27	if (offset&1) return duart68681_r(serial->m_duart68681, *m68k->program, offset>>1);
	28	}
	29	else
	30	{
	31	int pc = space.device().safe_pc();
	32
	33	switch (offset)
	34	{
	35	case m68307SER_UMR1_UMR2:
	36	logerror("%08x m68307_internal_serial_r %08x (UMR1, UMR2 - UART Mode Register)\n", pc, offset);
	37	return space.machine().rand();
	38
	39	case m68307SER_USR_UCSR:
	40	logerror("%08x m68307_internal_serial_r %08x (USR, UCSR - UART Status/Clock Select Register)\n", pc, offset);
	41	return space.machine().rand();
	42
	43	case m68307SER_UCR:
	44	logerror("%08x m68307_internal_serial_r %08x (UCR - UART Command Register)\n", pc, offset);
	45	return space.machine().rand();
	46
	47	case m68307SER_URB_UTB:
	48	logerror("%08x m68307_internal_serial_r %08x (URB, UTB - UART Recieve/Transmit Buffer)\n", pc, offset);
	49	return 0xff;//space.machine().rand();
	50
	51	case m68307SER_UIPCR_UACR:
	52	logerror("%08x m68307_internal_serial_r %08x (UIPCR, UACR - UART Input Port Change Register / UART Control Register)\n", pc, offset);
	53	return 0xff;//space.machine().rand();
	54
	55	case m68307SER_UISR_UIMR:
	56	logerror("%08x m68307_internal_serial_r %08x (UISR, UIMR - UART Interrupt Status Register / UART Interrupt Mask Register)\n", pc, offset);
	57	return space.machine().rand() & 0x87;
	58
	59	case m68307SER_UBG1:
	60	logerror("%08x m68307_internal_serial_r %08x (UBG1 - UART Baud Rate Gen. Precaler MSB)\n", pc, offset);
	61	return space.machine().rand() & 0x87;
	62
	63	case m68307SER_UBG2:
	64	logerror("%08x m68307_internal_serial_r %08x (UBG1 - UART Baud Rate Gen. Precaler LSB)\n", pc, offset);
	65	return space.machine().rand() & 0x87;
	66
	67	case m68307SER_UIVR:
	68	logerror("%08x m68307_internal_serial_r %08x (UIVR - UART Interrupt Vector Register)\n", pc, offset);
	69	return space.machine().rand() & 0x87;
	70
	71	case m68307SER_UIP:
	72	logerror("%08x m68307_internal_serial_r %08x (UIP - UART Register Input Port)\n", pc, offset);
	73	return space.machine().rand() & 0x87;
	74
	75	case m68307SER_UOP1:
	76	logerror("%08x m68307_internal_serial_r %08x (UOP1 - UART Output Port Bit Set Cmd)\n", pc, offset);
	77	return space.machine().rand() & 0x87;
	78
	79	case m68307SER_UOP0:
	80	logerror("%08x m68307_internal_serial_r %08x (UOP0 - UART Output Port Bit Reset Cmd)\n", pc, offset);
	81	return space.machine().rand() & 0x87;
	82
	83	default:
	84	logerror("%08x m68307_internal_serial_r %08x (UNKNOWN / ILLEGAL)\n", pc, offset);
	85	break;
	86	}
	87	}
	88	}
	89
	90	return 0x0000;
	91	}
	92
	93	WRITE8_MEMBER( m68307cpu_device::m68307_internal_serial_w )
	94	{
	95	m68307cpu_device *m68k = this;
	96	m68307_serial* serial = m68k->m68307SERIAL;
	97	assert(serial != NULL);
	98
	99	int pc = space.device().safe_pc();
	100
	101	if (serial)
	102	{
	103	// if we're piggybacking on the existing 68681 implementation...
	104	if (serial->m_duart68681)
	105	{
	106	if (offset&1) duart68681_w(serial->m_duart68681, *m68k->program, offset>>1, data);
	107	}
	108	else
	109	{
	110	switch (offset)
	111	{
	112	case m68307SER_UMR1_UMR2:
	113	logerror("%08x m68307_internal_serial_w %08x, %02x (UMR1, UMR2 - UART Mode Register)\n", pc, offset,data);
	114	break;
	115
	116	case m68307SER_USR_UCSR:
	117	logerror("%08x m68307_internal_serial_w %08x, %02x (UCSR - Clock Select Register)\n", pc, offset,data);
	118	break;
	119
	120	case m68307SER_UCR:
	121	logerror("%08x m68307_internal_serial_w %08x, %02x (UCR - UART Command Register)\n", pc, offset,data);
	122	break;
	123
	124	case m68307SER_URB_UTB:
	125	logerror("%08x m68307_internal_serial_w %08x, %02x (UTB - Transmit Buffer)\n", pc, offset,data);
	126	break;
	127
	128	case m68307SER_UIPCR_UACR:
	129	logerror("%08x m68307_internal_serial_w %08x, %02x (UIPCR, UACR - UART Input Port Change Register / UART Control Register)\n", pc, offset,data);
	130	break;
	131
	132	case m68307SER_UISR_UIMR:
	133	logerror("%08x m68307_internal_serial_w %08x, %02x (UIMR - Interrupt Mask Register)\n", pc, offset,data);
	134	break;
	135
	136	case m68307SER_UBG1:
	137	logerror("%08x m68307_internal_serial_w %08x, %02x (UBG1 - UART Baud Rate Gen. Precaler MSB)\n", pc, offset,data);
	138	break;
	139
	140	case m68307SER_UBG2:
	141	logerror("%08x m68307_internal_serial_w %08x, %02x (UBG1 - UART Baud Rate Gen. Precaler LSB)\n", pc, offset,data);
	142	break;
	143
	144	case m68307SER_UIVR:
	145	logerror("%08x m68307_internal_serial_w %08x, %02x (UIVR - Interrupt Vector Register)\n", pc, offset,data);
	146	serial->m_uivr = data;
	147	break;
	148
	149	case m68307SER_UIP:
	150	logerror("%08x m68307_internal_serial_w %08x, %02x (UIP - UART Register Input Port)\n", pc, offset,data);
	151	break;
	152
	153	case m68307SER_UOP1:
	154	logerror("%08x m68307_internal_serial_w %08x, %02x (UOP1 - UART Output Port Bit Set Cmd)\n", pc, offset,data);
	155	break;
	156
	157	case m68307SER_UOP0:
	158	logerror("%08x m68307_internal_serial_w %08x, %02x (UOP0 - UART Output Port Bit Reset Cmd)\n", pc, offset,data);
	159	break;
	160
	161
	162	default:
	163	logerror("%08x m68307_internal_serial_w %08x, %02x (UNKNOWN / ILLEGAL)\n", pc, offset,data);
	164	break;
	165	}
	166	}
	167	}
	168	}
	169
	170	void m68307_serial::reset(void)
	171	{
	172	}

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