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r24088 Friday 5th July, 2013 at 14:32:16 UTC by David Haywood
also untangle the skeleton 68340.  where the code ends up is TBD. the actual core type of the 68340 is CPU32, so it is now derived from that.

[src/emu/cpu]	cpu.mak
[src/emu/cpu/m68000]	68340dma.c 68340dma.h 68340ser.c 68340ser.h 68340sim.c 68340sim.h 68340tmu.c 68340tmu.h m68000.h m68kcpu.c m68kcpu.h m68kdasm.c m68kmake.c
[src/emu/machine]	68340.c* 68340.h* 68340dma.c* 68340dma.h* 68340ser.c* 68340ser.h* 68340sim.c* 68340sim.h* 68340tmu.c* 68340tmu.h* machine.mak
[src/mame]	mame.mak
[src/mame/drivers]	astrafr.c bfm_sc4h.c bfm_swp.c cupidon.c mpu5hw.c pluto5.c
[src/mame/includes]	bfm_sc45.h

trunk/src/mame/drivers/bfm_swp.c

r24087	r24088
100	100
101	101
102	102	#include "emu.h"
103		#include "cpu/m68000/m68000.h"
	103	#include "machine/68340.h"
104	104	#include "sound/ymz280b.h"
105	105
106	106	class bfm_swp_state : public driver_device
r24087	r24088
127	127	protected:
128	128
129	129	// devices
130		required_device<m68000_base_device> m_maincpu;
	130	required_device<m68340cpu_device> m_maincpu;
131	131
132	132	virtual void machine_start();
133	133	};

trunk/src/mame/drivers/bfm_sc4h.c

r24087	r24088
34	34	#include "emu.h"
35	35	#include "cpu/m68000/m68000.h"
36	36	#include "machine/68307.h"
	37	#include "machine/68340.h"
37	38	#include "includes/bfm_sc45.h"
38	39	#include "bfm_sc4.lh"
39	40	#include "video/awpvid.h"

trunk/src/mame/drivers/astrafr.c

r24087	r24088
11	11	*/
12	12
13	13	#include "emu.h"
14		#include "cpu/m68000/m68000.h"
	14	#include "machine/68340.h"
15	15
16	16
17	17
r24087	r24088
113	113	}
114	114
115	115	// devices
116		required_device<m68000_base_device> m_maincpu;
117		optional_device<m68000_base_device> m_slavecpu;
	116	required_device<m68340cpu_device> m_maincpu;
	117	optional_device<m68340cpu_device> m_slavecpu;
118	118
119	119	DECLARE_DRIVER_INIT(astradec_sml);
120	120	DECLARE_DRIVER_INIT(astradec);

trunk/src/mame/drivers/cupidon.c

r24087	r24088
7	7
8	8
9	9	#include "emu.h"
10		#include "cpu/m68000/m68000.h"
	10	#include "machine/68340.h"
11	11
12	12	class cupidon_state : public driver_device
13	13	{
r24087	r24088
20	20	protected:
21	21
22	22	// devices
23		required_device<cpu_device> m_maincpu;
	23	required_device<m68340cpu_device> m_maincpu;
24	24	public:
25	25	DECLARE_DRIVER_INIT(cupidon);
26	26	};

trunk/src/mame/drivers/mpu5hw.c

r24087	r24088
39	39
40	40
41	41	#include "emu.h"
42		#include "cpu/m68000/m68000.h"
	42	#include "machine/68340.h"
43	43
44
45	44	class mpu5_state : public driver_device
46	45	{
47	46	public:
r24087	r24088
58	57	protected:
59	58
60	59	// devices
61		required_device<m68000_base_device> m_maincpu;
	60	required_device<m68340cpu_device> m_maincpu;
62	61	virtual void machine_start();
63	62	};
64	63

trunk/src/mame/drivers/pluto5.c

r24087	r24088
176	176	*/
177	177
178	178	#include "emu.h"
179		#include "cpu/m68000/m68000.h"
	179	#include "machine/68340.h"
180	180
181	181	class pluto5_state : public driver_device
182	182	{
r24087	r24088
195	195	protected:
196	196
197	197	// devices
198		required_device<m68000_base_device> m_maincpu;
	198	required_device<m68340cpu_device> m_maincpu;
199	199	public:
200	200	DECLARE_DRIVER_INIT(hb);
201	201	virtual void machine_start();

trunk/src/mame/mame.mak

r24087	r24088
409	409	MACHINES += MC68901
410	410	MACHINES += MCCS1850
411	411	MACHINES += M68307
	412	MACHINES += M68340
412	413	MACHINES += MCF5206E
413	414	MACHINES += MICROTOUCH
414	415	MACHINES += MM58274C

trunk/src/mame/includes/bfm_sc45.h

r24087	r24088
10	10	#include "machine/68681.h"
11	11	#include "machine/nvram.h"
12	12	#include "machine/68307.h"
	13	#include "machine/68340.h"
13	14
14	15	// common base class for things shared between sc4 and sc5
15	16	class bfm_sc45_state : public driver_device
r24087	r24088
549	550	DECLARE_MACHINE_START(adder4);
550	551
551	552	// devices
552		required_device<m68000_base_device> m_adder4cpu;
	553	required_device<m68340cpu_device> m_adder4cpu;
553	554	};
554	555
555	556

trunk/src/emu/cpu/m68000/68340tmu.h

r24087	r24088
1
2
3		class m68340_timer
4		{
5		public:
6		void reset(void);
7		};

trunk/src/emu/cpu/m68000/68340sim.c

r24087	r24088
1		/* 68340 SIM module */
2
3		#include "emu.h"
4		#include "m68kcpu.h"
5
6
7		READ16_MEMBER( m68000_base_device::m68340_internal_sim_r )
8		{
9		m68000_base_device *m68k = this;
10		m68340_sim* sim = m68k->m68340SIM;
11		assert(sim != NULL);
12
13		if (sim)
14		{
15		int pc = space.device().safe_pc();
16
17		switch (offset<<1)
18		{
19		case m68340SIM_MCR:
20		logerror("%08x m68340_internal_sim_r %04x, (%04x) (MCR - Module Configuration Register)\n", pc, offset*2,mem_mask);
21		return space.machine().rand();
22
23		case m68340SIM_SYNCR:
24		logerror("%08x m68340_internal_sim_r %04x, (%04x) (SYNCR - Clock Synthesizer Register)\n", pc, offset*2,mem_mask);
25		return space.machine().rand();
26
27		case m68340SIM_AVR_RSR:
28		logerror("%08x m68340_internal_sim_r %04x, (%04x) (AVR, RSR - Auto Vector Register, Reset Status Register)\n", pc, offset*2,mem_mask);
29		return space.machine().rand();
30
31		case m68340SIM_SWIV_SYPCR:
32		logerror("%08x m68340_internal_sim_r %04x, (%04x) (SWIV_SYPCR - Software Interrupt Vector, System Protection Control Register)\n", pc, offset*2,mem_mask);
33		return space.machine().rand();
34
35		case m68340SIM_PICR:
36		logerror("%08x m68340_internal_sim_r %04x, (%04x) (PICR - Periodic Interrupt Control Register)\n", pc, offset*2,mem_mask);
37		return space.machine().rand();
38
39		case m68340SIM_PITR:
40		logerror("%08x m68340_internal_sim_r %04x, (%04x) (PITR - Periodic Interrupt Timer Register)\n", pc, offset*2,mem_mask);
41		return space.machine().rand();
42
43		case m68340SIM_SWSR:
44		logerror("%08x m68340_internal_sim_r %04x, (%04x) (SWSR - Software Service)\n", pc, offset*2,mem_mask);
45		return space.machine().rand();
46
47		default:
48		logerror("%08x m68340_internal_sim_r %04x, (%04x)\n", pc, offset*2,mem_mask);
49
50
51		}
52		}
53
54		return 0x0000;
55		}
56
57		READ8_MEMBER( m68000_base_device::m68340_internal_sim_ports_r )
58		{
59		offset += 0x10;
60		m68000_base_device *m68k = this;
61		m68340_sim* sim = m68k->m68340SIM;
62		assert(sim != NULL);
63
64		if (sim)
65		{
66		int pc = space.device().safe_pc();
67
68		switch (offset)
69		{
70		case m68340SIM_PORTA:
71		logerror("%08x m68340_internal_sim_r %04x (PORTA - Port A Data)\n", pc, offset);
72		return space.machine().rand();
73
74		case m68340SIM_DDRA:
75		logerror("%08x m68340_internal_sim_r %04x (DDRA - Port A Data Direction)\n", pc, offset);
76		return space.machine().rand();
77
78		case m68340SIM_PPRA1:
79		logerror("%08x m68340_internal_sim_r %04x (PPRA1 - Port A Pin Assignment 1)\n", pc, offset);
80		return space.machine().rand();
81
82		case m68340SIM_PPRA2:
83		logerror("%08x m68340_internal_sim_r %04x (PPRA2 - Port A Pin Assignment 2)\n", pc, offset);
84		return space.machine().rand();
85
86		case m68340SIM_PORTB:
87		logerror("%08x m68340_internal_sim_r %04x (PORTB - Port B Data 0)\n", pc, offset);
88		return space.machine().rand();
89
90		case m68340SIM_PORTB1:
91		logerror("%08x m68340_internal_sim_r %04x (PORTB1 - Port B Data 1)\n", pc, offset);
92		return space.machine().rand();
93
94		case m68340SIM_DDRB:
95		logerror("%08x m68340_internal_sim_r %04x (DDR - Port B Data Direction)\n", pc, offset);
96		return space.machine().rand();
97
98		case m68340SIM_PPARB:
99		logerror("%08x m68340_internal_sim_r %04x (PPARB - Port B Pin Assignment)\n", pc, offset);
100		return space.machine().rand();
101
102		default:
103		logerror("%08x m68340_internal_sim_r %04x (ILLEGAL?)\n", pc, offset);
104		return space.machine().rand();
105
106		}
107		}
108
109		return 0x00;
110		}
111
112		READ32_MEMBER( m68000_base_device::m68340_internal_sim_cs_r )
113		{
114		offset += m68340SIM_AM_CS0>>2;
115
116		m68000_base_device *m68k = this;
117		m68340_sim* sim = m68k->m68340SIM;
118		assert(sim != NULL);
119
120		if (sim)
121		{
122		int pc = space.device().safe_pc();
123
124		switch (offset<<2)
125		{
126		case m68340SIM_AM_CS0:  return sim->m_am[0];
127		case m68340SIM_BA_CS0:  return sim->m_ba[0];
128		case m68340SIM_AM_CS1:  return sim->m_am[1];
129		case m68340SIM_BA_CS1:  return sim->m_ba[1];
130		case m68340SIM_AM_CS2:  return sim->m_am[2];
131		case m68340SIM_BA_CS2:  return sim->m_ba[2];
132		case m68340SIM_AM_CS3:  return sim->m_am[3];
133		case m68340SIM_BA_CS3:  return sim->m_ba[3];
134
135		default:
136		logerror("%08x m68340_internal_sim_r %08x, (%08x)\n", pc, offset*4,mem_mask);
137
138		}
139		}
140
141		return 0x00000000;
142		}
143
144		WRITE16_MEMBER( m68000_base_device::m68340_internal_sim_w )
145		{
146		m68000_base_device *m68k = this;
147		m68340_sim* sim = m68k->m68340SIM;
148		assert(sim != NULL);
149
150		if (sim)
151		{
152		int pc = space.device().safe_pc();
153
154		switch (offset<<1)
155		{
156		case m68340SIM_MCR:
157		logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (MCR - Module Configuration Register)\n", pc, offset*2,data,mem_mask);
158		break;
159
160		case m68340SIM_SYNCR:
161		logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (SYNCR - Clock Synthesizer Register)\n", pc, offset*2,data,mem_mask);
162		break;
163
164
165		case m68340SIM_AVR_RSR:
166		logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (AVR, RSR - Auto Vector Register, Reset Status Register)\n", pc, offset*2,data,mem_mask);
167		break;
168
169		case m68340SIM_SWIV_SYPCR:
170		logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (SWIV_SYPCR - Software Interrupt Vector, System Protection Control Register)\n", pc, offset*2,data,mem_mask);
171		break;
172
173		case m68340SIM_PICR:
174		logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (PICR - Periodic Interrupt Control Register)\n", pc, offset*2,data,mem_mask);
175		break;
176
177		case m68340SIM_PITR:
178		logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (PITR - Periodic Interrupt Timer Register)\n", pc, offset*2,data,mem_mask);
179		break;
180
181		case m68340SIM_SWSR:
182		// basically watchdog, you must write an alternating pattern of 0x55 / 0xaa to keep the watchdog from resetting the system
183		//logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (SWSR - Software Service)\n", pc, offset*2,data,mem_mask);
184		break;
185
186		default:
187		logerror("%08x m68340_internal_sim_w %04x, %04x (%04x)\n", pc, offset*2,data,mem_mask);
188
189		}
190		}
191		}
192
193		WRITE8_MEMBER( m68000_base_device::m68340_internal_sim_ports_w )
194		{
195		offset += 0x10;
196		m68000_base_device *m68k = this;
197		m68340_sim* sim = m68k->m68340SIM;
198		assert(sim != NULL);
199
200		if (sim)
201		{
202		int pc = space.device().safe_pc();
203
204		switch (offset)
205		{
206		case m68340SIM_PORTA:
207		logerror("%08x m68340_internal_sim_w %04x, %02x (PORTA - Port A Data)\n", pc, offset,data);
208		break;
209
210		case m68340SIM_DDRA:
211		logerror("%08x m68340_internal_sim_w %04x, %02x (DDRA - Port A Data Direction)\n", pc, offset,data);
212		break;
213
214		case m68340SIM_PPRA1:
215		logerror("%08x m68340_internal_sim_w %04x, %02x (PPRA1 - Port A Pin Assignment 1)\n", pc, offset,data);
216		break;
217
218		case m68340SIM_PPRA2:
219		logerror("%08x m68340_internal_sim_w %04x, %02x (PPRA2 - Port A Pin Assignment 2)\n", pc, offset,data);
220		break;
221
222		case m68340SIM_PORTB:
223		logerror("%08x m68340_internal_sim_w %04x, %02x (PORTB - Port B Data)\n", pc, offset,data);
224		break;
225
226		case m68340SIM_PORTB1:
227		logerror("%08x m68340_internal_sim_w %04x, %02x (PORTB1 - Port B Data - mirror)\n", pc, offset,data);
228		break;
229
230		case m68340SIM_DDRB:
231		logerror("%08x m68340_internal_sim_w %04x, %02x (DDR - Port B Data Direction)\n", pc, offset,data);
232		break;
233
234		case m68340SIM_PPARB:
235		logerror("%08x m68340_internal_sim_w %04x, %02x (PPARB - Port B Pin Assignment)\n", pc, offset,data);
236		break;
237
238		default:
239		logerror("%08x m68340_internal_sim_w %04x, %02x (ILLEGAL?)\n", pc, offset,data);
240		break;
241
242		}
243		}
244		}
245
246		WRITE32_MEMBER( m68000_base_device::m68340_internal_sim_cs_w )
247		{
248		offset += m68340SIM_AM_CS0>>2;
249		m68000_base_device *m68k = this;
250		m68340_sim* sim = m68k->m68340SIM;
251		assert(sim != NULL);
252
253		if (sim)
254		{
255		int pc = space.device().safe_pc();
256
257		switch (offset<<2)
258		{
259		case m68340SIM_AM_CS0:
260		COMBINE_DATA(&sim->m_am[0]);
261		break;
262
263		case m68340SIM_BA_CS0:
264		COMBINE_DATA(&sim->m_ba[0]);
265		break;
266
267		case m68340SIM_AM_CS1:
268		COMBINE_DATA(&sim->m_am[1]);
269		break;
270
271		case m68340SIM_BA_CS1:
272		COMBINE_DATA(&sim->m_ba[1]);
273		break;
274
275		case m68340SIM_AM_CS2:
276		COMBINE_DATA(&sim->m_am[2]);
277		break;
278
279		case m68340SIM_BA_CS2:
280		COMBINE_DATA(&sim->m_ba[2]);
281		break;
282
283		case m68340SIM_AM_CS3:
284		COMBINE_DATA(&sim->m_am[3]);
285		break;
286
287		case m68340SIM_BA_CS3:
288		COMBINE_DATA(&sim->m_ba[3]);
289		break;
290
291		default:
292		logerror("%08x m68340_internal_sim_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask);
293		break;
294
295		}
296		}
297
298		}
299
300
301		void m68340_sim::reset(void)
302		{
303		}

trunk/src/emu/cpu/m68000/68340ser.c

r24087	r24088
1		/* 68340 SERIAL module */
2
3		#include "emu.h"
4		#include "m68kcpu.h"
5
6
7		READ32_HANDLER( m68000_base_device::m68340_internal_serial_r )
8		{
9		m68000_base_device *m68k = this;
10		m68340_serial* serial = m68k->m68340SERIAL;
11		assert(serial != NULL);
12
13		if (serial)
14		{
15		int pc = space.device().safe_pc();
16		logerror("%08x m68340_internal_serial_r %08x, (%08x)\n", pc, offset*4,mem_mask);
17		}
18
19		return 0x00000000;
20		}
21
22		WRITE32_MEMBER( m68000_base_device::m68340_internal_serial_w )
23		{
24		m68000_base_device *m68k = this;
25		m68340_serial* serial = m68k->m68340SERIAL;
26		assert(serial != NULL);
27
28		if (serial)
29		{
30		int pc = space.device().safe_pc();
31		logerror("%08x m68340_internal_serial_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask);
32		}
33
34		}
35
36		void m68340_serial::reset(void)
37		{
38		}

trunk/src/emu/cpu/m68000/68340sim.h

r24087	r24088
1		#define m68340SIM_MCR          (0x00)
2		//                             (0x02)
3		#define m68340SIM_SYNCR        (0x04)
4		#define m68340SIM_AVR_RSR      (0x06)
5		//                             (0x08)
6		//                             (0x0a)
7		//                             (0x0c)
8		//                             (0x0e)
9		#define m68340SIM_PORTA        (0x11)
10		#define m68340SIM_DDRA         (0x13)
11		#define m68340SIM_PPRA1        (0x15)
12		#define m68340SIM_PPRA2        (0x17)
13		#define m68340SIM_PORTB        (0x19)
14		#define m68340SIM_PORTB1       (0x1b)
15		#define m68340SIM_DDRB         (0x1d)
16		#define m68340SIM_PPARB        (0x1f)
17		#define m68340SIM_SWIV_SYPCR   (0x20)
18		#define m68340SIM_PICR         (0x22)
19		#define m68340SIM_PITR         (0x24)
20		#define m68340SIM_SWSR         (0x26)
21		//                             (0x28)
22		//                             (0x2a)
23		//                             (0x2c)
24		//                             (0x2e)
25		//                             (0x30)
26		//                             (0x32)
27		//                             (0x34)
28		//                             (0x36)
29		//                             (0x38)
30		//                             (0x3a)
31		//                             (0x3c)
32		//                             (0x3e)
33		#define m68340SIM_AM_CS0       (0x40)
34		#define m68340SIM_BA_CS0       (0x44)
35		#define m68340SIM_AM_CS1       (0x48)
36		#define m68340SIM_BA_CS1       (0x4c)
37		#define m68340SIM_AM_CS2       (0x50)
38		#define m68340SIM_BA_CS2       (0x54)
39		#define m68340SIM_AM_CS3       (0x58)
40		#define m68340SIM_BA_CS3       (0x5c)
41
42
43
44
45
46
47		class m68340_sim
48		{
49		public:
50
51		UINT32 m_am[4];
52		UINT32 m_ba[4];
53
54
55		void reset(void);
56		};

trunk/src/emu/cpu/m68000/68340ser.h

r24087	r24088
1
2		class m68340_serial
3		{
4		public:
5		void reset(void);
6		};

trunk/src/emu/cpu/m68000/68340dma.c

r24087	r24088
1		/* 68340 DMA module */
2
3		#include "emu.h"
4		#include "m68kcpu.h"
5
6
7		READ32_MEMBER( m68000_base_device::m68340_internal_dma_r )
8		{
9		m68000_base_device *m68k = this;
10		m68340_dma* dma = m68k->m68340DMA;
11		assert(dma != NULL);
12
13		if (dma)
14		{
15		int pc = space.device().safe_pc();
16		logerror("%08x m68340_internal_dma_r %08x, (%08x)\n", pc, offset*4,mem_mask);
17		}
18
19		return 0x00000000;
20		}
21
22		WRITE32_MEMBER( m68000_base_device::m68340_internal_dma_w )
23		{
24		m68000_base_device *m68k = this;
25		m68340_dma* dma = m68k->m68340DMA;
26		assert(dma != NULL);
27
28		if (dma)
29		{
30		int pc = space.device().safe_pc();
31		logerror("%08x m68340_internal_dma_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask);
32		}
33		}
34
35		void m68340_dma::reset(void)
36		{
37		}

trunk/src/emu/cpu/m68000/68340tmu.c

r24087	r24088
1		/* 68340 TIMER module */
2
3		#include "emu.h"
4		#include "m68kcpu.h"
5
6
7
8		READ32_MEMBER( m68000_base_device::m68340_internal_timer_r )
9		{
10		m68000_base_device *m68k = this;
11		m68340_timer* timer = m68k->m68340TIMER;
12		assert(timer != NULL);
13
14		if (timer)
15		{
16		int pc = space.device().safe_pc();
17		logerror("%08x m68340_internal_timer_r %08x, (%08x)\n", pc, offset*4,mem_mask);
18		}
19
20		return 0x00000000;
21		}
22
23		WRITE32_MEMBER( m68000_base_device::m68340_internal_timer_w )
24		{
25		m68000_base_device *m68k = this;
26		m68340_timer* timer = m68k->m68340TIMER;
27		assert(timer != NULL);
28
29		if (timer)
30		{
31		int pc = space.device().safe_pc();
32		logerror("%08x m68340_internal_timer_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask);
33		}
34		}
35
36		void m68340_timer::reset(void)
37		{
38		}

trunk/src/emu/cpu/m68000/68340dma.h

r24087	r24088
1
2		class m68340_dma
3		{
4		public:
5		void reset(void);
6		};

trunk/src/emu/cpu/m68000/m68000.h

r24087	r24088
5	5
6	6
7	7
8		#include "68340sim.h"
9		#include "68340dma.h"
10		#include "68340ser.h"
11		#include "68340tmu.h"
12	8
13	9	#include "../../../lib/softfloat/milieu.h"
14	10	#include "../../../lib/softfloat/softfloat.h"
r24087	r24088
64	60	M68K_CPU_TYPE_68LC040,
65	61	M68K_CPU_TYPE_68040,
66	62	M68K_CPU_TYPE_SCC68070,
67		M68K_CPU_TYPE_68340,
	63	M68K_CPU_TYPE_FSCPU32,
68	64	M68K_CPU_TYPE_COLDFIRE
69	65	};
70	66
r24087	r24088
130	126	class m68000_base_device;
131	127
132	128
133		extern UINT16 m68340_get_cs(m68000_base_device *device, offs_t address);
134	129
135	130	typedef int (*instruction_hook_t)(m68000_base_device *device, offs_t curpc);
136	131
r24087	r24088
361	356	UINT16 ic_data[M68K_IC_SIZE];      /* instruction cache content data */
362	357
363	358
364		int m68340_currentcs;
365	359
366		/* 68340 peripheral modules */
367		m68340_sim*    m68340SIM;
368		m68340_dma*    m68340DMA;
369		m68340_serial* m68340SERIAL;
370		m68340_timer*  m68340TIMER;
371	360
372		UINT32 m68340_base;
373
374
375
376		READ32_MEMBER( m68340_internal_base_r );
377		WRITE32_MEMBER( m68340_internal_base_w );
378		READ32_MEMBER( m68340_internal_dma_r );
379		WRITE32_MEMBER( m68340_internal_dma_w );
380		READ32_HANDLER( m68340_internal_serial_r );
381		WRITE32_MEMBER( m68340_internal_serial_w );
382		READ16_MEMBER( m68340_internal_sim_r );
383		READ8_MEMBER( m68340_internal_sim_ports_r );
384		READ32_MEMBER( m68340_internal_sim_cs_r );
385		WRITE16_MEMBER( m68340_internal_sim_w );
386		WRITE8_MEMBER( m68340_internal_sim_ports_w );
387		WRITE32_MEMBER( m68340_internal_sim_cs_w );
388		READ32_MEMBER( m68340_internal_timer_r );
389		WRITE32_MEMBER( m68340_internal_timer_w );
390
391
392	361	/* 68307 / 68340 internal address map */
393	362	address_space *internal;
394	363
r24087	r24088
412	381	void init_cpu_m68040(void);
413	382	void init_cpu_m68ec040(void);
414	383	void init_cpu_m68lc040(void);
415		void init_cpu_m68340(void);
	384	void init_cpu_fscpu32(void);
416	385	void init_cpu_scc68070(void);
417	386	void init_cpu_coldfire(void);
418	387
r24087	r24088
746	715
747	716
748	717
749		class m68340_device : public m68000_base_device
	718	class fscpu32_device : public m68000_base_device
750	719	{
751	720	public:
752	721	// construction/destruction
753		m68340_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	722	fscpu32_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
754	723
	724	fscpu32_device(const machine_config &mconfig, const char *name, const char *tag, device_t *owner, UINT32 clock,
	725	const device_type type, UINT32 prg_data_width, UINT32 prg_address_bits, address_map_constructor internal_map, const char *shortname, const char *source);
	726
755	727	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
756	728	virtual UINT32 disasm_max_opcode_bytes() const { return 20; };
757	729	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
r24087	r24088
805	777	extern const device_type M68LC040;
806	778	extern const device_type M68040;
807	779	extern const device_type SCC68070;
808		extern const device_type M68340;
	780	extern const device_type FSCPU32;
809	781	extern const device_type MCF5206E;
810	782
811	783	extern void m68k_set_reset_callback(m68000_base_device *device, m68k_reset_func callback);

trunk/src/emu/cpu/m68000/m68kcpu.h

r24087	r24088
84	84	#define CPU_TYPE_LC040  (0x00000100)
85	85	#define CPU_TYPE_040    (0x00000200)
86	86	#define CPU_TYPE_SCC070 (0x00000400)
87		#define CPU_TYPE_68340  (0x00000800)
	87	#define CPU_TYPE_FSCPU32  (0x00000800)
88	88	#define CPU_TYPE_COLDFIRE (0x00001000)
89	89
90	90	/* Different ways to stop the CPU */
r24087	r24088
237	237	#define CPU_TYPE_IS_030_PLUS(A)    ((A) & (CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040))
238	238	#define CPU_TYPE_IS_030_LESS(A)    1
239	239
240		#define CPU_TYPE_IS_020_PLUS(A)    ((A) & (CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_68340 | CPU_TYPE_COLDFIRE))
	240	#define CPU_TYPE_IS_020_PLUS(A)    ((A) & (CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_FSCPU32 | CPU_TYPE_COLDFIRE))
241	241	#define CPU_TYPE_IS_020_LESS(A)    1
242	242
243		#define CPU_TYPE_IS_020_VARIANT(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_68340))
	243	#define CPU_TYPE_IS_020_VARIANT(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_FSCPU32))
244	244
245		#define CPU_TYPE_IS_EC020_PLUS(A)  ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_68340 | CPU_TYPE_COLDFIRE))
	245	#define CPU_TYPE_IS_EC020_PLUS(A)  ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_FSCPU32 | CPU_TYPE_COLDFIRE))
246	246	#define CPU_TYPE_IS_EC020_LESS(A)  ((A) & (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010 | CPU_TYPE_EC020))
247	247
248	248	#define CPU_TYPE_IS_010(A)         ((A) == CPU_TYPE_010)
249		#define CPU_TYPE_IS_010_PLUS(A)    ((A) & (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_68340 | CPU_TYPE_COLDFIRE))
	249	#define CPU_TYPE_IS_010_PLUS(A)    ((A) & (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_FSCPU32 | CPU_TYPE_COLDFIRE))
250	250	#define CPU_TYPE_IS_010_LESS(A)    ((A) & (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010))
251	251
252	252	#define CPU_TYPE_IS_000(A)         ((A) == CPU_TYPE_000 || (A) == CPU_TYPE_008)

trunk/src/emu/cpu/m68000/m68kmake.c

r24087	r24088
136	136	CPU_TYPE_020,       // 2
137	137	CPU_TYPE_030,       // 3
138	138	CPU_TYPE_040,       // 4
139		CPU_TYPE_68340,     // 5
	139	CPU_TYPE_FSCPU32,     // 5
140	140	CPU_TYPE_COLDFIRE,  // 6
141	141	NUM_CPUS
142	142	};

trunk/src/emu/cpu/m68000/m68kdasm.c

r24087	r24088
3821	3821	case M68K_CPU_TYPE_68LC040:
3822	3822	g_cpu_type = TYPE_68040;
3823	3823	break;
3824		case M68K_CPU_TYPE_68340:
	3824	case M68K_CPU_TYPE_FSCPU32:
3825	3825	g_cpu_type = TYPE_68340;
3826	3826	break;
3827	3827	case M68K_CPU_TYPE_COLDFIRE:
r24087	r24088
4018	4018	case M68K_CPU_TYPE_68020:
4019	4019	case M68K_CPU_TYPE_68030:
4020	4020	case M68K_CPU_TYPE_68EC030:
4021		case M68K_CPU_TYPE_68340:
	4021	case M68K_CPU_TYPE_FSCPU32:
4022	4022	case M68K_CPU_TYPE_COLDFIRE:
4023	4023	if(g_instruction_table[instruction] == d68040_cinv)
4024	4024	return 0;
r24087	r24088
4101	4101
4102	4102	CPU_DISASSEMBLE( m68340 )
4103	4103	{
4104		return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68340);
	4104	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_FSCPU32);
4105	4105	}
4106	4106
4107	4107	CPU_DISASSEMBLE( coldfire )

trunk/src/emu/cpu/m68000/m68kcpu.c

r24087	r24088
456	456	4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
457	457	4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4
458	458	},
459		{ /* 68340 */
	459	{ /* CPU32 */
460	460	4, /*  0: Reset - Initial Stack Pointer                      */
461	461	4, /*  1: Reset - Initial Program Counter                    */
462	462	50, /*  2: Bus Error                             (unemulated) */
r24087	r24088
630	630	CPU STATE DESCRIPTION
631	631	***************************************************************************/
632	632
633		#define MASK_ALL                (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_EC040 | CPU_TYPE_040 | CPU_TYPE_68340 )
	633	#define MASK_ALL                (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_EC040 | CPU_TYPE_040 | CPU_TYPE_FSCPU32 )
634	634	#define MASK_24BIT_SPACE            (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010 | CPU_TYPE_EC020)
635		#define MASK_32BIT_SPACE            (CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_EC040 | CPU_TYPE_040 | CPU_TYPE_68340 )
636		#define MASK_010_OR_LATER           (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_68340)
637		#define MASK_020_OR_LATER           (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_EC040 | CPU_TYPE_040 | CPU_TYPE_68340)
	635	#define MASK_32BIT_SPACE            (CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_EC040 | CPU_TYPE_040 | CPU_TYPE_FSCPU32 )
	636	#define MASK_010_OR_LATER           (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_FSCPU32 )
	637	#define MASK_020_OR_LATER           (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_EC040 | CPU_TYPE_040 | CPU_TYPE_FSCPU32 )
638	638	#define MASK_030_OR_LATER           (CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040)
639	639	#define MASK_040_OR_LATER           (CPU_TYPE_040 | CPU_TYPE_EC040)
640	640
r24087	r24088
1229	1229	}
1230	1230
1231	1231
1232		int m68340_calc_cs(m68000_base_device *m68k, offs_t address)
1233		{
1234		m68340_sim* sim = m68k->m68340SIM;
1235	1232
1236		if ( !(sim->m_ba[0] & 1) ) return 1;
1237	1233
1238		for (int i=0;i<4;i++)
1239		{
1240		if (sim->m_ba[i] & 1)
1241		{
1242		int mask = ((sim->m_am[i]&0xffffff00) | 0xff);
1243		int base = sim->m_ba[i] & 0xffffff00;
1244		int fcmask = (sim->m_am[i] & 0xf0);
1245		int fcbase = (sim->m_ba[i] & 0xf0) & ~(sim->m_am[i] & 0xf0);
1246		int fc = m68k->mmu_tmp_fc;
1247	1234
1248		if ((address & ~mask) == base && ((fc << 4) & ~fcmask ) == fcbase ) return i+1;
1249		}
1250		}
1251
1252		return 0;
1253		}
1254
1255
1256
1257
1258
1259	1235	/****************************************************************************
1260	1236	* 32-bit data memory interface
1261	1237	****************************************************************************/
r24087	r24088
1645	1621	}
1646	1622
1647	1623
1648		UINT16 m68340_get_cs(m68000_base_device *device, offs_t address)
1649		{
1650		device->m68340_currentcs = m68340_calc_cs(device, address);
1651	1624
1652		return device->m68340_currentcs;
1653		}
1654	1625
1655	1626	/****************************************************************************
1656	1627	* State definition
r24087	r24088
1704	1675	}
1705	1676
1706	1677
1707		/* 68340 specifics - MOVE */
1708	1678
1709		READ32_MEMBER( m68000_base_device::m68340_internal_base_r )
1710		{
1711		m68000_base_device *m68k = this;
1712		int pc = space.device().safe_pc();
1713		logerror("%08x m68340_internal_base_r %08x, (%08x)\n", pc, offset*4,mem_mask);
1714		return m68k->m68340_base;
1715		}
1716
1717		WRITE32_MEMBER( m68000_base_device::m68340_internal_base_w )
1718		{
1719		m68000_base_device *m68k = this;
1720
1721		int pc = space.device().safe_pc();
1722		logerror("%08x m68340_internal_base_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask);
1723
1724		// other conditions?
1725		if (m68k->dfc==0x7)
1726		{
1727		// unmap old modules
1728		if (m68k->m68340_base&1)
1729		{
1730		int base = m68k->m68340_base & 0xfffff000;
1731
1732		m68k->internal->unmap_readwrite(base + 0x000, base + 0x05f);
1733		m68k->internal->unmap_readwrite(base + 0x600, base + 0x67f);
1734		m68k->internal->unmap_readwrite(base + 0x700, base + 0x723);
1735		m68k->internal->unmap_readwrite(base + 0x780, base + 0x7bf);
1736
1737		}
1738
1739		COMBINE_DATA(&m68k->m68340_base);
1740		logerror("%08x m68340_internal_base_w %08x, %08x (%08x) (m68340_base write)\n", pc, offset*4,data,mem_mask);
1741
1742		// map new modules
1743		if (m68k->m68340_base&1)
1744		{
1745		int base = m68k->m68340_base & 0xfffff000;
1746
1747		m68k->internal->install_readwrite_handler(base + 0x000, base + 0x03f, read16_delegate(FUNC(m68000_base_device::m68340_internal_sim_r),this),     write16_delegate(FUNC(m68000_base_device::m68340_internal_sim_w),this),0xffffffff);
1748		m68k->internal->install_readwrite_handler(base + 0x010, base + 0x01f, read8_delegate(FUNC(m68000_base_device::m68340_internal_sim_ports_r),this),write8_delegate(FUNC(m68000_base_device::m68340_internal_sim_ports_w),this),0xffffffff);
1749		m68k->internal->install_readwrite_handler(base + 0x040, base + 0x05f, read32_delegate(FUNC(m68000_base_device::m68340_internal_sim_cs_r),this),  write32_delegate(FUNC(m68000_base_device::m68340_internal_sim_cs_w),this));
1750		m68k->internal->install_readwrite_handler(base + 0x600, base + 0x67f, read32_delegate(FUNC(m68000_base_device::m68340_internal_timer_r),this),   write32_delegate(FUNC(m68000_base_device::m68340_internal_timer_w),this));
1751		m68k->internal->install_readwrite_handler(base + 0x700, base + 0x723, read32_delegate(FUNC(m68000_base_device::m68340_internal_serial_r),this),  write32_delegate(FUNC(m68000_base_device::m68340_internal_serial_w),this));
1752		m68k->internal->install_readwrite_handler(base + 0x780, base + 0x7bf, read32_delegate(FUNC(m68000_base_device::m68340_internal_dma_r),this),     write32_delegate(FUNC(m68000_base_device::m68340_internal_dma_w),this));
1753
1754		}
1755
1756		}
1757		else
1758		{
1759		logerror("%08x m68340_internal_base_w %08x, %04x (%04x) (should fall through?)\n", pc, offset*4,data,mem_mask);
1760		}
1761
1762
1763
1764		}
1765
1766
1767		static ADDRESS_MAP_START( m68340_internal_map, AS_PROGRAM, 32, m68000_base_device )
1768		AM_RANGE(0x0003ff00, 0x0003ff03) AM_READWRITE( m68340_internal_base_r, m68340_internal_base_w)
1769		ADDRESS_MAP_END
1770
1771
1772	1679	/****************
1773	1680	CPU Inits
1774	1681	****************/
r24087	r24088
2094	2001	}
2095	2002
2096	2003
2097		void m68000_base_device::init_cpu_m68340(void)
	2004	void m68000_base_device::init_cpu_fscpu32(void)
2098	2005	{
2099	2006	init_cpu_common();
2100	2007
2101		cpu_type         = CPU_TYPE_68340;
2102		//   dasm_type        = M68K_CPU_TYPE_68340;
	2008	cpu_type         = CPU_TYPE_FSCPU32;
	2009	//   dasm_type        = M68K_CPU_TYPE_FSCPU32;
2103	2010
2104	2011
2105	2012	init32(*program);
r24087	r24088
2117	2024	cyc_shift        = 0;
2118	2025	cyc_reset        = 518;
2119	2026
2120		m68340SIM    = new m68340_sim();
2121		m68340DMA    = new m68340_dma();
2122		m68340SERIAL = new m68340_serial();
2123		m68340TIMER  = new m68340_timer();
2124
2125		m68340SIM->reset();
2126		m68340DMA->reset();
2127		m68340SERIAL->reset();
2128		m68340TIMER->reset();
2129
2130		m68340_base = 0x00000000;
2131
2132		internal = &this->space(AS_PROGRAM);
2133
2134	2027	define_state();
2135	2028	}
2136	2029
r24087	r24088
2240	2133	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68LC040);
2241	2134	}
2242	2135
2243		CPU_DISASSEMBLE( dasm_m68340 )
	2136	CPU_DISASSEMBLE( dasm_fscpu32 )
2244	2137	{
2245		return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68340);
	2138	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_FSCPU32);
2246	2139	}
2247	2140
2248	2141	CPU_DISASSEMBLE( dasm_coldfire )
r24087	r24088
2266	2159	offs_t m68lc040_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68lc040)(this, buffer, pc, oprom, opram, options); };
2267	2160	offs_t m68040_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68040)(this, buffer, pc, oprom, opram, options); };
2268	2161	offs_t scc68070_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68000)(this, buffer, pc, oprom, opram, options); };
2269		offs_t m68340_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68340)(this, buffer, pc, oprom, opram, options); };
	2162	offs_t fscpu32_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_fscpu32)(this, buffer, pc, oprom, opram, options); };
2270	2163	offs_t mcf5206e_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_coldfire)(this, buffer, pc, oprom, opram, options); };
2271	2164
2272	2165
r24087	r24088
2497	2390	for (int i=0;i<M68K_IC_SIZE;i++)
2498	2391	ic_data[i] = 0;
2499	2392
2500		m68340SIM = 0;
2501		m68340DMA = 0;
2502		m68340SERIAL = 0;
2503		m68340TIMER = 0;
2504		m68340_base = 0;
2505	2393	internal = 0;
2506	2394
2507	2395	instruction_hook = 0;
r24087	r24088
2585	2473	const device_type M68LC040 = &device_creator<m68lc040_device>;
2586	2474	const device_type M68040 = &device_creator<m68040_device>;
2587	2475	const device_type SCC68070 = &device_creator<scc68070_device>;
2588		const device_type M68340 = &device_creator<m68340_device>;
	2476	const device_type FSCPU32 = &device_creator<fscpu32_device>;
2589	2477	const device_type MCF5206E = &device_creator<mcf5206e_device>;
2590	2478
2591	2479	m68000_device::m68000_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
r24087	r24088
2802	2690	}
2803	2691
2804	2692
2805		m68340_device::m68340_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
2806		: m68000_base_device(mconfig, "M68340", tag, owner, clock, M68340, 32,32, ADDRESS_MAP_NAME(m68340_internal_map), "m68340", __FILE__)
	2693	fscpu32_device::fscpu32_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	2694	: m68000_base_device(mconfig, "Freescale CPU32 Core", tag, owner, clock, FSCPU32, 32,32, "fscpu32", __FILE__)
2807	2695	{
2808	2696
2809	2697	}
2810	2698
2811		void m68340_device::device_start()
	2699	fscpu32_device::fscpu32_device(const machine_config &mconfig, const char *name, const char *tag, device_t *owner, UINT32 clock,
	2700	const device_type type, UINT32 prg_data_width, UINT32 prg_address_bits, address_map_constructor internal_map, const char *shortname, const char *source)
	2701	: m68000_base_device(mconfig, name, tag, owner, clock, type, prg_data_width, prg_address_bits, internal_map, shortname, source)
2812	2702	{
2813		init_cpu_m68340();
	2703
2814	2704	}
2815	2705
2816	2706
	2707	void fscpu32_device::device_start()
	2708	{
	2709	init_cpu_fscpu32();
	2710	}
2817	2711
	2712
	2713
2818	2714	mcf5206e_device::mcf5206e_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
2819	2715	: m68000_base_device(mconfig, "MCF5206E", tag, owner, clock, MCF5206E, 32,32, "mcf5206e", __FILE__)
2820	2716	{

trunk/src/emu/cpu/cpu.mak

r24087	r24088
1354	1354	ifneq ($(filter M680X0,$(CPUS)),)
1355	1355	OBJDIRS += $(CPUOBJ)/m68000
1356	1356	CPUOBJS += $(CPUOBJ)/m68000/m68kcpu.o $(CPUOBJ)/m68000/m68kops.o \
1357		$(CPUOBJ)/m68000/68340sim.o \
1358		$(CPUOBJ)/m68000/68340dma.o \
1359		$(CPUOBJ)/m68000/68340ser.o \
1360		$(CPUOBJ)/m68000/68340tmu.o \
1361	1357
1362	1358	DASMOBJS += $(CPUOBJ)/m68000/m68kdasm.o
1363	1359	ifndef M68KMAKE
r24087	r24088
1396	1392
1397	1393	# m68kcpu.h now includes m68kops.h; m68kops.h won't exist until m68kops.c has been made
1398	1394	$(CPUSRC)/m68000/m68kcpu.h: $(CPUOBJ)/m68000/m68kops.c
1399		$(CPUSRC)/m68000/68340sim.c: $(CPUOBJ)/m68000/m68kops.c
1400	1395
1401		$(CPUSRC)/m68000/68340dma.c: $(CPUOBJ)/m68000/m68kops.c
1402	1396
1403		$(CPUSRC)/m68000/68340ser.c: $(CPUOBJ)/m68000/m68kops.c
1404		$(CPUSRC)/m68000/68340tmu.c: $(CPUOBJ)/m68000/m68kops.c
1405	1397
1406
1407	1398	#-------------------------------------------------
1408	1399	# Motorola/Freescale dsp56k
1409	1400	#@src/emu/cpu/dsp56k/dsp56k.h,CPUS += DSP56156

trunk/src/emu/machine/68340dma.c

r0	r24088
	1	/* 68340 DMA module */
	2
	3	#include "emu.h"
	4	#include "68340.h"
	5
	6
	7	READ32_MEMBER( m68340cpu_device::m68340_internal_dma_r )
	8	{
	9	m68340cpu_device *m68k = this;
	10	m68340_dma* dma = m68k->m68340DMA;
	11	assert(dma != NULL);
	12
	13	if (dma)
	14	{
	15	int pc = space.device().safe_pc();
	16	logerror("%08x m68340_internal_dma_r %08x, (%08x)\n", pc, offset*4,mem_mask);
	17	}
	18
	19	return 0x00000000;
	20	}
	21
	22	WRITE32_MEMBER( m68340cpu_device::m68340_internal_dma_w )
	23	{
	24	m68340cpu_device *m68k = this;
	25	m68340_dma* dma = m68k->m68340DMA;
	26	assert(dma != NULL);
	27
	28	if (dma)
	29	{
	30	int pc = space.device().safe_pc();
	31	logerror("%08x m68340_internal_dma_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask);
	32	}
	33	}
	34
	35	void m68340_dma::reset(void)
	36	{
	37	}

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trunk/src/emu/machine/68340dma.h

r0	r24088
	1
	2	#include "cpu/m68000/m68000.h"
	3
	4	class m68340_dma
	5	{
	6	public:
	7	void reset(void);
	8	};

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trunk/src/emu/machine/machine.mak

r24087	r24088
818	818
819	819	#-------------------------------------------------
820	820	#
	821	#@src/emu/machine/68340.h,MACHINES += M68340
	822	#-------------------------------------------------
	823
	824	ifneq ($(filter M68340,$(MACHINES)),)
	825	MACHINEOBJS += $(MACHINEOBJ)/68340.o
	826	MACHINEOBJS += $(MACHINEOBJ)/68340sim.o
	827	MACHINEOBJS += $(MACHINEOBJ)/68340dma.o
	828	MACHINEOBJS += $(MACHINEOBJ)/68340ser.o
	829	MACHINEOBJS += $(MACHINEOBJ)/68340tmu.o
	830	endif
	831
	832	#-------------------------------------------------
	833	#
821	834	#@src/emu/machine/mcf5206e.h,MACHINES += MCF5206E
822	835	#-------------------------------------------------
823	836

trunk/src/emu/machine/68340ser.c

r0	r24088
	1	/* 68340 SERIAL module */
	2
	3	#include "emu.h"
	4	#include "68340.h"
	5
	6
	7	READ32_HANDLER( m68340cpu_device::m68340_internal_serial_r )
	8	{
	9	m68340cpu_device *m68k = this;
	10	m68340_serial* serial = m68k->m68340SERIAL;
	11	assert(serial != NULL);
	12
	13	if (serial)
	14	{
	15	int pc = space.device().safe_pc();
	16	logerror("%08x m68340_internal_serial_r %08x, (%08x)\n", pc, offset*4,mem_mask);
	17	}
	18
	19	return 0x00000000;
	20	}
	21
	22	WRITE32_MEMBER( m68340cpu_device::m68340_internal_serial_w )
	23	{
	24	m68340cpu_device *m68k = this;
	25	m68340_serial* serial = m68k->m68340SERIAL;
	26	assert(serial != NULL);
	27
	28	if (serial)
	29	{
	30	int pc = space.device().safe_pc();
	31	logerror("%08x m68340_internal_serial_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask);
	32	}
	33
	34	}
	35
	36	void m68340_serial::reset(void)
	37	{
	38	}

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trunk/src/emu/machine/68340ser.h

r0	r24088
	1
	2	#include "cpu/m68000/m68000.h"
	3
	4	class m68340_serial
	5	{
	6	public:
	7	void reset(void);
	8	};

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trunk/src/emu/machine/68340.c

r0	r24088
	1	/* 68340 */
	2
	3	#include "68340.h"
	4
	5
	6
	7
	8	int m68340_calc_cs(m68340cpu_device *m68k, offs_t address)
	9	{
	10	m68340_sim* sim = m68k->m68340SIM;
	11
	12	if ( !(sim->m_ba[0] & 1) ) return 1;
	13
	14	for (int i=0;i<4;i++)
	15	{
	16	if (sim->m_ba[i] & 1)
	17	{
	18	int mask = ((sim->m_am[i]&0xffffff00) | 0xff);
	19	int base = sim->m_ba[i] & 0xffffff00;
	20	int fcmask = (sim->m_am[i] & 0xf0);
	21	int fcbase = (sim->m_ba[i] & 0xf0) & ~(sim->m_am[i] & 0xf0);
	22	int fc = m68k->mmu_tmp_fc;
	23
	24	if ((address & ~mask) == base && ((fc << 4) & ~fcmask ) == fcbase ) return i+1;
	25	}
	26	}
	27
	28	return 0;
	29	}
	30
	31
	32
	33	UINT16 m68340_get_cs(m68340cpu_device *device, offs_t address)
	34	{
	35	device->m68340_currentcs = m68340_calc_cs(device, address);
	36
	37	return device->m68340_currentcs;
	38	}
	39
	40
	41
	42	/* 68340 specifics - MOVE */
	43
	44	READ32_MEMBER( m68340cpu_device::m68340_internal_base_r )
	45	{
	46	m68340cpu_device *m68k = this;
	47	int pc = space.device().safe_pc();
	48	logerror("%08x m68340_internal_base_r %08x, (%08x)\n", pc, offset*4,mem_mask);
	49	return m68k->m68340_base;
	50	}
	51
	52	WRITE32_MEMBER( m68340cpu_device::m68340_internal_base_w )
	53	{
	54	m68340cpu_device *m68k = this;
	55
	56	int pc = space.device().safe_pc();
	57	logerror("%08x m68340_internal_base_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask);
	58
	59	// other conditions?
	60	if (m68k->dfc==0x7)
	61	{
	62	// unmap old modules
	63	if (m68k->m68340_base&1)
	64	{
	65	int base = m68k->m68340_base & 0xfffff000;
	66
	67	m68k->internal->unmap_readwrite(base + 0x000, base + 0x05f);
	68	m68k->internal->unmap_readwrite(base + 0x600, base + 0x67f);
	69	m68k->internal->unmap_readwrite(base + 0x700, base + 0x723);
	70	m68k->internal->unmap_readwrite(base + 0x780, base + 0x7bf);
	71
	72	}
	73
	74	COMBINE_DATA(&m68k->m68340_base);
	75	logerror("%08x m68340_internal_base_w %08x, %08x (%08x) (m68340_base write)\n", pc, offset*4,data,mem_mask);
	76
	77	// map new modules
	78	if (m68k->m68340_base&1)
	79	{
	80	int base = m68k->m68340_base & 0xfffff000;
	81
	82	m68k->internal->install_readwrite_handler(base + 0x000, base + 0x03f, read16_delegate(FUNC(m68340cpu_device::m68340_internal_sim_r),this),     write16_delegate(FUNC(m68340cpu_device::m68340_internal_sim_w),this),0xffffffff);
	83	m68k->internal->install_readwrite_handler(base + 0x010, base + 0x01f, read8_delegate(FUNC(m68340cpu_device::m68340_internal_sim_ports_r),this),write8_delegate(FUNC(m68340cpu_device::m68340_internal_sim_ports_w),this),0xffffffff);
	84	m68k->internal->install_readwrite_handler(base + 0x040, base + 0x05f, read32_delegate(FUNC(m68340cpu_device::m68340_internal_sim_cs_r),this),  write32_delegate(FUNC(m68340cpu_device::m68340_internal_sim_cs_w),this));
	85	m68k->internal->install_readwrite_handler(base + 0x600, base + 0x67f, read32_delegate(FUNC(m68340cpu_device::m68340_internal_timer_r),this),   write32_delegate(FUNC(m68340cpu_device::m68340_internal_timer_w),this));
	86	m68k->internal->install_readwrite_handler(base + 0x700, base + 0x723, read32_delegate(FUNC(m68340cpu_device::m68340_internal_serial_r),this),  write32_delegate(FUNC(m68340cpu_device::m68340_internal_serial_w),this));
	87	m68k->internal->install_readwrite_handler(base + 0x780, base + 0x7bf, read32_delegate(FUNC(m68340cpu_device::m68340_internal_dma_r),this),     write32_delegate(FUNC(m68340cpu_device::m68340_internal_dma_w),this));
	88
	89	}
	90
	91	}
	92	else
	93	{
	94	logerror("%08x m68340_internal_base_w %08x, %04x (%04x) (should fall through?)\n", pc, offset*4,data,mem_mask);
	95	}
	96
	97
	98
	99	}
	100
	101
	102	static ADDRESS_MAP_START( m68340_internal_map, AS_PROGRAM, 32, m68340cpu_device )
	103	AM_RANGE(0x0003ff00, 0x0003ff03) AM_READWRITE( m68340_internal_base_r, m68340_internal_base_w)
	104	ADDRESS_MAP_END
	105
	106
	107
	108
	109
	110	m68340cpu_device::m68340cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	111	: fscpu32_device(mconfig, "MC68340", tag, owner, clock, M68340, 32,32, ADDRESS_MAP_NAME(m68340_internal_map), "mc68340", __FILE__)
	112	{
	113	m68340SIM = 0;
	114	m68340DMA = 0;
	115	m68340SERIAL = 0;
	116	m68340TIMER = 0;
	117	m68340_base = 0;
	118	}
	119
	120
	121
	122
	123
	124
	125	void m68340cpu_device::device_reset()
	126	{
	127	fscpu32_device::device_reset();
	128	}
	129
	130
	131	void m68340cpu_device::device_start()
	132	{
	133	fscpu32_device::device_start();
	134
	135	m68340SIM    = new m68340_sim();
	136	m68340DMA    = new m68340_dma();
	137	m68340SERIAL = new m68340_serial();
	138	m68340TIMER  = new m68340_timer();
	139
	140	m68340SIM->reset();
	141	m68340DMA->reset();
	142	m68340SERIAL->reset();
	143	m68340TIMER->reset();
	144
	145	m68340_base = 0x00000000;
	146
	147	internal = &this->space(AS_PROGRAM);
	148	}
	149
	150

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trunk/src/emu/machine/68340.h

r0	r24088
	1	/* 68340 */
	2
	3
	4	#pragma once
	5	#ifndef __M68340_H__
	6	#define __M68340_H__
	7
	8	#include "emu.h"
	9	#include "cpu/m68000/m68000.h"
	10
	11	#include "68340sim.h"
	12	#include "68340dma.h"
	13	#include "68340ser.h"
	14	#include "68340tmu.h"
	15
	16
	17
	18
	19
	20	class m68340cpu_device : public fscpu32_device {
	21	public:
	22	m68340cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	23
	24
	25	int m68340_currentcs;
	26
	27	/* 68340 peripheral modules */
	28	m68340_sim*    m68340SIM;
	29	m68340_dma*    m68340DMA;
	30	m68340_serial* m68340SERIAL;
	31	m68340_timer*  m68340TIMER;
	32
	33	UINT32 m68340_base;
	34
	35
	36
	37	READ32_MEMBER( m68340_internal_base_r );
	38	WRITE32_MEMBER( m68340_internal_base_w );
	39	READ32_MEMBER( m68340_internal_dma_r );
	40	WRITE32_MEMBER( m68340_internal_dma_w );
	41	READ32_HANDLER( m68340_internal_serial_r );
	42	WRITE32_MEMBER( m68340_internal_serial_w );
	43	READ16_MEMBER( m68340_internal_sim_r );
	44	READ8_MEMBER( m68340_internal_sim_ports_r );
	45	READ32_MEMBER( m68340_internal_sim_cs_r );
	46	WRITE16_MEMBER( m68340_internal_sim_w );
	47	WRITE8_MEMBER( m68340_internal_sim_ports_w );
	48	WRITE32_MEMBER( m68340_internal_sim_cs_w );
	49	READ32_MEMBER( m68340_internal_timer_r );
	50	WRITE32_MEMBER( m68340_internal_timer_w );
	51
	52
	53	protected:
	54
	55	virtual void device_start();
	56	virtual void device_reset();
	57
	58	};
	59
	60	static const device_type M68340 = &device_creator<m68340cpu_device>;
	61
	62	extern UINT16 m68340_get_cs(m68340cpu_device *device, offs_t address);
	63
	64
	65
	66
	67
	68	#endif
		No newline at end of file

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trunk/src/emu/machine/68340sim.c

r0	r24088
	1	/* 68340 SIM module */
	2
	3	#include "emu.h"
	4	#include "68340.h"
	5
	6
	7	READ16_MEMBER( m68340cpu_device::m68340_internal_sim_r )
	8	{
	9	m68340cpu_device *m68k = this;
	10	m68340_sim* sim = m68k->m68340SIM;
	11	assert(sim != NULL);
	12
	13	if (sim)
	14	{
	15	int pc = space.device().safe_pc();
	16
	17	switch (offset<<1)
	18	{
	19	case m68340SIM_MCR:
	20	logerror("%08x m68340_internal_sim_r %04x, (%04x) (MCR - Module Configuration Register)\n", pc, offset*2,mem_mask);
	21	return space.machine().rand();
	22
	23	case m68340SIM_SYNCR:
	24	logerror("%08x m68340_internal_sim_r %04x, (%04x) (SYNCR - Clock Synthesizer Register)\n", pc, offset*2,mem_mask);
	25	return space.machine().rand();
	26
	27	case m68340SIM_AVR_RSR:
	28	logerror("%08x m68340_internal_sim_r %04x, (%04x) (AVR, RSR - Auto Vector Register, Reset Status Register)\n", pc, offset*2,mem_mask);
	29	return space.machine().rand();
	30
	31	case m68340SIM_SWIV_SYPCR:
	32	logerror("%08x m68340_internal_sim_r %04x, (%04x) (SWIV_SYPCR - Software Interrupt Vector, System Protection Control Register)\n", pc, offset*2,mem_mask);
	33	return space.machine().rand();
	34
	35	case m68340SIM_PICR:
	36	logerror("%08x m68340_internal_sim_r %04x, (%04x) (PICR - Periodic Interrupt Control Register)\n", pc, offset*2,mem_mask);
	37	return space.machine().rand();
	38
	39	case m68340SIM_PITR:
	40	logerror("%08x m68340_internal_sim_r %04x, (%04x) (PITR - Periodic Interrupt Timer Register)\n", pc, offset*2,mem_mask);
	41	return space.machine().rand();
	42
	43	case m68340SIM_SWSR:
	44	logerror("%08x m68340_internal_sim_r %04x, (%04x) (SWSR - Software Service)\n", pc, offset*2,mem_mask);
	45	return space.machine().rand();
	46
	47	default:
	48	logerror("%08x m68340_internal_sim_r %04x, (%04x)\n", pc, offset*2,mem_mask);
	49
	50
	51	}
	52	}
	53
	54	return 0x0000;
	55	}
	56
	57	READ8_MEMBER( m68340cpu_device::m68340_internal_sim_ports_r )
	58	{
	59	offset += 0x10;
	60	m68340cpu_device *m68k = this;
	61	m68340_sim* sim = m68k->m68340SIM;
	62	assert(sim != NULL);
	63
	64	if (sim)
	65	{
	66	int pc = space.device().safe_pc();
	67
	68	switch (offset)
	69	{
	70	case m68340SIM_PORTA:
	71	logerror("%08x m68340_internal_sim_r %04x (PORTA - Port A Data)\n", pc, offset);
	72	return space.machine().rand();
	73
	74	case m68340SIM_DDRA:
	75	logerror("%08x m68340_internal_sim_r %04x (DDRA - Port A Data Direction)\n", pc, offset);
	76	return space.machine().rand();
	77
	78	case m68340SIM_PPRA1:
	79	logerror("%08x m68340_internal_sim_r %04x (PPRA1 - Port A Pin Assignment 1)\n", pc, offset);
	80	return space.machine().rand();
	81
	82	case m68340SIM_PPRA2:
	83	logerror("%08x m68340_internal_sim_r %04x (PPRA2 - Port A Pin Assignment 2)\n", pc, offset);
	84	return space.machine().rand();
	85
	86	case m68340SIM_PORTB:
	87	logerror("%08x m68340_internal_sim_r %04x (PORTB - Port B Data 0)\n", pc, offset);
	88	return space.machine().rand();
	89
	90	case m68340SIM_PORTB1:
	91	logerror("%08x m68340_internal_sim_r %04x (PORTB1 - Port B Data 1)\n", pc, offset);
	92	return space.machine().rand();
	93
	94	case m68340SIM_DDRB:
	95	logerror("%08x m68340_internal_sim_r %04x (DDR - Port B Data Direction)\n", pc, offset);
	96	return space.machine().rand();
	97
	98	case m68340SIM_PPARB:
	99	logerror("%08x m68340_internal_sim_r %04x (PPARB - Port B Pin Assignment)\n", pc, offset);
	100	return space.machine().rand();
	101
	102	default:
	103	logerror("%08x m68340_internal_sim_r %04x (ILLEGAL?)\n", pc, offset);
	104	return space.machine().rand();
	105
	106	}
	107	}
	108
	109	return 0x00;
	110	}
	111
	112	READ32_MEMBER( m68340cpu_device::m68340_internal_sim_cs_r )
	113	{
	114	offset += m68340SIM_AM_CS0>>2;
	115
	116	m68340cpu_device *m68k = this;
	117	m68340_sim* sim = m68k->m68340SIM;
	118	assert(sim != NULL);
	119
	120	if (sim)
	121	{
	122	int pc = space.device().safe_pc();
	123
	124	switch (offset<<2)
	125	{
	126	case m68340SIM_AM_CS0:  return sim->m_am[0];
	127	case m68340SIM_BA_CS0:  return sim->m_ba[0];
	128	case m68340SIM_AM_CS1:  return sim->m_am[1];
	129	case m68340SIM_BA_CS1:  return sim->m_ba[1];
	130	case m68340SIM_AM_CS2:  return sim->m_am[2];
	131	case m68340SIM_BA_CS2:  return sim->m_ba[2];
	132	case m68340SIM_AM_CS3:  return sim->m_am[3];
	133	case m68340SIM_BA_CS3:  return sim->m_ba[3];
	134
	135	default:
	136	logerror("%08x m68340_internal_sim_r %08x, (%08x)\n", pc, offset*4,mem_mask);
	137
	138	}
	139	}
	140
	141	return 0x00000000;
	142	}
	143
	144	WRITE16_MEMBER( m68340cpu_device::m68340_internal_sim_w )
	145	{
	146	m68340cpu_device *m68k = this;
	147	m68340_sim* sim = m68k->m68340SIM;
	148	assert(sim != NULL);
	149
	150	if (sim)
	151	{
	152	int pc = space.device().safe_pc();
	153
	154	switch (offset<<1)
	155	{
	156	case m68340SIM_MCR:
	157	logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (MCR - Module Configuration Register)\n", pc, offset*2,data,mem_mask);
	158	break;
	159
	160	case m68340SIM_SYNCR:
	161	logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (SYNCR - Clock Synthesizer Register)\n", pc, offset*2,data,mem_mask);
	162	break;
	163
	164
	165	case m68340SIM_AVR_RSR:
	166	logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (AVR, RSR - Auto Vector Register, Reset Status Register)\n", pc, offset*2,data,mem_mask);
	167	break;
	168
	169	case m68340SIM_SWIV_SYPCR:
	170	logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (SWIV_SYPCR - Software Interrupt Vector, System Protection Control Register)\n", pc, offset*2,data,mem_mask);
	171	break;
	172
	173	case m68340SIM_PICR:
	174	logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (PICR - Periodic Interrupt Control Register)\n", pc, offset*2,data,mem_mask);
	175	break;
	176
	177	case m68340SIM_PITR:
	178	logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (PITR - Periodic Interrupt Timer Register)\n", pc, offset*2,data,mem_mask);
	179	break;
	180
	181	case m68340SIM_SWSR:
	182	// basically watchdog, you must write an alternating pattern of 0x55 / 0xaa to keep the watchdog from resetting the system
	183	//logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (SWSR - Software Service)\n", pc, offset*2,data,mem_mask);
	184	break;
	185
	186	default:
	187	logerror("%08x m68340_internal_sim_w %04x, %04x (%04x)\n", pc, offset*2,data,mem_mask);
	188
	189	}
	190	}
	191	}
	192
	193	WRITE8_MEMBER( m68340cpu_device::m68340_internal_sim_ports_w )
	194	{
	195	offset += 0x10;
	196	m68340cpu_device *m68k = this;
	197	m68340_sim* sim = m68k->m68340SIM;
	198	assert(sim != NULL);
	199
	200	if (sim)
	201	{
	202	int pc = space.device().safe_pc();
	203
	204	switch (offset)
	205	{
	206	case m68340SIM_PORTA:
	207	logerror("%08x m68340_internal_sim_w %04x, %02x (PORTA - Port A Data)\n", pc, offset,data);
	208	break;
	209
	210	case m68340SIM_DDRA:
	211	logerror("%08x m68340_internal_sim_w %04x, %02x (DDRA - Port A Data Direction)\n", pc, offset,data);
	212	break;
	213
	214	case m68340SIM_PPRA1:
	215	logerror("%08x m68340_internal_sim_w %04x, %02x (PPRA1 - Port A Pin Assignment 1)\n", pc, offset,data);
	216	break;
	217
	218	case m68340SIM_PPRA2:
	219	logerror("%08x m68340_internal_sim_w %04x, %02x (PPRA2 - Port A Pin Assignment 2)\n", pc, offset,data);
	220	break;
	221
	222	case m68340SIM_PORTB:
	223	logerror("%08x m68340_internal_sim_w %04x, %02x (PORTB - Port B Data)\n", pc, offset,data);
	224	break;
	225
	226	case m68340SIM_PORTB1:
	227	logerror("%08x m68340_internal_sim_w %04x, %02x (PORTB1 - Port B Data - mirror)\n", pc, offset,data);
	228	break;
	229
	230	case m68340SIM_DDRB:
	231	logerror("%08x m68340_internal_sim_w %04x, %02x (DDR - Port B Data Direction)\n", pc, offset,data);
	232	break;
	233
	234	case m68340SIM_PPARB:
	235	logerror("%08x m68340_internal_sim_w %04x, %02x (PPARB - Port B Pin Assignment)\n", pc, offset,data);
	236	break;
	237
	238	default:
	239	logerror("%08x m68340_internal_sim_w %04x, %02x (ILLEGAL?)\n", pc, offset,data);
	240	break;
	241
	242	}
	243	}
	244	}
	245
	246	WRITE32_MEMBER( m68340cpu_device::m68340_internal_sim_cs_w )
	247	{
	248	offset += m68340SIM_AM_CS0>>2;
	249	m68340cpu_device *m68k = this;
	250	m68340_sim* sim = m68k->m68340SIM;
	251	assert(sim != NULL);
	252
	253	if (sim)
	254	{
	255	int pc = space.device().safe_pc();
	256
	257	switch (offset<<2)
	258	{
	259	case m68340SIM_AM_CS0:
	260	COMBINE_DATA(&sim->m_am[0]);
	261	break;
	262
	263	case m68340SIM_BA_CS0:
	264	COMBINE_DATA(&sim->m_ba[0]);
	265	break;
	266
	267	case m68340SIM_AM_CS1:
	268	COMBINE_DATA(&sim->m_am[1]);
	269	break;
	270
	271	case m68340SIM_BA_CS1:
	272	COMBINE_DATA(&sim->m_ba[1]);
	273	break;
	274
	275	case m68340SIM_AM_CS2:
	276	COMBINE_DATA(&sim->m_am[2]);
	277	break;
	278
	279	case m68340SIM_BA_CS2:
	280	COMBINE_DATA(&sim->m_ba[2]);
	281	break;
	282
	283	case m68340SIM_AM_CS3:
	284	COMBINE_DATA(&sim->m_am[3]);
	285	break;
	286
	287	case m68340SIM_BA_CS3:
	288	COMBINE_DATA(&sim->m_ba[3]);
	289	break;
	290
	291	default:
	292	logerror("%08x m68340_internal_sim_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask);
	293	break;
	294
	295	}
	296	}
	297
	298	}
	299
	300
	301	void m68340_sim::reset(void)
	302	{
	303	}

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trunk/src/emu/machine/68340sim.h

r0	r24088
	1
	2	#include "cpu/m68000/m68000.h"
	3
	4	#define m68340SIM_MCR          (0x00)
	5	//                             (0x02)
	6	#define m68340SIM_SYNCR        (0x04)
	7	#define m68340SIM_AVR_RSR      (0x06)
	8	//                             (0x08)
	9	//                             (0x0a)
	10	//                             (0x0c)
	11	//                             (0x0e)
	12	#define m68340SIM_PORTA        (0x11)
	13	#define m68340SIM_DDRA         (0x13)
	14	#define m68340SIM_PPRA1        (0x15)
	15	#define m68340SIM_PPRA2        (0x17)
	16	#define m68340SIM_PORTB        (0x19)
	17	#define m68340SIM_PORTB1       (0x1b)
	18	#define m68340SIM_DDRB         (0x1d)
	19	#define m68340SIM_PPARB        (0x1f)
	20	#define m68340SIM_SWIV_SYPCR   (0x20)
	21	#define m68340SIM_PICR         (0x22)
	22	#define m68340SIM_PITR         (0x24)
	23	#define m68340SIM_SWSR         (0x26)
	24	//                             (0x28)
	25	//                             (0x2a)
	26	//                             (0x2c)
	27	//                             (0x2e)
	28	//                             (0x30)
	29	//                             (0x32)
	30	//                             (0x34)
	31	//                             (0x36)
	32	//                             (0x38)
	33	//                             (0x3a)
	34	//                             (0x3c)
	35	//                             (0x3e)
	36	#define m68340SIM_AM_CS0       (0x40)
	37	#define m68340SIM_BA_CS0       (0x44)
	38	#define m68340SIM_AM_CS1       (0x48)
	39	#define m68340SIM_BA_CS1       (0x4c)
	40	#define m68340SIM_AM_CS2       (0x50)
	41	#define m68340SIM_BA_CS2       (0x54)
	42	#define m68340SIM_AM_CS3       (0x58)
	43	#define m68340SIM_BA_CS3       (0x5c)
	44
	45
	46
	47
	48
	49
	50	class m68340_sim
	51	{
	52	public:
	53
	54	UINT32 m_am[4];
	55	UINT32 m_ba[4];
	56
	57
	58	void reset(void);
	59	};

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trunk/src/emu/machine/68340tmu.c

r0	r24088
	1	/* 68340 TIMER module */
	2
	3	#include "emu.h"
	4	#include "68340.h"
	5
	6
	7	READ32_MEMBER( m68340cpu_device::m68340_internal_timer_r )
	8	{
	9	m68340cpu_device *m68k = this;
	10	m68340_timer* timer = m68k->m68340TIMER;
	11	assert(timer != NULL);
	12
	13	if (timer)
	14	{
	15	int pc = space.device().safe_pc();
	16	logerror("%08x m68340_internal_timer_r %08x, (%08x)\n", pc, offset*4,mem_mask);
	17	}
	18
	19	return 0x00000000;
	20	}
	21
	22	WRITE32_MEMBER( m68340cpu_device::m68340_internal_timer_w )
	23	{
	24	m68340cpu_device *m68k = this;
	25	m68340_timer* timer = m68k->m68340TIMER;
	26	assert(timer != NULL);
	27
	28	if (timer)
	29	{
	30	int pc = space.device().safe_pc();
	31	logerror("%08x m68340_internal_timer_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask);
	32	}
	33	}
	34
	35	void m68340_timer::reset(void)
	36	{
	37	}

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trunk/src/emu/machine/68340tmu.h

r0	r24088
	1	#include "cpu/m68000/m68000.h"
	2
	3
	4	class m68340_timer
	5	{
	6	public:
	7	void reset(void);
	8	};

Property changes on: trunk/src/emu/machine/68340tmu.h

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