MAME SVN History

199869 Revisions

r23537 Saturday 8th June, 2013 at 12:31:19 UTC by O. Galibert
naomi: Better IRQ isolation [O. Galibert]

[src/mame/drivers]	chihiro.c naomi.c triforce.c
[src/mame/includes]	dc.h
[src/mame/machine]	dc.c naomig1.c naomig1.h
[src/mame/video]	powervr2.c powervr2.h
[src/mess/drivers]	dccons.c

trunk/src/mame/drivers/triforce.c
r23536	r23537
547	547	MACHINE_CONFIG_END
548	548
549	549	static MACHINE_CONFIG_DERIVED( triforcegd, triforce_base )
550		MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", "picreturn", NULL, "maincpu", N~~ULL~~)
	550	MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", "picreturn", NULL, "maincpu", NOOP)
551	551	MACHINE_CONFIG_END
552	552
553	553

trunk/src/mame/drivers/naomi.c
r23536	r23537
2498	2498	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
2499	2499	MCFG_SCREEN_UPDATE_DEVICE("powervr2", powervr2_device, screen_update)
2500	2500	MCFG_PALETTE_LENGTH(0x1000)
2501		MCFG_POWERVR2_ADD("powervr2")
	2501	MCFG_POWERVR2_ADD("powervr2", WRITE8(dc_state, pvr_irq))
2502	2502
2503	2503
2504	2504	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
r23536	r23537
2521	2521	*/
2522	2522
2523	2523	static MACHINE_CONFIG_DERIVED( naomi, naomi_base )
2524		MCFG_NAOMI_ROM_BOARD_ADD("rom_board", "naomibd_eeprom", "maincpu", ~~naomi~~_g1_irq)
	2524	MCFG_NAOMI_ROM_BOARD_ADD("rom_board", "naomibd_eeprom", "maincpu", WRITE8(dc_state, g1_irq))
2525	2525	MACHINE_CONFIG_END
2526	2526
2527	2527	/*
r23536	r23537
2529	2529	*/
2530	2530
2531	2531	static MACHINE_CONFIG_DERIVED( naomigd, naomi_base )
2532		MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", ":pic", "naomibd_eeprom", "maincpu", ~~naomi~~_g1_irq)
	2532	MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", ":pic", "naomibd_eeprom", "maincpu", WRITE8(dc_state, g1_irq))
2533	2533	MACHINE_CONFIG_END
2534	2534
2535	2535	/*
r23536	r23537
2537	2537	*/
2538	2538
2539	2539	static MACHINE_CONFIG_DERIVED( naomim1, naomi_base )
2540		MCFG_NAOMI_M1_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", "maincpu", ~~naomi~~_g1_irq)
	2540	MCFG_NAOMI_M1_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", "maincpu", WRITE8(dc_state, g1_irq))
2541	2541	MACHINE_CONFIG_END
2542	2542
2543	2543	/*
r23536	r23537
2545	2545	*/
2546	2546
2547	2547	static MACHINE_CONFIG_DERIVED( naomim2, naomi_base )
2548		MCFG_NAOMI_M2_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", "maincpu", ~~naomi~~_g1_irq)
	2548	MCFG_NAOMI_M2_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", "maincpu", WRITE8(dc_state, g1_irq))
2549	2549	MACHINE_CONFIG_END
2550	2550
2551	2551	/*
r23536	r23537
2553	2553	*/
2554	2554
2555	2555	static MACHINE_CONFIG_DERIVED( naomim4, naomi_base )
2556		MCFG_NAOMI_M4_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", "maincpu", ~~naomi~~_g1_irq)
	2556	MCFG_NAOMI_M4_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", "maincpu", WRITE8(dc_state, g1_irq))
2557	2557	MACHINE_CONFIG_END
2558	2558
2559	2559	/*
r23536	r23537
2600	2600	MCFG_CPU_MODIFY("maincpu")
2601	2601	MCFG_CPU_PROGRAM_MAP(aw_map)
2602	2602	MCFG_MACRONIX_29L001MC_ADD("awflash")
2603		MCFG_AW_ROM_BOARD_ADD("rom_board", ":rom_key", "maincpu", ~~naomi~~_g1_irq)
	2603	MCFG_AW_ROM_BOARD_ADD("rom_board", ":rom_key", "maincpu", WRITE8(dc_state, g1_irq))
2604	2604	MACHINE_CONFIG_END
2605	2605
2606	2606	static MACHINE_CONFIG_DERIVED( aw1c, aw_base )

trunk/src/mame/drivers/chihiro.c
r23536	r23537
3069	3069	MACHINE_CONFIG_END
3070	3070
3071	3071	static MACHINE_CONFIG_DERIVED( chihirogd, chihiro_base )
3072		MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", "pic", NULL, "maincpu", N~~ULL~~)
	3072	MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", "pic", NULL, "maincpu", NOOP)
3073	3073	MACHINE_CONFIG_END
3074	3074
3075	3075	#define ROM_LOAD16_WORD_SWAP_BIOS(bios,name,offset,length,hash) \

trunk/src/mame/machine/dc.c
r23536	r23537
10	10	#include "cpu/sh4/sh4.h"
11	11	#include "sound/aica.h"
12	12	#include "machine/mie.h"
	13	#include "machine/naomig1.h"
	14	#include "video/powervr2.h"
13	15
14	16	#define DEBUG_REGISTERS (1)
15	17
r23536	r23537
81	83	dc_update_interrupt_status();
82	84	}
83	85
84		~~voi~~d ~~naomi~~_g1_irq~~(running_machine &machine~~)
	86	WRITE8_MEMBER(dc_state::g1_irq)
85	87	{
86		dc_state *state = machine.driver_data<dc_state>();
	88	switch(data) {
	89	case naomi_g1_device::DMA_GDROM_IRQ:
	90	dc_sysctrl_regs[SB_ISTNRM] \|= IST_DMA_GDROM;
	91	break;
	92	}
	93	dc_update_interrupt_status();
	94	}
87	95
88		state->dc_sysctrl_regs[SB_ISTNRM] \|= IST_DMA_GDROM;
89		state->dc_update_interrupt_status();
	96	WRITE8_MEMBER(dc_state::pvr_irq)
	97	{
	98	switch(data) {
	99	case powervr2_device::EOXFER_YUV_IRQ:
	100	dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOXFER_YUV;
	101	break;
	102
	103	case powervr2_device::EOXFER_OPLST_IRQ:
	104	dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOXFER_OPLST;
	105	break;
	106
	107	case powervr2_device::EOXFER_OPMV_IRQ:
	108	dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOXFER_OPMV;
	109	break;
	110
	111	case powervr2_device::EOXFER_TRLST_IRQ:
	112	dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOXFER_TRLST;
	113	break;
	114
	115	case powervr2_device::EOXFER_TRMV_IRQ:
	116	dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOXFER_TRMV;
	117	break;
	118
	119	case powervr2_device::EOXFER_PTLST_IRQ:
	120	dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOXFER_PTLST;
	121	break;
	122
	123	case powervr2_device::VBL_IN_IRQ:
	124	dc_sysctrl_regs[SB_ISTNRM] \|= IST_VBL_IN;
	125	break;
	126
	127	case powervr2_device::VBL_OUT_IRQ:
	128	dc_sysctrl_regs[SB_ISTNRM] \|= IST_VBL_OUT;
	129	break;
	130
	131	case powervr2_device::HBL_IN_IRQ:
	132	dc_sysctrl_regs[SB_ISTNRM] \|= IST_VBL_IN;
	133	break;
	134
	135	case powervr2_device::EOR_VIDEO_IRQ:
	136	dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOR_VIDEO;
	137	break;
	138
	139	case powervr2_device::EOR_TSP_IRQ:
	140	dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOR_TSP;
	141	break;
	142
	143	case powervr2_device::EOR_ISP_IRQ:
	144	dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOR_ISP;
	145	break;
	146
	147	case powervr2_device::DMA_PVR_IRQ:
	148	dc_sysctrl_regs[SB_ISTNRM] \|= IST_DMA_PVR;
	149	break;
	150	}
	151	dc_update_interrupt_status();
90	152	}
91	153
92	154	void dc_maple_irq(running_machine &machine)

trunk/src/mame/machine/naomig1.c
r23536	r23537
24	24	ADDRESS_MAP_END
25	25
26	26	naomi_g1_device::naomi_g1_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock)
27		: device_t(mconfig, type, name, tag, owner, clock)
	27	: device_t(mconfig, type, name, tag, owner, clock),
	28	irq_cb(*this)
28	29	{
29	30	cpu = 0;
30	31	}
31	32
32		void naomi_g1_device::s~~tatic_s~~et_maincpu_tag(~~devi~~c~~e_t &device, c~~onst char *maincpu_tag)
	33	void naomi_g1_device::set_maincpu_tag(const char *_maincpu_tag)
33	34	{
34		naomi_g1_device &naomi_g1 = downcast<naomi_g1_device &>(device);
35		naomi_g1.maincpu_tag = maincpu_tag;
	35	maincpu_tag = _maincpu_tag;
36	36	}
37	37
38		void naomi_g1_device::static_set_irq_cb(device_t &device, void (*irq_cb)(running_machine &))
39		{
40		naomi_g1_device &naomi_g1 = downcast<naomi_g1_device &>(device);
41		naomi_g1.irq_cb = irq_cb;
42		}
43
44	38	void naomi_g1_device::device_start()
45	39	{
46	40	cpu = machine().device<sh4_device>(maincpu_tag);
47	41	timer = timer_alloc(G1_TIMER_ID);
	42	irq_cb.resolve_safe();
48	43
49	44	save_item(NAME(gdstar));
50	45	save_item(NAME(gdlen));
r23536	r23537
68	63	if(!gdst)
69	64	return;
70	65	gdst = 0;
71		if(irq_cb)
72		irq_cb(machine());
	66	irq_cb(DMA_GDROM_IRQ);
73	67	}
74	68
75	69	READ32_MEMBER(naomi_g1_device::sb_gdstar_r)

trunk/src/mame/machine/naomig1.h
r23536	r23537
2	2	#define _NAOMIG1_H_
3	3
4	4	#include "cpu/sh4/sh4.h"
	5	#include "includes/dc.h"
5	6
6	7	#define MCFG_NAOMI_G1_ADD(_tag, type, _maincpu_tag, _irq_cb) \
7	8	MCFG_DEVICE_ADD(_tag, type, 0) \
8		naomi_g1_device::static_set_maincpu_tag(*device, _maincpu_tag); \
9		naomi_g1_device::static_set_irq_cb(*device, _irq_cb);
	9	downcast<naomi_g1_device *>(device)->set_maincpu_tag(_maincpu_tag); \
	10	downcast<naomi_g1_device *>(device)->set_irq_cb(DEVCB2_ ## _irq_cb);
10	11
11	12	class naomi_g1_device : public device_t
12	13	{
13	14	public:
	15	enum {
	16	DMA_GDROM_IRQ
	17	};
	18
14	19	naomi_g1_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock);
15		static void static_set_maincpu_tag(device_t &device, const char *maincpu_tag);
16		static void static_set_irq_cb(device_t &device, void (*irq_cb)(running_machine &));
	20	void set_maincpu_tag(const char *maincpu_tag);
	21	template<class _cb> void set_irq_cb(_cb cb) { irq_cb.set_callback(cb); }
17	22
18	23	DECLARE_ADDRESS_MAP(amap, 32);
19	24
r23536	r23537
59	64	sh4_device *cpu;
60	65	const char *maincpu_tag;
61	66	emu_timer *timer;
62		void (*irq_cb~~)(running_machine &)~~;
	67	devcb2_write8 irq_cb;
63	68
64	69	void dma(void *dma_ptr, UINT32 main_adr, UINT32 size, bool to_mainram);
65	70	};

trunk/src/mame/video/powervr2.c
r23536	r23537
124	124	---- ---- ---- ---- ---x ---- ---- ---- hsync
125	125	---- ---- ---- ---- ---- x--- ---- ---- blank
126	126	---- ---- ---- ---- ---- -x-- ---- ---- field number
127		---- ---- ---- ---- ---- --xx xxxx xxxx s~~tate->s~~canline
	127	---- ---- ---- ---- ---- --xx xxxx xxxx scanline
128	128	*/
129	129
130	130
r23536	r23537
832	832
833	833	static const int mipmap_4_8_offset[8] = { 0x00018, 0x00058, 0x00158, 0x00558, 0x01558, 0x05558, 0x15558, 0x55558 }; // 4bpp (4bit offset) / 8bpp (8bit offset)
834	834	static const int mipmap_np_offset[8] = { 0x00030, 0x000B0, 0x002B0, 0x00AB0, 0x02AB0, 0x0AAB0, 0x2AAB0, 0xAAAB0 }; // nonpalette textures
835		static const int mipmap_vq_offset[8] = { 0x00006, 0x00016, 0x00056, 0x00156, 0x00556, 0x01556, 0x05556, 0x15556 }; // vq textures
	835	static const int mipmap_vq_offset[8] = { 0x00006, 0x00016, 0x00056, 0x00156, 0x00556, 0x01556, 0x05556, 0x15556 }; // vq textures
836	836
837	837	switch (miptype)
838	838	{
r23536	r23537
1106	1106	printf("TA_YUV_TEX_BASE initialized to %08x\n", data);
1107	1107
1108	1108	// hack, this interrupt is generated after transfering a set amount of data
1109		//state->state->dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOXFER_YUV;
1110		//state->state->dc_update_interrupt_status();
	1109	//irq_cb(EOXFER_YUV_IRQ);
1111	1110
1112	1111	break;
1113	1112	case TA_YUV_TEX_CTRL:
r23536	r23537
1160	1159
1161	1160	TIMER_CALLBACK_MEMBER(powervr2_device::transfer_opaque_list_irq)
1162	1161	{
1163		dc_state *state = machine().driver_data<dc_state>();
1164		state->dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOXFER_OPLST;
1165		state->dc_update_interrupt_status();
	1162	irq_cb(EOXFER_OPLST_IRQ);
1166	1163	}
1167	1164
1168	1165	TIMER_CALLBACK_MEMBER(powervr2_device::transfer_opaque_modifier_volume_list_irq)
1169	1166	{
1170		dc_state *state = machine().driver_data<dc_state>();
1171		state->dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOXFER_OPMV;
1172		state->dc_update_interrupt_status();
	1167	irq_cb(EOXFER_OPMV_IRQ);
1173	1168	}
1174	1169
1175	1170	TIMER_CALLBACK_MEMBER(powervr2_device::transfer_translucent_list_irq)
1176	1171	{
1177		dc_state *state = machine().driver_data<dc_state>();
1178		state->dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOXFER_TRLST;
1179		state->dc_update_interrupt_status();
	1172	irq_cb(EOXFER_TRLST_IRQ);
1180	1173	}
1181	1174
1182	1175	TIMER_CALLBACK_MEMBER(powervr2_device::transfer_translucent_modifier_volume_list_irq)
1183	1176	{
1184		dc_state *state = machine().driver_data<dc_state>();
1185		state->dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOXFER_TRMV;
1186		state->dc_update_interrupt_status();
	1177	irq_cb(EOXFER_TRMV_IRQ);
1187	1178	}
1188	1179
1189	1180	TIMER_CALLBACK_MEMBER(powervr2_device::transfer_punch_through_list_irq)
1190	1181	{
1191		dc_state *state = machine().driver_data<dc_state>();
1192		state->dc_sysctrl_regs[SB_ISTNRM] \|= (1 << 21);
1193		state->dc_update_interrupt_status();
	1182	irq_cb(EOXFER_PTLST_IRQ);
1194	1183	}
1195	1184
1196	1185	void powervr2_device::process_ta_fifo()
r23536	r23537
1511	1500
1512	1501	WRITE64_MEMBER( powervr2_device::ta_fifo_yuv_w )
1513	1502	{
1514		//dc_state *state = space.machine().driver_data<dc_state>();
1515
1516		// int reg;
1517		// UINT64 shift;
1518		// UINT32 dat;
1519
1520		// reg = decode_reg_64(offset, mem_mask, &shift);
1521		// dat = (UINT32)(data >> shift);
1522
1523		// printf("YUV FIFO: [%08x=%x] write %" I64FMT "x to %x, mask %" I64FMT "x %08x\n", 0x10800000+reg*4, dat, data, offset, mem_mask,test);
1524	1503	}
1525	1504
1526	1505	// SB_LMMODE0
r23536	r23537
2376	2355
2377	2356	TIMER_CALLBACK_MEMBER(powervr2_device::vbin)
2378	2357	{
2379		dc_state *state = machine().driver_data<dc_state>();
2380		state->dc_sysctrl_regs[SB_ISTNRM] \|= IST_VBL_IN; // V Blank-in interrupt
2381		state->dc_update_interrupt_status();
	2358	irq_cb(VBL_IN_IRQ);
2382	2359
2383	2360	vbin_timer->adjust(machine().primary_screen->time_until_pos(spg_vblank_in_irq_line_num));
2384	2361	}
2385	2362
2386	2363	TIMER_CALLBACK_MEMBER(powervr2_device::vbout)
2387	2364	{
2388		dc_state *state = machine().driver_data<dc_state>();
2389		state->dc_sysctrl_regs[SB_ISTNRM] \|= IST_VBL_OUT; // V Blank-out interrupt
2390		state->dc_update_interrupt_status();
	2365	irq_cb(VBL_OUT_IRQ);
2391	2366
2392	2367	vbout_timer->adjust(machine().primary_screen->time_until_pos(spg_vblank_out_irq_line_num));
2393	2368	}
r23536	r23537
2398	2373	{
2399	2374	if(scanline == next_y)
2400	2375	{
2401		dc_state *state = machine().driver_data<dc_state>();
2402		state->dc_sysctrl_regs[SB_ISTNRM] \|= IST_HBL_IN; // H Blank-in interrupt
2403		state->dc_update_interrupt_status();
	2376	irq_cb(HBL_IN_IRQ);
2404	2377	next_y+=spg_line_comp_val;
2405	2378	}
2406	2379	}
2407	2380	else if((scanline == spg_line_comp_val) \|\| (spg_hblank_int_mode & 2))
2408	2381	{
2409		dc_state *state = machine().driver_data<dc_state>();
2410		state->dc_sysctrl_regs[SB_ISTNRM] \|= IST_HBL_IN; // H Blank-in interrupt
2411		state->dc_update_interrupt_status();
	2382	irq_cb(HBL_IN_IRQ);
2412	2383	}
2413	2384
2414	2385	// printf("hbin on scanline %d\n",scanline);
r23536	r23537
2428	2399
2429	2400	TIMER_CALLBACK_MEMBER(powervr2_device::endofrender_video)
2430	2401	{
2431		dc_state *state = machine().driver_data<dc_state>();
2432		state->dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOR_VIDEO;// VIDEO end of render
2433		state->dc_update_interrupt_status();
	2402	irq_cb(EOR_VIDEO_IRQ); // VIDEO end of render
2434	2403	endofrender_timer_video->adjust(attotime::never);
2435	2404	}
2436	2405
2437	2406	TIMER_CALLBACK_MEMBER(powervr2_device::endofrender_tsp)
2438		{
2439		dc_state *state = machine().driver_data<dc_state>();
2440		state->dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOR_TSP; // TSP end of render
2441		state->dc_update_interrupt_status();
	2407	{
	2408	irq_cb(EOR_TSP_IRQ); // TSP end of render
2442	2409
2443	2410	endofrender_timer_tsp->adjust(attotime::never);
2444	2411	endofrender_timer_video->adjust(attotime::from_usec(500) );
r23536	r23537
2446	2413
2447	2414	TIMER_CALLBACK_MEMBER(powervr2_device::endofrender_isp)
2448	2415	{
2449		dc_state *state = machine().driver_data<dc_state>();
2450		state->dc_sysctrl_regs[SB_ISTNRM] \|= IST_EOR_ISP; // ISP end of render
2451		state->dc_update_interrupt_status();
	2416	irq_cb(EOR_ISP_IRQ); // ISP end of render
2452	2417
2453	2418	endofrender_timer_isp->adjust(attotime::never);
2454	2419	endofrender_timer_tsp->adjust(attotime::from_usec(500) );
r23536	r23537
2574	2539
2575	2540	TIMER_CALLBACK_MEMBER(powervr2_device::pvr_dma_irq)
2576	2541	{
2577		dc_state *state = machine().driver_data<dc_state>();
2578	2542	m_pvr_dma.start = pvrctrl_regs[SB_PDST] = 0;
2579		state->dc_sysctrl_regs[SB_ISTNRM] \|= IST_DMA_PVR;
2580		state->dc_update_interrupt_status();
	2543	irq_cb(DMA_PVR_IRQ);
2581	2544	}
2582	2545
2583	2546	READ32_MEMBER(powervr2_device::pvr_ctrl_r)
r23536	r23537
2660	2623	}
2661	2624
2662	2625	powervr2_device::powervr2_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
2663		: device_t(mconfig, POWERVR2, "PowerVR 2", tag, owner, clock)
	2626	: device_t(mconfig, POWERVR2, "PowerVR 2", tag, owner, clock),
	2627	irq_cb(*this)
2664	2628	{
2665	2629	}
2666	2630
2667	2631	void powervr2_device::device_start()
2668	2632	{
	2633	irq_cb.resolve_safe();
	2634
2669	2635	memset(pvrctrl_regs, 0, sizeof(pvrctrl_regs));
2670	2636	memset(pvrta_regs, 0, sizeof(pvrta_regs));
2671	2637	memset(grab, 0, sizeof(grab));

trunk/src/mame/video/powervr2.h
r23536	r23537
1	1	#ifndef __POWERVR2_H__
2	2	#define __POWERVR2_H__
3	3
4		#define MCFG_POWERVR2_ADD(_tag) \
5		MCFG_DEVICE_ADD(_tag, POWERVR2, 0)
	4	#define MCFG_POWERVR2_ADD(_tag, _irq_cb) \
	5	MCFG_DEVICE_ADD(_tag, POWERVR2, 0) \
	6	downcast<powervr2_device *>(device)->set_irq_cb(DEVCB2_ ## _irq_cb);
6	7
7	8	class powervr2_device : public device_t
8	9	{
9	10	public:
10	11	enum { NUM_BUFFERS = 4 };
	12	enum {
	13	EOXFER_YUV_IRQ,
	14	EOXFER_OPLST_IRQ,
	15	EOXFER_OPMV_IRQ,
	16	EOXFER_TRLST_IRQ,
	17	EOXFER_TRMV_IRQ,
	18	EOXFER_PTLST_IRQ,
	19	VBL_IN_IRQ,
	20	VBL_OUT_IRQ,
	21	HBL_IN_IRQ,
	22	EOR_VIDEO_IRQ,
	23	EOR_TSP_IRQ,
	24	EOR_ISP_IRQ,
	25	DMA_PVR_IRQ
	26	};
11	27
12	28	struct {
13	29	UINT32 pvr_addr;
r23536	r23537
110	126	int next_y;
111	127
112	128	powervr2_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	129	template<class _cb> void set_irq_cb(_cb cb) { irq_cb.set_callback(cb); }
113	130
114	131	DECLARE_READ32_MEMBER( pvr_ctrl_r );
115	132	DECLARE_WRITE32_MEMBER( pvr_ctrl_w );
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147	164	virtual void device_reset();
148	165
149	166	private:
	167	devcb2_write8 irq_cb;
	168
150	169	static UINT32 (*const blend_functions[64])(UINT32 s, UINT32 d);
151	170
152	171	static inline INT32 clamp(INT32 in, INT32 min, INT32 max);

trunk/src/mame/includes/dc.h
r23536	r23537
52	52	virtual void machine_start();
53	53	virtual void machine_reset();
54	54	TIMER_CALLBACK_MEMBER(aica_dma_irq);
55		TIMER_CALLBACK_MEMBER(pvr_dma_irq);
56	55	TIMER_CALLBACK_MEMBER(ch2_dma_irq);
57	56	TIMER_CALLBACK_MEMBER(yuv_fifo_irq);
58	57	TIMER_CALLBACK_MEMBER(dc_rtc_increment);
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77	76	DECLARE_WRITE64_MEMBER( dc_modem_w );
78	77	DECLARE_READ64_MEMBER( dc_rtc_r );
79	78	DECLARE_WRITE64_MEMBER( dc_rtc_w );
	79	DECLARE_WRITE8_MEMBER( g1_irq );
	80	DECLARE_WRITE8_MEMBER( pvr_irq );
80	81
81	82	required_device<cpu_device> m_maincpu;
82	83	required_device<cpu_device> m_soundcpu;
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318	319	/* 0x005f8600 - 0x005f8f5c TA_OL_POINTERS (read only) */
319	320
320	321	/* ------------- normal interrupts ------------- */
321		#define IST_EOR_VIDEO 0x00000001
322		#define IST_EOR_ISP 0x00000002
323		#define IST_EOR_TSP 0x00000004
324		#define IST_VBL_IN 0x00000008
325		#define IST_VBL_OUT 0x00000010
326		#define IST_HBL_IN 0x00000020
327		#define IST_EOXFER_YUV 0x00000040
	322	#define IST_EOR_VIDEO 0x00000001
	323	#define IST_EOR_ISP 0x00000002
	324	#define IST_EOR_TSP 0x00000004
	325	#define IST_VBL_IN 0x00000008
	326	#define IST_VBL_OUT 0x00000010
	327	#define IST_HBL_IN 0x00000020
	328	#define IST_EOXFER_YUV 0x00000040
328	329	#define IST_EOXFER_OPLST 0x00000080
329		#define IST_EOXFER_OPMV 0x00000100
	330	#define IST_EOXFER_OPMV 0x00000100
330	331	#define IST_EOXFER_TRLST 0x00000200
331		#define IST_EOXFER_TRMV 0x00000400
332		#define IST_DMA_PVR 0x00000800
333		#define IST_DMA_MAPLE 0x00001000
334		#define IST_DMA_MAPLEVB 0x00002000
335		#define IST_DMA_GDROM 0x00004000
336		#define IST_DMA_AICA 0x00008000
337		#define IST_DMA_EXT1 0x00010000
338		#define IST_DMA_EXT2 0x00020000
339		#define IST_DMA_DEV 0x00040000
340		#define IST_DMA_CH2 0x00080000
341		#define IST_DMA_SORT 0x00100000
342		#define IST_G1G2EXTSTAT 0x40000000
343		#define IST_ERROR 0x80000000
	332	#define IST_EOXFER_TRMV 0x00000400
	333	#define IST_DMA_PVR 0x00000800
	334	#define IST_DMA_MAPLE 0x00001000
	335	#define IST_DMA_MAPLEVB 0x00002000
	336	#define IST_DMA_GDROM 0x00004000
	337	#define IST_DMA_AICA 0x00008000
	338	#define IST_DMA_EXT1 0x00010000
	339	#define IST_DMA_EXT2 0x00020000
	340	#define IST_DMA_DEV 0x00040000
	341	#define IST_DMA_CH2 0x00080000
	342	#define IST_DMA_SORT 0x00100000
	343	#define IST_EOXFER_PTLST 0x00200000
	344	#define IST_G1G2EXTSTAT 0x40000000
	345	#define IST_ERROR 0x80000000
344	346	/* ------------ external interrupts ------------ */
345	347	#define IST_EXT_EXTERNAL 0x00000008
346	348	#define IST_EXT_MODEM 0x00000004

trunk/src/mess/drivers/dccons.c
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206	206	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
207	207	MCFG_SCREEN_UPDATE_DEVICE("powervr2", powervr2_device, screen_update)
208	208	MCFG_PALETTE_LENGTH(0x1000)
209		MCFG_POWERVR2_ADD("powervr2")
	209	MCFG_POWERVR2_ADD("powervr2", WRITE8(dc_state, pvr_irq))
210	210
211	211	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
212	212	MCFG_SOUND_ADD("aica", AICA, 0)

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