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r23536 Saturday 8th June, 2013 at 12:31:10 UTC by O. Galibert
powervr2: Some register groups are obviously 32 bits, so make them so [O. Galibert]
[src/mame/drivers]naomi.c
[src/mame/video]powervr2.c powervr2.h
[src/mess/drivers]dccons.c

trunk/src/mame/drivers/naomi.c
r23535r23536
15341534   AM_RANGE(0x005f7000, 0x005f70ff) AM_MIRROR(0x02000000) AM_DEVICE16( "rom_board", naomi_board, submap, U64(0x0000ffff0000ffff) )
15351535   AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) )
15361536   AM_RANGE(0x005f7800, 0x005f78ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
1537   AM_RANGE(0x005f7c00, 0x005f7cff) AM_MIRROR(0x02000000) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w)
1538   AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w )
1537   AM_RANGE(0x005f7c00, 0x005f7cff) AM_MIRROR(0x02000000) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff))
1538   AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w, U64(0xffffffffffffffff))
15391539   AM_RANGE(0x00600000, 0x006007ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_modem_r, dc_modem_w )
15401540   AM_RANGE(0x00700000, 0x00707fff) AM_MIRROR(0x02000000) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
15411541   AM_RANGE(0x00710000, 0x0071000f) AM_MIRROR(0x02000000) AM_READWRITE(dc_rtc_r, dc_rtc_w )
r23535r23536
15861586   AM_RANGE(0x005f7000, 0x005f70ff) AM_MIRROR(0x02000000) AM_DEVICE16( "rom_board", naomi_board, submap, U64(0x0000ffff0000ffff) )
15871587   AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) )
15881588   AM_RANGE(0x005f7800, 0x005f78ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
1589   AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w)
1590   AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w )
1589   AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff))
1590   AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w, U64(0xffffffffffffffff))
15911591   AM_RANGE(0x00600000, 0x006007ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_modem_r, dc_modem_w )
15921592   AM_RANGE(0x00700000, 0x00707fff) AM_MIRROR(0x02000000) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
15931593   AM_RANGE(0x00710000, 0x0071000f) AM_MIRROR(0x02000000) AM_READWRITE(dc_rtc_r, dc_rtc_w )
r23535r23536
15981598   AM_RANGE(0x0103ff00, 0x0103ffff) AM_MIRROR(0x02000000) AM_READWRITE(naomi_unknown1_r, naomi_unknown1_w ) // bios uses it, actual start and end addresses not known
15991599
16001600//  AM_RANGE(0x025f6800, 0x025f69ff) AM_READWRITE_LEGACY(dc_sysctrl_r, dc_sysctrl_w ) // second PVR DMA!
1601//  AM_RANGE(0x025f7c00, 0x025f7cff) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w)
1602   AM_RANGE(0x025f8000, 0x025f9fff) AM_DEVREADWRITE("powervr2", powervr2_device, pvr2_ta_r, pvr2_ta_w )
1601//  AM_RANGE(0x025f7c00, 0x025f7cff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff))
1602   AM_RANGE(0x025f8000, 0x025f9fff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr2_ta_r, pvr2_ta_w, U64(0xffffffffffffffff))
16031603
16041604   /* Area 1 */
16051605   AM_RANGE(0x04000000, 0x04ffffff) AM_RAM AM_SHARE("dc_texture_ram")      // texture memory 64 bit access
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16091609
16101610   /* Area 2*/
16111611   AM_RANGE(0x085f6800, 0x085f69ff) AM_WRITE(dc_sysctrl_w ) // writes to BOTH PVRs
1612   AM_RANGE(0x085f8000, 0x085f9fff) AM_DEVWRITE("powervr2", powervr2_device, pvrs_ta_w ) // writes to BOTH PVRs
1613   AM_RANGE(0x08800000, 0x088000ff) AM_DEVREADWRITE32("powervr2", powervr2_device, elan_regs_r, elan_regs_w, U64(0xffffffffffffffff) ) // T&L chip registers
1612   AM_RANGE(0x085f8000, 0x085f9fff) AM_DEVWRITE32("powervr2", powervr2_device, pvrs_ta_w, U64(0xffffffffffffffff) ) // writes to BOTH PVRs
1613   AM_RANGE(0x08800000, 0x088000ff) AM_DEVREADWRITE32("powervr2", powervr2_device, elan_regs_r, elan_regs_w, U64(0xffffffffffffffff)) // T&L chip registers
16141614//  AM_RANGE(0x09000000, 0x09??????) T&L command processing
16151615   AM_RANGE(0x0a000000, 0x0bffffff) AM_RAM AM_SHARE("elan_ram") // T&L chip RAM
16161616
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17391739   AM_RANGE(0x005f7000, 0x005f70ff) AM_MIRROR(0x02000000) AM_DEVICE16( "rom_board", aw_rom_board, submap, U64(0x0000ffff0000ffff) )
17401740   AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) )
17411741   AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
1742   AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w)
1743   AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w )
1742   AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff))
1743   AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w, U64(0xffffffffffffffff))
17441744   AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE(aw_modem_r, aw_modem_w )
17451745   AM_RANGE(0x00700000, 0x00707fff) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
17461746   AM_RANGE(0x00710000, 0x0071000f) AM_READWRITE(dc_rtc_r, dc_rtc_w )
trunk/src/mame/video/powervr2.c
r23535r23536
860860
861861}
862862
863// register decode helper
864static inline int decode_reg_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift)
863READ32_MEMBER( powervr2_device::pvr_ta_r )
865864{
866   int reg = offset * 2;
867
868   *shift = 0;
869
870   // non 32-bit accesses have not yet been seen here, we need to know when they are
871   if ((mem_mask != U64(0xffffffff00000000)) && (mem_mask != U64(0x00000000ffffffff)))
865   switch (offset)
872866   {
873      /*assume to return the lower 32-bits ONLY*/
874      return reg & 0xffffffff;
875   }
876
877   if (mem_mask == U64(0xffffffff00000000))
878   {
879      reg++;
880      *shift = 32;
881   }
882
883   return reg;
884}
885
886READ64_MEMBER( powervr2_device::pvr_ta_r )
887{
888   int reg;
889   UINT64 shift;
890
891   reg = decode_reg_64(offset, mem_mask, &shift);
892
893   switch (reg)
894   {
895867   case SPG_STATUS:
896868      {
897869         UINT8 fieldnum,vsync,hsync,blank;
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908880         blank = (space.machine().primary_screen->vblank() | space.machine().primary_screen->hblank()) ? 0 : 1;
909881         if(spg_blank_pol) { blank^=1; }
910882
911         pvrta_regs[reg] = (vsync << 13) | (hsync << 12) | (blank << 11) | (fieldnum << 10) | (space.machine().primary_screen->vpos() & 0x3ff);
883         pvrta_regs[offset] = (vsync << 13) | (hsync << 12) | (blank << 11) | (fieldnum << 10) | (space.machine().primary_screen->vpos() & 0x3ff);
912884         break;
913885      }
914886   case SPG_TRIGGER_POS:
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922894   if (reg != 0x43)
923895      mame_printf_verbose("PVRTA: [%08x] read %x @ %x (reg %x), mask %" I64FMT "x (PC=%x)\n", 0x5f8000+reg*4, pvrta_regs[reg], offset, reg, mem_mask, space.device().safe_pc());
924896   #endif
925   return (UINT64)pvrta_regs[reg] << shift;
897   return (UINT64)pvrta_regs[offset];
926898}
927899
928WRITE64_MEMBER( powervr2_device::pvr_ta_w )
900WRITE32_MEMBER( powervr2_device::pvr_ta_w )
929901{
930   int reg;
931   UINT64 shift;
932   UINT32 dat;
933902   UINT32 sizera,offsetra;
934903   int a;
935904   int sanitycount;
936905
937   reg = decode_reg_64(offset, mem_mask, &shift);
938   dat = (UINT32)(data >> shift);
939   //old = pvrta_regs[reg];
940
941906   // Dreamcast BIOS attempts to set PVRID to zero and then dies
942907   // if it succeeds.  Don't allow.
943   if ((reg != PVRID) && (reg != REVISION))
908   if ((offset != PVRID) && (offset != REVISION))
944909   {
945      pvrta_regs[reg] = dat; // 5f8000+reg*4=dat
910      pvrta_regs[offset] = data; // 5f8000+reg*4=dat
946911   }
947912
948   switch (reg)
913   switch (offset)
949914   {
950915   case SOFTRESET:
951      if (dat & 1)
916      if (data & 1)
952917      {
953918         #if DEBUG_PVRTA
954919         mame_printf_verbose("pvr_ta_w:  TA soft reset\n");
955920         #endif
956921         listtype_used=0;
957922      }
958      if (dat & 2)
923      if (data & 2)
959924      {
960925         #if DEBUG_PVRTA
961926         mame_printf_verbose("pvr_ta_w:  Core Pipeline soft reset\n");
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968933            start_render_received = 0;
969934         }
970935      }
971      if (dat & 4)
936      if (data & 4)
972937      {
973938         #if DEBUG_PVRTA
974939         mame_printf_verbose("pvr_ta_w:  sdram I/F soft reset\n");
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10681033      assert_always(0, "TA grabber error A!\n");
10691034      break;
10701035   case TA_LIST_INIT:
1071      if(dat & 0x80000000)
1036      if(data & 0x80000000)
10721037      {
10731038         tafifo_pos=0;
10741039         tafifo_mask=7;
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11381103      break;
11391104//#define TA_YUV_TEX_BASE       ((0x005f8148-0x005f8000)/4)
11401105   case TA_YUV_TEX_BASE:
1141      printf("TA_YUV_TEX_BASE initialized to %08x\n", dat);
1106      printf("TA_YUV_TEX_BASE initialized to %08x\n", data);
11421107
11431108      // hack, this interrupt is generated after transfering a set amount of data
11441109      //state->state->dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_YUV;
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11461111
11471112      break;
11481113   case TA_YUV_TEX_CTRL:
1149      printf("TA_YUV_TEX_CTRL initialized to %08x\n", dat);
1114      printf("TA_YUV_TEX_CTRL initialized to %08x\n", data);
11501115      break;
11511116
11521117   case SPG_VBLANK_INT:
r23535r23536
11621127   #if DEBUG_PVRTA
11631128      mame_printf_verbose("List continuation processing\n");
11641129   #endif
1165      if(dat & 0x80000000)
1130      if(data & 0x80000000)
11661131      {
11671132         tafifo_listtype= -1; // no list being received
11681133         listtype_used |= (1+4);
r23535r23536
11881153   }
11891154
11901155   #if DEBUG_PVRTA_REGS
1191   if ((reg != 0x14) && (reg != 0x15))
1192      mame_printf_verbose("PVRTA: [%08x=%x] write %" I64FMT "x to %x (reg %x %x), mask %" I64FMT "x\n", 0x5f8000+reg*4, dat, data>>shift, offset, reg, (reg*4)+0x8000, mem_mask);
1156   if ((offset != 0x14) && (offset != 0x15))
1157      mame_printf_verbose("PVRTA: [%08x=%x] write %x to %x %x, mask %x\n", 0x5f8000+reg*4, data, offset, (reg*4)+0x8000, mem_mask);
11931158   #endif
11941159}
11951160
r23535r23536
25392504
25402505/* Naomi 2 attempts (TBD) */
25412506
2542READ64_MEMBER( powervr2_device::pvr2_ta_r )
2507READ32_MEMBER( powervr2_device::pvr2_ta_r )
25432508{
2544   int reg;
2545   UINT64 shift;
2509   printf("PVR2 %08x R\n", offset);
25462510
2547   reg = decode_reg_64(offset, mem_mask, &shift);
2548
2549   switch (reg)
2550   {
2551   }
2552
2553   printf("PVR2 %08x R\n",reg);
2554
25552511   return 0;
25562512}
25572513
2558WRITE64_MEMBER( powervr2_device::pvr2_ta_w )
2514WRITE32_MEMBER( powervr2_device::pvr2_ta_w )
25592515{
25602516//  int reg;
25612517//  UINT64 shift;
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26092565}
26102566
26112567
2612WRITE64_MEMBER( powervr2_device::pvrs_ta_w )
2568WRITE32_MEMBER( powervr2_device::pvrs_ta_w )
26132569{
26142570   pvr_ta_w(space,offset,data,mem_mask);
26152571   pvr2_ta_w(space,offset,data,mem_mask);
r23535r23536
26242580   state->dc_update_interrupt_status();
26252581}
26262582
2627READ64_MEMBER(powervr2_device::pvr_ctrl_r )
2583READ32_MEMBER(powervr2_device::pvr_ctrl_r)
26282584{
2629   int reg;
2630   UINT64 shift;
2631
2632   reg = decode_reg_64(offset, mem_mask, &shift);
2633
26342585   #if DEBUG_PVRCTRL
2635   mame_printf_verbose("PVRCTRL: [%08x] read %x @ %x (reg %x), mask %" I64FMT "x (PC=%x)\n", 0x5f7c00+reg*4, pvrctrl_regs[reg], offset, reg, mem_mask, space.device().safe_pc());
2586   mame_printf_verbose("PVRCTRL: [%08x] read %x @ %x, mask %x (PC=%x)\n", 0x5f7c00+reg*4, pvrctrl_regs[offset], offset, mem_mask, space.device().safe_pc());
26362587   #endif
26372588
2638   return (UINT64)pvrctrl_regs[reg] << shift;
2589   return (UINT64)pvrctrl_regs[offset];
26392590}
26402591
2641WRITE64_MEMBER(powervr2_device::pvr_ctrl_w )
2592WRITE32_MEMBER(powervr2_device::pvr_ctrl_w)
26422593{
2643   int reg;
2644   UINT64 shift;
2645   UINT32 dat;
26462594   UINT8 old;
26472595
2648   reg = decode_reg_64(offset, mem_mask, &shift);
2649   dat = (UINT32)(data >> shift);
2650
2651   switch (reg)
2596   switch (offset)
26522597   {
2653      case SB_PDSTAP: m_pvr_dma.pvr_addr = dat; break;
2654      case SB_PDSTAR: m_pvr_dma.sys_addr = dat; break;
2655      case SB_PDLEN: m_pvr_dma.size = dat; break;
2656      case SB_PDDIR: m_pvr_dma.dir = dat & 1; break;
2598      case SB_PDSTAP: m_pvr_dma.pvr_addr = data; break;
2599      case SB_PDSTAR: m_pvr_dma.sys_addr = data; break;
2600      case SB_PDLEN: m_pvr_dma.size = data; break;
2601      case SB_PDDIR: m_pvr_dma.dir = data & 1; break;
26572602      case SB_PDTSEL:
2658         m_pvr_dma.sel = dat & 1;
2603         m_pvr_dma.sel = data & 1;
26592604         //if(m_pvr_dma.sel & 1)
26602605         //  printf("Warning: Unsupported irq mode trigger PVR-DMA\n");
26612606         break;
2662      case SB_PDEN: m_pvr_dma.flag = dat & 1; break;
2607      case SB_PDEN: m_pvr_dma.flag = data & 1; break;
26632608      case SB_PDST:
26642609         old = m_pvr_dma.start & 1;
2665         m_pvr_dma.start = dat & 1;
2610         m_pvr_dma.start = data & 1;
26662611
26672612         if(((old & 1) == 0) && m_pvr_dma.flag && m_pvr_dma.start && ((m_pvr_dma.sel & 1) == 0)) // 0 -> 1
26682613            pvr_dma_execute(space);
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26702615   }
26712616
26722617   #if DEBUG_PVRCTRL
2673   mame_printf_verbose("PVRCTRL: [%08x=%x] write %" I64FMT "x to %x (reg %x), mask %" I64FMT "x\n", 0x5f7c00+reg*4, dat, data>>shift, offset, reg, mem_mask);
2618   mame_printf_verbose("PVRCTRL: [%08x=%x] write %x to %x (reg %x), mask %x\n", 0x5f7c00+reg*4, data, offset, mem_mask);
26742619   #endif
26752620
2676//  pvrctrl_regs[reg] |= dat;
2677   pvrctrl_regs[reg] = dat;
2621   pvrctrl_regs[offset] = data;
26782622}
26792623
26802624void powervr2_device::pvr_dma_execute(address_space &space)
trunk/src/mame/video/powervr2.h
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111111
112112   powervr2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
113113
114   DECLARE_READ64_MEMBER( pvr_ctrl_r );
115   DECLARE_WRITE64_MEMBER( pvr_ctrl_w );
116   DECLARE_READ64_MEMBER( pvr_ta_r );
117   DECLARE_WRITE64_MEMBER( pvr_ta_w );
118   DECLARE_READ64_MEMBER( pvr2_ta_r );
119   DECLARE_WRITE64_MEMBER( pvr2_ta_w );
120   DECLARE_READ64_MEMBER( pvrs_ta_r );
121   DECLARE_WRITE64_MEMBER( pvrs_ta_w );
114   DECLARE_READ32_MEMBER( pvr_ctrl_r );
115   DECLARE_WRITE32_MEMBER( pvr_ctrl_w );
116   DECLARE_READ32_MEMBER( pvr_ta_r );
117   DECLARE_WRITE32_MEMBER( pvr_ta_w );
118   DECLARE_READ32_MEMBER( pvr2_ta_r );
119   DECLARE_WRITE32_MEMBER( pvr2_ta_w );
120   DECLARE_READ32_MEMBER( pvrs_ta_r );
121   DECLARE_WRITE32_MEMBER( pvrs_ta_w );
122122   DECLARE_READ32_MEMBER( elan_regs_r );
123123   DECLARE_WRITE32_MEMBER( elan_regs_w );
124124   DECLARE_WRITE64_MEMBER( ta_fifo_poly_w );
trunk/src/mess/drivers/dccons.c
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118118   AM_RANGE(0x005f7000, 0x005f70ff) AM_READWRITE(dc_mess_gdrom_r, dc_mess_gdrom_w )
119119   AM_RANGE(0x005f7400, 0x005f74ff) AM_READWRITE(dc_mess_g1_ctrl_r, dc_mess_g1_ctrl_w )
120120   AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
121   AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w)
122   AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w )
121   AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff))
122   AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w, U64(0xffffffffffffffff))
123123   AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE(dc_modem_r, dc_modem_w )
124124   AM_RANGE(0x00700000, 0x00707fff) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
125125   AM_RANGE(0x00710000, 0x0071000f) AM_READWRITE(dc_rtc_r, dc_rtc_w )

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