trunk/src/emu/video/pc_vga.c
| r21195 | r21196 | |
|---|
| 2676 | 2676 | res = s3.reg_lock2; |
| 2677 | 2677 | break; |
| 2678 | 2678 | case 0x42: // CR42 Mode Control |
| 2679 | | res = 0x0d; // hardcode to non-interlace |
| 2679 | res = s3.cr42 & 0x0f; // bit 5 set if interlaced, leave it unset for now. |
| 2680 | 2680 | break; |
| 2681 | 2681 | case 0x45: |
| 2682 | 2682 | res = s3.cursor_mode; |
| r21195 | r21196 | |
|---|
| 2719 | 2719 | case 0x55: |
| 2720 | 2720 | res = s3.extended_dac_ctrl; |
| 2721 | 2721 | break; |
| 2722 | case 0x5c: |
| 2723 | // if VGA dot clock is set to 3 (misc reg bits 2-3), then selected dot clock is read, otherwise read VGA clock select |
| 2724 | if((vga.miscellaneous_output & 0xc) == 0x0c) |
| 2725 | res = s3.cr42 & 0x0f; |
| 2726 | else |
| 2727 | res = (vga.miscellaneous_output & 0xc) >> 2; |
| 2728 | break; |
| 2722 | 2729 | case 0x67: |
| 2723 | 2730 | res = s3.ext_misc_ctrl_2; |
| 2724 | 2731 | break; |
| r21195 | r21196 | |
|---|
| 2837 | 2844 | s3.memory_config = data; |
| 2838 | 2845 | vga.crtc.start_addr_latch &= ~0x30000; |
| 2839 | 2846 | vga.crtc.start_addr_latch |= ((data & 0x30) << 12); |
| 2840 | | //popmessage("%02x",data); |
| 2841 | 2847 | s3_define_video_mode(); |
| 2842 | 2848 | break; |
| 2843 | 2849 | case 0x35: |
| r21195 | r21196 | |
|---|
| 2987 | 2993 | vga.crtc.start_addr_latch &= ~0xc0000; |
| 2988 | 2994 | vga.crtc.start_addr_latch |= ((data & 0x3) << 18); |
| 2989 | 2995 | svga.bank_w = (svga.bank_w & 0xcf) | ((data & 0x0c) << 2); |
| 2990 | | svga.bank_r = svga.bank_r; |
| 2996 | svga.bank_r = svga.bank_w; |
| 2991 | 2997 | s3_define_video_mode(); |
| 2992 | 2998 | break; |
| 2993 | 2999 | case 0x53: |
| r21195 | r21196 | |
|---|
| 3042 | 3048 | vga.crtc.horz_total = (vga.crtc.horz_total & 0xfeff) | ((data & 0x01) << 8); |
| 3043 | 3049 | vga.crtc.horz_disp_end = (vga.crtc.horz_disp_end & 0xfeff) | ((data & 0x02) << 7); |
| 3044 | 3050 | vga.crtc.horz_blank_start = (vga.crtc.horz_blank_start & 0xfeff) | ((data & 0x04) << 6); |
| 3051 | vga.crtc.horz_blank_end = (vga.crtc.horz_blank_end & 0xffbf) | ((data & 0x08) << 3); |
| 3045 | 3052 | vga.crtc.horz_retrace_start = (vga.crtc.horz_retrace_start & 0xfeff) | ((data & 0x10) << 4); |
| 3053 | vga.crtc.horz_retrace_end = (vga.crtc.horz_retrace_end & 0xffdf) | (data & 0x20); |
| 3046 | 3054 | s3_define_video_mode(); |
| 3047 | 3055 | break; |
| 3048 | 3056 | /* |