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r21195 Tuesday 19th February, 2013 at 23:32:12 UTC by David Haywood
improve palette stuff + notes
[src/mame/drivers]coolridr.c

trunk/src/mame/drivers/coolridr.c
r21194r21195
323323   UINT8 m_vblank;
324324   int m_scsp_last_line;
325325   UINT8 an_mux_data;
326   UINT8 sound_data;
327326
327
328328   DECLARE_READ32_MEMBER(sysh1_unk_r);
329329   DECLARE_WRITE32_MEMBER(sysh1_unk_w);
330330   DECLARE_READ32_MEMBER(sysh1_ioga_r);
r21194r21195
342342   DECLARE_READ8_MEMBER(analog_mux_r);
343343   DECLARE_WRITE8_MEMBER(analog_mux_w);
344344   DECLARE_WRITE8_MEMBER(lamps_w);
345   DECLARE_WRITE8_MEMBER(sound_to_sh1_w);
346345   DECLARE_WRITE_LINE_MEMBER(scsp_to_main_irq);
347346   DECLARE_DRIVER_INIT(coolridr);
348347   virtual void machine_start();
r21194r21195
383382   if (which==1)
384383   {
385384      count += 0x20000/4;
386      color += 0x5e;
385//      color += 0x5e;
386      color += 2;
387387   }
388388   else
389389   {
390      color += 0x4e;
390//      color += 0x4e;
391//      color += 0x0;
392
391393   }
392394
393395   for (y=0;y<64;y++)
r21194r21195
467469/* unknown purpose */
468470READ32_MEMBER(coolridr_state::sysh1_unk_r)
469471{
470   if(offset == 8)
471      return sound_data;
472
473   if(offset != 2)
474      printf("%08x\n",offset);
475
476472   return m_h1_unk[offset];
477473}
478474
479475WRITE32_MEMBER(coolridr_state::sysh1_unk_w)
480476{
481   if(offset != 8) // 8 = sound irq ack?
482      printf("%08x %08x\n",offset,data);
483
484477   COMBINE_DATA(&m_h1_unk[offset]);
485478}
486479
r21194r21195
776769}
777770
778771
772// NOTE, this gets called from the blitter code above AND the DMA code below.. addresses from each are probably wrong
779773WRITE32_MEMBER(coolridr_state::sysh1_pal_w)
780774{
781775   int r,g,b;
776   COMBINE_DATA(&m_generic_paletteram_32[offset]);
782777
783   r = ((data & 0x00007c00) >> 10);
784   g = ((data & 0x000003e0) >> 5);
785   b = ((data & 0x0000001f) >> 0);
778   r = ((m_generic_paletteram_32[offset] & 0x00007c00) >> 10);
779   g = ((m_generic_paletteram_32[offset] & 0x000003e0) >> 5);
780   b = ((m_generic_paletteram_32[offset] & 0x0000001f) >> 0);
786781   palette_set_color_rgb(machine(),(offset*2)+1,pal5bit(r),pal5bit(g),pal5bit(b));
787   r = ((data & 0x7c000000) >> 26);
788   g = ((data & 0x03e00000) >> 21);
789   b = ((data & 0x001f0000) >> 16);
782   r = ((m_generic_paletteram_32[offset] & 0x7c000000) >> 26);
783   g = ((m_generic_paletteram_32[offset] & 0x03e00000) >> 21);
784   b = ((m_generic_paletteram_32[offset] & 0x001f0000) >> 16);
790785   palette_set_color_rgb(machine(),offset*2,pal5bit(r),pal5bit(g),pal5bit(b));
791786}
792787
r21194r21195
841836
842837         dst |= 0x3c00000; //to paletteram FIXME: unknown offset
843838         //size/=2;
839
840         // this is used when transfering palettes written by the blitter? maybe?
841         //  it might be a better indication of where blitter command 0xe0 should REALLY write data (at 0x3e00000)...
844842         if((src & 0xff00000) == 0x3e00000)
845            return; //FIXME: kludge to avoid palette corruption
843         {
844            src &= 0xfffff;
845            src |= 0x3c00000;
846         }
847         //   return; //FIXME: kludge to avoid palette corruption
846848         //debugger_break(space.machine());
847849      }
848850
r21194r21195
900902   AM_RANGE(0x01000000, 0x01ffffff) AM_ROM AM_REGION("gfx_data",0x0000000)
901903
902904   AM_RANGE(0x03000000, 0x030fffff) AM_RAM AM_SHARE("h1_vram")//bg vram
903   AM_RANGE(0x03c00000, 0x03c0ffff) AM_RAM AM_SHARE("paletteram2") // palettes get written here, but the actual used ones seem to get sent via blitter??
905   AM_RANGE(0x03c00000, 0x03c0ffff) AM_RAM_WRITE(sysh1_pal_w) AM_SHARE("paletteram") // palettes get written here, but the actual used ones seem to get sent via blitter??
904906   AM_RANGE(0x03d00000, 0x03dfffff) AM_RAM_WRITE(sysh1_char_w) AM_SHARE("h1_charram") //FIXME: half size
905907   AM_RANGE(0x03e00000, 0x03efffff) AM_RAM_WRITE(sysh1_dma_w) AM_SHARE("fb_vram") //FIXME: not all of it
906908
r21194r21195
970972   AM_RANGE(0x03200000, 0x0327ffff) AM_READWRITE16(h1_soundram2_r, h1_soundram2_w,0xffffffff) //AM_SHARE("soundram2")
971973   AM_RANGE(0x03300000, 0x03300fff) AM_DEVREADWRITE16_LEGACY("scsp2", scsp_r, scsp_w, 0xffffffff)
972974
973//   AM_RANGE(0x04000000, 0x0400001f) AM_DEVREADWRITE8("i8237", am9517a_device, read, write, 0xffffffff)
974   AM_RANGE(0x04000000, 0x0400003f) AM_READWRITE(sysh1_unk_r,sysh1_unk_w) AM_SHARE("h1_unk")
975//   AM_RANGE(0x04200000, 0x0420003f) AM_RAM
975   AM_RANGE(0x04000000, 0x0400001f) AM_DEVREADWRITE8("i8237", am9517a_device, read, write, 0xffffffff)
976   AM_RANGE(0x04000020, 0x0400003f) AM_READWRITE(sysh1_unk_r,sysh1_unk_w) AM_SHARE("h1_unk")
977   AM_RANGE(0x04200000, 0x0420003f) AM_RAM /* hi-word for DMA? */
976978
977979   AM_RANGE(0x05000000, 0x05000fff) AM_RAM
978980   AM_RANGE(0x05200000, 0x052001ff) AM_RAM
r21194r21195
993995   AM_RANGE(0x60000000, 0x600003ff) AM_WRITENOP
994996ADDRESS_MAP_END
995997
996WRITE8_MEMBER( coolridr_state::sound_to_sh1_w)
997{
998   sound_data = data;
999}
1000
998// SH-1 or SH-2 almost certainly copies the program down to here: the ROM containing the program is 32-bit wide and the 68000 is 16-bit
999// the SCSP is believed to be hardcoded to decode the first 4 MB like this for a master/slave config
1000// (see also Model 3):
10011001static ADDRESS_MAP_START( system_h1_sound_map, AS_PROGRAM, 16, coolridr_state )
10021002   AM_RANGE(0x000000, 0x07ffff) AM_RAM AM_REGION("scsp1",0) AM_SHARE("soundram")
10031003   AM_RANGE(0x100000, 0x100fff) AM_DEVREADWRITE_LEGACY("scsp1", scsp_r, scsp_w)
10041004   AM_RANGE(0x200000, 0x27ffff) AM_RAM AM_REGION("scsp2",0) AM_SHARE("soundram2")
10051005   AM_RANGE(0x300000, 0x300fff) AM_DEVREADWRITE_LEGACY("scsp2", scsp_r, scsp_w)
10061006   AM_RANGE(0x800000, 0x80ffff) AM_RAM
1007   AM_RANGE(0x900000, 0x900001) AM_WRITE8(sound_to_sh1_w,0x00ff)
1007   AM_RANGE(0x900000, 0x900001) AM_WRITENOP
10081008ADDRESS_MAP_END
10091009
10101010
r21194r21195
14691469static const scsp_interface scsp2_interface =
14701470{
14711471   0,
1472   NULL,
1473   DEVCB_DRIVER_LINE_MEMBER(coolridr_state, scsp_to_main_irq)
1472   NULL
14741473};
14751474
14761475#define MAIN_CLOCK XTAL_28_63636MHz

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