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r17797 Tuesday 11th September, 2012 at 15:16:43 UTC by Aaron Giles
Don't use safe_pc[base] when you already have a resolved device_state_interface. Added redundant methods to device_state_interface to generate errors when this is done.

[src/emu]	distate.h
[src/emu/cpu/m6502]	opsce02.h
[src/emu/cpu/tlcs90]	tlcs90.c
[src/emu/cpu/tms34010]	34010gfx.c
[src/mame/drivers]	cyclemb.c eolithsp.c
[src/mess/audio]	mea8000.c
[src/mess/devices]	sonydriv.c
[src/mess/drivers]	camplynx.c cxhumax.c gp2x.c next.c pasogo.c pasopia7.c vboy.c
[src/mess/machine]	apple2.c coco.c compis.c gamecom.c isa_hdc.c mac.c macpci.c mc6843.c mc6846.c mc6854.c mos6530.c ncr5380.c pokemini.c
[src/mess/video]	crtc_ega.c

trunk/src/mame/drivers/eolithsp.c

r17796	r17797
117	117	// StealSee doesn't use interrupts, just the vblank
118	118	CUSTOM_INPUT_MEMBER(eolith_state::stealsee_speedup_getvblank)
119	119	{
120		int pc = m_maincpu->safe_pc();
	120	int pc = m_maincpu->pc();
121	121
122	122	if (pc==0x400081ec)
123	123	if(!eolith_vblank)

trunk/src/mame/drivers/cyclemb.c

r17796	r17797
430	430	//printf("%04x\n",m_maincpu->safe_pc());
431	431
432	432	/* TODO: internal state of this */
433		if(m_maincpu->safe_pc() == m_dsw_pc_hack)
	433	if(m_maincpu->pc() == m_dsw_pc_hack)
434	434	m_mcu[0].rxd = (ioport("DSW1")->read() & 0x1f) << 2;
435	435	else if(m_mcu[0].rst)
436	436	{

trunk/src/emu/cpu/tms34010/34010gfx.c

r17796	r17797
84	84	int diff, cycles = 3;
85	85
86	86	if (WINDOW_CHECKING(tms) == 2)
87		logerror("%08x: %s apply_window window mode %d not supported!\n", tms->device->safe_pc(), inst_name, WINDOW_CHECKING(tms));
	87	logerror("%08x: %s apply_window window mode %d not supported!\n", tms->device->pc(), inst_name, WINDOW_CHECKING(tms));
88	88
89	89	CLR_V(tms);
90	90	if (WINDOW_CHECKING(tms) == 1)

trunk/src/emu/cpu/tlcs90/tlcs90.c

r17796	r17797
1967	1967	break;
1968	1968
1969	1969	default:
1970		fatalerror("%04x: unimplemented opcode, op=%02x\n",device->safe_pc(),cpustate->op);
	1970	fatalerror("%04x: unimplemented opcode, op=%02x\n",device->pc(),cpustate->op);
1971	1971	}
1972	1972
1973	1973	if ( cpustate->op != EI )

trunk/src/emu/cpu/m6502/opsce02.h

r17796	r17797
291	291	t1=RDOPARG();                           \
292	292	t2=RDOPARG();                           \
293	293	t3=RDOPARG();                           \
294		logerror("m65ce02 at pc:%.4x reserved op aug %.2x %.2x %.2x\n", cpustate->device->safe_pc(),t1,t2,t3);
	294	logerror("m65ce02 at pc:%.4x reserved op aug %.2x %.2x %.2x\n", cpustate->device->pc(),t1,t2,t3);
295	295
296	296	/* 65ce02 ******************************************************
297	297	*  BBR Branch if bit is reset

trunk/src/emu/distate.h

r17796	r17797
162	162	// state setters
163	163	void set_state(int index, UINT64 value);
164	164	void set_state_string(int index, const char *string);
	165
	166	// deliberately ambiguous functions; if you have the state interface
	167	// just use pc() and pcbase() directly
	168	offs_t safe_pc() { return pc(); }
	169	offs_t safe_pcbase() { return pcbase(); }
165	170
166	171	public:   // protected eventually
167	172

trunk/src/mess/devices/sonydriv.c

r17796	r17797
271	271	if (LOG_SONY_EXTRA)
272	272	{
273	273	printf("sony.status(): action=%x pc=0x%08x%s\n",
274		action, (int) device->machine().firstcpu->safe_pc(), sony.floppy_enable ? "" : " (no drive enabled)");
	274	action, (int) device->machine().firstcpu->pc(), sony.floppy_enable ? "" : " (no drive enabled)");
275	275	}
276	276
277	277	if ((! sony_enable2()) && sony.floppy_enable)
r17796	r17797
333	333	}
334	334	break;
335	335	case 0x0a:   /* At track 0: 0=track zero 1=not track zero */
336		logerror("sony.status(): reading Track 0 pc=0x%08x\n", (int) device->machine().firstcpu->safe_pc());
	336	logerror("sony.status(): reading Track 0 pc=0x%08x\n", (int) device->machine().firstcpu->pc());
337	337	if (cur_image)
338	338	result = floppy_tk00_r(&cur_image->device());
339	339	else
r17796	r17797
407	407	if (LOG_SONY)
408	408	{
409	409	logerror("sony_doaction(): action=%d pc=0x%08x%s\n",
410		action, (int) device->machine().firstcpu->safe_pc(), (sony.floppy_enable) ? "" : " (MOTOR OFF)");
	410	action, (int) device->machine().firstcpu->pc(), (sony.floppy_enable) ? "" : " (MOTOR OFF)");
411	411	}
412	412
413	413	if (sony.floppy_enable)

trunk/src/mess/audio/mea8000.c

r17796	r17797
556	556	case 1:
557	557	/* ready to accept next frame */
558	558	#if 0
559		LOG(( "$%04x %f: mea8000_r ready=%i\n", device->machine().firstcpu ->safe_pcbase( ), machine.time().as_double(), mea8000_accept_byte( mea8000 ) ));
	559	LOG(( "$%04x %f: mea8000_r ready=%i\n", device->machine().firstcpu->pcbase( ), machine.time().as_double(), mea8000_accept_byte( mea8000 ) ));
560	560	#endif
561	561	return mea8000_accept_byte(mea8000) << 7;
562	562
563	563	default:
564		logerror( "$%04x mea8000_r invalid read offset %i\n",  device->machine().firstcpu ->safe_pcbase( ), offset );
	564	logerror( "$%04x mea8000_r invalid read offset %i\n",  device->machine().firstcpu->pcbase( ), offset );
565	565	}
566	566	return 0;
567	567	}
r17796	r17797
577	577	{
578	578	/* got pitch byte before first frame */
579	579	mea8000->pitch = 2 * data;
580		LOG(( "$%04x %f: mea8000_w pitch %i\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), mea8000->pitch ));
	580	LOG(( "$%04x %f: mea8000_w pitch %i\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), mea8000->pitch ));
581	581	mea8000->state = MEA8000_WAIT_FIRST;
582	582	mea8000->bufpos = 0;
583	583	}
584	584	else if (mea8000->bufpos == 4)
585	585	{
586	586	/* overflow */
587		LOG(( "$%04x %f: mea8000_w data overflow %02X\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), data ));
	587	LOG(( "$%04x %f: mea8000_w data overflow %02X\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), data ));
588	588	}
589	589	else
590	590	{
591	591	/* enqueue frame byte */
592		LOG(( "$%04x %f: mea8000_w data %02X in frame pos %i\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(),
	592	LOG(( "$%04x %f: mea8000_w data %02X in frame pos %i\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(),
593	593	data, mea8000->bufpos ));
594	594	mea8000->buf[mea8000->bufpos] = data;
595	595	mea8000->bufpos++;
r17796	r17797
623	623	mea8000_stop_frame(device->machine(), mea8000);
624	624
625	625	LOG(( "$%04x %f: mea8000_w command %02X stop=%i cont=%i roe=%i\n",
626		device->machine().firstcpu->safe_pcbase(), device->machine().time().as_double(), data,
	626	device->machine().firstcpu->pcbase(), device->machine().time().as_double(), data,
627	627	stop, mea8000->cont, mea8000->roe ));
628	628
629	629	mea8000_update_req(device);
r17796	r17797
631	631	}
632	632
633	633	default:
634		logerror( "$%04x mea8000_w invalid write offset %i\n", device->machine().firstcpu ->safe_pcbase( ), offset );
	634	logerror( "$%04x mea8000_w invalid write offset %i\n", device->machine().firstcpu->pcbase( ), offset );
635	635	}
636	636	}
637	637

trunk/src/mess/machine/pokemini.c

r17796	r17797
409	409	case 0x02:   /* CPU related?
410	410	Bit 0-7 R/W Unknown
411	411	*/
412		logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu ->safe_pc( ), offset, data );
	412	logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu->pc( ), offset, data );
413	413	break;
414	414	case 0x08:   /* Seconds-timer control
415	415	Bit 0   R/W Timer enable
r17796	r17797
441	441	Bit 5   R   Battery status: 0 - battery OK, 1 - battery low
442	442	Bit 6-7     Unused
443	443	*/
444		logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu ->safe_pc( ), offset, data );
	444	logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu->pc( ), offset, data );
445	445	break;
446	446	case 0x18:   /* Timer 1 pre-scale + enable
447	447	Bit 0-2 R/W low timer 1 prescaler select
r17796	r17797
956	956	*/
957	957	case 0x35:   /* Timer 1 sound-pivot (high, unused)
958	958	*/
959		logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu ->safe_pc( ), offset, data );
	959	logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu->pc( ), offset, data );
960	960	break;
961	961	case 0x36:   /* Timer 1 counter (low), read only
962	962	*/
r17796	r17797
1035	1035	*/
1036	1036	case 0x3D:   /* Timer 2 sound-pivot (high, unused)
1037	1037	*/
1038		logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu ->safe_pc( ), offset, data );
	1038	logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu->pc( ), offset, data );
1039	1039	break;
1040	1040	case 0x3E:   /* Timer 2 counter (low), read only
1041	1041	Bit 0-7 R/W Timer 2 counter value bit 0-7
r17796	r17797
1300	1300	Map size 2: 0x00 to 0x60
1301	1301	Bit 7       Unused
1302	1302	*/
1303		logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu ->safe_pc( ), offset, data );
	1303	logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu->pc( ), offset, data );
1304	1304	break;
1305	1305	case 0x87:   /* Sprite tile data memory offset (low)
1306	1306	Bit 0-5     Always "0"
r17796	r17797
1341	1341	//      lcd_data_w( data );
1342	1342	break;
1343	1343	default:
1344		logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu ->safe_pc( ), offset, data );
	1344	logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu->pc( ), offset, data );
1345	1345	break;
1346	1346	}
1347	1347	state->m_pm_reg[offset] = data;

trunk/src/mess/machine/mos6530.c

r17796	r17797
227	227	if (!port->out_port_func.isnull())
228	228	port->out_port_func(0, data);
229	229	else
230		logerror("6530MIOT chip %s: Port %c is being written to but has no handler.  PC: %08X - %02X\n", device->tag(), 'A' + (offset & 1), device->machine().firstcpu->safe_pc(), data);
	230	logerror("6530MIOT chip %s: Port %c is being written to but has no handler.  PC: %08X - %02X\n", device->tag(), 'A' + (offset & 1), device->machine().firstcpu->pc(), data);
231	231	}
232	232	}
233	233	}
r17796	r17797
289	289	port->in = port->in_port_func(0);
290	290	}
291	291	else
292		logerror("6530MIOT chip %s: Port %c is being read but has no handler.  PC: %08X\n", device->tag(), 'A' + (offset & 1), device->machine().firstcpu->safe_pc());
	292	logerror("6530MIOT chip %s: Port %c is being read but has no handler.  PC: %08X\n", device->tag(), 'A' + (offset & 1), device->machine().firstcpu->pc());
293	293
294	294	/* apply the DDR to the result */
295	295	val = (out & port->ddr) | (port->in & ~port->ddr);

trunk/src/mess/machine/mc6854.c

r17796	r17797
808	808	case 0: /* status register 1 */
809	809	mc6854_update_sr1( mc6854 );
810	810	LOG(( "%f $%04x mc6854_r: get SR1=$%02X (rda=%i,s2rq=%i,fd=%i,cts=%i,tu=%i,tdra=%i,irq=%i)\n",
811		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6854->sr1,
	811	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6854->sr1,
812	812	( mc6854->sr1 & RDA) ? 1 : 0, ( mc6854->sr1 & S2RQ) ? 1 : 0,
813	813	( mc6854->sr1 & FD ) ? 1 : 0, ( mc6854->sr1 & CTS ) ? 1 : 0,
814	814	( mc6854->sr1 & TU ) ? 1 : 0, ( mc6854->sr1 & TDRA) ? 1 : 0,
r17796	r17797
818	818	case 1: /* status register 2 */
819	819	mc6854_update_sr2( mc6854 );
820	820	LOG(( "%f $%04x mc6854_r: get SR2=$%02X (ap=%i,fv=%i,ridle=%i,rabt=%i,err=%i,dcd=%i,ovrn=%i,rda2=%i)\n",
821		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6854->sr2,
	821	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6854->sr2,
822	822	( mc6854->sr2 & AP   ) ? 1 : 0, ( mc6854->sr2 & FV  ) ? 1 : 0,
823	823	( mc6854->sr2 & RIDLE) ? 1 : 0, ( mc6854->sr2 & RABT) ? 1 : 0,
824	824	( mc6854->sr2 & ERR  ) ? 1 : 0, ( mc6854->sr2 & DCD ) ? 1 : 0,
r17796	r17797
830	830	{
831	831	UINT8 data = mc6854_rfifo_pop( device );
832	832	LOG(( "%f $%04x mc6854_r: get data $%02X\n",
833		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data ));
	833	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data ));
834	834	return data;
835	835	}
836	836
837	837	default:
838		logerror( "$%04x mc6854 invalid read offset %i\n", device->machine().firstcpu ->safe_pcbase( ), offset );
	838	logerror( "$%04x mc6854 invalid read offset %i\n", device->machine().firstcpu->pcbase( ), offset );
839	839	}
840	840	return 0;
841	841	}
r17796	r17797
851	851	case 0: /* control register 1 */
852	852	mc6854->cr1 = data;
853	853	LOG(( "%f $%04x mc6854_w: set CR1=$%02X (ac=%i,irq=%c%c,%sreset=%c%c)\n",
854		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6854->cr1,
	854	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6854->cr1,
855	855	AC ? 1 : 0,
856	856	RIE ? 'r' : '-', TIE ? 't' : '-',
857	857	DISCONTINUE ? "discontinue," : "",
r17796	r17797
859	859	));
860	860	if ( mc6854->cr1 & 0xc )
861	861	logerror( "$%04x mc6854 DMA not handled (CR1=$%02X)\n",
862		device->machine().firstcpu ->safe_pcbase( ), mc6854->cr1 );
	862	device->machine().firstcpu->pcbase( ), mc6854->cr1 );
863	863	if ( DISCONTINUE )
864	864	{
865	865	/* abort receive FIFO but keeps shift register & synchro */
r17796	r17797
888	888	/* control register 3 */
889	889	mc6854->cr3 = data;
890	890	LOG(( "%f $%04x mc6854_w: set CR3=$%02X (lcf=%i,aex=%i,idl=%i,fdse=%i,loop=%i,tst=%i,dtr=%i)\n",
891		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6854->cr3,
	891	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6854->cr3,
892	892	LCF ? (CEX ? 16 : 8) : 0,  AEX ? 1 : 0,
893	893	IDL0 ? 0 : 1, FDSE ? 1 : 0, LOOP ? 1 : 0,
894	894	TST ? 1 : 0, DTR ? 1 : 0
895	895	));
896	896	if ( LOOP )
897		logerror( "$%04x mc6854 loop mode not handled (CR3=$%02X)\n", device->machine().firstcpu ->safe_pcbase( ), mc6854->cr3 );
	897	logerror( "$%04x mc6854 loop mode not handled (CR3=$%02X)\n", device->machine().firstcpu->pcbase( ), mc6854->cr3 );
898	898	if ( TST )
899		logerror( "$%04x mc6854 test mode not handled (CR3=$%02X)\n", device->machine().firstcpu ->safe_pcbase( ), mc6854->cr3 );
	899	logerror( "$%04x mc6854 test mode not handled (CR3=$%02X)\n", device->machine().firstcpu->pcbase( ), mc6854->cr3 );
900	900
901	901	mc6854->out_dtr_func( DTR ? 1 : 0 );
902	902
r17796	r17797
906	906	/* control register 2 */
907	907	mc6854->cr2 = data;
908	908	LOG(( "%f $%04x mc6854_w: set CR2=$%02X (pse=%i,bytes=%i,fmidle=%i,%s,tlast=%i,clr=%c%c,rts=%i)\n",
909		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6854->cr2,
	909	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6854->cr2,
910	910	PSE ? 1 : 0,  TWOBYTES ? 2 : 1,  FMIDLE ? 1 : 0,
911	911	FCTDRA ? "fc" : "tdra", TLAST ? 1 : 0,
912	912	data & 0x20 ? 'r' : '-',  data & 0x40 ? 't' : '-',
913	913	RTS ? 1 : 0 ));
914	914	if ( PSE )
915		logerror( "$%04x mc6854 status prioritization not handled (CR2=$%02X)\n", device->machine().firstcpu ->safe_pcbase( ), mc6854->cr2 );
	915	logerror( "$%04x mc6854 status prioritization not handled (CR2=$%02X)\n", device->machine().firstcpu->pcbase( ), mc6854->cr2 );
916	916	if ( TLAST )
917	917	mc6854_tfifo_terminate( device );
918	918	if ( data & 0x20 )
r17796	r17797
936	936	break;
937	937
938	938	case 2: /* transmitter data: continue data */
939		LOG(( "%f $%04xmc6854_w: push data=$%02X\n", device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data ));
	939	LOG(( "%f $%04xmc6854_w: push data=$%02X\n", device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data ));
940	940	mc6854_tfifo_push( device, data );
941	941	break;
942	942
r17796	r17797
945	945	{
946	946	/* control register 4 */
947	947	mc6854->cr4 = data;
948		LOG(( "%f $%04x mc6854_w: set CR4=$%02X (interframe=%i,tlen=%i,rlen=%i,%s%s)\n", device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6854->cr4,
	948	LOG(( "%f $%04x mc6854_w: set CR4=$%02X (interframe=%i,tlen=%i,rlen=%i,%s%s)\n", device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6854->cr4,
949	949	TWOINTER ? 2 : 1,
950	950	TWL, RWL,
951	951	ABT ? ( ABTEX ? "abort-ext," : "abort,") : "",
r17796	r17797
960	960	else
961	961	{
962	962	/* transmitter data: last data */
963		LOG(( "%f $%04x mc6854_w: push last-data=$%02X\n", device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data ));
	963	LOG(( "%f $%04x mc6854_w: push last-data=$%02X\n", device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data ));
964	964	mc6854_tfifo_push( device, data );
965	965	mc6854_tfifo_terminate( device );
966	966	}
967	967	break;
968	968
969	969	default:
970		logerror( "$%04x mc6854 invalid write offset %i (data=$%02X)\n", device->machine().firstcpu ->safe_pcbase( ), offset, data );
	970	logerror( "$%04x mc6854 invalid write offset %i (data=$%02X)\n", device->machine().firstcpu->pcbase( ), offset, data );
971	971	}
972	972	}
973	973

trunk/src/mess/machine/gamecom.c

r17796	r17797
329	329	case SM8521_55: case SM8521_56: case SM8521_57: case SM8521_58:
330	330	case SM8521_59: case SM8521_5A: case SM8521_5B: case SM8521_5C:
331	331	case SM8521_5D:
332		logerror( "%X: Write to reserved address (0x%02X). Value written: 0x%02X\n", m_maincpu->safe_pc(), offset, data );
	332	logerror( "%X: Write to reserved address (0x%02X). Value written: 0x%02X\n", m_maincpu->pc(), offset, data );
333	333	break;
334	334	}
335	335	m_p_ram[offset] = data;

trunk/src/mess/machine/mc6846.c

r17796	r17797
267	267	case 0:
268	268	case 4:
269	269	LOG (( "$%04x %f: mc6846 CSR read $%02X intr=%i (timer=%i, cp1=%i, cp2=%i)\n",
270		device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(),
	270	device->machine().firstcpu->pcbase( ), device->machine().time().as_double(),
271	271	mc6846->csr, (mc6846->csr >> 7) & 1,
272	272	mc6846->csr & 1, (mc6846->csr >> 1) & 1, (mc6846->csr >> 2) & 1 ));
273	273	mc6846->csr0_to_be_cleared = mc6846->csr & 1;
r17796	r17797
276	276	return mc6846->csr;
277	277
278	278	case 1:
279		LOG (( "$%04x %f: mc6846 PCR read $%02X\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), mc6846->pcr ));
	279	LOG (( "$%04x %f: mc6846 PCR read $%02X\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), mc6846->pcr ));
280	280	return mc6846->pcr;
281	281
282	282	case 2:
283		LOG (( "$%04x %f: mc6846 DDR read $%02X\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), mc6846->ddr ));
	283	LOG (( "$%04x %f: mc6846 DDR read $%02X\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), mc6846->ddr ));
284	284	return mc6846->ddr;
285	285
286	286	case 3:
287		LOG (( "$%04x %f: mc6846 PORT read $%02X\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), PORT ));
	287	LOG (( "$%04x %f: mc6846 PORT read $%02X\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), PORT ));
288	288	if ( ! (mc6846->pcr & 0x80) )
289	289	{
290	290	if ( mc6846->csr1_to_be_cleared )
r17796	r17797
298	298	return PORT;
299	299
300	300	case 5:
301		LOG (( "$%04x %f: mc6846 TCR read $%02X\n",device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), mc6846->tcr ));
	301	LOG (( "$%04x %f: mc6846 TCR read $%02X\n",device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), mc6846->tcr ));
302	302	return mc6846->tcr;
303	303
304	304	case 6:
305		LOG (( "$%04x %f: mc6846 COUNTER hi read $%02X\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), mc6846_counter( device ) >> 8 ));
	305	LOG (( "$%04x %f: mc6846 COUNTER hi read $%02X\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), mc6846_counter( device ) >> 8 ));
306	306	if ( mc6846->csr0_to_be_cleared )
307	307	{
308	308	mc6846->csr &= ~1;
r17796	r17797
312	312	return mc6846_counter( device ) >> 8;
313	313
314	314	case 7:
315		LOG (( "$%04x %f: mc6846 COUNTER low read $%02X\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), mc6846_counter( device ) & 0xff ));
	315	LOG (( "$%04x %f: mc6846 COUNTER low read $%02X\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), mc6846_counter( device ) & 0xff ));
316	316	if ( mc6846->csr0_to_be_cleared )
317	317	{
318	318	mc6846->csr &= ~1;
r17796	r17797
322	322	return mc6846_counter( device ) & 0xff;
323	323
324	324	default:
325		logerror( "$%04x mc6846 invalid read offset %i\n", device->machine().firstcpu ->safe_pcbase( ), offset );
	325	logerror( "$%04x mc6846 invalid read offset %i\n", device->machine().firstcpu->pcbase( ), offset );
326	326	}
327	327	return 0;
328	328	}
r17796	r17797
353	353	"latcged,pos-edge", "latcged,pos-edge,intr"
354	354	};
355	355	LOG (( "$%04x %f: mc6846 PCR write $%02X reset=%i cp2=%s cp1=%s\n",
356		device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), data,
	356	device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), data,
357	357	(data >> 7) & 1, cp2[ (data >> 3) & 7 ], cp1[ data & 7 ] ));
358	358
359	359	}
r17796	r17797
366	366	mc6846_update_irq( device );
367	367	}
368	368	if ( data & 4 )
369		logerror( "$%04x mc6846 CP1 latching not implemented\n", device->machine().firstcpu ->safe_pcbase( ) );
	369	logerror( "$%04x mc6846 CP1 latching not implemented\n", device->machine().firstcpu->pcbase( ) );
370	370	if (data & 0x20)
371	371	{
372	372	if (data & 0x10)
r17796	r17797
376	376	mc6846->iface->out_cp2_func( device, 0, mc6846->cp2_cpu );
377	377	}
378	378	else
379		logerror( "$%04x mc6846 acknowledge not implemented\n", device->machine().firstcpu ->safe_pcbase( ) );
	379	logerror( "$%04x mc6846 acknowledge not implemented\n", device->machine().firstcpu->pcbase( ) );
380	380	}
381	381	break;
382	382
383	383	case 2:
384		LOG (( "$%04x %f: mc6846 DDR write $%02X\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), data ));
	384	LOG (( "$%04x %f: mc6846 DDR write $%02X\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), data ));
385	385	if ( ! (mc6846->pcr & 0x80) )
386	386	{
387	387	mc6846->ddr = data;
r17796	r17797
391	391	break;
392	392
393	393	case 3:
394		LOG (( "$%04x %f: mc6846 PORT write $%02X (mask=$%02X)\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), data,mc6846->ddr ));
	394	LOG (( "$%04x %f: mc6846 PORT write $%02X (mask=$%02X)\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), data,mc6846->ddr ));
395	395	if ( ! (mc6846->pcr & 0x80) )
396	396	{
397	397	mc6846->pdr = data;
r17796	r17797
400	400	if ( mc6846->csr1_to_be_cleared && (mc6846->csr & 2) )
401	401	{
402	402	mc6846->csr &= ~2;
403		LOG (( "$%04x %f: mc6846 CP1 intr reset\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double() ));
	403	LOG (( "$%04x %f: mc6846 CP1 intr reset\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double() ));
404	404	}
405	405	if ( mc6846->csr2_to_be_cleared && (mc6846->csr & 4) )
406	406	{
407	407	mc6846->csr &= ~4;
408		LOG (( "$%04x %f: mc6846 CP2 intr reset\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double() ));
	408	LOG (( "$%04x %f: mc6846 CP2 intr reset\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double() ));
409	409	}
410	410	mc6846->csr1_to_be_cleared = 0;
411	411	mc6846->csr2_to_be_cleared = 0;
r17796	r17797
421	421	"freq-cmp", "freq-cmp", "pulse-cmp", "pulse-cmp"
422	422	};
423	423	LOG (( "$%04x %f: mc6846 TCR write $%02X reset=%i clock=%s scale=%i mode=%s out=%s\n",
424		device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), data,
	424	device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), data,
425	425	(data >> 7) & 1, (data & 0x40) ? "extern" : "sys",
426	426	(data & 0x40) ? 1 : 8, mode[ (data >> 1) & 7 ],
427	427	(data & 1) ? "enabled" : "0" ));
r17796	r17797
455	455
456	456	case 7:
457	457	mc6846->latch = ( ((UINT16) mc6846->time_MSB) << 8 ) + data;
458		LOG (( "$%04x %f: mc6846 COUNT write %i\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), mc6846->latch  ));
	458	LOG (( "$%04x %f: mc6846 COUNT write %i\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), mc6846->latch  ));
459	459	if (!(mc6846->tcr & 0x38))
460	460	{
461	461	/* timer initialization */
r17796	r17797
471	471	break;
472	472
473	473	default:
474		logerror( "$%04x mc6846 invalid write offset %i\n", device->machine().firstcpu ->safe_pcbase( ), offset );
	474	logerror( "$%04x mc6846 invalid write offset %i\n", device->machine().firstcpu->pcbase( ), offset );
475	475	}
476	476	}
477	477

trunk/src/mess/machine/isa_hdc.c

r17796	r17797
796	796	}
797	797
798	798	if (LOG_HDC_CALL)
799		logerror("pc_HDC_r(): pc=%06X offs=%d result=0x%02x\n", device->machine().firstcpu->safe_pc(), offset, data);
	799	logerror("pc_HDC_r(): pc=%06X offs=%d result=0x%02x\n", device->machine().firstcpu->pc(), offset, data);
800	800
801	801	return data;
802	802	}
r17796	r17797
805	805	{
806	806	isa8_hdc_device   *hdc  = downcast<isa8_hdc_device *>(device);
807	807	if (LOG_HDC_CALL)
808		logerror("pc_HDC_w(): pc=%06X offs=%d data=0x%02x\n", device->machine().firstcpu->safe_pc(), offset, data);
	808	logerror("pc_HDC_w(): pc=%06X offs=%d data=0x%02x\n", device->machine().firstcpu->pc(), offset, data);
809	809
810	810	switch( offset )
811	811	{

trunk/src/mess/machine/macpci.c

r17796	r17797
53	53	{
54	54	//  macpci_state *mac = device->machine().driver_data<macpci_state>();
55	55
56		//    printf("VIA1 IN_A (PC %x)\n", mac->m_maincpu->safe_pc());
	56	//    printf("VIA1 IN_A (PC %x)\n", mac->m_maincpu->pc());
57	57
58	58	return 0x80;
59	59	}
r17796	r17797
65	65
66	66	val |= mac->m_cuda->get_treq()<<3;
67	67
68		//    printf("VIA1 IN B = %02x (PC %x)\n", val, mac->m_maincpu->safe_pc());
	68	//    printf("VIA1 IN B = %02x (PC %x)\n", val, mac->m_maincpu->pc());
69	69
70	70	return val;
71	71	}
r17796	r17797
74	74	{
75	75	//  macpci_state *mac = device->machine().driver_data<macpci_state>();
76	76
77		//    printf("VIA1 OUT A: %02x (PC %x)\n", data, mac->m_maincpu->safe_pc());
	77	//    printf("VIA1 OUT A: %02x (PC %x)\n", data, mac->m_maincpu->pc());
78	78	}
79	79
80	80	static WRITE8_DEVICE_HANDLER(mac_via_out_b)
81	81	{
82	82	macpci_state *mac = device->machine().driver_data<macpci_state>();
83	83
84		//    printf("VIA1 OUT B: %02x (PC %x)\n", data, mac->m_maincpu->safe_pc());
	84	//    printf("VIA1 OUT B: %02x (PC %x)\n", data, mac->m_maincpu->pc());
85	85
86	86	#if LOG_ADB
87		printf("PPC: New Cuda state: TIP %d BYTEACK %d (PC %x)\n", (data>>5)&1, (data>>4)&1, mac->m_maincpu->safe_pc());
	87	printf("PPC: New Cuda state: TIP %d BYTEACK %d (PC %x)\n", (data>>5)&1, (data>>4)&1, mac->m_maincpu->pc());
88	88	#endif
89	89	mac->m_cuda->set_byteack((data&0x10) ? 1 : 0);
90	90	mac->m_cuda->set_tip((data&0x20) ? 1 : 0);
r17796	r17797
98	98	offset &= 0x0f;
99	99
100	100	if (LOG_VIA)
101		printf("mac_via_r: offset=0x%02x (PC=%x)\n", offset, m_maincpu->safe_pc());
	101	printf("mac_via_r: offset=0x%02x (PC=%x)\n", offset, m_maincpu->pc());
102	102	data = m_via1->read(space, offset);
103	103
104	104	device_adjust_icount(m_maincpu, m_via_cycles);
r17796	r17797
112	112	offset &= 0x0f;
113	113
114	114	if (LOG_VIA)
115		printf("mac_via_w: offset=0x%02x data=0x%08x (PC=%x)\n", offset, data, m_maincpu->safe_pc());
	115	printf("mac_via_w: offset=0x%02x data=0x%08x (PC=%x)\n", offset, data, m_maincpu->pc());
116	116
117	117	if (ACCESSING_BITS_0_7)
118	118	m_via1->write(space, offset, data & 0xff);
r17796	r17797
181	181
182	182	READ32_MEMBER(macpci_state::mac_read_id)
183	183	{
184		printf("Mac read ID reg @ PC=%x\n", m_maincpu->safe_pc());
	184	printf("Mac read ID reg @ PC=%x\n", m_maincpu->pc());
185	185
186	186	switch (m_model)
187	187	{

trunk/src/mess/machine/ncr5380.c

r17796	r17797
237	237	}
238	238
239	239	if (VERBOSE)
240		logerror("NCR5380: read %s (reg %d) = %02x [PC=%x]\n", rnames[reg], reg, rv, machine().firstcpu->safe_pc());
	240	logerror("NCR5380: read %s (reg %d) = %02x [PC=%x]\n", rnames[reg], reg, rv, machine().firstcpu->pc());
241	241
242	242	return rv;
243	243	}
r17796	r17797
247	247	int reg = offset & 7;
248	248
249	249	if (VERBOSE)
250		logerror("NCR5380: %02x to %s (reg %d) [PC=%x]\n", data, wnames[reg], reg, machine().firstcpu->safe_pc());
	250	logerror("NCR5380: %02x to %s (reg %d) [PC=%x]\n", data, wnames[reg], reg, machine().firstcpu->pc());
251	251
252	252	switch( reg )
253	253	{
r17796	r17797
334	334	if (get_cmd_len(m_5380_Command[0]) == m_cmd_ptr)
335	335	{
336	336	if (VERBOSE)
337		logerror("NCR5380: Command (to ID %d): %x %x %x %x %x %x %x %x %x %x (PC %x)\n", m_last_id, m_5380_Command[0], m_5380_Command[1], m_5380_Command[2], m_5380_Command[3], m_5380_Command[4], m_5380_Command[5], m_5380_Command[6], m_5380_Command[7], m_5380_Command[8], m_5380_Command[9], machine().firstcpu->safe_pc());
	337	logerror("NCR5380: Command (to ID %d): %x %x %x %x %x %x %x %x %x %x (PC %x)\n", m_last_id, m_5380_Command[0], m_5380_Command[1], m_5380_Command[2], m_5380_Command[3], m_5380_Command[4], m_5380_Command[5], m_5380_Command[6], m_5380_Command[7], m_5380_Command[8], m_5380_Command[9], machine().firstcpu->pc());
338	338
339	339	m_scsi_devices[m_last_id]->SetCommand(&m_5380_Command[0], 16);
340	340	m_scsi_devices[m_last_id]->ExecCommand(&m_d_limit);

trunk/src/mess/machine/coco.c

r17796	r17797
261	261	address_space *program = m_maincpu->space(AS_PROGRAM);
262	262
263	263	// get the previous and current PC
264		UINT16 prev_pc = m_maincpu->safe_pcbase();
265		UINT16 pc = m_maincpu->safe_pc();
	264	UINT16 prev_pc = m_maincpu->pcbase();
	265	UINT16 pc = m_maincpu->pc();
266	266
267	267	// get the byte; and skip over header bytes
268	268	byte = program->read_byte(prev_pc);

trunk/src/mess/machine/compis.c

r17796	r17797
550	550	case 0x0d:   m_i186.intr.in_service &= ~0x20;   break;
551	551	case 0x0e:   m_i186.intr.in_service &= ~0x40;   break;
552	552	case 0x0f:   m_i186.intr.in_service &= ~0x80;   break;
553		default:   logerror("%05X:ERROR - 80186 EOI with unknown vector %02X\n", m_maincpu->safe_pc(), data & 0x1f);
	553	default:   logerror("%05X:ERROR - 80186 EOI with unknown vector %02X\n", m_maincpu->pc(), data & 0x1f);
554	554	}
555	555	if (LOG_INTERRUPTS) logerror("(%f) **** Got EOI for vector %02X\n", machine().time().as_double(), data & 0x1f);
556	556	}
r17796	r17797
718	718	diff = new_control ^ t->control;
719	719	if (diff & 0x001c)
720	720	logerror("%05X:ERROR! -unsupported timer mode %04X\n",
721		m_maincpu->safe_pc(), new_control);
	721	m_maincpu->pc(), new_control);
722	722
723	723	/* if we have real changes, update things */
724	724	if (diff != 0)
r17796	r17797
820	820	diff = new_control ^ d->control;
821	821	if (diff & 0x6811)
822	822	logerror("%05X:ERROR! - unsupported DMA mode %04X\n",
823		m_maincpu->safe_pc(), new_control);
	823	m_maincpu->pc(), new_control);
824	824
825	825	/* if we're going live, set a timer */
826	826	if ((diff & 0x0002) && (new_control & 0x0002))
r17796	r17797
877	877	switch (offset)
878	878	{
879	879	case 0x11:
880		logerror("%05X:ERROR - read from 80186 EOI\n", m_maincpu->safe_pc());
	880	logerror("%05X:ERROR - read from 80186 EOI\n", m_maincpu->pc());
881	881	break;
882	882
883	883	case 0x12:
884		if (LOG_PORTS) logerror("%05X:read 80186 interrupt poll\n", m_maincpu->safe_pc());
	884	if (LOG_PORTS) logerror("%05X:read 80186 interrupt poll\n", m_maincpu->pc());
885	885	if (m_i186.intr.poll_status & 0x8000)
886	886	int_callback(machine().device("maincpu"), 0);
887	887	return m_i186.intr.poll_status;
888	888
889	889	case 0x13:
890		if (LOG_PORTS) logerror("%05X:read 80186 interrupt poll status\n", m_maincpu->safe_pc());
	890	if (LOG_PORTS) logerror("%05X:read 80186 interrupt poll status\n", m_maincpu->pc());
891	891	return m_i186.intr.poll_status;
892	892
893	893	case 0x14:
894		if (LOG_PORTS) logerror("%05X:read 80186 interrupt mask\n", m_maincpu->safe_pc());
	894	if (LOG_PORTS) logerror("%05X:read 80186 interrupt mask\n", m_maincpu->pc());
895	895	temp  = (m_i186.intr.timer  >> 3) & 0x01;
896	896	temp |= (m_i186.intr.dma[0] >> 1) & 0x04;
897	897	temp |= (m_i186.intr.dma[1] >> 0) & 0x08;
r17796	r17797
902	902	return temp;
903	903
904	904	case 0x15:
905		if (LOG_PORTS) logerror("%05X:read 80186 interrupt priority mask\n", m_maincpu->safe_pc());
	905	if (LOG_PORTS) logerror("%05X:read 80186 interrupt priority mask\n", m_maincpu->pc());
906	906	return m_i186.intr.priority_mask;
907	907
908	908	case 0x16:
909		if (LOG_PORTS) logerror("%05X:read 80186 interrupt in-service\n", m_maincpu->safe_pc());
	909	if (LOG_PORTS) logerror("%05X:read 80186 interrupt in-service\n", m_maincpu->pc());
910	910	return m_i186.intr.in_service;
911	911
912	912	case 0x17:
913		if (LOG_PORTS) logerror("%05X:read 80186 interrupt request\n", m_maincpu->safe_pc());
	913	if (LOG_PORTS) logerror("%05X:read 80186 interrupt request\n", m_maincpu->pc());
914	914	temp = m_i186.intr.request & ~0x0001;
915	915	if (m_i186.intr.status & 0x0007)
916	916	temp |= 1;
917	917	return temp;
918	918
919	919	case 0x18:
920		if (LOG_PORTS) logerror("%05X:read 80186 interrupt status\n", m_maincpu->safe_pc());
	920	if (LOG_PORTS) logerror("%05X:read 80186 interrupt status\n", m_maincpu->pc());
921	921	return m_i186.intr.status;
922	922
923	923	case 0x19:
924		if (LOG_PORTS) logerror("%05X:read 80186 timer interrupt control\n", m_maincpu->safe_pc());
	924	if (LOG_PORTS) logerror("%05X:read 80186 timer interrupt control\n", m_maincpu->pc());
925	925	return m_i186.intr.timer;
926	926
927	927	case 0x1a:
928		if (LOG_PORTS) logerror("%05X:read 80186 DMA 0 interrupt control\n", m_maincpu->safe_pc());
	928	if (LOG_PORTS) logerror("%05X:read 80186 DMA 0 interrupt control\n", m_maincpu->pc());
929	929	return m_i186.intr.dma[0];
930	930
931	931	case 0x1b:
932		if (LOG_PORTS) logerror("%05X:read 80186 DMA 1 interrupt control\n", m_maincpu->safe_pc());
	932	if (LOG_PORTS) logerror("%05X:read 80186 DMA 1 interrupt control\n", m_maincpu->pc());
933	933	return m_i186.intr.dma[1];
934	934
935	935	case 0x1c:
936		if (LOG_PORTS) logerror("%05X:read 80186 INT 0 interrupt control\n", m_maincpu->safe_pc());
	936	if (LOG_PORTS) logerror("%05X:read 80186 INT 0 interrupt control\n", m_maincpu->pc());
937	937	return m_i186.intr.ext[0];
938	938
939	939	case 0x1d:
940		if (LOG_PORTS) logerror("%05X:read 80186 INT 1 interrupt control\n", m_maincpu->safe_pc());
	940	if (LOG_PORTS) logerror("%05X:read 80186 INT 1 interrupt control\n", m_maincpu->pc());
941	941	return m_i186.intr.ext[1];
942	942
943	943	case 0x1e:
944		if (LOG_PORTS) logerror("%05X:read 80186 INT 2 interrupt control\n", m_maincpu->safe_pc());
	944	if (LOG_PORTS) logerror("%05X:read 80186 INT 2 interrupt control\n", m_maincpu->pc());
945	945	return m_i186.intr.ext[2];
946	946
947	947	case 0x1f:
948		if (LOG_PORTS) logerror("%05X:read 80186 INT 3 interrupt control\n", m_maincpu->safe_pc());
	948	if (LOG_PORTS) logerror("%05X:read 80186 INT 3 interrupt control\n", m_maincpu->pc());
949	949	return m_i186.intr.ext[3];
950	950
951	951	case 0x28:
952	952	case 0x2c:
953	953	case 0x30:
954		if (LOG_PORTS) logerror("%05X:read 80186 Timer %d count\n", m_maincpu->safe_pc(), (offset - 0x28) / 4);
	954	if (LOG_PORTS) logerror("%05X:read 80186 Timer %d count\n", m_maincpu->pc(), (offset - 0x28) / 4);
955	955	which = (offset - 0x28) / 4;
956	956	if (!(offset & 1))
957	957	internal_timer_sync(which);
r17796	r17797
960	960	case 0x29:
961	961	case 0x2d:
962	962	case 0x31:
963		if (LOG_PORTS) logerror("%05X:read 80186 Timer %d max A\n", m_maincpu->safe_pc(), (offset - 0x29) / 4);
	963	if (LOG_PORTS) logerror("%05X:read 80186 Timer %d max A\n", m_maincpu->pc(), (offset - 0x29) / 4);
964	964	which = (offset - 0x29) / 4;
965	965	return m_i186.timer[which].maxA;
966	966
967	967	case 0x2a:
968	968	case 0x2e:
969		logerror("%05X:read 80186 Timer %d max B\n", m_maincpu->safe_pc(), (offset - 0x2a) / 4);
	969	logerror("%05X:read 80186 Timer %d max B\n", m_maincpu->pc(), (offset - 0x2a) / 4);
970	970	which = (offset - 0x2a) / 4;
971	971	return m_i186.timer[which].maxB;
972	972
973	973	case 0x2b:
974	974	case 0x2f:
975	975	case 0x33:
976		if (LOG_PORTS) logerror("%05X:read 80186 Timer %d control\n", m_maincpu->safe_pc(), (offset - 0x2b) / 4);
	976	if (LOG_PORTS) logerror("%05X:read 80186 Timer %d control\n", m_maincpu->pc(), (offset - 0x2b) / 4);
977	977	which = (offset - 0x2b) / 4;
978	978	return m_i186.timer[which].control;
979	979
980	980	case 0x50:
981		if (LOG_PORTS) logerror("%05X:read 80186 upper chip select\n", m_maincpu->safe_pc());
	981	if (LOG_PORTS) logerror("%05X:read 80186 upper chip select\n", m_maincpu->pc());
982	982	return m_i186.mem.upper;
983	983
984	984	case 0x51:
985		if (LOG_PORTS) logerror("%05X:read 80186 lower chip select\n", m_maincpu->safe_pc());
	985	if (LOG_PORTS) logerror("%05X:read 80186 lower chip select\n", m_maincpu->pc());
986	986	return m_i186.mem.lower;
987	987
988	988	case 0x52:
989		if (LOG_PORTS) logerror("%05X:read 80186 peripheral chip select\n", m_maincpu->safe_pc());
	989	if (LOG_PORTS) logerror("%05X:read 80186 peripheral chip select\n", m_maincpu->pc());
990	990	return m_i186.mem.peripheral;
991	991
992	992	case 0x53:
993		if (LOG_PORTS) logerror("%05X:read 80186 middle chip select\n", m_maincpu->safe_pc());
	993	if (LOG_PORTS) logerror("%05X:read 80186 middle chip select\n", m_maincpu->pc());
994	994	return m_i186.mem.middle;
995	995
996	996	case 0x54:
997		if (LOG_PORTS) logerror("%05X:read 80186 middle P chip select\n", m_maincpu->safe_pc());
	997	if (LOG_PORTS) logerror("%05X:read 80186 middle P chip select\n", m_maincpu->pc());
998	998	return m_i186.mem.middle_size;
999	999
1000	1000	case 0x60:
1001	1001	case 0x68:
1002		if (LOG_PORTS) logerror("%05X:read 80186 DMA%d lower source address\n", m_maincpu->safe_pc(), (offset - 0x60) / 8);
	1002	if (LOG_PORTS) logerror("%05X:read 80186 DMA%d lower source address\n", m_maincpu->pc(), (offset - 0x60) / 8);
1003	1003	which = (offset - 0x60) / 8;
1004	1004	//          stream_update(dma_stream, 0);
1005	1005	return m_i186.dma[which].source;
1006	1006
1007	1007	case 0x61:
1008	1008	case 0x69:
1009		if (LOG_PORTS) logerror("%05X:read 80186 DMA%d upper source address\n", m_maincpu->safe_pc(), (offset - 0x61) / 8);
	1009	if (LOG_PORTS) logerror("%05X:read 80186 DMA%d upper source address\n", m_maincpu->pc(), (offset - 0x61) / 8);
1010	1010	which = (offset - 0x61) / 8;
1011	1011	//          stream_update(dma_stream, 0);
1012	1012	return m_i186.dma[which].source >> 16;
1013	1013
1014	1014	case 0x62:
1015	1015	case 0x6a:
1016		if (LOG_PORTS) logerror("%05X:read 80186 DMA%d lower dest address\n", m_maincpu->safe_pc(), (offset - 0x62) / 8);
	1016	if (LOG_PORTS) logerror("%05X:read 80186 DMA%d lower dest address\n", m_maincpu->pc(), (offset - 0x62) / 8);
1017	1017	which = (offset - 0x62) / 8;
1018	1018	//          stream_update(dma_stream, 0);
1019	1019	return m_i186.dma[which].dest;
1020	1020
1021	1021	case 0x63:
1022	1022	case 0x6b:
1023		if (LOG_PORTS) logerror("%05X:read 80186 DMA%d upper dest address\n", m_maincpu->safe_pc(), (offset - 0x63) / 8);
	1023	if (LOG_PORTS) logerror("%05X:read 80186 DMA%d upper dest address\n", m_maincpu->pc(), (offset - 0x63) / 8);
1024	1024	which = (offset - 0x63) / 8;
1025	1025	//          stream_update(dma_stream, 0);
1026	1026	return m_i186.dma[which].dest >> 16;
1027	1027
1028	1028	case 0x64:
1029	1029	case 0x6c:
1030		if (LOG_PORTS) logerror("%05X:read 80186 DMA%d transfer count\n", m_maincpu->safe_pc(), (offset - 0x64) / 8);
	1030	if (LOG_PORTS) logerror("%05X:read 80186 DMA%d transfer count\n", m_maincpu->pc(), (offset - 0x64) / 8);
1031	1031	which = (offset - 0x64) / 8;
1032	1032	//          stream_update(dma_stream, 0);
1033	1033	return m_i186.dma[which].count;
1034	1034
1035	1035	case 0x65:
1036	1036	case 0x6d:
1037		if (LOG_PORTS) logerror("%05X:read 80186 DMA%d control\n", m_maincpu->safe_pc(), (offset - 0x65) / 8);
	1037	if (LOG_PORTS) logerror("%05X:read 80186 DMA%d control\n", m_maincpu->pc(), (offset - 0x65) / 8);
1038	1038	which = (offset - 0x65) / 8;
1039	1039	//          stream_update(dma_stream, 0);
1040	1040	return m_i186.dma[which].control;
1041	1041
1042	1042	default:
1043		logerror("%05X:read 80186 port %02X\n", m_maincpu->safe_pc(), offset);
	1043	logerror("%05X:read 80186 port %02X\n", m_maincpu->pc(), offset);
1044	1044	break;
1045	1045	}
1046	1046	return 0x00;
r17796	r17797
1061	1061	switch (offset)
1062	1062	{
1063	1063	case 0x11:
1064		if (LOG_PORTS) logerror("%05X:80186 EOI = %04X\n", m_maincpu->safe_pc(), data16);
	1064	if (LOG_PORTS) logerror("%05X:80186 EOI = %04X\n", m_maincpu->pc(), data16);
1065	1065	handle_eoi(0x8000);
1066	1066	update_interrupt_state(machine());
1067	1067	break;
1068	1068
1069	1069	case 0x12:
1070		logerror("%05X:ERROR - write to 80186 interrupt poll = %04X\n", m_maincpu->safe_pc(), data16);
	1070	logerror("%05X:ERROR - write to 80186 interrupt poll = %04X\n", m_maincpu->pc(), data16);
1071	1071	break;
1072	1072
1073	1073	case 0x13:
1074		logerror("%05X:ERROR - write to 80186 interrupt poll status = %04X\n", m_maincpu->safe_pc(), data16);
	1074	logerror("%05X:ERROR - write to 80186 interrupt poll status = %04X\n", m_maincpu->pc(), data16);
1075	1075	break;
1076	1076
1077	1077	case 0x14:
1078		if (LOG_PORTS) logerror("%05X:80186 interrupt mask = %04X\n", m_maincpu->safe_pc(), data16);
	1078	if (LOG_PORTS) logerror("%05X:80186 interrupt mask = %04X\n", m_maincpu->pc(), data16);
1079	1079	m_i186.intr.timer  = (m_i186.intr.timer  & ~0x08) | ((data16 << 3) & 0x08);
1080	1080	m_i186.intr.dma[0] = (m_i186.intr.dma[0] & ~0x08) | ((data16 << 1) & 0x08);
1081	1081	m_i186.intr.dma[1] = (m_i186.intr.dma[1] & ~0x08) | ((data16 << 0) & 0x08);
r17796	r17797
1087	1087	break;
1088	1088
1089	1089	case 0x15:
1090		if (LOG_PORTS) logerror("%05X:80186 interrupt priority mask = %04X\n", m_maincpu->safe_pc(), data16);
	1090	if (LOG_PORTS) logerror("%05X:80186 interrupt priority mask = %04X\n", m_maincpu->pc(), data16);
1091	1091	m_i186.intr.priority_mask = data16 & 0x0007;
1092	1092	update_interrupt_state(machine());
1093	1093	break;
1094	1094
1095	1095	case 0x16:
1096		if (LOG_PORTS) logerror("%05X:80186 interrupt in-service = %04X\n", m_maincpu->safe_pc(), data16);
	1096	if (LOG_PORTS) logerror("%05X:80186 interrupt in-service = %04X\n", m_maincpu->pc(), data16);
1097	1097	m_i186.intr.in_service = data16 & 0x00ff;
1098	1098	update_interrupt_state(machine());
1099	1099	break;
1100	1100
1101	1101	case 0x17:
1102		if (LOG_PORTS) logerror("%05X:80186 interrupt request = %04X\n", m_maincpu->safe_pc(), data16);
	1102	if (LOG_PORTS) logerror("%05X:80186 interrupt request = %04X\n", m_maincpu->pc(), data16);
1103	1103	m_i186.intr.request = (m_i186.intr.request & ~0x00c0) | (data16 & 0x00c0);
1104	1104	update_interrupt_state(machine());
1105	1105	break;
1106	1106
1107	1107	case 0x18:
1108		if (LOG_PORTS) logerror("%05X:WARNING - wrote to 80186 interrupt status = %04X\n", m_maincpu->safe_pc(), data16);
	1108	if (LOG_PORTS) logerror("%05X:WARNING - wrote to 80186 interrupt status = %04X\n", m_maincpu->pc(), data16);
1109	1109	m_i186.intr.status = (m_i186.intr.status & ~0x8007) | (data16 & 0x8007);
1110	1110	update_interrupt_state(machine());
1111	1111	break;
1112	1112
1113	1113	case 0x19:
1114		if (LOG_PORTS) logerror("%05X:80186 timer interrupt control = %04X\n", m_maincpu->safe_pc(), data16);
	1114	if (LOG_PORTS) logerror("%05X:80186 timer interrupt control = %04X\n", m_maincpu->pc(), data16);
1115	1115	m_i186.intr.timer = data16 & 0x000f;
1116	1116	break;
1117	1117
1118	1118	case 0x1a:
1119		if (LOG_PORTS) logerror("%05X:80186 DMA 0 interrupt control = %04X\n", m_maincpu->safe_pc(), data16);
	1119	if (LOG_PORTS) logerror("%05X:80186 DMA 0 interrupt control = %04X\n", m_maincpu->pc(), data16);
1120	1120	m_i186.intr.dma[0] = data16 & 0x000f;
1121	1121	break;
1122	1122
1123	1123	case 0x1b:
1124		if (LOG_PORTS) logerror("%05X:80186 DMA 1 interrupt control = %04X\n", m_maincpu->safe_pc(), data16);
	1124	if (LOG_PORTS) logerror("%05X:80186 DMA 1 interrupt control = %04X\n", m_maincpu->pc(), data16);
1125	1125	m_i186.intr.dma[1] = data16 & 0x000f;
1126	1126	break;
1127	1127
1128	1128	case 0x1c:
1129		if (LOG_PORTS) logerror("%05X:80186 INT 0 interrupt control = %04X\n", m_maincpu->safe_pc(), data16);
	1129	if (LOG_PORTS) logerror("%05X:80186 INT 0 interrupt control = %04X\n", m_maincpu->pc(), data16);
1130	1130	m_i186.intr.ext[0] = data16 & 0x007f;
1131	1131	break;
1132	1132
1133	1133	case 0x1d:
1134		if (LOG_PORTS) logerror("%05X:80186 INT 1 interrupt control = %04X\n", m_maincpu->safe_pc(), data16);
	1134	if (LOG_PORTS) logerror("%05X:80186 INT 1 interrupt control = %04X\n", m_maincpu->pc(), data16);
1135	1135	m_i186.intr.ext[1] = data16 & 0x007f;
1136	1136	break;
1137	1137
1138	1138	case 0x1e:
1139		if (LOG_PORTS) logerror("%05X:80186 INT 2 interrupt control = %04X\n", m_maincpu->safe_pc(), data16);
	1139	if (LOG_PORTS) logerror("%05X:80186 INT 2 interrupt control = %04X\n", m_maincpu->pc(), data16);
1140	1140	m_i186.intr.ext[2] = data16 & 0x001f;
1141	1141	break;
1142	1142
1143	1143	case 0x1f:
1144		if (LOG_PORTS) logerror("%05X:80186 INT 3 interrupt control = %04X\n", m_maincpu->safe_pc(), data16);
	1144	if (LOG_PORTS) logerror("%05X:80186 INT 3 interrupt control = %04X\n", m_maincpu->pc(), data16);
1145	1145	m_i186.intr.ext[3] = data16 & 0x001f;
1146	1146	break;
1147	1147
1148	1148	case 0x28:
1149	1149	case 0x2c:
1150	1150	case 0x30:
1151		if (LOG_PORTS) logerror("%05X:80186 Timer %d count = %04X\n", m_maincpu->safe_pc(), (offset - 0x28) / 4, data16);
	1151	if (LOG_PORTS) logerror("%05X:80186 Timer %d count = %04X\n", m_maincpu->pc(), (offset - 0x28) / 4, data16);
1152	1152	which = (offset - 0x28) / 4;
1153	1153	internal_timer_update(which, data16, -1, -1, -1);
1154	1154	break;
r17796	r17797
1156	1156	case 0x29:
1157	1157	case 0x2d:
1158	1158	case 0x31:
1159		if (LOG_PORTS) logerror("%05X:80186 Timer %d max A = %04X\n", m_maincpu->safe_pc(), (offset - 0x29) / 4, data16);
	1159	if (LOG_PORTS) logerror("%05X:80186 Timer %d max A = %04X\n", m_maincpu->pc(), (offset - 0x29) / 4, data16);
1160	1160	which = (offset - 0x29) / 4;
1161	1161	internal_timer_update(which, -1, data16, -1, -1);
1162	1162	break;
1163	1163
1164	1164	case 0x2a:
1165	1165	case 0x2e:
1166		if (LOG_PORTS) logerror("%05X:80186 Timer %d max B = %04X\n", m_maincpu->safe_pc(), (offset - 0x2a) / 4, data16);
	1166	if (LOG_PORTS) logerror("%05X:80186 Timer %d max B = %04X\n", m_maincpu->pc(), (offset - 0x2a) / 4, data16);
1167	1167	which = (offset - 0x2a) / 4;
1168	1168	internal_timer_update(which, -1, -1, data16, -1);
1169	1169	break;
r17796	r17797
1171	1171	case 0x2b:
1172	1172	case 0x2f:
1173	1173	case 0x33:
1174		if (LOG_PORTS) logerror("%05X:80186 Timer %d control = %04X\n", m_maincpu->safe_pc(), (offset - 0x2b) / 4, data16);
	1174	if (LOG_PORTS) logerror("%05X:80186 Timer %d control = %04X\n", m_maincpu->pc(), (offset - 0x2b) / 4, data16);
1175	1175	which = (offset - 0x2b) / 4;
1176	1176	internal_timer_update(which, -1, -1, -1, data16);
1177	1177	break;
1178	1178
1179	1179	case 0x50:
1180		if (LOG_PORTS) logerror("%05X:80186 upper chip select = %04X\n", m_maincpu->safe_pc(), data16);
	1180	if (LOG_PORTS) logerror("%05X:80186 upper chip select = %04X\n", m_maincpu->pc(), data16);
1181	1181	m_i186.mem.upper = data16 | 0xc038;
1182	1182	break;
1183	1183
1184	1184	case 0x51:
1185		if (LOG_PORTS) logerror("%05X:80186 lower chip select = %04X\n", m_maincpu->safe_pc(), data16);
	1185	if (LOG_PORTS) logerror("%05X:80186 lower chip select = %04X\n", m_maincpu->pc(), data16);
1186	1186	m_i186.mem.lower = (data16 & 0x3fff) | 0x0038; //printf("%X\n",m_i186.mem.lower);
1187	1187	break;
1188	1188
1189	1189	case 0x52:
1190		if (LOG_PORTS) logerror("%05X:80186 peripheral chip select = %04X\n", m_maincpu->safe_pc(), data16);
	1190	if (LOG_PORTS) logerror("%05X:80186 peripheral chip select = %04X\n", m_maincpu->pc(), data16);
1191	1191	m_i186.mem.peripheral = data16 | 0x0038;
1192	1192	break;
1193	1193
1194	1194	case 0x53:
1195		if (LOG_PORTS) logerror("%05X:80186 middle chip select = %04X\n", m_maincpu->safe_pc(), data16);
	1195	if (LOG_PORTS) logerror("%05X:80186 middle chip select = %04X\n", m_maincpu->pc(), data16);
1196	1196	m_i186.mem.middle = data16 | 0x01f8;
1197	1197	break;
1198	1198
1199	1199	case 0x54:
1200		if (LOG_PORTS) logerror("%05X:80186 middle P chip select = %04X\n", m_maincpu->safe_pc(), data16);
	1200	if (LOG_PORTS) logerror("%05X:80186 middle P chip select = %04X\n", m_maincpu->pc(), data16);
1201	1201	m_i186.mem.middle_size = data16 | 0x8038;
1202	1202
1203	1203	temp = (m_i186.mem.peripheral & 0xffc0) << 4;
r17796	r17797
1221	1221
1222	1222	case 0x60:
1223	1223	case 0x68:
1224		if (LOG_PORTS) logerror("%05X:80186 DMA%d lower source address = %04X\n", m_maincpu->safe_pc(), (offset - 0x60) / 8, data16);
	1224	if (LOG_PORTS) logerror("%05X:80186 DMA%d lower source address = %04X\n", m_maincpu->pc(), (offset - 0x60) / 8, data16);
1225	1225	which = (offset - 0x60) / 8;
1226	1226	//          stream_update(dma_stream, 0);
1227	1227	m_i186.dma[which].source = (m_i186.dma[which].source & ~0x0ffff) | (data16 & 0x0ffff);
r17796	r17797
1229	1229
1230	1230	case 0x61:
1231	1231	case 0x69:
1232		if (LOG_PORTS) logerror("%05X:80186 DMA%d upper source address = %04X\n", m_maincpu->safe_pc(), (offset - 0x61) / 8, data16);
	1232	if (LOG_PORTS) logerror("%05X:80186 DMA%d upper source address = %04X\n", m_maincpu->pc(), (offset - 0x61) / 8, data16);
1233	1233	which = (offset - 0x61) / 8;
1234	1234	//          stream_update(dma_stream, 0);
1235	1235	m_i186.dma[which].source = (m_i186.dma[which].source & ~0xf0000) | ((data16 << 16) & 0xf0000);
r17796	r17797
1237	1237
1238	1238	case 0x62:
1239	1239	case 0x6a:
1240		if (LOG_PORTS) logerror("%05X:80186 DMA%d lower dest address = %04X\n", m_maincpu->safe_pc(), (offset - 0x62) / 8, data16);
	1240	if (LOG_PORTS) logerror("%05X:80186 DMA%d lower dest address = %04X\n", m_maincpu->pc(), (offset - 0x62) / 8, data16);
1241	1241	which = (offset - 0x62) / 8;
1242	1242	//          stream_update(dma_stream, 0);
1243	1243	m_i186.dma[which].dest = (m_i186.dma[which].dest & ~0x0ffff) | (data16 & 0x0ffff);
r17796	r17797
1245	1245
1246	1246	case 0x63:
1247	1247	case 0x6b:
1248		if (LOG_PORTS) logerror("%05X:80186 DMA%d upper dest address = %04X\n", m_maincpu->safe_pc(), (offset - 0x63) / 8, data16);
	1248	if (LOG_PORTS) logerror("%05X:80186 DMA%d upper dest address = %04X\n", m_maincpu->pc(), (offset - 0x63) / 8, data16);
1249	1249	which = (offset - 0x63) / 8;
1250	1250	//          stream_update(dma_stream, 0);
1251	1251	m_i186.dma[which].dest = (m_i186.dma[which].dest & ~0xf0000) | ((data16 << 16) & 0xf0000);
r17796	r17797
1253	1253
1254	1254	case 0x64:
1255	1255	case 0x6c:
1256		if (LOG_PORTS) logerror("%05X:80186 DMA%d transfer count = %04X\n", m_maincpu->safe_pc(), (offset - 0x64) / 8, data16);
	1256	if (LOG_PORTS) logerror("%05X:80186 DMA%d transfer count = %04X\n", m_maincpu->pc(), (offset - 0x64) / 8, data16);
1257	1257	which = (offset - 0x64) / 8;
1258	1258	//          stream_update(dma_stream, 0);
1259	1259	m_i186.dma[which].count = data16;
r17796	r17797
1261	1261
1262	1262	case 0x65:
1263	1263	case 0x6d:
1264		if (LOG_PORTS) logerror("%05X:80186 DMA%d control = %04X\n", m_maincpu->safe_pc(), (offset - 0x65) / 8, data16);
	1264	if (LOG_PORTS) logerror("%05X:80186 DMA%d control = %04X\n", m_maincpu->pc(), (offset - 0x65) / 8, data16);
1265	1265	which = (offset - 0x65) / 8;
1266	1266	//          stream_update(dma_stream, 0);
1267	1267	update_dma_control(which, data16);
1268	1268	break;
1269	1269
1270	1270	case 0x7f:
1271		if (LOG_PORTS) logerror("%05X:80186 relocation register = %04X\n", m_maincpu->safe_pc(), data16);
	1271	if (LOG_PORTS) logerror("%05X:80186 relocation register = %04X\n", m_maincpu->pc(), data16);
1272	1272
1273	1273	/* we assume here there that this doesn't happen too often */
1274	1274	/* plus, we can't really remove the old memory range, so we also assume that it's */
r17796	r17797
1289	1289	break;
1290	1290
1291	1291	default:
1292		logerror("%05X:80186 port %02X = %04X\n", m_maincpu->safe_pc(), offset, data16);
	1292	logerror("%05X:80186 port %02X = %04X\n", m_maincpu->pc(), offset, data16);
1293	1293	break;
1294	1294	}
1295	1295	}

trunk/src/mess/machine/mac.c

r17796	r17797
1158	1158	result = applefdc_r(fdc, (offset >> 8));
1159	1159
1160	1160	if (LOG_MAC_IWM)
1161		printf("mac_iwm_r: offset=0x%08x mem_mask %04x = %02x (PC %x)\n", offset, mem_mask, result, m_maincpu->safe_pc());
	1161	printf("mac_iwm_r: offset=0x%08x mem_mask %04x = %02x (PC %x)\n", offset, mem_mask, result, m_maincpu->pc());
1162	1162
1163	1163	return (result << 8) | result;
1164	1164	}
r17796	r17797
1168	1168	device_t *fdc = space.machine().device("fdc");
1169	1169
1170	1170	if (LOG_MAC_IWM)
1171		printf("mac_iwm_w: offset=0x%08x data=0x%04x mask %04x (PC=%x)\n", offset, data, mem_mask, m_maincpu->safe_pc());
	1171	printf("mac_iwm_w: offset=0x%08x data=0x%04x mask %04x (PC=%x)\n", offset, data, mem_mask, m_maincpu->pc());
1172	1172
1173	1173	if (ACCESSING_BITS_0_7)
1174	1174	applefdc_w(fdc, (offset >> 8), data & 0xff);
r17796	r17797
1534	1534	else if (ADB_IS_EGRET)
1535	1535	{
1536	1536	#if LOG_ADB
1537		printf("68K: New Egret state: SS %d VF %d (PC %x)\n", (data>>5)&1, (data>>4)&1, mac->m_maincpu->safe_pc());
	1537	printf("68K: New Egret state: SS %d VF %d (PC %x)\n", (data>>5)&1, (data>>4)&1, mac->m_maincpu->pc());
1538	1538	#endif
1539	1539	mac->m_egret->set_via_full((data&0x10) ? 1 : 0);
1540	1540	mac->m_egret->set_sys_session((data&0x20) ? 1 : 0);
r17796	r17797
1542	1542	else if (ADB_IS_CUDA)
1543	1543	{
1544	1544	#if LOG_ADB
1545		printf("68K: New Cuda state: TIP %d BYTEACK %d (PC %x)\n", (data>>5)&1, (data>>4)&1, mac->m_maincpu->safe_pc());
	1545	printf("68K: New Cuda state: TIP %d BYTEACK %d (PC %x)\n", (data>>5)&1, (data>>4)&1, mac->m_maincpu->pc());
1546	1546	#endif
1547	1547	mac->m_cuda->set_byteack((data&0x10) ? 1 : 0);
1548	1548	mac->m_cuda->set_tip((data&0x20) ? 1 : 0);
r17796	r17797
2012	2012
2013	2013	READ32_MEMBER(mac_state::mac_read_id)
2014	2014	{
2015		//    printf("Mac read ID reg @ PC=%x\n", m_maincpu->safe_pc());
	2015	//    printf("Mac read ID reg @ PC=%x\n", m_maincpu->pc());
2016	2016
2017	2017	switch (m_model)
2018	2018	{

trunk/src/mess/machine/mc6843.c

r17796	r17797
427	427	int cmd = mc6843->CMR & 0x0f;
428	428
429	429	LOG(( "%f $%04x mc6843_r: data input cmd=%s(%i), pos=%i/%i, GCR=%i, ",
430		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ),
	430	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ),
431	431	mc6843_cmd[cmd], cmd, mc6843->data_idx,
432	432	mc6843->data_size, mc6843->GCR ));
433	433
r17796	r17797
480	480	{
481	481	/* XXX TODO: other read modes */
482	482	data = mc6843->data[0];
483		logerror( "$%04x mc6843 read in unsupported command mode %i\n", device->machine().firstcpu ->safe_pcbase( ), cmd );
	483	logerror( "$%04x mc6843 read in unsupported command mode %i\n", device->machine().firstcpu->pcbase( ), cmd );
484	484	}
485	485
486	486	LOG(( "data=%02X\n", data ));
r17796	r17797
491	491	case 1: /* Current-Track Address Register (CTAR) */
492	492	data = mc6843->CTAR;
493	493	LOG(( "%f $%04x mc6843_r: read CTAR %i (actual=%i)\n",
494		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data,
	494	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data,
495	495	floppy_drive_get_current_track( mc6843_floppy_image( device ) ) ));
496	496	break;
497	497
498	498	case 2: /* Interrupt Status Register (ISR) */
499	499	data = mc6843->ISR;
500	500	LOG(( "%f $%04x mc6843_r: read ISR %02X: cmd=%scomplete settle=%scomplete sense-rq=%i STRB=%i\n",
501		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data,
	501	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data,
502	502	(data & 1) ? "" : "not-" , (data & 2) ? "" : "not-",
503	503	(data >> 2) & 1, (data >> 3) & 1 ));
504	504
r17796	r17797
524	524
525	525	data = mc6843->STRA;
526	526	LOG(( "%f $%04x mc6843_r: read STRA %02X: data-rq=%i del-dta=%i ready=%i t0=%i wp=%i trk-dif=%i idx=%i busy=%i\n",
527		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data,
	527	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data,
528	528	data & 1, (data >> 1) & 1, (data >> 2) & 1, (data >> 3) & 1,
529	529	(data >> 4) & 1, (data >> 5) & 1, (data >> 6) & 1, (data >> 7) & 1 ));
530	530	break;
r17796	r17797
533	533	case 4: /* Status Register B (STRB) */
534	534	data = mc6843->STRB;
535	535	LOG(( "%f $%04x mc6843_r: read STRB %02X: data-err=%i CRC-err=%i dta--mrk-err=%i sect-mrk-err=%i seek-err=%i fi=%i wr-err=%i hard-err=%i\n",
536		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data,
	536	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data,
537	537	data & 1, (data >> 1) & 1, (data >> 2) & 1, (data >> 3) & 1,
538	538	(data >> 4) & 1, (data >> 5) & 1, (data >> 6) & 1, (data >> 7) & 1 ));
539	539
r17796	r17797
545	545	case 7: /* Logical-Track Address Register (LTAR) */
546	546	data = mc6843->LTAR;
547	547	LOG(( "%f $%04x mc6843_r: read LTAR %i (actual=%i)\n",
548		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data,
	548	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data,
549	549	floppy_drive_get_current_track( mc6843_floppy_image( device ) ) ));
550	550	break;
551	551
552	552	default:
553		logerror( "$%04x mc6843 invalid read offset %i\n", device->machine().firstcpu ->safe_pcbase( ), offset );
	553	logerror( "$%04x mc6843 invalid read offset %i\n", device->machine().firstcpu->pcbase( ), offset );
554	554	}
555	555
556	556	return data;
r17796	r17797
567	567	int FWF = (mc6843->CMR >> 4) & 1;
568	568
569	569	LOG(( "%f $%04x mc6843_w: data output cmd=%s(%i), pos=%i/%i, GCR=%i, data=%02X\n",
570		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ),
	570	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ),
571	571	mc6843_cmd[cmd], cmd, mc6843->data_idx,
572	572	mc6843->data_size, mc6843->GCR, data ));
573	573
r17796	r17797
584	584	/* end of sector write */
585	585	device_t* img = mc6843_floppy_image( device );
586	586
587		LOG(( "%f $%04x mc6843_w: write sector %i\n", device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6843->data_id ));
	587	LOG(( "%f $%04x mc6843_w: write sector %i\n", device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6843->data_id ));
588	588
589	589	floppy_drive_write_sector_data(
590	590	img, mc6843->side, mc6843->data_id,
r17796	r17797
648	648	UINT8 track  = mc6843->data[1];
649	649	UINT8 sector = mc6843->data[3];
650	650	UINT8 filler = 0xe5; /* standard Thomson filler */
651		LOG(( "%f $%04x mc6843_w: address id detected track=%i sector=%i\n", device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), track, sector));
	651	LOG(( "%f $%04x mc6843_w: address id detected track=%i sector=%i\n", device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), track, sector));
652	652	floppy_drive_format_sector( img, mc6843->side, sector, track, 0, sector, 0, filler );
653	653	}
654	654	else
r17796	r17797
670	670	else
671	671	{
672	672	/* XXX TODO: other write modes */
673		logerror( "$%04x mc6843 write %02X in unsupported command mode %i (FWF=%i)\n", device->machine().firstcpu ->safe_pcbase( ), data, cmd, FWF );
	673	logerror( "$%04x mc6843 write %02X in unsupported command mode %i (FWF=%i)\n", device->machine().firstcpu->pcbase( ), data, cmd, FWF );
674	674	}
675	675	break;
676	676	}
r17796	r17797
678	678	case 1: /* Current-Track Address Register (CTAR) */
679	679	mc6843->CTAR = data & 0x7f;
680	680	LOG(( "%f $%04x mc6843_w: set CTAR to %i %02X (actual=%i) \n",
681		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6843->CTAR, data,
	681	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6843->CTAR, data,
682	682	floppy_drive_get_current_track( mc6843_floppy_image( device ) ) ));
683	683	break;
684	684
r17796	r17797
687	687	int cmd = data & 15;
688	688
689	689	LOG(( "%f $%04x mc6843_w: set CMR to $%02X: cmd=%s(%i) FWF=%i DMA=%i ISR3-intr=%i fun-intr=%i\n",
690		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ),
	690	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ),
691	691	data, mc6843_cmd[cmd], cmd, (data >> 4) & 1, (data >> 5) & 1,
692	692	(data >> 6) & 1, (data >> 7) & 1 ));
693	693
r17796	r17797
734	734
735	735	/* assume CLK freq = 1MHz (IBM 3740 compatibility) */
736	736	LOG(( "%f $%04x mc6843_w: set SUR to $%02X: head settling time=%fms, track-to-track seek time=%f\n",
737		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ),
	737	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ),
738	738	data, 4.096 * (data & 15), 1.024 * ((data >> 4) & 15) ));
739	739	break;
740	740
741	741	case 4: /* Sector Address Register (SAR) */
742	742	mc6843->SAR = data & 0x1f;
743		LOG(( "%f $%04x mc6843_w: set SAR to %i (%02X)\n", device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6843->SAR, data ));
	743	LOG(( "%f $%04x mc6843_w: set SAR to %i (%02X)\n", device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6843->SAR, data ));
744	744	break;
745	745
746	746	case 5: /* General Count Register (GCR) */
747	747	mc6843->GCR = data & 0x7f;
748		LOG(( "%f $%04x mc6843_w: set GCR to %i (%02X)\n", device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6843->GCR, data ));
	748	LOG(( "%f $%04x mc6843_w: set GCR to %i (%02X)\n", device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6843->GCR, data ));
749	749	break;
750	750
751	751	case 6: /* CRC Control Register (CCR) */
752	752	mc6843->CCR = data & 3;
753	753	LOG(( "%f $%04x mc6843_w: set CCR to %02X: CRC=%s shift=%i\n",
754		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data,
	754	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data,
755	755	(data & 1) ? "enabled" : "disabled", (data >> 1) & 1 ));
756	756	break;
757	757
758	758	case 7: /* Logical-Track Address Register (LTAR) */
759	759	mc6843->LTAR = data & 0x7f;
760	760	LOG(( "%f $%04x mc6843_w: set LTAR to %i %02X (actual=%i)\n",
761		device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6843->LTAR, data,
	761	device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6843->LTAR, data,
762	762	floppy_drive_get_current_track( mc6843_floppy_image( device ) ) ));
763	763	break;
764	764
765	765	default:
766		logerror( "$%04x mc6843 invalid write offset %i (data=$%02X)\n", device->machine().firstcpu ->safe_pcbase( ), offset, data );
	766	logerror( "$%04x mc6843 invalid write offset %i (data=$%02X)\n", device->machine().firstcpu->pcbase( ), offset, data );
767	767	}
768	768	}
769	769

trunk/src/mess/machine/apple2.c

r17796	r17797
1450	1450	if (offset == 0xa)  // RAM
1451	1451	{
1452	1452	apple2_setvar(space.machine(), VAR_TK2000RAM, ~0);
1453		printf("TK2000: RAM (PC %x)\n", m_maincpu->safe_pc());
	1453	printf("TK2000: RAM (PC %x)\n", m_maincpu->pc());
1454	1454	}
1455	1455	else if (offset == 0xb) // ROM
1456	1456	{
1457	1457	apple2_setvar(space.machine(), 0, ~VAR_TK2000RAM);
1458		printf("TK2000: ROM (PC %x)\n", m_maincpu->safe_pc());
	1458	printf("TK2000: ROM (PC %x)\n", m_maincpu->pc());
1459	1459	}
1460	1460	}
1461	1461

trunk/src/mess/video/crtc_ega.c

r17796	r17797
80	80
81	81	WRITE8_MEMBER( crtc_ega_device::register_w )
82	82	{
83		if (LOG)  logerror("CRTC_EGA PC %04x: reg 0x%02x = 0x%02x\n", machine().firstcpu->safe_pc(), m_register_address_latch, data);
	83	if (LOG)  logerror("CRTC_EGA PC %04x: reg 0x%02x = 0x%02x\n", machine().firstcpu->pc(), m_register_address_latch, data);
84	84
85	85	switch (m_register_address_latch)
86	86	{

trunk/src/mess/drivers/vboy.c

r17796	r17797
793	793	case 0x42:   //XPCTRL
794	794	return m_vip_regs.XPCTRL;
795	795	case 0x44:   //VER
796		printf("%08x read VER\n",m_maincpu->safe_pc());
	796	printf("%08x read VER\n",m_maincpu->pc());
797	797	return m_vip_regs.VER;
798	798	case 0x48:   //SPT0
799	799	return m_vip_regs.SPT[0];

trunk/src/mess/drivers/camplynx.c

r17796	r17797
121	121	if (data & 4)
122	122	membank("bank1")->set_entry(2);
123	123	else
124		logerror("%04X: Cannot understand bankswitch command %X\n",m_maincpu->safe_pc(), data);
	124	logerror("%04X: Cannot understand bankswitch command %X\n",m_maincpu->pc(), data);
125	125	}
126	126
127	127	WRITE8_MEMBER( camplynx_state::lynx128k_bank_w )
r17796	r17797
157	157	membank("bank8")->set_base(base + 0x2e000);
158	158	}
159	159	else
160		logerror("%04X: Cannot understand bankswitch command %X\n",m_maincpu->safe_pc(), data);
	160	logerror("%04X: Cannot understand bankswitch command %X\n",m_maincpu->pc(), data);
161	161
162	162	/* Set write banks */
163	163	bank = data & 0xd0;
r17796	r17797
186	186	membank("bank18")->set_base(base + 0x2e000);
187	187	}
188	188	else
189		logerror("%04X: Cannot understand bankswitch command %X\n",m_maincpu->safe_pc(), data);
	189	logerror("%04X: Cannot understand bankswitch command %X\n",m_maincpu->pc(), data);
190	190	}
191	191
192	192	static ADDRESS_MAP_START( lynx48k_mem, AS_PROGRAM, 8, camplynx_state )

trunk/src/mess/drivers/gp2x.c

r17796	r17797
250	250	break;
251	251
252	252	default:
253		logerror("NAND: read unk command %x (PC %x)\n", m_nand_cmd, m_maincpu->safe_pc());
	253	logerror("NAND: read unk command %x (PC %x)\n", m_nand_cmd, m_maincpu->pc());
254	254	break;
255	255	}
256	256	}
r17796	r17797
266	266	{
267	267	case 4:   // command
268	268	m_nand_cmd = data;
269		//          printf("NAND: command %x (PC %x0)\n", data, m_maincpu->safe_pc());
	269	//          printf("NAND: command %x (PC %x0)\n", data, m_maincpu->pc());
270	270	m_nand_stage = 0;
271	271	m_nand_subword_stage = 0;
272	272	break;

trunk/src/mess/drivers/pasopia7.c

r17796	r17797
615	615	return pasopia7_fdc_r(space, offset & 7);
616	616	else
617	617	{
618		logerror("(PC=%06x) Read i/o address %02x\n",m_maincpu->safe_pc(),io_port);
	618	logerror("(PC=%06x) Read i/o address %02x\n",m_maincpu->pc(),io_port);
619	619	}
620	620
621	621	return 0xff;
r17796	r17797
672	672	pasopia7_fdc_w(space, offset & 7, data);
673	673	else
674	674	{
675		logerror("(PC=%06x) Write i/o address %02x = %02x\n",m_maincpu->safe_pc(),offset,data);
	675	logerror("(PC=%06x) Write i/o address %02x = %02x\n",m_maincpu->pc(),offset,data);
676	676	}
677	677	}
678	678

trunk/src/mess/drivers/cxhumax.c

r17796	r17797
150	150	UINT32 data = m_scratch_reg;
151	151	verboselog( machine(), 9, "(SCRATCH) %08X -> %08X\n", 0xE0400024 + (offset << 2), data);
152	152
153		if((m_maincpu->safe_pc()==0xF0003BB8) || (m_maincpu->safe_pc()==0x01003724) || (m_maincpu->safe_pc()==0x00005d8c)) { // HDCI-2000
	153	if((m_maincpu->pc()==0xF0003BB8) || (m_maincpu->pc()==0x01003724) || (m_maincpu->pc()==0x00005d8c)) { // HDCI-2000
154	154	//we're in disabled debug_printf
155	155	unsigned char* buf = (unsigned char *)alloca(200);
156	156	unsigned char temp;

trunk/src/mess/drivers/next.c

r17796	r17797
529	529	data & DMA_INITBUFTURBO ? " initbufturbo" : "");
530	530	#endif
531	531	if(data & DMA_SETENABLE)
532		logerror("dma enable %s %s %08x (%08x)\n", name, data & DMA_SETREAD ? "read" : "write", (dma_slots[slot].limit-dma_slots[slot].start) & 0x7fffffff, maincpu->safe_pc());
	532	logerror("dma enable %s %s %08x (%08x)\n", name, data & DMA_SETREAD ? "read" : "write", (dma_slots[slot].limit-dma_slots[slot].start) & 0x7fffffff, maincpu->pc());
533	533
534	534	dma_slot &ds = dma_slots[slot];
535	535	if(data & (DMA_RESET|DMA_INITBUF|DMA_INITBUFTURBO)) {

trunk/src/mess/drivers/pasogo.c

r17796	r17797
177	177	}
178	178
179	179	if (log)
180		logerror("%.5x vg230 %02x read %.2x\n",(int) m_maincpu->safe_pc(),vg230->index,data);
	180	logerror("%.5x vg230 %02x read %.2x\n",(int) m_maincpu->pc(),vg230->index,data);
181	181	//    data=machine.root_device().memregion("maincpu")->base()[0x4000+offset];
182	182	}
183	183	else
r17796	r17797
221	221	}
222	222
223	223	if (log)
224		logerror("%.5x vg230 %02x write %.2x\n",(int)m_maincpu->safe_pc(),vg230->index,data);
	224	logerror("%.5x vg230 %02x write %.2x\n",(int)m_maincpu->pc(),vg230->index,data);
225	225	}
226	226	else
227	227	vg230->index=data;
r17796	r17797
288	288	ems->mapper[ems->index].address=(ems->mapper[ems->index].data[0]<<14)|((ems->mapper[ems->index].data[1]&0xf)<<22);
289	289	ems->mapper[ems->index].on=ems->mapper[ems->index].data[1]&0x80;
290	290	ems->mapper[ems->index].type=(ems->mapper[ems->index].data[1]&0x70)>>4;
291		logerror("%.5x ems mapper %d(%05x)on:%d type:%d address:%07x\n",(int)m_maincpu->safe_pc(),ems->index, ems->data<<12,
	291	logerror("%.5x ems mapper %d(%05x)on:%d type:%d address:%07x\n",(int)m_maincpu->pc(),ems->index, ems->data<<12,
292	292	ems->mapper[ems->index].on, ems->mapper[ems->index].type, ems->mapper[ems->index].address );
293	293
294	294	switch (ems->mapper[ems->index].type)

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