trunk/src/mame/drivers/imds2.c
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| 26 | 26 | // A82 2732 EPROM with monitor & boot firmware (assembly source of this ROM is in [4]) |
| 27 | 27 | // A66 8259A System PIC |
| 28 | 28 | // A89 8259A Local PIC |
| 29 | | //*A86 8253 PIT |
| 30 | | //*A91 8251A Serial channel #0 |
| 31 | | //*A90 8251A Serial channel #1 |
| 29 | // A86 8253 PIT |
| 30 | // A91 8251A Serial channel #0 |
| 31 | // A90 8251A Serial channel #1 |
| 32 | 32 | // |
| 33 | 33 | // ********** |
| 34 | 34 | // I/O Controller (IOC) |
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| 60 | 60 | // |
| 61 | 61 | // A3 8741 CPU @ 3.58 MHz |
| 62 | 62 | // |
| 63 | | // ICs that are not emulated yet are marked with "*" |
| 64 | | // |
| 65 | 63 | // NOTE: |
| 66 | 64 | // Firmware running on PIO is NOT original because a dump is not available at the moment. |
| 67 | 65 | // Emulator runs a version of PIO firmware that was specifically developped by me to implement |
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| 69 | 67 | // |
| 70 | 68 | // TODO: |
| 71 | 69 | // - Find a dump of the original PIO firmware |
| 72 | | // - Emulate serial channels on IPC |
| 73 | | // - Emulate PIT on IPC |
| 74 | 70 | // - Adjust speed of processors. Wait states are not accounted for yet. |
| 75 | 71 | // |
| 76 | 72 | // Huge thanks to Dave Mabry for dumping IOC firmware, KB firmware and character generator. This driver would not |
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| 176 | 172 | m_ipctimer(*this , "ipctimer"), |
| 177 | 173 | m_ipcusart0(*this , "ipcusart0"), |
| 178 | 174 | m_ipcusart1(*this , "ipcusart1"), |
| 175 | m_serial0(*this , "serial0"), |
| 176 | m_serial1(*this , "serial1"), |
| 179 | 177 | m_ioccpu(*this , "ioccpu"), |
| 180 | 178 | m_iocdma(*this , "iocdma"), |
| 181 | 179 | m_ioccrtc(*this , "ioccrtc"), |
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| 787 | 785 | MCFG_I8251_RTS_HANDLER(DEVWRITELINE("ipcusart0" , i8251_device , write_cts)) |
| 788 | 786 | MCFG_I8251_RXRDY_HANDLER(DEVWRITELINE("ipclocpic" , pic8259_device , ir0_w)) |
| 789 | 787 | MCFG_I8251_TXRDY_HANDLER(DEVWRITELINE("ipclocpic" , pic8259_device , ir1_w)) |
| 788 | MCFG_I8251_TXD_HANDLER(DEVWRITELINE("serial0" , rs232_port_device , write_txd)) |
| 790 | 789 | |
| 791 | 790 | MCFG_DEVICE_ADD("ipcusart1" , I8251 , 0) |
| 792 | 791 | MCFG_I8251_RXRDY_HANDLER(DEVWRITELINE("ipclocpic" , pic8259_device , ir2_w)) |
| 793 | 792 | MCFG_I8251_TXRDY_HANDLER(DEVWRITELINE("ipclocpic" , pic8259_device , ir3_w)) |
| 793 | MCFG_I8251_TXD_HANDLER(DEVWRITELINE("serial1" , rs232_port_device , write_txd)) |
| 794 | MCFG_I8251_RTS_HANDLER(DEVWRITELINE("serial1" , rs232_port_device , write_rts)) |
| 795 | MCFG_I8251_DTR_HANDLER(DEVWRITELINE("serial1" , rs232_port_device , write_dtr)) |
| 794 | 796 | |
| 797 | MCFG_RS232_PORT_ADD("serial0" , default_rs232_devices , NULL) |
| 798 | MCFG_RS232_RXD_HANDLER(DEVWRITELINE("ipcusart0" , i8251_device , write_rxd)) |
| 799 | MCFG_RS232_DSR_HANDLER(DEVWRITELINE("ipcusart0" , i8251_device , write_dsr)) |
| 800 | |
| 801 | MCFG_RS232_PORT_ADD("serial1" , default_rs232_devices , NULL) |
| 802 | MCFG_RS232_RXD_HANDLER(DEVWRITELINE("ipcusart1" , i8251_device , write_rxd)) |
| 803 | MCFG_RS232_CTS_HANDLER(DEVWRITELINE("ipcusart1" , i8251_device , write_cts)) |
| 804 | MCFG_RS232_DSR_HANDLER(DEVWRITELINE("ipcusart1" , i8251_device , write_dsr)) |
| 805 | |
| 795 | 806 | MCFG_CPU_ADD("ioccpu" , I8080A , IOC_XTAL_Y2 / 18) // 2.448 MHz but running at 50% (due to wait states & DMA usage of bus) |
| 796 | 807 | MCFG_CPU_PROGRAM_MAP(ioc_mem_map) |
| 797 | 808 | MCFG_CPU_IO_MAP(ioc_io_map) |