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r36369 Tuesday 10th March, 2015 at 21:48:56 UTC by David Haywood

expose some more V53 pins for the internal peripherals to the outside world (nw) timers seem very active, does some DMA ops (transfering a big block of 0 data) a few times on startup, then stops.. maybe because no interrupts happen. interrupt table looks.. weird, need to understand how it configures the interrupt controller and what that means. there are port writes to low port numbers, writes to port 0x0000 in the format with data in the format 0x??00 0x??01 0x??02 0x??03 0x??04 0x??05 0x??06 0x??07 0x??08 0x??09 0x??0a 0x??0b 0x??0c 0x??0d 0x??0e 0x??0f 0x??10 0x??11 0x??12 0x??13 0x??14 0x??15 0x??16 0x??17 0x??18 0x??19 0x??1a 0x??1b 0x??1c 0x??1d 0x??1e 0x??1f and after each write to port 0 with those values it writes some other data to ports 2,4,6. if the information is correct, and this is a 32-channel based sound system, then that could well be some kind of configuration for the channels.

[src/emu/cpu/nec]	v53.c v53.h
[src/mame/audio]	hng64.c
[src/mame/includes]	hng64.h

trunk/src/emu/cpu/nec/v53.c

r244880	r244881
198	198	m_out0_handler.resolve_safe();
199	199	m_out1_handler.resolve_safe();
200	200	m_out2_handler.resolve_safe();
	201
	202	m_out_hreq_cb.resolve_safe();
	203	m_out_eop_cb.resolve_safe();
	204	m_in_memr_cb.resolve_safe(0);
	205	m_out_memw_cb.resolve_safe();
	206	m_in_ior_0_cb.resolve_safe(0);
	207	m_in_ior_1_cb.resolve_safe(0);
	208	m_in_ior_2_cb.resolve_safe(0);
	209	m_in_ior_3_cb.resolve_safe(0);
	210	m_out_iow_0_cb.resolve_safe();
	211	m_out_iow_1_cb.resolve_safe();
	212	m_out_iow_2_cb.resolve_safe();
	213	m_out_iow_3_cb.resolve_safe();
	214	m_out_dack_0_cb.resolve_safe();
	215	m_out_dack_1_cb.resolve_safe();
	216	m_out_dack_2_cb.resolve_safe();
	217	m_out_dack_3_cb.resolve_safe();
201	218	}
202	219
203	220	void v53_base_device::install_peripheral_io()
r244880	r244881
304	321	printf("v53: scu_simk_w %02x\n", data);
305	322	}
306	323
307		WRITE_LINE_MEMBER(v53_base_device::scu_txd_trampoline_cb)
308		{
309		m_txd_handler(state);
310		}
311	324
312		WRITE_LINE_MEMBER(v53_base_device::scu_dtr_trampoline_cb)
313		{
314		m_dtr_handler(state);
315		}
316	325
317		WRITE_LINE_MEMBER(v53_base_device::scu_rts_trampoline_cb)
318		{
319		m_rts_handler(state);
320		}
321
322		WRITE_LINE_MEMBER(v53_base_device::scu_rxrdy_trampoline_cb)
323		{
324		// should we mask this here based on m_simk? it can mask the interrupt
325		m_rxrdy_handler(state);
326		}
327
328		WRITE_LINE_MEMBER(v53_base_device::scu_txrdy_trampoline_cb)
329		{
330		// should we mask this here based on m_simk? it can mask the interrupt
331		m_txrdy_handler(state);
332		}
333
334		WRITE_LINE_MEMBER(v53_base_device::scu_txempty_trampoline_cb)
335		{
336		m_txempty_handler(state);
337		}
338
339		WRITE_LINE_MEMBER(v53_base_device::scu_syndet_trampoline_cb)
340		{
341		m_syndet_handler(state);
342		}
343
344
345	326	/*** TCU ***/
346	327
347	328	WRITE8_MEMBER(v53_base_device::tmu_tct0_w) { m_v53tcu->write(space, 0, data); }
r244880	r244881
355	336	READ8_MEMBER(v53_base_device::tmu_tst2_r) {   return m_v53tcu->read(space, 2); }
356	337
357	338
358		WRITE_LINE_MEMBER(v53_base_device::tcu_out0_trampoline_cb)
359		{
360		m_out0_handler(state);
361		}
362	339
363		WRITE_LINE_MEMBER(v53_base_device::tcu_out1_trampoline_cb)
364		{
365		m_out1_handler(state);
366		}
367	340
368		WRITE_LINE_MEMBER(v53_base_device::tcu_out2_trampoline_cb)
369		{
370		m_out2_handler(state);
371		}
372	341
373
374
375	342	/*** DMA ***/
376	343
377	344	// could be wrong / nonexistent
378		WRITE_LINE_MEMBER(v53_base_device::dreq0_trampoline_w)
	345	WRITE_LINE_MEMBER(v53_base_device::dreq0_w)
379	346	{
380	347	if (!(m_SCTL & 0x02))
381	348	{
r244880	r244881
387	354	}
388	355	}
389	356
390		WRITE_LINE_MEMBER(v53_base_device::dreq1_trampoline_w)
	357	WRITE_LINE_MEMBER(v53_base_device::dreq1_w)
391	358	{
392	359	if (!(m_SCTL & 0x02))
393	360	{
r244880	r244881
399	366	}
400	367	}
401	368
402		WRITE_LINE_MEMBER(v53_base_device::dreq2_trampoline_w)
	369	WRITE_LINE_MEMBER(v53_base_device::dreq2_w)
403	370	{
404	371	if (!(m_SCTL & 0x02))
405	372	{
r244880	r244881
411	378	}
412	379	}
413	380
414		WRITE_LINE_MEMBER(v53_base_device::dreq3_trampoline_w)
	381	WRITE_LINE_MEMBER(v53_base_device::dreq3_w)
415	382	{
416	383	if (!(m_SCTL & 0x02))
417	384	{
r244880	r244881
423	390	}
424	391	}
425	392
426		WRITE_LINE_MEMBER(v53_base_device::hack_trampoline_w)
	393	WRITE_LINE_MEMBER(v53_base_device::hack_w)
427	394	{
428	395	if (!(m_SCTL & 0x02))
429	396	{
r244880	r244881
431	398	}
432	399	else
433	400	{
434		printf("v53: hack_trampoline_w not in 71071mode\n");
	401	printf("v53: hack_w not in 71071mode\n");
435	402	}
436	403	}
437	404
r244880	r244881
472	439	//   AM_RANGE(0xfffe, 0xffff) // (reserved     ,  0xff00) // 0xffff
473	440	ADDRESS_MAP_END
474	441
475		WRITE_LINE_MEMBER(v53_base_device::dma_hrq_changed)
476		{
477		// pass this back to the driver? / expose externally?
478		m_v53dmau->hack_w(state);
479		}
480	442
481		WRITE8_MEMBER(v53_base_device::dma_io_3_w)
482		{
483		//   logerror("dma_io_3_w %02x\n", data);
484		}
485	443
486		READ8_MEMBER(v53_base_device::dma_memin_r)
487		{
488		UINT8 ret = rand();
489		//   logerror("dma_memin_r offset %08x %02x\n", offset, ret);
490		return ret;
491		}
492	444
493	445	READ8_MEMBER(v53_base_device::get_pic_ack)
494	446	{
r244880	r244881
510	462	MCFG_PIT8253_OUT1_HANDLER(WRITELINE( v53_base_device, tcu_out1_trampoline_cb ))
511	463	MCFG_PIT8253_OUT2_HANDLER(WRITELINE( v53_base_device, tcu_out2_trampoline_cb ))
512	464
513
514	465	MCFG_DEVICE_ADD("upd71071dma", V53_DMAU, 4000000)
515		MCFG_I8237_OUT_HREQ_CB(WRITELINE(v53_base_device, dma_hrq_changed))
516		MCFG_I8237_OUT_IOW_3_CB(WRITE8(v53_base_device, dma_io_3_w))
517		MCFG_I8237_IN_MEMR_CB(READ8(v53_base_device, dma_memin_r))
	466	MCFG_AM9517A_OUT_HREQ_CB(WRITELINE(v53_base_device, hreq_trampoline_cb))
	467	MCFG_AM9517A_OUT_EOP_CB(WRITELINE(v53_base_device, eop_trampoline_cb))
	468	MCFG_AM9517A_IN_MEMR_CB(READ8(v53_base_device, dma_memr_trampoline_r))
	469	MCFG_AM9517A_OUT_MEMW_CB(WRITE8(v53_base_device, dma_memw_trampoline_w))
	470	MCFG_AM9517A_IN_IOR_0_CB(READ8(v53_base_device, dma_io_0_trampoline_r))
	471	MCFG_AM9517A_IN_IOR_1_CB(READ8(v53_base_device, dma_io_1_trampoline_r))
	472	MCFG_AM9517A_IN_IOR_2_CB(READ8(v53_base_device, dma_io_2_trampoline_r))
	473	MCFG_AM9517A_IN_IOR_3_CB(READ8(v53_base_device, dma_io_3_trampoline_r))
	474	MCFG_AM9517A_OUT_IOW_0_CB(WRITE8(v53_base_device, dma_io_0_trampoline_w))
	475	MCFG_AM9517A_OUT_IOW_1_CB(WRITE8(v53_base_device, dma_io_1_trampoline_w))
	476	MCFG_AM9517A_OUT_IOW_2_CB(WRITE8(v53_base_device, dma_io_2_trampoline_w))
	477	MCFG_AM9517A_OUT_IOW_3_CB(WRITE8(v53_base_device, dma_io_3_trampoline_w))
	478	MCFG_AM9517A_OUT_DACK_0_CB(WRITELINE(v53_base_device, dma_dack0_trampoline_w))
	479	MCFG_AM9517A_OUT_DACK_1_CB(WRITELINE(v53_base_device, dma_dack1_trampoline_w))
	480	MCFG_AM9517A_OUT_DACK_2_CB(WRITELINE(v53_base_device, dma_dack2_trampoline_w))
	481	MCFG_AM9517A_OUT_DACK_3_CB(WRITELINE(v53_base_device, dma_dack3_trampoline_w))
	482
518	483
519
520	484	MCFG_PIC8259_ADD( "upd71059pic", WRITELINE(v53_base_device, upd71059_irq_w), VCC, READ8(v53_base_device,get_pic_ack))
521	485
522	486	MCFG_DEVICE_ADD("v53scu", V53_SCU, 0)
r244880	r244881
554	518	// TCU
555	519	m_out0_handler(*this),
556	520	m_out1_handler(*this),
557		m_out2_handler(*this)
	521	m_out2_handler(*this),
	522	// DMAU
	523	m_out_hreq_cb(*this),
	524	m_out_eop_cb(*this),
	525	m_in_memr_cb(*this),
	526	m_out_memw_cb(*this),
	527	m_in_ior_0_cb(*this),
	528	m_in_ior_1_cb(*this),
	529	m_in_ior_2_cb(*this),
	530	m_in_ior_3_cb(*this),
	531	m_out_iow_0_cb(*this),
	532	m_out_iow_1_cb(*this),
	533	m_out_iow_2_cb(*this),
	534	m_out_iow_3_cb(*this),
	535	m_out_dack_0_cb(*this),
	536	m_out_dack_1_cb(*this),
	537	m_out_dack_2_cb(*this),
	538	m_out_dack_3_cb(*this)
558	539	{
559	540	}
560	541

trunk/src/emu/cpu/nec/v53.h

r244880	r244881
50	50	#define MCFG_V53_TCU_OUT2_HANDLER(_devcb) \
51	51	devcb = &v53_base_device::set_out2_handler(*device, DEVCB_##_devcb);
52	52
	53	// DMAU
53	54
	55	#define MCFG_V53_DMAU_OUT_HREQ_CB(_devcb) \
	56	devcb = &v53_base_device::set_out_hreq_callback(*device, DEVCB_##_devcb);
54	57
	58	#define MCFG_V53_DMAU_OUT_EOP_CB(_devcb) \
	59	devcb = &v53_base_device::set_out_eop_callback(*device, DEVCB_##_devcb);
	60
	61	#define MCFG_V53_DMAU_IN_MEMR_CB(_devcb) \
	62	devcb = &v53_base_device::set_in_memr_callback(*device, DEVCB_##_devcb);
	63
	64	#define MCFG_V53_DMAU_OUT_MEMW_CB(_devcb) \
	65	devcb = &v53_base_device::set_out_memw_callback(*device, DEVCB_##_devcb);
	66
	67	#define MCFG_V53_DMAU_IN_IOR_0_CB(_devcb) \
	68	devcb = &v53_base_device::set_in_ior_0_callback(*device, DEVCB_##_devcb);
	69
	70	#define MCFG_V53_DMAU_IN_IOR_1_CB(_devcb) \
	71	devcb = &v53_base_device::set_in_ior_1_callback(*device, DEVCB_##_devcb);
	72
	73	#define MCFG_V53_DMAU_IN_IOR_2_CB(_devcb) \
	74	devcb = &v53_base_device::set_in_ior_2_callback(*device, DEVCB_##_devcb);
	75
	76	#define MCFG_V53_DMAU_IN_IOR_3_CB(_devcb) \
	77	devcb = &v53_base_device::set_in_ior_3_callback(*device, DEVCB_##_devcb);
	78
	79	#define MCFG_V53_DMAU_OUT_IOW_0_CB(_devcb) \
	80	devcb = &v53_base_device::set_out_iow_0_callback(*device, DEVCB_##_devcb);
	81
	82	#define MCFG_V53_DMAU_OUT_IOW_1_CB(_devcb) \
	83	devcb = &v53_base_device::set_out_iow_1_callback(*device, DEVCB_##_devcb);
	84
	85	#define MCFG_V53_DMAU_OUT_IOW_2_CB(_devcb) \
	86	devcb = &v53_base_device::set_out_iow_2_callback(*device, DEVCB_##_devcb);
	87
	88	#define MCFG_V53_DMAU_OUT_IOW_3_CB(_devcb) \
	89	devcb = &v53_base_device::set_out_iow_3_callback(*device, DEVCB_##_devcb);
	90
	91	#define MCFG_V53_DMAU_OUT_DACK_0_CB(_devcb) \
	92	devcb = &v53_base_device::set_out_dack_0_callback(*device, DEVCB_##_devcb);
	93
	94	#define MCFG_V53_DMAU_OUT_DACK_1_CB(_devcb) \
	95	devcb = &v53_base_device::set_out_dack_1_callback(*device, DEVCB_##_devcb);
	96
	97	#define MCFG_V53_DMAU_OUT_DACK_2_CB(_devcb) \
	98	devcb = &v53_base_device::set_out_dack_2_callback(*device, DEVCB_##_devcb);
	99
	100	#define MCFG_V53_DMAU_OUT_DACK_3_CB(_devcb) \
	101	devcb = &v53_base_device::set_out_dack_3_callback(*device, DEVCB_##_devcb);
	102
	103
	104
55	105	class v53_base_device : public nec_common_device
56	106	{
57	107	public:
r244880	r244881
88	138	UINT8 m_DULA;
89	139	UINT8 m_OPHA;
90	140
91		// TCU
92
93
94	141	// SCU
95	142	DECLARE_READ8_MEMBER(scu_simk_r);
96	143	DECLARE_WRITE8_MEMBER(scu_simk_w);
r244880	r244881
102	149	template<class _Object> static devcb_base &set_txrdy_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_txrdy_handler.set_callback(object); }
103	150	template<class _Object> static devcb_base &set_txempty_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_txempty_handler.set_callback(object); }
104	151	template<class _Object> static devcb_base &set_syndet_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_syndet_handler.set_callback(object); }
105		DECLARE_WRITE_LINE_MEMBER(scu_txd_trampoline_cb);
106		DECLARE_WRITE_LINE_MEMBER(scu_dtr_trampoline_cb);
107		DECLARE_WRITE_LINE_MEMBER(scu_rts_trampoline_cb);
108		DECLARE_WRITE_LINE_MEMBER(scu_rxrdy_trampoline_cb);
109		DECLARE_WRITE_LINE_MEMBER(scu_txrdy_trampoline_cb);
110		DECLARE_WRITE_LINE_MEMBER(scu_txempty_trampoline_cb);
111		DECLARE_WRITE_LINE_MEMBER(scu_syndet_trampoline_cb);
	152	DECLARE_WRITE_LINE_MEMBER(scu_txd_trampoline_cb) { m_txd_handler(state); }
	153	DECLARE_WRITE_LINE_MEMBER(scu_dtr_trampoline_cb) { m_dtr_handler(state); }
	154	DECLARE_WRITE_LINE_MEMBER(scu_rts_trampoline_cb) {   m_rts_handler(state); }
	155	DECLARE_WRITE_LINE_MEMBER(scu_rxrdy_trampoline_cb) { m_rxrdy_handler(state); } /* should we mask this here based on m_simk? it can mask the interrupt */
	156	DECLARE_WRITE_LINE_MEMBER(scu_txrdy_trampoline_cb) { m_txrdy_handler(state); } /* should we mask this here based on m_simk? it can mask the interrupt */
	157	DECLARE_WRITE_LINE_MEMBER(scu_txempty_trampoline_cb) {   m_txempty_handler(state); }
	158	DECLARE_WRITE_LINE_MEMBER(scu_syndet_trampoline_cb) { m_syndet_handler(state); }
112	159
113	160	// TCU
114	161	DECLARE_READ8_MEMBER(tmu_tst0_r);
r244880	r244881
124	171	template<class _Object> static devcb_base &set_out0_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out0_handler.set_callback(object); }
125	172	template<class _Object> static devcb_base &set_out1_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out1_handler.set_callback(object); }
126	173	template<class _Object> static devcb_base &set_out2_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out2_handler.set_callback(object); }
127		DECLARE_WRITE_LINE_MEMBER(tcu_out0_trampoline_cb);
128		DECLARE_WRITE_LINE_MEMBER(tcu_out1_trampoline_cb);
129		DECLARE_WRITE_LINE_MEMBER(tcu_out2_trampoline_cb);
	174	DECLARE_WRITE_LINE_MEMBER(tcu_out0_trampoline_cb){ m_out0_handler(state); }
	175	DECLARE_WRITE_LINE_MEMBER(tcu_out1_trampoline_cb){ m_out1_handler(state); }
	176	DECLARE_WRITE_LINE_MEMBER(tcu_out2_trampoline_cb){ m_out2_handler(state); }
130	177
131
	178	// DMAU
	179	template<class _Object> static devcb_base &set_out_hreq_callback(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out_hreq_cb.set_callback(object); }
	180	template<class _Object> static devcb_base &set_out_eop_callback(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out_eop_cb.set_callback(object); }
	181	template<class _Object> static devcb_base &set_in_memr_callback(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_in_memr_cb.set_callback(object); }
	182	template<class _Object> static devcb_base &set_out_memw_callback(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out_memw_cb.set_callback(object); }
	183	template<class _Object> static devcb_base &set_in_ior_0_callback(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_in_ior_0_cb.set_callback(object); }
	184	template<class _Object> static devcb_base &set_in_ior_1_callback(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_in_ior_1_cb.set_callback(object); }
	185	template<class _Object> static devcb_base &set_in_ior_2_callback(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_in_ior_2_cb.set_callback(object); }
	186	template<class _Object> static devcb_base &set_in_ior_3_callback(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_in_ior_3_cb.set_callback(object); }
	187	template<class _Object> static devcb_base &set_out_iow_0_callback(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out_iow_0_cb.set_callback(object); }
	188	template<class _Object> static devcb_base &set_out_iow_1_callback(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out_iow_1_cb.set_callback(object); }
	189	template<class _Object> static devcb_base &set_out_iow_2_callback(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out_iow_2_cb.set_callback(object); }
	190	template<class _Object> static devcb_base &set_out_iow_3_callback(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out_iow_3_cb.set_callback(object); }
	191	template<class _Object> static devcb_base &set_out_dack_0_callback(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out_dack_0_cb.set_callback(object); }
	192	template<class _Object> static devcb_base &set_out_dack_1_callback(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out_dack_1_cb.set_callback(object); }
	193	template<class _Object> static devcb_base &set_out_dack_2_callback(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out_dack_2_cb.set_callback(object); }
	194	template<class _Object> static devcb_base &set_out_dack_3_callback(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out_dack_3_cb.set_callback(object); }
	195	DECLARE_WRITE_LINE_MEMBER(hreq_trampoline_cb) { m_out_hreq_cb(state); }
	196	DECLARE_WRITE_LINE_MEMBER(eop_trampoline_cb) { m_out_eop_cb(state); }
	197	DECLARE_READ8_MEMBER(dma_memr_trampoline_r) { return m_in_memr_cb(space, offset); }
	198	DECLARE_WRITE8_MEMBER(dma_memw_trampoline_w) {   m_out_memw_cb(space, offset, data); }
	199	DECLARE_READ8_MEMBER(dma_io_0_trampoline_r) { return m_in_ior_0_cb(space, offset); }
	200	DECLARE_READ8_MEMBER(dma_io_1_trampoline_r) { return m_in_ior_1_cb(space, offset); }
	201	DECLARE_READ8_MEMBER(dma_io_2_trampoline_r) { return m_in_ior_2_cb(space, offset); }
	202	DECLARE_READ8_MEMBER(dma_io_3_trampoline_r) { return m_in_ior_3_cb(space, offset); }
	203	DECLARE_WRITE8_MEMBER(dma_io_0_trampoline_w) { m_out_iow_0_cb(space, offset, data); }
	204	DECLARE_WRITE8_MEMBER(dma_io_1_trampoline_w) { m_out_iow_1_cb(space, offset, data); }
	205	DECLARE_WRITE8_MEMBER(dma_io_2_trampoline_w) { m_out_iow_2_cb(space, offset, data); }
	206	DECLARE_WRITE8_MEMBER(dma_io_3_trampoline_w) { m_out_iow_3_cb(space, offset, data); }
	207	DECLARE_WRITE_LINE_MEMBER(dma_dack0_trampoline_w) {   m_out_dack_0_cb(state); }
	208	DECLARE_WRITE_LINE_MEMBER(dma_dack1_trampoline_w) {   m_out_dack_1_cb(state); }
	209	DECLARE_WRITE_LINE_MEMBER(dma_dack2_trampoline_w) {   m_out_dack_2_cb(state); }
	210	DECLARE_WRITE_LINE_MEMBER(dma_dack3_trampoline_w) {   m_out_dack_3_cb(state); }
	211
	212
	213	DECLARE_WRITE_LINE_MEMBER(dreq0_w);
	214	DECLARE_WRITE_LINE_MEMBER(dreq1_w);
	215	DECLARE_WRITE_LINE_MEMBER(dreq2_w);
	216	DECLARE_WRITE_LINE_MEMBER(dreq3_w);
	217	DECLARE_WRITE_LINE_MEMBER(hack_w);
	218
	219
	220
132	221	void install_peripheral_io();
133	222
134	223	const address_space_config m_io_space_config;
r244880	r244881
142	231	}
143	232	}
144	233
145		required_device<pit8253_device> m_v53tcu;
146		required_device<upd71071_v53_device> m_v53dmau;
147		required_device<pic8259_device> m_v53icu;
148		required_device<v53_scu_device> m_v53scu;
149	234
150		DECLARE_WRITE_LINE_MEMBER(dreq0_trampoline_w);
151		DECLARE_WRITE_LINE_MEMBER(dreq1_trampoline_w);
152		DECLARE_WRITE_LINE_MEMBER(dreq2_trampoline_w);
153		DECLARE_WRITE_LINE_MEMBER(dreq3_trampoline_w);
154		DECLARE_WRITE_LINE_MEMBER(hack_trampoline_w);
155	235
156		DECLARE_WRITE_LINE_MEMBER(dma_hrq_changed);
157		DECLARE_WRITE8_MEMBER(dma_io_3_w);
158		DECLARE_READ8_MEMBER(dma_memin_r);
159	236
160	237	DECLARE_READ8_MEMBER(get_pic_ack);
161	238	DECLARE_WRITE_LINE_MEMBER(upd71059_irq_w);
r244880	r244881
165	242	virtual machine_config_constructor device_mconfig_additions() const;
166	243	virtual void device_start();
167	244	virtual void device_reset();
	245
	246	required_device<pit8253_device> m_v53tcu;
	247	required_device<upd71071_v53_device> m_v53dmau;
	248	required_device<pic8259_device> m_v53icu;
	249	required_device<v53_scu_device> m_v53scu;
168	250
169	251	// SCU
170	252	devcb_write_line m_txd_handler;
r244880	r244881
182	264	devcb_write_line m_out0_handler;
183	265	devcb_write_line m_out1_handler;
184	266	devcb_write_line m_out2_handler;
	267
	268
	269	// DMAU
	270	devcb_write_line   m_out_hreq_cb;
	271	devcb_write_line   m_out_eop_cb;
	272	devcb_read8        m_in_memr_cb;
	273	devcb_write8       m_out_memw_cb;
	274	devcb_read8        m_in_ior_0_cb;
	275	devcb_read8        m_in_ior_1_cb;
	276	devcb_read8        m_in_ior_2_cb;
	277	devcb_read8        m_in_ior_3_cb;
	278	devcb_write8       m_out_iow_0_cb;
	279	devcb_write8       m_out_iow_1_cb;
	280	devcb_write8       m_out_iow_2_cb;
	281	devcb_write8       m_out_iow_3_cb;
	282	devcb_write_line   m_out_dack_0_cb;
	283	devcb_write_line   m_out_dack_1_cb;
	284	devcb_write_line   m_out_dack_2_cb;
	285	devcb_write_line   m_out_dack_3_cb;
	286
	287
	288
	289
185	290	};
186	291
187	292

trunk/src/mame/audio/hng64.c

r244880	r244881
153	153	// seems to one or more of the DMARQ on the V53, writes here when it expects DMA channel 3 to transfer ~0x20 bytes just after startup
154	154
155	155
156		m_audiocpu->dreq3_trampoline_w(data&1);
157		//   m_audiocpu->hack_trampoline_w(1);
	156	m_audiocpu->dreq3_w(data&1);
	157	//   m_audiocpu->hack_w(1);
158	158
159	159	}
160	160
r244880	r244881
162	162	AM_RANGE(0x0008, 0x0009) AM_WRITE( hng64_sound_port_0008_w )
163	163	ADDRESS_MAP_END
164	164
	165	WRITE_LINE_MEMBER(hng64_state::dma_hreq_cb)
	166	{
	167	m_audiocpu->hack_w(1);
	168	}
165	169
	170	READ8_MEMBER(hng64_state::dma_memr_cb)
	171	{
	172	return m_audiocpu->space(AS_PROGRAM).read_byte(offset);;
	173	}
	174
	175	WRITE8_MEMBER(hng64_state::dma_iow3_cb)
	176	{
	177	// currently it reads a block of 0x20 '0x00' values from a very specific block of RAM where there is a 0x20 space in the data and transfers them repeatedly, I assume
	178	// this is some kind of buffer for the audio or DSP and eventually will be populated with other values...
	179	// if this comes to life maybe something interesting is happening!
	180	if (data!=0x00) printf("dma_iow3_cb %02x\n", data);
	181	}
	182
	183	WRITE_LINE_MEMBER(hng64_state::tcu_tm0_cb)
	184	{
	185	// this goes high once near startup
	186	printf("tcu_tm0_cb %02x\n", state);
	187	}
	188
	189	WRITE_LINE_MEMBER(hng64_state::tcu_tm1_cb)
	190	{
	191	// these are very active, maybe they feed back into the v53 via one of the IRQ pins?  TM2 toggles more rapidly than TM1
	192	//   printf("tcu_tm1_cb %02x\n", state);
	193	}
	194
	195	WRITE_LINE_MEMBER(hng64_state::tcu_tm2_cb)
	196	{
	197	// these are very active, maybe they feed back into the v53 via one of the IRQ pins?  TM2 toggles more rapidly than TM1
	198	//   printf("tcu_tm2_cb %02x\n", state);
	199	}
	200
	201
	202
166	203	MACHINE_CONFIG_FRAGMENT( hng64_audio )
167	204	MCFG_CPU_ADD("audiocpu", V53A, 16000000)              // V53A, 16? mhz!
168	205	MCFG_CPU_PROGRAM_MAP(hng_sound_map)
169	206	MCFG_CPU_IO_MAP(hng_sound_io)
	207	MCFG_V53_DMAU_OUT_HREQ_CB(WRITELINE(hng64_state, dma_hreq_cb))
	208	MCFG_V53_DMAU_IN_MEMR_CB(READ8(hng64_state, dma_memr_cb))
	209	MCFG_V53_DMAU_OUT_IOW_3_CB(WRITE8(hng64_state,dma_iow3_cb))
	210
	211	MCFG_V53_TCU_OUT0_HANDLER(WRITELINE(hng64_state, tcu_tm0_cb))
	212	MCFG_V53_TCU_OUT1_HANDLER(WRITELINE(hng64_state, tcu_tm1_cb))
	213	MCFG_V53_TCU_OUT2_HANDLER(WRITELINE(hng64_state, tcu_tm2_cb))
	214
170	215	MACHINE_CONFIG_END
171	216
172	217

trunk/src/mame/includes/hng64.h

r244880	r244881
354	354	int m_vertsrom_size;
355	355	void reset_sound();
356	356	void reset_net();
357		WRITE16_MEMBER(hng64_sound_port_0008_w);
	357	DECLARE_WRITE16_MEMBER(hng64_sound_port_0008_w);
358	358
	359	DECLARE_WRITE_LINE_MEMBER(dma_hreq_cb);
	360	DECLARE_READ8_MEMBER(dma_memr_cb);
	361	DECLARE_WRITE8_MEMBER(dma_iow3_cb);
	362	WRITE_LINE_MEMBER(tcu_tm0_cb);
	363	WRITE_LINE_MEMBER(tcu_tm1_cb);
	364	WRITE_LINE_MEMBER(tcu_tm2_cb);
	365
359	366	};
360	367

https://github.com/mamedev/mame/commit/6d56aa957cbe4fba97189195f46028140d226997

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