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r36185 Monday 2nd March, 2015 at 16:53:20 UTC by hap
removed PIC16 mcu fake io memory map

[src/emu/cpu/pic16c5x]	pic16c5x.c pic16c5x.h
[src/mame/drivers]	bingor.c blackt96.c drgnmst.c kickgoal.c megaphx.c midzeus.c playmark.c
[src/mame/includes]	drgnmst.h midzeus.h playmark.h

trunk/src/emu/cpu/pic16c5x/pic16c5x.c

r244696	r244697
110	110	, ( ( program_width == 9 ) ? ADDRESS_MAP_NAME(pic16c5x_rom_9) : ( ( program_width == 10 ) ? ADDRESS_MAP_NAME(pic16c5x_rom_10) : ADDRESS_MAP_NAME(pic16c5x_rom_11) )))
111	111	, m_data_config("data", ENDIANNESS_LITTLE, 8, data_width, 0
112	112	, ( ( data_width == 5 ) ? ADDRESS_MAP_NAME(pic16c5x_ram_5) : ADDRESS_MAP_NAME(pic16c5x_ram_7) ) )
113		, m_io_config("io", ENDIANNESS_LITTLE, 8, 5, 0)
114	113	, m_reset_vector((program_width == 9) ? 0x1ff : ((program_width == 10) ? 0x3ff : 0x7ff))
115	114	, m_picmodel(picmodel)
	115	, m_temp_config(0)
116	116	, m_picRAMmask((data_width == 5) ? 0x1f : 0x7f)
	117	, m_read_a(*this)
	118	, m_read_b(*this)
	119	, m_read_c(*this)
	120	, m_write_a(*this)
	121	, m_write_b(*this)
	122	, m_write_c(*this)
	123	, m_read_t0(*this)
117	124	{
118	125	}
119	126
r244696	r244697
161	168	#define PIC16C5x_RDOP(A)         (m_direct->read_decrypted_word((A)<<1))
162	169	#define PIC16C5x_RAM_RDMEM(A)    ((UINT8)m_data->read_byte(A))
163	170	#define PIC16C5x_RAM_WRMEM(A,V)  (m_data->write_byte(A,V))
164		#define PIC16C5x_In(Port)        ((UINT8)m_io->read_byte((Port)))
165		#define PIC16C5x_Out(Port,Value) (m_io->write_byte((Port),Value))
166		/************  Read the state of the T0 Clock input signal  ************/
167		#define PIC16C5x_T0_In           (m_io->read_byte(PIC16C5x_T0))
168	171
169	172	#define M_RDRAM(A)      (((A) < 8) ? m_internalram[A] : PIC16C5x_RAM_RDMEM(A))
170	173	#define M_WRTRAM(A,V)   do { if ((A) < 8) m_internalram[A] = (V); else PIC16C5x_RAM_WRMEM(A,V); } while (0)
171	174	#define M_RDOP(A)       PIC16C5x_RDOP(A)
172		#define P_IN(A)         PIC16C5x_In(A)
173		#define P_OUT(A,V)      PIC16C5x_Out(A,V)
174		#define S_T0_IN         PIC16C5x_T0_In
175	175	#define ADDR_MASK       0x7ff
176	176
177	177
r244696	r244697
332	332	break;
333	333	case 04:    data = (FSR | (UINT8)(~m_picRAMmask));
334	334	break;
335		case 05:    data = P_IN(0);
	335	case 05:    data = m_read_a(PIC16C5x_PORTA, 0xff);
336	336	data &= m_TRISA;
337	337	data |= ((UINT8)(~m_TRISA) & PORTA);
338	338	data &= 0x0f;       /* 4-bit port (only lower 4 bits used) */
339	339	break;
340		case 06:    data = P_IN(1);
	340	case 06:    data = m_read_b(PIC16C5x_PORTB, 0xff);
341	341	data &= m_TRISB;
342	342	data |= ((UINT8)(~m_TRISB) & PORTB);
343	343	break;
344	344	case 07:    if ((m_picmodel == 0x16C55) || (m_picmodel == 0x16C57)) {
345		data = P_IN(2);
	345	data = m_read_c(PIC16C5x_PORTC, 0xff);
346	346	data &= m_TRISC;
347	347	data |= ((UINT8)(~m_TRISC) & PORTC);
348	348	}
r244696	r244697
384	384	case 04:    FSR = (data | (UINT8)(~m_picRAMmask));
385	385	break;
386	386	case 05:    data &= 0x0f;       /* 4-bit port (only lower 4 bits used) */
387		P_OUT(0,data & (UINT8)(~m_TRISA)); PORTA = data;
	387	m_write_a(PIC16C5x_PORTA, data & (UINT8)(~m_TRISA), 0xff);
	388	PORTA = data;
388	389	break;
389		case 06:    P_OUT(1,data & (UINT8)(~m_TRISB)); PORTB = data;
	390	case 06:    m_write_b(PIC16C5x_PORTB, data & (UINT8)(~m_TRISB), 0xff);
	391	PORTB = data;
390	392	break;
391	393	case 07:    if ((m_picmodel == 0x16C55) || (m_picmodel == 0x16C57)) {
392		P_OUT(2,data & (UINT8)(~m_TRISC));
	394	m_write_c(PIC16C5x_PORTC, data & (UINT8)(~m_TRISC), 0xff);
393	395	PORTC = data;
394	396	}
395	397	else {      /* PIC16C54, PIC16C56, PIC16C58 */
r244696	r244697
665	667	switch(m_opcode.b.l & 0x7)
666	668	{
667	669	case 05:    if   (m_TRISA == m_W) break;
668		else { m_TRISA = m_W | 0xf0; P_OUT(0,PORTA & (UINT8)(~m_TRISA) & 0x0f); break; }
	670	else { m_TRISA = m_W | 0xf0; m_write_a(PIC16C5x_PORTA, PORTA & (UINT8)(~m_TRISA) & 0x0f, 0xff); break; }
669	671	case 06:    if   (m_TRISB == m_W) break;
670		else { m_TRISB = m_W; P_OUT(1,PORTB & (UINT8)(~m_TRISB)); break; }
	672	else { m_TRISB = m_W; m_write_b(PIC16C5x_PORTB, PORTB & (UINT8)(~m_TRISB), 0xff); break; }
671	673	case 07:    if ((m_picmodel == 0x16C55) || (m_picmodel == 0x16C57)) {
672	674	if   (m_TRISC == m_W) break;
673		else { m_TRISC = m_W; P_OUT(2,PORTC & (UINT8)(~m_TRISC)); break; }
	675	else { m_TRISC = m_W; m_write_c(PIC16C5x_PORTC, PORTC & (UINT8)(~m_TRISC), 0xff); break; }
674	676	}
675	677	else {
676	678	illegal(); break;
r244696	r244697
783	785	*  Inits CPU emulation
784	786	****************************************************************************/
785	787
	788	enum
	789	{
	790	PIC16C5x_PC=1, PIC16C5x_STK0, PIC16C5x_STK1, PIC16C5x_FSR,
	791	PIC16C5x_W,    PIC16C5x_ALU,  PIC16C5x_STR,  PIC16C5x_OPT,
	792	PIC16C5x_TMR0, PIC16C5x_PRTA, PIC16C5x_PRTB, PIC16C5x_PRTC,
	793	PIC16C5x_WDT,  PIC16C5x_TRSA, PIC16C5x_TRSB, PIC16C5x_TRSC,
	794	PIC16C5x_PSCL
	795	};
	796
786	797	void pic16c5x_device::device_start()
787	798	{
788	799	m_program = &space(AS_PROGRAM);
789	800	m_direct = &m_program->direct();
790	801	m_data = &space(AS_DATA);
791		m_io = &space(AS_IO);
	802
	803	m_read_a.resolve_safe(0);
	804	m_read_b.resolve_safe(0);
	805	m_read_c.resolve_safe(0);
	806	m_write_a.resolve_safe();
	807	m_write_b.resolve_safe();
	808	m_write_c.resolve_safe();
	809	m_read_t0.resolve_safe(0);
792	810
793	811	/* ensure the internal ram pointers are set before get_info is called */
794	812	update_internalram_ptr();
r244696	r244697
955	973	pic16c5x_reset_regs();
956	974	}
957	975
958		void pic16c5x_device::pic16c5x_set_config(int data)
	976	void pic16c5x_device::pic16c5x_set_config(UINT16 data)
959	977	{
960	978	logerror("Writing %04x to the PIC16C5x config register\n",data);
961		m_temp_config = (data & 0xfff);
	979	m_temp_config = data;
962	980	}
963	981
964	982
r244696	r244697
1071	1089	}
1072	1090
1073	1091	if (T0CS) {                     /* Count mode */
1074		T0_in = S_T0_IN;
1075		if (T0_in) T0_in = 1;
	1092	T0_in = m_read_t0() ? 1 : 0;
1076	1093	if (T0SE) {                 /* Count falling edge T0 input */
1077	1094	if (FALLING_EDGE_T0) {
1078	1095	pic16c5x_update_timer(1);

trunk/src/emu/cpu/pic16c5x/pic16c5x.h

r244696	r244697
15	15	#define __PIC16C5X_H__
16	16
17	17
18
19
20		/**************************************************************************
21		*  Internal Clock divisor
22		*
23		*  External Clock is divided internally by 4 for the instruction cycle
24		*  times. (Each instruction cycle passes through 4 machine states). This
25		*  is handled by the cpu execution engine.
26		*/
27
	18	// i/o ports
28	19	enum
29	20	{
30		PIC16C5x_PC=1, PIC16C5x_STK0, PIC16C5x_STK1, PIC16C5x_FSR,
31		PIC16C5x_W,    PIC16C5x_ALU,  PIC16C5x_STR,  PIC16C5x_OPT,
32		PIC16C5x_TMR0, PIC16C5x_PRTA, PIC16C5x_PRTB, PIC16C5x_PRTC,
33		PIC16C5x_WDT,  PIC16C5x_TRSA, PIC16C5x_TRSB, PIC16C5x_TRSC,
34		PIC16C5x_PSCL
	21	PIC16C5x_PORTA = 0,
	22	PIC16C5x_PORTB,
	23	PIC16C5x_PORTC
35	24	};
36	25
37		#define PIC16C5x_T0     0x10
	26	// port a, 4 bits, 2-way
	27	#define MCFG_PIC16C5x_READ_A_CB(_devcb) \
	28	pic16c5x_device::set_read_a_callback(*device, DEVCB_##_devcb);
	29	#define MCFG_PIC16C5x_WRITE_A_CB(_devcb) \
	30	pic16c5x_device::set_write_a_callback(*device, DEVCB_##_devcb);
38	31
	32	// port b, 8 bits, 2-way
	33	#define MCFG_PIC16C5x_READ_B_CB(_devcb) \
	34	pic16c5x_device::set_read_b_callback(*device, DEVCB_##_devcb);
	35	#define MCFG_PIC16C5x_WRITE_B_CB(_devcb) \
	36	pic16c5x_device::set_write_b_callback(*device, DEVCB_##_devcb);
39	37
	38	// port c, 8 bits, 2-way
	39	#define MCFG_PIC16C5x_READ_C_CB(_devcb) \
	40	pic16c5x_device::set_read_c_callback(*device, DEVCB_##_devcb);
	41	#define MCFG_PIC16C5x_WRITE_C_CB(_devcb) \
	42	pic16c5x_device::set_write_c_callback(*device, DEVCB_##_devcb);
	43
	44	// T0 pin (readline)
	45	#define MCFG_PIC16C5x_T0_CB(_devcb) \
	46	pic16c5x_device::set_t0_callback(*device, DEVCB_##_devcb);
	47
	48	// CONFIG register
	49	#define MCFG_PIC16C5x_SET_CONFIG(_data) \
	50	pic16c5x_device::set_config_static(*device, _data);
	51
	52
	53
40	54	extern const device_type PIC16C54;
41	55	extern const device_type PIC16C55;
42	56	extern const device_type PIC16C56;
r244696	r244697
50	64	// construction/destruction
51	65	pic16c5x_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, int program_width, int data_width, int picmodel);
52	66
	67	// static configuration helpers
	68	template<class _Object> static devcb_base &set_read_a_callback(device_t &device, _Object object) { return downcast<pic16c5x_device &>(device).m_read_a.set_callback(object); }
	69	template<class _Object> static devcb_base &set_read_b_callback(device_t &device, _Object object) { return downcast<pic16c5x_device &>(device).m_read_b.set_callback(object); }
	70	template<class _Object> static devcb_base &set_read_c_callback(device_t &device, _Object object) { return downcast<pic16c5x_device &>(device).m_read_c.set_callback(object); }
	71
	72	template<class _Object> static devcb_base &set_write_a_callback(device_t &device, _Object object) { return downcast<pic16c5x_device &>(device).m_write_a.set_callback(object); }
	73	template<class _Object> static devcb_base &set_write_b_callback(device_t &device, _Object object) { return downcast<pic16c5x_device &>(device).m_write_b.set_callback(object); }
	74	template<class _Object> static devcb_base &set_write_c_callback(device_t &device, _Object object) { return downcast<pic16c5x_device &>(device).m_write_c.set_callback(object); }
	75
	76	template<class _Object> static devcb_base &set_t0_callback(device_t &device, _Object object) { return downcast<pic16c5x_device &>(device).m_read_t0.set_callback(object); }
	77
53	78	/****************************************************************************
54	79	*  Function to configure the CONFIG register. This is actually hard-wired
55	80	*  during ROM programming, so should be called in the driver INIT, with
56	81	*  the value if known (available in HEX dumps of the ROM).
57	82	*/
58		void pic16c5x_set_config(int data);
	83	void pic16c5x_set_config(UINT16 data);
	84
	85	// or with a macro
	86	static void set_config_static(device_t &device, UINT16 data) { downcast<pic16c5x_device &>(device).m_temp_config = data; }
59	87
60	88	protected:
61	89	// device-level overrides
r244696	r244697
63	91	virtual void device_reset();
64	92
65	93	// device_execute_interface overrides
	94	/**************************************************************************
	95	*  Internal Clock divisor
	96	*
	97	*  External Clock is divided internally by 4 for the instruction cycle
	98	*  times. (Each instruction cycle passes through 4 machine states). This
	99	*  is handled by the cpu execution engine.
	100	*/
66	101	virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 4 - 1) / 4; }
67	102	virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 4); }
68	103	virtual UINT32 execute_min_cycles() const { return 1; }
r244696	r244697
74	109	// device_memory_interface overrides
75	110	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
76	111	{
77		return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ) );
	112	return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL );
78	113	}
79	114
80	115	// device_state_interface overrides
r244696	r244697
90	125	private:
91	126	address_space_config m_program_config;
92	127	address_space_config m_data_config;
93		address_space_config m_io_config;
94	128
95	129	/******************** CPU Internal Registers *******************/
96	130	UINT16  m_PC;
r244696	r244697
121	155	address_space *m_program;
122	156	direct_read_data *m_direct;
123	157	address_space *m_data;
124		address_space *m_io;
	158
	159	// i/o handlers
	160	devcb_read8 m_read_a;
	161	devcb_read8 m_read_b;
	162	devcb_read8 m_read_c;
	163	devcb_write8 m_write_a;
	164	devcb_write8 m_write_b;
	165	devcb_write8 m_write_c;
	166	devcb_read_line m_read_t0;
125	167
126	168	// For debugger
127	169	int m_debugger_temp;

trunk/src/mame/drivers/bingor.c

r244696	r244697
453	453	m_palette(*this, "palette")  { }
454	454
455	455	required_shared_ptr<UINT16> m_blit_ram;
456		DECLARE_READ16_MEMBER(test_r);
457		DECLARE_READ8_MEMBER(test8_r);
458	456	virtual void video_start();
459	457	UINT32 screen_update_bingor(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
460	458	INTERRUPT_GEN_MEMBER(vblank_irq);
r244696	r244697
509	507	return 0;
510	508	}
511	509
512		#if 0
513		READ16_MEMBER(bingor_state::test_r)
514		{
515		return machine().rand();
516		}
517		#endif
518	510
519	511	static ADDRESS_MAP_START( bingor_map, AS_PROGRAM, 16, bingor_state )
520	512	AM_RANGE(0x00000, 0x0ffff) AM_RAM
r244696	r244697
525	517	ADDRESS_MAP_END
526	518
527	519	static ADDRESS_MAP_START( bingor_io, AS_IO, 16, bingor_state )
528		//  AM_RANGE(0x0000, 0x00ff) AM_READ(test_r )
529	520	AM_RANGE(0x0100, 0x0101) AM_DEVWRITE8("saa", saa1099_device, data_w, 0x00ff)
530	521	AM_RANGE(0x0102, 0x0103) AM_DEVWRITE8("saa", saa1099_device, control_w, 0x00ff)
531		//  AM_RANGE(0x0200, 0x0201) AM_READ(test_r )
532	522	ADDRESS_MAP_END
533	523
534		READ8_MEMBER(bingor_state::test8_r)
535		{
536		return machine().rand();
537		}
538	524
539		static ADDRESS_MAP_START( pic_io_map, AS_IO, 8, bingor_state )
540		AM_RANGE(0x00, 0x00) AM_WRITENOP
541		AM_RANGE(0x02, 0x02) AM_READ(test8_r)
542		AM_RANGE(0x10, 0x10) AM_READNOP
543		ADDRESS_MAP_END
544
545	525	static INPUT_PORTS_START( bingor )
546	526	PORT_START("IN0")
547	527	PORT_DIPNAME( 0x0001, 0x0001, "IN0" )
r244696	r244697
631	611	MCFG_CPU_PERIODIC_INT_DRIVER(bingor_state, unk_irq,  30)
632	612
633	613	MCFG_CPU_ADD("pic", PIC16C57, 12000000) //?? Mhz
634		MCFG_CPU_IO_MAP(pic_io_map)
635	614
636
637	615	MCFG_GFXDECODE_ADD("gfxdecode", "palette", bingor)
638	616	//MCFG_NVRAM_ADD_0FILL("nvram")
639	617

trunk/src/mame/drivers/blackt96.c

r244696	r244697
117	117	required_shared_ptr<UINT16> m_spriteram7;
118	118	DECLARE_WRITE16_MEMBER(blackt96_c0000_w);
119	119	DECLARE_WRITE16_MEMBER(blackt96_80000_w);
120		DECLARE_READ8_MEMBER(PIC16C5X_T0_clk_r);
	120	DECLARE_READ_LINE_MEMBER(PIC16C5X_T0_clk_r);
121	121	DECLARE_WRITE8_MEMBER(blackt96_soundio_port00_w);
122	122	DECLARE_READ8_MEMBER(blackt96_soundio_port01_r);
123	123	DECLARE_WRITE8_MEMBER(blackt96_soundio_port01_w);
r244696	r244697
560	560	GFXDECODE_END
561	561
562	562
563		READ8_MEMBER(blackt96_state::PIC16C5X_T0_clk_r)
	563	READ_LINE_MEMBER(blackt96_state::PIC16C5X_T0_clk_r)
564	564	{
565	565	return 0;
566	566	}
r244696	r244697
587	587	{
588	588	}
589	589
590		static ADDRESS_MAP_START( sound_io_map, AS_IO, 8, blackt96_state )
591		AM_RANGE(0x00, 0x00) AM_WRITE(blackt96_soundio_port00_w )
592		AM_RANGE(0x01, 0x01) AM_READWRITE(blackt96_soundio_port01_r, blackt96_soundio_port01_w )
593		AM_RANGE(0x02, 0x02) AM_READWRITE(blackt96_soundio_port02_r, blackt96_soundio_port02_w )
594		AM_RANGE(PIC16C5x_T0, PIC16C5x_T0) AM_READ(PIC16C5X_T0_clk_r)
595		ADDRESS_MAP_END
596	590
597	591
598
599	592	static MACHINE_CONFIG_START( blackt96, blackt96_state )
600	593	MCFG_CPU_ADD("maincpu", M68000, 18000000 /2)
601	594	MCFG_CPU_PROGRAM_MAP(blackt96_map)
602	595	MCFG_CPU_VBLANK_INT_DRIVER("screen", blackt96_state,  irq1_line_hold)
603	596
604	597	MCFG_CPU_ADD("audiocpu", PIC16C57, 8000000) /* ? */
605		MCFG_CPU_IO_MAP(sound_io_map)
	598	MCFG_PIC16C5x_WRITE_A_CB(WRITE8(blackt96_state, blackt96_soundio_port00_w))
	599	MCFG_PIC16C5x_READ_B_CB(READ8(blackt96_state, blackt96_soundio_port01_r))
	600	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(blackt96_state, blackt96_soundio_port01_w))
	601	MCFG_PIC16C5x_READ_C_CB(READ8(blackt96_state, blackt96_soundio_port02_r))
	602	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(blackt96_state, blackt96_soundio_port02_w))
	603	MCFG_PIC16C5x_T0_CB(READLINE(blackt96_state, PIC16C5X_T0_clk_r))
606	604
607	605	MCFG_GFXDECODE_ADD("gfxdecode", "palette", blackt96)
608	606

trunk/src/mame/drivers/drgnmst.c

r244696	r244697
174	174	}
175	175
176	176
177		READ8_MEMBER(drgnmst_state::PIC16C5X_T0_clk_r)
	177	READ_LINE_MEMBER(drgnmst_state::PIC16C5X_T0_clk_r)
178	178	{
179	179	return 0;
180	180	}
r244696	r244697
207	207	ADDRESS_MAP_END
208	208
209	209
210
211		/***************************** PIC16C55 Memory Map **************************/
212
213		/* $000 - 1FF  PIC16C55 Internal Program ROM. Note: code is 12bits wide */
214		/* $000 - 01F  PIC16C55 Internal Data RAM */
215
216		static ADDRESS_MAP_START( drgnmst_sound_io_map, AS_IO, 8, drgnmst_state )
217		AM_RANGE(0x00, 0x00) AM_READWRITE(pic16c5x_port0_r, drgnmst_pcm_banksel_w)  /* 4 bit port */
218		AM_RANGE(0x01, 0x01) AM_READWRITE(drgnmst_snd_command_r, drgnmst_oki_w)
219		AM_RANGE(0x02, 0x02) AM_READWRITE(drgnmst_snd_flag_r, drgnmst_snd_control_w)
220		AM_RANGE(PIC16C5x_T0, PIC16C5x_T0) AM_READ(PIC16C5X_T0_clk_r)
221		ADDRESS_MAP_END
222
223
224
225	210	static INPUT_PORTS_START( drgnmst )
226	211	PORT_START("P1_P2")
227	212	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
r244696	r244697
396	381	MCFG_CPU_VBLANK_INT_DRIVER("screen", drgnmst_state,  irq2_line_hold)
397	382
398	383	MCFG_CPU_ADD("audiocpu", PIC16C55, 32000000/8)  /* Confirmed */
399		/* Program and Data Maps are internal to the MCU */
400		MCFG_CPU_IO_MAP(drgnmst_sound_io_map)
	384	MCFG_PIC16C5x_READ_A_CB(READ8(drgnmst_state, pic16c5x_port0_r))
	385	MCFG_PIC16C5x_WRITE_A_CB(WRITE8(drgnmst_state, drgnmst_pcm_banksel_w))
	386	MCFG_PIC16C5x_READ_B_CB(READ8(drgnmst_state, drgnmst_snd_command_r))
	387	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(drgnmst_state, drgnmst_oki_w))
	388	MCFG_PIC16C5x_READ_C_CB(READ8(drgnmst_state, drgnmst_snd_flag_r))
	389	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(drgnmst_state, drgnmst_snd_control_w))
	390	MCFG_PIC16C5x_T0_CB(READLINE(drgnmst_state, PIC16C5X_T0_clk_r))
401	391
402
403	392	MCFG_GFXDECODE_ADD("gfxdecode", "palette", drgnmst)
404	393
405	394	MCFG_SCREEN_ADD("screen", RASTER)

trunk/src/mame/drivers/kickgoal.c

r244696	r244697
492	492	AM_RANGE(0xff0000, 0xffffff) AM_RAM
493	493	ADDRESS_MAP_END
494	494
495		/***************************** PIC16C57 Memory Map **************************/
496	495
497		/* $000 - 7FF  PIC16C57 Internal Program ROM. Note: code is 12bits wide */
498		/* $000 - 07F  PIC16C57 Internal Data RAM */
499
500		static ADDRESS_MAP_START( kickgoal_sound_io_map, AS_IO, 8, kickgoal_state )
501		/* Unknown without the PIC dump */
502		ADDRESS_MAP_END
503
504		static ADDRESS_MAP_START( actionhw_io_map, AS_IO, 8, kickgoal_state )
505		/* Unknown without the PIC dump */
506		ADDRESS_MAP_END
507
508
509	496	/* INPUT ports ***************************************************************/
510	497
511	498	static INPUT_PORTS_START( kickgoal )
r244696	r244697
646	633	MCFG_CPU_ADD("audiocpu", PIC16C57, 12000000/4)  /* 3MHz ? */
647	634	MCFG_DEVICE_DISABLE()   /* Disables since the internal rom isn't dumped */
648	635	/* Program and Data Maps are internal to the MCU */
649		MCFG_CPU_IO_MAP(kickgoal_sound_io_map)
650	636
651
652	637	MCFG_EEPROM_SERIAL_93C46_ADD("eeprom")
653	638	MCFG_EEPROM_SERIAL_DATA(kickgoal_default_eeprom_type1, 128)
654	639
r244696	r244697
683	668	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_12MHz/3)    /* verified on pcb */
684	669	MCFG_DEVICE_DISABLE() /* Disables since the internal rom isn't dumped */
685	670	/* Program and Data Maps are internal to the MCU */
686		MCFG_CPU_IO_MAP(actionhw_io_map)
687	671
688
689	672	MCFG_EEPROM_SERIAL_93C46_ADD("eeprom")
690	673	MCFG_EEPROM_SERIAL_DATA(kickgoal_default_eeprom_type1, 128)
691	674

trunk/src/mame/drivers/megaphx.c

r244696	r244697
348	348	}
349	349
350	350
351		static ADDRESS_MAP_START( megaphx_pic_io_map, AS_IO, 8, megaphx_state )
352		//  AM_RANGE(0x00, 0x00) AM_WRITE(playmark_oki_banking_w)
353		//  AM_RANGE(0x01, 0x01) AM_READWRITE(playmark_snd_command_r, playmark_oki_w)
354		//  AM_RANGE(0x02, 0x02) AM_READWRITE(playmark_snd_flag_r, playmark_snd_control_w)
355		//  AM_RANGE(PIC16C5x_T0, PIC16C5x_T0) AM_READ(PIC16C5X_T0_clk_r)
356		ADDRESS_MAP_END
357
358
359	351	static MACHINE_CONFIG_START( megaphx, megaphx_state )
360	352
361	353	MCFG_CPU_ADD("maincpu", M68000, 8000000) // ??  can't read xtal due to reflections, CPU is an 8Mhz part
r244696	r244697
363	355
364	356	MCFG_CPU_ADD("pic", PIC16C54, 12000000)    /* 3MHz */
365	357	/* Program and Data Maps are internal to the MCU */
366		MCFG_CPU_IO_MAP(megaphx_pic_io_map)
367	358
368	359	MCFG_INDER_AUDIO_ADD("inder_sb")
369	360

trunk/src/mame/drivers/midzeus.c

r244696	r244697
1114	1114	MCFG_MIDWAY_IOASIC_SHUFFLE_DEFAULT(1)
1115	1115	MACHINE_CONFIG_END
1116	1116
1117		READ8_MEMBER(midzeus_state::PIC16C5X_T0_clk_r)
	1117	READ_LINE_MEMBER(midzeus_state::PIC16C5X_T0_clk_r)
1118	1118	{
1119	1119	return 0;
1120	1120	}
1121	1121
1122		static ADDRESS_MAP_START( pic_io_map, AS_IO, 8, midzeus_state )
1123		AM_RANGE(PIC16C5x_T0, PIC16C5x_T0) AM_READ(PIC16C5X_T0_clk_r)
1124		ADDRESS_MAP_END
1125	1122
1126
1127	1123	static MACHINE_CONFIG_DERIVED( invasn, midzeus )
1128	1124	MCFG_CPU_ADD("pic", PIC16C57, 8000000)  /* ? */
1129		MCFG_CPU_IO_MAP(pic_io_map)
	1125	MCFG_PIC16C5x_T0_CB(READLINE(midzeus_state, PIC16C5X_T0_clk_r))
1130	1126
1131	1127	MCFG_DEVICE_MODIFY("ioasic")
1132	1128	MCFG_MIDWAY_IOASIC_UPPER(468/* or 488 */)

trunk/src/mame/drivers/playmark.c

r244696	r244697
272	272	}
273	273
274	274
275		READ8_MEMBER(playmark_state::PIC16C5X_T0_clk_r)
	275	READ_LINE_MEMBER(playmark_state::PIC16C5X_T0_clk_r)
276	276	{
277	277	return 0;
278	278	}
r244696	r244697
425	425	ADDRESS_MAP_END
426	426
427	427
428		/***************************** PIC16C57 Memory Map **************************/
429
430		/* $000 - 7FF  PIC16C57 Internal Program ROM. Note: code is 12bits wide */
431		/* $000 - 07F  PIC16C57 Internal Data RAM */
432
433		static ADDRESS_MAP_START( playmark_sound_io_map, AS_IO, 8, playmark_state )
434		AM_RANGE(0x00, 0x00) AM_WRITE(playmark_oki_banking_w)
435		AM_RANGE(0x01, 0x01) AM_READWRITE(playmark_snd_command_r, playmark_oki_w)
436		AM_RANGE(0x02, 0x02) AM_READWRITE(playmark_snd_flag_r, playmark_snd_control_w)
437		AM_RANGE(PIC16C5x_T0, PIC16C5x_T0) AM_READ(PIC16C5X_T0_clk_r)
438		ADDRESS_MAP_END
439
440		static ADDRESS_MAP_START( hrdtimes_sound_io_map, AS_IO, 8, playmark_state )
441		AM_RANGE(0x00, 0x00) AM_NOP     /* AM_WRITE(playmark_oki_banking_w)  Banking data output but not wired. Port 2 (Port C) is wired to the OKI banking instead */
442		AM_RANGE(0x01, 0x01) AM_READWRITE(playmark_snd_command_r, playmark_oki_w)
443		AM_RANGE(0x02, 0x02) AM_READWRITE(playmark_snd_flag_r, hrdtimes_snd_control_w)
444		AM_RANGE(PIC16C5x_T0, PIC16C5x_T0) AM_READ(PIC16C5X_T0_clk_r)
445		ADDRESS_MAP_END
446
447
448	428	static INPUT_PORTS_START( bigtwin )
449	429	PORT_START("SYSTEM")
450	430	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
r244696	r244697
1231	1211	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state,  irq2_line_hold)
1232	1212
1233	1213	MCFG_CPU_ADD("audiocpu", PIC16C57, 12000000)
1234		/* Program and Data Maps are internal to the MCU */
1235		MCFG_CPU_IO_MAP(playmark_sound_io_map)
	1214	MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w))
	1215	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
	1216	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
	1217	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
	1218	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, playmark_snd_control_w))
	1219	MCFG_PIC16C5x_T0_CB(READLINE(playmark_state, PIC16C5X_T0_clk_r))
1236	1220
1237	1221	MCFG_MACHINE_START_OVERRIDE(playmark_state,playmark)
1238	1222	MCFG_MACHINE_RESET_OVERRIDE(playmark_state,playmark)
r244696	r244697
1267	1251	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state,  irq2_line_hold)
1268	1252
1269	1253	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2)
1270		/* Program and Data Maps are internal to the MCU */
1271		MCFG_CPU_IO_MAP(playmark_sound_io_map)
	1254	MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w))
	1255	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
	1256	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
	1257	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
	1258	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, playmark_snd_control_w))
	1259	MCFG_PIC16C5x_T0_CB(READLINE(playmark_state, PIC16C5X_T0_clk_r))
1272	1260
1273	1261	MCFG_MACHINE_START_OVERRIDE(playmark_state,playmark)
1274	1262	MCFG_MACHINE_RESET_OVERRIDE(playmark_state,playmark)
r244696	r244697
1303	1291	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state,  irq2_line_hold)
1304	1292
1305	1293	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2)    /* 12MHz with internal 4x divisor */
1306		/* Program and Data Maps are internal to the MCU */
1307		MCFG_CPU_IO_MAP(playmark_sound_io_map)
	1294	MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w))
	1295	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
	1296	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
	1297	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
	1298	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, playmark_snd_control_w))
	1299	MCFG_PIC16C5x_T0_CB(READLINE(playmark_state, PIC16C5X_T0_clk_r))
1308	1300	MCFG_DEVICE_DISABLE()       /* Internal code is not dumped yet */
1309	1301
1310	1302	MCFG_EEPROM_SERIAL_93C46_ADD("eeprom")
r244696	r244697
1343	1335	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state,  irq2_line_hold)
1344	1336
1345	1337	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2)    /* 12MHz with internal 4x divisor */
1346		/* Program and Data Maps are internal to the MCU */
1347		MCFG_CPU_IO_MAP(playmark_sound_io_map)
	1338	MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w))
	1339	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
	1340	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
	1341	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
	1342	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, playmark_snd_control_w))
	1343	MCFG_PIC16C5x_T0_CB(READLINE(playmark_state, PIC16C5X_T0_clk_r))
1348	1344
1349	1345	MCFG_MACHINE_START_OVERRIDE(playmark_state,playmark)
1350	1346	MCFG_MACHINE_RESET_OVERRIDE(playmark_state,playmark)
r244696	r244697
1379	1375	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state,  irq6_line_hold)
1380	1376
1381	1377	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2)    /* verified on pcb */
1382		/* Program and Data Maps are internal to the MCU */
1383		MCFG_CPU_IO_MAP(hrdtimes_sound_io_map)
	1378	//   MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
	1379	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
	1380	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
	1381	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
	1382	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, hrdtimes_snd_control_w))
	1383	MCFG_PIC16C5x_T0_CB(READLINE(playmark_state, PIC16C5X_T0_clk_r))
1384	1384	MCFG_DEVICE_DISABLE()       /* Internal code is not dumped yet */
1385	1385
1386	1386	MCFG_MACHINE_START_OVERRIDE(playmark_state,playmark)
r244696	r244697
1416	1416	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state,  irq6_line_hold) // irq 2 and 6 point to the same location on hotmind
1417	1417
1418	1418	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2)    /* verified on pcb */
1419		/* Program and Data Maps are internal to the MCU */
1420		MCFG_CPU_IO_MAP(hrdtimes_sound_io_map)
	1419	//   MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
	1420	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
	1421	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
	1422	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
	1423	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, hrdtimes_snd_control_w))
	1424	MCFG_PIC16C5x_T0_CB(READLINE(playmark_state, PIC16C5X_T0_clk_r))
1421	1425
1422	1426	MCFG_EEPROM_SERIAL_93C46_ADD("eeprom")
1423	1427	MCFG_EEPROM_SERIAL_DEFAULT_VALUE(0)
r244696	r244697
1458	1462	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state,  irq6_line_hold)
1459	1463
1460	1464	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2)    /* verified on pcb */
1461		/* Program and Data Maps are internal to the MCU */
1462		MCFG_CPU_IO_MAP(hrdtimes_sound_io_map)
	1465	//   MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
	1466	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
	1467	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
	1468	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
	1469	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, hrdtimes_snd_control_w))
	1470	MCFG_PIC16C5x_T0_CB(READLINE(playmark_state, PIC16C5X_T0_clk_r))
1463	1471
1464	1472	MCFG_NVRAM_ADD_0FILL("nvram")
1465	1473

trunk/src/mame/includes/drgnmst.h

r244696	r244697
57	57	DECLARE_WRITE8_MEMBER(drgnmst_pcm_banksel_w);
58	58	DECLARE_WRITE8_MEMBER(drgnmst_oki_w);
59	59	DECLARE_WRITE8_MEMBER(drgnmst_snd_control_w);
60		DECLARE_READ8_MEMBER(PIC16C5X_T0_clk_r);
	60	DECLARE_READ_LINE_MEMBER(PIC16C5X_T0_clk_r);
61	61	DECLARE_WRITE16_MEMBER(drgnmst_fg_videoram_w);
62	62	DECLARE_WRITE16_MEMBER(drgnmst_bg_videoram_w);
63	63	DECLARE_WRITE16_MEMBER(drgnmst_md_videoram_w);

trunk/src/mame/includes/midzeus.h

r244696	r244697
53	53	DECLARE_WRITE32_MEMBER(analog_w);
54	54	DECLARE_WRITE32_MEMBER(invasn_gun_w);
55	55	DECLARE_READ32_MEMBER(invasn_gun_r);
56		DECLARE_READ8_MEMBER(PIC16C5X_T0_clk_r);
	56	DECLARE_READ_LINE_MEMBER(PIC16C5X_T0_clk_r);
57	57	DECLARE_READ32_MEMBER(zeus_r);
58	58	DECLARE_WRITE32_MEMBER(zeus_w);
59	59	DECLARE_CUSTOM_INPUT_MEMBER(custom_49way_r);

trunk/src/mame/includes/playmark.h

r244696	r244697
66	66	DECLARE_WRITE8_MEMBER(playmark_oki_w);
67	67	DECLARE_WRITE8_MEMBER(playmark_snd_control_w);
68	68	DECLARE_WRITE8_MEMBER(hrdtimes_snd_control_w);
69		DECLARE_READ8_MEMBER(PIC16C5X_T0_clk_r);
	69	DECLARE_READ_LINE_MEMBER(PIC16C5X_T0_clk_r);
70	70	DECLARE_WRITE16_MEMBER(wbeachvl_txvideoram_w);
71	71	DECLARE_WRITE16_MEMBER(wbeachvl_fgvideoram_w);
72	72	DECLARE_WRITE16_MEMBER(wbeachvl_bgvideoram_w);

https://github.com/mamedev/mame/commit/202d316cdb561b63bc89e6d43d17c775fef62ec4

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