branches/kale/src/mess/drivers/c65.c
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| 6 | 6 | |
| 7 | 7 | Attempt at rewriting the driver ... |
| 8 | 8 | |
| 9 | TODO: |
| 10 | - Dies as soon as it enters into DOS ROM (bp 0x9d1a, it never returns due of a bad stack pointer read); |
| 11 | |
| 9 | 12 | Note: |
| 10 | 13 | - VIC-4567 will be eventually be added via compile switch, once that I |
| 11 | 14 | get the hang of the system (and checking where the old code fails |
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| 30 | 33 | m_palred(*this, "redpal"), |
| 31 | 34 | m_palgreen(*this, "greenpal"), |
| 32 | 35 | m_palblue(*this, "bluepal"), |
| 33 | | m_dmalist(*this, "dmalist") |
| 36 | m_dmalist(*this, "dmalist"), |
| 37 | m_cram(*this, "cram") |
| 34 | 38 | { } |
| 35 | 39 | |
| 36 | 40 | // devices |
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| 41 | 45 | required_shared_ptr<UINT8> m_palgreen; |
| 42 | 46 | required_shared_ptr<UINT8> m_palblue; |
| 43 | 47 | required_shared_ptr<UINT8> m_dmalist; |
| 44 | | |
| 48 | required_shared_ptr<UINT8> m_cram; |
| 49 | |
| 45 | 50 | DECLARE_READ8_MEMBER(vic4567_dummy_r); |
| 46 | 51 | DECLARE_WRITE8_MEMBER(vic4567_dummy_w); |
| 47 | 52 | DECLARE_WRITE8_MEMBER(PalRed_w); |
| 48 | 53 | DECLARE_WRITE8_MEMBER(PalGreen_w); |
| 49 | 54 | DECLARE_WRITE8_MEMBER(PalBlue_w); |
| 50 | 55 | DECLARE_WRITE8_MEMBER(DMAgic_w); |
| 56 | DECLARE_READ8_MEMBER(CIASelect_r); |
| 57 | DECLARE_WRITE8_MEMBER(CIASelect_w); |
| 51 | 58 | |
| 59 | DECLARE_READ8_MEMBER(dummy_r); |
| 60 | |
| 52 | 61 | // screen updates |
| 53 | 62 | UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); |
| 54 | 63 | DECLARE_PALETTE_INIT(c65); |
| 55 | 64 | DECLARE_DRIVER_INIT(c65); |
| 56 | 65 | DECLARE_DRIVER_INIT(c65pal); |
| 66 | |
| 67 | INTERRUPT_GEN_MEMBER(vic3_vblank_irq); |
| 57 | 68 | protected: |
| 58 | 69 | // driver_device overrides |
| 59 | 70 | virtual void machine_start(); |
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| 61 | 72 | |
| 62 | 73 | virtual void video_start(); |
| 63 | 74 | private: |
| 75 | UINT8 m_VIC2_IRQMask; |
| 76 | UINT8 m_VIC3_ControlA; |
| 64 | 77 | void PalEntryFlush(UINT8 offset); |
| 65 | 78 | void DMAgicExecute(address_space &space,UINT32 address); |
| 66 | 79 | }; |
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| 87 | 100 | case 0x12: |
| 88 | 101 | res = (m_screen->vpos() & 0xff); |
| 89 | 102 | return res; |
| 103 | case 0x30: |
| 104 | return m_VIC3_ControlA; |
| 90 | 105 | } |
| 91 | 106 | |
| 92 | 107 | if(!space.debugger_access()) |
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| 98 | 113 | { |
| 99 | 114 | switch(offset) |
| 100 | 115 | { |
| 116 | case 0x1a: |
| 117 | m_VIC2_IRQMask = data & 0xf; |
| 118 | break; |
| 101 | 119 | /* KEY register, handles vic-iii and vic-ii modes via two consecutive writes |
| 102 | 120 | 0xa5 -> 0x96 vic-iii mode |
| 103 | 121 | any other write vic-ii mode |
| 104 | 122 | */ |
| 105 | 123 | //case 0x2f: break; |
| 124 | case 0x30: |
| 125 | printf("CONTROL A %02x\n",data); |
| 126 | m_VIC3_ControlA = data; |
| 127 | break; |
| 106 | 128 | default: |
| 107 | 129 | if(!space.debugger_access()) |
| 108 | 130 | printf("%02x %02x\n",offset,data); |
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| 187 | 209 | DMAgicExecute(space,(m_dmalist[0])|(m_dmalist[1]<<8)|(m_dmalist[2]<<16)); |
| 188 | 210 | } |
| 189 | 211 | |
| 212 | READ8_MEMBER(c65_state::CIASelect_r) |
| 213 | { |
| 214 | if(m_VIC3_ControlA & 1) |
| 215 | return m_cram[offset]; |
| 216 | else |
| 217 | { |
| 218 | // CIA |
| 219 | } |
| 190 | 220 | |
| 221 | return 0xff; |
| 222 | } |
| 191 | 223 | |
| 224 | WRITE8_MEMBER(c65_state::CIASelect_w) |
| 225 | { |
| 226 | if(m_VIC3_ControlA & 1) |
| 227 | m_cram[offset] = data; |
| 228 | else |
| 229 | { |
| 230 | // CIA |
| 231 | } |
| 232 | |
| 233 | } |
| 234 | |
| 235 | READ8_MEMBER(c65_state::dummy_r) |
| 236 | { |
| 237 | return 0xff; |
| 238 | } |
| 239 | |
| 192 | 240 | static ADDRESS_MAP_START( c65_map, AS_PROGRAM, 8, c65_state ) |
| 193 | 241 | AM_RANGE(0x00000, 0x01fff) AM_RAM // TODO: bank |
| 194 | 242 | AM_RANGE(0x0c800, 0x0cfff) AM_ROM AM_REGION("maincpu", 0xc800) |
| 195 | 243 | AM_RANGE(0x0d000, 0x0d07f) AM_READWRITE(vic4567_dummy_r,vic4567_dummy_w) // 0x0d000, 0x0d07f VIC-4567 |
| 196 | | // 0x0d080, 0x0d09f FDC |
| 244 | AM_RANGE(0x0d080, 0x0d081) AM_READ(dummy_r) // 0x0d080, 0x0d09f FDC |
| 197 | 245 | // 0x0d0a0, 0x0d0ff Ram Expansion Control (REC) |
| 198 | 246 | AM_RANGE(0x0d100, 0x0d1ff) AM_RAM_WRITE(PalRed_w) AM_SHARE("redpal")// 0x0d100, 0x0d1ff Red Palette |
| 199 | 247 | AM_RANGE(0x0d200, 0x0d2ff) AM_RAM_WRITE(PalGreen_w) AM_SHARE("greenpal") // 0x0d200, 0x0d2ff Green Palette |
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| 204 | 252 | AM_RANGE(0x0d700, 0x0d702) AM_WRITE(DMAgic_w) AM_SHARE("dmalist") // 0x0d700, 0x0d7** DMAgic |
| 205 | 253 | //AM_RANGE(0x0d703, 0x0d703) AM_READ(DMAgic_r) |
| 206 | 254 | // 0x0d800, 0x0d8** Color matrix |
| 255 | AM_RANGE(0x0dc00, 0x0dfff) AM_READWRITE(CIASelect_r,CIASelect_w) AM_SHARE("cram") |
| 207 | 256 | // 0x0dc00, 0x0dc** CIA-1 |
| 208 | 257 | // 0x0dd00, 0x0dd** CIA-2 |
| 209 | 258 | // 0x0de00, 0x0de** Ext I/O Select 1 |
| 210 | | AM_RANGE(0x0df00, 0x0dfff) AM_RAM // 0x0df00, 0x0df** Ext I/O Select 2 (RAM window?) |
| 259 | // 0x0df00, 0x0df** Ext I/O Select 2 (RAM window?) |
| 260 | AM_RANGE(0x0e000, 0x0ffff) AM_ROM AM_REGION("maincpu",0x0e000) |
| 211 | 261 | AM_RANGE(0x10000, 0x1f7ff) AM_RAM |
| 212 | 262 | AM_RANGE(0x1f800, 0x1ffff) AM_RAM // VRAM |
| 213 | 263 | AM_RANGE(0x20000, 0x3ffff) AM_ROM AM_REGION("maincpu",0) |
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| 286 | 336 | // TODO: initial state? |
| 287 | 337 | } |
| 288 | 338 | |
| 339 | static const gfx_layout charlayout = |
| 340 | { |
| 341 | 8,8, |
| 342 | 0x1000/8, |
| 343 | 1, |
| 344 | { RGN_FRAC(0,1) }, |
| 345 | { 0, 1, 2, 3, 4, 5, 6, 7 }, |
| 346 | { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8 }, |
| 347 | 8*8 |
| 348 | }; |
| 349 | |
| 350 | static GFXDECODE_START( c65 ) |
| 351 | GFXDECODE_ENTRY( "maincpu", 0xd000, charlayout, 0, 1 ) // another identical copy is at 0x9000 |
| 352 | GFXDECODE_END |
| 353 | |
| 354 | INTERRUPT_GEN_MEMBER(c65_state::vic3_vblank_irq) |
| 355 | { |
| 356 | if(m_VIC2_IRQMask & 1) |
| 357 | m_maincpu->set_input_line(M4510_IRQ_LINE,HOLD_LINE); |
| 358 | } |
| 359 | |
| 289 | 360 | static MACHINE_CONFIG_START( c65, c65_state ) |
| 290 | 361 | |
| 291 | 362 | /* basic machine hardware */ |
| 292 | 363 | MCFG_CPU_ADD("maincpu",M4510,MAIN_CLOCK) |
| 293 | 364 | MCFG_CPU_PROGRAM_MAP(c65_map) |
| 365 | MCFG_CPU_VBLANK_INT_DRIVER("screen",c65_state,vic3_vblank_irq) |
| 294 | 366 | |
| 295 | 367 | /* video hardware */ |
| 296 | 368 | MCFG_SCREEN_ADD("screen", RASTER) |
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| 299 | 371 | MCFG_SCREEN_UPDATE_DRIVER(c65_state, screen_update) |
| 300 | 372 | // MCFG_SCREEN_SIZE(32*8, 32*8) |
| 301 | 373 | // MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 0*8, 32*8-1) |
| 302 | | MCFG_SCREEN_RAW_PARAMS(MAIN_CLOCK, 525, 0, 320, 525, 0, 240) // mods needed |
| 374 | MCFG_SCREEN_RAW_PARAMS(MAIN_CLOCK, 910, 0, 320, 525, 0, 240) // mods needed |
| 303 | 375 | MCFG_SCREEN_PALETTE("palette") |
| 304 | 376 | |
| 377 | MCFG_GFXDECODE_ADD("gfxdecode", "palette", c65) |
| 378 | |
| 305 | 379 | MCFG_PALETTE_ADD("palette", 0x100) |
| 306 | 380 | MCFG_PALETTE_INIT_OWNER(c65_state, c65) |
| 307 | 381 | |