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r34576 Friday 23rd January, 2015 at 22:39:33 UTC by Angelo Salese
It's a kind of (D)MAgic (sets up basic VRAM)
[/branches/kale/src/mess/drivers]c65.c

branches/kale/src/mess/drivers/c65.c
r243087r243088
2929         m_palette(*this, "palette"),
3030         m_palred(*this, "redpal"),
3131         m_palgreen(*this, "greenpal"),
32         m_palblue(*this, "bluepal")
33         
32         m_palblue(*this, "bluepal"),
33         m_dmalist(*this, "dmalist")         
3434   { }
3535
3636   // devices
37   required_device<cpu_device> m_maincpu;
37   required_device<m4510_device> m_maincpu;
3838   required_device<screen_device> m_screen;
3939   required_device<palette_device> m_palette;
4040   required_shared_ptr<UINT8> m_palred;
4141   required_shared_ptr<UINT8> m_palgreen;
4242   required_shared_ptr<UINT8> m_palblue;
43   required_shared_ptr<UINT8> m_dmalist;
4344   
4445   DECLARE_READ8_MEMBER(vic4567_dummy_r);
4546   DECLARE_WRITE8_MEMBER(vic4567_dummy_w);
4647   DECLARE_WRITE8_MEMBER(PalRed_w);
4748   DECLARE_WRITE8_MEMBER(PalGreen_w);
4849   DECLARE_WRITE8_MEMBER(PalBlue_w);
50   DECLARE_WRITE8_MEMBER(DMAgic_w);
4951   
5052   // screen updates
5153   UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
r243087r243088
6062   virtual void video_start();
6163private:
6264   void PalEntryFlush(UINT8 offset);
65   void DMAgicExecute(address_space &space,UINT32 address);
6366};
6467
6568void c65_state::video_start()
r243087r243088
8689         return res;
8790   }
8891   
89   printf("%02x\n",offset); // TODO: PC
92   if(!space.debugger_access())
93      printf("%02x\n",offset); // TODO: PC
9094   return res;
9195}
9296
r243087r243088
99103          any other write vic-ii mode
100104        */
101105      //case 0x2f: break;
102      default: printf("%02x %02x\n",offset,data); break;
106      default:
107         if(!space.debugger_access())
108            printf("%02x %02x\n",offset,data);
109         break;
103110   }
104111
105112}
r243087r243088
127134   PalEntryFlush(offset);
128135}
129136
137void c65_state::DMAgicExecute(address_space &space,UINT32 address)
138{
139   UINT8 cmd;// = space.read_byte(address++);
140   UINT16 length; //= space.read_byte(address++);
141   UINT32 src, dst;
142   static const char *const dma_cmd_string[] =
143   {
144      "COPY",                 // 0
145      "MIX",
146      "SWAP",
147      "FILL"
148   };
149   cmd = space.read_byte(address++);
150   length = space.read_byte(address++);
151   length|=(space.read_byte(address++)<<8);
152   src = space.read_byte(address++);
153   src|=(space.read_byte(address++)<<8);
154   src|=(space.read_byte(address++)<<16);
155   dst = space.read_byte(address++);
156   dst|=(space.read_byte(address++)<<8);
157   dst|=(space.read_byte(address++)<<16);
130158
159   switch(cmd & 3)
160   {
161      case 3: // fill
162         {
163            /* TODO: upper bits of source */
164            printf("DMAgic %s %02x -> %08x %04x (CHAIN=%s)\n",dma_cmd_string[cmd & 3],src & 0xff,dst,length,cmd & 4 ? "yes" : "no");
165            UINT8 FillValue;
166            UINT32 DestIndex;
167            UINT16 SizeIndex;
168            FillValue = src & 0xff;
169            DestIndex = dst & 0xfffff;
170            SizeIndex = length;
171            do
172            {
173               space.write_byte(DestIndex++,FillValue);
174               SizeIndex--;
175            }while(SizeIndex != 0);
176         }
177         return;
178   }
179   printf("DMAgic %s %08x %08x %04x (CHAIN=%s)\n",dma_cmd_string[cmd & 3],src,dst,length,cmd & 4 ? "yes" : "no");
180}
181
182
183WRITE8_MEMBER(c65_state::DMAgic_w)
184{
185   m_dmalist[offset] = data;
186   if(offset == 0)
187      DMAgicExecute(space,(m_dmalist[0])|(m_dmalist[1]<<8)|(m_dmalist[2]<<16));
188}
189
190
191
131192static ADDRESS_MAP_START( c65_map, AS_PROGRAM, 8, c65_state )
132193   AM_RANGE(0x00000, 0x01fff) AM_RAM // TODO: bank
133194   AM_RANGE(0x0c800, 0x0cfff) AM_ROM AM_REGION("maincpu", 0xc800)
r243087r243088
140201   // 0x0d400, 0x0d4*f Right SID
141202   // 0x0d440, 0x0d4*f Left  SID
142203   // 0x0d600, 0x0d6** UART
143   // 0x0d700, 0x0d7** DMAgic
204   AM_RANGE(0x0d700, 0x0d702) AM_WRITE(DMAgic_w) AM_SHARE("dmalist") // 0x0d700, 0x0d7** DMAgic
205   //AM_RANGE(0x0d703, 0x0d703) AM_READ(DMAgic_r)
144206   // 0x0d800, 0x0d8** Color matrix
145207   // 0x0dc00, 0x0dc** CIA-1
146208   // 0x0dd00, 0x0dd** CIA-2
147209   // 0x0de00, 0x0de** Ext I/O Select 1
148210   AM_RANGE(0x0df00, 0x0dfff) AM_RAM // 0x0df00, 0x0df** Ext I/O Select 2 (RAM window?)
211   AM_RANGE(0x10000, 0x1f7ff) AM_RAM
212   AM_RANGE(0x1f800, 0x1ffff) AM_RAM // VRAM
149213   AM_RANGE(0x20000, 0x3ffff) AM_ROM AM_REGION("maincpu",0)
150214ADDRESS_MAP_END
151215


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