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r33909 Monday 15th December, 2014 at 19:57:28 UTC by David Haywood
arcompact dasm wip (nw)
[src/emu/cpu/arcompact]arcompactdasm_dispatch.c arcompactdasm_ops.c

trunk/src/emu/cpu/arcompact/arcompactdasm_dispatch.c
r242420r242421
640640{
641641   int size = 2;
642642   UINT8 subinstr2 = (op & 0x0700) >> 8;
643   op &= ~0x001f;
643   op &= ~0x0700;
644644
645645   switch (subinstr2)
646646   {
trunk/src/emu/cpu/arcompact/arcompactdasm_ops.c
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195195
196196
197197
198int arcompact_01_01_00_helper(char *output, offs_t pc, UINT32 op, const UINT8* oprom, const char* optext)
199{
200   int size = 4;
201
202   // Branch on Compare / Bit Test - Register-Register
203   // 00001 bbb sssssss 1 S BBB CCCCCC N 0 iiii
204   INT32 address = (op & 0x00fe0000) >> 17;
205   address |= ((op & 0x00008000) >> 15) << 7;
206   if (address & 0x80) address = -(address & 0x7f);
207
208   int c = (op & 0x00000fc0) >> 6;
209   int b = (op & 0x07000000) >> 24;
210   b |= ((op & 0x00007000) >> 12) << 3;
211   int n = (op & 0x00000020) >> 5; op &= ~0x00000020;
212
213   op &= ~0x07007fe0;
214
215   if ((b != LIMM_REG) && (c != LIMM_REG))
216   {
217      print("%s%s (r%d) (r%d) %08x (%08x)", optext, delaybit[n], b, c, pc + (address * 2) + 4, op & ~0xf8fe800f);
218   }
219   else
220   {
221      UINT32 limm;
222      GET_LIMM_32;
223      size = 8;
224
225      if ((b == LIMM_REG) && (c != LIMM_REG))
226      {
227         print("%s%s (%08x) (r%d) %08x (%08x)", optext, delaybit[n], limm, c, pc + (address * 2) + 4, op & ~0xf8fe800f);
228      }
229      else if ((c == LIMM_REG) && (b != LIMM_REG))
230      {
231         print("%s%s (r%d) (%08x) %08x (%08x)", optext, delaybit[n], b, limm, pc + (address * 2) + 4, op & ~0xf8fe800f);
232      }
233      else
234      {
235         // b and c are LIMM? invalid??
236         print("%s%s (%08x) (%08x) (illegal?) %08x (%08x)", optext, delaybit[n], limm, limm, pc + (address * 2) + 4, op & ~0xf8fe800f);
237
238      }
239   }
240
241   return size;
242}
243
244198#define GET_01_01_01_BRANCH_ADDR \
245199   INT32 address = (op & 0x00fe0000) >> 17; \
246200   address |= ((op & 0x00008000) >> 15) << 7; \
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251205#define GROUP_0e_GET_h \
252206   h =  ((op & 0x0007) << 3); \
253207    h |= ((op & 0x00e0) >> 5); \
208   op &= ~0x00e7; \
254209
210#define COMMON16_GET_breg \
211   breg =  ((op & 0x0700) >>8); \
212   op &= ~0x0700; \
213
214#define COMMON16_GET_creg \
215   creg =  ((op & 0x00e0) >>5); \
216   op &= ~0x00e0; \
217
218#define COMMON16_GET_u5 \
219   u =  ((op & 0x001f) >>0); \
220   op &= ~0x001f; \
221
222#define COMMON16_GET_u8 \
223   u =  ((op & 0x00ff) >>0); \
224   op &= ~0x00ff; \
225
226#define COMMON16_GET_u7 \
227   u =  ((op & 0x007f) >>0); \
228   op &= ~0x007f; \
229
230// registers used in 16-bit opcodes hae a limited range
231// and can only address registers r0-r3 and r12-r15
232
233#define REG_16BIT_RANGE(_reg_) \
234   if (_reg_>3) _reg_+= 8; \
235
236
255237// this is as messed up as the rest of the 16-bit alignment in LE mode...
256238
257239#define GET_LIMM \
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269251{
270252   int size = 4;
271253   // Branch Conditionally
272   // 00000 ssssssssss 0 SSSSSSSSSS N QQQQQ
254   // 0000 0sss ssss sss0 SSSS SSSS SSNQ QQQQ
273255   INT32 address = (op & 0x07fe0000) >> 17;
274256   address |= ((op & 0x0000ffc0) >> 6) << 10;
275257   if (address & 0x800000) address = -(address & 0x7fffff);
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284266{
285267   int size = 4;
286268   // Branch Unconditionally Far
287   // 00000 ssssssssss 1 SSSSSSSSSS N R TTTT
269   // 0000 0sss ssss sss1 SSSS SSSS SSNR TTTT
288270   INT32 address = (op & 0x07fe0000) >> 17;
289271   address |= ((op & 0x0000ffc0) >> 6) << 10;
290272   address |= ((op & 0x0000000f) >> 0) << 20;
r242420r242421
333315   return size;
334316}
335317
336int arcompact_handle01_01_00_00_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BREQ b - c"); }
337int arcompact_handle01_01_00_01_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BRNE b - c"); }
338int arcompact_handle01_01_00_02_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BRLT b - c"); }
339int arcompact_handle01_01_00_03_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BRGE b - c"); }
340int arcompact_handle01_01_00_04_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BRLO b - c"); }
341int arcompact_handle01_01_00_05_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BRHS b - c"); }
342int arcompact_handle01_01_00_0e_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BBIT0 (b & 1<<c) == 0");  }
343int arcompact_handle01_01_00_0f_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BBIT1 (b & 1<<c) != 0");  }
344318
345319
346int arcompact_handle01_01_01_00_dasm(DASM_OPS_32)  { GET_01_01_01_BRANCH_ADDR;  print("BREQ b - u6 (dst %08x) (%08x)", pc + (address * 2) + 4, op); return 4; }
347int arcompact_handle01_01_01_01_dasm(DASM_OPS_32)  { GET_01_01_01_BRANCH_ADDR;  print("BRNE b - u6 (dst %08x) (%08x)", pc + (address * 2) + 4, op); return 4; }
348int arcompact_handle01_01_01_02_dasm(DASM_OPS_32)  { GET_01_01_01_BRANCH_ADDR;  print("BRLT b - u6 (dst %08x) (%08x)", pc + (address * 2) + 4, op); return 4; }
349int arcompact_handle01_01_01_03_dasm(DASM_OPS_32)  { GET_01_01_01_BRANCH_ADDR;  print("BRGE b - u6 (dst %08x) (%08x)", pc + (address * 2) + 4, op); return 4; }
350int arcompact_handle01_01_01_04_dasm(DASM_OPS_32)  { GET_01_01_01_BRANCH_ADDR;  print("BRLO b - u6 (dst %08x) (%08x)", pc + (address * 2) + 4, op); return 4; }
351int arcompact_handle01_01_01_05_dasm(DASM_OPS_32)  { GET_01_01_01_BRANCH_ADDR;  print("BRHS b - u6 (dst %08x) (%08x)", pc + (address * 2) + 4, op); return 4; }
320int arcompact_01_01_00_helper(char *output, offs_t pc, UINT32 op, const UINT8* oprom, const char* optext)
321{
322   int size = 4;
352323
324   // Branch on Compare / Bit Test - Register-Register
325   // 00001 bbb sssssss 1 S BBB CCCCCC N 0 iiii
326   GET_01_01_01_BRANCH_ADDR
353327
354int arcompact_handle01_01_01_0e_dasm(DASM_OPS_32)  { GET_01_01_01_BRANCH_ADDR;  print("BBIT0 (b & 1<<u6) == 0 (dst %08x) (%08x)", pc + (address * 2) + 4, op); return 4; }
355int arcompact_handle01_01_01_0f_dasm(DASM_OPS_32)  { GET_01_01_01_BRANCH_ADDR;  print("BBIT1 (b & 1<<u6) != 0 (dst %08x) (%08x)", pc + (address * 2) + 4, op); return 4; }
356328
329   int c = (op & 0x00000fc0) >> 6;
330   int b = (op & 0x07000000) >> 24;
331   b |= ((op & 0x00007000) >> 12) << 3;
332   int n = (op & 0x00000020) >> 5; op &= ~0x00000020;
357333
334   op &= ~0x07007fe0;
335
336   if ((b != LIMM_REG) && (c != LIMM_REG))
337   {
338      print("%s%s %s %s %08x (%08x)", optext, delaybit[n], regnames[b], regnames[c], pc + (address * 2) + 4, op & ~0xf8fe800f);
339   }
340   else
341   {
342      UINT32 limm;
343      GET_LIMM_32;
344      size = 8;
345
346      if ((b == LIMM_REG) && (c != LIMM_REG))
347      {
348         print("%s%s (%08x) %s %08x (%08x)", optext, delaybit[n], limm, regnames[b], pc + (address * 2) + 4, op & ~0xf8fe800f);
349      }
350      else if ((c == LIMM_REG) && (b != LIMM_REG))
351      {
352         print("%s%s %s (%08x) %08x (%08x)", optext, delaybit[n], regnames[b], limm, pc + (address * 2) + 4, op & ~0xf8fe800f);
353      }
354      else
355      {
356         // b and c are LIMM? invalid??
357         print("%s%s (%08x) (%08x) (illegal?) %08x (%08x)", optext, delaybit[n], limm, limm, pc + (address * 2) + 4, op & ~0xf8fe800f);
358
359      }
360   }
361
362   return size;
363}
364
365
366// register - register cases
367int arcompact_handle01_01_00_00_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BREQ"); }
368int arcompact_handle01_01_00_01_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BRNE"); }
369int arcompact_handle01_01_00_02_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BRLT"); }
370int arcompact_handle01_01_00_03_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BRGE"); }
371int arcompact_handle01_01_00_04_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BRLO"); }
372int arcompact_handle01_01_00_05_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BRHS"); }
373int arcompact_handle01_01_00_0e_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BBIT0");}
374int arcompact_handle01_01_00_0f_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BBIT1");}
375
376int arcompact_01_01_01_helper(char *output, offs_t pc, UINT32 op, const UINT8* oprom, const char* optext)
377{
378   int size = 4;
379
380   // using 'b' as limm here makes no sense (comparing a long immediate against a short immediate) so I assume it isn't
381   // valid?
382
383   // Branch on Compare / Bit Test - Register-Immediate
384   // 0000 1bbb ssss sss1 SBBB uuuu uuN1 iiii
385   GET_01_01_01_BRANCH_ADDR
386
387   int u = (op & 0x00000fc0) >> 6;
388   int b = (op & 0x07000000) >> 24;
389   b |= ((op & 0x00007000) >> 12) << 3;
390   int n = (op & 0x00000020) >> 5; op &= ~0x00000020;
391
392   op &= ~0x07007fe0;
393
394   print("%s%s %s %02x %08x (%08x)", optext, delaybit[n], regnames[b], u, pc + (address * 2) + 4, op & ~0xf8fe800f);
395   
396   return size;
397}
398
399// register -immediate cases
400int arcompact_handle01_01_01_00_dasm(DASM_OPS_32)  { return arcompact_01_01_01_helper(output, pc, op, oprom, "BREQ"); }
401int arcompact_handle01_01_01_01_dasm(DASM_OPS_32)  { return arcompact_01_01_01_helper(output, pc, op, oprom, "BRNE"); }
402int arcompact_handle01_01_01_02_dasm(DASM_OPS_32)  { return arcompact_01_01_01_helper(output, pc, op, oprom, "BRLT"); }
403int arcompact_handle01_01_01_03_dasm(DASM_OPS_32)  { return arcompact_01_01_01_helper(output, pc, op, oprom, "BRGE"); }
404int arcompact_handle01_01_01_04_dasm(DASM_OPS_32)  { return arcompact_01_01_01_helper(output, pc, op, oprom, "BRLO"); }
405int arcompact_handle01_01_01_05_dasm(DASM_OPS_32)  { return arcompact_01_01_01_helper(output, pc, op, oprom, "BRHS"); }
406int arcompact_handle01_01_01_0e_dasm(DASM_OPS_32)  { return arcompact_01_01_01_helper(output, pc, op, oprom, "BBIT0"); }
407int arcompact_handle01_01_01_0f_dasm(DASM_OPS_32)  { return arcompact_01_01_01_helper(output, pc, op, oprom, "BBIT1"); }
408
409
358410int arcompact_handle02_dasm(DASM_OPS_32)
359411{
360412   // bitpos
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9891041
9901042
9911043
992
993
994
995int arcompact_handle0e_00_dasm(DASM_OPS_16)
1044int arcompact_handle0e_0x_helper_dasm(char *output, offs_t pc, UINT16 op, const UINT8* oprom, const char* optext, int revop)
9961045{
997   int h;
1046   int h,breg;
9981047   int size = 2;
9991048
10001049   GROUP_0e_GET_h;
1001
1050   COMMON16_GET_breg;
1051   REG_16BIT_RANGE(breg);
1052   
10021053   if (h == LIMM_REG)
10031054   {
10041055      UINT32 limm;
10051056      GET_LIMM;
10061057      size = 6;
1007      print("ADD_S b <- b + (%08x) (%04x)", limm, op);
1058      if (!revop) print("%s %s, (%08x) (%04x)", optext, regnames[breg], limm, op);
1059      else print("%s (%08x), %s (%04x)", optext, limm, regnames[breg], op);
10081060   }
10091061   else
10101062   {
1063      if (!revop) print("%s %s, %s (%04x)", optext, regnames[breg], regnames[h], op);
1064      else print("%s %s, %s (%04x)", optext, regnames[h], regnames[breg], op);
10111065
1012      print("ADD_S b <- b + (r%d) (%04x)", h, op);
10131066   }
10141067
10151068   return size;
1069
10161070}
10171071
1072int arcompact_handle0e_00_dasm(DASM_OPS_16)
1073{
1074   return arcompact_handle0e_0x_helper_dasm(output, pc, op, oprom, "ADD_S", 0);
1075}
1076
10181077int arcompact_handle0e_01_dasm(DASM_OPS_16)
10191078{
1020   int h;
1021   int size = 2;
1022   GROUP_0e_GET_h;
1023
1024   if (h == LIMM_REG)
1025   {
1026      UINT32 limm;
1027      GET_LIMM;
1028      size = 6;
1029      print("MOV_S b <- (%08x)  (%04x)", limm, op);
1030   }
1031   else
1032   {
1033      print("MOV_S b <- (r%d)  (%04x)", h, op);
1034   }
1035   return size;
1079   return arcompact_handle0e_0x_helper_dasm(output, pc, op, oprom, "MOV_S", 0);
10361080}
10371081
10381082int arcompact_handle0e_02_dasm(DASM_OPS_16)
10391083{
1040   int h;
1041   int size = 2;
1042   GROUP_0e_GET_h;
1043
1044   if (h == LIMM_REG)
1045   {
1046      UINT32 limm;
1047      GET_LIMM;
1048      size = 6;
1049      print("CMP_S b - (%08x) (%04x)", limm, op);
1050   }
1051   else
1052   {
1053      print("CMP_S b - (r%d) (%04x)", h, op);
1054   }
1055   return size;
1084   return arcompact_handle0e_0x_helper_dasm(output, pc, op, oprom, "CMP_S", 0);
10561085}
10571086
10581087int arcompact_handle0e_03_dasm(DASM_OPS_16)
10591088{
1060   int h;
1061   int size = 2;
1062   GROUP_0e_GET_h;
1063
1064   if (h == LIMM_REG)
1065   {
1066      UINT32 limm;
1067      GET_LIMM;
1068      size = 6;
1069      print("MOV_S (%08x) <- b (%04x)", limm, op);
1070   }
1071   else
1072   {
1073      print("MOV_S (r%d) <- b (%04x)", h, op);
1074   }
1075
1076   return size;
1089   return arcompact_handle0e_0x_helper_dasm(output, pc, op, oprom, "MOV_S", 1);
10771090}
10781091
10791092
r242420r242421
11341147int arcompact_handle0f_1f_dasm(DASM_OPS_16)  { print("BRK_S (%08x)", op); return 2;}
11351148
11361149
1137int arcompact_handle10_dasm(DASM_OPS_16)
1150int arcompact_handle_ld_helper_dasm(char *output, offs_t pc, UINT16 op, const UINT8* oprom, const char* optext, int shift, int swap)
11381151{
1139   print("LD_S (%04x)",  op);
1152   int breg, creg, u;
1153
1154   COMMON16_GET_breg;
1155   COMMON16_GET_creg;
1156   COMMON16_GET_u5;
1157
1158   REG_16BIT_RANGE(breg);
1159   REG_16BIT_RANGE(creg);
1160
1161   u <<= shift;
1162
1163   if (!swap) print("%s %s, [%s, 0x%02x] (%04x)", optext, regnames[creg], regnames[breg], u, op);
1164   else  print("%s [%s, 0x%02x], %s (%04x)", optext, regnames[breg], u, regnames[creg], op);
11401165   return 2;
1166
11411167}
11421168
1169
1170int arcompact_handle10_dasm(DASM_OPS_16)
1171{
1172   return arcompact_handle_ld_helper_dasm(output, pc, op, oprom, "LD_S", 2, 0);
1173}
1174
11431175int arcompact_handle11_dasm(DASM_OPS_16)
11441176{
1145   print("LDB_S (%04x)", op);
1146   return 2;
1177   return arcompact_handle_ld_helper_dasm(output, pc, op, oprom, "LDB_S", 0, 0);
11471178}
11481179
11491180int arcompact_handle12_dasm(DASM_OPS_16)
11501181{
1151   print("LDW_S (%04x)", op);
1152   return 2;
1182   return arcompact_handle_ld_helper_dasm(output, pc, op, oprom, "LDW_S", 1, 0);
11531183}
11541184
11551185int arcompact_handle13_dasm(DASM_OPS_16)
11561186{
1157   print("LSW_S.X (%04x)", op);
1158   return 2;
1187   return arcompact_handle_ld_helper_dasm(output, pc, op, oprom, "LDW_S.X", 1, 0);
11591188}
11601189
11611190int arcompact_handle14_dasm(DASM_OPS_16)
11621191{
1163   print("ST_S (%04x)", op);
1164   return 2;
1192   return arcompact_handle_ld_helper_dasm(output, pc, op, oprom, "ST_S", 2, 1);
11651193}
11661194
11671195int arcompact_handle15_dasm(DASM_OPS_16)
11681196{
1169   print("STB_S (%04x)", op);
1170   return 2;
1197   return arcompact_handle_ld_helper_dasm(output, pc, op, oprom, "STB_S", 0, 1);
11711198}
11721199
11731200int arcompact_handle16_dasm(DASM_OPS_16)
11741201{
1175   print("STW_S (%04x)",  op);
1176   return 2;
1202   return arcompact_handle_ld_helper_dasm(output, pc, op, oprom, "STW_S", 1, 1);
11771203}
11781204
11791205
r242420r242421
12891315// op bits remaining for 0x18_06_xx subgroups 0x0700
12901316int arcompact_handle18_06_01_dasm(DASM_OPS_16)
12911317{
1292   int b = (op & 0x0700) >> 8;
1318   int breg = (op & 0x0700) >> 8;
12931319   op &= ~0x0700; // all bits now used
1320   REG_16BIT_RANGE(breg)
12941321
1295   print("POP_S [%02x]", b);
1322   print("POP_S %s", regnames[breg]);
12961323
12971324   return 2;
12981325}
r242420r242421
13131340// op bits remaining for 0x18_07_xx subgroups 0x0700
13141341int arcompact_handle18_07_01_dasm(DASM_OPS_16)
13151342{
1316   int b = (op & 0x0700) >> 8;
1343   int breg = (op & 0x0700) >> 8;
13171344   op &= ~0x0700; // all bits now used
1345   REG_16BIT_RANGE(breg)
13181346
1319   print("PUSH_S [%02x]", b);
1347   print("PUSH_S %s", regnames[breg]);
13201348
13211349   return 2;
13221350}
r242420r242421
13481376
13491377int arcompact_handle1b_dasm(DASM_OPS_16)
13501378{
1351   print("MOV_S (%04x)", op);
1379   int breg, u;
1380   COMMON16_GET_breg;
1381   COMMON16_GET_u8;
1382   REG_16BIT_RANGE(breg);
1383
1384   print("MOV_S %s, %02x", regnames[breg], u);
13521385   return 2;
13531386}
13541387
1355int arcompact_handle1c_00_dasm(DASM_OPS_16)  { print("ADD_S b <- b + u7 (%04x)",  op); return 2;}
1356int arcompact_handle1c_01_dasm(DASM_OPS_16)  { print("CMP_S b - u7 (%04x)",  op); return 2;}
1388int arcompact_handle1c_00_dasm(DASM_OPS_16)
1389{
1390   int breg, u;
1391   COMMON16_GET_breg;
1392   COMMON16_GET_u7;
1393   REG_16BIT_RANGE(breg);
13571394
1395   print("ADD_S %s, %02x", regnames[breg], u);
1396   return 2;
1397}
13581398
1399int arcompact_handle1c_01_dasm(DASM_OPS_16)
1400{
1401   int breg, u;
1402   COMMON16_GET_breg;
1403   COMMON16_GET_u7;
1404   REG_16BIT_RANGE(breg);
1405
1406   print("CMP_S %s, %02x", regnames[breg], u);
1407   return 2;
1408}
1409
1410
13591411int arcompact_handle1d_00_dasm(DASM_OPS_16)  { print("BREQ_S (%04x)",  op); return 2;}
13601412int arcompact_handle1d_01_dasm(DASM_OPS_16)  { print("BRNE_S (%04x)",  op); return 2;}
13611413

https://github.com/mamedev/mame/commit/ab74f0e4c27502a4c4ead08e3f82deba2593e2a5

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