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r33828 Thursday 11th December, 2014 at 17:36:13 UTC by Curt Coder
(MESS) c8050: Floppy WIP. (nw)
[src/emu/bus/ieee488]c2040fdc.c c8050fdc.c c8050fdc.h
[src/lib/formats]d64_dsk.h d80_dsk.c

trunk/src/emu/bus/ieee488/c2040fdc.c
r242339r242340
427427
428428   UINT8 data = (BIT(e, 6) << 7) | (BIT(i, 7) << 6) | (e & 0x33) | (BIT(e, 2) << 3) | (i & 0x04);
429429
430   if (LOG) logerror("%s VIA reads data %02x (%03x)\n", machine().time().as_string(), data, checkpoint_live.shift_reg);
430   if (LOG) logerror("%s %s VIA reads data %02x (%03x)\n", machine().time().as_string(), machine().describe_context(), data, checkpoint_live.shift_reg);
431431
432432   return data;
433433}
r242339r242340
439439      live_sync();
440440      m_pi = cur_live.pi = data;
441441      checkpoint();
442      if (LOG) logerror("%s PI %02x\n", machine().time().as_string(), data);
442      if (LOG) logerror("%s %s PI %02x\n", machine().time().as_string(), machine().describe_context(), data);
443443      live_run();
444444   }
445445}
r242339r242340
451451      live_sync();
452452      m_drv_sel = cur_live.drv_sel = state;
453453      checkpoint();
454      if (LOG) logerror("%s DRV SEL %u\n", machine().time().as_string(), state);
454      if (LOG) logerror("%s %s DRV SEL %u\n", machine().time().as_string(), machine().describe_context(), state);
455455      live_run();
456456   }
457457}
r242339r242340
463463      live_sync();
464464      m_mode_sel = cur_live.mode_sel = state;
465465      checkpoint();
466      if (LOG) logerror("%s MODE SEL %u\n", machine().time().as_string(), state);
466      if (LOG) logerror("%s %s MODE SEL %u\n", machine().time().as_string(), machine().describe_context(), state);
467467      live_run();
468468   }
469469}
r242339r242340
475475      live_sync();
476476      m_rw_sel = cur_live.rw_sel = state;
477477      checkpoint();
478      if (LOG) logerror("%s RW SEL %u\n", machine().time().as_string(), state);
478      if (LOG) logerror("%s %s RW SEL %u\n", machine().time().as_string(), machine().describe_context(), state);
479479      if (m_rw_sel) {
480480         stop_writing(machine().time());
481481      } else {
r242339r242340
491491   {
492492      live_sync();
493493      m_mtr0 = state;
494      if (LOG) logerror("%s MTR0 %u\n", machine().time().as_string(), state);
494      if (LOG) logerror("%s %s MTR0 %u\n", machine().time().as_string(), machine().describe_context(), state);
495495      m_floppy0->mon_w(state);
496496      checkpoint();
497497
r242339r242340
513513   {
514514      live_sync();
515515      m_mtr1 = state;
516      if (LOG) logerror("%s MTR1 %u\n", machine().time().as_string(), state);
516      if (LOG) logerror("%s %s MTR1 %u\n", machine().time().as_string(), machine().describe_context(), state);
517517      if (m_floppy1) m_floppy1->mon_w(state);
518518      checkpoint();
519519
r242339r242340
587587   {
588588      live_sync();
589589      m_ds = cur_live.ds = ds;
590      if (LOG) logerror("%s %s DS %u\n", machine().time().as_string(), machine().describe_context(), ds);
590591      checkpoint();
591592      live_run();
592593   }
trunk/src/emu/bus/ieee488/c8050fdc.c
r242339r242340
1717//  MACROS / CONSTANTS
1818//**************************************************************************
1919
20#define LOG 0
20#define LOG 1
2121
22#define GCR_DECODE(_e, _i) \
23    ((BIT(_e, 6) << 7) | (BIT(_i, 7) << 6) | (_e & 0x33) | (BIT(_e, 2) << 3) | (_i & 0x04))
2224
25#define GCR_ENCODE(_e, _i) \
26    ((_e & 0xc0) << 2 | (_i & 0x80) | (_e & 0x3c) << 1 | (_i & 0x04) | (_e & 0x03))
2327
28
29
2430//**************************************************************************
2531//  DEVICE DEFINITIONS
2632//**************************************************************************
r242339r242340
7278   m_ds(0),
7379   m_drv_sel(0),
7480   m_mode_sel(0),
75   m_rw_sel(0),
76   m_period(attotime::from_hz(clock))
81   m_rw_sel(0)
7782{
7883   cur_live.tm = attotime::never;
7984   cur_live.state = IDLE;
r242339r242340
169174   if (m_stp0 != stp)
170175   {
171176      live_sync();
172      this->stp_w(m_floppy0, m_mtr0, m_stp0, stp);
177      stp_w(m_floppy0, m_mtr0, m_stp0, stp);
173178      checkpoint();
174179      live_run();
175180   }
r242339r242340
180185   if (m_stp1 != stp)
181186   {
182187      live_sync();
183      if (m_floppy1) this->stp_w(m_floppy1, m_mtr1, m_stp1, stp);
188      if (m_floppy1) stp_w(m_floppy1, m_mtr1, m_stp1, stp);
184189      checkpoint();
185190      live_run();
186191   }
r242339r242340
192197   {
193198      live_sync();
194199      m_ds = cur_live.ds = ds;
200      pll_reset(cur_live.tm, attotime::from_hz(clock() / (16 - m_ds)));
195201      checkpoint();
196202      live_run();
197203   }
r242339r242340
220226   cur_live.rw_sel = m_rw_sel;
221227   cur_live.pi = m_pi;
222228
223   pll_reset(cur_live.tm, attotime::from_double(0));
229   pll_reset(cur_live.tm, attotime::from_hz(clock() / (16 - m_ds)));
224230   checkpoint_live = cur_live;
225231   pll_save_checkpoint();
226232
r242339r242340
281287   pll_retrieve_checkpoint();
282288}
283289
290void c8050_fdc_t::live_delay(int state)
291{
292   cur_live.next_state = state;
293   if(cur_live.tm != machine().time())
294      t_gen->adjust(cur_live.tm - machine().time());
295   else
296      live_sync();
297}
298
284299void c8050_fdc_t::live_sync()
285300{
286301   if(!cur_live.tm.is_never()) {
r242339r242340
322337   cur_live.error = 1;
323338}
324339
325
326340void c8050_fdc_t::live_run(const attotime &limit)
327341{
328342   if(cur_live.state == IDLE || cur_live.next_state != -1)
r242339r242340
340354         if(bit < 0)
341355            return;
342356
357         cur_live.shift_reg <<= 1;
358         cur_live.shift_reg |= bit;
359         cur_live.shift_reg &= 0x3ff;
360
361         // sync
362         int sync = !((cur_live.shift_reg == 0x3ff) && cur_live.rw_sel);
363
364         // bit counter
365         if (cur_live.rw_sel) {
366            if (!sync) {
367               cur_live.bit_counter = 0;
368            } else if (cur_live.sync) {
369               cur_live.bit_counter++;
370               if (cur_live.bit_counter == 10) {
371                  cur_live.bit_counter = 0;
372               }
373            }
374         } else {
375            cur_live.bit_counter++;
376            if (cur_live.bit_counter == 10) {
377               cur_live.bit_counter = 0;
378            }
379         }
380
381         // GCR decoder
382         if (cur_live.rw_sel) {
383            cur_live.i = cur_live.shift_reg;
384         } else {
385            cur_live.i = ((cur_live.pi & 0xf0) << 1) | (cur_live.mode_sel << 4) | (cur_live.pi & 0x0f);
386         }
387
388         cur_live.e = m_gcr_rom->base()[cur_live.rw_sel << 10 | cur_live.i];
389
390         if (LOG) logerror("%s cyl %u bit %u sync %u bc %u sr %03x i %03x e %02x\n",cur_live.tm.as_string(),get_floppy()->get_cyl(),bit,sync,cur_live.bit_counter,cur_live.shift_reg,cur_live.i,cur_live.e);
391
392         // byte ready
393         int ready = !(cur_live.bit_counter == 9);
394
395         // GCR error
396         int error = !(ready || BIT(cur_live.e, 3));
397
398         // write bit
399         if (!cur_live.rw_sel) { // TODO WPS
400            int write_bit = BIT(cur_live.shift_reg_write, 9);
401            if (LOG) logerror("%s writing bit %u sr %03x\n",cur_live.tm.as_string(),write_bit,cur_live.shift_reg_write);
402            pll_write_next_bit(write_bit, cur_live.tm, get_floppy(), limit);
403         }
404
405         if (!ready) {
406            // load write shift register
407            cur_live.shift_reg_write = GCR_ENCODE(cur_live.e, cur_live.i);
408
409            if (LOG) logerror("%s load write shift register %03x\n",cur_live.tm.as_string(),cur_live.shift_reg_write);
410         } else {
411            // clock write shift register
412            cur_live.shift_reg_write <<= 1;
413            cur_live.shift_reg_write &= 0x3ff;
414         }
415
416         if (ready != cur_live.ready) {
417            if (LOG) logerror("%s READY %u : %02x\n", cur_live.tm.as_string(),ready,GCR_DECODE(cur_live.e, cur_live.i));
418            cur_live.ready = ready;
419            syncpoint = true;
420         }
421
422         if (sync != cur_live.sync) {
423            if (LOG) logerror("%s SYNC %u\n", cur_live.tm.as_string(),sync);
424            cur_live.sync = sync;
425            syncpoint = true;
426         }
427
428         if (error != cur_live.error) {
429            if (LOG) logerror("%s ERROR %u\n", cur_live.tm.as_string(),error);
430            cur_live.error = error;
431            syncpoint = true;
432         }
433
343434         if (syncpoint) {
344435            live_delay(RUNNING_SYNCPOINT);
345436            return;
r242339r242340
367458
368459   UINT8 data = (BIT(e, 6) << 7) | (BIT(i, 7) << 6) | (e & 0x33) | (BIT(e, 2) << 3) | (i & 0x04);
369460
370   if (LOG) logerror("%s VIA reads data %02x (%03x)\n", machine().time().as_string(), data, checkpoint_live.shift_reg);
461   if (LOG) logerror("%s %s VIA reads data %02x (%03x)\n", machine().time().as_string(), machine().describe_context(), data, checkpoint_live.shift_reg);
371462
372463   return data;
373464}
r242339r242340
379470      live_sync();
380471      m_pi = cur_live.pi = data;
381472      checkpoint();
382      if (LOG) logerror("%s PI %02x\n", machine().time().as_string(), data);
473      if (LOG) logerror("%s %s PI %02x\n", machine().time().as_string(), machine().describe_context(), data);
383474      live_run();
384475   }
385476}
r242339r242340
391482      live_sync();
392483      m_drv_sel = cur_live.drv_sel = state;
393484      checkpoint();
394      if (LOG) logerror("%s DRV SEL %u\n", machine().time().as_string(), state);
485      if (LOG) logerror("%s %s DRV SEL %u\n", machine().time().as_string(), machine().describe_context(), state);
395486      live_run();
396487   }
397488}
r242339r242340
403494      live_sync();
404495      m_mode_sel = cur_live.mode_sel = state;
405496      checkpoint();
406      if (LOG) logerror("%s MODE SEL %u\n", machine().time().as_string(), state);
497      if (LOG) logerror("%s %s MODE SEL %u\n", machine().time().as_string(), machine().describe_context(), state);
407498      live_run();
408499   }
409500}
r242339r242340
415506      live_sync();
416507      m_rw_sel = cur_live.rw_sel = state;
417508      checkpoint();
418      if (LOG) logerror("%s RW SEL %u\n", machine().time().as_string(), state);
509      if (LOG) logerror("%s %s RW SEL %u\n", machine().time().as_string(), machine().describe_context(), state);
419510      if (m_rw_sel) {
420511         pll_stop_writing(get_floppy(), machine().time());
421512      } else {
r242339r242340
431522   {
432523      live_sync();
433524      m_mtr0 = state;
434      if (LOG) logerror("%s MTR0 %u\n", machine().time().as_string(), state);
525      if (LOG) logerror("%s %s MTR0 %u\n", machine().time().as_string(), machine().describe_context(), state);
435526      m_floppy0->mon_w(state);
436527      checkpoint();
437528
r242339r242340
453544   {
454545      live_sync();
455546      m_mtr1 = state;
456      if (LOG) logerror("%s MTR1 %u\n", machine().time().as_string(), state);
547      if (LOG) logerror("%s %s MTR1 %u\n", machine().time().as_string(), machine().describe_context(), state);
457548      if (m_floppy1) m_floppy1->mon_w(state);
458549      checkpoint();
459550
r242339r242340
475566   {
476567      live_sync();
477568      m_odd_hd = cur_live.odd_hd = state;
478      if (LOG) logerror("%s ODD HD %u\n", machine().time().as_string(), state);
569      if (LOG) logerror("%s %s ODD HD %u\n", machine().time().as_string(), machine().describe_context(), state);
479570      m_floppy0->ss_w(!state);
480571      if (m_floppy1) m_floppy1->ss_w(!state);
481572      checkpoint();
r242339r242340
486577WRITE_LINE_MEMBER( c8050_fdc_t::pull_sync_w )
487578{
488579   // TODO
489   if (LOG) logerror("%s PULL SYNC %u\n", machine().time().as_string(), state);
580   if (LOG) logerror("%s %s PULL SYNC %u\n", machine().time().as_string(), machine().describe_context(), state);
490581}
trunk/src/emu/bus/ieee488/c8050fdc.h
r242339r242340
6565   DECLARE_WRITE_LINE_MEMBER( pull_sync_w );
6666
6767   DECLARE_READ_LINE_MEMBER( wps_r ) { return checkpoint_live.drv_sel ? m_floppy1->wpt_r() : m_floppy0->wpt_r(); }
68   DECLARE_READ_LINE_MEMBER( sync_r ) { return checkpoint_live.sync; }
6968
7069   void stp0_w(int stp);
7170   void stp1_w(int stp);
r242339r242340
134133   int m_odd_hd;
135134   UINT8 m_pi;
136135
137   attotime m_period;
138
139136   live_info cur_live, checkpoint_live;
140137   fdc_pll_t cur_pll, checkpoint_pll;
141138   emu_timer *t_gen;
trunk/src/lib/formats/d64_dsk.h
r242339r242340
6363   virtual int get_sectors_per_track(const format &f, int track);
6464   virtual int get_disk_id_offset(const format &f);
6565   void get_disk_id(const format &f, io_generic *io, UINT8 &id1, UINT8 &id2);
66   floppy_image_format_t::desc_e* get_sector_desc(const format &f, int &current_size, int sector_count, UINT8 id1, UINT8 id2, int gap_2);
66   virtual floppy_image_format_t::desc_e* get_sector_desc(const format &f, int &current_size, int sector_count, UINT8 id1, UINT8 id2, int gap_2);
6767   void build_sector_description(const format &f, UINT8 *sectdata, offs_t sect_offs, offs_t error_offs, desc_s *sectors, int sector_count) const;
6868
6969   static const format file_formats[];
trunk/src/lib/formats/d80_dsk.c
r242339r242340
4343
4444const UINT32 d80_format::d80_cell_size[] =
4545{
46   2667, // 12MHz/16/2
47   2500, // 12MHz/15/2
48   2333, // 12MHz/14/2
49   2167  // 12MHz/13/2
46   2667, // 12MHz/2/16
47   2500, // 12MHz/2/15
48   2333, // 12MHz/2/14
49   2167  // 12MHz/2/13
5050};
5151
5252const int d80_format::d80_sectors_per_track[] =

https://github.com/mamedev/mame/commit/af46cb98f92c50353c0d5de6a9c1044732032fcd

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