trunk/src/mame/drivers/gts1.c
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| 67 | 67 | |
| 68 | 68 | |
| 69 | 69 | #include "machine/genpin.h" |
| 70 | #include "machine/r10696.h" |
| 70 | 71 | #include "machine/r10788.h" |
| 71 | 72 | #include "cpu/pps4/pps4.h" |
| 72 | 73 | #include "gts1.lh" |
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| 92 | 93 | DECLARE_WRITE8_MEMBER(gts1_display_w); |
| 93 | 94 | DECLARE_READ8_MEMBER (gts1_io_r); |
| 94 | 95 | DECLARE_WRITE8_MEMBER(gts1_io_w); |
| 96 | DECLARE_READ8_MEMBER (gts1_nvram_r); |
| 97 | DECLARE_WRITE8_MEMBER(gts1_nvram_w); |
| 95 | 98 | DECLARE_READ8_MEMBER (gts1_pa_r); |
| 96 | 99 | DECLARE_WRITE8_MEMBER(gts1_pa_w); |
| 97 | 100 | DECLARE_WRITE8_MEMBER(gts1_pb_w); |
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| 99 | 102 | virtual void machine_reset(); |
| 100 | 103 | required_device<cpu_device> m_maincpu; |
| 101 | 104 | UINT8 m_io[256]; |
| 105 | UINT8 m_nvram_addr; |
| 102 | 106 | UINT8 m_6351_addr; |
| 103 | 107 | }; |
| 104 | 108 | |
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| 111 | 115 | ADDRESS_MAP_END |
| 112 | 116 | |
| 113 | 117 | static ADDRESS_MAP_START( gts1_io, AS_IO, 8, gts1_state ) |
| 114 | | AM_RANGE(0x00d0, 0x00df) AM_DEVREADWRITE ( "r10788", r10788_device, io_r, io_w ) |
| 118 | AM_RANGE(0x0060, 0x006f) AM_DEVREADWRITE ( "r10696", r10696_device, io_r, io_w ) // NVRAM io chip |
| 119 | AM_RANGE(0x00d0, 0x00df) AM_DEVREADWRITE ( "r10788", r10788_device, io_r, io_w ) // display chip |
| 115 | 120 | AM_RANGE(0x0000, 0x00ff) AM_READ ( gts1_io_r ) AM_WRITE( gts1_io_w ) // connects to all the other chips |
| 116 | 121 | |
| 117 | 122 | AM_RANGE(0x0100, 0x0100) AM_READ ( gts1_pa_r ) AM_WRITE( gts1_pa_w ) |
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| 200 | 205 | |
| 201 | 206 | void gts1_state::machine_reset() |
| 202 | 207 | { |
| 208 | m_nvram_addr = 0; |
| 203 | 209 | m_6351_addr = 0; |
| 204 | 210 | } |
| 205 | 211 | |
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| 274 | 280 | #undef _h |
| 275 | 281 | } |
| 276 | 282 | |
| 283 | READ8_MEMBER (gts1_state::gts1_nvram_r) |
| 284 | { |
| 285 | UINT8 data = 0x0f; |
| 286 | switch (offset) |
| 287 | { |
| 288 | case 0: // group A |
| 289 | // FIXME: Schematics says TO Z5 |
| 290 | break; |
| 291 | case 1: // group B |
| 292 | case 2: // group C |
| 293 | // Schematics says: SPARES |
| 294 | break; |
| 295 | } |
| 296 | return data; |
| 297 | } |
| 298 | |
| 299 | WRITE8_MEMBER(gts1_state::gts1_nvram_w) |
| 300 | { |
| 301 | switch (offset) |
| 302 | { |
| 303 | case 0: // group A - address lines 3:0 |
| 304 | m_nvram_addr = (m_nvram_addr & ~15) | (data & 15); |
| 305 | break; |
| 306 | case 1: // group B - address lines 7:4 |
| 307 | m_nvram_addr = (m_nvram_addr & ~(15 << 4)) | ((data & 15) << 4); |
| 308 | break; |
| 309 | case 2: // group C - data bits 3:0 of NVRAM |
| 310 | // FIXME: schematics says write enable is U4-36 (O14) |
| 311 | LOG(("%s: nvram[%02x] <- %x\n", __FUNCTION__, m_nvram_addr, data & 15)); |
| 312 | break; |
| 313 | } |
| 314 | } |
| 315 | |
| 277 | 316 | READ8_MEMBER (gts1_state::gts1_io_r) |
| 278 | 317 | { |
| 279 | 318 | UINT8 data = m_io[offset] & 0x0f; |
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| 320 | 359 | |
| 321 | 360 | //MCFG_NVRAM_ADD_0FILL("nvram") |
| 322 | 361 | |
| 362 | /* General Purpose Input/Output */ |
| 363 | MCFG_DEVICE_ADD( "r10696", R10696, 0 ) |
| 364 | MCFG_R10696_IO( READ8 (gts1_state,gts1_nvram_r), |
| 365 | WRITE8(gts1_state,gts1_nvram_w) ) |
| 366 | |
| 323 | 367 | /* General Purpose Display and Keyboard */ |
| 324 | 368 | MCFG_DEVICE_ADD( "r10788", R10788, XTAL_3_579545MHz / 18 ) // divided in the circuit |
| 325 | 369 | MCFG_R10788_UPDATE( WRITE8(gts1_state,gts1_display_w) ) |