trunk/src/emu/cpu/tms0980/tms0980.c
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| 48 | 48 | - Execute: |
| 49 | 49 | 1. Execute BRANCH/CALL/RETN part #1 |
| 50 | 50 | |
| 51 | */ |
| 51 | 52 | |
| 53 | #include "tms0980.h" |
| 54 | #include "debugger.h" |
| 55 | |
| 56 | /* |
| 57 | |
| 52 | 58 | The MCU cores contains a set of fixed instructions and a set of |
| 53 | 59 | instructions created using microinstructions. A subset of the |
| 54 | 60 | instruction set could be defined from the microinstructions by |
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| 58 | 64 | cycle #2: C8(?), CKM, NE(?), STO |
| 59 | 65 | cycle #3,#4: AUTA, AUTY |
| 60 | 66 | |
| 67 | unknown cycle: CME, SSE, SSS |
| 68 | |
| 61 | 69 | */ |
| 62 | 70 | |
| 63 | | #include "tms0980.h" |
| 64 | | #include "debugger.h" |
| 71 | /* Microinstructions */ |
| 72 | #define M_15TN 0x00000001 /* 15 to -ALU */ |
| 73 | #define M_ATN 0x00000002 /* ACC to -ALU */ |
| 74 | #define M_AUTA 0x00000004 /* ALU to ACC */ |
| 75 | #define M_AUTY 0x00000008 /* ALU to Y */ |
| 76 | #define M_C8 0x00000010 /* CARRY8 to STATUS */ |
| 77 | #define M_CIN 0x00000020 /* Carry In to ALU */ |
| 78 | #define M_CKM 0x00000040 /* CKB to MEM */ |
| 79 | #define M_CKN 0x00000080 /* CKB to -ALU */ |
| 80 | #define M_CKP 0x00000100 /* CKB to +ALU */ |
| 81 | #define M_CME 0x00000200 /* Conditional Memory Enable */ |
| 82 | #define M_DMTP 0x00000400 /* DAM to +ALU */ |
| 83 | #define M_MTN 0x00000800 /* MEM to -ALU */ |
| 84 | #define M_MTP 0x00001000 /* MEM to +ALU */ |
| 85 | #define M_NATN 0x00002000 /* ~ACC to -ALU */ |
| 86 | #define M_NDMTP 0x00004000 /* ~DAM to +ALU */ |
| 87 | #define M_NE 0x00008000 /* COMP to STATUS */ |
| 88 | #define M_SSE 0x00010000 /* Special Status Enable */ |
| 89 | #define M_SSS 0x00020000 /* Special Status Sample */ |
| 90 | #define M_STO 0x00040000 /* ACC to MEM */ |
| 91 | #define M_STSL 0x00080000 /* STATUS to Status Latch */ |
| 92 | #define M_YTP 0x00100000 /* Y to +ALU */ |
| 65 | 93 | |
| 94 | /* Standard/fixed instructions - these are documented more in their specific handlers below */ |
| 95 | #define F_BR 0x00000001 |
| 96 | #define F_CALL 0x00000002 |
| 97 | #define F_CLO 0x00000004 |
| 98 | #define F_COMC 0x00000008 |
| 99 | #define F_COMX 0x00000010 |
| 100 | #define F_COMX8 0x00000020 |
| 101 | #define F_LDP 0x00000040 |
| 102 | #define F_LDX 0x00000080 |
| 103 | #define F_OFF 0x00000100 |
| 104 | #define F_RBIT 0x00000200 |
| 105 | #define F_REAC 0x00000400 |
| 106 | #define F_RETN 0x00000800 |
| 107 | #define F_RSTR 0x00001000 |
| 108 | #define F_SAL 0x00002000 |
| 109 | #define F_SBIT 0x00004000 |
| 110 | #define F_SBL 0x00008000 |
| 111 | #define F_SEAC 0x00010000 |
| 112 | #define F_SETR 0x00020000 |
| 113 | #define F_TDO 0x00040000 |
| 114 | #define F_XDA 0x00080000 |
| 115 | |
| 116 | |
| 66 | 117 | // supported types: |
| 67 | 118 | // note: dice information assumes the orientation is pictured with RAM at the bottom-left |
| 68 | 119 | |
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| 289 | 340 | |
| 290 | 341 | |
| 291 | 342 | |
| 292 | | /* Standard/fixed instructions */ |
| 293 | | #define F_BR 0x00000001 |
| 294 | | #define F_CALL 0x00000002 |
| 295 | | #define F_CLO 0x00000004 |
| 296 | | #define F_COMC 0x00000008 |
| 297 | | #define F_COMX 0x00000010 |
| 298 | | #define F_COMX8 0x00000020 |
| 299 | | #define F_LDP 0x00000040 |
| 300 | | #define F_LDX 0x00000080 |
| 301 | | #define F_OFF 0x00000100 |
| 302 | | #define F_RBIT 0x00000200 |
| 303 | | #define F_REAC 0x00000400 |
| 304 | | #define F_RETN 0x00000800 |
| 305 | | #define F_RSTR 0x00001000 |
| 306 | | #define F_SAL 0x00002000 |
| 307 | | #define F_SBIT 0x00004000 |
| 308 | | #define F_SBL 0x00008000 |
| 309 | | #define F_SEAC 0x00010000 |
| 310 | | #define F_SETR 0x00020000 |
| 311 | | #define F_TDO 0x00040000 |
| 312 | | #define F_XDA 0x00080000 |
| 313 | | |
| 314 | | /* Microinstructions */ |
| 315 | | #define M_15TN 0x00000001 |
| 316 | | #define M_ATN 0x00000002 |
| 317 | | #define M_AUTA 0x00000004 |
| 318 | | #define M_AUTY 0x00000008 |
| 319 | | #define M_C8 0x00000010 |
| 320 | | #define M_CIN 0x00000020 |
| 321 | | #define M_CKM 0x00000040 |
| 322 | | #define M_CKN 0x00000080 |
| 323 | | #define M_CKP 0x00000100 |
| 324 | | #define M_CME 0x00000200 |
| 325 | | #define M_DMTP 0x00000400 |
| 326 | | #define M_MTN 0x00000800 |
| 327 | | #define M_MTP 0x00001000 |
| 328 | | #define M_NATN 0x00002000 |
| 329 | | #define M_NDMTP 0x00004000 |
| 330 | | #define M_NE 0x00008000 |
| 331 | | #define M_SSE 0x00010000 |
| 332 | | #define M_SSS 0x00020000 |
| 333 | | #define M_STO 0x00040000 |
| 334 | | #define M_STSL 0x00080000 |
| 335 | | #define M_YTP 0x00100000 |
| 336 | | |
| 337 | | |
| 338 | | |
| 339 | 343 | //------------------------------------------------- |
| 340 | 344 | // device_start - device-specific startup |
| 341 | 345 | //------------------------------------------------- |