Previous

199869 Revisions

Next

r33148 Sunday 2nd November, 2014 at 19:31:20 UTC by Curt Coder
(MESS) victor9k: Floppy WIP. (nw)

[src/mess/drivers]	victor9k.c
[src/mess/includes]	victor9k.h
[src/mess/machine]	victor9k_fdc.c victor9k_fdc.h

trunk/src/mess/drivers/victor9k.c

r241659	r241660
47	47	AM_RANGE(0xe8040, 0xe804f) AM_DEVREADWRITE(M6522_2_TAG, via6522_device, read, write)
48	48	AM_RANGE(0xe8060, 0xe8061) AM_DEVREADWRITE(MC6852_TAG, mc6852_device, read, write)
49	49	AM_RANGE(0xe8080, 0xe808f) AM_DEVREADWRITE(M6522_3_TAG, via6522_device, read, write)
50		AM_RANGE(0xe80a0, 0xe80af) AM_DEVREADWRITE(M6522_4_TAG, via6522_device, read, write)
51		AM_RANGE(0xe80c0, 0xe80cf) AM_DEVREADWRITE(M6522_6_TAG, via6522_device, read, write)
52		AM_RANGE(0xe80e0, 0xe80ef) AM_DEVREADWRITE(M6522_5_TAG, via6522_device, read, write)
	50	AM_RANGE(0xe80a0, 0xe80af) AM_DEVREADWRITE(FDC_TAG, victor_9000_fdc_t, cs5_r, cs5_w)
	51	AM_RANGE(0xe80c0, 0xe80cf) AM_DEVREADWRITE(FDC_TAG, victor_9000_fdc_t, cs6_r, cs6_w)
	52	AM_RANGE(0xe80e0, 0xe80ef) AM_DEVREADWRITE(FDC_TAG, victor_9000_fdc_t, cs7_r, cs7_w)
53	53	AM_RANGE(0xf0000, 0xf0fff) AM_MIRROR(0x1000) AM_RAM AM_SHARE("video_ram")
54	54	AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_REGION(I8088_TAG, 0)
55	55	ADDRESS_MAP_END
r241659	r241660
160	160	{
161	161	m_ssda_irq = state;
162	162
163		m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_via4_irq || m_via5_irq || m_via6_irq);
	163	m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
164	164	}
165	165
166	166
r241659	r241660
232	232	{
233	233	m_via1_irq = state;
234	234
235		m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_via4_irq || m_via5_irq || m_via6_irq);
	235	m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
236	236	}
237	237
238	238	WRITE8_MEMBER( victor9k_state::via2_pa_w )
r241659	r241660
299	299	{
300	300	m_via2_irq = state;
301	301
302		m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_via4_irq || m_via5_irq || m_via6_irq);
	302	m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
303	303	}
304	304
305	305
r241659	r241660
339	339	{
340	340	m_via3_irq = state;
341	341
342		m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_via4_irq || m_via5_irq || m_via6_irq);
	342	m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
343	343	}
344	344
345	345
346		WRITE8_MEMBER( victor9k_state::via4_pa_w )
347		{
348		/*
349
350		bit     description
351
352		PA0     L0MS0
353		PA1     L0MS1
354		PA2     L0MS2
355		PA3     L0MS3
356		PA4     ST0A
357		PA5     ST0B
358		PA6     ST0C
359		PA7     ST0D
360
361		*/
362
363		m_fdc->l0ms_w(data & 0x0f);
364		m_fdc->st0_w(data >> 4);
365		}
366
367		WRITE8_MEMBER( victor9k_state::via4_pb_w )
368		{
369		/*
370
371		bit     description
372
373		PB0     L1MS0
374		PB1     L1MS1
375		PB2     L1MS2
376		PB3     L1MS3
377		PB4     ST1A
378		PB5     ST1B
379		PB6     ST1C
380		PB7     ST1D
381
382		*/
383
384		m_fdc->l1ms_w(data & 0x0f);
385		m_fdc->st1_w(data >> 4);
386		}
387
388		WRITE_LINE_MEMBER( victor9k_state::mode_w )
389		{
390		}
391
392		WRITE_LINE_MEMBER( victor9k_state::via4_irq_w )
393		{
394		m_via4_irq = state;
395
396		m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_via4_irq || m_via5_irq || m_via6_irq);
397		}
398
399
400		/*
401
402		bit     description
403
404		PA0     E0
405		PA1     E1
406		PA2     I1
407		PA3     E2
408		PA4     E4
409		PA5     E5
410		PA6     I7
411		PA7     E6
412
413		*/
414
415		WRITE8_MEMBER( victor9k_state::via5_pb_w )
416		{
417		/*
418
419		bit     description
420
421		PB0     WD0
422		PB1     WD1
423		PB2     WD2
424		PB3     WD3
425		PB4     WD4
426		PB5     WD5
427		PB6     WD6
428		PB7     WD7
429
430		*/
431		}
432
433		WRITE_LINE_MEMBER( victor9k_state::via5_irq_w )
434		{
435		m_via5_irq = state;
436
437		m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_via4_irq || m_via5_irq || m_via6_irq);
438		}
439
440
441		READ8_MEMBER( victor9k_state::via6_pa_r )
442		{
443		/*
444
445		bit     description
446
447		PA0
448		PA1     _TRK0D0
449		PA2
450		PA3     _TRK0D1
451		PA4
452		PA5
453		PA6     WPS
454		PA7     _SYNC
455
456		*/
457
458		UINT8 data = 0;
459
460		// track 0 drive A sense
461		data |= m_fdc->trk0d0_r() << 1;
462
463		// track 0 drive B sense
464		data |= m_fdc->trk0d1_r() << 3;
465
466		// write protect sense
467		data |= m_fdc->wps_r() << 6;
468
469		// disk sync detect
470		data |= m_fdc->sync_r() << 7;
471
472		return data;
473		}
474
475		WRITE8_MEMBER( victor9k_state::via6_pa_w )
476		{
477		/*
478
479		bit     description
480
481		PA0     LED0A
482		PA1
483		PA2     LED1A
484		PA3
485		PA4     SIDE SELECT
486		PA5     DRIVE SELECT
487		PA6
488		PA7
489
490		*/
491
492		// LED, drive A
493		m_fdc->led0a_w(BIT(data, 0));
494
495		// LED, drive B
496		m_fdc->led1a_w(BIT(data, 2));
497
498		// dual side select
499		m_fdc->side_select_w(BIT(data, 4));
500
501		// select drive A/B
502		m_fdc->drive_select_w(BIT(data, 5));
503		}
504
505		READ8_MEMBER( victor9k_state::via6_pb_r )
506		{
507		/*
508
509		bit     description
510
511		PB0     RDY0
512		PB1     RDY1
513		PB2
514		PB3     _DS1
515		PB4     _DS0
516		PB5     SINGLE/_DOUBLE SIDED
517		PB6
518		PB7
519
520		*/
521
522		UINT8 data = 0;
523
524		// motor speed status, drive A
525		data |= m_fdc->rdy0_r();
526
527		// motor speed status, drive B
528		data |= m_fdc->rdy1_r() << 1;
529
530		// door B sense
531		data |= m_fdc->ds1_r() << 3;
532
533		// door A sense
534		data |= m_fdc->ds0_r() << 4;
535
536		// single/double sided
537		data |= m_fdc->single_double_sided_r() << 5;
538
539		return data;
540		}
541
542		WRITE8_MEMBER( victor9k_state::via6_pb_w )
543		{
544		/*
545
546		bit     description
547
548		PB0
549		PB1
550		PB2     _SCRESET
551		PB3
552		PB4
553		PB5
554		PB6     STP0
555		PB7     STP1
556
557		*/
558
559		// motor speed controller reset
560		m_fdc->screset_w(BIT(data, 2));
561
562		// stepper enable A
563		m_fdc->stp0_w(BIT(data, 6));
564
565		// stepper enable B
566		m_fdc->stp1_w(BIT(data, 7));
567		}
568
569		WRITE_LINE_MEMBER( victor9k_state::via6_irq_w )
570		{
571		m_via6_irq = state;
572
573		m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_via4_irq || m_via5_irq || m_via6_irq);
574		}
575
576
577	346	//-------------------------------------------------
578	347	//  VICTOR9K_KEYBOARD_INTERFACE( kb_intf )
579	348	//-------------------------------------------------
r241659	r241660
594	363	}
595	364
596	365
	366	WRITE_LINE_MEMBER( victor9k_state::fdc_irq_w )
	367	{
	368	m_fdc_irq = state;
	369
	370	m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
	371	}
	372
	373
597	374	//**************************************************************************
598	375	//  MACHINE INITIALIZATION
599	376	//**************************************************************************
r241659	r241660
610	387	save_item(NAME(m_via1_irq));
611	388	save_item(NAME(m_via2_irq));
612	389	save_item(NAME(m_via3_irq));
613		save_item(NAME(m_via4_irq));
614		save_item(NAME(m_via5_irq));
615		save_item(NAME(m_via6_irq));
	390	save_item(NAME(m_fdc_irq));
616	391	save_item(NAME(m_ssda_irq));
617	392
618	393	// memory banking
r241659	r241660
707	482	MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(victor9k_state, via3_pb_w))
708	483	MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor9k_state, via3_irq_w))
709	484
710		MCFG_DEVICE_ADD(M6522_4_TAG, VIA6522, XTAL_30MHz/30)
711		MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(victor9k_state, via4_pa_w))
712		MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(victor9k_state, via4_pb_w))
713		MCFG_VIA6522_CA2_HANDLER(WRITELINE(victor9k_state, mode_w))
714		MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor9k_state, via4_irq_w))
715
716		MCFG_DEVICE_ADD(M6522_5_TAG, VIA6522, XTAL_30MHz/30)
717		MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor9k_state, via5_irq_w))
718
719		MCFG_DEVICE_ADD(M6522_6_TAG, VIA6522, XTAL_30MHz/30)
720		MCFG_VIA6522_READPA_HANDLER(READ8(victor9k_state, via6_pa_r))
721		MCFG_VIA6522_READPB_HANDLER(READ8(victor9k_state, via6_pb_r))
722		MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(victor9k_state, via6_pa_w))
723		MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(victor9k_state, via6_pb_w))
724		MCFG_VIA6522_CA2_HANDLER(DEVWRITELINE(FDC_TAG, victor_9000_fdc_t, drw_w))
725		MCFG_VIA6522_CB2_HANDLER(DEVWRITELINE(FDC_TAG, victor_9000_fdc_t, erase_w))
726		MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor9k_state, via6_irq_w))
727
728	485	MCFG_RS232_PORT_ADD(RS232_A_TAG, default_rs232_devices, NULL)
729	486	MCFG_RS232_RXD_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, rxa_w))
730	487	MCFG_RS232_DCD_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, dcda_w))
r241659	r241660
744	501	MCFG_VICTOR9K_KBDATA_HANDLER(WRITELINE(victor9k_state, kbdata_w))
745	502
746	503	MCFG_DEVICE_ADD(FDC_TAG, VICTOR_9000_FDC, 0)
747		MCFG_VICTOR_9000_FDC_DS0_CB(DEVWRITELINE(M6522_4_TAG, via6522_device, write_ca1))
748		MCFG_VICTOR_9000_FDC_DS1_CB(DEVWRITELINE(M6522_4_TAG, via6522_device, write_cb1))
749		MCFG_VICTOR_9000_FDC_RDY0_CB(DEVWRITELINE(M6522_5_TAG, via6522_device, write_ca2))
750		MCFG_VICTOR_9000_FDC_RDY1_CB(DEVWRITELINE(M6522_5_TAG, via6522_device, write_cb2))
751		MCFG_VICTOR_9000_FDC_BRDY_CB(DEVWRITELINE(M6522_5_TAG, via6522_device, write_ca1))
752		MCFG_VICTOR_9000_FDC_GCRERR_CB(DEVWRITELINE(M6522_6_TAG, via6522_device, write_ca1))
	504	MCFG_VICTOR_9000_FDC_IRQ_CB(WRITELINE(victor9k_state, fdc_irq_w))
753	505
754	506	// internal ram
755	507	MCFG_RAM_ADD(RAM_TAG)

trunk/src/mess/includes/victor9k.h

r241659	r241660
41	41	#define M6522_1_TAG     "m6522_1"
42	42	#define M6522_2_TAG     "m6522_2"
43	43	#define M6522_3_TAG     "14l"
44		#define M6522_4_TAG     "1f"
45		#define M6522_5_TAG     "1k"
46		#define M6522_6_TAG     "1h"
47	44	#define DAC0808_0_TAG   "5b"
48	45	#define DAC0808_1_TAG   "5c"
49	46	#define CENTRONICS_TAG  "centronics"
r241659	r241660
66	63	m_via1(*this, M6522_1_TAG),
67	64	m_via2(*this, M6522_2_TAG),
68	65	m_via3(*this, M6522_3_TAG),
69		m_via4(*this, M6522_4_TAG),
70		m_via5(*this, M6522_5_TAG),
71		m_via6(*this, M6522_6_TAG),
72	66	m_cvsd(*this, HC55516_TAG),
73	67	m_crtc(*this, HD46505S_TAG),
74	68	m_ram(*this, RAM_TAG),
r241659	r241660
83	77	m_via1_irq(CLEAR_LINE),
84	78	m_via2_irq(CLEAR_LINE),
85	79	m_via3_irq(CLEAR_LINE),
86		m_via4_irq(CLEAR_LINE),
87		m_via5_irq(CLEAR_LINE),
88		m_via6_irq(CLEAR_LINE),
	80	m_fdc_irq(CLEAR_LINE),
89	81	m_ssda_irq(CLEAR_LINE)
90	82	{ }
91	83
r241659	r241660
97	89	required_device<via6522_device> m_via1;
98	90	required_device<via6522_device> m_via2;
99	91	required_device<via6522_device> m_via3;
100		required_device<via6522_device> m_via4;
101		required_device<via6522_device> m_via5;
102		required_device<via6522_device> m_via6;
103	92	required_device<hc55516_device> m_cvsd;
104	93	required_device<mc6845_device> m_crtc;
105	94	required_device<ram_device> m_ram;
r241659	r241660
128	117	DECLARE_WRITE8_MEMBER( via3_pb_w );
129	118	DECLARE_WRITE_LINE_MEMBER( via3_irq_w );
130	119
131		DECLARE_WRITE8_MEMBER( via4_pa_w );
132		DECLARE_WRITE8_MEMBER( via4_pb_w );
133		DECLARE_WRITE_LINE_MEMBER( mode_w );
134		DECLARE_WRITE_LINE_MEMBER( via4_irq_w );
	120	DECLARE_WRITE_LINE_MEMBER( fdc_irq_w );
135	121
136		DECLARE_WRITE8_MEMBER( via5_pb_w );
137		DECLARE_WRITE_LINE_MEMBER( via5_irq_w );
	122	DECLARE_WRITE_LINE_MEMBER( ssda_irq_w );
138	123
139		DECLARE_READ8_MEMBER( via6_pa_r );
140		DECLARE_READ8_MEMBER( via6_pb_r );
141		DECLARE_WRITE8_MEMBER( via6_pa_w );
142		DECLARE_WRITE8_MEMBER( via6_pb_w );
143	124	DECLARE_WRITE_LINE_MEMBER( kbrdy_w );
144	125	DECLARE_WRITE_LINE_MEMBER( kbdata_w );
145	126	DECLARE_WRITE_LINE_MEMBER( vert_w );
146		DECLARE_WRITE_LINE_MEMBER( via6_irq_w );
147	127
148		DECLARE_WRITE_LINE_MEMBER( ssda_irq_w );
149	128	MC6845_UPDATE_ROW( crtc_update_row );
150	129
151	130	/* video state */
r241659	r241660
156	135	int m_via1_irq;
157	136	int m_via2_irq;
158	137	int m_via3_irq;
159		int m_via4_irq;
160		int m_via5_irq;
161		int m_via6_irq;
	138	int m_fdc_irq;
162	139	int m_ssda_irq;
163	140
164	141	DECLARE_WRITE_LINE_MEMBER(mux_serial_b_w);

trunk/src/mess/machine/victor9k_fdc.c

r241659	r241660
28	28	#define LOG 0
29	29
30	30	#define I8048_TAG       "5d"
	31	#define M6522_4_TAG     "1f"
	32	#define M6522_5_TAG     "1k"
	33	#define M6522_6_TAG     "1h"
31	34
32	35
33	36
r241659	r241660
82	85	{
83	86	m_rdy0 = state;
84	87
85		m_rdy0_cb(state);
	88	m_via5->write_ca2(m_rdy0);
86	89	}
87	90
88	91	int victor_9000_fdc_t::load0_cb(floppy_image_device *device)
89	92	{
90	93	m_ds0 = 0;
91	94
92		m_ds0_cb(0);
	95	m_via4->write_ca1(m_ds0);
93	96
94	97	return IMAGE_INIT_PASS;
95	98	}
r241659	r241660
98	101	{
99	102	m_ds0 = 1;
100	103
101		m_ds0_cb(1);
	104	m_via4->write_ca1(m_ds0);
102	105	}
103	106
104	107	void victor_9000_fdc_t::ready1_cb(floppy_image_device *device, int state)
105	108	{
106	109	m_rdy1 = state;
107	110
108		m_rdy1_cb(state);
	111	m_via5->write_cb2(m_rdy1);
109	112	}
110	113
111	114	int victor_9000_fdc_t::load1_cb(floppy_image_device *device)
112	115	{
113	116	m_ds1 = 0;
114	117
115		m_ds1_cb(0);
	118	m_via4->write_cb1(m_ds1);
116	119
117	120	return IMAGE_INIT_PASS;
118	121	}
r241659	r241660
121	124	{
122	125	m_ds1 = 1;
123	126
124		m_ds1_cb(1);
	127	m_via4->write_cb1(m_ds1);
125	128	}
126	129
127	130	static SLOT_INTERFACE_START( victor9k_floppies )
r241659	r241660
141	144	MCFG_CPU_ADD(I8048_TAG, I8048, XTAL_30MHz/6)
142	145	MCFG_CPU_IO_MAP(floppy_io)
143	146
	147	MCFG_DEVICE_ADD(M6522_4_TAG, VIA6522, XTAL_30MHz/30)
	148	MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(victor_9000_fdc_t, via4_pa_w))
	149	MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(victor_9000_fdc_t, via4_pb_w))
	150	MCFG_VIA6522_CA2_HANDLER(WRITELINE(victor_9000_fdc_t, mode_w))
	151	MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor_9000_fdc_t, via4_irq_w))
	152
	153	MCFG_DEVICE_ADD(M6522_5_TAG, VIA6522, XTAL_30MHz/30)
	154	MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor_9000_fdc_t, via5_irq_w))
	155
	156	MCFG_DEVICE_ADD(M6522_6_TAG, VIA6522, XTAL_30MHz/30)
	157	MCFG_VIA6522_READPA_HANDLER(READ8(victor_9000_fdc_t, via6_pa_r))
	158	MCFG_VIA6522_READPB_HANDLER(READ8(victor_9000_fdc_t, via6_pb_r))
	159	MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(victor_9000_fdc_t, via6_pa_w))
	160	MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(victor_9000_fdc_t, via6_pb_w))
	161	MCFG_VIA6522_CA2_HANDLER(WRITELINE(victor_9000_fdc_t, drw_w))
	162	MCFG_VIA6522_CB2_HANDLER(WRITELINE(victor_9000_fdc_t, erase_w))
	163	MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor_9000_fdc_t, via6_irq_w))
	164
144	165	MCFG_FLOPPY_DRIVE_ADD(I8048_TAG":0", victor9k_floppies, "525qd", victor_9000_fdc_t::floppy_formats)
145	166	MCFG_FLOPPY_DRIVE_ADD(I8048_TAG":1", victor9k_floppies, "525qd", victor_9000_fdc_t::floppy_formats)
146	167	MACHINE_CONFIG_END
r241659	r241660
168	189
169	190	victor_9000_fdc_t::victor_9000_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
170	191	device_t(mconfig, VICTOR_9000_FDC, "Victor 9000 FDC", tag, owner, clock, "victor9k_fdc", __FILE__),
171		m_ds0_cb(*this),
172		m_ds1_cb(*this),
173		m_rdy0_cb(*this),
174		m_rdy1_cb(*this),
175		m_brdy_cb(*this),
176		m_gcrerr_cb(*this),
	192	m_irq_cb(*this),
177	193	m_maincpu(*this, I8048_TAG),
	194	m_via4(*this, M6522_4_TAG),
	195	m_via5(*this, M6522_5_TAG),
	196	m_via6(*this, M6522_6_TAG),
178	197	m_floppy0(*this, I8048_TAG":0:525qd"),
179	198	m_floppy1(*this, I8048_TAG":1:525qd"),
180	199	m_gcr_rom(*this, "gcr"),
r241659	r241660
198	217	m_side(0),
199	218	m_brdy(1),
200	219	m_sync(1),
201		m_gcrerr(0)
	220	m_gcrerr(0),
	221	m_via4_irq(CLEAR_LINE),
	222	m_via5_irq(CLEAR_LINE),
	223	m_via6_irq(CLEAR_LINE)
202	224	{
203	225	}
204	226
r241659	r241660
231	253	save_item(NAME(m_brdy));
232	254	save_item(NAME(m_sync));
233	255	save_item(NAME(m_gcrerr));
	256	save_item(NAME(m_via4_irq));
	257	save_item(NAME(m_via5_irq));
	258	save_item(NAME(m_via6_irq));
234	259	}
235	260
236	261
r241659	r241660
241	266	void victor_9000_fdc_t::device_reset()
242	267	{
243	268	// resolve callbacks
244		m_ds0_cb.resolve_safe();
245		m_ds1_cb.resolve_safe();
246		m_rdy0_cb.resolve_safe();
247		m_rdy1_cb.resolve_safe();
248		m_brdy_cb.resolve_safe();
249		m_gcrerr_cb.resolve_safe();
	269	m_irq_cb.resolve_safe();
250	270
251	271	// set floppy callbacks
252	272	m_floppy0->setup_ready_cb(floppy_image_device::ready_cb(FUNC(victor_9000_fdc_t::ready0_cb), this));
r241659	r241660
398	418	{
399	419	m_da = data;
400	420	}
	421
	422	WRITE8_MEMBER( victor_9000_fdc_t::via4_pa_w )
	423	{
	424	/*
	425
	426	bit     description
	427
	428	PA0     L0MS0
	429	PA1     L0MS1
	430	PA2     L0MS2
	431	PA3     L0MS3
	432	PA4     ST0A
	433	PA5     ST0B
	434	PA6     ST0C
	435	PA7     ST0D
	436
	437	*/
	438
	439	m_lms = (m_lms & 0xf0) | (data & 0x0f);
	440	m_st0 = data >> 4;
	441	}
	442
	443	WRITE8_MEMBER( victor_9000_fdc_t::via4_pb_w )
	444	{
	445	/*
	446
	447	bit     description
	448
	449	PB0     L1MS0
	450	PB1     L1MS1
	451	PB2     L1MS2
	452	PB3     L1MS3
	453	PB4     ST1A
	454	PB5     ST1B
	455	PB6     ST1C
	456	PB7     ST1D
	457
	458	*/
	459
	460	m_lms = (data << 4) | (m_lms & 0x0f);
	461	m_st1 = data >> 4;
	462	}
	463
	464	WRITE_LINE_MEMBER( victor_9000_fdc_t::mode_w )
	465	{
	466	}
	467
	468	WRITE_LINE_MEMBER( victor_9000_fdc_t::via4_irq_w )
	469	{
	470	m_via4_irq = state;
	471
	472	m_irq_cb(m_via4_irq || m_via5_irq || m_via6_irq);
	473	}
	474
	475
	476	/*
	477
	478	bit     description
	479
	480	PA0     E0
	481	PA1     E1
	482	PA2     I1
	483	PA3     E2
	484	PA4     E4
	485	PA5     E5
	486	PA6     I7
	487	PA7     E6
	488
	489	*/
	490
	491	WRITE8_MEMBER( victor_9000_fdc_t::via5_pb_w )
	492	{
	493	/*
	494
	495	bit     description
	496
	497	PB0     WD0
	498	PB1     WD1
	499	PB2     WD2
	500	PB3     WD3
	501	PB4     WD4
	502	PB5     WD5
	503	PB6     WD6
	504	PB7     WD7
	505
	506	*/
	507	}
	508
	509	WRITE_LINE_MEMBER( victor_9000_fdc_t::via5_irq_w )
	510	{
	511	m_via5_irq = state;
	512
	513	m_irq_cb(m_via4_irq || m_via5_irq || m_via6_irq);
	514	}
	515
	516
	517	READ8_MEMBER( victor_9000_fdc_t::via6_pa_r )
	518	{
	519	/*
	520
	521	bit     description
	522
	523	PA0
	524	PA1     _TRK0D0
	525	PA2
	526	PA3     _TRK0D1
	527	PA4
	528	PA5
	529	PA6     WPS
	530	PA7     _SYNC
	531
	532	*/
	533
	534	UINT8 data = 0;
	535
	536	// track 0 drive A sense
	537	data |= m_floppy0->trk00_r() << 1;
	538
	539	// track 0 drive B sense
	540	data |= m_floppy1->trk00_r() << 3;
	541
	542	// write protect sense
	543	data |= (m_drive ? m_floppy1->wpt_r() : m_floppy0->wpt_r()) << 6;
	544
	545	// disk sync detect
	546	data |= m_sync << 7;
	547
	548	return data;
	549	}
	550
	551	WRITE8_MEMBER( victor_9000_fdc_t::via6_pa_w )
	552	{
	553	/*
	554
	555	bit     description
	556
	557	PA0     LED0A
	558	PA1
	559	PA2     LED1A
	560	PA3
	561	PA4     SIDE SELECT
	562	PA5     DRIVE SELECT
	563	PA6
	564	PA7
	565
	566	*/
	567
	568	// LED, drive A
	569	output_set_led_value(LED_A, BIT(data, 0));
	570
	571	// LED, drive B
	572	output_set_led_value(LED_B, BIT(data, 2));
	573
	574	// dual side select
	575	m_side = BIT(data, 4);
	576
	577	// select drive A/B
	578	m_drive = BIT(data, 5);
	579	}
	580
	581	READ8_MEMBER( victor_9000_fdc_t::via6_pb_r )
	582	{
	583	/*
	584
	585	bit     description
	586
	587	PB0     RDY0
	588	PB1     RDY1
	589	PB2
	590	PB3     _DS1
	591	PB4     _DS0
	592	PB5     SINGLE/_DOUBLE SIDED
	593	PB6
	594	PB7
	595
	596	*/
	597
	598	UINT8 data = 0;
	599
	600	// motor speed status, drive A
	601	data |= m_rdy0;
	602
	603	// motor speed status, drive B
	604	data |= m_rdy1 << 1;
	605
	606	// door B sense
	607	data |= m_ds1 << 3;
	608
	609	// door A sense
	610	data |= m_ds0 << 4;
	611
	612	// single/double sided
	613	data |= (m_drive ? m_floppy1->twosid_r() : m_floppy0->twosid_r()) << 5;
	614
	615	return data;
	616	}
	617
	618	WRITE8_MEMBER( victor_9000_fdc_t::via6_pb_w )
	619	{
	620	/*
	621
	622	bit     description
	623
	624	PB0
	625	PB1
	626	PB2     _SCRESET
	627	PB3
	628	PB4
	629	PB5
	630	PB6     STP0
	631	PB7     STP1
	632
	633	*/
	634
	635	// motor speed controller reset
	636	if (!BIT(data, 2))
	637	m_maincpu->reset();
	638
	639	// stepper enable A
	640	m_stp0 = BIT(data, 6);
	641
	642	// stepper enable B
	643	m_stp1 = BIT(data, 7);
	644	}
	645
	646	WRITE_LINE_MEMBER( victor_9000_fdc_t::drw_w )
	647	{
	648	}
	649
	650	WRITE_LINE_MEMBER( victor_9000_fdc_t::erase_w )
	651	{
	652	}
	653
	654	WRITE_LINE_MEMBER( victor_9000_fdc_t::via6_irq_w )
	655	{
	656	m_via6_irq = state;
	657
	658	m_irq_cb(m_via4_irq || m_via5_irq || m_via6_irq);
	659	}

trunk/src/mess/machine/victor9k_fdc.h

r241659	r241660
18	18	#include "cpu/mcs48/mcs48.h"
19	19	#include "formats/victor9k_dsk.h"
20	20	#include "imagedev/floppy.h"
	21	#include "machine/6522via.h"
21	22
22	23
23	24
r241659	r241660
25	26	//  INTERFACE CONFIGURATION MACROS
26	27	//**************************************************************************
27	28
28		#define MCFG_VICTOR_9000_FDC_DS0_CB(_write) \
29		devcb = &victor_9000_fdc_t::set_ds0_wr_callback(*device, DEVCB_##_write);
	29	#define MCFG_VICTOR_9000_FDC_IRQ_CB(_write) \
	30	devcb = &victor_9000_fdc_t::set_irq_wr_callback(*device, DEVCB_##_write);
30	31
31		#define MCFG_VICTOR_9000_FDC_DS1_CB(_write) \
32		devcb = &victor_9000_fdc_t::set_ds1_wr_callback(*device, DEVCB_##_write);
33	32
34		#define MCFG_VICTOR_9000_FDC_RDY0_CB(_write) \
35		devcb = &victor_9000_fdc_t::set_rdy0_wr_callback(*device, DEVCB_##_write);
36	33
37		#define MCFG_VICTOR_9000_FDC_RDY1_CB(_write) \
38		devcb = &victor_9000_fdc_t::set_rdy1_wr_callback(*device, DEVCB_##_write);
39
40		#define MCFG_VICTOR_9000_FDC_BRDY_CB(_write) \
41		devcb = &victor_9000_fdc_t::set_brdy_wr_callback(*device, DEVCB_##_write);
42
43		#define MCFG_VICTOR_9000_FDC_GCRERR_CB(_write) \
44		devcb = &victor_9000_fdc_t::set_gcrerr_wr_callback(*device, DEVCB_##_write);
45
46
47
48	34	//**************************************************************************
49	35	//  TYPE DEFINITIONS
50	36	//**************************************************************************
r241659	r241660
57	43	// construction/destruction
58	44	victor_9000_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
59	45
60		template<class _Object> static devcb_base &set_ds0_wr_callback(device_t &device, _Object object) { return downcast<victor_9000_fdc_t &>(device).m_ds0_cb.set_callback(object); }
61		template<class _Object> static devcb_base &set_ds1_wr_callback(device_t &device, _Object object) { return downcast<victor_9000_fdc_t &>(device).m_ds1_cb.set_callback(object); }
62		template<class _Object> static devcb_base &set_rdy0_wr_callback(device_t &device, _Object object) { return downcast<victor_9000_fdc_t &>(device).m_rdy0_cb.set_callback(object); }
63		template<class _Object> static devcb_base &set_rdy1_wr_callback(device_t &device, _Object object) { return downcast<victor_9000_fdc_t &>(device).m_rdy1_cb.set_callback(object); }
64		template<class _Object> static devcb_base &set_brdy_wr_callback(device_t &device, _Object object) { return downcast<victor_9000_fdc_t &>(device).m_brdy_cb.set_callback(object); }
65		template<class _Object> static devcb_base &set_gcrerr_wr_callback(device_t &device, _Object object) { return downcast<victor_9000_fdc_t &>(device).m_gcrerr_cb.set_callback(object); }
	46	template<class _Object> static devcb_base &set_irq_wr_callback(device_t &device, _Object object) { return downcast<victor_9000_fdc_t &>(device).m_irq_cb.set_callback(object); }
66	47
67		void set_floppy(floppy_image_device *floppy0, floppy_image_device *floppy1);
	48	DECLARE_READ8_MEMBER( cs5_r ) { return m_via4->read(space, offset); }
	49	DECLARE_WRITE8_MEMBER( cs5_w ) { return m_via4->write(space, offset, data); }
	50	DECLARE_READ8_MEMBER( cs6_r ) { return m_via6->read(space, offset); }
	51	DECLARE_WRITE8_MEMBER( cs6_w ) { return m_via6->write(space, offset, data); }
	52	DECLARE_READ8_MEMBER( cs7_r ) { return m_via5->read(space, offset); }
	53	DECLARE_WRITE8_MEMBER( cs7_w ) { return m_via5->write(space, offset, data); }
68	54
69		void l0ms_w(UINT8 data) { m_lms = (m_lms & 0xf0) | (data & 0x0f); }
70		void l1ms_w(UINT8 data) { m_lms = (data << 4) | (m_lms & 0x0f); }
71		void st0_w(UINT8 data) { m_st0 = data; }
72		void st1_w(UINT8 data) { m_st1 = data; }
73		DECLARE_WRITE_LINE_MEMBER( side_select_w ) { m_side = state; }
74		DECLARE_WRITE_LINE_MEMBER( drive_select_w ) { m_drive = state; }
75		DECLARE_WRITE_LINE_MEMBER( stp0_w ) { m_stp0 = state; }
76		DECLARE_WRITE_LINE_MEMBER( stp1_w ) { m_stp1 = state; }
77		DECLARE_WRITE_LINE_MEMBER( drw_w ) { }
78		DECLARE_WRITE_LINE_MEMBER( erase_w ) { }
79		DECLARE_READ_LINE_MEMBER( trk0d0_r ) { return m_floppy0->trk00_r(); }
80		DECLARE_READ_LINE_MEMBER( trk0d1_r ) { return m_floppy1->trk00_r(); }
81		DECLARE_READ_LINE_MEMBER( wps_r ) { return m_drive ? m_floppy1->wpt_r() : m_floppy0->wpt_r(); }
82		DECLARE_READ_LINE_MEMBER( sync_r ) { return 1; }
83		DECLARE_WRITE_LINE_MEMBER( led0a_w ) { output_set_led_value(LED_A, state); }
84		DECLARE_WRITE_LINE_MEMBER( led1a_w ) { output_set_led_value(LED_B, state); }
85		DECLARE_READ_LINE_MEMBER( rdy0_r ) { return m_rdy0; }
86		DECLARE_READ_LINE_MEMBER( rdy1_r ) { return m_rdy1; }
87		DECLARE_READ_LINE_MEMBER( ds0_r ) { return m_ds0; }
88		DECLARE_READ_LINE_MEMBER( ds1_r ) { return m_ds1; }
89		DECLARE_READ_LINE_MEMBER( single_double_sided_r ) { return m_drive ? m_floppy1->twosid_r() : m_floppy0->twosid_r(); }
90		DECLARE_WRITE_LINE_MEMBER( screset_w ) { if (!state) m_maincpu->reset(); }
91
92	55	DECLARE_FLOPPY_FORMATS( floppy_formats );
93	56
94	57	DECLARE_READ8_MEMBER( floppy_p1_r );
r241659	r241660
98	61	DECLARE_READ8_MEMBER( tach1_r );
99	62	DECLARE_WRITE8_MEMBER( da_w );
100	63
	64	DECLARE_WRITE8_MEMBER( via4_pa_w );
	65	DECLARE_WRITE8_MEMBER( via4_pb_w );
	66	DECLARE_WRITE_LINE_MEMBER( mode_w );
	67	DECLARE_WRITE_LINE_MEMBER( via4_irq_w );
	68
	69	DECLARE_WRITE8_MEMBER( via5_pb_w );
	70	DECLARE_WRITE_LINE_MEMBER( via5_irq_w );
	71
	72	DECLARE_READ8_MEMBER( via6_pa_r );
	73	DECLARE_READ8_MEMBER( via6_pb_r );
	74	DECLARE_WRITE8_MEMBER( via6_pa_w );
	75	DECLARE_WRITE8_MEMBER( via6_pb_w );
	76	DECLARE_WRITE_LINE_MEMBER( drw_w );
	77	DECLARE_WRITE_LINE_MEMBER( erase_w );
	78	DECLARE_WRITE_LINE_MEMBER( via6_irq_w );
	79
101	80	protected:
102	81	// device-level overrides
103	82	virtual void device_start();
r241659	r241660
115	94	LED_B
116	95	};
117	96
118		devcb_write_line m_ds0_cb;
119		devcb_write_line m_ds1_cb;
120		devcb_write_line m_rdy0_cb;
121		devcb_write_line m_rdy1_cb;
122		devcb_write_line m_brdy_cb;
123		devcb_write_line m_gcrerr_cb;
	97	devcb_write_line m_irq_cb;
124	98
125	99	required_device<cpu_device> m_maincpu;
	100	required_device<via6522_device> m_via4;
	101	required_device<via6522_device> m_via5;
	102	required_device<via6522_device> m_via6;
126	103	required_device<floppy_image_device> m_floppy0;
127	104	required_device<floppy_image_device> m_floppy1;
128	105	required_memory_region m_gcr_rom;
r241659	r241660
156	133	int m_brdy;
157	134	int m_sync;
158	135	int m_gcrerr;
	136
	137	int m_via4_irq;
	138	int m_via5_irq;
	139	int m_via6_irq;
159	140	};
160	141
161	142

https://github.com/mamedev/mame/commit/4ede8ce068403c358d3153d2fcbc3ac12b972b17

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team