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r32830 Monday 20th October, 2014 at 00:37:21 UTC by Robbbert
gts3a.c : a bit of WIP
[src/mame/drivers]gts3.c gts3a.c

trunk/src/mame/drivers/gts3.c
r32829r32830
22
33  PINBALL
44  Gottlieb System 3
5  Alpha-Numeric Display
56
67Setting up:
78- Press F2
trunk/src/mame/drivers/gts3a.c
r32829r32830
1/*
2    Gottlieb System 3
3*/
1/****************************************************************************************************
42
3  PINBALL
4  Gottlieb System 3
5  Dot Matrix Display
56
6#include "emu.h"
7Status:
8- Nothing works
9- The code here has been copied from gts3 but not yet adjusted for this hardware
10
11ToDo:
12- Everything
13- There's an undumped GAL 16V8-25L on the DMD board (position U8)
14
15*****************************************************************************************************/
16
17#include "machine/genpin.h"
718#include "cpu/m6502/m65c02.h"
19#include "machine/6522via.h"
820
921class gts3a_state : public driver_device
1022{
1123public:
1224   gts3a_state(const machine_config &mconfig, device_type type, const char *tag)
13      : driver_device(mconfig, type, tag),
14         m_maincpu(*this, "maincpu")
25      : driver_device(mconfig, type, tag)
26      , m_maincpu(*this, "maincpu")
27      , m_u4(*this, "u4")
28      , m_u5(*this, "u5")
29      , m_switches(*this, "X")
1530   { }
1631
17protected:
18
19   // devices
20   required_device<cpu_device> m_maincpu;
21
22   // driver_device overrides
32   DECLARE_DRIVER_INIT(gts3a);
33   DECLARE_WRITE8_MEMBER(segbank_w);
34   DECLARE_READ8_MEMBER(u4a_r);
35   DECLARE_READ8_MEMBER(u4b_r);
36   DECLARE_WRITE8_MEMBER(u4b_w);
37   DECLARE_WRITE_LINE_MEMBER(nmi_w);
38   DECLARE_INPUT_CHANGED_MEMBER(test_inp);
39private:
40   bool m_dispclk;
41   bool m_lampclk;
42   UINT8 m_digit;
43   UINT8 m_row; // for lamps and switches
44   UINT8 m_segment[4];
45   UINT8 m_u4b;
2346   virtual void machine_reset();
24public:
25   DECLARE_DRIVER_INIT(gts3a);
47   required_device<m65c02_device> m_maincpu;
48   required_device<via6522_device> m_u4;
49   required_device<via6522_device> m_u5;
50   required_ioport_array<12> m_switches;
2651};
2752
2853
2954static ADDRESS_MAP_START( gts3a_map, AS_PROGRAM, 8, gts3a_state )
30   AM_RANGE(0x0000, 0xffff) AM_NOP
55   AM_RANGE(0x0000, 0x1fff) AM_RAM AM_SHARE("nvram")
56   AM_RANGE(0x2000, 0x200f) AM_DEVREADWRITE("u4", via6522_device, read, write)
57   AM_RANGE(0x2010, 0x201f) AM_DEVREADWRITE("u5", via6522_device, read, write)
58   AM_RANGE(0x2020, 0x2023) AM_MIRROR(0x0c) AM_WRITE(segbank_w)
59   AM_RANGE(0x4000, 0xffff) AM_ROM
3160ADDRESS_MAP_END
3261
3362static INPUT_PORTS_START( gts3a )
63   PORT_START("TTS")
64   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE) PORT_NAME("Test") PORT_CHANGED_MEMBER(DEVICE_SELF, gts3a_state, test_inp, 1)
65   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Slam Tilt") PORT_CODE(KEYCODE_7_PAD)
66   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_TILT)
67
68   PORT_START("X.0")
69   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_COIN1)
70   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_COIN3)
71   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_COIN2)
72   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_START)
73   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_SERVICE1) PORT_NAME("Left Advance")
74   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_SERVICE2) PORT_NAME("Right Advance")
75   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_MINUS)
76   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_EQUALS)
77
78   PORT_START("X.1")
79   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_A)
80   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_S)
81   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_D)
82   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_F)
83   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_G)
84   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_H)
85   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_J)
86   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_K)
87
88   PORT_START("X.2")
89   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_Q)
90   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_W)
91   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_E)
92   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_R)
93   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_Y)
94   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_U)
95   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_I)
96   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_O)
97
98   PORT_START("X.3")
99   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_Z)
100   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_X)
101   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_C)
102   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_V)
103   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_B)
104   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_N)
105   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_M)
106   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_COMMA)
107
108   PORT_START("X.4")
109   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_L)
110   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_BACKSPACE)
111   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_OPENBRACE)
112   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_CLOSEBRACE)
113   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_BACKSLASH)
114   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_COLON)
115   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_QUOTE)
116   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_ENTER)
117
118   PORT_START("X.5")
119   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_STOP)
120   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_SLASH)
121   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_SPACE)
122   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_CAPSLOCK)
123   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_UP)
124   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_DOWN)
125   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_LEFT)
126   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_RIGHT)
127
128   PORT_START("X.6")
129   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER)
130   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER)
131   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER)
132   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER)
133   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER)
134   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER)
135   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER)
136   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER)
137
138   PORT_START("X.7")
139   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER)
140   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER)
141   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER)
142   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER)
143   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER)
144   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER)
145   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER)
146   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER)
147
148   PORT_START("X.8")
149   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER)
150   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER)
151   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER)
152   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER)
153   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER)
154   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER)
155   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER)
156   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER)
157
158   PORT_START("X.9")
159   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER)
160   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER)
161   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER)
162   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER)
163   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER)
164   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER)
165   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER)
166   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER)
167
168   PORT_START("X.10")
169   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER)
170   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER)
171   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER)
172   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER)
173   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER)
174   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER)
175   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER)
176   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER)
177
178   PORT_START("X.11")
179   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER)
180   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER)
181   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER)
182   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER)
183   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER)
184   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER)
185   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER)
186   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER)
34187INPUT_PORTS_END
35188
189INPUT_CHANGED_MEMBER( gts3a_state::test_inp )
190{
191   m_u4->write_ca1(newval);
192}
193
194// This trampoline needed; DEVWRITELINE("maincpu", m65c02_device, nmi_line) does not work
195WRITE_LINE_MEMBER( gts3a_state::nmi_w )
196{
197   m_maincpu->set_input_line(INPUT_LINE_NMI, (state) ? CLEAR_LINE : HOLD_LINE);
198}
199
200WRITE8_MEMBER( gts3a_state::segbank_w )
201{ // this is all wrong
202   UINT32 seg1,seg2;
203   m_segment[offset] = data;
204   seg1 = m_segment[offset&2] | (m_segment[offset|1] << 8);
205   seg2 = BITSWAP32(seg1,16,16,16,16,16,16,16,16,16,16,16,16,16,16,15,14,9,7,13,11,10,6,8,12,5,4,3,3,2,1,0,0);
206   output_set_digit_value(m_digit+(BIT(offset, 1) ? 0 : 20), seg2);
207}
208
209WRITE8_MEMBER( gts3a_state::u4b_w )
210{
211   m_u4b = data & 0xe7;
212   bool clk_bit = BIT(data, 6);
213   if ((!m_dispclk) && clk_bit) // 0->1 is valid
214   {
215      if BIT(data, 5)
216         m_digit = 0;
217      else
218         m_digit++;
219   }
220   m_dispclk = clk_bit;
221
222   clk_bit = BIT(data, 1);
223   if ((!m_lampclk) && clk_bit) // 0->1 is valid
224   {
225      if BIT(data, 0)
226         m_row = 0;
227      else
228         m_row++;
229   }
230   m_lampclk = clk_bit;
231
232
233//   printf("B=%s=%X ",machine().describe_context(),data&0xe0);
234}
235
236READ8_MEMBER( gts3a_state::u4a_r )
237{
238   if (m_row < 12)
239      return m_switches[m_row]->read();
240   else
241      return 0xff;
242}
243
244READ8_MEMBER( gts3a_state::u4b_r )
245{
246   return m_u4b | (ioport("TTS")->read() & 0x18);
247}
248
36249void gts3a_state::machine_reset()
37250{
251   m_digit = 0;
252   m_dispclk = 0;
38253}
39254
40DRIVER_INIT_MEMBER(gts3a_state,gts3a)
255DRIVER_INIT_MEMBER( gts3a_state, gts3a )
41256{
42257}
43258
44259static MACHINE_CONFIG_START( gts3a, gts3a_state )
45260   /* basic machine hardware */
46   MCFG_CPU_ADD("maincpu", M65C02, 2000000)
261   MCFG_CPU_ADD("maincpu", M65C02, XTAL_4MHz / 2)
47262   MCFG_CPU_PROGRAM_MAP(gts3a_map)
263   MCFG_NVRAM_ADD_0FILL("nvram")
264
265   /* Video */
266   // to be done
267
268   /* Sound */
269   MCFG_FRAGMENT_ADD( genpin_audio )
270
271   MCFG_DEVICE_ADD("u4", VIA6522, 0)
272   MCFG_VIA6522_IRQ_HANDLER(DEVWRITELINE("maincpu", m65c02_device, irq_line))
273   MCFG_VIA6522_READPA_HANDLER(READ8(gts3a_state, u4a_r))
274   MCFG_VIA6522_READPB_HANDLER(READ8(gts3a_state, u4b_r))
275   MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(gts3a_state, u4b_w))
276   //MCFG_VIA6522_CA2_HANDLER(WRITELINE(gts3a_state, u4ca2_w))
277   MCFG_VIA6522_CB2_HANDLER(WRITELINE(gts3a_state, nmi_w))
278
279   MCFG_DEVICE_ADD("u5", VIA6522, 0)
280   MCFG_VIA6522_IRQ_HANDLER(DEVWRITELINE("maincpu", m65c02_device, irq_line))
281   //MCFG_VIA6522_READPA_HANDLER(READ8(gts3a_state, u5a_r))
282   //MCFG_VIA6522_READPB_HANDLER(READ8(gts3a_state, u5b_r))
283   //MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(gts3a_state, u5b_w))
284   //MCFG_VIA6522_CA2_HANDLER(WRITELINE(gts3a_state, u5ca2_w))
285   //MCFG_VIA6522_CB1_HANDLER(WRITELINE(gts3a_state, u5cb1_w))
286   //MCFG_VIA6522_CB2_HANDLER(WRITELINE(gts3a_state, u5cb2_w))
48287MACHINE_CONFIG_END
49288
50289/*-------------------------------------------------------------------
r32829r32830
72311ROM_END
73312
74313/*-------------------------------------------------------------------
75/ Brooks & Dunn (#749)
314/ Brooks & Dunn (#749T1)
76315/-------------------------------------------------------------------*/
77316ROM_START(brooks)
78317   ROM_REGION(0x10000, "maincpu", 0)

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