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r32829 Monday 20th October, 2014 at 00:01:50 UTC by Robbbert
gts3.c : Added switches. After setting up, the games are playable.
[src/mame/drivers]gts3.c

trunk/src/mame/drivers/gts3.c
r32828r32829
33  PINBALL
44  Gottlieb System 3
55
6Setting up:
7- Press F2
8- Press 9
9- Press 1 (to load factory defaults)
10- Press 1 (to select English)
11- Press F2 until the credit settings appear (settings #9,10,11)
12- On each of the 3 coin slots, press 0 to set to 1 credit.
13- Press F3
14- Now you can play
15
616Status:
717- Display works
818- Attract mode works
19- Can setup
20- Can play a game
921
22ToDo:
23- Outputs
24- Sound
25- Mechanical sounds
26- Display flickers a bit
27
1028*****************************************************************************************************/
1129
1230#include "machine/genpin.h"
r32828r32829
2240      , m_maincpu(*this, "maincpu")
2341      , m_u4(*this, "u4")
2442      , m_u5(*this, "u5")
43      , m_switches(*this, "X")
2544   { }
2645
2746   DECLARE_DRIVER_INIT(gts3);
2847   DECLARE_WRITE8_MEMBER(segbank_w);
48   DECLARE_READ8_MEMBER(u4a_r);
49   DECLARE_READ8_MEMBER(u4b_r);
2950   DECLARE_WRITE8_MEMBER(u4b_w);
3051   DECLARE_WRITE_LINE_MEMBER(nmi_w);
52   DECLARE_INPUT_CHANGED_MEMBER(test_inp);
3153private:
3254   bool m_dispclk;
33   UINT32 m_digit;
55   bool m_lampclk;
56   UINT8 m_digit;
57   UINT8 m_row; // for lamps and switches
3458   UINT8 m_segment[4];
59   UINT8 m_u4b;
3560   virtual void machine_reset();
3661   required_device<m65c02_device> m_maincpu;
3762   required_device<via6522_device> m_u4;
3863   required_device<via6522_device> m_u5;
64   required_ioport_array<12> m_switches;
3965};
4066
4167
r32828r32829
4874ADDRESS_MAP_END
4975
5076static INPUT_PORTS_START( gts3 )
77   PORT_START("TTS")
78   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE) PORT_NAME("Test") PORT_CHANGED_MEMBER(DEVICE_SELF, gts3_state, test_inp, 1)
79   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Slam Tilt") PORT_CODE(KEYCODE_7_PAD)
80   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_TILT)
81
82   PORT_START("X.0")
83   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_COIN1)
84   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_COIN3)
85   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_COIN2)
86   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_START)
87   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_SERVICE1) PORT_NAME("Left Advance")
88   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_SERVICE2) PORT_NAME("Right Advance")
89   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_MINUS)
90   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_EQUALS)
91
92   PORT_START("X.1")
93   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_A)
94   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_S)
95   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_D)
96   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_F)
97   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_G)
98   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_H)
99   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_J)
100   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_K)
101
102   PORT_START("X.2")
103   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_Q)
104   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_W)
105   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_E)
106   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_R)
107   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_Y)
108   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_U)
109   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_I)
110   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_O)
111
112   PORT_START("X.3")
113   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_Z)
114   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_X)
115   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_C)
116   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_V)
117   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_B)
118   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_N)
119   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_M)
120   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_COMMA)
121
122   PORT_START("X.4")
123   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_L)
124   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_BACKSPACE)
125   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_OPENBRACE)
126   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_CLOSEBRACE)
127   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_BACKSLASH)
128   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_COLON)
129   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_QUOTE)
130   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_ENTER)
131
132   PORT_START("X.5")
133   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_STOP)
134   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_SLASH)
135   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_SPACE)
136   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_CAPSLOCK)
137   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_UP)
138   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_DOWN)
139   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_LEFT)
140   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER) PORT_CODE(KEYCODE_RIGHT)
141
142   PORT_START("X.6")
143   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER)
144   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER)
145   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER)
146   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER)
147   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER)
148   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER)
149   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER)
150   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER)
151
152   PORT_START("X.7")
153   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER)
154   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER)
155   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER)
156   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER)
157   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER)
158   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER)
159   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER)
160   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER)
161
162   PORT_START("X.8")
163   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER)
164   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER)
165   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER)
166   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER)
167   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER)
168   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER)
169   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER)
170   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER)
171
172   PORT_START("X.9")
173   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER)
174   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER)
175   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER)
176   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER)
177   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER)
178   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER)
179   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER)
180   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER)
181
182   PORT_START("X.10")
183   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER)
184   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER)
185   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER)
186   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER)
187   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER)
188   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER)
189   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER)
190   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER)
191
192   PORT_START("X.11")
193   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER)
194   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER)
195   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER)
196   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER)
197   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER)
198   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER)
199   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_OTHER)
200   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_OTHER)
51201INPUT_PORTS_END
52202
53// This trampoline needed - DEVWRITELINE("maincpu", m65c02_device, nmi_line) does not work
203INPUT_CHANGED_MEMBER( gts3_state::test_inp )
204{
205   m_u4->write_ca1(newval);
206}
207
208// This trampoline needed; DEVWRITELINE("maincpu", m65c02_device, nmi_line) does not work
54209WRITE_LINE_MEMBER( gts3_state::nmi_w )
55210{
56211   m_maincpu->set_input_line(INPUT_LINE_NMI, (state) ? CLEAR_LINE : HOLD_LINE);
r32828r32829
58213
59214WRITE8_MEMBER( gts3_state::segbank_w )
60215{
216   UINT32 seg1,seg2;
61217   m_segment[offset] = data;
62   UINT8 i;
63   UINT32 seg1,seg2;
64   offset &= 2;
65   for (i = 0;i < 20; i++)
66   {
67      if BIT(m_digit, i)
68      {
69         seg1 = m_segment[offset] | (m_segment[offset+1] << 8);
70         seg2 = BITSWAP32(seg1, 16,16,16,16,16,16,16,16,16,16,16,16,16,16,15,14,9,7,13,11,10,6,8,12,5,4,3,3,2,1,0,0);
71         output_set_digit_value(i+(offset ? 0 : 20), seg2);
72      }
73   }
218   seg1 = m_segment[offset&2] | (m_segment[offset|1] << 8);
219   seg2 = BITSWAP32(seg1,16,16,16,16,16,16,16,16,16,16,16,16,16,16,15,14,9,7,13,11,10,6,8,12,5,4,3,3,2,1,0,0);
220   output_set_digit_value(m_digit+(BIT(offset, 1) ? 0 : 20), seg2);
74221}
75222
76223WRITE8_MEMBER( gts3_state::u4b_w )
77224{
78   bool dispclk = BIT(data, 6);
79   if ((!m_dispclk) && dispclk) // 0->1 is valid
225   m_u4b = data & 0xe7;
226   bool clk_bit = BIT(data, 6);
227   if ((!m_dispclk) && clk_bit) // 0->1 is valid
80228   {
81      m_digit = (m_digit << 1) | BIT(data, 5);
229      if BIT(data, 5)
230         m_digit = 0;
231      else
232         m_digit++;
82233   }
83   m_dispclk = dispclk;
234   m_dispclk = clk_bit;
84235
236   clk_bit = BIT(data, 1);
237   if ((!m_lampclk) && clk_bit) // 0->1 is valid
238   {
239      if BIT(data, 0)
240         m_row = 0;
241      else
242         m_row++;
243   }
244   m_lampclk = clk_bit;
85245
246
86247//   printf("B=%s=%X ",machine().describe_context(),data&0xe0);
87248}
88249
250READ8_MEMBER( gts3_state::u4a_r )
251{
252   if (m_row < 12)
253      return m_switches[m_row]->read();
254   else
255      return 0xff;
256}
257
258READ8_MEMBER( gts3_state::u4b_r )
259{
260   return m_u4b | (ioport("TTS")->read() & 0x18);
261}
262
89263void gts3_state::machine_reset()
90264{
91265   m_digit = 0;
r32828r32829
100274   /* basic machine hardware */
101275   MCFG_CPU_ADD("maincpu", M65C02, XTAL_4MHz / 2)
102276   MCFG_CPU_PROGRAM_MAP(gts3_map)
277   MCFG_NVRAM_ADD_0FILL("nvram")
103278
104279   /* Video */
105280   MCFG_DEFAULT_LAYOUT(layout_gts3)
r32828r32829
109284
110285   MCFG_DEVICE_ADD("u4", VIA6522, 0)
111286   MCFG_VIA6522_IRQ_HANDLER(DEVWRITELINE("maincpu", m65c02_device, irq_line))
112   //MCFG_VIA6522_READPA_HANDLER(WRITE8(gts3_state, u4a_r))
113   //MCFG_VIA6522_READPB_HANDLER(WRITE8(gts3_state, u4b_r))
287   MCFG_VIA6522_READPA_HANDLER(READ8(gts3_state, u4a_r))
288   MCFG_VIA6522_READPB_HANDLER(READ8(gts3_state, u4b_r))
114289   MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(gts3_state, u4b_w))
115290   //MCFG_VIA6522_CA2_HANDLER(WRITELINE(gts3_state, u4ca2_w))
116291   MCFG_VIA6522_CB2_HANDLER(WRITELINE(gts3_state, nmi_w))
117292
118293   MCFG_DEVICE_ADD("u5", VIA6522, 0)
119294   MCFG_VIA6522_IRQ_HANDLER(DEVWRITELINE("maincpu", m65c02_device, irq_line))
120   //MCFG_VIA6522_READPA_HANDLER(WRITE8(gts3_state, u5a_r))
121   //MCFG_VIA6522_READPB_HANDLER(WRITE8(gts3_state, u5b_r))
295   //MCFG_VIA6522_READPA_HANDLER(READ8(gts3_state, u5a_r))
296   //MCFG_VIA6522_READPB_HANDLER(READ8(gts3_state, u5b_r))
122297   //MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(gts3_state, u5b_w))
123298   //MCFG_VIA6522_CA2_HANDLER(WRITELINE(gts3_state, u5ca2_w))
124299   //MCFG_VIA6522_CB1_HANDLER(WRITELINE(gts3_state, u5cb1_w))

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