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r32809 Saturday 18th October, 2014 at 20:44:47 UTC by Tafoid
calchase.c:  [Peter Ferrie]
* Implemented missing DIP switch for Eggs Playing Chicken, promote to working.  Press "S" to skip the CMOS error, "S" or wait to skip the emm386.exe error (not an emulation issue), use "Coin 2" to
coin-up and start the game, and "1 Player Start" to brake.

calchase.c, gamecstl.c, midqslvr.c, queen.c, savquest.c, taitowlf.c,
voyager.c, xtom3d.c:  [Peter Ferrie]
* Intel component is not MXTC, it's MTXC.
[src/mame/drivers]calchase.c gamecstl.c midqslvr.c queen.c savquest.c taitowlf.c voyager.c xtom3d.c

trunk/src/mame/drivers/savquest.c
r32808r32809
8787   UINT8 m_port379;
8888   int m_hasp_passmode;
8989
90   UINT8 m_mxtc_config_reg[256];
90   UINT8 m_mtxc_config_reg[256];
9191   UINT8 m_piix4_config_reg[8][256];
9292
9393   DECLARE_WRITE32_MEMBER( bios_f0000_ram_w );
r32808r32809
115115   void intel82439tx_init();
116116};
117117
118// Intel 82439TX System Controller (MXTC)
118// Intel 82439TX System Controller (MTXC)
119119
120static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg)
120static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg)
121121{
122122   savquest_state *state = busdevice->machine().driver_data<savquest_state>();
123//  osd_printf_debug("MXTC: read %d, %02X\n", function, reg);
123//  osd_printf_debug("MTXC: read %d, %02X\n", function, reg);
124124
125125   if((reg & 0xfe) == 0)
126126      return (reg & 1) ? 0x80 : 0x86; // Vendor ID, Intel
127127
128128   if((reg & 0xfe) == 2)
129      return (reg & 1) ? 0x70 : 0x00; // Device ID, MXTC
129      return (reg & 1) ? 0x70 : 0x00; // Device ID, MTXC
130130
131   return state->m_mxtc_config_reg[reg];
131   return state->m_mtxc_config_reg[reg];
132132}
133133
134static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
134static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
135135{
136136   savquest_state *state = busdevice->machine().driver_data<savquest_state>();
137137//  osd_printf_debug("%s:MXTC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data);
r32808r32809
198198   }
199199   #endif
200200
201   state->m_mxtc_config_reg[reg] = data;
201   state->m_mtxc_config_reg[reg] = data;
202202}
203203
204204void savquest_state::intel82439tx_init()
205205{
206   m_mxtc_config_reg[0x60] = 0x02;
207   m_mxtc_config_reg[0x61] = 0x02;
208   m_mxtc_config_reg[0x62] = 0x02;
209   m_mxtc_config_reg[0x63] = 0x02;
210   m_mxtc_config_reg[0x64] = 0x02;
211   m_mxtc_config_reg[0x65] = 0x02;
206   m_mtxc_config_reg[0x60] = 0x02;
207   m_mtxc_config_reg[0x61] = 0x02;
208   m_mtxc_config_reg[0x62] = 0x02;
209   m_mtxc_config_reg[0x63] = 0x02;
210   m_mtxc_config_reg[0x64] = 0x02;
211   m_mtxc_config_reg[0x65] = 0x02;
212212   m_smram = auto_alloc_array(machine(), UINT8, 0x20000);
213213}
214214
r32808r32809
217217   UINT32 r = 0;
218218   if (ACCESSING_BITS_24_31)
219219   {
220      r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24;
220      r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24;
221221   }
222222   if (ACCESSING_BITS_16_23)
223223   {
224      r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16;
224      r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16;
225225   }
226226   if (ACCESSING_BITS_8_15)
227227   {
228      r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8;
228      r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8;
229229   }
230230   if (ACCESSING_BITS_0_7)
231231   {
232      r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0;
232      r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0;
233233   }
234234   return r;
235235}
r32808r32809
238238{
239239   if (ACCESSING_BITS_24_31)
240240   {
241      mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
241      mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
242242   }
243243   if (ACCESSING_BITS_16_23)
244244   {
245      mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
245      mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
246246   }
247247   if (ACCESSING_BITS_8_15)
248248   {
249      mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
249      mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
250250   }
251251   if (ACCESSING_BITS_0_7)
252252   {
253      mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
253      mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
254254   }
255255}
256256
r32808r32809
327327
328328WRITE32_MEMBER(savquest_state::bios_f0000_ram_w)
329329{
330   //if (m_mxtc_config_reg[0x59] & 0x20)       // write to RAM if this region is write-enabled
330   //if (m_mtxc_config_reg[0x59] & 0x20)       // write to RAM if this region is write-enabled
331331   #if 1
332   if (m_mxtc_config_reg[0x59] & 0x20)     // write to RAM if this region is write-enabled
332   if (m_mtxc_config_reg[0x59] & 0x20)     // write to RAM if this region is write-enabled
333333   {
334334      COMBINE_DATA(m_bios_f0000_ram + offset);
335335   }
r32808r32809
338338
339339WRITE32_MEMBER(savquest_state::bios_e0000_ram_w)
340340{
341   //if (m_mxtc_config_reg[0x5e] & 2)       // write to RAM if this region is write-enabled
341   //if (m_mtxc_config_reg[0x5e] & 2)       // write to RAM if this region is write-enabled
342342   #if 1
343   if (m_mxtc_config_reg[0x5e] & 2)        // write to RAM if this region is write-enabled
343   if (m_mtxc_config_reg[0x5e] & 2)        // write to RAM if this region is write-enabled
344344   {
345345      COMBINE_DATA(m_bios_e0000_ram + offset);
346346   }
r32808r32809
349349
350350WRITE32_MEMBER(savquest_state::bios_e4000_ram_w)
351351{
352   //if (m_mxtc_config_reg[0x5e] & 0x20)       // write to RAM if this region is write-enabled
352   //if (m_mtxc_config_reg[0x5e] & 0x20)       // write to RAM if this region is write-enabled
353353   #if 1
354   if (m_mxtc_config_reg[0x5e] & 0x20)     // write to RAM if this region is write-enabled
354   if (m_mtxc_config_reg[0x5e] & 0x20)     // write to RAM if this region is write-enabled
355355   {
356356      COMBINE_DATA(m_bios_e4000_ram + offset);
357357   }
r32808r32809
360360
361361WRITE32_MEMBER(savquest_state::bios_e8000_ram_w)
362362{
363   //if (m_mxtc_config_reg[0x5f] & 2)       // write to RAM if this region is write-enabled
363   //if (m_mtxc_config_reg[0x5f] & 2)       // write to RAM if this region is write-enabled
364364   #if 1
365   if (m_mxtc_config_reg[0x5f] & 2)        // write to RAM if this region is write-enabled
365   if (m_mtxc_config_reg[0x5f] & 2)        // write to RAM if this region is write-enabled
366366   {
367367      COMBINE_DATA(m_bios_e8000_ram + offset);
368368   }
r32808r32809
371371
372372WRITE32_MEMBER(savquest_state::bios_ec000_ram_w)
373373{
374   //if (m_mxtc_config_reg[0x5f] & 0x20)       // write to RAM if this region is write-enabled
374   //if (m_mtxc_config_reg[0x5f] & 0x20)       // write to RAM if this region is write-enabled
375375   #if 1
376   if (m_mxtc_config_reg[0x5f] & 0x20)     // write to RAM if this region is write-enabled
376   if (m_mtxc_config_reg[0x5f] & 0x20)     // write to RAM if this region is write-enabled
377377   {
378378      COMBINE_DATA(m_bios_ec000_ram + offset);
379379   }
r32808r32809
579579READ8_MEMBER(savquest_state::smram_r)
580580{
581581   /* TODO: way more complex than this */
582   if(m_mxtc_config_reg[0x72] & 0x40)
582   if(m_mtxc_config_reg[0x72] & 0x40)
583583      return m_smram[offset];
584584   else
585585      return m_vga->mem_r(space,offset,0xff);
r32808r32809
588588WRITE8_MEMBER(savquest_state::smram_w)
589589{
590590   /* TODO: way more complex than this */
591   if(m_mxtc_config_reg[0x72] & 0x40)
591   if(m_mtxc_config_reg[0x72] & 0x40)
592592      m_smram[offset] = data;
593593   else
594594      m_vga->mem_w(space,offset,data,0xff);
trunk/src/mame/drivers/midqslvr.c
r32808r32809
4545   UINT32 *m_bios_ext4_ram;
4646   UINT32 *m_isa_ram1;
4747   UINT32 *m_isa_ram2;
48   UINT8 m_mxtc_config_reg[256];
48   UINT8 m_mtxc_config_reg[256];
4949   UINT8 m_piix4_config_reg[4][256];
5050
5151   DECLARE_WRITE32_MEMBER( isa_ram1_w );
r32808r32809
6363};
6464
6565
66// Intel 82439TX System Controller (MXTC)
66// Intel 82439TX System Controller (MTXC)
6767
68static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg)
68static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg)
6969{
7070   midqslvr_state *state = busdevice->machine().driver_data<midqslvr_state>();
71//  osd_printf_debug("MXTC: read %d, %02X\n", function, reg);
71//  osd_printf_debug("MTXC: read %d, %02X\n", function, reg);
7272
7373   if((reg & 0xfc) == 0 && function == 0) // return vendor ID
7474      return (0x71008086 >> (reg & 3)*8) & 0xff;
7575
76   return state->m_mxtc_config_reg[reg];
76   return state->m_mtxc_config_reg[reg];
7777}
7878
79static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
79static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
8080{
8181   midqslvr_state *state = busdevice->machine().driver_data<midqslvr_state>();
82   printf("MXTC: write %d, %02X, %02X\n",  function, reg, data);
82   printf("MTXC: write %d, %02X, %02X\n",  function, reg, data);
8383
8484   /*
8585   memory banking with North Bridge:
r32808r32809
155155      }
156156   }
157157
158   state->m_mxtc_config_reg[reg] = data;
158   state->m_mtxc_config_reg[reg] = data;
159159}
160160
161161void midqslvr_state::intel82439tx_init()
162162{
163   m_mxtc_config_reg[0x60] = 0x02;
164   m_mxtc_config_reg[0x61] = 0x02;
165   m_mxtc_config_reg[0x62] = 0x02;
166   m_mxtc_config_reg[0x63] = 0x02;
167   m_mxtc_config_reg[0x64] = 0x02;
168   m_mxtc_config_reg[0x65] = 0x02;
163   m_mtxc_config_reg[0x60] = 0x02;
164   m_mtxc_config_reg[0x61] = 0x02;
165   m_mtxc_config_reg[0x62] = 0x02;
166   m_mtxc_config_reg[0x63] = 0x02;
167   m_mtxc_config_reg[0x64] = 0x02;
168   m_mtxc_config_reg[0x65] = 0x02;
169169}
170170
171171static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask)
r32808r32809
173173   UINT32 r = 0;
174174   if (ACCESSING_BITS_24_31)
175175   {
176      r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24;
176      r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24;
177177   }
178178   if (ACCESSING_BITS_16_23)
179179   {
180      r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16;
180      r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16;
181181   }
182182   if (ACCESSING_BITS_8_15)
183183   {
184      r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8;
184      r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8;
185185   }
186186   if (ACCESSING_BITS_0_7)
187187   {
188      r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0;
188      r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0;
189189   }
190190   return r;
191191}
r32808r32809
194194{
195195   if (ACCESSING_BITS_24_31)
196196   {
197      mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
197      mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
198198   }
199199   if (ACCESSING_BITS_16_23)
200200   {
201      mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
201      mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
202202   }
203203   if (ACCESSING_BITS_8_15)
204204   {
205      mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
205      mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
206206   }
207207   if (ACCESSING_BITS_0_7)
208208   {
209      mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
209      mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
210210   }
211211}
212212
r32808r32809
296296
297297WRITE32_MEMBER(midqslvr_state::isa_ram1_w)
298298{
299   if (m_mxtc_config_reg[0x5a] & 0x2)      // write to RAM if this region is write-enabled
299   if (m_mtxc_config_reg[0x5a] & 0x2)      // write to RAM if this region is write-enabled
300300   {
301301      COMBINE_DATA(m_isa_ram1 + offset);
302302   }
r32808r32809
304304
305305WRITE32_MEMBER(midqslvr_state::isa_ram2_w)
306306{
307   if (m_mxtc_config_reg[0x5a] & 0x2)      // write to RAM if this region is write-enabled
307   if (m_mtxc_config_reg[0x5a] & 0x2)      // write to RAM if this region is write-enabled
308308   {
309309      COMBINE_DATA(m_isa_ram2 + offset);
310310   }
r32808r32809
312312
313313WRITE32_MEMBER(midqslvr_state::bios_ext1_ram_w)
314314{
315   if (m_mxtc_config_reg[0x5e] & 0x2)      // write to RAM if this region is write-enabled
315   if (m_mtxc_config_reg[0x5e] & 0x2)      // write to RAM if this region is write-enabled
316316   {
317317      COMBINE_DATA(m_bios_ext1_ram + offset);
318318   }
r32808r32809
321321
322322WRITE32_MEMBER(midqslvr_state::bios_ext2_ram_w)
323323{
324   if (m_mxtc_config_reg[0x5e] & 0x20)     // write to RAM if this region is write-enabled
324   if (m_mtxc_config_reg[0x5e] & 0x20)     // write to RAM if this region is write-enabled
325325   {
326326      COMBINE_DATA(m_bios_ext2_ram + offset);
327327   }
r32808r32809
330330
331331WRITE32_MEMBER(midqslvr_state::bios_ext3_ram_w)
332332{
333   if (m_mxtc_config_reg[0x5f] & 0x2)      // write to RAM if this region is write-enabled
333   if (m_mtxc_config_reg[0x5f] & 0x2)      // write to RAM if this region is write-enabled
334334   {
335335      COMBINE_DATA(m_bios_ext3_ram + offset);
336336   }
r32808r32809
339339
340340WRITE32_MEMBER(midqslvr_state::bios_ext4_ram_w)
341341{
342   if (m_mxtc_config_reg[0x5f] & 0x20)     // write to RAM if this region is write-enabled
342   if (m_mtxc_config_reg[0x5f] & 0x20)     // write to RAM if this region is write-enabled
343343   {
344344      COMBINE_DATA(m_bios_ext4_ram + offset);
345345   }
r32808r32809
348348
349349WRITE32_MEMBER(midqslvr_state::bios_ram_w)
350350{
351   if (m_mxtc_config_reg[0x59] & 0x20)     // write to RAM if this region is write-enabled
351   if (m_mtxc_config_reg[0x59] & 0x20)     // write to RAM if this region is write-enabled
352352   {
353353      COMBINE_DATA(m_bios_ram + offset);
354354   }
trunk/src/mame/drivers/queen.c
r32808r32809
4343
4444   UINT32 *m_bios_ram;
4545   UINT32 *m_bios_ext_ram;
46   UINT8 m_mxtc_config_reg[256];
46   UINT8 m_mtxc_config_reg[256];
4747   UINT8 m_piix4_config_reg[4][256];
4848
4949   DECLARE_WRITE32_MEMBER( bios_ext_ram_w );
r32808r32809
5555};
5656
5757
58// Intel 82439TX System Controller (MXTC)
58// Intel 82439TX System Controller (MTXC)
5959
60static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg)
60static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg)
6161{
6262   queen_state *state = busdevice->machine().driver_data<queen_state>();
63//  osd_printf_debug("MXTC: read %d, %02X\n", function, reg);
63//  osd_printf_debug("MTXC: read %d, %02X\n", function, reg);
6464
65   return state->m_mxtc_config_reg[reg];
65   return state->m_mtxc_config_reg[reg];
6666}
6767
68static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
68static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
6969{
7070   queen_state *state = busdevice->machine().driver_data<queen_state>();
71   printf("MXTC: write %d, %02X, %02X\n",  function, reg, data);
71   printf("MTXC: write %d, %02X, %02X\n",  function, reg, data);
7272
7373   /*
7474   memory banking with North Bridge:
r32808r32809
9292         state->membank("bios_ext")->set_base(state->memregion("bios")->base() + 0x20000);
9393   }
9494
95   state->m_mxtc_config_reg[reg] = data;
95   state->m_mtxc_config_reg[reg] = data;
9696}
9797
9898void queen_state::intel82439tx_init()
9999{
100   m_mxtc_config_reg[0x60] = 0x02;
101   m_mxtc_config_reg[0x61] = 0x02;
102   m_mxtc_config_reg[0x62] = 0x02;
103   m_mxtc_config_reg[0x63] = 0x02;
104   m_mxtc_config_reg[0x64] = 0x02;
105   m_mxtc_config_reg[0x65] = 0x02;
100   m_mtxc_config_reg[0x60] = 0x02;
101   m_mtxc_config_reg[0x61] = 0x02;
102   m_mtxc_config_reg[0x62] = 0x02;
103   m_mtxc_config_reg[0x63] = 0x02;
104   m_mtxc_config_reg[0x64] = 0x02;
105   m_mtxc_config_reg[0x65] = 0x02;
106106}
107107
108108static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask)
r32808r32809
110110   UINT32 r = 0;
111111   if (ACCESSING_BITS_24_31)
112112   {
113      r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24;
113      r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24;
114114   }
115115   if (ACCESSING_BITS_16_23)
116116   {
117      r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16;
117      r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16;
118118   }
119119   if (ACCESSING_BITS_8_15)
120120   {
121      r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8;
121      r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8;
122122   }
123123   if (ACCESSING_BITS_0_7)
124124   {
125      r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0;
125      r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0;
126126   }
127127   return r;
128128}
r32808r32809
131131{
132132   if (ACCESSING_BITS_24_31)
133133   {
134      mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
134      mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
135135   }
136136   if (ACCESSING_BITS_16_23)
137137   {
138      mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
138      mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
139139   }
140140   if (ACCESSING_BITS_8_15)
141141   {
142      mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
142      mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
143143   }
144144   if (ACCESSING_BITS_0_7)
145145   {
146      mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
146      mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
147147   }
148148}
149149
r32808r32809
209209
210210WRITE32_MEMBER(queen_state::bios_ext_ram_w)
211211{
212   if (m_mxtc_config_reg[0x63] & 0x40)     // write to RAM if this region is write-enabled
212   if (m_mtxc_config_reg[0x63] & 0x40)     // write to RAM if this region is write-enabled
213213   {
214214      COMBINE_DATA(m_bios_ext_ram + offset);
215215   }
r32808r32809
218218
219219WRITE32_MEMBER(queen_state::bios_ram_w)
220220{
221   if (m_mxtc_config_reg[0x63] & 0x10)     // write to RAM if this region is write-enabled
221   if (m_mtxc_config_reg[0x63] & 0x10)     // write to RAM if this region is write-enabled
222222   {
223223      COMBINE_DATA(m_bios_ram + offset);
224224   }
trunk/src/mame/drivers/calchase.c
r32808r32809
142142
143143   UINT32 *m_bios_ram;
144144   UINT32 *m_bios_ext_ram;
145   UINT8 m_mxtc_config_reg[256];
145   UINT8 m_mtxc_config_reg[256];
146146   UINT8 m_piix4_config_reg[4][256];
147147
148148   UINT32 m_idle_skip_ram;
r32808r32809
166166   required_device<dac_device> m_dac_r;
167167};
168168
169// Intel 82439TX System Controller (MXTC)
169// Intel 82439TX System Controller (MTXC)
170170// TODO: change with a VIA82C585VPX (North Bridge - APOLLO Chipset)
171171
172static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg)
172static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg)
173173{
174174   calchase_state *state = busdevice->machine().driver_data<calchase_state>();
175//  osd_printf_debug("MXTC: read %d, %02X\n", function, reg);
175//  osd_printf_debug("MTXC: read %d, %02X\n", function, reg);
176176
177   return state->m_mxtc_config_reg[reg];
177   return state->m_mtxc_config_reg[reg];
178178}
179179
180static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
180static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
181181{
182182   calchase_state *state = busdevice->machine().driver_data<calchase_state>();
183//  osd_printf_debug("%s:MXTC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data);
183//  osd_printf_debug("%s:MTXC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data);
184184
185185   /*
186186   memory banking with North Bridge:
r32808r32809
204204         state->membank("bios_ext")->set_base(state->memregion("bios")->base() + 0);
205205   }
206206
207   state->m_mxtc_config_reg[reg] = data;
207   state->m_mtxc_config_reg[reg] = data;
208208}
209209
210210void calchase_state::intel82439tx_init()
211211{
212   m_mxtc_config_reg[0x60] = 0x02;
213   m_mxtc_config_reg[0x61] = 0x02;
214   m_mxtc_config_reg[0x62] = 0x02;
215   m_mxtc_config_reg[0x63] = 0x02;
216   m_mxtc_config_reg[0x64] = 0x02;
217   m_mxtc_config_reg[0x65] = 0x02;
212   m_mtxc_config_reg[0x60] = 0x02;
213   m_mtxc_config_reg[0x61] = 0x02;
214   m_mtxc_config_reg[0x62] = 0x02;
215   m_mtxc_config_reg[0x63] = 0x02;
216   m_mtxc_config_reg[0x64] = 0x02;
217   m_mtxc_config_reg[0x65] = 0x02;
218218}
219219
220220static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask)
r32808r32809
226226
227227   if (ACCESSING_BITS_24_31)
228228   {
229      r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24;
229      r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24;
230230   }
231231   if (ACCESSING_BITS_16_23)
232232   {
233      r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16;
233      r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16;
234234   }
235235   if (ACCESSING_BITS_8_15)
236236   {
237      r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8;
237      r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8;
238238   }
239239   if (ACCESSING_BITS_0_7)
240240   {
241      r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0;
241      r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0;
242242   }
243243   return r;
244244}
r32808r32809
247247{
248248   if (ACCESSING_BITS_24_31)
249249   {
250      mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
250      mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
251251   }
252252   if (ACCESSING_BITS_16_23)
253253   {
254      mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
254      mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
255255   }
256256   if (ACCESSING_BITS_8_15)
257257   {
258      mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
258      mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
259259   }
260260   if (ACCESSING_BITS_0_7)
261261   {
262      mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
262      mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
263263   }
264264}
265265
r32808r32809
328328
329329WRITE32_MEMBER(calchase_state::bios_ram_w)
330330{
331   if (m_mxtc_config_reg[0x63] & 0x10)       // write to RAM if this region is write-enabled
331   if (m_mtxc_config_reg[0x63] & 0x10)       // write to RAM if this region is write-enabled
332332   {
333333      COMBINE_DATA(m_bios_ram + offset);
334334   }
r32808r32809
336336
337337WRITE32_MEMBER(calchase_state::bios_ext_ram_w)
338338{
339   if (m_mxtc_config_reg[0x63] & 0x40)       // write to RAM if this region is write-enabled
339   if (m_mtxc_config_reg[0x63] & 0x40)       // write to RAM if this region is write-enabled
340340   {
341341      COMBINE_DATA(m_bios_ext_ram + offset);
342342   }
r32808r32809
571571   PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) )
572572   PORT_DIPSETTING(    0x1000, DEF_STR( Off ) )
573573   PORT_DIPSETTING(    0x0000, DEF_STR( On ) )
574   PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) )
575   PORT_DIPSETTING(    0x2000, DEF_STR( Off ) )
576   PORT_DIPSETTING(    0x0000, DEF_STR( On ) )
574   PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen") //eggsplc
577575   PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) )
578576   PORT_DIPSETTING(    0x4000, DEF_STR( Off ) )
579577   PORT_DIPSETTING(    0x0000, DEF_STR( On ) )
r32808r32809
774772
775773GAME( 1998, hostinv,   0,    hostinv,  calchase, calchase_state,  hostinv,  ROT0, "The Game Room", "Host Invaders", GAME_NOT_WORKING|GAME_IMPERFECT_GRAPHICS )
776774GAME( 1999, calchase,  0,    calchase, calchase, calchase_state,  calchase, ROT0, "The Game Room", "California Chase", GAME_NOT_WORKING|GAME_IMPERFECT_GRAPHICS )
777GAME( 2002, eggsplc,   0,    calchase, calchase, calchase_state,  hostinv,  ROT0, "The Game Room", "Eggs Playing Chicken", GAME_NOT_WORKING|GAME_IMPERFECT_GRAPHICS )
775GAME( 2002, eggsplc,   0,    calchase, calchase, calchase_state,  hostinv,  ROT0, "The Game Room", "Eggs Playing Chicken", 0 )
trunk/src/mame/drivers/xtom3d.c
r32808r32809
6161   UINT32 *m_bios_ext4_ram;
6262   UINT32 *m_isa_ram1;
6363   UINT32 *m_isa_ram2;
64   UINT8 m_mxtc_config_reg[256];
64   UINT8 m_mtxc_config_reg[256];
6565   UINT8 m_piix4_config_reg[4][256];
6666
6767   DECLARE_WRITE32_MEMBER( isa_ram1_w );
r32808r32809
7878   void intel82439tx_init();
7979};
8080
81// Intel 82439TX System Controller (MXTC)
81// Intel 82439TX System Controller (MTXC)
8282
83static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg)
83static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg)
8484{
8585   xtom3d_state *state = busdevice->machine().driver_data<xtom3d_state>();
86//  osd_printf_debug("MXTC: read %d, %02X\n", function, reg);
86//  osd_printf_debug("MTXC: read %d, %02X\n", function, reg);
8787
88   return state->m_mxtc_config_reg[reg];
88   return state->m_mtxc_config_reg[reg];
8989}
9090
91static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
91static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
9292{
9393   xtom3d_state *state = busdevice->machine().driver_data<xtom3d_state>();
94   printf("MXTC: write %d, %02X, %02X\n",  function, reg, data);
94   printf("MTXC: write %d, %02X, %02X\n",  function, reg, data);
9595
9696   /*
9797   memory banking with North Bridge:
r32808r32809
167167      }
168168   }
169169
170   state->m_mxtc_config_reg[reg] = data;
170   state->m_mtxc_config_reg[reg] = data;
171171}
172172
173173void xtom3d_state::intel82439tx_init()
174174{
175   m_mxtc_config_reg[0x60] = 0x02;
176   m_mxtc_config_reg[0x61] = 0x02;
177   m_mxtc_config_reg[0x62] = 0x02;
178   m_mxtc_config_reg[0x63] = 0x02;
179   m_mxtc_config_reg[0x64] = 0x02;
180   m_mxtc_config_reg[0x65] = 0x02;
175   m_mtxc_config_reg[0x60] = 0x02;
176   m_mtxc_config_reg[0x61] = 0x02;
177   m_mtxc_config_reg[0x62] = 0x02;
178   m_mtxc_config_reg[0x63] = 0x02;
179   m_mtxc_config_reg[0x64] = 0x02;
180   m_mtxc_config_reg[0x65] = 0x02;
181181}
182182
183183static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask)
r32808r32809
185185   UINT32 r = 0;
186186   if (ACCESSING_BITS_24_31)
187187   {
188      r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24;
188      r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24;
189189   }
190190   if (ACCESSING_BITS_16_23)
191191   {
192      r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16;
192      r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16;
193193   }
194194   if (ACCESSING_BITS_8_15)
195195   {
196      r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8;
196      r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8;
197197   }
198198   if (ACCESSING_BITS_0_7)
199199   {
200      r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0;
200      r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0;
201201   }
202202   return r;
203203}
r32808r32809
206206{
207207   if (ACCESSING_BITS_24_31)
208208   {
209      mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
209      mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
210210   }
211211   if (ACCESSING_BITS_16_23)
212212   {
213      mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
213      mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
214214   }
215215   if (ACCESSING_BITS_8_15)
216216   {
217      mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
217      mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
218218   }
219219   if (ACCESSING_BITS_0_7)
220220   {
221      mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
221      mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
222222   }
223223}
224224
r32808r32809
283283
284284WRITE32_MEMBER(xtom3d_state::isa_ram1_w)
285285{
286   if (m_mxtc_config_reg[0x5a] & 0x2)      // write to RAM if this region is write-enabled
286   if (m_mtxc_config_reg[0x5a] & 0x2)      // write to RAM if this region is write-enabled
287287   {
288288      COMBINE_DATA(m_isa_ram1 + offset);
289289   }
r32808r32809
291291
292292WRITE32_MEMBER(xtom3d_state::isa_ram2_w)
293293{
294   if (m_mxtc_config_reg[0x5a] & 0x2)      // write to RAM if this region is write-enabled
294   if (m_mtxc_config_reg[0x5a] & 0x2)      // write to RAM if this region is write-enabled
295295   {
296296      COMBINE_DATA(m_isa_ram2 + offset);
297297   }
r32808r32809
299299
300300WRITE32_MEMBER(xtom3d_state::bios_ext1_ram_w)
301301{
302   if (m_mxtc_config_reg[0x5e] & 0x2)      // write to RAM if this region is write-enabled
302   if (m_mtxc_config_reg[0x5e] & 0x2)      // write to RAM if this region is write-enabled
303303   {
304304      COMBINE_DATA(m_bios_ext1_ram + offset);
305305   }
r32808r32809
308308
309309WRITE32_MEMBER(xtom3d_state::bios_ext2_ram_w)
310310{
311   if (m_mxtc_config_reg[0x5e] & 0x20)     // write to RAM if this region is write-enabled
311   if (m_mtxc_config_reg[0x5e] & 0x20)     // write to RAM if this region is write-enabled
312312   {
313313      COMBINE_DATA(m_bios_ext2_ram + offset);
314314   }
r32808r32809
317317
318318WRITE32_MEMBER(xtom3d_state::bios_ext3_ram_w)
319319{
320   if (m_mxtc_config_reg[0x5f] & 0x2)      // write to RAM if this region is write-enabled
320   if (m_mtxc_config_reg[0x5f] & 0x2)      // write to RAM if this region is write-enabled
321321   {
322322      COMBINE_DATA(m_bios_ext3_ram + offset);
323323   }
r32808r32809
326326
327327WRITE32_MEMBER(xtom3d_state::bios_ext4_ram_w)
328328{
329   if (m_mxtc_config_reg[0x5f] & 0x20)     // write to RAM if this region is write-enabled
329   if (m_mtxc_config_reg[0x5f] & 0x20)     // write to RAM if this region is write-enabled
330330   {
331331      COMBINE_DATA(m_bios_ext4_ram + offset);
332332   }
r32808r32809
335335
336336WRITE32_MEMBER(xtom3d_state::bios_ram_w)
337337{
338   if (m_mxtc_config_reg[0x59] & 0x20)     // write to RAM if this region is write-enabled
338   if (m_mtxc_config_reg[0x59] & 0x20)     // write to RAM if this region is write-enabled
339339   {
340340      COMBINE_DATA(m_bios_ram + offset);
341341   }
trunk/src/mame/drivers/taitowlf.c
r32808r32809
4444      m_palette(*this, "palette") { }
4545
4646   UINT32 *m_bios_ram;
47   UINT8 m_mxtc_config_reg[256];
47   UINT8 m_mtxc_config_reg[256];
4848   UINT8 m_piix4_config_reg[4][256];
4949
5050   required_region_ptr<UINT8> m_bootscreen_rom;
r32808r32809
9292#endif
9393
9494
95// Intel 82439TX System Controller (MXTC)
95// Intel 82439TX System Controller (MTXC)
9696
97static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg)
97static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg)
9898{
9999   taitowlf_state *state = busdevice->machine().driver_data<taitowlf_state>();
100//  osd_printf_debug("MXTC: read %d, %02X\n", function, reg);
100//  osd_printf_debug("MTXC: read %d, %02X\n", function, reg);
101101
102   return state->m_mxtc_config_reg[reg];
102   return state->m_mtxc_config_reg[reg];
103103}
104104
105static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
105static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
106106{
107107   taitowlf_state *state = busdevice->machine().driver_data<taitowlf_state>();
108//  osd_printf_debug("%s:MXTC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data);
108//  osd_printf_debug("%s:MTXC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data);
109109
110110   switch(reg)
111111   {
r32808r32809
123123      }
124124   }
125125
126   state->m_mxtc_config_reg[reg] = data;
126   state->m_mtxc_config_reg[reg] = data;
127127}
128128
129129void taitowlf_state::intel82439tx_init()
130130{
131   m_mxtc_config_reg[0x60] = 0x02;
132   m_mxtc_config_reg[0x61] = 0x02;
133   m_mxtc_config_reg[0x62] = 0x02;
134   m_mxtc_config_reg[0x63] = 0x02;
135   m_mxtc_config_reg[0x64] = 0x02;
136   m_mxtc_config_reg[0x65] = 0x02;
131   m_mtxc_config_reg[0x60] = 0x02;
132   m_mtxc_config_reg[0x61] = 0x02;
133   m_mtxc_config_reg[0x62] = 0x02;
134   m_mtxc_config_reg[0x63] = 0x02;
135   m_mtxc_config_reg[0x64] = 0x02;
136   m_mtxc_config_reg[0x65] = 0x02;
137137}
138138
139139static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask)
r32808r32809
141141   UINT32 r = 0;
142142   if (ACCESSING_BITS_24_31)
143143   {
144      r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24;
144      r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24;
145145   }
146146   if (ACCESSING_BITS_16_23)
147147   {
148      r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16;
148      r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16;
149149   }
150150   if (ACCESSING_BITS_8_15)
151151   {
152      r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8;
152      r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8;
153153   }
154154   if (ACCESSING_BITS_0_7)
155155   {
156      r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0;
156      r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0;
157157   }
158158   return r;
159159}
r32808r32809
162162{
163163   if (ACCESSING_BITS_24_31)
164164   {
165      mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
165      mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
166166   }
167167   if (ACCESSING_BITS_16_23)
168168   {
169      mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
169      mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
170170   }
171171   if (ACCESSING_BITS_8_15)
172172   {
173      mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
173      mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
174174   }
175175   if (ACCESSING_BITS_0_7)
176176   {
177      mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
177      mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
178178   }
179179}
180180
r32808r32809
257257
258258WRITE32_MEMBER(taitowlf_state::bios_ram_w)
259259{
260   if (m_mxtc_config_reg[0x59] & 0x20)     // write to RAM if this region is write-enabled
260   if (m_mtxc_config_reg[0x59] & 0x20)     // write to RAM if this region is write-enabled
261261   {
262262      COMBINE_DATA(m_bios_ram + offset);
263263   }
trunk/src/mame/drivers/gamecstl.c
r32808r32809
8383   required_device<gfxdecode_device> m_gfxdecode;
8484   required_device<palette_device> m_palette;
8585   UINT32 *m_bios_ram;
86   UINT8 m_mxtc_config_reg[256];
86   UINT8 m_mtxc_config_reg[256];
8787   UINT8 m_piix4_config_reg[4][256];
8888
8989   DECLARE_WRITE32_MEMBER(pnp_config_w);
r32808r32809
162162   return 0;
163163}
164164
165// Intel 82439TX System Controller (MXTC)
165// Intel 82439TX System Controller (MTXC)
166166
167static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg)
167static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg)
168168{
169169   gamecstl_state *state = busdevice->machine().driver_data<gamecstl_state>();
170   printf("MXTC: read %d, %02X\n", function, reg);
171   return state->m_mxtc_config_reg[reg];
170   printf("MTXC: read %d, %02X\n", function, reg);
171   return state->m_mtxc_config_reg[reg];
172172}
173173
174static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
174static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
175175{
176176   gamecstl_state *state = busdevice->machine().driver_data<gamecstl_state>();
177   printf("%s:MXTC: write %d, %02X, %02X\n", busdevice->machine().describe_context(), function, reg, data);
177   printf("%s:MTXC: write %d, %02X, %02X\n", busdevice->machine().describe_context(), function, reg, data);
178178
179179   switch(reg)
180180   {
r32808r32809
192192      }
193193   }
194194
195   state->m_mxtc_config_reg[reg] = data;
195   state->m_mtxc_config_reg[reg] = data;
196196}
197197
198198void gamecstl_state::intel82439tx_init()
199199{
200   m_mxtc_config_reg[0x60] = 0x02;
201   m_mxtc_config_reg[0x61] = 0x02;
202   m_mxtc_config_reg[0x62] = 0x02;
203   m_mxtc_config_reg[0x63] = 0x02;
204   m_mxtc_config_reg[0x64] = 0x02;
205   m_mxtc_config_reg[0x65] = 0x02;
200   m_mtxc_config_reg[0x60] = 0x02;
201   m_mtxc_config_reg[0x61] = 0x02;
202   m_mtxc_config_reg[0x62] = 0x02;
203   m_mtxc_config_reg[0x63] = 0x02;
204   m_mtxc_config_reg[0x64] = 0x02;
205   m_mtxc_config_reg[0x65] = 0x02;
206206}
207207
208208static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask)
r32808r32809
210210   UINT32 r = 0;
211211   if (ACCESSING_BITS_24_31)
212212   {
213      r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24;
213      r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24;
214214   }
215215   if (ACCESSING_BITS_16_23)
216216   {
217      r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16;
217      r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16;
218218   }
219219   if (ACCESSING_BITS_8_15)
220220   {
221      r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8;
221      r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8;
222222   }
223223   if (ACCESSING_BITS_0_7)
224224   {
225      r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0;
225      r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0;
226226   }
227227   return r;
228228}
r32808r32809
231231{
232232   if (ACCESSING_BITS_24_31)
233233   {
234      mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
234      mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
235235   }
236236   if (ACCESSING_BITS_16_23)
237237   {
238      mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
238      mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
239239   }
240240   if (ACCESSING_BITS_8_15)
241241   {
242      mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
242      mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
243243   }
244244   if (ACCESSING_BITS_0_7)
245245   {
246      mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
246      mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
247247   }
248248}
249249
r32808r32809
326326
327327WRITE32_MEMBER(gamecstl_state::bios_ram_w)
328328{
329   if (m_mxtc_config_reg[0x59] & 0x20)     // write to RAM if this region is write-enabled
329   if (m_mtxc_config_reg[0x59] & 0x20)     // write to RAM if this region is write-enabled
330330   {
331331      COMBINE_DATA(m_bios_ram + offset);
332332   }
trunk/src/mame/drivers/voyager.c
r32808r32809
3030   }
3131
3232   UINT32 *m_bios_ram;
33   UINT8 m_mxtc_config_reg[256];
33   UINT8 m_mtxc_config_reg[256];
3434   UINT8 m_piix4_config_reg[4][256];
3535
3636   UINT32 m_idle_skip_ram;
r32808r32809
4242};
4343
4444
45// Intel 82439TX System Controller (MXTC)
45// Intel 82439TX System Controller (MTXC)
4646
47static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg)
47static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg)
4848{
4949   voyager_state *state = busdevice->machine().driver_data<voyager_state>();
50//  osd_printf_debug("MXTC: read %d, %02X\n", function, reg);
50//  osd_printf_debug("MTXC: read %d, %02X\n", function, reg);
5151
52   return state->m_mxtc_config_reg[reg];
52   return state->m_mtxc_config_reg[reg];
5353}
5454
55static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
55static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
5656{
5757   voyager_state *state = busdevice->machine().driver_data<voyager_state>();
58//  osd_printf_debug("%s:MXTC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data);
58//  osd_printf_debug("%s:MTXC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data);
5959
6060   switch(reg)
6161   {
r32808r32809
7272            //Execution Hack to avoid crash when switch back from Shadow RAM to Bios ROM, since i386 emu haven't yet pipelined execution structure.
7373            //It happens when exit from BIOS SETUP.
7474            #if 0
75            if ((state->m_mxtc_config_reg[0x63] & 0x50) | ( state->m_mxtc_config_reg[0x63] & 0xA0)) // Only DO if comes a change to disable ROM.
75            if ((state->m_mtxc_config_reg[0x63] & 0x50) | ( state->m_mtxc_config_reg[0x63] & 0xA0)) // Only DO if comes a change to disable ROM.
7676            {
7777               if ( busdevice->machine(->safe_pc().device("maincpu"))==0xff74e) state->m_maincpu->set_pc(0xff74d);
7878            }
r32808r32809
8585      }
8686   }
8787
88   state->m_mxtc_config_reg[reg] = data;
88   state->m_mtxc_config_reg[reg] = data;
8989}
9090
9191void voyager_state::intel82439tx_init()
9292{
93   m_mxtc_config_reg[0x60] = 0x02;
94   m_mxtc_config_reg[0x61] = 0x02;
95   m_mxtc_config_reg[0x62] = 0x02;
96   m_mxtc_config_reg[0x63] = 0x02;
97   m_mxtc_config_reg[0x64] = 0x02;
98   m_mxtc_config_reg[0x65] = 0x02;
93   m_mtxc_config_reg[0x60] = 0x02;
94   m_mtxc_config_reg[0x61] = 0x02;
95   m_mtxc_config_reg[0x62] = 0x02;
96   m_mtxc_config_reg[0x63] = 0x02;
97   m_mtxc_config_reg[0x64] = 0x02;
98   m_mtxc_config_reg[0x65] = 0x02;
9999}
100100
101101static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask)
r32808r32809
107107
108108   if (ACCESSING_BITS_24_31)
109109   {
110      r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24;
110      r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24;
111111   }
112112   if (ACCESSING_BITS_16_23)
113113   {
114      r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16;
114      r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16;
115115   }
116116   if (ACCESSING_BITS_8_15)
117117   {
118      r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8;
118      r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8;
119119   }
120120   if (ACCESSING_BITS_0_7)
121121   {
122      r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0;
122      r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0;
123123   }
124124   return r;
125125}
r32808r32809
128128{
129129   if (ACCESSING_BITS_24_31)
130130   {
131      mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
131      mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
132132   }
133133   if (ACCESSING_BITS_16_23)
134134   {
135      mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
135      mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
136136   }
137137   if (ACCESSING_BITS_8_15)
138138   {
139      mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
139      mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
140140   }
141141   if (ACCESSING_BITS_0_7)
142142   {
143      mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
143      mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
144144   }
145145}
146146
r32808r32809
208208
209209WRITE32_MEMBER(voyager_state::bios_ram_w)
210210{
211   //if (m_mxtc_config_reg[0x59] & 0x20)       // write to RAM if this region is write-enabled
212         if (m_mxtc_config_reg[0x63] & 0x50)
211   //if (m_mtxc_config_reg[0x59] & 0x20)       // write to RAM if this region is write-enabled
212         if (m_mtxc_config_reg[0x63] & 0x50)
213213   {
214214      COMBINE_DATA(m_bios_ram + offset);
215215   }

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