Previous

199869 Revisions

Next

r32808 Saturday 18th October, 2014 at 20:24:58 UTC by Tafoid

intelfsh.c:  [Joe Sturm] * Added support for AMD 29F400T, AMD 29F800T and FUJITSU 29F160T. ti85.c:  [Joe Sturm] * Improved support of TI83 Plus, TI83 Plus Silver Edition, and TI84 Plus, and TI84 Plus Silver Edition by switching over to bankdev and adding proper flash chips.  They should be working now (press Q to power on). Out of whatsnew: ti84p was not added to mess.lst becuase rom is not available yet.  Current romload is same CRC as ti84pse but at a smaller size.  Once corrected and obtained it should work.

[src/emu/machine]	intelfsh.c intelfsh.h
[src/mess/drivers]	ti85.c
[src/mess/includes]	ti85.h
[src/mess/machine]	ti85.c

trunk/src/emu/machine/intelfsh.c

r32807	r32808
82	82	const device_type AMD_29F010 = &device_creator<amd_29f010_device>;
83	83	const device_type AMD_29F040 = &device_creator<amd_29f040_device>;
84	84	const device_type AMD_29F080 = &device_creator<amd_29f080_device>;
	85	const device_type AMD_29F400T = &device_creator<amd_29f400t_device>;
	86	const device_type AMD_29F800T = &device_creator<amd_29f800t_device>;
85	87	const device_type AMD_29LV200T = &device_creator<amd_29lv200t_device>;
	88	const device_type FUJITSU_29F160T = &device_creator<fujitsu_29f160t_device>;
86	89	const device_type FUJITSU_29F016A = &device_creator<fujitsu_29f016a_device>;
87	90	const device_type FUJITSU_29DL16X = &device_creator<fujitsu_29dl16x_device>;
88	91	const device_type INTEL_E28F400B = &device_creator<intel_e28f400b_device>;
r32807	r32808
163	166	m_maker_id(0),
164	167	m_sector_is_4k(false),
165	168	m_sector_is_16k(false),
	169	m_top_boot_sector(false),
166	170	m_status(0x80),
167	171	m_erase_sector(0),
168	172	m_flash_mode(FM_NORMAL),
r32807	r32808
211	215	m_device_id = 0xd5;
212	216	map = ADDRESS_MAP_NAME( memory_map8_8Mb );
213	217	break;
	218	case FLASH_AMD_29F400T:
	219	m_bits = 8;
	220	m_size = 0x80000;
	221	m_maker_id = MFG_AMD;
	222	m_device_id = 0x23;
	223	m_top_boot_sector = true;
	224	map = ADDRESS_MAP_NAME( memory_map8_4Mb );
	225	break;
	226	case FLASH_AMD_29F800T:
	227	m_bits = 8;
	228	m_size = 0x100000;
	229	m_maker_id = MFG_AMD;
	230	m_device_id = 0xda;
	231	m_top_boot_sector = true;
	232	map = ADDRESS_MAP_NAME( memory_map8_8Mb );
	233	break;
214	234	case FLASH_AMD_29LV200T:
215	235	m_bits = 8;
216	236	m_size = 0x40000;
r32807	r32808
256	276	m_device_id = 0x4471;
257	277	map = ADDRESS_MAP_NAME( memory_map16_4Mb );
258	278	break;
	279	case FLASH_FUJITSU_29F160T:
	280	m_bits = 8;
	281	m_size = 0x200000;
	282	m_maker_id = MFG_FUJITSU;
	283	m_device_id = 0xad;
	284	m_top_boot_sector = true;
	285	map = ADDRESS_MAP_NAME( memory_map8_16Mb );
	286	break;
259	287	case FLASH_FUJITSU_29F016A:
260	288	m_bits = 8;
261	289	m_size = 0x200000;
r32807	r32808
349	377	intel_28f016s5_device::intel_28f016s5_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
350	378	: intelfsh8_device(mconfig, INTEL_28F016S5, "Intel 28F016S5 Flash", tag, owner, clock, FLASH_INTEL_28F016S5, "intel_28f016s5", __FILE__) { }
351	379
	380	fujitsu_29f160t_device::fujitsu_29f160t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	381	: intelfsh8_device(mconfig, FUJITSU_29F160T, "Fujitsu 29F160 Flash", tag, owner, clock, FLASH_FUJITSU_29F160T, "fujitsu_29f160t", __FILE__) { }
	382
352	383	fujitsu_29f016a_device::fujitsu_29f016a_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
353	384	: intelfsh8_device(mconfig, FUJITSU_29F016A, "Fujitsu 29F016A Flash", tag, owner, clock, FLASH_FUJITSU_29F016A, "fujitsu_29f016a", __FILE__) { }
354	385
r32807	r32808
369	400
370	401	amd_29f080_device::amd_29f080_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
371	402	: intelfsh8_device(mconfig, AMD_29F080, "AMD 29F080 Flash", tag, owner, clock, FLASH_AMD_29F080, "amd_29f080", __FILE__) { }
	403
	404	amd_29f400t_device::amd_29f400t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	405	: intelfsh8_device(mconfig, AMD_29F080, "AMD 29F400 Flash", tag, owner, clock, FLASH_AMD_29F400T, "amd_29f400t", __FILE__) { }
	406
	407	amd_29f800t_device::amd_29f800t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	408	: intelfsh8_device(mconfig, AMD_29F080, "AMD 29F800 Flash", tag, owner, clock, FLASH_AMD_29F080, "amd_29f800t", __FILE__) { }
372	409
373	410	amd_29lv200t_device::amd_29lv200t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
374	411	: intelfsh8_device(mconfig, AMD_29LV200T, "AMD 29LV200T Flash", tag, owner, clock, FLASH_AMD_29LV200T, "amd_29lv200t", __FILE__) { }
r32807	r32808
878	915	m_erase_sector = address & ((m_bits == 16) ? ~0x1fff : ~0x3fff);
879	916	m_timer->adjust( attotime::from_msec( 500 ) );
880	917	}
	918	else if(m_top_boot_sector && address >= (m_size - 64*1024))
	919	{
	920	if (address >= (m_size - (16*1024)))
	921	{
	922	for (offs_t offs = 0; offs < 16 * 1024; offs++)
	923	m_addrspace[0]->write_byte((base & ~0x3fff) + offs, 0xff);
	924	m_erase_sector = address & ((m_bits == 16) ? ~0x1fff : ~0x3fff);
	925	m_timer->adjust( attotime::from_msec( 500 ) );
	926	}
	927	else if (address >= (m_size - (32*1024)))
	928	{
	929	for (offs_t offs = 0; offs < 8 * 1024; offs++)
	930	m_addrspace[0]->write_byte((base & ~0x1fff) + offs, 0xff);
	931	m_erase_sector = address & ((m_bits == 16) ? ~0xfff : ~0x1fff);
	932	m_timer->adjust( attotime::from_msec( 250 ) );
	933	}
	934	else
	935	{
	936	for (offs_t offs = 0; offs < 32 * 1024; offs++)
	937	m_addrspace[0]->write_byte((base & ~0x7fff) + offs, 0xff);
	938	m_erase_sector = address & ((m_bits == 16) ? ~0x3fff : ~0x7fff);
	939	m_timer->adjust( attotime::from_msec( 500 ) );
	940	}
	941	}
881	942	else
882	943	{
883	944	for (offs_t offs = 0; offs < 64 * 1024; offs++)

trunk/src/emu/machine/intelfsh.h

r32807	r32808
28	28	#define MCFG_AMD_29F080_ADD(_tag) \
29	29	MCFG_DEVICE_ADD(_tag, AMD_29F080, 0)
30	30
	31	#define MCFG_AMD_29F400T_ADD(_tag) \
	32	MCFG_DEVICE_ADD(_tag, AMD_29F400T, 0)
	33
	34	#define MCFG_AMD_29F800T_ADD(_tag) \
	35	MCFG_DEVICE_ADD(_tag, AMD_29F800T, 0)
	36
31	37	#define MCFG_AMD_29LV200T_ADD(_tag) \
32	38	MCFG_DEVICE_ADD(_tag, AMD_29LV200T, 0)
33	39
	40	#define MCFG_FUJITSU_29F160T_ADD(_tag) \
	41	MCFG_DEVICE_ADD(_tag, FUJITSU_29F160T, 0)
	42
34	43	#define MCFG_FUJITSU_29F016A_ADD(_tag) \
35	44	MCFG_DEVICE_ADD(_tag, FUJITSU_29F016A, 0)
36	45
r32807	r32808
94	103	{
95	104	// 8-bit variants
96	105	FLASH_INTEL_28F016S5 = 0x0800,
	106	FLASH_FUJITSU_29F160T,
97	107	FLASH_FUJITSU_29F016A,
98	108	FLASH_FUJITSU_29DL16X,
99	109	FLASH_ATMEL_29C010,
100	110	FLASH_AMD_29F010,
101	111	FLASH_AMD_29F040,
102	112	FLASH_AMD_29F080,
	113	FLASH_AMD_29F400T,
	114	FLASH_AMD_29F800T,
103	115	FLASH_AMD_29LV200T,
104	116	FLASH_SHARP_LH28F016S,
105	117	FLASH_INTEL_E28F008SA,
r32807	r32808
149	161	UINT8                   m_maker_id;
150	162	bool                    m_sector_is_4k;
151	163	bool                    m_sector_is_16k;
	164	bool               m_top_boot_sector;
152	165	UINT8                   m_page_size;
153	166
154	167	// internal state
r32807	r32808
211	224	intel_28f016s5_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
212	225	};
213	226
	227	class fujitsu_29f160t_device : public intelfsh8_device
	228	{
	229	public:
	230	fujitsu_29f160t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	231	};
	232
214	233	class fujitsu_29f016a_device : public intelfsh8_device
215	234	{
216	235	public:
r32807	r32808
247	266	amd_29f080_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
248	267	};
249	268
	269	class amd_29f400t_device : public intelfsh8_device
	270	{
	271	public:
	272	amd_29f400t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	273	};
	274
	275	class amd_29f800t_device : public intelfsh8_device
	276	{
	277	public:
	278	amd_29f800t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	279	};
	280
250	281	class amd_29lv200t_device : public intelfsh8_device
251	282	{
252	283	public:
r32807	r32808
346	377	extern const device_type AMD_29F010;
347	378	extern const device_type AMD_29F040;
348	379	extern const device_type AMD_29F080;
	380	extern const device_type AMD_29F400T;
	381	extern const device_type AMD_29F800T;
349	382	extern const device_type AMD_29LV200T;
	383	extern const device_type FUJITSU_29F160T;
350	384	extern const device_type FUJITSU_29F016A;
351	385	extern const device_type FUJITSU_29DL16X;
352	386	extern const device_type INTEL_E28F400B;

trunk/src/mess/machine/ti85.c

r32807	r32808
14	14	#define TI85_SNAPSHOT_SIZE   32976
15	15	#define TI86_SNAPSHOT_SIZE  131284
16	16
17
18	17	TIMER_CALLBACK_MEMBER(ti85_state::ti85_timer_callback)
19	18	{
20	19	if (ioport("ON")->read() & 0x01)
r32807	r32808
23	22	{
24	23	m_maincpu->set_input_line(0, HOLD_LINE);
25	24	m_ON_interrupt_status = 1;
26		if (!m_timer_interrupt_mask) m_timer_interrupt_mask = 1;
	25	if (!m_timer_interrupt_mask) m_timer_interrupt_mask = 2;
27	26	}
28	27	m_ON_pressed = 1;
29	28	return;
r32807	r32808
33	32	if (m_timer_interrupt_mask)
34	33	{
35	34	m_maincpu->set_input_line(0, HOLD_LINE);
36		m_timer_interrupt_status = 1;
	35	m_timer_interrupt_status = m_timer_interrupt_mask;
37	36	}
38	37	}
39	38
	39	TIMER_CALLBACK_MEMBER(ti85_state::ti83_timer1_callback)
	40	{
	41	if (ioport("ON")->read() & 0x01)
	42	{
	43	if (m_ON_interrupt_mask && !m_ON_pressed)
	44	{
	45	m_maincpu->set_input_line(0, HOLD_LINE);
	46	m_ON_interrupt_status = 1;
	47	}
	48	m_ON_pressed = 1;
	49	return;
	50	}
	51	else
	52	{
	53	m_ON_pressed = 0;
	54	}
	55	if (m_timer_interrupt_mask & 2)
	56	{
	57	m_maincpu->set_input_line(0, HOLD_LINE);
	58	m_timer_interrupt_status = m_timer_interrupt_status | 2;
	59	}
	60	}
	61
	62	TIMER_CALLBACK_MEMBER(ti85_state::ti83_timer2_callback)
	63	{
	64	if (m_timer_interrupt_mask & 4)
	65	{
	66	m_maincpu->set_input_line(0, HOLD_LINE);
	67	m_timer_interrupt_status = m_timer_interrupt_status | 4;
	68	}
	69	}
	70
	71	void ti85_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
	72	{
	73	switch (id)
	74	{
	75	case CRYSTAL_TIMER3:
	76	case CRYSTAL_TIMER2:
	77	case CRYSTAL_TIMER1:
	78	if (m_ctimer[id].count)
	79	{
	80	m_ctimer[id].count--;
	81	if (!m_ctimer[id].count)
	82	{
	83	if (!(m_ctimer[id].loop & 4))
	84	{
	85	if (!(m_ctimer[id].loop & 1))
	86	{
	87	m_ctimer[id].setup = 0;
	88	}
	89	else
	90	{
	91	ti83pse_count(id, m_ctimer[id].max);
	92	}
	93	if (!(m_ctimer[id].loop & 2))
	94	{
	95	//generate interrupt
	96	m_ctimer_interrupt_status |= (0x20 << id);
	97	m_maincpu->set_input_line(0, HOLD_LINE);
	98	}
	99	m_ctimer[id].loop &= 2;
	100	}
	101	}
	102	}
	103	break;
	104	case HW_TIMER1:
	105	if (ioport("ON")->read() & 0x01)
	106	{
	107	if (m_ON_interrupt_mask && !m_ON_pressed)
	108	{
	109	m_maincpu->set_input_line(0, HOLD_LINE);
	110	m_ON_interrupt_status = 1;
	111	}
	112	m_ON_pressed = 1;
	113	return;
	114	}
	115	else
	116	{
	117	m_ON_pressed = 0;
	118	}
	119	if (m_timer_interrupt_mask & 2)
	120	{
	121	m_maincpu->set_input_line(0, HOLD_LINE);
	122	m_timer_interrupt_status = m_timer_interrupt_status | 2;
	123	}
	124	break;
	125	case HW_TIMER2:
	126	if (m_timer_interrupt_mask & 4)
	127	{
	128	m_maincpu->set_input_line(0, HOLD_LINE);
	129	m_timer_interrupt_status = m_timer_interrupt_status | 4;
	130	}
	131	}
	132	}
	133
40	134	inline void ti8x_update_bank(address_space &space, UINT8 bank, UINT8 *base, UINT8 page, bool is_ram)
41	135	{
42	136	ti85_state *state = space.machine().driver_data<ti85_state>();
r32807	r32808
59	153	{
60	154	address_space &space = m_maincpu->space(AS_PROGRAM);
61	155
62		if (m_ti8x_memory_page_1 & 0x40)
	156	m_membank1->set_bank(0); //Always flash page 0, well allmost
	157
	158	if (m_ti83p_port4 & 1)
63	159	{
64		ti8x_update_bank(space, (m_ti83p_port4 & 1) ? 2 : 1, m_ti8x_ram, m_ti8x_memory_page_1 & 0x01, true);
	160
	161	m_membank2->set_bank(m_ti8x_memory_page_1 & 0xfe);
	162
	163	m_membank3->set_bank(m_ti8x_memory_page_1);
	164
	165	m_membank4->set_bank(m_ti8x_memory_page_2);
	166
65	167	}
66	168	else
67	169	{
68		ti8x_update_bank(space, (m_ti83p_port4 & 1) ? 2 : 1, m_bios, m_ti8x_memory_page_1 & 0x1f, false);
	170
	171	m_membank2->set_bank(m_ti8x_memory_page_1);
	172
	173	m_membank3->set_bank(m_ti8x_memory_page_2);
	174
	175	m_membank4->set_bank(0x40); //Always first ram page
	176
69	177	}
	178	}
70	179
71		if (m_ti8x_memory_page_2 & 0x40)
72		{
73		ti8x_update_bank(space, (m_ti83p_port4 & 1) ? 3 : 2, m_ti8x_ram, m_ti8x_memory_page_2 & 0x01, true);
	180	void ti85_state::update_ti83pse_memory ()
	181	{
	182	address_space &space = m_maincpu->space(AS_PROGRAM);
	183
	184	m_membank1->set_bank(m_ti8x_memory_page_0);
	185
	186	if (m_ti83p_port4 & 1)
	187	{
	188
	189	m_membank2->set_bank(m_ti8x_memory_page_1 & 0xfe);
	190
	191	m_membank3->set_bank(m_ti8x_memory_page_1 | 1);
	192
	193	m_membank4->set_bank(m_ti8x_memory_page_2);
	194
	195
74	196	}
75	197	else
76	198	{
77		ti8x_update_bank(space, (m_ti83p_port4 & 1) ? 3 : 2, m_bios, m_ti8x_memory_page_2 & 0x1f, false);
	199
	200	m_membank2->set_bank(m_ti8x_memory_page_1);
	201
	202	m_membank3->set_bank(m_ti8x_memory_page_2);
	203
	204	m_membank4->set_bank(m_ti8x_memory_page_3 + 0x80);
	205
78	206	}
79	207	}
80	208
r32807	r32808
127	255	m_port4_bit0 = 0;
128	256	m_ti81_port_7_data = 0;
129	257
130		machine().scheduler().timer_pulse(attotime::from_hz(200), timer_expired_delegate(FUNC(ti85_state::ti85_timer_callback),this));
	258	machine().scheduler().timer_pulse(attotime::from_hz(256), timer_expired_delegate(FUNC(ti85_state::ti85_timer_callback),this));
131	259
132	260	space.unmap_write(0x0000, 0x3fff);
133	261	space.unmap_write(0x4000, 0x7fff);
r32807	r32808
142	270	m_PCR = 0xc0;
143	271	}
144	272
	273	MACHINE_RESET_MEMBER(ti85_state,ti83p)
	274	{
	275	m_red_out = 0x00;
	276	m_white_out = 0x00;
	277	m_PCR = 0xc0;
145	278
	279	m_ti8x_memory_page_0 = 0;//0x1f;
	280	m_ti8x_memory_page_1 = 0x1f;
	281	m_ti8x_memory_page_2 = 0;
	282	m_ti8x_memory_page_3 = 0;
	283	m_ti83p_port4 = 1;
	284	update_ti83p_memory();
	285
	286	m_maincpu->set_pc(0x8000);
	287	}
	288
	289	MACHINE_RESET_MEMBER(ti85_state,ti83pse)
	290	{
	291	m_red_out = 0x00;
	292	m_white_out = 0x00;
	293	m_PCR = 0xc0;
	294
	295	m_ti8x_memory_page_0 = 0;//0x1f;
	296	m_ti8x_memory_page_1 = 0x7f;
	297	m_ti8x_memory_page_2 = 0;
	298	m_ti8x_memory_page_3 = 0;
	299	m_ti83p_port4 = 1;
	300	update_ti83pse_memory();
	301
	302	m_maincpu->set_pc(0x8000);
	303	}
	304
146	305	MACHINE_START_MEMBER(ti85_state,ti83p)
147	306	{
148	307	address_space &space = m_maincpu->space(AS_PROGRAM);
149		m_bios = memregion("bios")->base();
	308	//m_bios = memregion("flash")->base();
150	309
151	310	m_timer_interrupt_mask = 0;
152	311	m_timer_interrupt_status = 0;
153	312	m_ON_interrupt_mask = 0;
154	313	m_ON_interrupt_status = 0;
155	314	m_ON_pressed = 0;
156		m_ti8x_memory_page_1 = 0;
	315	m_ti8x_memory_page_0 = 0;//0x1f;
	316	m_ti8x_memory_page_1 = 0x1f;
157	317	m_ti8x_memory_page_2 = 0;
	318	m_ti8x_memory_page_3 = 0;
158	319	m_LCD_memory_base = 0;
159	320	m_LCD_status = 0;
160	321	m_LCD_mask = 0;
r32807	r32808
162	323	m_keypad_mask = 0;
163	324	m_video_buffer_width = 0;
164	325	m_interrupt_speed = 0;
165		m_port4_bit0 = 0;
	326	m_ti83p_port4 = 1;
	327	m_flash_unlocked = 0;
166	328
167		m_ti8x_ram = auto_alloc_array(machine(), UINT8, 32*1024);
168		memset(m_ti8x_ram, 0, sizeof(UINT8)*32*1024);
	329	ti85_state::update_ti83p_memory ();
169	330
170		space.unmap_write(0x0000, 0x3fff);
171		space.unmap_write(0x4000, 0x7fff);
172		space.unmap_write(0x8000, 0xbfff);
	331	machine().scheduler().timer_pulse(attotime::from_hz(256), timer_expired_delegate(FUNC(ti85_state::ti83_timer1_callback),this));
	332	machine().scheduler().timer_pulse(attotime::from_hz(512), timer_expired_delegate(FUNC(ti85_state::ti83_timer2_callback),this));
173	333
174		membank("bank1")->set_base(m_bios);
175		membank("bank2")->set_base(m_bios);
176		membank("bank3")->set_base(m_bios);
177		membank("bank4")->set_base(m_ti8x_ram);
178		machine().device<nvram_device>("nvram")->set_base(m_ti8x_ram, sizeof(UINT8)*32*1024);
	334	/* save states and debugging */
	335	save_item(NAME(m_timer_interrupt_mask));
	336	save_item(NAME(m_ti8x_memory_page_0));
	337	save_item(NAME(m_ti8x_memory_page_1));
	338	save_item(NAME(m_ti8x_memory_page_2));
	339	save_item(NAME(m_ti8x_memory_page_3));
	340	save_item(NAME(m_ti83p_port4));
	341	}
179	342
180		machine().scheduler().timer_pulse(attotime::from_hz(200), timer_expired_delegate(FUNC(ti85_state::ti85_timer_callback),this));
	343	MACHINE_START_MEMBER(ti85_state,ti83pse)
	344	{
	345	address_space &space = m_maincpu->space(AS_PROGRAM);
	346	//address_space &asic =  ADDRESS_MAP_NAME(ti83p_asic_mem);
	347
	348	m_timer_interrupt_mask = 0;
	349	m_timer_interrupt_status = 0;
	350	m_ctimer_interrupt_status = 0;
	351	m_ON_interrupt_mask = 0;
	352	m_ON_interrupt_status = 0;
	353	m_ON_pressed = 0;
	354	m_ti8x_memory_page_0 = 00;//0x7f;
	355	m_ti8x_memory_page_1 = 0x7f;
	356	m_ti8x_memory_page_2 = 0;
	357	m_ti8x_memory_page_3 = 0;
	358	m_LCD_memory_base = 0;
	359	m_LCD_status = 0;
	360	m_LCD_mask = 0;
	361	m_power_mode = 0;
	362	m_keypad_mask = 0;
	363	m_video_buffer_width = 0;
	364	m_interrupt_speed = 0;
	365	m_ti83p_port4 = 1;
	366	m_flash_unlocked = 0;
	367
	368	ti85_state::update_ti83p_memory();
	369	m_maincpu->set_pc(0x8000);
	370
	371
	372	machine().scheduler().timer_pulse(attotime::from_hz(256), timer_expired_delegate(FUNC(ti85_state::ti83_timer1_callback),this));
	373	machine().scheduler().timer_pulse(attotime::from_hz(512), timer_expired_delegate(FUNC(ti85_state::ti83_timer2_callback),this));
	374
	375	m_crystal_timer1 = timer_alloc(CRYSTAL_TIMER1);
	376	m_crystal_timer2 = timer_alloc(CRYSTAL_TIMER2);
	377	m_crystal_timer3 = timer_alloc(CRYSTAL_TIMER3);
	378
	379	/* save states and debugging */
	380	save_item(NAME(m_ctimer_interrupt_status));
	381	save_item(NAME(m_timer_interrupt_status));
	382	save_item(NAME(m_ti8x_memory_page_0));
	383	save_item(NAME(m_ti8x_memory_page_1));
	384	save_item(NAME(m_ti8x_memory_page_2));
	385	save_item(NAME(m_ti8x_memory_page_3));
	386	save_item(NAME(m_ti83p_port4));
181	387	}
182	388
183
184	389	MACHINE_START_MEMBER(ti85_state,ti86)
185	390	{
186	391	address_space &space = m_maincpu->space(AS_PROGRAM);
r32807	r32808
213	418	membank("bank4")->set_base(m_ti8x_ram);
214	419	machine().device<nvram_device>("nvram")->set_base(m_ti8x_ram, sizeof(UINT8)*128*1024);
215	420
216		machine().scheduler().timer_pulse(attotime::from_hz(200), timer_expired_delegate(FUNC(ti85_state::ti85_timer_callback),this));
	421	machine().scheduler().timer_pulse(attotime::from_hz(256), timer_expired_delegate(FUNC(ti85_state::ti85_timer_callback),this));
217	422	}
218	423
219	424
r32807	r32808
309	514	return m_ti8x_memory_page_2;
310	515	}
311	516
	517	READ8_MEMBER(ti85_state::ti83pse_port_0005_r )
	518	{
	519	return m_ti8x_memory_page_3;
	520	}
	521
312	522	READ8_MEMBER(ti85_state::ti83_port_0000_r)
313	523	{
314	524	return ((m_ti8x_memory_page_1 & 0x08) << 1) | 0x0C;
r32807	r32808
323	533	{
324	534	int data = 0;
325	535
326		data |= m_LCD_mask;
327
328	536	if (m_ON_interrupt_status)
329	537	data |= 0x01;
330	538	if (!m_ON_pressed)
331	539	data |= 0x08;
332		m_ON_interrupt_status = 0;
333		m_timer_interrupt_status = 0;
	540
	541	data |= m_timer_interrupt_status;
	542
334	543	return data;
335	544	}
336	545
r32807	r32808
350	559	return m_ti8x_port2|3;
351	560	}
352	561
	562	READ8_MEMBER(ti85_state::ti83p_port_0004_r )
	563	{
	564	int data = 0;
	565
	566	//data |= m_LCD_mask;
	567
	568	if (m_ON_interrupt_status)
	569	data |= 0x01;
	570	if (!m_ON_pressed)
	571	data |= 0x08;
	572
	573	data |= m_timer_interrupt_status;
	574
	575	data |= m_ctimer_interrupt_status;
	576
	577	return data;
	578	}
	579
	580	//------------------------
	581	// bit 0 - battery test (not implemented)
	582	// Bit 1 - LCD wait
	583	// bit 2 - flash lock
	584	// bit 3 - not used
	585	// bit 4 - not used
	586	// bit 5 - Set if USB hardware is present
	587	// bit 6 - Indicates if Link Assist is available
	588	// bit 7 - SE or Basic
	589
	590	READ8_MEMBER(ti85_state::ti83pse_port_0002_r )
	591	{
	592	return 0xC3 | (m_flash_unlocked << 2);
	593	}
	594
	595	READ8_MEMBER(ti85_state::ti83pse_port_0009_r )
	596	{
	597	return 0;
	598	}
	599
	600	READ8_MEMBER(ti85_state::ti83pse_port_0015_r )
	601	{
	602	return 0x33;
	603	}
	604
	605
353	606	WRITE8_MEMBER(ti85_state::ti81_port_0007_w)
354	607	{
355	608	m_ti81_port_7_data = data;
r32807	r32808
460	713	m_PCR = data & 0xf0;
461	714	}
462	715
463		WRITE8_MEMBER(ti85_state::ti83p_port_0002_w)
	716	WRITE8_MEMBER(ti85_state::ti83pse_int_ack_w)
464	717	{
465		m_ti8x_port2 = data;
	718	//Lets ignore this for now, I think it'll be fine.
	719	m_ON_interrupt_status = data & 1;
	720	m_timer_interrupt_status = data & 0x06;
466	721	}
467	722
468		WRITE8_MEMBER(ti85_state::ti83p_port_0003_w)
	723	WRITE8_MEMBER(ti85_state::ti83p_int_mask_w)
469	724	{
470		m_LCD_mask = (data&0x08) >> 2;
	725	//m_LCD_mask = (data&0x08) >> 2;
471	726	m_ON_interrupt_mask = data & 0x01;
	727	m_ON_interrupt_status &= m_ON_interrupt_mask;
	728
	729	m_timer_interrupt_mask = data & 0x06;
	730
	731	m_timer_interrupt_status &= m_timer_interrupt_mask;
472	732	}
473	733
474	734	WRITE8_MEMBER(ti85_state::ti83p_port_0004_w)
475	735	{
476		if ((data & 1) && !(m_ti83p_port4 & 1))
477		{
478		m_ti8x_memory_page_1 = 0x1f;
479		m_ti8x_memory_page_2 = 0x1f;
480		}
481		else if (!(data & 1) && (m_ti83p_port4 & 1))
482		{
483		m_ti8x_memory_page_1 = 0x1f;
484		m_ti8x_memory_page_2 = 0x40;
485		}
	736	m_ti83p_port4 = data | 0xe0;
486	737	update_ti83p_memory();
487		m_ti83p_port4 = data;
488	738	}
489	739
490	740	WRITE8_MEMBER(ti85_state::ti83p_port_0006_w)
r32807	r32808
499	749	update_ti83p_memory();
500	750	}
501	751
	752	WRITE8_MEMBER(ti85_state::ti83pse_port_0004_w)
	753	{
	754	m_ti83p_port4 = data;
	755	update_ti83pse_memory();
	756	}
	757
	758	WRITE8_MEMBER(ti85_state::ti83pse_port_0005_w)
	759	{
	760	m_ti8x_memory_page_3 = data & 0x07;
	761	update_ti83pse_memory();
	762	}
	763
	764	WRITE8_MEMBER(ti85_state::ti83pse_port_0006_w)
	765	{
	766	m_ti8x_memory_page_1 = data; //& ((data&0x80) ? 0x41 : 0x7f);
	767	update_ti83pse_memory();
	768	}
	769
	770	WRITE8_MEMBER(ti85_state::ti83pse_port_0007_w)
	771	{
	772	m_ti8x_memory_page_2 = data; //& ((data&0x80) ? 0x41 : 0x7f);
	773	update_ti83pse_memory();
	774	}
	775
	776	WRITE8_MEMBER(ti85_state::ti83p_port_0014_w)
	777	{
	778	m_flash_unlocked = data;
	779	update_ti83pse_memory();
	780	}
	781
	782	WRITE8_MEMBER(ti85_state::ti83pse_port_0020_w)
	783	{
	784	m_cpu_speed = data;
	785	if(data)
	786	{
	787	m_maincpu->set_unscaled_clock(15000000);
	788	}
	789	else
	790	{
	791	m_maincpu->set_unscaled_clock(6000000);
	792	}
	793	}
	794
	795	READ8_MEMBER(ti85_state::ti83pse_port_0020_r)
	796	{
	797	return m_cpu_speed;
	798	}
	799
	800	WRITE8_MEMBER(ti85_state::ti83pse_port_0021_w)
	801	{
	802	m_ti83pse_port21 = data & 0x0f;
	803	}
	804
	805	READ8_MEMBER(ti85_state::ti83pse_port_0021_r)
	806	{
	807	return m_ti83pse_port21;
	808	}
	809
	810	READ8_MEMBER(ti85_state::ti84pse_port_0055_r)
	811	{
	812	return 0x1f;
	813	}
	814
	815	READ8_MEMBER(ti85_state::ti84pse_port_0056_r)
	816	{
	817	return 0;
	818	}
	819
	820	//timer ports
	821
	822	void ti85_state::ti83pse_count( UINT8 timer, UINT8 data)
	823	{
	824	m_ctimer[timer].max = m_ctimer[timer].count = data;
	825
	826	if (m_ctimer[timer].setup)
	827	{
	828	switch (m_ctimer[timer].setup & 0x07)
	829	{
	830	case 0x00:
	831	m_ctimer[timer].divsor = 3.0;
	832	break;
	833	case 0x01:
	834	m_ctimer[timer].divsor = 32.0;
	835	break;
	836	case 0x02:
	837	m_ctimer[timer].divsor = 327.000;
	838	break;
	839	case 0x03:
	840	m_ctimer[timer].divsor = 3276.00;
	841	break;
	842	case 0x04:
	843	m_ctimer[timer].divsor = 1.0;
	844	break;
	845	case 0x05:
	846	m_ctimer[timer].divsor = 16.0;
	847	break;
	848	case 0x06:
	849	m_ctimer[timer].divsor = 256.0;
	850	break;
	851	case 0x07:
	852	m_ctimer[timer].divsor = 4096.0;
	853	break;
	854	}
	855	switch (timer)
	856	{
	857	case CRYSTAL_TIMER1:
	858	m_crystal_timer1->adjust(attotime::zero, 0, attotime::from_hz( 32768.0/m_ctimer[timer].divsor));
	859	m_crystal_timer1->enable(true);
	860	break;
	861	case CRYSTAL_TIMER2:
	862	m_crystal_timer2->adjust(attotime::zero, 0, attotime::from_hz( 32768.0/m_ctimer[timer].divsor));
	863	m_crystal_timer2->enable(true);
	864	break;
	865	case CRYSTAL_TIMER3:
	866	m_crystal_timer3->adjust(attotime::zero, 0, attotime::from_hz( 32768.0/m_ctimer[timer].divsor));
	867	m_crystal_timer3->enable(true);
	868	break;
	869
	870	}
	871	}
	872	}
	873
	874
	875	READ8_MEMBER(ti85_state::ti83pse_ctimer1_setup_r)
	876	{
	877	return m_ctimer[CRYSTAL_TIMER1].setup;
	878	}
	879
	880	WRITE8_MEMBER(ti85_state::ti83pse_ctimer1_setup_w)
	881	{
	882	m_crystal_timer1->enable(false);
	883	m_ctimer[CRYSTAL_TIMER1].setup = data;
	884	}
	885
	886	READ8_MEMBER(ti85_state::ti83pse_ctimer1_loop_r)
	887	{
	888	return m_ctimer[CRYSTAL_TIMER1].loop;
	889	}
	890
	891	WRITE8_MEMBER(ti85_state::ti83pse_ctimer1_loop_w)
	892	{
	893	m_ctimer[CRYSTAL_TIMER1].loop = data & 0x03;
	894	m_ctimer_interrupt_status = 0;
	895	}
	896
	897	READ8_MEMBER(ti85_state::ti83pse_ctimer1_count_r)
	898	{
	899	return m_ctimer[CRYSTAL_TIMER1].count;
	900	}
	901
	902	WRITE8_MEMBER(ti85_state::ti83pse_ctimer1_count_w)
	903	{
	904	ti83pse_count(CRYSTAL_TIMER1, data);
	905
	906	}
	907
	908	//
	909
	910	READ8_MEMBER(ti85_state::ti83pse_ctimer2_setup_r)
	911	{
	912	return m_ctimer[CRYSTAL_TIMER2].setup;
	913	}
	914
	915	WRITE8_MEMBER(ti85_state::ti83pse_ctimer2_setup_w)
	916	{
	917	m_crystal_timer2->enable(false);
	918	m_ctimer[CRYSTAL_TIMER2].setup = data;
	919	}
	920
	921	READ8_MEMBER(ti85_state::ti83pse_ctimer2_loop_r)
	922	{
	923	return m_ctimer[CRYSTAL_TIMER2].loop;
	924	}
	925
	926	WRITE8_MEMBER(ti85_state::ti83pse_ctimer2_loop_w)
	927	{
	928	m_ctimer[CRYSTAL_TIMER2].loop = data & 0x03;
	929	m_ctimer_interrupt_status = 0;
	930	}
	931
	932	READ8_MEMBER(ti85_state::ti83pse_ctimer2_count_r)
	933	{
	934	return m_ctimer[CRYSTAL_TIMER2].count;
	935	}
	936
	937	WRITE8_MEMBER(ti85_state::ti83pse_ctimer2_count_w)
	938	{
	939	ti83pse_count(CRYSTAL_TIMER2, data);
	940
	941	}
	942
	943	//
	944
	945	READ8_MEMBER(ti85_state::ti83pse_ctimer3_setup_r)
	946	{
	947	return m_ctimer[CRYSTAL_TIMER3].setup;
	948	}
	949
	950	WRITE8_MEMBER(ti85_state::ti83pse_ctimer3_setup_w)
	951	{
	952	m_crystal_timer3->enable(false);
	953	m_ctimer[CRYSTAL_TIMER3].setup = data;
	954	}
	955
	956	READ8_MEMBER(ti85_state::ti83pse_ctimer3_loop_r)
	957	{
	958	return m_ctimer[CRYSTAL_TIMER3].loop;
	959	}
	960
	961	WRITE8_MEMBER(ti85_state::ti83pse_ctimer3_loop_w)
	962	{
	963	m_ctimer[CRYSTAL_TIMER3].loop = data & 0x03;
	964	m_ctimer_interrupt_status = 0;
	965	}
	966
	967	READ8_MEMBER(ti85_state::ti83pse_ctimer3_count_r)
	968	{
	969	return m_ctimer[CRYSTAL_TIMER3].count;
	970	}
	971
	972	WRITE8_MEMBER(ti85_state::ti83pse_ctimer3_count_w)
	973	{
	974	ti83pse_count(CRYSTAL_TIMER3, data);
	975
	976	}
	977
	978
	979
502	980	/***************************************************************************
503	981	TI calculators snapshot files (SAV)
504	982	***************************************************************************/

trunk/src/mess/includes/ti85.h

r32807	r32808
9	9
10	10	#include "imagedev/snapquik.h"
11	11	#include "video/t6a04.h"
	12	#include "machine/bankdev.h"
12	13	#include "sound/speaker.h"
13	14	#include "machine/nvram.h"
	15	#include "machine/intelfsh.h"
14	16
	17
	18	/* model */
	19	typedef enum {
	20	TI81,
	21	TI81v2,
	22	TI82,
	23	TI83,
	24	TI85,
	25	TI86,
	26	TI83P,
	27	TI83PSE,
	28	TI84P,
	29	TI84PSE
	30	} ti85_models;
	31
	32	typedef struct
	33	{
	34	UINT8 loop;
	35	UINT8 setup;
	36	float divsor;
	37	bool interrupt;
	38	UINT8 max;
	39	UINT8 count;
	40	} ti83pse_timer;
	41
	42	typedef enum TI83PSE_CTIMER
	43	{
	44	CRYSTAL_TIMER1 = 0,
	45	CRYSTAL_TIMER2,
	46	CRYSTAL_TIMER3,
	47	HW_TIMER1,
	48	HW_TIMER2
	49	} ti83pse_ctimers;
	50
15	51	class ti85_state : public driver_device
16	52	{
17	53	public:
r32807	r32808
20	56	m_maincpu(*this, "maincpu"),
21	57	m_speaker(*this, "speaker"),
22	58	//        m_serial(*this, "tiserial"),
23		m_nvram(*this, "nvram")
	59	m_nvram(*this, "nvram"),
	60	m_flash(*this, "flash"),
	61	m_membank1(*this, "membank1"),
	62	m_membank2(*this, "membank2"),
	63	m_membank3(*this, "membank3"),
	64	m_membank4(*this, "membank4")
24	65	{ }
25	66
26	67	required_device<cpu_device> m_maincpu;
27	68	optional_device<speaker_sound_device> m_speaker;
28	69	//optional_device<> m_serial;
29	70	optional_shared_ptr<UINT8>  m_nvram;
	71	optional_device<intelfsh_device> m_flash;
	72	optional_device<address_map_bank_device> m_membank1;
	73	optional_device<address_map_bank_device> m_membank2;
	74	optional_device<address_map_bank_device> m_membank3;
	75	optional_device<address_map_bank_device> m_membank4;
30	76
31	77	UINT8 m_LCD_memory_base;
32	78	UINT8 m_LCD_contrast;
33	79	UINT8 m_LCD_status;
34	80	UINT8 m_timer_interrupt_mask;
35	81	UINT8 m_timer_interrupt_status;
	82	UINT8 m_ctimer_interrupt_status;
36	83	UINT8 m_ON_interrupt_mask;
37	84	UINT8 m_ON_interrupt_status;
38	85	UINT8 m_ON_pressed;
	86	UINT8 m_flash_unlocked;
	87	UINT8 m_ti8x_memory_page_0;
39	88	UINT8 m_ti8x_memory_page_1;
40	89	UINT8 m_ti8x_memory_page_2;
	90	UINT8 m_ti8x_memory_page_3;
41	91	UINT8 m_LCD_mask;
42	92	UINT8 m_power_mode;
	93	UINT8 m_cpu_speed;
43	94	UINT8 m_keypad_mask;
44	95	UINT8 m_video_buffer_width;
45	96	UINT8 m_interrupt_speed;
r32807	r32808
51	102	UINT8 m_white_out;
52	103	UINT8 m_ti8x_port2;
53	104	UINT8 m_ti83p_port4;
	105	UINT8 m_ti83pse_port21;
54	106	int m_ti_video_memory_size;
55	107	int m_ti_screen_x_size;
56	108	int m_ti_screen_y_size;
r32807	r32808
80	132	DECLARE_WRITE8_MEMBER(ti83_port_0002_w);
81	133	DECLARE_WRITE8_MEMBER(ti83_port_0003_w);
82	134	DECLARE_WRITE8_MEMBER(ti8x_plus_serial_w);
83		DECLARE_WRITE8_MEMBER(ti83p_port_0002_w);
84		DECLARE_WRITE8_MEMBER(ti83p_port_0003_w);
	135	DECLARE_WRITE8_MEMBER(ti83p_int_mask_w);
85	136	DECLARE_WRITE8_MEMBER(ti83p_port_0004_w);
86	137	DECLARE_WRITE8_MEMBER(ti83p_port_0006_w);
87	138	DECLARE_WRITE8_MEMBER(ti83p_port_0007_w);
	139	DECLARE_WRITE8_MEMBER(ti83pse_int_ack_w);
	140	DECLARE_WRITE8_MEMBER(ti83pse_port_0004_w);
	141	DECLARE_WRITE8_MEMBER(ti83pse_port_0005_w);
	142	DECLARE_WRITE8_MEMBER(ti83pse_port_0006_w);
	143	DECLARE_WRITE8_MEMBER(ti83pse_port_0007_w);
	144	DECLARE_WRITE8_MEMBER(ti83p_port_0014_w);
	145	DECLARE_WRITE8_MEMBER(ti83pse_port_0020_w);
	146	DECLARE_WRITE8_MEMBER(ti83pse_port_0021_w);
88	147	DECLARE_READ8_MEMBER( ti85_port_0002_r );
89	148	DECLARE_READ8_MEMBER( ti85_port_0003_r );
90	149	DECLARE_READ8_MEMBER( ti85_port_0004_r );
r32807	r32808
94	153	DECLARE_READ8_MEMBER( ti83_port_0002_r );
95	154	DECLARE_READ8_MEMBER( ti83_port_0003_r );
96	155	DECLARE_READ8_MEMBER( ti83p_port_0002_r );
	156	DECLARE_READ8_MEMBER( ti83p_port_0004_r );
	157	DECLARE_READ8_MEMBER( ti83pse_port_0002_r );
	158	DECLARE_READ8_MEMBER( ti83pse_port_0005_r );
	159	DECLARE_READ8_MEMBER( ti83pse_port_0009_r );
	160	DECLARE_READ8_MEMBER( ti83pse_port_0015_r );
	161	DECLARE_READ8_MEMBER( ti83pse_port_0020_r );
	162	DECLARE_READ8_MEMBER( ti83pse_port_0021_r );
	163	DECLARE_READ8_MEMBER( ti84pse_port_0055_r );
	164	DECLARE_READ8_MEMBER( ti84pse_port_0056_r );
97	165	virtual void machine_start();
98	166	virtual void video_start();
99	167	DECLARE_PALETTE_INIT(ti85);
100	168	DECLARE_MACHINE_RESET(ti85);
	169	DECLARE_MACHINE_RESET(ti83p);
	170	DECLARE_MACHINE_RESET(ti83pse);
101	171	DECLARE_PALETTE_INIT(ti82);
102	172	DECLARE_MACHINE_START(ti86);
103	173	DECLARE_MACHINE_START(ti83p);
	174	DECLARE_MACHINE_START(ti83pse);
104	175	UINT32 screen_update_ti85(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
105	176	TIMER_CALLBACK_MEMBER(ti85_timer_callback);
	177	TIMER_CALLBACK_MEMBER(ti83_timer1_callback);
	178	TIMER_CALLBACK_MEMBER(ti83_timer2_callback);
	179
	180	//crystal timers
	181	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	182	void ti83pse_count( UINT8 timer, UINT8 data);
	183
	184	emu_timer *m_crystal_timer1;
	185	emu_timer *m_crystal_timer2;
	186	emu_timer *m_crystal_timer3;
	187	DECLARE_READ8_MEMBER( ti83pse_ctimer1_setup_r );
	188	DECLARE_WRITE8_MEMBER( ti83pse_ctimer1_setup_w );
	189	DECLARE_READ8_MEMBER( ti83pse_ctimer1_loop_r );
	190	DECLARE_WRITE8_MEMBER( ti83pse_ctimer1_loop_w );
	191	DECLARE_READ8_MEMBER( ti83pse_ctimer1_count_r );
	192	DECLARE_WRITE8_MEMBER( ti83pse_ctimer1_count_w );
	193	DECLARE_READ8_MEMBER( ti83pse_ctimer2_setup_r );
	194	DECLARE_WRITE8_MEMBER( ti83pse_ctimer2_setup_w );
	195	DECLARE_READ8_MEMBER( ti83pse_ctimer2_loop_r );
	196	DECLARE_WRITE8_MEMBER( ti83pse_ctimer2_loop_w );
	197	DECLARE_READ8_MEMBER( ti83pse_ctimer2_count_r );
	198	DECLARE_WRITE8_MEMBER( ti83pse_ctimer2_count_w );
	199	DECLARE_READ8_MEMBER( ti83pse_ctimer3_setup_r );
	200	DECLARE_WRITE8_MEMBER( ti83pse_ctimer3_setup_w );
	201	DECLARE_READ8_MEMBER( ti83pse_ctimer3_loop_r );
	202	DECLARE_WRITE8_MEMBER( ti83pse_ctimer3_loop_w );
	203	DECLARE_READ8_MEMBER( ti83pse_ctimer3_count_r );
	204	DECLARE_WRITE8_MEMBER( ti83pse_ctimer3_count_w );
	205
	206
106	207	void update_ti85_memory ();
107	208	void update_ti83p_memory ();
	209	void update_ti83pse_memory ();
108	210	void update_ti86_memory ();
109	211	void ti8x_snapshot_setup_registers (UINT8 * data);
110	212	void ti85_setup_snapshot (UINT8 * data);
111	213	void ti86_setup_snapshot (UINT8 * data);
112	214	DECLARE_SNAPSHOT_LOAD_MEMBER( ti8x );
	215
	216	ti83pse_timer m_ctimer[3];
	217
	218	//address_space &asic;
113	219	};
114	220
115	221	#endif /* TI85_H_ */

trunk/src/mess/drivers/ti85.c

r32807	r32808
163	163	10: Control port for the display controller
164	164	11: Data port for the display controller
165	165
	166	TI-83PlusSE ports:
	167	0: Link
	168	1: Keypad
	169	2: ?
	170	3: ON status, LCD power
	171	4: Interrupt status
	172	5: Memory page 3
	173	6: Memory page 1
	174	7: Memory page 2
	175	10: Controll port for the display controller
	176	11: Data port for the display controller
	177	15: Asic Version
	178
166	179	TI-85 ports:
167	180	0: Video buffer offset (write only)
168	181	1: Keypad
r32807	r32808
189	202	#include "cpu/z80/z80.h"
190	203	#include "imagedev/snapquik.h"
191	204	#include "includes/ti85.h"
	205	#include "machine/bankdev.h"
192	206
193	207	/* port i/o functions */
194	208
r32807	r32808
252	266	ADDRESS_MAP_GLOBAL_MASK(0xff)
253	267	AM_RANGE(0x0000, 0x0000) AM_READWRITE(ti8x_plus_serial_r, ti8x_plus_serial_w)
254	268	AM_RANGE(0x0001, 0x0001) AM_READWRITE(ti8x_keypad_r, ti8x_keypad_w )
255		AM_RANGE(0x0002, 0x0002) AM_READWRITE(ti83p_port_0002_r, ti83p_port_0002_w )
256		AM_RANGE(0x0003, 0x0003) AM_READWRITE(ti83_port_0003_r, ti83p_port_0003_w )
257		AM_RANGE(0x0004, 0x0004) AM_READWRITE(ti83_port_0003_r, ti83p_port_0004_w )
	269	AM_RANGE(0x0002, 0x0002) AM_READ(ti83p_port_0002_r)
	270	AM_RANGE(0x0003, 0x0003) AM_READWRITE(ti83_port_0003_r, ti83p_int_mask_w )
	271	AM_RANGE(0x0004, 0x0004) AM_READWRITE(ti83p_port_0004_r, ti83p_port_0004_w )
258	272	AM_RANGE(0x0006, 0x0006) AM_READWRITE(ti86_port_0005_r, ti83p_port_0006_w )
259	273	AM_RANGE(0x0007, 0x0007) AM_READWRITE(ti86_port_0006_r, ti83p_port_0007_w )
260	274	AM_RANGE(0x0010, 0x0010) AM_DEVREADWRITE("t6a04", t6a04_device, control_read, control_write)
261	275	AM_RANGE(0x0011, 0x0011) AM_DEVREADWRITE("t6a04", t6a04_device, data_read, data_write)
	276	AM_RANGE(0x0007, 0x0007) AM_WRITE(ti83p_port_0014_w )
262	277	ADDRESS_MAP_END
263	278
	279	static ADDRESS_MAP_START( ti83pse_io, AS_IO, 8, ti85_state )
	280	ADDRESS_MAP_GLOBAL_MASK(0xff)
	281	AM_RANGE(0x0000, 0x0000) AM_READWRITE(ti8x_plus_serial_r, ti8x_plus_serial_w)
	282	AM_RANGE(0x0001, 0x0001) AM_READWRITE(ti8x_keypad_r, ti8x_keypad_w )
	283	AM_RANGE(0x0002, 0x0002) AM_READWRITE(ti83pse_port_0002_r, ti83pse_int_ack_w )
	284	AM_RANGE(0x0003, 0x0003) AM_READWRITE(ti83_port_0003_r, ti83p_int_mask_w )
	285	AM_RANGE(0x0004, 0x0004) AM_READWRITE(ti83p_port_0004_r, ti83pse_port_0004_w )
	286	AM_RANGE(0x0005, 0x0005) AM_READWRITE(ti83pse_port_0005_r, ti83pse_port_0005_w )
	287	AM_RANGE(0x0006, 0x0006) AM_READWRITE(ti86_port_0005_r, ti83pse_port_0006_w )
	288	AM_RANGE(0x0007, 0x0007) AM_READWRITE(ti86_port_0006_r, ti83pse_port_0007_w )
	289	AM_RANGE(0x0009, 0x0009) AM_READ(ti83pse_port_0009_r)
	290	AM_RANGE(0x0010, 0x0010) AM_DEVREADWRITE("t6a04", t6a04_device, control_read, control_write)
	291	AM_RANGE(0x0011, 0x0011) AM_DEVREADWRITE("t6a04", t6a04_device, data_read, data_write)
	292	AM_RANGE(0x0012, 0x0012) AM_DEVREADWRITE("t6a04", t6a04_device, control_read, control_write)
	293	AM_RANGE(0x0013, 0x0013) AM_DEVREADWRITE("t6a04", t6a04_device, data_read, data_write)
	294	AM_RANGE(0x0014, 0x0014) AM_WRITE(ti83p_port_0014_w )
	295	AM_RANGE(0x0015, 0x0015) AM_READ(ti83pse_port_0015_r)
	296	AM_RANGE(0x0020, 0x0020) AM_READWRITE(ti83pse_port_0020_r, ti83pse_port_0020_w )
	297	AM_RANGE(0x0021, 0x0021) AM_READWRITE(ti83pse_port_0021_r, ti83pse_port_0021_w )
	298
	299	AM_RANGE(0x0030, 0x0030) AM_READWRITE(ti83pse_ctimer1_setup_r, ti83pse_ctimer1_setup_w )
	300	AM_RANGE(0x0031, 0x0031) AM_READWRITE(ti83pse_ctimer1_loop_r, ti83pse_ctimer1_loop_w )
	301	AM_RANGE(0x0032, 0x0032) AM_READWRITE(ti83pse_ctimer1_count_r, ti83pse_ctimer1_count_w )
	302	AM_RANGE(0x0033, 0x0033) AM_READWRITE(ti83pse_ctimer2_setup_r, ti83pse_ctimer2_setup_w )
	303	AM_RANGE(0x0034, 0x0034) AM_READWRITE(ti83pse_ctimer2_loop_r, ti83pse_ctimer2_loop_w )
	304	AM_RANGE(0x0035, 0x0035) AM_READWRITE(ti83pse_ctimer2_count_r, ti83pse_ctimer2_count_w )
	305	AM_RANGE(0x0036, 0x0036) AM_READWRITE(ti83pse_ctimer3_setup_r, ti83pse_ctimer3_setup_w )
	306	AM_RANGE(0x0037, 0x0037) AM_READWRITE(ti83pse_ctimer3_loop_r, ti83pse_ctimer3_loop_w )
	307	AM_RANGE(0x0038, 0x0038) AM_READWRITE(ti83pse_ctimer3_count_r, ti83pse_ctimer3_count_w )
	308
	309	AM_RANGE(0x0055, 0x0055) AM_READ(ti84pse_port_0055_r)
	310	AM_RANGE(0x0056, 0x0056) AM_READ(ti84pse_port_0056_r)
	311	ADDRESS_MAP_END
	312
264	313	static ADDRESS_MAP_START( ti86_io, AS_IO, 8, ti85_state )
265	314	ADDRESS_MAP_GLOBAL_MASK(0xff)
266	315	AM_RANGE(0x0000, 0x0000) AM_READWRITE(ti85_port_0000_r, ti85_port_0000_w )
r32807	r32808
288	337	AM_RANGE(0xc000, 0xffff) AM_RAMBANK("bank4")
289	338	ADDRESS_MAP_END
290	339
	340	static ADDRESS_MAP_START( ti83pse_banked_mem , AS_PROGRAM, 8, ti85_state )
	341	AM_RANGE(0x0000, 0x1fffff) AM_DEVREADWRITE("flash", intelfsh8_device, read, write)
	342	AM_RANGE(0x200000, 0x21BFFF) AM_RAM AM_SHARE("nvram")
	343	ADDRESS_MAP_END
	344
	345	static ADDRESS_MAP_START( ti83p_banked_mem , AS_PROGRAM, 8, ti85_state )
	346	AM_RANGE(0x00000, 0x7ffff) AM_DEVREADWRITE("flash", intelfsh8_device, read, write)
	347	AM_RANGE(0x100000, 0x107fff) AM_RAM AM_SHARE("nvram")
	348	ADDRESS_MAP_END
	349
	350	static ADDRESS_MAP_START( ti83p_asic_mem , AS_PROGRAM, 8, ti85_state )
	351	AM_RANGE(0x0000, 0x3fff) AM_DEVREADWRITE("membank1", address_map_bank_device, read8, write8)
	352	AM_RANGE(0x4000, 0x7fff) AM_DEVREADWRITE("membank2", address_map_bank_device, read8, write8)
	353	AM_RANGE(0x8000, 0xbfff) AM_DEVREADWRITE("membank3", address_map_bank_device, read8, write8)
	354	AM_RANGE(0xc000, 0xffff) AM_DEVREADWRITE("membank4", address_map_bank_device, read8, write8)
	355	ADDRESS_MAP_END
	356
291	357	/* keyboard input */
292	358
293	359	static INPUT_PORTS_START (ti81)
r32807	r32808
428	494	PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("3") PORT_CODE(KEYCODE_3)
429	495	PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("2") PORT_CODE(KEYCODE_2)
430	496	PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("1") PORT_CODE(KEYCODE_1)
431		PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("STORE") PORT_CODE(KEYCODE_TAB)
	497	PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("STORE") PORT_CODE(KEYCODE_S)
432	498	PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("TRACE") PORT_CODE(KEYCODE_F4)
433	499	PORT_START("BIT2")   /* bit 2 */
434	500	PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Right") PORT_CODE(KEYCODE_RIGHT)
r32807	r32808
470	536	PORT_START("BIT7")   /* bit 7 */
471	537	PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("STAT") PORT_CODE(KEYCODE_TILDE)
472	538	PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("x-VAR") PORT_CODE(KEYCODE_X)
473		PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ALPHA") PORT_CODE(KEYCODE_CAPSLOCK)
	539	PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ALPHA") PORT_CODE(KEYCODE_LSHIFT)
474	540	PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("DEL") PORT_CODE(KEYCODE_DEL)
475	541	PORT_START("ON")   /* ON */
476	542	PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ON/OFF") PORT_CODE(KEYCODE_Q)
r32807	r32808
597	663	static MACHINE_CONFIG_DERIVED( ti83p, ti81 )
598	664	MCFG_CPU_MODIFY("maincpu")
599	665	MCFG_CPU_CLOCK(6000000)        /* 8 MHz running at 6 MHz */
600		MCFG_CPU_PROGRAM_MAP(ti86_mem)
	666	MCFG_CPU_PROGRAM_MAP(ti83p_asic_mem)
601	667	MCFG_CPU_IO_MAP(ti83p_io)
602	668
603	669	MCFG_MACHINE_START_OVERRIDE(ti85_state, ti83p )
604		MCFG_MACHINE_RESET_OVERRIDE(ti85_state, ti85 )
	670	MCFG_MACHINE_RESET_OVERRIDE(ti85_state, ti83p )
605	671
606	672	MCFG_SCREEN_MODIFY("screen")
607	673	MCFG_SCREEN_UPDATE_DEVICE("t6a04", t6a04_device, screen_update)
r32807	r32808
610	676	MCFG_PALETTE_ENTRIES(2)
611	677	MCFG_PALETTE_INIT_OWNER(ti85_state, ti82 )
612	678
	679	MCFG_DEVICE_ADD("membank1", ADDRESS_MAP_BANK, 0)
	680	MCFG_DEVICE_PROGRAM_MAP(ti83p_banked_mem)
	681	MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
	682	MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
	683	MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
	684
	685	MCFG_DEVICE_ADD("membank2", ADDRESS_MAP_BANK, 0)
	686	MCFG_DEVICE_PROGRAM_MAP(ti83p_banked_mem)
	687	MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
	688	MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
	689	MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
	690
	691	MCFG_DEVICE_ADD("membank3", ADDRESS_MAP_BANK, 0)
	692	MCFG_DEVICE_PROGRAM_MAP(ti83p_banked_mem)
	693	MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
	694	MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
	695	MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
	696
	697	MCFG_DEVICE_ADD("membank4", ADDRESS_MAP_BANK, 0)
	698	MCFG_DEVICE_PROGRAM_MAP(ti83p_banked_mem)
	699	MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
	700	MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
	701	MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
	702
613	703	MCFG_DEVICE_ADD("t6a04", T6A04, 0)
614	704	MCFG_T6A04_SIZE(96, 64)
615	705
616	706	MCFG_SPEAKER_STANDARD_MONO("mono")
617	707	MCFG_SOUND_ADD("speaker", SPEAKER_SOUND, 0)
618	708	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
	709
	710	MCFG_AMD_29F400T_ADD("flash")
619	711
620	712	//MCFG_TI83PSERIAL_ADD( "tiserial" )
621	713	MACHINE_CONFIG_END
622	714
	715	static MACHINE_CONFIG_DERIVED( ti83pse, ti83p )
	716	MCFG_CPU_MODIFY("maincpu")
	717	MCFG_CPU_CLOCK( 15000000)
	718	MCFG_CPU_IO_MAP(ti83pse_io)
	719
	720	MCFG_DEVICE_MODIFY("membank1")
	721	MCFG_DEVICE_PROGRAM_MAP(ti83pse_banked_mem)
	722
	723	MCFG_DEVICE_MODIFY("membank2")
	724	MCFG_DEVICE_PROGRAM_MAP(ti83pse_banked_mem)
	725
	726	MCFG_DEVICE_MODIFY("membank3")
	727	MCFG_DEVICE_PROGRAM_MAP(ti83pse_banked_mem)
	728
	729	MCFG_DEVICE_MODIFY("membank4")
	730	MCFG_DEVICE_PROGRAM_MAP(ti83pse_banked_mem)
	731
	732	MCFG_MACHINE_START_OVERRIDE(ti85_state, ti83pse )
	733	MCFG_MACHINE_RESET_OVERRIDE(ti85_state, ti83pse )
	734	MCFG_DEVICE_REPLACE("flash", FUJITSU_29F160T, 0)
	735
	736	//MCFG_TI83PSERIAL_ADD( "tiserial" )
	737	MACHINE_CONFIG_END
	738
	739	static MACHINE_CONFIG_DERIVED( ti84p, ti83pse )
	740	MCFG_DEVICE_REPLACE("flash", AMD_29F800T , 0)
	741	//MCFG_TI83PSERIAL_ADD( "tiserial" )
	742	MACHINE_CONFIG_END
	743
	744
623	745	static MACHINE_CONFIG_DERIVED( ti73, ti83p )
624	746	//MCFG_DEVICE_REMOVE( "tiserial" )
625	747	//MCFG_TI73SERIAL_ADD( "tiserial" )
626	748	MACHINE_CONFIG_END
627	749
628	750	ROM_START (ti73)
629		ROM_REGION (0x80000, "bios",0)
	751	ROM_REGION (0x80000, "flash",0)
630	752	ROM_DEFAULT_BIOS("v16")
631	753	ROM_SYSTEM_BIOS( 0, "v16", "V 1.6" )
632	754	ROMX_LOAD( "ti73v160.rom", 0x00000, 0x80000, CRC(bb0e3a16) SHA1(d62c2c7532698962818a747a7f32e35e41dfe338), ROM_BIOS(1) )
r32807	r32808
688	810	ROM_END
689	811
690	812	ROM_START (ti83p)
691		ROM_REGION (0x80000, "bios",0)
	813	ROM_REGION (0x80000, "flash",0)
692	814	ROM_DEFAULT_BIOS("v116")
693	815	ROM_SYSTEM_BIOS( 0, "v103", "V 1.03" )
694	816	ROMX_LOAD( "ti83pv103.bin", 0x00000, 0x80000, CRC(da466be0) SHA1(37eaeeb9fb5c18fb494e322b75070e80cc4d858e), ROM_BIOS(1) )
r32807	r32808
752	874
753	875
754	876	ROM_START (ti83pse)
755		ROM_REGION (0x200000, "bios",0)
	877	ROM_REGION (0x200000, "flash", 0)
756	878	ROM_DEFAULT_BIOS("v116")
757	879	ROM_SYSTEM_BIOS( 0, "v116", "V 1.16" )
758	880	ROMX_LOAD( "ti83psev116.bin", 0x00000, 0x200000, CRC(d2570863) SHA1(d4214b3c0ebb26e10fe95294ac72a90d2ba99537), ROM_BIOS(1) )
759	881	ROM_END
760	882
761	883	ROM_START (ti84pse)
762		ROM_REGION (0x200000, "bios",0)
	884	ROM_REGION (0x200000, "flash",0)
763	885	ROM_DEFAULT_BIOS("v241")
764	886	ROM_SYSTEM_BIOS( 0, "v241", "V 2.41" )
765	887	ROMX_LOAD( "ti84sev241.bin", 0x00000, 0x200000, CRC(5758db36) SHA1(7daa4f22e9b5dc8a1cc8fd31bceece9fa8b43515), ROM_BIOS(1) )
766	888	ROM_END
767	889
	890	ROM_START (ti84p)
	891	ROM_REGION (0x100000, "flash",0)
	892	ROM_DEFAULT_BIOS("v241")
	893	ROM_SYSTEM_BIOS( 0, "v241", "V 2.41" )
	894	ROMX_LOAD( "ti84v241.bin", 0x00000, 0x100000, CRC(5758db36) SHA1(7daa4f22e9b5dc8a1cc8fd31bceece9fa8b43515), ROM_BIOS(1) )
	895	ROM_END
768	896
	897
769	898	/*    YEAR  NAME        PARENT  COMPAT  MACHINE INPUT   INIT   COMPANY                 FULLNAME                        FLAGS */
770	899	COMP( 1990, ti81,       0,      0,      ti81,   ti81, driver_device,   0,     "Texas Instruments",    "TI-81",                        GAME_NO_SOUND )
771	900	COMP( 1992, ti85,       0,      0,      ti85d,  ti85, driver_device,   0,     "Texas Instruments",    "TI-85",                        GAME_NO_SOUND )
r32807	r32808
775	904	COMP( 1997, ti86,       0,      0,      ti86,   ti85, driver_device,   0,     "Texas Instruments",    "TI-86",                        GAME_NO_SOUND )
776	905	COMP( 1998, ti73,       0,      0,      ti73,   ti82, driver_device,   0,     "Texas Instruments",    "TI-73",                        GAME_NO_SOUND )
777	906	COMP( 1999, ti83p,      0,      0,      ti83p,  ti82, driver_device,   0,     "Texas Instruments",    "TI-83 Plus",                   GAME_NO_SOUND )
778		COMP( 2001, ti83pse,    0,      0,      ti85,   ti85, driver_device,   0,     "Texas Instruments",    "TI-83 Plus Silver Edition",    GAME_NOT_WORKING | GAME_NO_SOUND)
779		//COMP( 2004, ti84p,      0,      0,      ti85,   ti85, driver_device,   0,   "Texas Instruments",    "TI-84 Plus",                   GAME_NOT_WORKING | GAME_NO_SOUND)
780		COMP( 2004, ti84pse,    0,      0,      ti85,   ti85, driver_device,   0,     "Texas Instruments",    "TI-84 Plus Silver Edition",    GAME_NOT_WORKING | GAME_NO_SOUND)
	907	COMP( 2001, ti83pse,    0,      0,      ti83pse,   ti82, driver_device,   0,     "Texas Instruments",    "TI-83 Plus Silver Edition", GAME_NO_SOUND )
	908	COMP( 2004, ti84p,      0,      0,      ti84p,   ti82, driver_device,   0,   "Texas Instruments",    "TI-84 Plus",                    GAME_NO_SOUND )
	909	COMP( 2004, ti84pse,    0,      0,      ti83pse,   ti82, driver_device,   0,     "Texas Instruments",    "TI-84 Plus Silver Edition", GAME_NO_SOUND )

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team