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r31654 Thursday 14th August, 2014 at 14:18:28 UTC by Alex Jackson
Implemented the Namco Custom 116 palette and raster IRQ controller as a device, and hooked it up to the namcos1, namconb1 and namcofl drivers [Alex Jackson] digfx.c: Make some members protected instead of private to be less fascistic and more consistent with other device_interfaces.

[src/emu]	digfx.h
[src/mame]	mame.mak
[src/mame/drivers]	namcofl.c namconb1.c namcos1.c
[src/mame/includes]	namcofl.h namconb1.h namcos1.h namcos2.h
[src/mame/video]	c116.c* c116.h* c45.c namcofl.c namconb1.c namcos1.c

trunk/src/mame/includes/namcofl.h

r31653	r31654
1	1	#include "namcos2.h"
	2	#include "video/c116.h"
2	3
3	4	#define NAMCOFL_HTOTAL      (288)   /* wrong */
4	5	#define NAMCOFL_HBSTART (288)
r31653	r31654
22	23	: namcos2_shared_state(mconfig, type, tag),
23	24	m_maincpu(*this,"maincpu"),
24	25	m_mcu(*this,"mcu"),
25		m_shareram(*this, "shareram"),
26		m_generic_paletteram_32(*this, "paletteram"){ }
	26	m_c116(*this,"c116"),
	27	m_shareram(*this, "shareram") { }
27	28
28	29	required_device<cpu_device> m_maincpu;
29	30	required_device<cpu_device> m_mcu;
	31	required_device<namco_c116_device> m_c116;
30	32	emu_timer *m_raster_interrupt_timer;
31	33	UINT32 *m_workram;
32	34	required_shared_ptr<UINT16> m_shareram;
33		required_shared_ptr<UINT32> m_generic_paletteram_32;
34	35	UINT8 m_mcu_port6;
35	36	UINT32 m_sprbank;
36	37
r31653	r31654
38	39	DECLARE_READ32_MEMBER(fl_network_r);
39	40	DECLARE_READ32_MEMBER(namcofl_sysreg_r);
40	41	DECLARE_WRITE32_MEMBER(namcofl_sysreg_w);
41		DECLARE_WRITE32_MEMBER(namcofl_paletteram_w);
	42	DECLARE_WRITE8_MEMBER(namcofl_c116_w);
42	43	DECLARE_READ32_MEMBER(namcofl_share_r);
43	44	DECLARE_WRITE32_MEMBER(namcofl_share_w);
44	45	DECLARE_WRITE16_MEMBER(mcu_shared_w);

trunk/src/mame/includes/namcos1.h

r31653	r31654
1	1	#include "machine/c117.h"
2	2	#include "sound/dac.h"
3	3	#include "sound/namco.h"
	4	#include "video/c116.h"
4	5
5	6	class namcos1_state : public driver_device
6	7	{
r31653	r31654
11	12	m_subcpu(*this, "subcpu"),
12	13	m_audiocpu(*this, "audiocpu"),
13	14	m_mcu(*this, "mcu"),
	15	m_c116(*this, "c116"),
14	16	m_c117(*this, "c117"),
15	17	m_dac(*this, "dac"),
16	18	m_gfxdecode(*this, "gfxdecode"),
17	19	m_palette(*this, "palette"),
18		m_paletteram(*this, "paletteram"),
19	20	m_videoram(*this, "videoram"),
20	21	m_spriteram(*this, "spriteram"),
21	22	m_playfield_control(*this, "pfcontrol"),
r31653	r31654
26	27	required_device<cpu_device> m_subcpu;
27	28	required_device<cpu_device> m_audiocpu;
28	29	required_device<cpu_device> m_mcu;
	30	required_device<namco_c116_device> m_c116;
29	31	required_device<namco_c117_device> m_c117;
30	32	required_device<dac_device> m_dac;
31	33	required_device<gfxdecode_device> m_gfxdecode;
32	34	required_device<palette_device> m_palette;
33	35
34		required_shared_ptr<UINT8> m_paletteram;
35	36	required_shared_ptr<UINT8> m_videoram;
36	37	required_shared_ptr<UINT8> m_spriteram;
37	38	required_shared_ptr<UINT8> m_playfield_control;
r31653	r31654
60	61	int m_strobe;
61	62	int m_strobe_count;
62	63	int m_stored_input[2];
63		UINT8 m_cus116[0x10];
64	64	tilemap_t *m_bg_tilemap[6];
65	65	UINT8 *m_tilemap_maskdata;
66	66	int m_copy_sprites;
r31653	r31654
117	117	void namcos1_update_DACs();
118	118	void namcos1_init_DACs();
119	119	DECLARE_WRITE8_MEMBER( namcos1_videoram_w );
120		DECLARE_WRITE8_MEMBER( namcos1_paletteram_w );
121	120	DECLARE_WRITE8_MEMBER( namcos1_spriteram_w );
122	121	WRITE8_MEMBER( namcos1_3dcs_w );
123	122	READ8_MEMBER( no_key_r );

trunk/src/mame/includes/namconb1.h

r31653	r31654
6	6
7	7	#include "namcos2.h"
8	8	#include "machine/eeprompar.h"
	9	#include "video/c116.h"
9	10
10	11	#define NAMCONB1_HTOTAL     (288)   /* wrong */
11	12	#define NAMCONB1_HBSTART    (288)
r31653	r31654
27	28	public:
28	29	namconb1_state(const machine_config &mconfig, device_type type, const char *tag)
29	30	: namcos2_shared_state(mconfig, type, tag),
30		m_maincpu(*this,"maincpu"),
31		m_mcu(*this,"mcu"),
	31	m_maincpu(*this, "maincpu"),
	32	m_mcu(*this, "mcu"),
	33	m_c116(*this, "c116"),
32	34	m_eeprom(*this, "eeprom"),
33	35	m_spritebank32(*this, "spritebank32"),
34	36	m_tilebank32(*this, "tilebank32"),
35		m_namconb_shareram(*this, "namconb_share"),
36		m_generic_paletteram_32(*this, "paletteram") { }
	37	m_namconb_shareram(*this, "namconb_share") { }
37	38
38	39	required_device<cpu_device> m_maincpu;
39	40	required_device<cpu_device> m_mcu;
	41	required_device<namco_c116_device> m_c116;
40	42	required_device<eeprom_parallel_28xx_device> m_eeprom;
41	43	required_shared_ptr<UINT32> m_spritebank32;
42	44	optional_shared_ptr<UINT32> m_tilebank32;
43	45	required_shared_ptr<UINT16> m_namconb_shareram;
44		required_shared_ptr<UINT32> m_generic_paletteram_32;
45	46
46	47	UINT8 m_vbl_irq_level;
47	48	UINT8 m_pos_irq_level;

trunk/src/mame/includes/namcos2.h

r31653	r31654
352	352	#define NAMCOS21_NUM_COLORS 0x8000
353	353
354	354	/**************************************************************/
355		/*  Shared video palette function handlers                    */
356		/**************************************************************/
357
358		#define VIRTUAL_PALETTE_BANKS 30
359
360		/**************************************************************/
361	355	/*  ROZ - Rotate & Zoom memory function handlers              */
362	356	/**************************************************************/
363	357

trunk/src/mame/mame.mak

r31653	r31654
1517	1517	$(MACHINE)/namco62.o \
1518	1518	$(AUDIO)/namco52.o \
1519	1519	$(AUDIO)/namco54.o \
	1520	$(VIDEO)/c116.o \
1520	1521	$(VIDEO)/c45.o \
1521	1522	$(VIDEO)/bosco.o \
1522	1523	$(VIDEO)/digdug.o \

trunk/src/mame/video/c116.c

r0	r31654
	1	// license:BSD-3-Clause
	2	// copyright-holders:Alex W. Jackson
	3	/*
	4	Namco Custom 116, used in:
	5	System 1
	6	System 2
	7	NB-1/NB-2
	8	System FL
	9
	10	C116 controls palette RAM, blanking/clipping, and generates raster IRQs.
	11	It is paired with one of two priority mixer chips, depending on the board.
	12	On System 1, its partner is Custom 120; on System 2, NB-1, NB-2, and System
	13	FL, its partner is Custom 156. Based on schematics, C156 has more color input
	14	pins than C120 in order to support sprites with higher bit depth; other
	15	differences between the two mixer chips are unknown.
	16
	17	The mixer (C120 or C156) outputs a 13-bit address corresponding to the color
	18	index of the highest-priority input pixel to three 6264 SRAMs, one for each of
	19	red, green and blue. The data from the RAMs is output to C116, which either
	20	sends it to the DAC or clips it to black if the beam position is outside the
	21	visible area programmed via its registers.
	22
	23	When accessing the palette RAM from the CPU, data lines D0-D7 and address lines
	24	A11 and A12 go to C116; these two address lines select between the three RAMs
	25	and the C116 internal registers. A0-A10, A13 and A14 go to C120 or C156, which
	26	simply pass them through to the RAMs (A13 becoming A11 and A14 becoming A12).
	27	Thus, the palette RAM and the C116 registers are laid out like this from the
	28	perspective of the CPU:
	29
	30	0000-07FF: Red   (first 2048 pens)
	31	0800-0FFF: Green ("")
	32	1000-17FF: Blue  ("")
	33	1800-1FFF: C116 registers
	34	2000-27FF: Red   (second 2048 pens)
	35	2800-2FFF: Green ("")
	36	3000-37FF: Blue  ("")
	37	3800-3FFF: C116 registers (mirror)
	38	4000-47FF: Red   (third 2048 pens)
	39	4800-4FFF: Green ("")
	40	5000-57FF: Blue  ("")
	41	5800-5FFF: C116 registers (mirror)
	42	6000-67FF: Red (last 2048 pens)
	43	6800-6FFF: Green ("")
	44	7000-77FF: Blue  ("")
	45	7800-7FFF: C116 registers (mirror)
	46
	47	C116 has six (or eight?) 16-bit registers:
	48
	49	00-01: left clip
	50	02-03: right clip
	51	04-05: top clip
	52	06-07: bottom clip
	53	08-09: raster IRQ horizontal position?
	54	0A-0B: raster IRQ scanline
	55	0C-0D: unknown, some games write 0 here, but probably unused
	56	0E-0F: ""
	57
	58	The registers are mirrored every 0x10 bytes within the address ranges
	59	indicated above.
	60
	61	Although the registers are logically 16-bit, the chip's external interface
	62	is 8-bit, so the registers are written a byte at a time and in a big-endian
	63	fashion (even addresses access the MSB and odd addresses access the LSB)
	64	regardless of the endianness of the CPU. Thus System FL, which has an Intel
	65	i960 CPU, needs to write its clip and raster values byteswapped.
	66	*/
	67
	68	#include "emu.h"
	69	#include "video/c116.h"
	70
	71
	72	//-------------------------------------------------
	73	//  namco_c116_device -- constructor
	74	//-------------------------------------------------
	75
	76	namco_c116_device::namco_c116_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	77	: device_t(mconfig, NAMCO_C116, "Namco C116 Video Controller", tag, owner, clock, "namco_c116", __FILE__),
	78	device_gfx_interface(mconfig, *this),
	79	device_video_interface(mconfig, *this)
	80	{
	81	}
	82
	83
	84	//-------------------------------------------------
	85	//  device_start - device-specific startup
	86	//-------------------------------------------------
	87
	88	void namco_c116_device::device_start()
	89	{
	90	m_ram_r.resize(0x2000);
	91	m_ram_g.resize(0x2000);
	92	m_ram_b.resize(0x2000);
	93	memset(m_regs, 0, sizeof(m_regs));
	94
	95	save_item(NAME(m_ram_r));
	96	save_item(NAME(m_ram_g));
	97	save_item(NAME(m_ram_b));
	98	save_item(NAME(m_regs));
	99	}
	100
	101
	102	READ8_MEMBER(namco_c116_device::read)
	103	{
	104	UINT8 *RAM;
	105
	106	switch (offset & 0x1800)
	107	{
	108	case 0x0000:
	109	RAM = m_ram_r;
	110	break;
	111	case 0x0800:
	112	RAM = m_ram_g;
	113	break;
	114	case 0x1000:
	115	RAM = m_ram_b;
	116	break;
	117	default: // case 0x1800 (internal registers)
	118	{
	119	int reg = (offset & 0xf) >> 1;
	120	if (offset & 1)
	121	return m_regs[reg] & 0xff;
	122	else
	123	return m_regs[reg] >> 8;
	124	}
	125	}
	126
	127	return RAM[((offset & 0x6000) >> 2) | (offset & 0x7ff)];
	128	}
	129
	130
	131	WRITE8_MEMBER(namco_c116_device::write)
	132	{
	133	UINT8 *RAM;
	134
	135	switch (offset & 0x1800)
	136	{
	137	case 0x0000:
	138	RAM = m_ram_r;
	139	break;
	140	case 0x0800:
	141	RAM = m_ram_g;
	142	break;
	143	case 0x1000:
	144	RAM = m_ram_b;
	145	break;
	146	default: // case 0x1800 (internal registers)
	147	{
	148	int reg = (offset & 0xf) >> 1;
	149	if (offset & 1)
	150	m_regs[reg] = (m_regs[reg] & 0xff00) | data;
	151	else
	152	m_regs[reg] = (m_regs[reg] & 0x00ff) | (data << 8);
	153	//printf("reg%d = %d\n", reg, m_regs[reg]);
	154	return;
	155	}
	156	}
	157	int color = ((offset & 0x6000) >> 2) | (offset & 0x7ff);
	158	RAM[color] = data;
	159	m_palette->set_pen_color(color,m_ram_r[color],m_ram_g[color],m_ram_b[color]);
	160	}
	161
	162
	163	const device_type NAMCO_C116 = &device_creator<namco_c116_device>;

Property changes on: trunk/src/mame/video/c116.c

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trunk/src/mame/video/c116.h

r0	r31654
	1	// license:BSD-3-Clause
	2	// copyright-holders:Alex W. Jackson
	3
	4	#pragma once
	5
	6	#ifndef __C116_H__
	7	#define __C116_H__
	8
	9
	10	//***************************************************************************
	11	//  TYPE DEFINITIONS
	12	//***************************************************************************
	13
	14	class namco_c116_device :
	15	public device_t,
	16	public device_gfx_interface,
	17	public device_video_interface
	18	{
	19	public:
	20	//construction/destruction
	21	namco_c116_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	22
	23	//read/write handlers
	24	DECLARE_READ8_MEMBER( read );
	25	DECLARE_WRITE8_MEMBER( write );
	26
	27	//getters
	28	UINT16 get_reg(int reg) { return m_regs[reg]; }
	29
	30	protected:
	31	// device-level overrides
	32	virtual void device_start();
	33
	34	private:
	35	// internal state
	36	dynamic_array<UINT8> m_ram_r;
	37	dynamic_array<UINT8> m_ram_g;
	38	dynamic_array<UINT8> m_ram_b;
	39	UINT16 m_regs[8];
	40	};
	41
	42	extern const device_type NAMCO_C116;
	43
	44	#endif

Property changes on: trunk/src/mame/video/c116.h

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trunk/src/mame/video/namcofl.c

r31653	r31654
45	45	} /* nth_byte32 */
46	46	#endif
47	47
48		static void namcofl_install_palette(running_machine &machine)
49		{
50		namcofl_state *state = machine.driver_data<namcofl_state>();
51		int pen, page, dword_offset, byte_offset;
52		UINT32 r,g,b;
53		UINT32 *pSource;
54
55		/* this is unnecessarily expensive.  Better would be to mark palette entries dirty as
56		* they are modified, and only process those that have changed.
57		*/
58		pen = 0;
59		for( page=0; page<4; page++ )
60		{
61		pSource = &state->m_generic_paletteram_32[page*0x2000/4];
62		for( dword_offset=0; dword_offset<0x800/4; dword_offset++ )
63		{
64		r = pSource[dword_offset+0x0000/4];
65		g = pSource[dword_offset+0x0800/4];
66		b = pSource[dword_offset+0x1000/4];
67
68		for( byte_offset=0; byte_offset<4; byte_offset++ )
69		{
70		state->m_palette->set_pen_color(pen++, r&0xff, g&0xff, b&0xff);
71		r>>=8; g>>=8; b>>=8;
72		}
73		}
74		}
75		}
76	48	static void TilemapCB(running_machine &machine, UINT16 code, int *tile, int *mask )
77	49	{
78	50	*tile = code;
r31653	r31654
84	56	{
85	57	int pri;
86	58
87		namcofl_install_palette(machine());
88
89	59	bitmap.fill(m_palette->black_pen(), cliprect );
90	60
91	61	for( pri=0; pri<16; pri++ )

trunk/src/mame/video/namconb1.c

r31653	r31654
71	71	}
72	72	} /* NB2TilemapCB */
73	73
74		static void namconb1_install_palette(running_machine &machine)
75		{
76		namconb1_state *state = machine.driver_data<namconb1_state>();
77		int pen, page, dword_offset, byte_offset;
78		UINT32 r,g,b;
79		UINT32 *pSource;
80
81		/**
82		* This is unnecessarily expensive.  Better would be to mark palette entries dirty as
83		* they are modified, and only process those that have changed.
84		*/
85		pen = 0;
86		for( page=0; page<4; page++ )
87		{
88		pSource = &state->m_generic_paletteram_32[page*0x2000/4];
89		for( dword_offset=0; dword_offset<0x800/4; dword_offset++ )
90		{
91		r = pSource[dword_offset+0x0000/4];
92		g = pSource[dword_offset+0x0800/4];
93		b = pSource[dword_offset+0x1000/4];
94
95		for( byte_offset=0; byte_offset<4; byte_offset++ )
96		{
97		state->m_palette->set_pen_color(pen++, r>>24, g>>24, b>>24 );
98		r<<=8; g<<=8; b<<=8;
99		}
100		}
101		}
102		} /* namconb1_install_palette */
103
104	74	static void
105	75	video_update_common(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int bROZ )
106	76	{
107	77	namconb1_state *state = screen.machine().driver_data<namconb1_state>();
108	78	int pri;
109		namconb1_install_palette(screen.machine());
110	79
111	80	if( bROZ )
112	81	{
r31653	r31654
137	106	/* compute window for custom screen blanking */
138	107	rectangle clip;
139	108	//004a 016a 0021 0101 0144 0020 (nebulas ray)
140		UINT32 xclip = m_generic_paletteram_32[0x1800/4];
141		UINT32 yclip = m_generic_paletteram_32[0x1804/4];
142		clip.min_x = (xclip>>16)    - 0x4a;
143		clip.max_x = (xclip&0xffff) - 0x4a - 1;
144		clip.min_y = (yclip>>16)    - 0x21;
145		clip.max_y = (yclip&0xffff) - 0x21 - 1;
	109	clip.min_x = m_c116->get_reg(0) - 0x4a;
	110	clip.max_x = m_c116->get_reg(1) - 0x4a - 1;
	111	clip.min_y = m_c116->get_reg(2) - 0x21;
	112	clip.max_y = m_c116->get_reg(3) - 0x21 - 1;
146	113	/* intersect with master clip rectangle */
147	114	clip &= cliprect;
148	115
r31653	r31654
174	141	/* compute window for custom screen blanking */
175	142	rectangle clip;
176	143	//004a016a 00210101 01440020
177		UINT32 xclip = m_generic_paletteram_32[0x1800/4];
178		UINT32 yclip = m_generic_paletteram_32[0x1804/4];
179		clip.min_x = (xclip>>16)    - 0x4b;
180		clip.max_x = (xclip&0xffff) - 0x4b - 1;
181		clip.min_y = (yclip>>16)    - 0x21;
182		clip.max_y = (yclip&0xffff) - 0x21 - 1;
	144	clip.min_x = m_c116->get_reg(0) - 0x4b;
	145	clip.max_x = m_c116->get_reg(1) - 0x4b - 1;
	146	clip.min_y = m_c116->get_reg(2) - 0x21;
	147	clip.max_y = m_c116->get_reg(3) - 0x21 - 1;
183	148	/* intersect with master clip rectangle */
184	149	clip &= cliprect;
185	150

trunk/src/mame/video/namcos1.c

r31653	r31654
125	125	m_bg_tilemap[4]->set_scrolldy(16, 16);
126	126	m_bg_tilemap[5]->set_scrolldy(16, 16);
127	127
128		/* register videoram to the save state system (post-allocation) */
129		save_item(NAME(m_cus116));
130
131	128	/* set table for sprite color == 0x7f */
132	129	for (i = 0;i < 15;i++)
133	130	m_drawmode_table[i] = DRAWMODE_SHADOW;
134	131	m_drawmode_table[15] = DRAWMODE_NONE;
135	132
136		/* clear paletteram */
137		memset(m_paletteram, 0, 0x8000);
138		memset(m_cus116, 0, 0x10);
139		for (i = 0; i < 0x2000; i++)
140		m_palette->set_pen_color(i, rgb_t(0, 0, 0));
141
142	133	/* all palette entries are not affected by shadow sprites... */
143	134	for (i = 0;i < 0x2000;i++)
144	135	m_palette->shadow_table()[i] = i;
r31653	r31654
177	168	}
178	169
179	170
180		WRITE8_MEMBER( namcos1_state::namcos1_paletteram_w )
181		{
182		if (m_paletteram[offset] == data)
183		return;
184
185		if ((offset & 0x1800) != 0x1800)
186		{
187		int r,g,b;
188		int color = ((offset & 0x6000) >> 2) | (offset & 0x7ff);
189
190		m_paletteram[offset] = data;
191
192		offset &= ~0x1800;
193		r = m_paletteram[offset];
194		g = m_paletteram[offset + 0x0800];
195		b = m_paletteram[offset + 0x1000];
196		m_palette->set_pen_color(color,rgb_t(r,g,b));
197		}
198		else
199		{
200		int i, j;
201
202		m_cus116[offset & 0x0f] = data;
203
204		for (i = 0x1800; i < 0x8000; i += 0x2000)
205		{
206		offset = (offset & 0x0f) | i;
207
208		for (j = 0; j < 0x80; j++, offset += 0x10)
209		m_paletteram[offset] = data;
210		}
211		}
212		}
213
214
215
216	171	WRITE8_MEMBER( namcos1_state::namcos1_spriteram_w )
217	172	{
218	173	/* 0000-07ff work ram */
r31653	r31654
335	290	bitmap.fill(m_palette->black_pen(), cliprect);
336	291
337	292	/* berabohm uses asymmetrical visibility windows to iris on the character */
338		i = ((m_cus116[0] << 8) | m_cus116[1]) - 1;         // min x
	293	i = m_c116->get_reg(0) - 1;                         // min x
339	294	if (new_clip.min_x < i) new_clip.min_x = i;
340		i = ((m_cus116[2] << 8) | m_cus116[3]) - 1 - 1;     // max x
	295	i = m_c116->get_reg(1) - 1 - 1;                     // max x
341	296	if (new_clip.max_x > i) new_clip.max_x = i;
342		i = ((m_cus116[4] << 8) | m_cus116[5]) - 0x11;      // min y
	297	i = m_c116->get_reg(2) - 0x11;                      // min y
343	298	if (new_clip.min_y < i) new_clip.min_y = i;
344		i = ((m_cus116[6] << 8) | m_cus116[7]) - 0x11 - 1;  // max y
	299	i = m_c116->get_reg(3) - 0x11 - 1;                  // max y
345	300	if (new_clip.max_y > i) new_clip.max_y = i;
346	301
347	302	if (new_clip.empty())

trunk/src/mame/video/c45.c

r31653	r31654
131	131	WRITE16_MEMBER( namco_c45_road_device::tileram_w )
132	132	{
133	133	COMBINE_DATA(&m_tileram[offset]);
134		gfx(0)->mark_dirty(offset / WORDS_PER_ROAD_TILE);
	134	m_gfx[0]->mark_dirty(offset / WORDS_PER_ROAD_TILE);
135	135	}
136	136
137	137
r31653	r31654
198	198	while (numpixels-- > 0)
199	199	{
200	200	int pen = source_gfx[sourcex >> 16];
201		if (palette()->pen_indirect(pen) != m_transparent_color)
	201	if (m_palette->pen_indirect(pen) != m_transparent_color)
202	202	{
203	203	if (m_clut != NULL)
204	204	pen = (pen & ~0xff) | m_clut[pen & 0xff];

trunk/src/mame/drivers/namcos1.c

r31653	r31654
415	415
416	416	static ADDRESS_MAP_START( virtual_map, AS_PROGRAM, 8, namcos1_state )
417	417	AM_RANGE(0x2c0000, 0x2c1fff) AM_WRITE(namcos1_3dcs_w)
418		AM_RANGE(0x2e0000, 0x2e7fff) AM_RAM_WRITE(namcos1_paletteram_w) AM_SHARE("paletteram")
	418	AM_RANGE(0x2e0000, 0x2e7fff) AM_DEVREADWRITE("c116", namco_c116_device, read, write)
419	419	AM_RANGE(0x2f0000, 0x2f7fff) AM_RAM_WRITE(namcos1_videoram_w) AM_SHARE("videoram")
420	420	AM_RANGE(0x2f8000, 0x2f9fff) AM_READWRITE(no_key_r, no_key_w)
421	421	AM_RANGE(0x2fc000, 0x2fcfff) AM_RAM_WRITE(namcos1_spriteram_w) AM_SHARE("spriteram")
r31653	r31654
1070	1070	MCFG_PALETTE_ADD("palette", 0x2000)
1071	1071	MCFG_PALETTE_ENABLE_SHADOWS()
1072	1072
	1073	MCFG_DEVICE_ADD("c116", NAMCO_C116, 0)
	1074	MCFG_GFX_PALETTE("palette")
	1075
1073	1076	/* sound hardware */
1074	1077	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
1075	1078

trunk/src/mame/drivers/namcofl.c

r31653	r31654
197	197	}
198	198	}
199	199
200		WRITE32_MEMBER(namcofl_state::namcofl_paletteram_w)
	200	// FIXME: remove this trampoline once the IRQ is moved into the actual device
	201	WRITE8_MEMBER(namcofl_state::namcofl_c116_w)
201	202	{
202		COMBINE_DATA(&m_generic_paletteram_32[offset]);
	203	m_c116->write(space, offset, data);
203	204
204		if ((offset == 0x1808/4) && ACCESSING_BITS_16_31)
	205	if ((offset & 0x180e) == 0x180a)
205	206	{
206		UINT16 v = m_generic_paletteram_32[offset] >> 16;
	207	UINT16 v = m_c116->get_reg(5);
207	208	UINT16 triggerscanline=(((v>>8)&0xff)|((v&0xff)<<8))-(32+1);
208	209
209	210	m_raster_interrupt_timer->adjust(m_screen->time_until_pos(triggerscanline));
r31653	r31654
232	233	AM_RANGE(0x30284000, 0x3028bfff) AM_READWRITE(namcofl_share_r, namcofl_share_w)
233	234	AM_RANGE(0x30300000, 0x30303fff) AM_RAM /* COMRAM */
234	235	AM_RANGE(0x30380000, 0x303800ff) AM_READ(fl_network_r ) /* network registers */
235		AM_RANGE(0x30400000, 0x3040ffff) AM_RAM_WRITE(namcofl_paletteram_w) AM_SHARE("paletteram")
	236	AM_RANGE(0x30400000, 0x30407fff) AM_DEVREAD8("c116", namco_c116_device,read,0xffffffff) AM_WRITE8(namcofl_c116_w,0xffffffff)
236	237	AM_RANGE(0x30800000, 0x3080ffff) AM_READWRITE16(c123_tilemap_videoram_r,c123_tilemap_videoram_w,0xffffffff)
237	238	AM_RANGE(0x30a00000, 0x30a0003f) AM_READWRITE16(c123_tilemap_control_r,c123_tilemap_control_w,0xffffffff)
238	239	AM_RANGE(0x30c00000, 0x30c1ffff) AM_READWRITE16(c169_roz_videoram_r,c169_roz_videoram_w,0xffffffff) AM_SHARE("rozvideoram")
r31653	r31654
604	605
605	606	MCFG_GFXDECODE_ADD("gfxdecode", "palette", 2)
606	607
	608	MCFG_DEVICE_ADD("c116", NAMCO_C116, 0)
	609	MCFG_GFX_PALETTE("palette")
	610
607	611	MCFG_VIDEO_START_OVERRIDE(namcofl_state,namcofl)
608	612
609	613	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")

trunk/src/mame/drivers/namconb1.c

r31653	r31654
293	293	}
294	294
295	295	// Handle POSIRQ
296		UINT32 posirq_scanline = (m_generic_paletteram_32[0x1808/4] & 0xffff) - 32;
	296	UINT32 posirq_scanline = m_c116->get_reg(5) - 32;
297	297
298	298	if (scanline == posirq_scanline)
299	299	{
r31653	r31654
667	667	AM_RANGE(0x660000, 0x66003f) AM_READWRITE16(c123_tilemap_control_r,c123_tilemap_control_w,0xffffffff)
668	668	AM_RANGE(0x680000, 0x68000f) AM_RAM AM_SHARE("spritebank32")
669	669	AM_RANGE(0x6e0000, 0x6e001f) AM_READ(custom_key_r) AM_WRITENOP
670		AM_RANGE(0x700000, 0x707fff) AM_RAM AM_SHARE("paletteram")
	670	AM_RANGE(0x700000, 0x707fff) AM_DEVREADWRITE8("c116", namco_c116_device, read, write, 0xffffffff)
671	671	ADDRESS_MAP_END
672	672
673	673	static ADDRESS_MAP_START( namconb2_am, AS_PROGRAM, 32, namconb1_state )
r31653	r31654
684	684	AM_RANGE(0x6c0000, 0x6c003f) AM_READWRITE16(c123_tilemap_control_r,c123_tilemap_control_w,0xffffffff)
685	685	AM_RANGE(0x700000, 0x71ffff) AM_READWRITE16(c169_roz_videoram_r,c169_roz_videoram_w,0xffffffff) AM_SHARE("rozvideoram")
686	686	AM_RANGE(0x740000, 0x74001f) AM_READWRITE16(c169_roz_control_r,c169_roz_control_w,0xffffffff)
687		AM_RANGE(0x800000, 0x807fff) AM_RAM AM_SHARE("paletteram")
	687	AM_RANGE(0x800000, 0x807fff) AM_DEVREADWRITE8("c116", namco_c116_device, read, write, 0xffffffff)
688	688	AM_RANGE(0x900008, 0x90000f) AM_RAM AM_SHARE("spritebank32")
689	689	AM_RANGE(0x940000, 0x94000f) AM_RAM AM_SHARE("tilebank32")
690	690	AM_RANGE(0x980000, 0x98000f) AM_READWRITE16(c169_roz_bank_r,c169_roz_bank_w,0xffffffff)
r31653	r31654
1116	1116	MCFG_SCREEN_PALETTE("palette")
1117	1117
1118	1118	MCFG_GFXDECODE_ADD("gfxdecode", "palette", namconb1)
1119
1120	1119	MCFG_PALETTE_ADD("palette", 0x2000)
1121	1120	MCFG_PALETTE_ENABLE_SHADOWS()
1122	1121
	1122	MCFG_DEVICE_ADD("c116", NAMCO_C116, 0)
	1123	MCFG_GFX_PALETTE("palette")
	1124
1123	1125	MCFG_VIDEO_START_OVERRIDE(namconb1_state,namconb1)
1124	1126
1125	1127	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
r31653	r31654
1154	1156	MCFG_PALETTE_ADD("palette", 0x2000)
1155	1157	MCFG_PALETTE_ENABLE_SHADOWS()
1156	1158
	1159	MCFG_DEVICE_ADD("c116", NAMCO_C116, 0)
	1160	MCFG_GFX_PALETTE("palette")
	1161
1157	1162	MCFG_VIDEO_START_OVERRIDE(namconb1_state,namconb2)
1158	1163
1159	1164	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")

trunk/src/emu/digfx.h

r31653	r31654
212	212	virtual void interface_pre_start();
213	213	virtual void interface_post_start();
214	214
	215	palette_device *            m_palette;                  // pointer to the palette device
	216	auto_pointer<gfx_element>   m_gfx[MAX_GFX_ELEMENTS];    // array of pointers to graphic sets
	217
215	218	private:
216	219	// configuration
217	220	const gfx_decode_entry *    m_gfxdecodeinfo;        // pointer to array of gfx decode information
r31653	r31654
220	223
221	224	// internal state
222	225	bool                        m_decoded;                  // have we processed our decode info yet?
223		palette_device *            m_palette;                  // pointer to the palette device
224		auto_pointer<gfx_element>   m_gfx[MAX_GFX_ELEMENTS];    // array of pointers to graphic sets
225	226	};
226	227
227	228	// iterator

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