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r31653 Thursday 14th August, 2014 at 12:49:17 UTC by Robbbert
hankin.c : more WIP
[src/mame/drivers]by35.c hankin.c
[src/mame/layout]hankin.lay

trunk/src/mame/layout/hankin.lay
r31652r31653
117117      </bezel>
118118
119119      <!-- Credits and Balls -->
120      <bezel name="digit44" element="digit">
120      <bezel name="digit40" element="digit">
121121         <bounds left="39" top="345" right="73" bottom="384" />
122122      </bezel>
123      <bezel name="digit43" element="digit">
123      <bezel name="digit42" element="digit">
124124         <bounds left="110" top="345" right="144" bottom="384" />
125125      </bezel>
126      <bezel name="digit42" element="digit">
126      <bezel name="digit44" element="digit">
127127         <bounds left="171" top="345" right="205" bottom="384" />
128128      </bezel>
129      <bezel name="digit41" element="digit">
129      <bezel name="digit43" element="digit">
130130         <bounds left="210" top="345" right="244" bottom="384" />
131131      </bezel>
132132      <bezel element="P2"><bounds left="100" right="158" top="330" bottom="342" /></bezel>
trunk/src/mame/drivers/hankin.c
r31652r31653
44  Hankin
55  Based on Bally BY35
66
7
8ToDo:
9- High score isn't saved or remembered
10- Sound
11- Inputs
12- Outputs
13- Mechanical
14
715***********************************************************************************/
816
917#include "machine/genpin.h"
r31652r31653
2129      , m_ic10(*this, "ic10")
2230      , m_ic11(*this, "ic11")
2331      , m_ic2(*this, "ic2")
32      , m_io_test(*this, "TEST")
33      , m_io_dsw0(*this, "DSW0")
34      , m_io_dsw1(*this, "DSW1")
35      , m_io_dsw2(*this, "DSW2")
36      , m_io_x0(*this, "X0")
37      , m_io_x1(*this, "X1")
38      , m_io_x2(*this, "X2")
39      , m_io_x3(*this, "X3")
40      , m_io_x4(*this, "X4")
2441   { }
2542
2643   DECLARE_DRIVER_INIT(hankin);
44   DECLARE_WRITE_LINE_MEMBER(ic10_ca2_w);
45   DECLARE_WRITE_LINE_MEMBER(ic11_ca2_w);
46   DECLARE_WRITE8_MEMBER(ic10_a_w);
47   DECLARE_WRITE8_MEMBER(ic11_a_w);
48   DECLARE_READ8_MEMBER(ic11_b_r);
49   DECLARE_INPUT_CHANGED_MEMBER(self_test);
50   TIMER_DEVICE_CALLBACK_MEMBER(timer_x);
2751private:
52   bool m_timer_x;
53   bool m_ic11_ca2;
54   UINT8 m_counter;
55   UINT8 m_digit;
56   UINT8 m_segment;
57   UINT8 m_ic10a;
58   UINT8 m_ic11a;
2859   virtual void machine_reset();
2960   required_device<m6802_cpu_device> m_maincpu;
3061   required_device<m6802_cpu_device> m_audiocpu;
3162   required_device<pia6821_device> m_ic10;
3263   required_device<pia6821_device> m_ic11;
3364   required_device<pia6821_device> m_ic2;
65   required_ioport m_io_test;
66   required_ioport m_io_dsw0;
67   required_ioport m_io_dsw1;
68   required_ioport m_io_dsw2;
69   required_ioport m_io_x0;
70   required_ioport m_io_x1;
71   required_ioport m_io_x2;
72   required_ioport m_io_x3;
73   required_ioport m_io_x4;
3474};
3575
3676
r31652r31653
5191ADDRESS_MAP_END
5292
5393static INPUT_PORTS_START( hankin )
94   PORT_START("TEST")
95   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_NAME("Self Test") PORT_IMPULSE(1) PORT_CHANGED_MEMBER(DEVICE_SELF, hankin_state, self_test, 0)
96
97   PORT_START("DSW0")
98   PORT_DIPNAME( 0x01, 0x00, "S01") // S1-5: 32 combinations of coins/credits of a coin slot. S9-13 other slot.
99   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
100   PORT_DIPSETTING(    0x01, DEF_STR( On ))
101   PORT_DIPNAME( 0x02, 0x00, "S02")
102   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
103   PORT_DIPSETTING(    0x02, DEF_STR( On ))
104   PORT_DIPNAME( 0x04, 0x00, "S03")
105   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
106   PORT_DIPSETTING(    0x04, DEF_STR( On ))
107   PORT_DIPNAME( 0x08, 0x00, "S04")
108   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
109   PORT_DIPSETTING(    0x08, DEF_STR( On ))
110   PORT_DIPNAME( 0x10, 0x00, "S05")
111   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
112   PORT_DIPSETTING(    0x10, DEF_STR( On ))
113   PORT_DIPNAME( 0x20, 0x20, "S06")
114   PORT_DIPSETTING(    0x00, DEF_STR( No ))
115   PORT_DIPSETTING(    0x20, DEF_STR( Yes ))
116   PORT_DIPNAME( 0x40, 0x40, "S07")
117   PORT_DIPSETTING(    0x00, DEF_STR( No ))
118   PORT_DIPSETTING(    0x40, DEF_STR( Yes ))
119   PORT_DIPNAME( 0x80, 0x80, "S08")
120   PORT_DIPSETTING(    0x00, DEF_STR( No ))
121   PORT_DIPSETTING(    0x80, DEF_STR( Yes ))
122
123   PORT_START("DSW1")
124   PORT_DIPNAME( 0x01, 0x00, "S09")
125   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
126   PORT_DIPSETTING(    0x01, DEF_STR( On ))
127   PORT_DIPNAME( 0x02, 0x00, "S10")
128   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
129   PORT_DIPSETTING(    0x02, DEF_STR( On ))
130   PORT_DIPNAME( 0x04, 0x00, "S11")
131   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
132   PORT_DIPSETTING(    0x04, DEF_STR( On ))
133   PORT_DIPNAME( 0x08, 0x00, "S12")
134   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
135   PORT_DIPSETTING(    0x08, DEF_STR( On ))
136   PORT_DIPNAME( 0x10, 0x00, "S13")
137   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
138   PORT_DIPSETTING(    0x10, DEF_STR( On ))
139   PORT_DIPNAME( 0x20, 0x00, "S14")
140   PORT_DIPSETTING(    0x00, DEF_STR( Yes ))
141   PORT_DIPSETTING(    0x20, DEF_STR( No ))
142   PORT_DIPNAME( 0x40, 0x40, "S15")
143   PORT_DIPSETTING(    0x00, DEF_STR( No ))
144   PORT_DIPSETTING(    0x40, DEF_STR( Yes ))
145   PORT_DIPNAME( 0x80, 0x00, "S16")
146   PORT_DIPSETTING(    0x00, DEF_STR( No ))
147   PORT_DIPSETTING(    0x80, DEF_STR( Yes ))
148
149   PORT_START("DSW2")
150   PORT_DIPNAME( 0x01, 0x00, "S17")
151   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
152   PORT_DIPSETTING(    0x01, DEF_STR( On ))
153   PORT_DIPNAME( 0x02, 0x00, "S18")
154   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
155   PORT_DIPSETTING(    0x02, DEF_STR( On ))
156   PORT_DIPNAME( 0x04, 0x00, "S19")
157   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
158   PORT_DIPSETTING(    0x04, DEF_STR( On ))
159   PORT_DIPNAME( 0x08, 0x00, "S20")
160   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
161   PORT_DIPSETTING(    0x08, DEF_STR( On ))
162   PORT_DIPNAME( 0x10, 0x00, "S21")
163   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
164   PORT_DIPSETTING(    0x10, DEF_STR( On ))
165   PORT_DIPNAME( 0x20, 0x00, "S22")
166   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
167   PORT_DIPSETTING(    0x20, DEF_STR( On ))
168   PORT_DIPNAME( 0x40, 0x00, "S23")
169   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
170   PORT_DIPSETTING(    0x40, DEF_STR( On ))
171   PORT_DIPNAME( 0x80, 0x00, "S24")
172   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
173   PORT_DIPSETTING(    0x80, DEF_STR( On ))
174
175   PORT_START("DSW3")
176   PORT_DIPNAME( 0x03, 0x03, "Maximum Credits")
177   PORT_DIPSETTING(    0x00, "10")
178   PORT_DIPSETTING(    0x01, "15")
179   PORT_DIPSETTING(    0x02, "25")
180   PORT_DIPSETTING(    0x03, "40")
181   PORT_DIPNAME( 0x04, 0x04, "Credits displayed")
182   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
183   PORT_DIPSETTING(    0x04, DEF_STR( On ))
184   PORT_DIPNAME( 0x08, 0x08, "Match")
185   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
186   PORT_DIPSETTING(    0x08, DEF_STR( On ))
187   PORT_DIPNAME( 0x10, 0x00, "Keep all replays")
188   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
189   PORT_DIPSETTING(    0x10, DEF_STR( On ))
190   PORT_DIPNAME( 0x20, 0x00, "Voice" )
191   PORT_DIPSETTING(    0x00, DEF_STR( Off ))
192   PORT_DIPSETTING(    0x20, DEF_STR( On ))
193   PORT_DIPNAME( 0xC0, 0x40, "Balls")
194   PORT_DIPSETTING(    0xC0, "2")
195   PORT_DIPSETTING(    0x00, "3")
196   PORT_DIPSETTING(    0x80, "4")
197   PORT_DIPSETTING(    0x40, "5")
198
199   PORT_START("X0")
200   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OTHER )
201   PORT_BIT( 0x0a, IP_ACTIVE_HIGH, IPT_UNUSED )
202   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_START2 )
203   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OTHER )
204   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_START1 )
205   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_TILT )
206   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Outhole") PORT_CODE(KEYCODE_X)
207
208   PORT_START("X1")
209   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN2 )
210   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN1 )
211   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_COIN3 )
212   PORT_BIT( 0x38, IP_ACTIVE_HIGH, IPT_UNUSED )
213   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_OTHER )
214   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_TILT1 ) PORT_NAME("Slam Tilt")
215
216   // from here, vary per game
217   PORT_START("X2")
218   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_A)
219   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_S)
220   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_D)
221   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_F)
222   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_G)
223   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_H)
224   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_J)
225   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_K)
226
227   PORT_START("X3")
228   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_Q)
229   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_W)
230   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_E)
231   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_R)
232   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_Y)
233   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_U)
234   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_I)
235   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_O)
236
237   PORT_START("X4")
238   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_Z)
239   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_C)
240   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_V)
241   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_B)
242   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_N)
243   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_M)
244   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_COMMA)
245   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_STOP)
54246INPUT_PORTS_END
55247
248INPUT_CHANGED_MEMBER( hankin_state::self_test )
249{
250   m_ic11->ca1_w(newval);
251}
252
253WRITE8_MEMBER( hankin_state::ic10_a_w )
254{
255   m_ic10a = data;
256   //m_digit = 0xff;
257
258   if (!m_ic11_ca2)
259   {
260      if BIT(data, 2)
261         m_digit = 5;
262      else
263      if BIT(data, 3)
264         m_digit = 4;
265      else
266      if BIT(data, 4)
267         m_digit = 3;
268      else
269      if BIT(data, 5)
270         m_digit = 2;
271      else
272      if BIT(data, 6)
273         m_digit = 1;
274      else
275      if BIT(data, 7)
276         m_digit = 0;
277
278      m_counter++;
279   }
280}
281
282WRITE_LINE_MEMBER( hankin_state::ic10_ca2_w )
283{
284   output_set_value("led0", !state);
285}
286
287WRITE8_MEMBER( hankin_state::ic11_a_w )
288{
289   static const UINT8 patterns[16] = { 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f,0,0,0,0,0,0 }; // MC14543
290   m_ic11a = data;
291
292   if (!m_ic11_ca2)
293   {
294      if (m_counter==3)
295         output_set_digit_value(m_digit, patterns[m_segment]);
296
297      m_counter++;
298      m_segment = data >> 4;
299
300      if (m_counter==4)
301         output_set_digit_value(10+m_digit, patterns[m_segment]);
302      else
303      if (m_counter==6)
304         output_set_digit_value(20+m_digit, patterns[m_segment]);
305      else
306      if (m_counter==8)
307         output_set_digit_value(30+m_digit, patterns[m_segment]);
308      else
309      if (m_counter==10)
310         output_set_digit_value(40+m_digit, patterns[m_segment]);
311   }
312}
313
314READ8_MEMBER( hankin_state::ic11_b_r )
315{
316   UINT8 data = 0;
317
318   if (BIT(m_ic11a, 0))
319      data |= m_io_x0->read();
320
321   if (BIT(m_ic11a, 1))
322      data |= m_io_x1->read();
323
324   if (BIT(m_ic11a, 2))
325      data |= m_io_x2->read();
326
327   if (BIT(m_ic11a, 3))
328      data |= m_io_x3->read();
329
330   if (BIT(m_ic11a, 4))
331      data |= m_io_x4->read();
332
333   if (BIT(m_ic11a, 5))
334      data |= m_io_dsw0->read();
335
336   if (BIT(m_ic11a, 6))
337      data |= m_io_dsw1->read();
338
339   if (BIT(m_ic11a, 7))
340      data |= m_io_dsw2->read();
341
342   return data;
343}
344
345WRITE_LINE_MEMBER( hankin_state::ic11_ca2_w )
346{
347   m_ic11_ca2 = state;
348   if (!state)
349      m_counter = 0;
350}
351     
352// zero-cross detection
353TIMER_DEVICE_CALLBACK_MEMBER( hankin_state::timer_x )
354{
355   m_timer_x ^= 1;
356   m_ic11->cb1_w(m_timer_x);
357}
358
56359void hankin_state::machine_reset()
57360{
58361}
r31652r31653
80383   /* Devices */
81384   MCFG_DEVICE_ADD("ic10", PIA6821, 0)
82385   //MCFG_PIA_READPA_HANDLER(READ8(hankin_state, ic10_a_r))
83   //MCFG_PIA_WRITEPA_HANDLER(WRITE8(hankin_state, ic10_a_w))
386   MCFG_PIA_WRITEPA_HANDLER(WRITE8(hankin_state, ic10_a_w))
84387   //MCFG_PIA_READPB_HANDLER(READ8(hankin_state, ic10_b_r))
85388   //MCFG_PIA_WRITEPB_HANDLER(WRITE8(hankin_state, ic10_b_w))
86   //MCFG_PIA_CA2_HANDLER(WRITELINE(hankin_state, ic10_ca2_w))
389   MCFG_PIA_CA2_HANDLER(WRITELINE(hankin_state, ic10_ca2_w))
87390   //MCFG_PIA_CB2_HANDLER(WRITELINE(hankin_state, ic10_cb2_w))
88391   MCFG_PIA_IRQA_HANDLER(DEVWRITELINE("maincpu", m6802_cpu_device, irq_line))
89392   MCFG_PIA_IRQB_HANDLER(DEVWRITELINE("maincpu", m6802_cpu_device, irq_line))
90393
91394   MCFG_DEVICE_ADD("ic11", PIA6821, 0)
92395   //MCFG_PIA_READPA_HANDLER(READ8(hankin_state, ic11_a_r))
93   //MCFG_PIA_WRITEPA_HANDLER(WRITE8(hankin_state, ic11_a_w))
94   //MCFG_PIA_READPB_HANDLER(READ8(hankin_state, ic11_b_r))
396   MCFG_PIA_WRITEPA_HANDLER(WRITE8(hankin_state, ic11_a_w))
397   MCFG_PIA_READPB_HANDLER(READ8(hankin_state, ic11_b_r))
95398   //MCFG_PIA_WRITEPB_HANDLER(WRITE8(hankin_state, ic11_b_w))
96   //MCFG_PIA_CA2_HANDLER(WRITELINE(hankin_state, ic11_ca2_w))
399   MCFG_PIA_CA2_HANDLER(WRITELINE(hankin_state, ic11_ca2_w))
97400   //MCFG_PIA_CB2_HANDLER(WRITELINE(hankin_state, ic11_cb2_w))
98401   MCFG_PIA_IRQA_HANDLER(DEVWRITELINE("maincpu", m6802_cpu_device, irq_line))
99402   MCFG_PIA_IRQB_HANDLER(DEVWRITELINE("maincpu", m6802_cpu_device, irq_line))
r31652r31653
107410   //MCFG_PIA_CB2_HANDLER(WRITELINE(hankin_state, ic2_cb2_w))
108411   MCFG_PIA_IRQA_HANDLER(DEVWRITELINE("audiocpu", m6802_cpu_device, irq_line))
109412   MCFG_PIA_IRQB_HANDLER(DEVWRITELINE("audiocpu", m6802_cpu_device, irq_line))
413
414   MCFG_TIMER_DRIVER_ADD_PERIODIC("timer_x", hankin_state, timer_x, attotime::from_hz(120)) // mains freq*2
110415MACHINE_CONFIG_END
111416
112417/*--------------------------------
trunk/src/mame/drivers/by35.c
r31652r31653
309309{
310310   m_u10_ca2 = state;
311311}
312     
312
313313WRITE_LINE_MEMBER( by35_state::u10_cb2_w )
314314{
315315}

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