trunk/src/emu/cpu/tms7000/tms7000.c
| r31424 | r31425 | |
| 23 | 23 | * - memory modes with IOCNT0, currently always running in full expansion mode |
| 24 | 24 | * - timer event counter mode (timer control register, bit 6) |
| 25 | 25 | * - TMS70x1/2 serial port and timer 3 |
| 26 | * - TMS70C46 external memory mode is via "E" bus instead of configuring IOCNT0 |
| 26 | 27 | * - TMS70C46 clock divider (don't know which part of the memorymap is slow) |
| 27 | 28 | * - TMS70C46 INT3 on keypress |
| 28 | 29 | * - when they're needed, add TMS70Cx2, TMS7742, TMS77C82, SE70xxx |
| r31424 | r31425 | |
| 118 | 119 | AM_IMPORT_FROM( tms7002_mem ) |
| 119 | 120 | ADDRESS_MAP_END |
| 120 | 121 | |
| 121 | | static ADDRESS_MAP_START(tms70c46_io, AS_IO, 8, tms70c46_device) |
| 122 | | AM_RANGE(TMS7000_PORTC, TMS7000_PORTC) AM_WRITE(e_bus_address_lo_w) |
| 123 | | AM_RANGE(TMS7000_PORTD, TMS7000_PORTD) AM_WRITE(e_bus_address_hi_w) |
| 124 | | AM_IMPORT_FROM( tms7000_io ) |
| 125 | | ADDRESS_MAP_END |
| 126 | | |
| 127 | 122 | static ADDRESS_MAP_START(tms70c46_mem, AS_PROGRAM, 8, tms70c46_device ) |
| 128 | 123 | AM_RANGE(0x010c, 0x010c) AM_READWRITE(e_bus_data_r, e_bus_data_w) |
| 129 | 124 | // AM_RANGE(0x010d, 0x010d) --> to outside --> DOCK-BUS available |
| r31424 | r31425 | |
| 139 | 134 | : cpu_device(mconfig, TMS7000, "TMS7000", tag, owner, clock, "tms7000", __FILE__), |
| 140 | 135 | m_program_config("program", ENDIANNESS_BIG, 8, 16, 0, ADDRESS_MAP_NAME(tms7000_mem)), |
| 141 | 136 | m_io_config("io", ENDIANNESS_BIG, 8, 8, 0, ADDRESS_MAP_NAME(tms7000_io)), |
| 142 | | m_data_config("data", ENDIANNESS_BIG, 8, 16, 0), |
| 143 | 137 | m_info_flags(0) |
| 144 | 138 | { |
| 145 | 139 | } |
| r31424 | r31425 | |
| 148 | 142 | : cpu_device(mconfig, type, name, tag, owner, clock, shortname, source), |
| 149 | 143 | m_program_config("program", ENDIANNESS_BIG, 8, 16, 0, internal), |
| 150 | 144 | m_io_config("io", ENDIANNESS_BIG, 8, 8, 0, ADDRESS_MAP_NAME(tms7000_io)), |
| 151 | | m_data_config("data", ENDIANNESS_BIG, 8, 16, 0), |
| 152 | 145 | m_info_flags(info_flags) |
| 153 | 146 | { |
| 154 | 147 | } |
| r31424 | r31425 | |
| 206 | 199 | tms70c46_device::tms70c46_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) |
| 207 | 200 | : tms7000_device(mconfig, TMS70C46, "TMS70C46", tag, owner, clock, ADDRESS_MAP_NAME(tms70c46_mem), TMS7000_CHIP_IS_CMOS, "tms70c46", __FILE__) |
| 208 | 201 | { |
| 209 | | m_io_config = address_space_config("io", ENDIANNESS_BIG, 8, 8, 0, ADDRESS_MAP_NAME(tms70c46_io)); |
| 210 | 202 | } |
| 211 | 203 | |
| 212 | 204 | |
| r31424 | r31425 | |
| 220 | 212 | m_program = &space(AS_PROGRAM); |
| 221 | 213 | m_direct = &m_program->direct(); |
| 222 | 214 | m_io = &space(AS_IO); |
| 223 | | m_data = &space(AS_DATA); |
| 224 | 215 | |
| 225 | 216 | m_icountptr = &m_icount; |
| 226 | 217 | |
| r31424 | r31425 | |
| 906 | 897 | void tms70c46_device::device_start() |
| 907 | 898 | { |
| 908 | 899 | // init/zerofill |
| 909 | | m_e_bus_address = 0; |
| 910 | 900 | m_control = 0; |
| 911 | 901 | |
| 912 | 902 | // register for savestates |
| 913 | | save_item(NAME(m_e_bus_address)); |
| 914 | 903 | save_item(NAME(m_control)); |
| 915 | 904 | |
| 916 | 905 | tms7000_device::device_start(); |
| 917 | 906 | } |
| 918 | 907 | |
| 908 | void tms70c46_device::device_reset() |
| 909 | { |
| 910 | m_control = 0; |
| 911 | m_io->write_byte(TMS7000_PORTE, 0xff); |
| 912 | |
| 913 | tms7000_device::device_reset(); |
| 914 | } |
| 915 | |
| 919 | 916 | READ8_MEMBER(tms70c46_device::control_r) |
| 920 | 917 | { |
| 921 | 918 | return m_control; |
| r31424 | r31425 | |
| 924 | 921 | WRITE8_MEMBER(tms70c46_device::control_w) |
| 925 | 922 | { |
| 926 | 923 | // d5: enable external databus |
| 924 | if (~m_control & data & 0x20) |
| 925 | m_io->write_byte(TMS7000_PORTE, 0xff); // go into high impedance |
| 926 | |
| 927 | 927 | // d4: enable clock divider when accessing slow memory |
| 928 | 928 | // d0-d3: clock divider |
| 929 | 929 | m_control = data; |
trunk/src/emu/cpu/tms7000/tms7000.h
| r31424 | r31425 | |
| 88 | 88 | virtual void execute_set_input(int extline, int state); |
| 89 | 89 | |
| 90 | 90 | // device_memory_interface overrides |
| 91 | | virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ) ); } |
| 91 | virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); } |
| 92 | 92 | |
| 93 | 93 | // device_state_interface overrides |
| 94 | 94 | void state_string_export(const device_state_entry &entry, astring &string); |
| r31424 | r31425 | |
| 102 | 102 | |
| 103 | 103 | address_space_config m_program_config; |
| 104 | 104 | address_space_config m_io_config; |
| 105 | | address_space_config m_data_config; // TMS70C46 only, the "E" bus |
| 106 | 105 | |
| 107 | 106 | UINT32 m_info_flags; |
| 108 | 107 | |
| 109 | 108 | address_space *m_program; |
| 110 | 109 | direct_read_data *m_direct; |
| 111 | 110 | address_space *m_io; |
| 112 | | address_space *m_data; |
| 113 | 111 | int m_icount; |
| 114 | 112 | |
| 115 | 113 | bool m_irq_state[2]; |
| r31424 | r31425 | |
| 316 | 314 | DECLARE_READ8_MEMBER(control_r); |
| 317 | 315 | DECLARE_WRITE8_MEMBER(control_w); |
| 318 | 316 | |
| 319 | | // extra 64KB external memory bus, or extra i/o port |
| 320 | | DECLARE_WRITE8_MEMBER(e_bus_address_lo_w) { m_e_bus_address = (m_e_bus_address & 0xff00) | data; } |
| 321 | | DECLARE_WRITE8_MEMBER(e_bus_address_hi_w) { m_e_bus_address = (m_e_bus_address & 0x00ff) | data << 8; } |
| 322 | | DECLARE_READ8_MEMBER(e_bus_data_r) { return (space.debugger_access()) ? 0 : ((m_control & 0x20) ? m_data->read_byte(m_e_bus_address) : m_io->read_byte(TMS7000_PORTE)); } |
| 323 | | DECLARE_WRITE8_MEMBER(e_bus_data_w) { if (m_control & 0x20) m_data->write_byte(m_e_bus_address, data); else m_io->write_byte(TMS7000_PORTE, data); } |
| 317 | // access I/O port E if databus is disabled |
| 318 | DECLARE_READ8_MEMBER(e_bus_data_r) { return (space.debugger_access()) ? 0xff : ((m_control & 0x20) ? 0xff : m_io->read_byte(TMS7000_PORTE)); } |
| 319 | DECLARE_WRITE8_MEMBER(e_bus_data_w) { if (~m_control & 0x20) m_io->write_byte(TMS7000_PORTE, data); } |
| 324 | 320 | |
| 325 | 321 | protected: |
| 326 | 322 | // device-level overrides |
| 327 | 323 | virtual void device_start(); |
| 324 | virtual void device_reset(); |
| 328 | 325 | |
| 329 | 326 | private: |
| 330 | | UINT16 m_e_bus_address; |
| 331 | 327 | UINT8 m_control; |
| 332 | 328 | }; |
| 333 | 329 | |
trunk/src/mess/drivers/ti74.c
| r31424 | r31425 | |
| 285 | 285 | AM_RANGE(TMS7000_PORTE, TMS7000_PORTE) AM_WRITE(keyboard_w) AM_READNOP |
| 286 | 286 | ADDRESS_MAP_END |
| 287 | 287 | |
| 288 | | static ADDRESS_MAP_START( e_map, AS_DATA, 8, ti74_state ) |
| 289 | | ADDRESS_MAP_END |
| 290 | 288 | |
| 291 | 289 | |
| 292 | | |
| 293 | 290 | /*************************************************************************** |
| 294 | 291 | |
| 295 | 292 | Inputs |
| r31424 | r31425 | |
| 490 | 487 | |
| 491 | 488 | // zerofill |
| 492 | 489 | m_key_select = 0; |
| 493 | | m_power = 0; |
| 490 | m_power = 1; |
| 494 | 491 | |
| 495 | 492 | // register for savestates |
| 496 | 493 | save_item(NAME(m_key_select)); |
| r31424 | r31425 | |
| 503 | 500 | MCFG_CPU_ADD("maincpu", TMS70C46, XTAL_4MHz) |
| 504 | 501 | MCFG_CPU_PROGRAM_MAP(main_map) |
| 505 | 502 | MCFG_CPU_IO_MAP(main_io_map) |
| 506 | | MCFG_CPU_DATA_MAP(e_map) |
| 507 | 503 | |
| 508 | 504 | MCFG_NVRAM_ADD_0FILL("6264.ic3") |
| 509 | 505 | |
| r31424 | r31425 | |
| 539 | 535 | MCFG_CPU_ADD("maincpu", TMS70C46, XTAL_4MHz) |
| 540 | 536 | MCFG_CPU_PROGRAM_MAP(main_map) |
| 541 | 537 | MCFG_CPU_IO_MAP(main_io_map) |
| 542 | | MCFG_CPU_DATA_MAP(e_map) |
| 543 | 538 | |
| 544 | 539 | MCFG_NVRAM_ADD_0FILL("6264.ic3") |
| 545 | 540 | |