Previous

199869 Revisions

Next

r31424 Friday 25th July, 2014 at 21:15:25 UTC by Roberto Fresca
Changed set mpoker and driver to mgames. Also description from Multi-Poker to Match Games accordingly with the official flyer. http://flyers.arcade-museum.com/?page=thumbs&db=videodb&id=6500 In fact, these are skill instead of poker games. Also added way more documentation and some cosmetic fixes. [Roberto Fresca]

[src/mame]	mame.lst mame.mak
[src/mame/drivers]	mgames.c* mpoker.c
[src/mame/layout]	mgames.lay* mpoker.lay

trunk/src/mame/layout/mpoker.lay

r31423	r31424
1		<?xml version="1.0"?>
2		<mamelayout version="2">
3		<element name="L1" defstate="1">
4		<rect state="1">
5		<color red="1.0" green="1.0" blue="1.0" />
6		</rect>
7		<rect state="0">
8		<color red="0.3" green="0.3" blue="0.3" />
9		</rect>
10		<text string="BET">
11		<color red="0.0" green="0.0" blue="0.0" />
12		<bounds x="0" y="0.2" width="1" height="0.6" />
13		</text>
14		</element>
15
16		<element name="L2" defstate="1">
17		<rect state="1">
18		<color red="1.0" green="1.0" blue="1.0" />
19		</rect>
20		<rect state="0">
21		<color red="0.3" green="0.3" blue="0.3" />
22		</rect>
23		<text string="DEAL">
24		<color red="0.0" green="0.0" blue="0.0" />
25		<bounds x="0" y="0.2" width="1" height="0.6" />
26		</text>
27		</element>
28
29		<element name="L3" defstate="1">
30		<rect state="1">
31		<color red="1.0" green="1.0" blue="1.0" />
32		</rect>
33		<rect state="0">
34		<color red="0.3" green="0.3" blue="0.3" />
35		</rect>
36		<text string="CANCEL">
37		<color red="0.0" green="0.0" blue="0.0" />
38		<bounds x="0" y="0.2" width="1" height="0.6" />
39		</text>
40		</element>
41
42		<element name="L4" defstate="1">
43		<rect state="1">
44		<color red="1.0" green="1.0" blue="1.0" />
45		</rect>
46		<rect state="0">
47		<color red="0.3" green="0.3" blue="0.3" />
48		</rect>
49		<text string="STAND">
50		<color red="0.0" green="0.0" blue="0.0" />
51		<bounds x="0" y="0.2" width="1" height="0.6" />
52		</text>
53		</element>
54
55		<element name="L5" defstate="1">
56		<rect state="1">
57		<color red="1.0" green="0.0" blue="0.0" />
58		</rect>
59		<rect state="0">
60		<color red="0.3" green="0.0" blue="0.0" />
61		</rect>
62		<text string="HOLD1">
63		<color red="0.0" green="0.0" blue="0.0" />
64		<bounds x="0" y="0.2" width="1" height="0.6" />
65		</text>
66		</element>
67
68		<element name="L6" defstate="1">
69		<rect state="1">
70		<color red="1.0" green="0.0" blue="0.0" />
71		</rect>
72		<rect state="0">
73		<color red="0.3" green="0.0" blue="0.0" />
74		</rect>
75		<text string="HOLD2">
76		<color red="0.0" green="0.0" blue="0.0" />
77		<bounds x="0" y="0.2" width="1" height="0.6" />
78		</text>
79		</element>
80
81		<element name="L7" defstate="1">
82		<rect state="1">
83		<color red="1.0" green="0.0" blue="0.0" />
84		</rect>
85		<rect state="0">
86		<color red="0.3" green="0.0" blue="0.0" />
87		</rect>
88		<text string="HOLD3">
89		<color red="0.0" green="0.0" blue="0.0" />
90		<bounds x="0" y="0.2" width="1" height="0.6" />
91		</text>
92		</element>
93
94		<element name="L8" defstate="1">
95		<rect state="1">
96		<color red="1.0" green="0.0" blue="0.0" />
97		</rect>
98		<rect state="0">
99		<color red="0.3" green="0.0" blue="0.0" />
100		</rect>
101		<text string="HOLD4">
102		<color red="0.0" green="0.0" blue="0.0" />
103		<bounds x="0" y="0.2" width="1" height="0.6" />
104		</text>
105		</element>
106
107		<element name="L9" defstate="1">
108		<rect state="1">
109		<color red="1.0" green="0.0" blue="0.0" />
110		</rect>
111		<rect state="0">
112		<color red="0.3" green="0.0" blue="0.0" />
113		</rect>
114		<text string="HOLD5">
115		<color red="0.0" green="0.0" blue="0.0" />
116		<bounds x="0" y="0.2" width="1" height="0.6" />
117		</text>
118		</element>
119
120		<view name="Button Lamps">
121		<screen index="0">
122		<bounds left="0" top="0" right="4" bottom="3" />
123		</screen>
124		<bezel name="lamp1" element="L1">
125		<bounds x="0" y="3.13" width="0.35" height="0.24" />
126		</bezel>
127		<bezel name="lamp2" element="L2">
128		<bounds x="0.4" y="3.13" width="0.35" height="0.24" />
129		</bezel>
130		<bezel name="lamp3" element="L3">
131		<bounds x="0.8" y="3.13" width="0.35" height="0.24" />
132		</bezel>
133		<bezel name="lamp4" element="L4">
134		<bounds x="1.2" y="3.13" width="0.35" height="0.24" />
135		</bezel>
136
137		<bezel name="lamp5" element="L5">
138		<bounds x="2.05" y="3.13" width="0.35" height="0.24" />
139		</bezel>
140		<bezel name="lamp6" element="L6">
141		<bounds x="2.45" y="3.13" width="0.35" height="0.24" />
142		</bezel>
143		<bezel name="lamp7" element="L7">
144		<bounds x="2.85" y="3.13" width="0.35" height="0.24" />
145		</bezel>
146		<bezel name="lamp8" element="L8">
147		<bounds x="3.25" y="3.13" width="0.35" height="0.24" />
148		</bezel>
149		<bezel name="lamp9" element="L9">
150		<bounds x="3.65" y="3.13" width="0.35" height="0.24" />
151		</bezel>
152		</view>
153		</mamelayout>

trunk/src/mame/layout/mgames.lay

r0	r31424
	1	<?xml version="1.0"?>
	2	<mamelayout version="2">
	3	<element name="L1" defstate="1">
	4	<rect state="1">
	5	<color red="1.0" green="1.0" blue="1.0" />
	6	</rect>
	7	<rect state="0">
	8	<color red="0.3" green="0.3" blue="0.3" />
	9	</rect>
	10	<text string="BET">
	11	<color red="0.0" green="0.0" blue="0.0" />
	12	<bounds x="0" y="0.2" width="1" height="0.6" />
	13	</text>
	14	</element>
	15
	16	<element name="L2" defstate="1">
	17	<rect state="1">
	18	<color red="1.0" green="1.0" blue="1.0" />
	19	</rect>
	20	<rect state="0">
	21	<color red="0.3" green="0.3" blue="0.3" />
	22	</rect>
	23	<text string="DEAL">
	24	<color red="0.0" green="0.0" blue="0.0" />
	25	<bounds x="0" y="0.2" width="1" height="0.6" />
	26	</text>
	27	</element>
	28
	29	<element name="L3" defstate="1">
	30	<rect state="1">
	31	<color red="1.0" green="1.0" blue="1.0" />
	32	</rect>
	33	<rect state="0">
	34	<color red="0.3" green="0.3" blue="0.3" />
	35	</rect>
	36	<text string="CANCEL">
	37	<color red="0.0" green="0.0" blue="0.0" />
	38	<bounds x="0" y="0.2" width="1" height="0.6" />
	39	</text>
	40	</element>
	41
	42	<element name="L4" defstate="1">
	43	<rect state="1">
	44	<color red="1.0" green="1.0" blue="1.0" />
	45	</rect>
	46	<rect state="0">
	47	<color red="0.3" green="0.3" blue="0.3" />
	48	</rect>
	49	<text string="STAND">
	50	<color red="0.0" green="0.0" blue="0.0" />
	51	<bounds x="0" y="0.2" width="1" height="0.6" />
	52	</text>
	53	</element>
	54
	55	<element name="L5" defstate="1">
	56	<rect state="1">
	57	<color red="1.0" green="0.0" blue="0.0" />
	58	</rect>
	59	<rect state="0">
	60	<color red="0.3" green="0.0" blue="0.0" />
	61	</rect>
	62	<text string="HOLD1">
	63	<color red="0.0" green="0.0" blue="0.0" />
	64	<bounds x="0" y="0.2" width="1" height="0.6" />
	65	</text>
	66	</element>
	67
	68	<element name="L6" defstate="1">
	69	<rect state="1">
	70	<color red="1.0" green="0.0" blue="0.0" />
	71	</rect>
	72	<rect state="0">
	73	<color red="0.3" green="0.0" blue="0.0" />
	74	</rect>
	75	<text string="HOLD2">
	76	<color red="0.0" green="0.0" blue="0.0" />
	77	<bounds x="0" y="0.2" width="1" height="0.6" />
	78	</text>
	79	</element>
	80
	81	<element name="L7" defstate="1">
	82	<rect state="1">
	83	<color red="1.0" green="0.0" blue="0.0" />
	84	</rect>
	85	<rect state="0">
	86	<color red="0.3" green="0.0" blue="0.0" />
	87	</rect>
	88	<text string="HOLD3">
	89	<color red="0.0" green="0.0" blue="0.0" />
	90	<bounds x="0" y="0.2" width="1" height="0.6" />
	91	</text>
	92	</element>
	93
	94	<element name="L8" defstate="1">
	95	<rect state="1">
	96	<color red="1.0" green="0.0" blue="0.0" />
	97	</rect>
	98	<rect state="0">
	99	<color red="0.3" green="0.0" blue="0.0" />
	100	</rect>
	101	<text string="HOLD4">
	102	<color red="0.0" green="0.0" blue="0.0" />
	103	<bounds x="0" y="0.2" width="1" height="0.6" />
	104	</text>
	105	</element>
	106
	107	<element name="L9" defstate="1">
	108	<rect state="1">
	109	<color red="1.0" green="0.0" blue="0.0" />
	110	</rect>
	111	<rect state="0">
	112	<color red="0.3" green="0.0" blue="0.0" />
	113	</rect>
	114	<text string="HOLD5">
	115	<color red="0.0" green="0.0" blue="0.0" />
	116	<bounds x="0" y="0.2" width="1" height="0.6" />
	117	</text>
	118	</element>
	119
	120	<view name="Button Lamps">
	121	<screen index="0">
	122	<bounds left="0" top="0" right="4" bottom="3" />
	123	</screen>
	124	<bezel name="lamp1" element="L1">
	125	<bounds x="0" y="3.13" width="0.35" height="0.24" />
	126	</bezel>
	127	<bezel name="lamp2" element="L2">
	128	<bounds x="0.4" y="3.13" width="0.35" height="0.24" />
	129	</bezel>
	130	<bezel name="lamp3" element="L3">
	131	<bounds x="0.8" y="3.13" width="0.35" height="0.24" />
	132	</bezel>
	133	<bezel name="lamp4" element="L4">
	134	<bounds x="1.2" y="3.13" width="0.35" height="0.24" />
	135	</bezel>
	136
	137	<bezel name="lamp5" element="L5">
	138	<bounds x="2.05" y="3.13" width="0.35" height="0.24" />
	139	</bezel>
	140	<bezel name="lamp6" element="L6">
	141	<bounds x="2.45" y="3.13" width="0.35" height="0.24" />
	142	</bezel>
	143	<bezel name="lamp7" element="L7">
	144	<bounds x="2.85" y="3.13" width="0.35" height="0.24" />
	145	</bezel>
	146	<bezel name="lamp8" element="L8">
	147	<bounds x="3.25" y="3.13" width="0.35" height="0.24" />
	148	</bezel>
	149	<bezel name="lamp9" element="L9">
	150	<bounds x="3.65" y="3.13" width="0.35" height="0.24" />
	151	</bezel>
	152	</view>
	153	</mamelayout>

Property changes on: trunk/src/mame/layout/mgames.lay

Added: svn:mime-type    + text/xml Added: svn:eol-style    + native

trunk/src/mame/drivers/mpoker.c

r31423	r31424
1		// license:?
2		// copyright-holders:Angelo Salese, Roberto Fresca,David Haywood
3		/*********************************************************************************
4
5		Merit Industries Multi-Poker (1981)
6		-----------------------------------
7
8		Driver by Angelo Salese, David Haywood & Roberto Fresca.
9
10		Maybe the first Merit videopoker.
11		The system has 4 different themed videopokers selectable through DIP switches:
12
13		* "The Frog Pond"
14		* "Pharaohs"
15		* "Wild Bulls"
16		* "The White Knight"
17
18		**********************************************************************************
19
20		Hardware Notes:
21		---------------
22
23		1x OSC = 18.000 MHz.
24		1x CPU = Zilog Z80 (Z0840006PSC / 9512 / 2K).
25		4x 74LS253N (multiplexers).
26		4x MM2114N-3 (4096-Bit Static RAM).
27		2x SCM5101E (256x4 Static RAM).
28
29		The PCB has a socket for two standard AA batteries
30
31
32		MAIN BOARD:
33		_________________________   ___________________   __________________________
34		|                         |_|||||||||||||||||||||_|                          |
35		|                                  J2                       -|4.7 Ohm 10% |- |
36		|                                                            |____________|  |
37		|                                                                            |
38		|         DSW (8)                 _|___|___|___|_               LM340K-5     |
39		|                                |   |   |   |   |              7805K        |
40		|                                | 4x4700uF 16V  |    KBL005                 |
41		|                                |   |   |   |   |     8137                  |
42		|                                |   |   |   |   |      AC                   |
43		|                                |___|___|___|___|                           |
44		|                                  |   |   |   |                             |
45		|                                                                            |
46		|    74LS253N  74LS253N 74LS253N 74LS253                                     |
47		|                                                _____________               |
48		|                                               | 4700uF 35V  |   MC7812CT   |
49		|                                              -|  Capacitor  |-             |
50		|                                               |_____________|              |
51		|                                                                            |
52		|                                                                            |
53		|                _____________________                                       |
54		|               |    B A T T E R Y    |                                -     |
55		|  _            |_____________________|                    74LS04N     -     |
56		| | |                                                                  - J1  |
57		| | |       74LS04N  74LS02N  74LS74N   74LS02N 74LS132N               -     |
58		| | |                                                                  -     |
59		| | |       74LS138N 74LS08N    7416N   74LS10N 74LS161N   74123N      -     |
60		| | |                                                                  -     |
61		| |J|       74LS00N  74LS11N  74LS161N 74LS157N 74LS161N    7416N            |
62		| |4|                                                                        |
63		| | |       74LS02N  74LS32N  74LS259N 74LS151N  74LS11N             LED     |
64		| | |                                                18.000 OSC              |
65		| | |                74LS367N 74LS161N 74LS161N  74LS04N    DM7404N          |
66		| | |                                                                        |
67		| | |        74LS245PC             _________     74LS74N    LM3302N          |
68		| | |                             | Z80 CPU |                                |
69		| | |        74LS245PC            |___U1____|   MM2114N-3  74LS174N 74LS166J |
70		| | |                                                                 _____  |
71		| |_|        74LS138N       74LS245PC 74LS245PC MM2114N-3  74LS157N  |_U68_| |
72		|                                                                            |
73		|            SCM5101E                 74LS245PC MM2114N-3  74LS174N   _____  |
74		|                             _____                                  |_U67_| |
75		|            SCM5101E        |_U18_|  74LS157N  MM2114N-3  74LS138N   _____  |
76		|     _____    _____          _____                                  |_U66_| |
77		|    |_U16_|  |_U13_|        |_U19_|  74LS157N             74LS161N          |
78		|     _____    _____          _____                                   _____  |
79		|    |_U15_|  |_U14_|        |_U17_|  74LS157N             74LS157N  |_U65_| |
80		|                                                                            |
81		|____________________________________________________________________________|
82
83
84		U13 = MLTI 0    U68 = CGM 0
85		U14 = MLTI 1    U67 = CGM 1
86		U15 = MLTI 2    U66 = CGM 2
87		U16 = MLTI 3    U65 = CGM 3
88		U17 = MLTI 4    U1 = Zilog Z0840006PSC Z80 CPU 9512 2K
89		U18 = MLTI 5
90
91		J4 = Conn to video I/O board
92		J1 = Jumpers bank? (see multiplexed port)
93
94
95		VIDEO I/O BOARD CRT810:
96		____________________
97		_______________________|||||||||||||||||||||______________________
98		|                                                                  |
99		|                                                          LM380N  |
100		|                                                                  |
101		|                                                          MC1455P |
102		|                                                                  |
103		|                                                                  |
104		| SW 7407-N    SW 7407-N    SW 7407-N    SW 7407-N                 |
105		| 21430 7301   21430 7301   21430 7301   21430 7301                |
106		|                                                                  |
107		| 74LS259N     74LS259N     74LS259N     74LS259N                  |
108		|                                                                  |
109		|________________                                  ________________|
110		||||||||||||||||||||||||||||||||||
111		---------------------------------
112		To J4 on Main Board
113
114		LM380N = 2.5W Audio Power Amplifier.
115		MC1455P = Direct Replacement for NE555 Timers.
116
117		(Audio seems to be discrete).
118
119		4x 7407N (Buffer Gates Non-Inverting).
120		4x 74LS259N (8-Bit Addressable Latches).
121
122		4x 7301 (HDSP?)(RED Seven Segment Displays).
123
124		+---------+  Pin | Description
125		|    A    |  ----+------------
126		|   ---   |   01 | Anode (4).
127		| F|   |B |   02 | Cathode F.
128		|   -G-   |   03 | Cathode G.
129		| E|   |C |   04 | Cathode E.
130		|   ---   |   05 | Cathode D.
131		|    D .DP|   06 | Anode (4).
132		+---------+   07 | Cathode DP.
133		08 | Cathode C.
134		09 | Cathode B.
135		10 | Cathode A.
136
137
138		**********************************************************************************
139
140		Dev Notes:
141		----------
142
143		Additional work:
144
145		* Full Inputs.
146		* DIP Switches.
147		* Simulated spark-watchdog circuitery.
148		* Demuxed custom port.
149		* NVRAM support.
150		* CPU clock derived from #defined crystal.
151		* 8000-8007 Output ports.
152		* Coin related counters.
153		* Sound components and trigger found at 8000-8003, bit2.
154		* Full lamps support.
155		* PCBs layouts & technical notes.
156
157		Todo:
158
159		- Writes to offset 0x0158 (so many!)
160
161		- Still analyze 8000-8007 offset range remaining bits.
162		These writes sounds like a BCD valueset.
163		Maybe were intended formerly to send some data to 7seg display unit.
164
165		- Color system (no bipolar PROMs in the system), needs a reference
166
167
168		**********************************************************************************/
169
170		#define MASTER_CLOCK    XTAL_18MHz
171
172		#include "emu.h"
173		#include "cpu/z80/z80.h"
174		//#include "sound/dac.h"
175		#include "machine/nvram.h"
176		#include "mpoker.lh"
177
178
179		class mpoker_state : public driver_device
180		{
181		public:
182		mpoker_state(const machine_config &mconfig, device_type type, const char *tag)
183		: driver_device(mconfig, type, tag),
184		m_video(*this, "video"),
185		m_maincpu(*this, "maincpu"),
186		m_gfxdecode(*this, "gfxdecode"),
187		m_palette(*this, "palette") { }
188
189		UINT8 m_output[8];
190		required_shared_ptr<UINT8> m_video;
191		int m_mixdata;
192		DECLARE_READ8_MEMBER(mixport_r);
193		DECLARE_WRITE8_MEMBER(muxed_w);
194		DECLARE_WRITE8_MEMBER(outport0_w);
195		DECLARE_WRITE8_MEMBER(outport1_w);
196		DECLARE_WRITE8_MEMBER(outport2_w);
197		DECLARE_WRITE8_MEMBER(outport3_w);
198		DECLARE_WRITE8_MEMBER(outport4_w);
199		DECLARE_WRITE8_MEMBER(outport5_w);
200		DECLARE_WRITE8_MEMBER(outport6_w);
201		DECLARE_WRITE8_MEMBER(outport7_w);
202		DECLARE_WRITE8_MEMBER(sound_w);
203		virtual void video_start();
204		DECLARE_PALETTE_INIT(mpoker);
205		UINT32 screen_update_mpoker(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
206		required_device<cpu_device> m_maincpu;
207		required_device<gfxdecode_device> m_gfxdecode;
208		required_device<palette_device> m_palette;
209		};
210
211
212		void mpoker_state::video_start()
213		{
214		}
215
216		UINT32 mpoker_state::screen_update_mpoker(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
217		{
218		int y,x;
219		int count;
220		gfx_element *gfx = m_gfxdecode->gfx(0);
221
222		count = 0;
223		for (y=0;y<32;y++)
224		{
225		for (x=0;x<32;x++)
226		{
227		UINT16 dat = m_video[count];
228		UINT16 col = m_video[count+0x400] & 0x7f;
229		gfx->opaque(bitmap,cliprect,dat,col,0,0,x*16,y*16);
230		count++;
231		}
232
233		}
234		return 0;
235		}
236
237		PALETTE_INIT_MEMBER(mpoker_state, mpoker)
238		{
239		int i;
240
241		for (i = 0; i < 0x100; i++)
242		{
243		rgb_t color;
244
245		if (i & 0x01)
246		color = rgb_t(pal2bit((i & 0x6) >> 1),pal2bit((i & 0x18) >> 3),pal2bit((i & 0x60) >> 5));
247		else
248		color = rgb_t::black;
249
250		palette.set_pen_color(i, color);
251		}
252		}
253
254		READ8_MEMBER(mpoker_state::mixport_r)
255		{
256		/*  - bits -
257		7654 3210
258		---- ---x   Unknown.
259		---- --x-   Spark-Watchdog...
260		---- -x--   DIP Switch Bank #2.
261		---- x---   DIP Switch Bank #2.
262		---x ----   DIP Switch Bank #2.
263		xxx- ----   Unknown.
264
265		Spark-Watchdog... The system expect status changes on bit1, otherwise stop the hardware with an error message.
266		The line seems to be tied to a clock. We can't use XORed status due to the nested checks.
267		If you change the status *every* read, the HW stucks.
268		*/
269
270		m_mixdata = (ioport("SW2")->read() & 0xfd) | (machine().rand() & 0x02);
271
272		return m_mixdata;
273		}
274
275		/***** Port 0158 *****
276
277		- bits -
278		7654 3210
279		---- ---x   Unknown.
280		---- --x-   Unknown.
281		---- -x--   Unknown.
282		---- x---   Unknown.
283		---x ----   Unknown.
284		xxx- ----   Unknown.
285		*/
286
287		//WRITE8_MEMBER(mpoker_state::muxed_w)
288		//{
289		//  popmessage("written : %02X %02X %02X %02X %02X %02X %02X %02X", data & 0x01, data & 0x02, data & 0x04, data & 0x08, data & 0x10, data & 0x20, data & 0x40, data & 0x80);
290		//}
291
292		/***** Port 8000 *****
293
294		- bits -
295		7654 3210
296		---- ---x   BET lamp.
297		---- --x-   HOLD1 lamp.
298		---- -x--   Sound component #1.
299		---- x---   Unknown.
300		---x ----   Unknown.
301		xxx- ----   Unknown.
302		*/
303
304		WRITE8_MEMBER(mpoker_state::outport0_w)
305		{
306		output_set_lamp_value(1, (data & 1));           /* Lamp 1 - BET */
307		output_set_lamp_value(5, (data >> 1) & 1);      /* Lamp 5 - HOLD 1 */
308
309		m_output[0] = data;
310		popmessage("outport0 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
311		}
312
313		/***** Port 8001 *****
314
315		- bits -
316		7654 3210
317		---- ---x   DEAL lamp.
318		---- --x-   HOLD2 lamp.
319		---- -x--   Sound component #2.
320		---- x---   Unknown.
321		---x ----   Unknown.
322		xxx- ----   Unknown.
323		*/
324
325		WRITE8_MEMBER(mpoker_state::outport1_w)
326		{
327		output_set_lamp_value(2, (data & 1));           /* Lamp 2 - DEAL */
328		output_set_lamp_value(6, (data >> 1) & 1);      /* Lamp 6 - HOLD 2 */
329
330		m_output[1] = data;
331		popmessage("outport1 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
332		}
333
334		/***** Port 8002 *****
335
336		- bits -
337		7654 3210
338		---- ---x   CANCEL lamp.
339		---- --x-   HOLD3 lamp.
340		---- -x--   Sound component #3.
341		---- x---   Unknown.
342		---x ----   Unknown.
343		xxx- ----   Unknown.
344		*/
345
346		WRITE8_MEMBER(mpoker_state::outport2_w)
347		{
348		output_set_lamp_value(3, (data & 1));           /* Lamp 3 - CANCEL */
349		output_set_lamp_value(7, (data >> 1) & 1);      /* Lamp 7 - HOLD 3 */
350
351		m_output[2] = data;
352		popmessage("outport2 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
353		}
354
355		/***** Port 8003 *****
356
357		- bits -
358		7654 3210
359		---- ---x   Unknown lamp.
360		---- --x-   HOLD4 lamp.
361		---- -x--   Sound trigger.
362		---- x---   Unknown.
363		---x ----   Unknown.
364		xxx- ----   Unknown.
365		*/
366
367		WRITE8_MEMBER(mpoker_state::outport3_w)
368		{
369		output_set_lamp_value(4, (data & 1));           /* Lamp 4 - STAND */
370		output_set_lamp_value(8, (data >> 1) & 1);      /* Lamp 8 - HOLD 4 */
371
372		m_output[3] = data;
373		popmessage("outport3 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
374		}
375
376		/***** Port 8004 *****
377
378		- bits -
379		7654 3210
380		---- ---x   Unknown.
381		---- --x-   HOLD5 lamp.
382		---- -x--   Unknown.
383		---- x---   Unknown.
384		---x ----   Unknown.
385		xxx- ----   Unknown.
386		*/
387
388		WRITE8_MEMBER(mpoker_state::outport4_w)
389		{
390		output_set_lamp_value(9, (data >> 1) & 1);      /* Lamp 9 - HOLD 5 */
391
392		m_output[4] = data;
393		popmessage("outport4 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
394		}
395
396		/***** Port 8005 *****
397
398		- bits -
399		7654 3210
400		---- ---x   Unknown.
401		---- --x-   Unknown.
402		---- -x--   Unknown.
403		---- x---   Unknown.
404		---x ----   Unknown.
405		xxx- ----   Unknown.
406		*/
407
408		WRITE8_MEMBER(mpoker_state::outport5_w)
409		{
410		m_output[5] = data;
411		popmessage("outport5 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
412		}
413
414		/***** Port 8006 *****
415
416		- bits -
417		7654 3210
418		---- ---x   Unknown.
419		---- --x-   Payout pulse.
420		---- -x--   Unknown.
421		---- x---   Unknown.
422		---x ----   Unknown.
423		xxx- ----   Unknown.
424		*/
425
426		WRITE8_MEMBER(mpoker_state::outport6_w)
427		{
428		coin_counter_w(machine(), 1, data & 0x02);  /* Payout pulse */
429
430		m_output[6] = data;
431		popmessage("outport6 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
432		}
433
434		/***** Port 8007 *****
435
436		- bits -
437		7654 3210
438		---- ---x   Unknown.
439		---- --x-   Coin pulse.
440		---- -x--   Unknown.
441		---- x---   Unknown.
442		---x ----   Unknown.
443		xxx- ----   Unknown.
444		*/
445
446		WRITE8_MEMBER(mpoker_state::outport7_w)
447		{
448		coin_counter_w(machine(), 0, data & 0x02);  /* Coin pulse */
449
450		m_output[7] = data;
451		popmessage("outport7 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
452		}
453
454
455		/********  Discrete Sound  ********
456
457		There are 3 components plus a trigger:
458
459		Component #1 = $8000, bit2.
460		Component #2 = $8001, bit2.
461		Component #3 = $8002, bit2.
462
463		Trigger = $8003, bit2.
464
465		All bits are inverted.
466
467
468		Sound | 8000 | 8001 | 8002 | 8003
469		------+------+------+------+-----
470		01   | bit2 | bit2 | bit2 | bit2
471		02   | ---- | bit2 | bit2 | bit2
472		03   | bit2 | ---- | bit2 | bit2
473		04   | bit2 | bit2 | ---- | bit2
474		05   | ---- | ---- | ---- | bit2
475
476
477		WRITE8_MEMBER(mpoker_state::sound_w)
478		//{
479		//  m_dac->write_unsigned8(data);
480		//}
481		*/
482
483		static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, mpoker_state )
484		AM_RANGE(0x0000, 0x2fff) AM_ROM
485		//  AM_RANGE(0x0158, 0x0158) AM_WRITE (muxed_w)
486		AM_RANGE(0x3800, 0x38ff) AM_RAM AM_SHARE("nvram")   /* NVRAM = 2x SCM5101E */
487		AM_RANGE(0x4000, 0x47ff) AM_RAM AM_SHARE("video")   /* 4x MM2114N-3 */
488		AM_RANGE(0x8000, 0x8000) AM_READ_PORT("SW1")
489		AM_RANGE(0x8001, 0x8001) AM_READ(mixport_r) /* DIP switch bank 2 + a sort of watchdog */
490		AM_RANGE(0x8002, 0x8002) AM_READ_PORT("IN1")
491		AM_RANGE(0x8003, 0x8003) AM_READ_PORT("IN2")
492		AM_RANGE(0x8000, 0x8000) AM_WRITE(outport0_w)
493		AM_RANGE(0x8001, 0x8001) AM_WRITE(outport1_w)
494		AM_RANGE(0x8002, 0x8002) AM_WRITE(outport2_w)
495		AM_RANGE(0x8003, 0x8003) AM_WRITE(outport3_w)
496		AM_RANGE(0x8004, 0x8004) AM_WRITE(outport4_w)
497		AM_RANGE(0x8005, 0x8005) AM_WRITE(outport5_w)
498		AM_RANGE(0x8006, 0x8006) AM_WRITE(outport6_w)
499		AM_RANGE(0x8007, 0x8007) AM_WRITE(outport7_w)
500
501		ADDRESS_MAP_END
502
503		static INPUT_PORTS_START( mpoker )
504		PORT_START("IN1")
505		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_GAMBLE_BET )
506		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_GAMBLE_DEAL )
507		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_POKER_CANCEL ) PORT_NAME("Cancel Discards")
508		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Stand (Hold all Cards)")
509		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_POKER_HOLD1 ) PORT_NAME("Discard 1")
510		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_POKER_HOLD2 ) PORT_NAME("Discard 2")
511		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_POKER_HOLD3 ) PORT_NAME("Discard 3")
512		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_POKER_HOLD4 ) PORT_NAME("Discard 4")
513
514		PORT_START("IN2")
515		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_POKER_HOLD5 ) PORT_NAME("Discard 5")
516		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_GAMBLE_BOOK ) PORT_NAME("Stats")
517		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_GAMBLE_PAYOUT )
518		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
519		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2)
520		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_GAMBLE_SERVICE ) PORT_NAME("Settings")
521		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
522		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
523
524		PORT_START("SW1")
525		PORT_DIPNAME( 0x0f, 0x0f, DEF_STR( Coin_A ) )
526		PORT_DIPSETTING(    0x00, "20 Coins/1 Credit" )
527		PORT_DIPSETTING(    0x01, "10 Coins/1 Credit" )
528		PORT_DIPSETTING(    0x02, DEF_STR( 8C_1C ) )
529		PORT_DIPSETTING(    0x03, DEF_STR( 5C_1C ) )
530		PORT_DIPSETTING(    0x04, DEF_STR( 4C_1C ) )
531		PORT_DIPSETTING(    0x05, "5 Coins/2 Credits" )
532		PORT_DIPSETTING(    0x06, DEF_STR( 2C_1C ) )
533		//  PORT_DIPSETTING(    0x07, DEF_STR( 1C_1C ) ) --> damn check... you can't set 2 different bits pointing to the same coinage.
534		PORT_DIPSETTING(    0x0f, DEF_STR( 1C_1C ) )
535		PORT_DIPSETTING(    0x0e, DEF_STR( 1C_2C ) )
536		PORT_DIPSETTING(    0x0d, DEF_STR( 2C_5C ) )
537		PORT_DIPSETTING(    0x0c, DEF_STR( 1C_4C ) )
538		PORT_DIPSETTING(    0x0b, DEF_STR( 1C_5C ) )
539		PORT_DIPSETTING(    0x0a, DEF_STR( 1C_8C ) )
540		PORT_DIPSETTING(    0x09, "1 Coin/10 Credits" )
541		PORT_DIPSETTING(    0x08, "1 Coin/20 Credits" )
542		PORT_DIPNAME( 0x30, 0x30, "Game Select" )
543		PORT_DIPSETTING(    0x00, "The White Knight" )
544		PORT_DIPSETTING(    0x10, "Wild Bulls" )
545		PORT_DIPSETTING(    0x20, "Pharaohs" )
546		PORT_DIPSETTING(    0x30, "The Frog Pond" )
547		PORT_DIPNAME( 0xc0, 0xc0, "Maximun Bet" )
548		PORT_DIPSETTING(    0x40, "1" )
549		PORT_DIPSETTING(    0xc0, "10" )
550		PORT_DIPSETTING(    0x80, "20" )
551		PORT_DIPSETTING(    0x00, "50" )
552
553		PORT_START("SW2")
554		PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
555		PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
556		PORT_DIPSETTING(    0x00, DEF_STR( On ) )
557		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER )      /* bit1 connected to a signal heartbeat */
558		PORT_DIPNAME( 0x1c, 0x0c, "Main Percentage" )
559		PORT_DIPSETTING(    0x18, "75%" )
560		PORT_DIPSETTING(    0x14, "80%" )
561		PORT_DIPSETTING(    0x00, "85%" )
562		PORT_DIPSETTING(    0x0c, "90%" )
563		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
564		PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
565		PORT_DIPSETTING(    0x00, DEF_STR( On ) )
566		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
567		PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
568		PORT_DIPSETTING(    0x00, DEF_STR( On ) )
569		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
570		PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
571		PORT_DIPSETTING(    0x00, DEF_STR( On ) )
572
573		INPUT_PORTS_END
574
575
576		static const gfx_layout tiles16x16_layout =
577		{
578		16,16,
579		RGN_FRAC(1,1),
580		1,
581		{ 0 },
582		{ 0, 1, 2, 3, 4, 5, 6, 7,8,9,10,11,12,13,14,15 },
583		{ 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16,
584		8*16, 9*16,10*16,11*16,12*16,13*16,14*16,15*16},
585		16*16
586		};
587
588		static GFXDECODE_START( mpoker )
589		GFXDECODE_ENTRY( "gfx1", 0, tiles16x16_layout, 0, 0x100 )
590		GFXDECODE_END
591
592		static MACHINE_CONFIG_START( mpoker, mpoker_state )
593		/* basic machine hardware */
594		MCFG_CPU_ADD("maincpu", Z80,MASTER_CLOCK/6)      /* 3 MHz? */
595		MCFG_CPU_PROGRAM_MAP(main_map)
596		MCFG_CPU_VBLANK_INT_DRIVER("screen", mpoker_state,  irq0_line_hold)
597
598		MCFG_NVRAM_ADD_0FILL("nvram")
599
600		/* video hardware */
601		MCFG_SCREEN_ADD("screen", RASTER)
602		MCFG_SCREEN_REFRESH_RATE(60)
603		MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
604		MCFG_SCREEN_SIZE(512, 256)
605		MCFG_SCREEN_VISIBLE_AREA(0, 512-1, 0, 256-1)
606		MCFG_SCREEN_UPDATE_DRIVER(mpoker_state, screen_update_mpoker)
607		MCFG_SCREEN_PALETTE("palette")
608
609		MCFG_GFXDECODE_ADD("gfxdecode", "palette", mpoker)
610		MCFG_PALETTE_ADD("palette", 0x200)
611		MCFG_PALETTE_INIT_OWNER(mpoker_state, mpoker)
612
613		/* sound hardware */
614		//  MCFG_SPEAKER_STANDARD_MONO("mono")
615		//  MCFG_DAC_ADD("dac")
616		//  MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
617		MACHINE_CONFIG_END
618
619		ROM_START( mpoker )
620		ROM_REGION( 0x3000, "maincpu", 0 )
621		ROM_LOAD( "u13_mlt10_mk2716j.bin", 0x0000, 0x0800, CRC(ce2da863) SHA1(ddb921ac2fdd965138a91757843d3035144a7007) )
622		ROM_LOAD( "u14_mlt11_mk2716j.bin", 0x0800, 0x0800, CRC(1382d166) SHA1(a8e7339f94d65b9540a8c16190a28ff0af48ccb4) )
623		ROM_LOAD( "u15_mlt12_mk2716j.bin", 0x1000, 0x0800, CRC(eb12716c) SHA1(1589cb0aa180a3bfa5cb3da200b71f77c2191272) )
624		ROM_LOAD( "u16_mlt13_mk2716j.bin", 0x1800, 0x0800, CRC(e2d80ff0) SHA1(f8aaa513f57da458ca89f999e30ea6b2d2ef41d3) )
625		ROM_LOAD( "u17_mlt14_mk2716j.bin", 0x2000, 0x0800, CRC(36efcdf1) SHA1(d6fdc6abb1dbb5f812dc1c1ecb8d369bfcbf2b8a) )
626		ROM_LOAD( "u18_mlt15_mk2716j.bin", 0x2800, 0x0800, CRC(7701c7df) SHA1(abf19f75367f926e49031e2fb4021172ebf176e1) )
627
628		ROM_REGION( 0x2000, "gfx1", 0 )
629		ROM_LOAD( "u68_cgm0_mk2716j.bin", 0x0000, 0x0800, CRC(3e4148e3) SHA1(bc5d173cc6ff17e0a7f06d36790e20d254be0377) )
630		ROM_LOAD( "u67_cgm1_mk2716j.bin", 0x0800, 0x0800, CRC(c66c30ed) SHA1(9fb8fc669da37ff2e0379b023349ed314c8dcba4) )
631		ROM_LOAD( "u66_cgm2_mk2716j.bin", 0x1000, 0x0800, CRC(3b6b98d3) SHA1(9fc1d9d61d67ad696750c21ef9a19968ddb0a9e1) )
632		ROM_LOAD( "u65_cgm3_mk2716j.bin", 0x1800, 0x0800, CRC(d61ae9d1) SHA1(219123518999fc925397db4f442ac444dfddffbe) )
633		ROM_END
634
635
636		/*************************
637		*      Game Drivers      *
638		*************************/
639
640		/*     YEAR  NAME      PARENT  MACHINE   INPUT     INIT   ROT    COMPANY  FULLNAME      FLAGS...                           LAYOUT  */
641		GAMEL( 1981, mpoker,   0,      mpoker,   mpoker, driver_device,   0,     ROT0, "Merit", "Multi-Poker", GAME_WRONG_COLORS | GAME_NO_SOUND, layout_mpoker )

trunk/src/mame/drivers/mgames.c

r0	r31424
	1	// license:?
	2	// copyright-holders:Angelo Salese, Roberto Fresca, David Haywood
	3	/*********************************************************************************
	4
	5	Merit Industries Match Games (1981)
	6	-----------------------------------
	7
	8	Driver by Angelo Salese, David Haywood & Roberto Fresca.
	9
	10	Maybe the first Merit videopoker.
	11	The system has 4 different themed skill games, selectable through DIP switches:
	12
	13	* "The Frog Pond"
	14	* "Pharaohs"
	15	* "Wild Bulls"
	16	* "The White Knight"
	17
	18	**********************************************************************************
	19
	20	From the Flyer...
	21
	22	FOR AMUSEMENT ONLY.
	23
	24	The ingenious Match Games offers something for everyone. Four captivating themes
	25	with brillant graphics, challenging play action, an enticing bonus feature and a
	26	host of options to tailor the game to any location.
	27
	28	Match Games is today's perfect alternative in adult video skill games...
	29
	30
	31	MATCH GAMES...
	32
	33	Unique and captivating graphics start the fun out right.
	34	Players score skills points as they match the amusing characters to winning color
	35	and number combinations. Play appeal stays high as new characters are introduced.
	36
	37	"Wild" characters liven the action even more and build special bonus points, co-
	38	llected on a 5-way number match. The appeal is irresistable... Players stay hoo-
	39	ked in for lot more action (and more earnings) for you!.
	40
	41
	42	GAME THEMES:
	43
	44	Match Games aknowledges every scoring combination by displaying its own special
	45	name keyed to each game theme.
	46
	47	Every time 2 "Wild" characters pop up together, special bonus symbols appear,
	48	increasing bonus by 5 points.
	49
	50	* "THE WHITE KNIGHT" features knights in armor with colores plumes and wild
	51	'White Knights'.
	52
	53	* "THE FROG POND" stars colorful and humorous frogs perched on top of mushrooms.
	54
	55	* "WILD BULLS" is based around multi-colored sets of bulls with 2 wild 'Red Bulls'.
	56
	57	* "PHARAOHS" features an Egyptian look with comical mummies as the wild characters.
	58
	59
	60	FEATURES:
	61
	62	- Four game themes (operator selected).
	63	- "Wild" characters.
	64	- Bonus Feature, with color keyed graphics.
	65	- Adjustable game difficulty settings.
	66	- Adjustable play limit (1-10-20-50).
	67	- On screen bookkeeping.
	68	- Battery backup.
	69	- Hi quality 13" monitor.
	70	- Complete schematics.
	71	- Easy front access servicing.
	72	- All plywood construction.
	73	- Top drop coin entry.
	74	- Hi security cash box.
	75
	76
	77	**********************************************************************************
	78
	79	Hardware Notes:
	80	---------------
	81
	82	1x OSC = 18.000 MHz.
	83	1x CPU = Zilog Z80 (Z0840006PSC / 9512 / 2K).
	84	4x 74LS253N (multiplexers).
	85	4x MM2114N-3 (4096-Bit Static RAM).
	86	2x SCM5101E (256x4 Static RAM).
	87
	88	The PCB has a socket for two standard AA batteries
	89
	90
	91	MAIN BOARD:
	92	.------------------------. .-------------------. .---------------------------.
	93	|                        | ||||||||||||||||||||| |           .------------.  |
	94	|                        '-'        J2         '-'          -|4.7 Ohm 10% |- |
	95	|                                                            '------------'  |
	96	|                                                                            |
	97	|         DSW (8)                .-+-.-+-.-+-.-+-.              LM340K-5     |
	98	|                                |   |   |   |   |              7805K        |
	99	|                                | 4x 4700uF 16V |    KBL005                 |
	100	|                                |  capacitors   |     8137                  |
	101	|                                |   |   |   |   |      AC                   |
	102	|                                '-+-'-+-'-+-'-+-'                           |
	103	|                                                                            |
	104	|                                                                            |
	105	|    74LS253N  74LS253N 74LS253N 74LS253                                     |
	106	|                                               .-------------.              |
	107	|                                               | 4700uF 35V  |   MC7812CT   |
	108	|                                              -|  capacitor  |-             |
	109	|                                               '-------------'              |
	110	|               .------------------.                                         |
	111	|               |    AA BATTERY    |                                         |
	112	|               |------------------|                                         |
	113	|               |    AA BATTERY    |                                   -     |
	114	| .-.           '------------------'                       74LS04N     -     |
	115	| | |                                                                  - J1  |
	116	| | |       74LS04N  74LS02N  74LS74N   74LS02N 74LS132N               -     |
	117	| | |                                                                  -     |
	118	| | |       74LS138N 74LS08N    7416N   74LS10N 74LS161N   74123N      -     |
	119	| | |                                                                  -     |
	120	| |J|       74LS00N  74LS11N  74LS161N 74LS157N 74LS161N    7416N            |
	121	| |4|                                                                        |
	122	| | |       74LS02N  74LS32N  74LS259N 74LS151N  74LS11N             LED     |
	123	| | |                                                18.000 OSC              |
	124	| | |                74LS367N 74LS161N 74LS161N  74LS04N    DM7404N          |
	125	| | |                                                                        |
	126	| | |        74LS245PC        .-------------.    74LS74N    LM3302N          |
	127	| | |                         |   Z80 CPU   |                                |
	128	| | |        74LS245PC        '-------------'   MM2114N-3  74LS174N 74LS166J |
	129	| | |                                                                .-----. |
	130	| '-'        74LS138N       74LS245PC 74LS245PC MM2114N-3  74LS157N  | U68 | |
	131	|                                                                    '-----' |
	132	|            SCM5101E                 74LS245PC MM2114N-3  74LS174N  .-----. |
	133	|                            .-----.                                 | U67 | |
	134	|            SCM5101E        |-U18-|  74LS157N  MM2114N-3  74LS138N  |-----| |
	135	|    .-----.  .-----.        |-----|                                 | U66 | |
	136	|    |-U16-|  |-U13-|        |-U19-|  74LS157N             74LS161N  '-----' |
	137	|    |-----|  |-----|        |-----|                                 .-----. |
	138	|    |-U15-|  |-U14-|        |-U17-|  74LS157N             74LS157N  | U65 | |
	139	|    '-----'  '-----'        '-----'                                 '-----' |
	140	'----------------------------------------------------------------------------'
	141
	142
	143	U13 = MLTI 0    U68 = CGM 0
	144	U14 = MLTI 1    U67 = CGM 1
	145	U15 = MLTI 2    U66 = CGM 2
	146	U16 = MLTI 3    U65 = CGM 3
	147	U17 = MLTI 4    U1 = Zilog Z0840006PSC Z80 CPU 9512 2K
	148	U18 = MLTI 5
	149
	150	J4 = Conn to video I/O board
	151	J1 = Jumpers bank? (see multiplexed port)
	152
	153
	154	VIDEO I/O BOARD CRT810:
	155	.-------------------.
	156	|||||||||||||||||||||
	157	.-----------------------'                   '----------------------.
	158	|                                                                  |
	159	|                                                          LM380N  |
	160	|                                                                  |
	161	|                                                          MC1455P |
	162	|                                                                  |
	163	|                                                                  |
	164	| SW 7407-N    SW 7407-N    SW 7407-N    SW 7407-N                 |
	165	| 21430 7301   21430 7301   21430 7301   21430 7301                |
	166	|                                                                  |
	167	| 74LS259N     74LS259N     74LS259N     74LS259N                  |
	168	|                                                                  |
	169	'----------------.                                .----------------'
	170	||||||||||||||||||||||||||||||||||
	171	'--------------------------------'
	172	To J4 on Main Board
	173
	174	LM380N = 2.5W Audio Power Amplifier.
	175	MC1455P = Direct Replacement for NE555 Timers.
	176
	177	(Audio seems to be discrete).
	178
	179	4x 7407N (Buffer Gates Non-Inverting).
	180	4x 74LS259N (8-Bit Addressable Latches).
	181
	182	4x 7301 (HDSP?)(RED Seven Segment Displays).
	183
	184	+---------+  Pin | Description
	185	|    A    |  ----+------------
	186	|   ---   |   01 | Anode (4).
	187	| F|   |B |   02 | Cathode F.
	188	|   -G-   |   03 | Cathode G.
	189	| E|   |C |   04 | Cathode E.
	190	|   ---   |   05 | Cathode D.
	191	|    D .DP|   06 | Anode (4).
	192	+---------+   07 | Cathode DP.
	193	08 | Cathode C.
	194	09 | Cathode B.
	195	10 | Cathode A.
	196
	197
	198	**********************************************************************************
	199
	200	Dev Notes:
	201	----------
	202
	203	Additional work:
	204
	205	* Full Inputs.
	206	* DIP Switches.
	207	* Simulated spark-watchdog circuitery.
	208	* Demuxed custom port.
	209	* NVRAM support.
	210	* CPU clock derived from #defined crystal.
	211	* 8000-8007 Output ports.
	212	* Coin related counters.
	213	* Sound components and trigger found at 8000-8003, bit2.
	214	* Full lamps support.
	215	* PCBs layouts & technical notes.
	216
	217	Todo:
	218
	219	- Writes to offset 0x0158 (so many!)
	220
	221	- Still analyze 8000-8007 offset range remaining bits.
	222	These writes sounds like a BCD valueset.
	223	Maybe were intended formerly to send some data to 7seg display unit.
	224
	225	- Color system (no bipolar PROMs in the system), needs a reference
	226
	227
	228	**********************************************************************************/
	229
	230	#define MASTER_CLOCK    XTAL_18MHz
	231
	232	#include "emu.h"
	233	#include "cpu/z80/z80.h"
	234	//#include "sound/dac.h"
	235	#include "machine/nvram.h"
	236	#include "mgames.lh"
	237
	238
	239	class mgames_state : public driver_device
	240	{
	241	public:
	242	mgames_state(const machine_config &mconfig, device_type type, const char *tag)
	243	: driver_device(mconfig, type, tag),
	244	m_video(*this, "video"),
	245	m_maincpu(*this, "maincpu"),
	246	m_gfxdecode(*this, "gfxdecode"),
	247	m_palette(*this, "palette") { }
	248
	249	UINT8 m_output[8];
	250	required_shared_ptr<UINT8> m_video;
	251	int m_mixdata;
	252	DECLARE_READ8_MEMBER(mixport_r);
	253	DECLARE_WRITE8_MEMBER(muxed_w);
	254	DECLARE_WRITE8_MEMBER(outport0_w);
	255	DECLARE_WRITE8_MEMBER(outport1_w);
	256	DECLARE_WRITE8_MEMBER(outport2_w);
	257	DECLARE_WRITE8_MEMBER(outport3_w);
	258	DECLARE_WRITE8_MEMBER(outport4_w);
	259	DECLARE_WRITE8_MEMBER(outport5_w);
	260	DECLARE_WRITE8_MEMBER(outport6_w);
	261	DECLARE_WRITE8_MEMBER(outport7_w);
	262	DECLARE_WRITE8_MEMBER(sound_w);
	263	virtual void video_start();
	264	DECLARE_PALETTE_INIT(mgames);
	265	UINT32 screen_update_mgames(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	266	required_device<cpu_device> m_maincpu;
	267	required_device<gfxdecode_device> m_gfxdecode;
	268	required_device<palette_device> m_palette;
	269	};
	270
	271
	272	void mgames_state::video_start()
	273	{
	274	}
	275
	276	UINT32 mgames_state::screen_update_mgames(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
	277	{
	278	int y,x;
	279	int count;
	280	gfx_element *gfx = m_gfxdecode->gfx(0);
	281
	282	count = 0;
	283	for (y=0;y<32;y++)
	284	{
	285	for (x=0;x<32;x++)
	286	{
	287	UINT16 dat = m_video[count];
	288	UINT16 col = m_video[count+0x400] & 0x7f;
	289	gfx->opaque(bitmap,cliprect,dat,col,0,0,x*16,y*16);
	290	count++;
	291	}
	292
	293	}
	294	return 0;
	295	}
	296
	297	PALETTE_INIT_MEMBER(mgames_state, mgames)
	298	{
	299	int i;
	300
	301	for (i = 0; i < 0x100; i++)
	302	{
	303	rgb_t color;
	304
	305	if (i & 0x01)
	306	color = rgb_t(pal2bit((i & 0x6) >> 1),pal2bit((i & 0x18) >> 3),pal2bit((i & 0x60) >> 5));
	307	else
	308	color = rgb_t::black;
	309
	310	palette.set_pen_color(i, color);
	311	}
	312	}
	313
	314	READ8_MEMBER(mgames_state::mixport_r)
	315	{
	316	/*  - bits -
	317	7654 3210
	318	---- ---x   Unknown.
	319	---- --x-   Spark-Watchdog...
	320	---- -x--   DIP Switch Bank #2.
	321	---- x---   DIP Switch Bank #2.
	322	---x ----   DIP Switch Bank #2.
	323	xxx- ----   Unknown.
	324
	325	Spark-Watchdog... The system expect status changes on bit1, otherwise stop the hardware with an error message.
	326	The line seems to be tied to a clock. We can't use XORed status due to the nested checks.
	327	If you change the status *every* read, the HW stucks.
	328	*/
	329
	330	m_mixdata = (ioport("SW2")->read() & 0xfd) | (machine().rand() & 0x02);
	331
	332	return m_mixdata;
	333	}
	334
	335	/***** Port 0158 *****
	336
	337	- bits -
	338	7654 3210
	339	---- ---x   Unknown.
	340	---- --x-   Unknown.
	341	---- -x--   Unknown.
	342	---- x---   Unknown.
	343	---x ----   Unknown.
	344	xxx- ----   Unknown.
	345	*/
	346
	347	//WRITE8_MEMBER(mgames_state::muxed_w)
	348	//{
	349	//  popmessage("written : %02X %02X %02X %02X %02X %02X %02X %02X", data & 0x01, data & 0x02, data & 0x04, data & 0x08, data & 0x10, data & 0x20, data & 0x40, data & 0x80);
	350	//}
	351
	352	/***** Port 8000 *****
	353
	354	- bits -
	355	7654 3210
	356	---- ---x   BET lamp.
	357	---- --x-   HOLD1 lamp.
	358	---- -x--   Sound component #1.
	359	---- x---   Unknown.
	360	---x ----   Unknown.
	361	xxx- ----   Unknown.
	362	*/
	363
	364	WRITE8_MEMBER(mgames_state::outport0_w)
	365	{
	366	output_set_lamp_value(1, (data & 1));           /* Lamp 1 - BET */
	367	output_set_lamp_value(5, (data >> 1) & 1);      /* Lamp 5 - HOLD 1 */
	368
	369	m_output[0] = data;
	370	popmessage("outport0 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
	371	}
	372
	373	/***** Port 8001 *****
	374
	375	- bits -
	376	7654 3210
	377	---- ---x   DEAL lamp.
	378	---- --x-   HOLD2 lamp.
	379	---- -x--   Sound component #2.
	380	---- x---   Unknown.
	381	---x ----   Unknown.
	382	xxx- ----   Unknown.
	383	*/
	384
	385	WRITE8_MEMBER(mgames_state::outport1_w)
	386	{
	387	output_set_lamp_value(2, (data & 1));           /* Lamp 2 - DEAL */
	388	output_set_lamp_value(6, (data >> 1) & 1);      /* Lamp 6 - HOLD 2 */
	389
	390	m_output[1] = data;
	391	popmessage("outport1 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
	392	}
	393
	394	/***** Port 8002 *****
	395
	396	- bits -
	397	7654 3210
	398	---- ---x   CANCEL lamp.
	399	---- --x-   HOLD3 lamp.
	400	---- -x--   Sound component #3.
	401	---- x---   Unknown.
	402	---x ----   Unknown.
	403	xxx- ----   Unknown.
	404	*/
	405
	406	WRITE8_MEMBER(mgames_state::outport2_w)
	407	{
	408	output_set_lamp_value(3, (data & 1));           /* Lamp 3 - CANCEL */
	409	output_set_lamp_value(7, (data >> 1) & 1);      /* Lamp 7 - HOLD 3 */
	410
	411	m_output[2] = data;
	412	popmessage("outport2 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
	413	}
	414
	415	/***** Port 8003 *****
	416
	417	- bits -
	418	7654 3210
	419	---- ---x   Unknown lamp.
	420	---- --x-   HOLD4 lamp.
	421	---- -x--   Sound trigger.
	422	---- x---   Unknown.
	423	---x ----   Unknown.
	424	xxx- ----   Unknown.
	425	*/
	426
	427	WRITE8_MEMBER(mgames_state::outport3_w)
	428	{
	429	output_set_lamp_value(4, (data & 1));           /* Lamp 4 - STAND */
	430	output_set_lamp_value(8, (data >> 1) & 1);      /* Lamp 8 - HOLD 4 */
	431
	432	m_output[3] = data;
	433	popmessage("outport3 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
	434	}
	435
	436	/***** Port 8004 *****
	437
	438	- bits -
	439	7654 3210
	440	---- ---x   Unknown.
	441	---- --x-   HOLD5 lamp.
	442	---- -x--   Unknown.
	443	---- x---   Unknown.
	444	---x ----   Unknown.
	445	xxx- ----   Unknown.
	446	*/
	447
	448	WRITE8_MEMBER(mgames_state::outport4_w)
	449	{
	450	output_set_lamp_value(9, (data >> 1) & 1);      /* Lamp 9 - HOLD 5 */
	451
	452	m_output[4] = data;
	453	popmessage("outport4 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
	454	}
	455
	456	/***** Port 8005 *****
	457
	458	- bits -
	459	7654 3210
	460	---- ---x   Unknown.
	461	---- --x-   Unknown.
	462	---- -x--   Unknown.
	463	---- x---   Unknown.
	464	---x ----   Unknown.
	465	xxx- ----   Unknown.
	466	*/
	467
	468	WRITE8_MEMBER(mgames_state::outport5_w)
	469	{
	470	m_output[5] = data;
	471	popmessage("outport5 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
	472	}
	473
	474	/***** Port 8006 *****
	475
	476	- bits -
	477	7654 3210
	478	---- ---x   Unknown.
	479	---- --x-   Payout pulse.
	480	---- -x--   Unknown.
	481	---- x---   Unknown.
	482	---x ----   Unknown.
	483	xxx- ----   Unknown.
	484	*/
	485
	486	WRITE8_MEMBER(mgames_state::outport6_w)
	487	{
	488	coin_counter_w(machine(), 1, data & 0x02);  /* Payout pulse */
	489
	490	m_output[6] = data;
	491	popmessage("outport6 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
	492	}
	493
	494	/***** Port 8007 *****
	495
	496	- bits -
	497	7654 3210
	498	---- ---x   Unknown.
	499	---- --x-   Coin pulse.
	500	---- -x--   Unknown.
	501	---- x---   Unknown.
	502	---x ----   Unknown.
	503	xxx- ----   Unknown.
	504	*/
	505
	506	WRITE8_MEMBER(mgames_state::outport7_w)
	507	{
	508	coin_counter_w(machine(), 0, data & 0x02);  /* Coin pulse */
	509
	510	m_output[7] = data;
	511	popmessage("outport7 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
	512	}
	513
	514
	515	/********  Discrete Sound  ********
	516
	517	There are 3 components plus a trigger:
	518
	519	Component #1 = $8000, bit2.
	520	Component #2 = $8001, bit2.
	521	Component #3 = $8002, bit2.
	522
	523	Trigger = $8003, bit2.
	524
	525	All bits are inverted.
	526
	527
	528	Sound | 8000 | 8001 | 8002 | 8003
	529	------+------+------+------+-----
	530	01   | bit2 | bit2 | bit2 | bit2
	531	02   | ---- | bit2 | bit2 | bit2
	532	03   | bit2 | ---- | bit2 | bit2
	533	04   | bit2 | bit2 | ---- | bit2
	534	05   | ---- | ---- | ---- | bit2
	535
	536
	537	WRITE8_MEMBER(mgames_state::sound_w)
	538	//{
	539	//  m_dac->write_unsigned8(data);
	540	//}
	541	*/
	542
	543	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, mgames_state )
	544	AM_RANGE(0x0000, 0x2fff) AM_ROM
	545	//  AM_RANGE(0x0158, 0x0158) AM_WRITE (muxed_w)
	546	AM_RANGE(0x3800, 0x38ff) AM_RAM AM_SHARE("nvram")   /* NVRAM = 2x SCM5101E */
	547	AM_RANGE(0x4000, 0x47ff) AM_RAM AM_SHARE("video")   /* 4x MM2114N-3 */
	548	AM_RANGE(0x8000, 0x8000) AM_READ_PORT("SW1")
	549	AM_RANGE(0x8001, 0x8001) AM_READ(mixport_r) /* DIP switch bank 2 + a sort of watchdog */
	550	AM_RANGE(0x8002, 0x8002) AM_READ_PORT("IN1")
	551	AM_RANGE(0x8003, 0x8003) AM_READ_PORT("IN2")
	552	AM_RANGE(0x8000, 0x8000) AM_WRITE(outport0_w)
	553	AM_RANGE(0x8001, 0x8001) AM_WRITE(outport1_w)
	554	AM_RANGE(0x8002, 0x8002) AM_WRITE(outport2_w)
	555	AM_RANGE(0x8003, 0x8003) AM_WRITE(outport3_w)
	556	AM_RANGE(0x8004, 0x8004) AM_WRITE(outport4_w)
	557	AM_RANGE(0x8005, 0x8005) AM_WRITE(outport5_w)
	558	AM_RANGE(0x8006, 0x8006) AM_WRITE(outport6_w)
	559	AM_RANGE(0x8007, 0x8007) AM_WRITE(outport7_w)
	560	ADDRESS_MAP_END
	561
	562
	563	static INPUT_PORTS_START( mgames )
	564	PORT_START("IN1")
	565	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_GAMBLE_BET )
	566	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_GAMBLE_DEAL )
	567	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_POKER_CANCEL ) PORT_NAME("Cancel Discards")
	568	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Stand (Hold all Cards)")
	569	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_POKER_HOLD1 ) PORT_NAME("Discard 1")
	570	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_POKER_HOLD2 ) PORT_NAME("Discard 2")
	571	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_POKER_HOLD3 ) PORT_NAME("Discard 3")
	572	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_POKER_HOLD4 ) PORT_NAME("Discard 4")
	573
	574	PORT_START("IN2")
	575	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_POKER_HOLD5 ) PORT_NAME("Discard 5")
	576	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_GAMBLE_BOOK ) PORT_NAME("Stats")
	577	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_GAMBLE_PAYOUT )
	578	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
	579	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2)
	580	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_GAMBLE_SERVICE ) PORT_NAME("Settings")
	581	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	582	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
	583
	584	PORT_START("SW1")
	585	PORT_DIPNAME( 0x0f, 0x0f, DEF_STR( Coin_A ) )
	586	PORT_DIPSETTING(    0x00, "20 Coins/1 Credit" )
	587	PORT_DIPSETTING(    0x01, "10 Coins/1 Credit" )
	588	PORT_DIPSETTING(    0x02, DEF_STR( 8C_1C ) )
	589	PORT_DIPSETTING(    0x03, DEF_STR( 5C_1C ) )
	590	PORT_DIPSETTING(    0x04, DEF_STR( 4C_1C ) )
	591	PORT_DIPSETTING(    0x05, "5 Coins/2 Credits" )
	592	PORT_DIPSETTING(    0x06, DEF_STR( 2C_1C ) )
	593	//  PORT_DIPSETTING(    0x07, DEF_STR( 1C_1C ) ) --> damn check... you can't set 2 different bits pointing to the same coinage.
	594	PORT_DIPSETTING(    0x0f, DEF_STR( 1C_1C ) )
	595	PORT_DIPSETTING(    0x0e, DEF_STR( 1C_2C ) )
	596	PORT_DIPSETTING(    0x0d, DEF_STR( 2C_5C ) )
	597	PORT_DIPSETTING(    0x0c, DEF_STR( 1C_4C ) )
	598	PORT_DIPSETTING(    0x0b, DEF_STR( 1C_5C ) )
	599	PORT_DIPSETTING(    0x0a, DEF_STR( 1C_8C ) )
	600	PORT_DIPSETTING(    0x09, "1 Coin/10 Credits" )
	601	PORT_DIPSETTING(    0x08, "1 Coin/20 Credits" )
	602	PORT_DIPNAME( 0x30, 0x30, "Game Select" )
	603	PORT_DIPSETTING(    0x00, "The White Knight" )
	604	PORT_DIPSETTING(    0x10, "Wild Bulls" )
	605	PORT_DIPSETTING(    0x20, "Pharaohs" )
	606	PORT_DIPSETTING(    0x30, "The Frog Pond" )
	607	PORT_DIPNAME( 0xc0, 0xc0, "Maximun Bet" )
	608	PORT_DIPSETTING(    0x40, "1" )
	609	PORT_DIPSETTING(    0xc0, "10" )
	610	PORT_DIPSETTING(    0x80, "20" )
	611	PORT_DIPSETTING(    0x00, "50" )
	612
	613	PORT_START("SW2")
	614	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
	615	PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
	616	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	617	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER )      /* bit1 connected to a signal heartbeat */
	618	PORT_DIPNAME( 0x1c, 0x0c, "Main Percentage" )
	619	PORT_DIPSETTING(    0x18, "75%" )
	620	PORT_DIPSETTING(    0x14, "80%" )
	621	PORT_DIPSETTING(    0x00, "85%" )
	622	PORT_DIPSETTING(    0x0c, "90%" )
	623	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	624	PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
	625	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	626	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	627	PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
	628	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	629	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	630	PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
	631	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	632
	633	INPUT_PORTS_END
	634
	635
	636	static const gfx_layout tiles16x16_layout =
	637	{
	638	16,16,
	639	RGN_FRAC(1,1),
	640	1,
	641	{ 0 },
	642	{ 0, 1, 2, 3, 4, 5, 6, 7,8,9,10,11,12,13,14,15 },
	643	{ 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16,
	644	8*16, 9*16,10*16,11*16,12*16,13*16,14*16,15*16},
	645	16*16
	646	};
	647
	648	static GFXDECODE_START( mgames )
	649	GFXDECODE_ENTRY( "gfx1", 0, tiles16x16_layout, 0, 0x100 )
	650	GFXDECODE_END
	651
	652
	653	static MACHINE_CONFIG_START( mgames, mgames_state )
	654	/* basic machine hardware */
	655	MCFG_CPU_ADD("maincpu", Z80,MASTER_CLOCK/6)      /* 3 MHz? */
	656	MCFG_CPU_PROGRAM_MAP(main_map)
	657	MCFG_CPU_VBLANK_INT_DRIVER("screen", mgames_state,  irq0_line_hold)
	658
	659	MCFG_NVRAM_ADD_0FILL("nvram")
	660
	661	/* video hardware */
	662	MCFG_SCREEN_ADD("screen", RASTER)
	663	MCFG_SCREEN_REFRESH_RATE(60)
	664	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
	665	MCFG_SCREEN_SIZE(512, 256)
	666	MCFG_SCREEN_VISIBLE_AREA(0, 512-1, 0, 256-1)
	667	MCFG_SCREEN_UPDATE_DRIVER(mgames_state, screen_update_mgames)
	668	MCFG_SCREEN_PALETTE("palette")
	669
	670	MCFG_GFXDECODE_ADD("gfxdecode", "palette", mgames)
	671	MCFG_PALETTE_ADD("palette", 0x200)
	672	MCFG_PALETTE_INIT_OWNER(mgames_state, mgames)
	673
	674	/* sound hardware */
	675	//  MCFG_SPEAKER_STANDARD_MONO("mono")
	676	//  MCFG_DAC_ADD("dac")
	677	//  MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
	678	MACHINE_CONFIG_END
	679
	680
	681	ROM_START( mgames )
	682	ROM_REGION( 0x3000, "maincpu", 0 )
	683	ROM_LOAD( "u13_mlt10_mk2716j.bin", 0x0000, 0x0800, CRC(ce2da863) SHA1(ddb921ac2fdd965138a91757843d3035144a7007) )
	684	ROM_LOAD( "u14_mlt11_mk2716j.bin", 0x0800, 0x0800, CRC(1382d166) SHA1(a8e7339f94d65b9540a8c16190a28ff0af48ccb4) )
	685	ROM_LOAD( "u15_mlt12_mk2716j.bin", 0x1000, 0x0800, CRC(eb12716c) SHA1(1589cb0aa180a3bfa5cb3da200b71f77c2191272) )
	686	ROM_LOAD( "u16_mlt13_mk2716j.bin", 0x1800, 0x0800, CRC(e2d80ff0) SHA1(f8aaa513f57da458ca89f999e30ea6b2d2ef41d3) )
	687	ROM_LOAD( "u17_mlt14_mk2716j.bin", 0x2000, 0x0800, CRC(36efcdf1) SHA1(d6fdc6abb1dbb5f812dc1c1ecb8d369bfcbf2b8a) )
	688	ROM_LOAD( "u18_mlt15_mk2716j.bin", 0x2800, 0x0800, CRC(7701c7df) SHA1(abf19f75367f926e49031e2fb4021172ebf176e1) )
	689
	690	ROM_REGION( 0x2000, "gfx1", 0 )
	691	ROM_LOAD( "u68_cgm0_mk2716j.bin", 0x0000, 0x0800, CRC(3e4148e3) SHA1(bc5d173cc6ff17e0a7f06d36790e20d254be0377) )
	692	ROM_LOAD( "u67_cgm1_mk2716j.bin", 0x0800, 0x0800, CRC(c66c30ed) SHA1(9fb8fc669da37ff2e0379b023349ed314c8dcba4) )
	693	ROM_LOAD( "u66_cgm2_mk2716j.bin", 0x1000, 0x0800, CRC(3b6b98d3) SHA1(9fc1d9d61d67ad696750c21ef9a19968ddb0a9e1) )
	694	ROM_LOAD( "u65_cgm3_mk2716j.bin", 0x1800, 0x0800, CRC(d61ae9d1) SHA1(219123518999fc925397db4f442ac444dfddffbe) )
	695	ROM_END
	696
	697
	698	/*************************
	699	*      Game Drivers      *
	700	*************************/
	701
	702	/*     YEAR  NAME      PARENT  MACHINE   INPUT   STATE          INIT   ROT    COMPANY  FULLNAME      FLAGS...                           LAYOUT  */
	703	GAMEL( 1981, mgames,   0,      mgames,   mgames, driver_device, 0,     ROT0, "Merit", "Match Games", GAME_WRONG_COLORS | GAME_NO_SOUND, layout_mgames )

Property changes on: trunk/src/mame/drivers/mgames.c

Added: svn:mime-type    + text/xml Added: svn:eol-style    + native

trunk/src/mame/mame.lst

r31423	r31424
10363	10363	popobear        // (c) 2000 BMC
10364	10364
10365	10365	// Merit
10366		mpoker          // (c) 1983 Merit
	10366	mgames          // (c) 1981 Merit
10367	10367	pitboss         // (c) 1983 Merit
10368	10368	pitbossa        // (c) 1983 Merit
10369	10369	pitbossa1       // (c) 1983 Merit

trunk/src/mame/mame.mak

r31423	r31424
1421	1421	$(DRIVERS)/warpsped.o
1422	1422
1423	1423	$(MAMEOBJ)/merit.a: \
1424		$(DRIVERS)/mpoker.o \
	1424	$(DRIVERS)/mgames.o \
1425	1425	$(DRIVERS)/merit.o \
1426	1426	$(DRIVERS)/meritm.o \
1427	1427
r31423	r31424
2674	2674	$(DRIVERS)/mcr3.o:      $(LAYOUT)/spyhunt.lh \
2675	2675	$(LAYOUT)/turbotag.lh
2676	2676
2677		$(DRIVERS)/mpoker.o:    $(LAYOUT)/mpoker.lh
	2677	$(DRIVERS)/mgames.o:    $(LAYOUT)/mgames.lh
2678	2678
2679	2679	$(DRIVERS)/mpu3.o:      $(LAYOUT)/mpu3.lh
2680	2680

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team