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r31285 Tuesday 15th July, 2014 at 13:05:41 UTC by Curt Coder
(MESS) c128: Optimized from 118% to 124%. (nw)
[src/mess/drivers]c128.c
[src/mess/includes]c128.h

trunk/src/mess/includes/c128.h
r31284r31285
4040class c128_state : public driver_device
4141{
4242public:
43   c128_state(const machine_config &mconfig, device_type type, const char *tag)
44      : driver_device(mconfig, type, tag),
45         m_maincpu(*this, Z80A_TAG),
46         m_subcpu(*this, M8502_TAG),
47         m_mmu(*this, MOS8722_TAG),
48         m_pla(*this, MOS8721_TAG),
49         m_vdc(*this, MOS8563_TAG),
50         m_vic(*this, MOS8564_TAG),
51         m_sid(*this, MOS6581_TAG),
52         m_cia1(*this, MOS6526_1_TAG),
53         m_cia2(*this, MOS6526_2_TAG),
54         m_iec(*this, CBM_IEC_TAG),
55         m_joy1(*this, CONTROL1_TAG),
56         m_joy2(*this, CONTROL2_TAG),
57         m_exp(*this, C64_EXPANSION_SLOT_TAG),
58         m_user(*this, PET_USER_PORT_TAG),
59         m_ram(*this, RAM_TAG),
60         m_cassette(*this, PET_DATASSETTE_PORT_TAG),
61         m_rom(*this, M8502_TAG),
62         m_from(*this, "from"),
63         m_charom(*this, "charom"),
64         m_color_ram(*this, "color_ram"),
65         m_row0(*this, "ROW0"),
66         m_row1(*this, "ROW1"),
67         m_row2(*this, "ROW2"),
68         m_row3(*this, "ROW3"),
69         m_row4(*this, "ROW4"),
70         m_row5(*this, "ROW5"),
71         m_row6(*this, "ROW6"),
72         m_row7(*this, "ROW7"),
73         m_k0(*this, "K0"),
74         m_k1(*this, "K1"),
75         m_k2(*this, "K2"),
76         m_lock(*this, "LOCK"),
77         m_caps(*this, "CAPS"),
78         m_40_80(*this, "40_80"),
79         m_z80en(0),
80         m_loram(1),
81         m_hiram(1),
82         m_charen(1),
83         m_game(1),
84         m_exrom(1),
85         m_va14(1),
86         m_va15(1),
87         m_clrbank(0),
88         m_cnt1(1),
89         m_sp1(1),
90         m_iec_data_out(1),
91         m_restore(1),
92         m_cia1_irq(CLEAR_LINE),
93         m_cia2_irq(CLEAR_LINE),
94         m_vic_irq(CLEAR_LINE),
95         m_exp_irq(CLEAR_LINE),
96         m_exp_nmi(CLEAR_LINE),
97         m_cass_rd(1),
98         m_iec_srq(1),
99         m_vic_k(0x07),
100         m_caps_lock(1)
43   c128_state(const machine_config &mconfig, device_type type, const char *tag) :
44      driver_device(mconfig, type, tag),
45      m_maincpu(*this, Z80A_TAG),
46      m_subcpu(*this, M8502_TAG),
47      m_mmu(*this, MOS8722_TAG),
48      m_pla(*this, MOS8721_TAG),
49      m_vdc(*this, MOS8563_TAG),
50      m_vic(*this, MOS8564_TAG),
51      m_sid(*this, MOS6581_TAG),
52      m_cia1(*this, MOS6526_1_TAG),
53      m_cia2(*this, MOS6526_2_TAG),
54      m_iec(*this, CBM_IEC_TAG),
55      m_joy1(*this, CONTROL1_TAG),
56      m_joy2(*this, CONTROL2_TAG),
57      m_exp(*this, C64_EXPANSION_SLOT_TAG),
58      m_user(*this, PET_USER_PORT_TAG),
59      m_ram(*this, RAM_TAG),
60      m_cassette(*this, PET_DATASSETTE_PORT_TAG),
61      m_rom(*this, M8502_TAG),
62      m_from(*this, "from"),
63      m_charom(*this, "charom"),
64      m_color_ram(*this, "color_ram"),
65      m_row0(*this, "ROW0"),
66      m_row1(*this, "ROW1"),
67      m_row2(*this, "ROW2"),
68      m_row3(*this, "ROW3"),
69      m_row4(*this, "ROW4"),
70      m_row5(*this, "ROW5"),
71      m_row6(*this, "ROW6"),
72      m_row7(*this, "ROW7"),
73      m_k0(*this, "K0"),
74      m_k1(*this, "K1"),
75      m_k2(*this, "K2"),
76      m_lock(*this, "LOCK"),
77      m_caps(*this, "CAPS"),
78      m_40_80(*this, "40_80"),
79      m_z80en(0),
80      m_loram(1),
81      m_hiram(1),
82      m_charen(1),
83      m_game(1),
84      m_exrom(1),
85      m_va14(1),
86      m_va15(1),
87      m_clrbank(0),
88      m_cnt1(1),
89      m_sp1(1),
90      m_iec_data_out(1),
91      m_restore(1),
92      m_cia1_irq(CLEAR_LINE),
93      m_cia2_irq(CLEAR_LINE),
94      m_vic_irq(CLEAR_LINE),
95      m_exp_irq(CLEAR_LINE),
96      m_exp_nmi(CLEAR_LINE),
97      m_cass_rd(1),
98      m_iec_srq(1),
99      m_vic_k(0x07),
100      m_caps_lock(1)
101101   { }
102102
103103   required_device<cpu_device> m_maincpu;
r31284r31285
139139   virtual void machine_reset();
140140
141141   inline void check_interrupts();
142   void read_pla(offs_t offset, offs_t ca, offs_t vma, int ba, int rw, int aec, int z80io, int ms3, int ms2, int ms1, int ms0,
143      int *sden, int *dir, int *gwe, int *rom1, int *rom2, int *rom3, int *rom4, int *charom, int *colorram, int *vic,
144      int *from1, int *romh, int *roml, int *dwe, int *ioacc, int *clrbank, int *iocs, int *casenb);
142   int read_pla(offs_t offset, offs_t ca, offs_t vma, int ba, int rw, int aec, int z80io, int ms3, int ms2, int ms1, int ms0);
145143   UINT8 read_memory(address_space &space, offs_t offset, offs_t vma, int ba, int aec, int z80io);
146144   void write_memory(address_space &space, offs_t offset, offs_t vma, UINT8 data, int ba, int aec, int z80io);
147145   inline void update_iec();
trunk/src/mess/drivers/c128.c
r31284r31285
3333#define VMA5 BIT(vma, 13)
3434#define VMA4 BIT(vma, 12)
3535
36enum
37{
38   PLA_OUT_SDEN = 0,
39   PLA_OUT_ROM4 = 1,
40   PLA_OUT_ROM2 = 2,
41   PLA_OUT_DIR = 3,
42   PLA_OUT_ROML = 4,
43   PLA_OUT_ROMH = 5,
44   PLA_OUT_CLRBANK = 6,
45   PLA_OUT_FROM1 = 7,
46   PLA_OUT_ROM3 = 8,
47   PLA_OUT_ROM1 = 9,
48   PLA_OUT_IOCS = 10,
49   PLA_OUT_DWE = 11,
50   PLA_OUT_CASENB = 12,
51   PLA_OUT_VIC = 13,
52   PLA_OUT_IOACC = 14,
53   PLA_OUT_GWE = 15,
54   PLA_OUT_COLORRAM = 16,
55   PLA_OUT_CHAROM = 17
56};
3657
3758
3859QUICKLOAD_LOAD_MEMBER( c128_state, cbm_c64 )
r31284r31285
4061   return general_cbm_loadsnap(image, file_type, quickload_size, m_maincpu->space(AS_PROGRAM), 0, cbm_quick_sethiaddress);
4162}
4263
64
4365//**************************************************************************
4466//  INTERRUPTS
4567//**************************************************************************
r31284r31285
7294//  read_pla -
7395//-------------------------------------------------
7496
75void c128_state::read_pla(offs_t offset, offs_t ca, offs_t vma, int ba, int rw, int aec, int z80io, int ms3, int ms2, int ms1, int ms0,
76      int *sden, int *dir, int *gwe, int *rom1, int *rom2, int *rom3, int *rom4, int *charom, int *colorram, int *vic,
77      int *from1, int *romh, int *roml, int *dwe, int *ioacc, int *clrbank, int *iocs, int *casenb)
97int c128_state::read_pla(offs_t offset, offs_t ca, offs_t vma, int ba, int rw, int aec, int z80io, int ms3, int ms2, int ms1, int ms0)
7898{
7999   int _128_256 = 1;
80100   int dmaack = 1;
r31284r31285
89109      m_exrom << 15 | m_game << 14 | rw << 13 | aec << 12 | A10 << 11 | A11 << 10 | A12 << 9 | A13 << 8 |
90110      A14 << 7 | A15 << 6 | z80io << 5 | m_z80en << 4 | ms3 << 3 | vicfix << 2 | dmaack << 1 | _128_256;
91111
92   UINT32 data = m_pla->read(input);
93
94   *sden = BIT(data, 0);
95   *rom4 = BIT(data, 1);
96   *rom2 = BIT(data, 2);
97   *dir = BIT(data, 3);
98   *roml = BIT(data, 4);
99   *romh = BIT(data, 5);
100   *clrbank = BIT(data, 6);
101   *from1 = BIT(data, 7);
102   *rom3 = BIT(data, 8);
103   *rom1 = BIT(data, 9);
104   *iocs = BIT(data, 10);
105   *dwe = BIT(data, 11);
106   *casenb = BIT(data, 12);
107   *vic = BIT(data, 13);
108   *ioacc = BIT(data, 14);
109   *gwe = BIT(data, 15);
110   *colorram = BIT(data, 16);
111   *charom = BIT(data, 17);
112
113   m_clrbank = *clrbank;
112   return m_pla->read(input);
114113}
115114
116115
r31284r31285
121120UINT8 c128_state::read_memory(address_space &space, offs_t offset, offs_t vma, int ba, int aec, int z80io)
122121{
123122   int rw = 1, ms0 = 1, ms1 = 1, ms2 = 1, ms3 = 1, cas0 = 1, cas1 = 1;
124   int sden = 1, dir = 1, gwe = 1, rom1 = 1, rom2 = 1, rom3 = 1, rom4 = 1, charom = 1, colorram = 1, vic = 1,
125      from1 = 1, romh = 1, roml = 1, dwe = 1, ioacc = 1, clrbank = 1, iocs = 1, casenb = 1;
126123   int io1 = 1, io2 = 1;
127124   int sphi2 = m_vic->phi0_r();
128125
r31284r31285
148145
149146   offs_t ca = ta | sa;
150147
151   read_pla(offset, ca, vma, ba, rw, aec, z80io, ms3, ms2, ms1, ms0,
152      &sden, &dir, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic,
153      &from1, &romh, &roml, &dwe, &ioacc, &clrbank, &iocs, &casenb);
148   int plaout = read_pla(offset, ca, vma, ba, rw, aec, z80io, ms3, ms2, ms1, ms0);
154149
155   if (!casenb)
150   m_clrbank = BIT(plaout, PLA_OUT_CLRBANK);
151
152   if (!BIT(plaout, PLA_OUT_CASENB))
156153   {
157154      if (!cas0)
158155      {
r31284r31285
163160         data = m_ram->pointer()[0x10000 | ma];
164161      }
165162   }
166   if (!rom1)
163   if (!BIT(plaout, PLA_OUT_ROM1))
167164   {
168165      // CR: data = m_rom1[(ms3 << 14) | ((BIT(ta, 14) && BIT(offset, 13)) << 13) | (ta & 0x1000) | (offset & 0xfff)];
169166      data = m_rom->base()[((BIT(ta, 14) && BIT(offset, 13)) << 13) | (ta & 0x1000) | (offset & 0xfff)];
170167   }
171   if (!rom2)
168   if (!BIT(plaout, PLA_OUT_ROM2))
172169   {
173170      data = m_rom->base()[0x4000 | (offset & 0x3fff)];
174171   }
175   if (!rom3)
172   if (!BIT(plaout, PLA_OUT_ROM3))
176173   {
177174      // CR: data = m_rom3[(BIT(offset, 15) << 14) | (offset & 0x3fff)];
178175      data = m_rom->base()[0x8000 | (offset & 0x3fff)];
179176   }
180   if (!rom4)
177   if (!BIT(plaout, PLA_OUT_ROM4))
181178   {
182179      data = m_rom->base()[0xc000 | (ta & 0x1000) | (offset & 0x2fff)];
183180   }
184   if (!charom)
181   if (!BIT(plaout, PLA_OUT_CHAROM))
185182   {
186183      data = m_charom->base()[(ms3 << 12) | (ta & 0xf00) | sa];
187184   }
188   if (!colorram && aec)
185   if (!BIT(plaout, PLA_OUT_COLORRAM) && aec)
189186   {
190      data = m_color_ram[(clrbank << 10) | (ta & 0x300) | sa] & 0x0f;
187      data = m_color_ram[(m_clrbank << 10) | (ta & 0x300) | sa] & 0x0f;
191188   }
192   if (!vic)
189   if (!BIT(plaout, PLA_OUT_VIC))
193190   {
194191      data = m_vic->read(space, offset & 0x3f);
195192   }
196   if (!from1)
193   if (!BIT(plaout, PLA_OUT_FROM1))
197194   {
198195      data = m_from->base()[offset & 0x7fff];
199196   }
200   if (!iocs && BIT(offset, 10))
197   if (!BIT(plaout, PLA_OUT_IOCS) && BIT(offset, 10))
201198   {
202199      switch ((BIT(offset, 11) << 2) | ((offset >> 8) & 0x03))
203200      {
r31284r31285
234231      }
235232   }
236233
234   int roml = BIT(plaout, PLA_OUT_ROML);
235   int romh = BIT(plaout, PLA_OUT_ROMH);
236
237237   data = m_exp->cd_r(space, ca, data, sphi2, ba, roml, romh, io1, io2);
238238
239239   return m_mmu->read(offset, data);
r31284r31285
247247void c128_state::write_memory(address_space &space, offs_t offset, offs_t vma, UINT8 data, int ba, int aec, int z80io)
248248{
249249   int rw = 0, ms0 = 1, ms1 = 1, ms2 = 1, ms3 = 1, cas0 = 1, cas1 = 1;
250   int sden = 1, dir = 1, gwe = 1, rom1 = 1, rom2 = 1, rom3 = 1, rom4 = 1, charom = 1, colorram = 1, vic = 1,
251      from1 = 1, romh = 1, roml = 1, dwe = 1, ioacc = 1, clrbank = 1, iocs = 1, casenb = 1;
252250   int io1 = 1, io2 = 1;
253251   int sphi2 = m_vic->phi0_r();
254252
r31284r31285
257255   offs_t ma = ta | (offset & 0xff);
258256   offs_t sa = offset & 0xff;
259257
260   read_pla(offset, ca, vma, ba, rw, aec, z80io, ms3, ms2, ms1, ms0,
261      &sden, &dir, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic,
262      &from1, &romh, &roml, &dwe, &ioacc, &clrbank, &iocs, &casenb);
258   int plaout = read_pla(offset, ca, vma, ba, rw, aec, z80io, ms3, ms2, ms1, ms0);
263259
264   if (!casenb && !dwe)
260   m_clrbank = BIT(plaout, PLA_OUT_CLRBANK);
261
262   if (!BIT(plaout, PLA_OUT_CASENB) && !BIT(plaout, PLA_OUT_DWE))
265263   {
266264      if (!cas0)
267265      {
r31284r31285
272270         m_ram->pointer()[0x10000 | ma] = data;
273271      }
274272   }
275   if (!colorram && !gwe)
273   if (!BIT(plaout, PLA_OUT_COLORRAM) && !BIT(plaout, PLA_OUT_GWE))
276274   {
277      m_color_ram[(clrbank << 10) | (ta & 0x300) | sa] = data & 0x0f;
275      m_color_ram[(m_clrbank << 10) | (ta & 0x300) | sa] = data & 0x0f;
278276   }
279   if (!vic)
277   if (!BIT(plaout, PLA_OUT_VIC))
280278   {
281279      m_vic->write(space, offset & 0x3f, data);
282280   }
283   if (!iocs && BIT(offset, 10))
281   if (!BIT(plaout, PLA_OUT_IOCS) && BIT(offset, 10))
284282   {
285283      switch ((BIT(offset, 11) << 2) | ((offset >> 8) & 0x03))
286284      {
r31284r31285
317315      }
318316   }
319317
318   int roml = BIT(plaout, PLA_OUT_ROML);
319   int romh = BIT(plaout, PLA_OUT_ROMH);
320
320321   m_exp->cd_w(space, ca, data, sphi2, ba, roml, romh, io1, io2);
321322
322323   m_mmu->write(space, offset, data);

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