MAME SVN History

199869 Revisions

r31177 Thursday 3rd July, 2014 at 20:28:08 UTC by Wilbert Pol
tms34010: Modernised cpu core. (nw)

[src/emu/cpu/tms34010]	34010fld.c 34010gfx.c 34010ops.c 34010ops.h 34010tbl.c tms34010.c tms34010.h
[src/mame/drivers]	artmagic.c btoads.c coolpool.c exterm.c harddriv.c jpmimpct.c lethalj.c metalmx.c micro3d.c midtunit.c midwunit.c midxunit.c midyunit.c potgoldu.c skeetsht.c skimaxx.c tickee.c xtheball.c
[src/mame/machine]	inder_vid.c
[src/mame/video]	exterm.c

trunk/src/mame/drivers/midwunit.c
r31176	r31177
615	615	*
616	616	*************************************/
617	617
618		static const tms34010_config tms_config =
	618	static const tms340x0_config tms_config =
619	619	{
620	620	FALSE, /* halt on reset */
621	621	"screen", /* the screen operated on */
r31176	r31177
639	639	static MACHINE_CONFIG_START( wunit, midwunit_state )
640	640
641	641	MCFG_CPU_ADD("maincpu", TMS34010, 50000000)
642		MCFG_~~CPU~~_CONFIG(tms_config)
	642	MCFG_TMS340X0_CONFIG(tms_config)
643	643	MCFG_CPU_PROGRAM_MAP(main_map)
644	644
645	645	MCFG_MACHINE_RESET_OVERRIDE(midwunit_state,midwunit)

trunk/src/mame/drivers/skimaxx.c
r31176	r31177
467	467	// TODO
468	468	}
469	469
470		static const tms34010_config tms_config =
	470	static const tms340x0_config tms_config =
471	471	{
472	472	FALSE, /* halt on reset */
473	473	"screen", /* the screen operated on */
r31176	r31177
508	508
509	509	/* video hardware */
510	510	MCFG_CPU_ADD("tms", TMS34010, XTAL_50MHz)
511		MCFG_~~CPU~~_CONFIG(tms_config)
	511	MCFG_TMS340X0_CONFIG(tms_config)
512	512	MCFG_CPU_PROGRAM_MAP(tms_program_map)
513	513
514	514	MCFG_SCREEN_ADD("screen", RASTER)

trunk/src/mame/drivers/btoads.c
r31176	r31177
299	299	*
300	300	*************************************/
301	301
302		static const tms34010_config tms_config =
	302	static const tms340x0_config tms_config =
303	303	{
304	304	FALSE, /* halt on reset */
305	305	"screen", /* the screen operated on */
r31176	r31177
323	323	static MACHINE_CONFIG_START( btoads, btoads_state )
324	324
325	325	MCFG_CPU_ADD("maincpu", TMS34020, CPU_CLOCK/2)
326		MCFG_~~CPU~~_CONFIG(tms_config)
	326	MCFG_TMS340X0_CONFIG(tms_config)
327	327	MCFG_CPU_PROGRAM_MAP(main_map)
328	328
329	329	MCFG_CPU_ADD("audiocpu", Z80, SOUND_CLOCK/4)

trunk/src/mame/drivers/midyunit.c
r31176	r31177
1066	1066	*
1067	1067	*************************************/
1068	1068
1069		static const tms34010_config zunit_tms_config =
	1069	static const tms340x0_config zunit_tms_config =
1070	1070	{
1071	1071	FALSE, /* halt on reset */
1072	1072	"screen", /* the screen operated on */
r31176	r31177
1079	1079	midyunit_from_shiftreg /* read from shiftreg function */
1080	1080	};
1081	1081
1082		static const tms34010_config yunit_tms_config =
	1082	static const tms340x0_config yunit_tms_config =
1083	1083	{
1084	1084	FALSE, /* halt on reset */
1085	1085	"screen", /* the screen operated on */
r31176	r31177
1104	1104
1105	1105	/* basic machine hardware */
1106	1106	MCFG_CPU_ADD("maincpu", TMS34010, FAST_MASTER_CLOCK)
1107		MCFG_~~CPU~~_CONFIG(zunit_tms_config)
	1107	MCFG_TMS340X0_CONFIG(zunit_tms_config)
1108	1108	MCFG_CPU_PROGRAM_MAP(main_map)
1109	1109
1110	1110	MCFG_MACHINE_RESET_OVERRIDE(midyunit_state,midyunit)
r31176	r31177
1140	1140
1141	1141	/* basic machine hardware */
1142	1142	MCFG_CPU_ADD("maincpu", TMS34010, SLOW_MASTER_CLOCK)
1143		MCFG_~~CPU~~_CONFIG(yunit_tms_config)
	1143	MCFG_TMS340X0_CONFIG(yunit_tms_config)
1144	1144	MCFG_CPU_PROGRAM_MAP(main_map)
1145	1145
1146	1146	MCFG_MACHINE_RESET_OVERRIDE(midyunit_state,midyunit)

trunk/src/mame/drivers/artmagic.c
r31176	r31177
475	475	*
476	476	*************************************/
477	477
478		static const tms34010_config tms_config =
	478	static const tms340x0_config tms_config =
479	479	{
480	480	TRUE, /* halt on reset */
481	481	"screen", /* the screen operated on */
r31176	r31177
827	827	MCFG_CPU_PROGRAM_MAP(main_map)
828	828
829	829	MCFG_CPU_ADD("tms", TMS34010, MASTER_CLOCK_40MHz)
830		MCFG_~~CPU~~_CONFIG(tms_config)
	830	MCFG_TMS340X0_CONFIG(tms_config)
831	831	MCFG_CPU_PROGRAM_MAP(tms_map)
832	832
833	833	MCFG_QUANTUM_TIME(attotime::from_hz(6000))

trunk/src/mame/drivers/coolpool.c
r31176	r31177
794	794	*
795	795	*************************************/
796	796
797		static const tms34010_config tms_config_amerdart =
	797	static const tms340x0_config tms_config_amerdart =
798	798	{
799	799	FALSE, /* halt on reset */
800	800	"screen", /* the screen operated on */
r31176	r31177
808	808	};
809	809
810	810
811		static const tms34010_config tms_config_coolpool =
	811	static const tms340x0_config tms_config_coolpool =
812	812	{
813	813	FALSE, /* halt on reset */
814	814	"screen", /* the screen operated on */
r31176	r31177
833	833
834	834	/* basic machine hardware */
835	835	MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
836		MCFG_~~CPU~~_CONFIG(tms_config_amerdart)
	836	MCFG_TMS340X0_CONFIG(tms_config_amerdart)
837	837	MCFG_CPU_PROGRAM_MAP(amerdart_map)
838	838
839	839	MCFG_CPU_ADD("dsp", TMS32015, XTAL_40MHz/2)
r31176	r31177
864	864
865	865	/* basic machine hardware */
866	866	MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
867		MCFG_~~CPU~~_CONFIG(tms_config_coolpool)
	867	MCFG_TMS340X0_CONFIG(tms_config_coolpool)
868	868	MCFG_CPU_PROGRAM_MAP(coolpool_map)
869	869
870	870	MCFG_CPU_ADD("dsp", TMS32026,XTAL_40MHz)

trunk/src/mame/drivers/midtunit.c
r31176	r31177
579	579	*
580	580	*************************************/
581	581
582		static const tms34010_config tms_config =
	582	static const tms340x0_config tms_config =
583	583	{
584	584	FALSE, /* halt on reset */
585	585	"screen", /* the screen operated on */
r31176	r31177
604	604
605	605	/* basic machine hardware */
606	606	MCFG_CPU_ADD("maincpu", TMS34010, CPU_CLOCK)
607		MCFG_~~CPU~~_CONFIG(tms_config)
	607	MCFG_TMS340X0_CONFIG(tms_config)
608	608	MCFG_CPU_PROGRAM_MAP(main_map)
609	609
610	610	MCFG_MACHINE_RESET_OVERRIDE(midtunit_state,midtunit)

trunk/src/mame/drivers/tickee.c
r31176	r31177
735	735	*
736	736	*************************************/
737	737
738		static const tms34010_config tms_config =
	738	static const tms340x0_config tms_config =
739	739	{
740	740	FALSE, /* halt on reset */
741	741	"screen", /* the screen operated on */
r31176	r31177
749	749	};
750	750
751	751
752		static const tms34010_config rapidfir_tms_config =
	752	static const tms340x0_config rapidfir_tms_config =
753	753	{
754	754	FALSE, /* halt on reset */
755	755	"screen", /* the screen operated on */
r31176	r31177
774	774
775	775	/* basic machine hardware */
776	776	MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
777		MCFG_~~CPU~~_CONFIG(tms_config)
	777	MCFG_TMS340X0_CONFIG(tms_config)
778	778	MCFG_CPU_PROGRAM_MAP(tickee_map)
779	779
780	780	MCFG_MACHINE_RESET_OVERRIDE(tickee_state,tickee)
r31176	r31177
819	819
820	820	/* basic machine hardware */
821	821	MCFG_CPU_ADD("maincpu", TMS34010, XTAL_50MHz)
822		MCFG_~~CPU~~_CONFIG(rapidfir_tms_config)
	822	MCFG_TMS340X0_CONFIG(rapidfir_tms_config)
823	823	MCFG_CPU_PROGRAM_MAP(rapidfir_map)
824	824
825	825	MCFG_MACHINE_RESET_OVERRIDE(tickee_state,rapidfir)
r31176	r31177
846	846
847	847	/* basic machine hardware */
848	848	MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
849		MCFG_~~CPU~~_CONFIG(tms_config)
	849	MCFG_TMS340X0_CONFIG(tms_config)
850	850	MCFG_CPU_PROGRAM_MAP(mouseatk_map)
851	851
852	852	MCFG_MACHINE_RESET_OVERRIDE(tickee_state,tickee)

trunk/src/mame/drivers/micro3d.c
r31176	r31177
286	286	*
287	287	*************************************/
288	288
289		static const tms34010_config vgb_config =
	289	static const tms340x0_config vgb_config =
290	290	{
291	291	FALSE, /* halt on reset */
292	292	"screen", /* the screen operated on */
r31176	r31177
312	312	MCFG_CPU_VBLANK_INT_DRIVER("screen", micro3d_state, micro3d_vblank)
313	313
314	314	MCFG_CPU_ADD("vgb", TMS34010, XTAL_40MHz)
315		MCFG_~~CPU~~_CONFIG(vgb_config)
	315	MCFG_TMS340X0_CONFIG(vgb_config)
316	316	MCFG_CPU_PROGRAM_MAP(vgbmem)
317	317
318	318	MCFG_CPU_ADD("drmath", AM29000, XTAL_32MHz / 2)

trunk/src/mame/drivers/exterm.c
r31176	r31177
400	400	*
401	401	*************************************/
402	402
403		static const tms34010_config master_config =
	403	static const tms340x0_config master_config =
404	404	{
405	405	FALSE, /* halt on reset */
406	406	"screen", /* the screen operated on */
r31176	r31177
413	413	exterm_from_shiftreg_master /* read from shiftreg function */
414	414	};
415	415
416		static const tms34010_config slave_config =
	416	static const tms340x0_config slave_config =
417	417	{
418	418	TRUE, /* halt on reset */
419	419	"screen", /* the screen operated on */
r31176	r31177
438	438
439	439	/* basic machine hardware */
440	440	MCFG_CPU_ADD("maincpu", TMS34010, 40000000)
441		MCFG_~~CPU~~_CONFIG(master_config)
	441	MCFG_TMS340X0_CONFIG(master_config)
442	442	MCFG_CPU_PROGRAM_MAP(master_map)
443	443
444	444	MCFG_CPU_ADD("slave", TMS34010, 40000000)
445		MCFG_~~CPU~~_CONFIG(slave_config)
	445	MCFG_TMS340X0_CONFIG(slave_config)
446	446	MCFG_CPU_PROGRAM_MAP(slave_map)
447	447
448	448	MCFG_CPU_ADD("audiocpu", M6502, 2000000)

trunk/src/mame/drivers/harddriv.c
r31176	r31177
338	338	*************************************/
339	339
340	340	/* used on the medium-resolution driver boards */
341		static const tms34010_config gsp_config_driver =
	341	static const tms340x0_config gsp_config_driver =
342	342	{
343	343	TRUE, /* halt on reset */
344	344	"screen", /* the screen operated on */
r31176	r31177
353	353
354	354
355	355	/* used on the low-resolution multisync boards for harddrivc, racedrivc, steeltal */
356		static const tms34010_config gsp_config_multisync =
	356	static const tms340x0_config gsp_config_multisync =
357	357	{
358	358	TRUE, /* halt on reset */
359	359	"screen", /* the screen operated on */
r31176	r31177
368	368
369	369
370	370	/* used on the low-resolution multisync board for stunrun */
371		static const tms34010_config gsp_config_multisync_stunrun =
	371	static const tms340x0_config gsp_config_multisync_stunrun =
372	372	{
373	373	TRUE, /* halt on reset */
374	374	"screen", /* the screen operated on */
r31176	r31177
382	382	};
383	383
384	384
385		static const tms34010_config msp_config =
	385	static const tms340x0_config msp_config =
386	386	{
387	387	TRUE, /* halt on reset */
388	388	"screen", /* the screen operated on */
r31176	r31177
1296	1296
1297	1297	MCFG_CPU_ADD("gsp", TMS34010, HARDDRIV_GSP_CLOCK)
1298	1298	MCFG_CPU_PROGRAM_MAP(driver_gsp_map)
1299		MCFG_~~CPU~~_CONFIG(gsp_config_driver)
	1299	MCFG_TMS340X0_CONFIG(gsp_config_driver)
1300	1300
1301	1301	MCFG_QUANTUM_TIME(attotime::from_hz(30000))
1302	1302
r31176	r31177
1328	1328	/* basic machine hardware */
1329	1329	MCFG_CPU_ADD("msp", TMS34010, XTAL_50MHz)
1330	1330	MCFG_CPU_PROGRAM_MAP(driver_msp_map)
1331		MCFG_~~CPU~~_CONFIG(msp_config)
	1331	MCFG_TMS340X0_CONFIG(msp_config)
1332	1332	MACHINE_CONFIG_END
1333	1333
1334	1334
r31176	r31177
1340	1340	MCFG_CPU_PROGRAM_MAP(multisync_68k_map)
1341	1341
1342	1342	MCFG_CPU_MODIFY("gsp")
1343		MCFG_~~CPU~~_CONFIG(gsp_config_multisync)
	1343	MCFG_TMS340X0_CONFIG(gsp_config_multisync)
1344	1344	MCFG_CPU_PROGRAM_MAP(multisync_gsp_map)
1345	1345
1346	1346	/* video hardware */
r31176	r31177
1355	1355	/* basic machine hardware */
1356	1356	MCFG_CPU_ADD("msp", TMS34010, XTAL_50MHz)
1357	1357	MCFG_CPU_PROGRAM_MAP(driver_msp_map)
1358		MCFG_~~CPU~~_CONFIG(msp_config)
	1358	MCFG_TMS340X0_CONFIG(msp_config)
1359	1359	MACHINE_CONFIG_END
1360	1360
1361	1361
r31176	r31177
1530	1530
1531	1531	/* basic machine hardware / / multisync board without MSP */
1532	1532	MCFG_CPU_MODIFY("gsp")
1533		MCFG_~~CPU~~_CONFIG(gsp_config_multisync_stunrun)
	1533	MCFG_TMS340X0_CONFIG(gsp_config_multisync_stunrun)
1534	1534	MCFG_FRAGMENT_ADD( adsp ) /* ADSP board */
1535	1535
1536	1536	/* video hardware */

trunk/src/mame/drivers/midxunit.c
r31176	r31177
239	239	*
240	240	*************************************/
241	241
242		static const tms34010_config tms_config =
	242	static const tms340x0_config tms_config =
243	243	{
244	244	FALSE, /* halt on reset */
245	245	"screen", /* the screen operated on */
r31176	r31177
264	264
265	265	/* basic machine hardware */
266	266	MCFG_CPU_ADD("maincpu", TMS34020, 40000000)
267		MCFG_~~CPU~~_CONFIG(tms_config)
	267	MCFG_TMS340X0_CONFIG(tms_config)
268	268	MCFG_CPU_PROGRAM_MAP(main_map)
269	269
270	270	MCFG_MACHINE_RESET_OVERRIDE(midxunit_state,midxunit)

trunk/src/mame/drivers/potgoldu.c
r31176	r31177
64	64	INPUT_PORTS_END
65	65
66	66
67		static const tms34010_config tms_config =
	67	static const tms340x0_config tms_config =
68	68	{
69	69	FALSE, /* halt on reset */
70	70	"screen", /* the screen operated on */
r31176	r31177
82	82
83	83	/* basic machine hardware */
84	84	MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
85		MCFG_~~CPU~~_CONFIG(tms_config)
	85	MCFG_TMS340X0_CONFIG(tms_config)
86	86	MCFG_CPU_PROGRAM_MAP(potgold_map)
87	87
88	88

trunk/src/mame/drivers/lethalj.c
r31176	r31177
629	629	*
630	630	*************************************/
631	631
632		static const tms34010_config tms_config =
	632	static const tms340x0_config tms_config =
633	633	{
634	634	FALSE, /* halt on reset */
635	635	"screen", /* the screen operated on */
r31176	r31177
641	641	NULL /* read from shiftreg function */
642	642	};
643	643
644		static const tms34010_config tms_config_lethalj =
	644	static const tms340x0_config tms_config_lethalj =
645	645	{
646	646	FALSE, /* halt on reset */
647	647	"screen", /* the screen operated on */
r31176	r31177
665	665
666	666	/* basic machine hardware */
667	667	MCFG_CPU_ADD("maincpu", TMS34010, MASTER_CLOCK)
668		MCFG_~~CPU~~_CONFIG(tms_config)
	668	MCFG_TMS340X0_CONFIG(tms_config)
669	669	MCFG_CPU_PROGRAM_MAP(lethalj_map)
670	670
671	671	MCFG_TICKET_DISPENSER_ADD("ticket", attotime::from_msec(200), TICKET_MOTOR_ACTIVE_HIGH, TICKET_STATUS_ACTIVE_HIGH)
r31176	r31177
695	695	static MACHINE_CONFIG_DERIVED( lethalj, gameroom )
696	696
697	697	MCFG_CPU_MODIFY("maincpu")
698		MCFG_~~CPU~~_CONFIG(tms_config_lethalj)
	698	MCFG_TMS340X0_CONFIG(tms_config_lethalj)
699	699
700	700	MCFG_SCREEN_MODIFY("screen")
701	701	MCFG_SCREEN_RAW_PARAMS(VIDEO_CLOCK_LETHALJ, 689, 0, 512, 259, 0, 236)

trunk/src/mame/drivers/skeetsht.c
r31176	r31177
219	219	*
220	220	*************************************/
221	221
222		static const tms34010_config tms_config =
	222	static const tms340x0_config tms_config =
223	223	{
224	224	TRUE, /* halt on reset */
225	225	"screen", /* the screen operated on */
r31176	r31177
248	248	MCFG_MC68HC11_CONFIG( 0, 0x100, 0x01 ) // And 512 bytes EEPROM? (68HC11A1)
249	249
250	250	MCFG_CPU_ADD("tms", TMS34010, 48000000)
251		MCFG_~~CPU~~_CONFIG(tms_config)
	251	MCFG_TMS340X0_CONFIG(tms_config)
252	252	MCFG_CPU_PROGRAM_MAP(tms_program_map)
253	253
254	254

trunk/src/mame/drivers/xtheball.c
r31176	r31177
322	322	*
323	323	*************************************/
324	324
325		static const tms34010_config tms_config =
	325	static const tms340x0_config tms_config =
326	326	{
327	327	FALSE, /* halt on reset */
328	328	"screen", /* the screen operated on */
r31176	r31177
346	346	static MACHINE_CONFIG_START( xtheball, xtheball_state )
347	347
348	348	MCFG_CPU_ADD("maincpu", TMS34010, 40000000)
349		MCFG_~~CPU~~_CONFIG(tms_config)
	349	MCFG_TMS340X0_CONFIG(tms_config)
350	350	MCFG_CPU_PROGRAM_MAP(main_map)
351	351	MCFG_CPU_PERIODIC_INT_DRIVER(xtheball_state, irq1_line_hold, 15000)
352	352

trunk/src/mame/drivers/jpmimpct.c
r31176	r31177
826	826	drvstate->update_irqs();
827	827	}
828	828
829		static const tms34010_config tms_config =
	829	static const tms340x0_config tms_config =
830	830	{
831	831	TRUE, /* halt on reset */
832	832	"screen", /* the screen operated on */
r31176	r31177
851	851	MCFG_CPU_PROGRAM_MAP(m68k_program_map)
852	852
853	853	MCFG_CPU_ADD("dsp", TMS34010, 40000000)
854		MCFG_~~CPU~~_CONFIG(tms_config)
	854	MCFG_TMS340X0_CONFIG(tms_config)
855	855	MCFG_CPU_PROGRAM_MAP(tms_program_map)
856	856
857	857	MCFG_QUANTUM_TIME(attotime::from_hz(30000))

trunk/src/mame/drivers/metalmx.c
r31176	r31177
688	688	*
689	689	*************************************/
690	690
691		static const tms34010_config gsp_config =
	691	static const tms340x0_config gsp_config =
692	692	{
693	693	TRUE, /* halt on reset */
694	694	"screen", /* the screen operated on */
r31176	r31177
715	715	MCFG_CPU_DATA_MAP(adsp_data_map)
716	716
717	717	MCFG_CPU_ADD("gsp", TMS34020, 40000000) /* Unverified */
718		MCFG_~~CPU~~_CONFIG(gsp_config)
	718	MCFG_TMS340X0_CONFIG(gsp_config)
719	719	MCFG_CPU_PROGRAM_MAP(gsp_map)
720	720
721	721	MCFG_CPU_ADD("dsp32c_1", DSP32C, 40000000) /* Unverified */

trunk/src/mame/machine/inder_vid.c
r31176	r31177
90	90	}
91	91
92	92
93		static const tms34010_config tms_config_megaphx =
	93	static const tms340x0_config tms_config_megaphx =
94	94	{
95	95	TRUE, /* halt on reset */
96	96	"inder_vid:inder_screen", /* the screen operated on */
r31176	r31177
110	110
111	111	static MACHINE_CONFIG_FRAGMENT( inder_vid )
112	112	MCFG_CPU_ADD("tms", TMS34010, XTAL_40MHz)
113		MCFG_~~CPU~~_CONFIG(tms_config_megaphx)
	113	MCFG_TMS340X0_CONFIG(tms_config_megaphx)
114	114	MCFG_CPU_PROGRAM_MAP(megaphx_tms_map)
115	115
116	116	MCFG_SCREEN_ADD("inder_screen", RASTER)

trunk/src/mame/video/exterm.c
r31176	r31177
79	79	int x;
80	80
81	81	/* get parameters for the slave CPU */
82		tm~~s34010~~_get_display_params(~~state->m_slave,~~ &fgparams);
	82	state->m_slave->get_display_params(&fgparams);
83	83
84	84	/* compute info about the slave vram */
85	85	if (fgparams.enabled && scanline >= fgparams.veblnk && scanline < fgparams.vsblnk && fgparams.heblnk < fgparams.hsblnk)

trunk/src/emu/cpu/tms34010/34010ops.c
r31176	r31177
16	16	#define ZEXTEND(val,width) if (width) (val) &= ((UINT32)0xffffffff >> (32 - (width)))
17	17	#define SEXTEND(val,width) if (width) (val) = (INT32)((val) << (32 - (width))) >> (32 - (width))
18	18
19		#define SXYTOL(T,val) ((((INT16)(val).y * (T)->convsp) + ((INT16)(val).x << (T)->pixelshift)) + OFFSET(T))
20		#define DXYTOL(T,val) ((((INT16)(val).y * (T)->convdp) + ((INT16)(val).x << (T)->pixelshift)) + OFFSET(T))
21		#define MXYTOL(T,val) ((((INT16)(val).y * (T)->convmp) + ((INT16)(val).x << (T)->pixelshift)) + OFFSET(T))
	19	#define SXYTOL(val) ((((INT16)(val).y * m_convsp) + ((INT16)(val).x << m_pixelshift)) + OFFSET())
	20	#define DXYTOL(val) ((((INT16)(val).y * m_convdp) + ((INT16)(val).x << m_pixelshift)) + OFFSET())
	21	#define MXYTOL(val) ((((INT16)(val).y * m_convmp) + ((INT16)(val).x << m_pixelshift)) + OFFSET())
22	22
23		#define COUNT_CYCLES(T,x) (T)->icount -= x
24		#define COUNT_UNKNOWN_CYCLES(T,x) COUNT_CYCLES(T,x)
	23	#define COUNT_CYCLES(x) m_icount -= x
	24	#define COUNT_UNKNOWN_CYCLES(x) COUNT_CYCLES(x)
25	25
26		#define CORRECT_ODD_PC(T,x) do { if (~~(T)->~~pc & 0x0f) logerror("%s to PC=%08X\n", x, ~~(T)->~~pc); ~~(T)->~~pc &= ~0x0f; } while (0)
	26	#define CORRECT_ODD_PC(x) do { if (m_pc & 0x0f) logerror("%s to PC=%08X\n", x, m_pc); m_pc &= ~0x0f; } while (0)
27	27
28	28
29	29
r31176	r31177
33	33
34	34	#define SIGN(val) ((val) & 0x80000000)
35	35
36		#define CLR_Z(T) (T)->st &= ~STBIT_Z
37		#define CLR_V(T) (T)->st &= ~STBIT_V
38		#define CLR_C(T) (T)->st &= ~STBIT_C
39		#define CLR_N(T) (T)->st &= ~STBIT_N
40		#define CLR_NZ(T) (T)->st &= ~(STBIT_N \| STBIT_Z)
41		#define CLR_CZ(T) (T)->st &= ~(STBIT_C \| STBIT_Z)
42		#define CLR_ZV(T) (T)->st &= ~(STBIT_Z \| STBIT_V)
43		#define CLR_NZV(T) (T)->st &= ~(STBIT_N \| STBIT_Z \| STBIT_V)
44		#define CLR_NCZ(T) (T)->st &= ~(STBIT_N \| STBIT_C \| STBIT_Z)
45		#define CLR_NCZV(T) (T)->st &= ~(STBIT_N \| STBIT_C \| STBIT_Z \| STBIT_V)
	36	#define CLR_Z() m_st &= ~STBIT_Z
	37	#define CLR_V() m_st &= ~STBIT_V
	38	#define CLR_C() m_st &= ~STBIT_C
	39	#define CLR_N() m_st &= ~STBIT_N
	40	#define CLR_NZ() m_st &= ~(STBIT_N \| STBIT_Z)
	41	#define CLR_CZ() m_st &= ~(STBIT_C \| STBIT_Z)
	42	#define CLR_ZV() m_st &= ~(STBIT_Z \| STBIT_V)
	43	#define CLR_NZV() m_st &= ~(STBIT_N \| STBIT_Z \| STBIT_V)
	44	#define CLR_NCZ() m_st &= ~(STBIT_N \| STBIT_C \| STBIT_Z)
	45	#define CLR_NCZV() m_st &= ~(STBIT_N \| STBIT_C \| STBIT_Z \| STBIT_V)
46	46
47		#define SET_V_BIT_LO(T,val,bit) (T)->st \|= ((val) << (28 - (bit))) & STBIT_V
48		#define SET_V_BIT_HI(T,val,bit) (T)->st \|= ((val) >> ((bit) - 28)) & STBIT_V
49		#define SET_V_LOG(T,val) (T)->st \|= (val) << 28
50		#define SET_Z_BIT_LO(T,val,bit) (T)->st \|= ((val) << (29 - (bit))) & STBIT_Z
51		#define SET_Z_BIT_HI(T,val,bit) (T)->st \|= ((val) >> ((bit) - 29)) & STBIT_Z
52		#define SET_Z_LOG(T,val) (T)->st \|= (val) << 29
53		#define SET_C_BIT_LO(T,val,bit) (T)->st \|= ((val) << (30 - (bit))) & STBIT_C
54		#define SET_C_BIT_HI(T,val,bit) (T)->st \|= ((val) >> ((bit) - 30)) & STBIT_C
55		#define SET_C_LOG(T,val) (T)->st \|= (val) << 30
56		#define SET_N_BIT(T,val,bit) (T)->st \|= ((val) << (31 - (bit))) & STBIT_N
57		#define SET_N_LOG(T,val) (T)->st \|= (val) << 31
	47	#define SET_V_BIT_LO(val,bit) m_st \|= ((val) << (28 - (bit))) & STBIT_V
	48	#define SET_V_BIT_HI(val,bit) m_st \|= ((val) >> ((bit) - 28)) & STBIT_V
	49	#define SET_V_LOG(val) m_st \|= (val) << 28
	50	#define SET_Z_BIT_LO(val,bit) m_st \|= ((val) << (29 - (bit))) & STBIT_Z
	51	#define SET_Z_BIT_HI(val,bit) m_st \|= ((val) >> ((bit) - 29)) & STBIT_Z
	52	#define SET_Z_LOG(val) m_st \|= (val) << 29
	53	#define SET_C_BIT_LO(val,bit) m_st \|= ((val) << (30 - (bit))) & STBIT_C
	54	#define SET_C_BIT_HI(val,bit) m_st \|= ((val) >> ((bit) - 30)) & STBIT_C
	55	#define SET_C_LOG(val) m_st \|= (val) << 30
	56	#define SET_N_BIT(val,bit) m_st \|= ((val) << (31 - (bit))) & STBIT_N
	57	#define SET_N_LOG(val) m_st \|= (val) << 31
58	58
59		#define SET_Z_VAL(T,val) SET_Z_LOG(T, (val) == 0)
60		#define SET_N_VAL(T,val) SET_N_BIT(T, val, 31)
61		#define SET_NZ_VAL(T,val) SET_Z_VAL(T, val); SET_N_VAL(T, val)
62		#define SET_V_SUB(T,a,b,r) SET_V_BIT_HI(T, ((a) ^ (b)) & ((a) ^ (r)), 31)
63		#define SET_V_ADD(T,a,b,r) SET_V_BIT_HI(T, ~((a) ^ (b)) & ((a) ^ (r)), 31)
64		#define SET_C_SUB(T,a,b) SET_C_LOG(T, (UINT32)(b) > (UINT32)(a))
65		#define SET_C_ADD(T,a,b) SET_C_LOG(T, (UINT32)~(a) < (UINT32)(b))
66		#define SET_NZV_SUB(T,a,b,r) SET_NZ_VAL(T,r); SET_V_SUB(T,a,b,r)
67		#define SET_NZCV_SUB(T,a,b,r) SET_NZV_SUB(T,a,b,r); SET_C_SUB(T,a,b)
68		#define SET_NZCV_ADD(T,a,b,r) SET_NZ_VAL(T,r); SET_V_ADD(T,a,b,r); SET_C_ADD(T,a,b)
	59	#define SET_Z_VAL(val) SET_Z_LOG((val) == 0)
	60	#define SET_N_VAL(val) SET_N_BIT(val, 31)
	61	#define SET_NZ_VAL(val) SET_Z_VAL(val); SET_N_VAL(val)
	62	#define SET_V_SUB(a,b,r) SET_V_BIT_HI(((a) ^ (b)) & ((a) ^ (r)), 31)
	63	#define SET_V_ADD(a,b,r) SET_V_BIT_HI(~((a) ^ (b)) & ((a) ^ (r)), 31)
	64	#define SET_C_SUB(a,b) SET_C_LOG((UINT32)(b) > (UINT32)(a))
	65	#define SET_C_ADD(a,b) SET_C_LOG((UINT32)~(a) < (UINT32)(b))
	66	#define SET_NZV_SUB(a,b,r) SET_NZ_VAL(r); SET_V_SUB(a,b,r)
	67	#define SET_NZCV_SUB(a,b,r) SET_NZV_SUB(a,b,r); SET_C_SUB(a,b)
	68	#define SET_NZCV_ADD(a,b,r) SET_NZ_VAL(r); SET_V_ADD(a,b,r); SET_C_ADD(a,b)
69	69
70	70	static const UINT8 fw_inc[32] = { 32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 };
71	71
r31176	r31177
74	74	UNIMPLEMENTED INSTRUCTION
75	75	***************************************************************************/
76	76
77		~~static~~ void ~~unimpl(~~tms34010_~~stat~~e *tms, UINT16 op)
	77	void tms340x0_device::unimpl(UINT16 op)
78	78	{
79	79	/* kludge for Super High Impact -- this doesn't seem to cause */
80	80	/* an illegal opcode exception */
81		if (tm~~s->~~direct->read_decrypted_word(TOBYTE(tm~~s->~~pc - 0x10)) == 0x0007)
	81	if (m_direct->read_decrypted_word(TOBYTE(m_pc - 0x10)) == 0x0007)
82	82	return;
83	83
84	84	/* 9 Ball Shootout calls to FFDF7468, expecting it */
85	85	/* to execute the next instruction from FFDF7470 */
86	86	/* but the instruction at FFDF7460 is an 0x0001 */
87		if (tm~~s->~~direct->read_decrypted_word(TOBYTE(tm~~s->~~pc - 0x10)) == 0x0001)
	87	if (m_direct->read_decrypted_word(TOBYTE(m_pc - 0x10)) == 0x0001)
88	88	return;
89	89
90		PUSH(tms, tms->pc);
91		PUSH(tms, tms->st);
92		RESET_ST(tms);
93		tms->pc = RLONG(tms, 0xfffffc20);
94		COUNT_UNKNOWN_CYCLES(tms,16);
	90	PUSH(m_pc);
	91	PUSH(m_st);
	92	RESET_ST();
	93	m_pc = RLONG(0xfffffc20);
	94	COUNT_UNKNOWN_CYCLES(16);
95	95
96	96	/* extra check to prevent bad things */
97		if (tm~~s->~~pc == 0 \|\| opcode_table[tm~~s->~~direct->read_decrypted_word(TOBYTE(tm~~s->~~pc)) >> 4] == unimpl)
	97	if (m_pc == 0 \|\| s_opcode_table[m_direct->read_decrypted_word(TOBYTE(m_pc)) >> 4] == &tms34010_device::unimpl)
98	98	{
99		tms->device->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
100		debugger_break(tms->device->machine());
	99	set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
	100	debugger_break(machine());
101	101	}
102	102	}
103	103
r31176	r31177
109	109
110	110	#define ADD_XY(R) \
111	111	{ \
112		XY a = R##REG_XY(tms,SRCREG(op)); \
113		XY *b = &R##REG_XY(tms,DSTREG(op)); \
114		CLR_NCZV(tms); \
	112	XY a = R##REG_XY(SRCREG(op)); \
	113	XY *b = &R##REG_XY(DSTREG(op)); \
	114	CLR_NCZV(); \
115	115	b->x += a.x; \
116	116	b->y += a.y; \
117		SET_N_LOG(tms, b->x == 0); \
118		SET_C_BIT_LO(tms, b->y, 15); \
119		SET_Z_LOG(tms, b->y == 0); \
120		SET_V_BIT_LO(tms, b->x, 15); \
121		COUNT_CYCLES(tms,1); \
	117	SET_N_LOG(b->x == 0); \
	118	SET_C_BIT_LO(b->y, 15); \
	119	SET_Z_LOG(b->y == 0); \
	120	SET_V_BIT_LO(b->x, 15); \
	121	COUNT_CYCLES(1); \
122	122	}
123		static void add_xy_a(tms34010_state *tms, UINT16 op) { ADD_XY(A); }
124		static void add_xy_b(tms34010_state *tms, UINT16 op) { ADD_XY(B); }
	123	void tms340x0_device::add_xy_a(UINT16 op) { ADD_XY(A); }
	124	void tms340x0_device::add_xy_b(UINT16 op) { ADD_XY(B); }
125	125
126	126	#define SUB_XY(R) \
127	127	{ \
128		XY a = R##REG_XY(tms,SRCREG(op)); \
129		XY *b = &R##REG_XY(tms,DSTREG(op)); \
130		CLR_NCZV(tms); \
131		SET_N_LOG(tms, a.x == b->x); \
132		SET_C_LOG(tms, a.y > b->y); \
133		SET_Z_LOG(tms, a.y == b->y); \
134		SET_V_LOG(tms, a.x > b->x); \
	128	XY a = R##REG_XY(SRCREG(op)); \
	129	XY *b = &R##REG_XY(DSTREG(op)); \
	130	CLR_NCZV(); \
	131	SET_N_LOG(a.x == b->x); \
	132	SET_C_LOG(a.y > b->y); \
	133	SET_Z_LOG(a.y == b->y); \
	134	SET_V_LOG(a.x > b->x); \
135	135	b->x -= a.x; \
136	136	b->y -= a.y; \
137		COUNT_CYCLES(~~tms,~~1); \
	137	COUNT_CYCLES(1); \
138	138	}
139		static void sub_xy_a(tms34010_state *tms, UINT16 op) { SUB_XY(A); }
140		static void sub_xy_b(tms34010_state *tms, UINT16 op) { SUB_XY(B); }
	139	void tms340x0_device::sub_xy_a(UINT16 op) { SUB_XY(A); }
	140	void tms340x0_device::sub_xy_b(UINT16 op) { SUB_XY(B); }
141	141
142	142	#define CMP_XY(R) \
143	143	{ \
144	144	INT16 res; \
145		XY a = R##REG_XY(tms,DSTREG(op)); \
146		XY b = R##REG_XY(tms,SRCREG(op)); \
147		CLR_NCZV(tms); \
	145	XY a = R##REG_XY(DSTREG(op)); \
	146	XY b = R##REG_XY(SRCREG(op)); \
	147	CLR_NCZV(); \
148	148	res = a.x-b.x; \
149		SET_N_LOG(tms, res == 0); \
150		SET_V_BIT_LO(tms, res, 15); \
	149	SET_N_LOG(res == 0); \
	150	SET_V_BIT_LO(res, 15); \
151	151	res = a.y-b.y; \
152		SET_Z_LOG(tms, res == 0); \
153		SET_C_BIT_LO(tms, res, 15); \
154		COUNT_CYCLES(tms,1); \
	152	SET_Z_LOG(res == 0); \
	153	SET_C_BIT_LO(res, 15); \
	154	COUNT_CYCLES(1); \
155	155	}
156		static void cmp_xy_a(tms34010_state *tms, UINT16 op) { CMP_XY(A); }
157		static void cmp_xy_b(tms34010_state *tms, UINT16 op) { CMP_XY(B); }
	156	void tms340x0_device::cmp_xy_a(UINT16 op) { CMP_XY(A); }
	157	void tms340x0_device::cmp_xy_b(UINT16 op) { CMP_XY(B); }
158	158
159	159	#define CPW(R) \
160	160	{ \
161	161	INT32 res = 0; \
162		INT16 x = R##REG_X(tms,SRCREG(op)); \
163		INT16 y = R##REG_Y(tms,SRCREG(op)); \
	162	INT16 x = R##REG_X(SRCREG(op)); \
	163	INT16 y = R##REG_Y(SRCREG(op)); \
164	164	\
165		CLR_V(tms); \
166		res \|= ((WSTART_X(tms) > x) ? 0x20 : 0); \
167		res \|= ((x > WEND_X(tms)) ? 0x40 : 0); \
168		res \|= ((WSTART_Y(tms) > y) ? 0x80 : 0); \
169		res \|= ((y > WEND_Y(tms)) ? 0x100 : 0); \
170		R##REG(tms,DSTREG(op)) = res; \
171		SET_V_LOG(tms, res != 0); \
172		COUNT_CYCLES(tms,1); \
	165	CLR_V(); \
	166	res \|= ((WSTART_X() > x) ? 0x20 : 0); \
	167	res \|= ((x > WEND_X()) ? 0x40 : 0); \
	168	res \|= ((WSTART_Y() > y) ? 0x80 : 0); \
	169	res \|= ((y > WEND_Y()) ? 0x100 : 0); \
	170	R##REG(DSTREG(op)) = res; \
	171	SET_V_LOG(res != 0); \
	172	COUNT_CYCLES(1); \
173	173	}
174		static void cpw_a(tms34010_state *tms, UINT16 op) { CPW(A); }
175		static void cpw_b(tms34010_state *tms, UINT16 op) { CPW(B); }
	174	void tms340x0_device::cpw_a(UINT16 op) { CPW(A); }
	175	void tms340x0_device::cpw_b(UINT16 op) { CPW(B); }
176	176
177	177	#define CVXYL(R) \
178	178	{ \
179		R##REG(tms,DSTREG(op)) = DXYTOL(tms,R##REG_XY(tms,SRCREG(op))); \
180		COUNT_CYCLES(tms,3); \
	179	R##REG(DSTREG(op)) = DXYTOL(R##REG_XY(SRCREG(op))); \
	180	COUNT_CYCLES(3); \
181	181	}
182		static void cvxyl_a(tms34010_state *tms, UINT16 op) { CVXYL(A); }
183		static void cvxyl_b(tms34010_state *tms, UINT16 op) { CVXYL(B); }
	182	void tms340x0_device::cvxyl_a(UINT16 op) { CVXYL(A); }
	183	void tms340x0_device::cvxyl_b(UINT16 op) { CVXYL(B); }
184	184
185	185	#define MOVX(R) \
186	186	{ \
187		R##REG(tms,DSTREG(op)) = (R##REG(tms,DSTREG(op)) & 0xffff0000) \| (UINT16)R##REG(tms,SRCREG(op)); \
188		COUNT_CYCLES(tms,1); \
	187	R##REG(DSTREG(op)) = (R##REG(DSTREG(op)) & 0xffff0000) \| (UINT16)R##REG(SRCREG(op)); \
	188	COUNT_CYCLES(1); \
189	189	}
190		static void movx_a(tms34010_state *tms, UINT16 op) { MOVX(A); }
191		static void movx_b(tms34010_state *tms, UINT16 op) { MOVX(B); }
	190	void tms340x0_device::movx_a(UINT16 op) { MOVX(A); }
	191	void tms340x0_device::movx_b(UINT16 op) { MOVX(B); }
192	192
193	193	#define MOVY(R) \
194	194	{ \
195		R##REG(tms,DSTREG(op)) = (R##REG(tms,SRCREG(op)) & 0xffff0000) \| (UINT16)R##REG(tms,DSTREG(op)); \
196		COUNT_CYCLES(tms,1); \
	195	R##REG(DSTREG(op)) = (R##REG(SRCREG(op)) & 0xffff0000) \| (UINT16)R##REG(DSTREG(op)); \
	196	COUNT_CYCLES(1); \
197	197	}
198		static void movy_a(tms34010_state *tms, UINT16 op) { MOVY(A); }
199		static void movy_b(tms34010_state *tms, UINT16 op) { MOVY(B); }
	198	void tms340x0_device::movy_a(UINT16 op) { MOVY(A); }
	199	void tms340x0_device::movy_b(UINT16 op) { MOVY(B); }
200	200
201	201
202	202
r31176	r31177
206	206
207	207	#define PIXT_RI(R) \
208	208	{ \
209		WPIXEL(tms,R##REG(tms,DSTREG(op)),R##REG(tms,SRCREG(op))); \
210		COUNT_UNKNOWN_CYCLES(tms,2); \
	209	WPIXEL(R##REG(DSTREG(op)),R##REG(SRCREG(op))); \
	210	COUNT_UNKNOWN_CYCLES(2); \
211	211	}
212		static void pixt_ri_a(tms34010_state *tms, UINT16 op) { PIXT_RI(A); }
213		static void pixt_ri_b(tms34010_state *tms, UINT16 op) { PIXT_RI(B); }
	212	void tms340x0_device::pixt_ri_a(UINT16 op) { PIXT_RI(A); }
	213	void tms340x0_device::pixt_ri_b(UINT16 op) { PIXT_RI(B); }
214	214
215	215	#define PIXT_RIXY(R) \
216	216	{ \
217		if (WINDOW_CHECKING(~~tms~~) != 0) \
	217	if (WINDOW_CHECKING() != 0) \
218	218	{ \
219		CLR_V(tms); \
220		if (R##REG_X(tms,DSTREG(op)) < WSTART_X(tms) \|\| R##REG_X(tms,DSTREG(op)) > WEND_X(tms) \|\| \
221		R##REG_Y(tms,DSTREG(op)) < WSTART_Y(tms) \|\| R##REG_Y(tms,DSTREG(op)) > WEND_Y(tms)) \
	219	CLR_V(); \
	220	if (R##REG_X(DSTREG(op)) < WSTART_X() \|\| R##REG_X(DSTREG(op)) > WEND_X() \|\| \
	221	R##REG_Y(DSTREG(op)) < WSTART_Y() \|\| R##REG_Y(DSTREG(op)) > WEND_Y()) \
222	222	{ \
223		SET_V_LOG(~~tms,~~ 1); \
	223	SET_V_LOG(1); \
224	224	goto skip; \
225	225	} \
226		if (WINDOW_CHECKING(~~tms~~) == 1) goto skip; \
	226	if (WINDOW_CHECKING() == 1) goto skip; \
227	227	} \
228		WPIXEL(~~tms,~~DXYTOL(~~tms,~~R##REG_XY(~~tms,~~DSTREG(op))),R##REG(~~tms,~~SRCREG(op))); \
	228	WPIXEL(DXYTOL(R##REG_XY(DSTREG(op))),R##REG(SRCREG(op))); \
229	229	skip: \
230		COUNT_UNKNOWN_CYCLES(~~tms,~~4); \
	230	COUNT_UNKNOWN_CYCLES(4); \
231	231	}
232		static void pixt_rixy_a(tms34010_state *tms, UINT16 op) { PIXT_RIXY(A); }
233		static void pixt_rixy_b(tms34010_state *tms, UINT16 op) { PIXT_RIXY(B); }
	232	void tms340x0_device::pixt_rixy_a(UINT16 op) { PIXT_RIXY(A); }
	233	void tms340x0_device::pixt_rixy_b(UINT16 op) { PIXT_RIXY(B); }
234	234
235	235	#define PIXT_IR(R) \
236	236	{ \
237		INT32 temp = RPIXEL(tms,R##REG(tms,SRCREG(op))); \
238		CLR_V(tms); \
239		R##REG(tms,DSTREG(op)) = temp; \
240		SET_V_LOG(tms, temp != 0); \
241		COUNT_CYCLES(tms,4); \
	237	INT32 temp = RPIXEL(R##REG(SRCREG(op))); \
	238	CLR_V(); \
	239	R##REG(DSTREG(op)) = temp; \
	240	SET_V_LOG(temp != 0); \
	241	COUNT_CYCLES(4); \
242	242	}
243		static void pixt_ir_a(tms34010_state *tms, UINT16 op) { PIXT_IR(A); }
244		static void pixt_ir_b(tms34010_state *tms, UINT16 op) { PIXT_IR(B); }
	243	void tms340x0_device::pixt_ir_a(UINT16 op) { PIXT_IR(A); }
	244	void tms340x0_device::pixt_ir_b(UINT16 op) { PIXT_IR(B); }
245	245
246	246	#define PIXT_II(R) \
247	247	{ \
248		WPIXEL(tms,R##REG(tms,DSTREG(op)),RPIXEL(tms,R##REG(tms,SRCREG(op)))); \
249		COUNT_UNKNOWN_CYCLES(tms,4); \
	248	WPIXEL(R##REG(DSTREG(op)),RPIXEL(R##REG(SRCREG(op)))); \
	249	COUNT_UNKNOWN_CYCLES(4); \
250	250	}
251		static void pixt_ii_a(tms34010_state *tms, UINT16 op) { PIXT_II(A); }
252		static void pixt_ii_b(tms34010_state *tms, UINT16 op) { PIXT_II(B); }
	251	void tms340x0_device::pixt_ii_a(UINT16 op) { PIXT_II(A); }
	252	void tms340x0_device::pixt_ii_b(UINT16 op) { PIXT_II(B); }
253	253
254	254	#define PIXT_IXYR(R) \
255	255	{ \
256		INT32 temp = RPIXEL(tms,SXYTOL(tms,R##REG_XY(tms,SRCREG(op)))); \
257		CLR_V(tms); \
258		R##REG(tms,DSTREG(op)) = temp; \
259		SET_V_LOG(tms, temp != 0); \
260		COUNT_CYCLES(tms,6); \
	256	INT32 temp = RPIXEL(SXYTOL(R##REG_XY(SRCREG(op)))); \
	257	CLR_V(); \
	258	R##REG(DSTREG(op)) = temp; \
	259	SET_V_LOG(temp != 0); \
	260	COUNT_CYCLES(6); \
261	261	}
262		static void pixt_ixyr_a(tms34010_state *tms, UINT16 op) { PIXT_IXYR(A); }
263		static void pixt_ixyr_b(tms34010_state *tms, UINT16 op) { PIXT_IXYR(B); }
	262	void tms340x0_device::pixt_ixyr_a(UINT16 op) { PIXT_IXYR(A); }
	263	void tms340x0_device::pixt_ixyr_b(UINT16 op) { PIXT_IXYR(B); }
264	264
265	265	#define PIXT_IXYIXY(R) \
266	266	{ \
267		if (WINDOW_CHECKING(~~tms~~) != 0) \
	267	if (WINDOW_CHECKING() != 0) \
268	268	{ \
269		CLR_V(tms); \
270		if (R##REG_X(tms,DSTREG(op)) < WSTART_X(tms) \|\| R##REG_X(tms,DSTREG(op)) > WEND_X(tms) \|\| \
271		R##REG_Y(tms,DSTREG(op)) < WSTART_Y(tms) \|\| R##REG_Y(tms,DSTREG(op)) > WEND_Y(tms)) \
	269	CLR_V(); \
	270	if (R##REG_X(DSTREG(op)) < WSTART_X() \|\| R##REG_X(DSTREG(op)) > WEND_X() \|\| \
	271	R##REG_Y(DSTREG(op)) < WSTART_Y() \|\| R##REG_Y(DSTREG(op)) > WEND_Y()) \
272	272	{ \
273		SET_V_LOG(~~tms,~~ 1); \
	273	SET_V_LOG(1); \
274	274	goto skip; \
275	275	} \
276		if (WINDOW_CHECKING(~~tms~~) == 1) goto skip; \
	276	if (WINDOW_CHECKING() == 1) goto skip; \
277	277	} \
278		WPIXEL(~~tms,~~DXYTOL(~~tms,~~R##REG_XY(~~tms,~~DSTREG(op))),RPIXEL(~~tms,~~SXYTOL(~~tms,~~R##REG_XY(~~tms,~~SRCREG(op))))); \
	278	WPIXEL(DXYTOL(R##REG_XY(DSTREG(op))),RPIXEL(SXYTOL(R##REG_XY(SRCREG(op))))); \
279	279	skip: \
280		COUNT_UNKNOWN_CYCLES(~~tms,~~7); \
	280	COUNT_UNKNOWN_CYCLES(7); \
281	281	}
282		static void pixt_ixyixy_a(tms34010_state *tms, UINT16 op) { PIXT_IXYIXY(A); }
283		static void pixt_ixyixy_b(tms34010_state *tms, UINT16 op) { PIXT_IXYIXY(B); }
	282	void tms340x0_device::pixt_ixyixy_a(UINT16 op) { PIXT_IXYIXY(A); }
	283	void tms340x0_device::pixt_ixyixy_b(UINT16 op) { PIXT_IXYIXY(B); }
284	284
285	285	#define DRAV(R) \
286	286	{ \
287		if (WINDOW_CHECKING(~~tms~~) != 0) \
	287	if (WINDOW_CHECKING() != 0) \
288	288	{ \
289		CLR_V(tms); \
290		if (R##REG_X(tms,DSTREG(op)) < WSTART_X(tms) \|\| R##REG_X(tms,DSTREG(op)) > WEND_X(tms) \|\| \
291		R##REG_Y(tms,DSTREG(op)) < WSTART_Y(tms) \|\| R##REG_Y(tms,DSTREG(op)) > WEND_Y(tms)) \
	289	CLR_V(); \
	290	if (R##REG_X(DSTREG(op)) < WSTART_X() \|\| R##REG_X(DSTREG(op)) > WEND_X() \|\| \
	291	R##REG_Y(DSTREG(op)) < WSTART_Y() \|\| R##REG_Y(DSTREG(op)) > WEND_Y()) \
292	292	{ \
293		SET_V_LOG(~~tms,~~ 1); \
	293	SET_V_LOG(1); \
294	294	goto skip; \
295	295	} \
296		if (WINDOW_CHECKING(~~tms~~) == 1) goto skip; \
	296	if (WINDOW_CHECKING() == 1) goto skip; \
297	297	} \
298		WPIXEL(~~tms,~~DXYTOL(~~tms,~~R##REG_XY(~~tms,~~DSTREG(op))),COLOR1(~~tms~~)); \
	298	WPIXEL(DXYTOL(R##REG_XY(DSTREG(op))),COLOR1()); \
299	299	skip: \
300		R##REG_X(tms,DSTREG(op)) += R##REG_X(tms,SRCREG(op)); \
301		R##REG_Y(tms,DSTREG(op)) += R##REG_Y(tms,SRCREG(op)); \
302		COUNT_UNKNOWN_CYCLES(tms,4); \
	300	R##REG_X(DSTREG(op)) += R##REG_X(SRCREG(op)); \
	301	R##REG_Y(DSTREG(op)) += R##REG_Y(SRCREG(op)); \
	302	COUNT_UNKNOWN_CYCLES(4); \
303	303	}
304		static void drav_a(tms34010_state *tms, UINT16 op) { DRAV(A); }
305		static void drav_b(tms34010_state *tms, UINT16 op) { DRAV(B); }
	304	void tms340x0_device::drav_a(UINT16 op) { DRAV(A); }
	305	void tms340x0_device::drav_b(UINT16 op) { DRAV(B); }
306	306
307	307
308	308
r31176	r31177
312	312
313	313	#define ABS(R) \
314	314	{ \
315		INT32 *rd = &R##REG(~~tms,~~DSTREG(op)); \
	315	INT32 *rd = &R##REG(DSTREG(op)); \
316	316	INT32 r = 0 - *rd; \
317		CLR_NZV(~~tms~~); \
	317	CLR_NZV(); \
318	318	if (r > 0) *rd = r; \
319		SET_NZ_VAL(tms, r); \
320		SET_V_LOG(tms, r == (INT32)0x80000000); \
321		COUNT_CYCLES(tms,1); \
	319	SET_NZ_VAL(r); \
	320	SET_V_LOG(r == (INT32)0x80000000); \
	321	COUNT_CYCLES(1); \
322	322	}
323		static void abs_a(tms34010_state *tms, UINT16 op) { ABS(A); }
324		static void abs_b(tms34010_state *tms, UINT16 op) { ABS(B); }
	323	void tms340x0_device::abs_a(UINT16 op) { ABS(A); }
	324	void tms340x0_device::abs_b(UINT16 op) { ABS(B); }
325	325
326	326	#define ADD(R) \
327	327	{ \
328		INT32 a = R##REG(tms,SRCREG(op)); \
329		INT32 *rd = &R##REG(tms,DSTREG(op)); \
	328	INT32 a = R##REG(SRCREG(op)); \
	329	INT32 *rd = &R##REG(DSTREG(op)); \
330	330	INT32 b = *rd; \
331	331	INT32 r = a + b; \
332		CLR_NCZV(~~tms~~); \
	332	CLR_NCZV(); \
333	333	*rd = r; \
334		SET_NZCV_ADD(tms,a,b,r); \
335		COUNT_CYCLES(tms,1); \
	334	SET_NZCV_ADD(a,b,r); \
	335	COUNT_CYCLES(1); \
336	336	}
337		static void add_a(tms34010_state *tms, UINT16 op) { ADD(A); }
338		static void add_b(tms34010_state *tms, UINT16 op) { ADD(B); }
	337	void tms340x0_device::add_a(UINT16 op) { ADD(A); }
	338	void tms340x0_device::add_b(UINT16 op) { ADD(B); }
339	339
340	340	#define ADDC(R) \
341	341	{ \
342	342	/* I'm not sure to which side the carry is added to, should */ \
343	343	/* verify it against the examples */ \
344		INT32 a = R##REG(tms,SRCREG(op)); \
345		INT32 *rd = &R##REG(tms,DSTREG(op)); \
	344	INT32 a = R##REG(SRCREG(op)); \
	345	INT32 *rd = &R##REG(DSTREG(op)); \
346	346	INT32 b = *rd; \
347		INT32 r = a + b + (C_FLAG(tms) ? 1 : 0); \
348		CLR_NCZV(tms); \
	347	INT32 r = a + b + (C_FLAG() ? 1 : 0); \
	348	CLR_NCZV(); \
349	349	*rd = r; \
350		SET_NZCV_ADD(tms,a,b,r); \
351		COUNT_CYCLES(tms,1); \
	350	SET_NZCV_ADD(a,b,r); \
	351	COUNT_CYCLES(1); \
352	352	}
353		static void addc_a(tms34010_state *tms, UINT16 op) { ADDC(A); }
354		static void addc_b(tms34010_state *tms, UINT16 op) { ADDC(B); }
	353	void tms340x0_device::addc_a(UINT16 op) { ADDC(A); }
	354	void tms340x0_device::addc_b(UINT16 op) { ADDC(B); }
355	355
356	356	#define ADDI_W(R) \
357	357	{ \
358		INT32 a = PARAM_WORD(tms); \
359		INT32 *rd = &R##REG(tms,DSTREG(op)); \
	358	INT32 a = PARAM_WORD(); \
	359	INT32 *rd = &R##REG(DSTREG(op)); \
360	360	INT32 b = *rd; \
361	361	INT32 r = a + b; \
362		CLR_NCZV(~~tms~~); \
	362	CLR_NCZV(); \
363	363	*rd = r; \
364		SET_NZCV_ADD(tms,a,b,r); \
365		COUNT_CYCLES(tms,2); \
	364	SET_NZCV_ADD(a,b,r); \
	365	COUNT_CYCLES(2); \
366	366	}
367		static void addi_w_a(tms34010_state *tms, UINT16 op) { ADDI_W(A); }
368		static void addi_w_b(tms34010_state *tms, UINT16 op) { ADDI_W(B); }
	367	void tms340x0_device::addi_w_a(UINT16 op) { ADDI_W(A); }
	368	void tms340x0_device::addi_w_b(UINT16 op) { ADDI_W(B); }
369	369
370	370	#define ADDI_L(R) \
371	371	{ \
372		INT32 a = PARAM_LONG(tms); \
373		INT32 *rd = &R##REG(tms,DSTREG(op)); \
	372	INT32 a = PARAM_LONG(); \
	373	INT32 *rd = &R##REG(DSTREG(op)); \
374	374	INT32 b = *rd; \
375	375	INT32 r = a + b; \
376		CLR_NCZV(~~tms~~); \
	376	CLR_NCZV(); \
377	377	*rd = r; \
378		SET_NZCV_ADD(tms,a,b,r); \
379		COUNT_CYCLES(tms,3); \
	378	SET_NZCV_ADD(a,b,r); \
	379	COUNT_CYCLES(3); \
380	380	}
381		static void addi_l_a(tms34010_state *tms, UINT16 op) { ADDI_L(A); }
382		static void addi_l_b(tms34010_state *tms, UINT16 op) { ADDI_L(B); }
	381	void tms340x0_device::addi_l_a(UINT16 op) { ADDI_L(A); }
	382	void tms340x0_device::addi_l_b(UINT16 op) { ADDI_L(B); }
383	383
384	384	#define ADDK(R) \
385	385	{ \
386	386	INT32 a = fw_inc[PARAM_K(op)]; \
387		INT32 *rd = &R##REG(~~tms,~~DSTREG(op)); \
	387	INT32 *rd = &R##REG(DSTREG(op)); \
388	388	INT32 b = *rd; \
389	389	INT32 r = a + b; \
390		CLR_NCZV(~~tms~~); \
	390	CLR_NCZV(); \
391	391	*rd = r; \
392		SET_NZCV_ADD(tms,a,b,r); \
393		COUNT_CYCLES(tms,1); \
	392	SET_NZCV_ADD(a,b,r); \
	393	COUNT_CYCLES(1); \
394	394	}
395		static void addk_a(tms34010_state *tms, UINT16 op) { ADDK(A); }
396		static void addk_b(tms34010_state *tms, UINT16 op) { ADDK(B); }
	395	void tms340x0_device::addk_a(UINT16 op) { ADDK(A); }
	396	void tms340x0_device::addk_b(UINT16 op) { ADDK(B); }
397	397
398	398	#define AND(R) \
399	399	{ \
400		INT32 *rd = &R##REG(tms,DSTREG(op)); \
401		CLR_Z(tms); \
402		*rd &= R##REG(tms,SRCREG(op)); \
403		SET_Z_VAL(tms, *rd); \
404		COUNT_CYCLES(tms,1); \
	400	INT32 *rd = &R##REG(DSTREG(op)); \
	401	CLR_Z(); \
	402	*rd &= R##REG(SRCREG(op)); \
	403	SET_Z_VAL(*rd); \
	404	COUNT_CYCLES(1); \
405	405	}
406		static void and_a(tms34010_state *tms, UINT16 op) { AND(A); }
407		static void and_b(tms34010_state *tms, UINT16 op) { AND(B); }
	406	void tms340x0_device::and_a(UINT16 op) { AND(A); }
	407	void tms340x0_device::and_b(UINT16 op) { AND(B); }
408	408
409	409	#define ANDI(R) \
410	410	{ \
411		INT32 *rd = &R##REG(tms,DSTREG(op)); \
412		CLR_Z(tms); \
413		*rd &= ~PARAM_LONG(tms); \
414		SET_Z_VAL(tms, *rd); \
415		COUNT_CYCLES(tms,3); \
	411	INT32 *rd = &R##REG(DSTREG(op)); \
	412	CLR_Z(); \
	413	*rd &= ~PARAM_LONG(); \
	414	SET_Z_VAL(*rd); \
	415	COUNT_CYCLES(3); \
416	416	}
417		static void andi_a(tms34010_state *tms, UINT16 op) { ANDI(A); }
418		static void andi_b(tms34010_state *tms, UINT16 op) { ANDI(B); }
	417	void tms340x0_device::andi_a(UINT16 op) { ANDI(A); }
	418	void tms340x0_device::andi_b(UINT16 op) { ANDI(B); }
419	419
420	420	#define ANDN(R) \
421	421	{ \
422		INT32 *rd = &R##REG(tms,DSTREG(op)); \
423		CLR_Z(tms); \
424		*rd &= ~R##REG(tms,SRCREG(op)); \
425		SET_Z_VAL(tms, *rd); \
426		COUNT_CYCLES(tms,1); \
	422	INT32 *rd = &R##REG(DSTREG(op)); \
	423	CLR_Z(); \
	424	*rd &= ~R##REG(SRCREG(op)); \
	425	SET_Z_VAL(*rd); \
	426	COUNT_CYCLES(1); \
427	427	}
428		static void andn_a(tms34010_state *tms, UINT16 op) { ANDN(A); }
429		static void andn_b(tms34010_state *tms, UINT16 op) { ANDN(B); }
	428	void tms340x0_device::andn_a(UINT16 op) { ANDN(A); }
	429	void tms340x0_device::andn_b(UINT16 op) { ANDN(B); }
430	430
431	431	#define BTST_K(R) \
432	432	{ \
433	433	int bit = 31 - PARAM_K(op); \
434		CLR_Z(~~tms~~); \
	434	CLR_Z(); \
435	435	if (bit <= 29) \
436		SET_Z_BIT_LO(~~tms,~~ ~R##REG(~~tms,~~DSTREG(op)), bit); \
	436	SET_Z_BIT_LO(~R##REG(DSTREG(op)), bit); \
437	437	else \
438		SET_Z_BIT_HI(tms, ~R##REG(tms,DSTREG(op)), bit); \
439		COUNT_CYCLES(tms,1); \
	438	SET_Z_BIT_HI(~R##REG(DSTREG(op)), bit); \
	439	COUNT_CYCLES(1); \
440	440	}
441		static void btst_k_a(tms34010_state *tms, UINT16 op) { BTST_K(A); }
442		static void btst_k_b(tms34010_state *tms, UINT16 op) { BTST_K(B); }
	441	void tms340x0_device::btst_k_a(UINT16 op) { BTST_K(A); }
	442	void tms340x0_device::btst_k_b(UINT16 op) { BTST_K(B); }
443	443
444	444	#define BTST_R(R) \
445	445	{ \
446		int bit = R##REG(tms,SRCREG(op)) & 0x1f; \
447		CLR_Z(tms); \
	446	int bit = R##REG(SRCREG(op)) & 0x1f; \
	447	CLR_Z(); \
448	448	if (bit <= 29) \
449		SET_Z_BIT_LO(~~tms,~~ ~R##REG(~~tms,~~DSTREG(op)), bit); \
	449	SET_Z_BIT_LO(~R##REG(DSTREG(op)), bit); \
450	450	else \
451		SET_Z_BIT_HI(tms, ~R##REG(tms,DSTREG(op)), bit); \
452		COUNT_CYCLES(tms,2); \
	451	SET_Z_BIT_HI(~R##REG(DSTREG(op)), bit); \
	452	COUNT_CYCLES(2); \
453	453	}
454		static void btst_r_a(tms34010_state *tms, UINT16 op) { BTST_R(A); }
455		static void btst_r_b(tms34010_state *tms, UINT16 op) { BTST_R(B); }
	454	void tms340x0_device::btst_r_a(UINT16 op) { BTST_R(A); }
	455	void tms340x0_device::btst_r_b(UINT16 op) { BTST_R(B); }
456	456
457		~~static~~ void ~~clrc(~~tms34010_~~stat~~e *tms, UINT16 op)
	457	void tms340x0_device::clrc(UINT16 op)
458	458	{
459		CLR_C(tms);
460		COUNT_CYCLES(tms,1);
	459	CLR_C();
	460	COUNT_CYCLES(1);
461	461	}
462	462
463	463	#define CMP(R) \
464	464	{ \
465		INT32 *rs = &R##REG(tms,SRCREG(op)); \
466		INT32 *rd = &R##REG(tms,DSTREG(op)); \
	465	INT32 *rs = &R##REG(SRCREG(op)); \
	466	INT32 *rd = &R##REG(DSTREG(op)); \
467	467	INT32 r = rd - rs; \
468		CLR_NCZV(tms); \
469		SET_NZCV_SUB(tms,rd,rs,r); \
470		COUNT_CYCLES(tms,1); \
	468	CLR_NCZV(); \
	469	SET_NZCV_SUB(rd,rs,r); \
	470	COUNT_CYCLES(1); \
471	471	}
472		static void cmp_a(tms34010_state *tms, UINT16 op) { CMP(A); }
473		static void cmp_b(tms34010_state *tms, UINT16 op) { CMP(B); }
	472	void tms340x0_device::cmp_a(UINT16 op) { CMP(A); }
	473	void tms340x0_device::cmp_b(UINT16 op) { CMP(B); }
474	474
475	475	#define CMPI_W(R) \
476	476	{ \
477		INT32 *rd = &R##REG(tms,DSTREG(op)); \
478		INT32 t = (INT16)~PARAM_WORD(tms); \
	477	INT32 *rd = &R##REG(DSTREG(op)); \
	478	INT32 t = (INT16)~PARAM_WORD(); \
479	479	INT32 r = *rd - t; \
480		CLR_NCZV(tms); \
481		SET_NZCV_SUB(tms,*rd,t,r); \
482		COUNT_CYCLES(tms,2); \
	480	CLR_NCZV(); \
	481	SET_NZCV_SUB(*rd,t,r); \
	482	COUNT_CYCLES(2); \
483	483	}
484		static void cmpi_w_a(tms34010_state *tms, UINT16 op) { CMPI_W(A); }
485		static void cmpi_w_b(tms34010_state *tms, UINT16 op) { CMPI_W(B); }
	484	void tms340x0_device::cmpi_w_a(UINT16 op) { CMPI_W(A); }
	485	void tms340x0_device::cmpi_w_b(UINT16 op) { CMPI_W(B); }
486	486
487	487	#define CMPI_L(R) \
488	488	{ \
489		INT32 *rd = &R##REG(tms,DSTREG(op)); \
490		INT32 t = ~PARAM_LONG(tms); \
	489	INT32 *rd = &R##REG(DSTREG(op)); \
	490	INT32 t = ~PARAM_LONG(); \
491	491	INT32 r = *rd - t; \
492		CLR_NCZV(tms); \
493		SET_NZCV_SUB(tms,*rd,t,r); \
494		COUNT_CYCLES(tms,3); \
	492	CLR_NCZV(); \
	493	SET_NZCV_SUB(*rd,t,r); \
	494	COUNT_CYCLES(3); \
495	495	}
496		static void cmpi_l_a(tms34010_state *tms, UINT16 op) { CMPI_L(A); }
497		static void cmpi_l_b(tms34010_state *tms, UINT16 op) { CMPI_L(B); }
	496	void tms340x0_device::cmpi_l_a(UINT16 op) { CMPI_L(A); }
	497	void tms340x0_device::cmpi_l_b(UINT16 op) { CMPI_L(B); }
498	498
499		~~static~~ void ~~din~~t(tms34010_~~stat~~e *t~~ms,~~ UINT16 op)
	499	void tms340x0_device::dint(UINT16 op)
500	500	{
501		tms->st &= ~STBIT_IE;
502		COUNT_CYCLES(tms,3);
	501	m_st &= ~STBIT_IE;
	502	COUNT_CYCLES(3);
503	503	}
504	504
505	505	#define DIVS(R) \
506	506	{ \
507		INT32 *rs = &R##REG(tms,SRCREG(op)); \
508		INT32 *rd1 = &R##REG(tms,DSTREG(op)); \
509		CLR_NZV(tms); \
	507	INT32 *rs = &R##REG(SRCREG(op)); \
	508	INT32 *rd1 = &R##REG(DSTREG(op)); \
	509	CLR_NZV(); \
510	510	if (!(DSTREG(op) & 1)) \
511	511	{ \
512	512	if (!*rs) \
513	513	{ \
514		SET_V_LOG(~~tms,~~ 1); \
	514	SET_V_LOG(1); \
515	515	} \
516	516	else \
517	517	{ \
518		INT32 *rd2 = &R##REG(~~tms,~~DSTREG(op)+1); \
	518	INT32 *rd2 = &R##REG(DSTREG(op)+1); \
519	519	INT64 dividend = ((UINT64)rd1 << 32) \| (UINT32)rd2; \
520	520	INT64 quotient = dividend / *rs; \
521	521	INT32 remainder = dividend % *rs; \
522	522	UINT32 signbits = (INT32)quotient >> 31; \
523	523	if (EXTRACT_64HI(quotient) != signbits) \
524	524	{ \
525		SET_V_LOG(~~tms,~~ 1); \
	525	SET_V_LOG(1); \
526	526	} \
527	527	else \
528	528	{ \
529	529	*rd1 = quotient; \
530	530	*rd2 = remainder; \
531		SET_NZ_VAL(~~tms,~~ *rd1); \
	531	SET_NZ_VAL(*rd1); \
532	532	} \
533	533	} \
534		COUNT_CYCLES(~~tms,~~40); \
	534	COUNT_CYCLES(40); \
535	535	} \
536	536	else \
537	537	{ \
538	538	if (!*rs) \
539	539	{ \
540		SET_V_LOG(~~tms,~~ 1); \
	540	SET_V_LOG(1); \
541	541	} \
542	542	else \
543	543	{ \
544	544	rd1 /= rs; \
545		SET_NZ_VAL(~~tms,~~ *rd1); \
	545	SET_NZ_VAL(*rd1); \
546	546	} \
547		COUNT_CYCLES(~~tms,~~39); \
	547	COUNT_CYCLES(39); \
548	548	} \
549	549	}
550		static void divs_a(tms34010_state *tms, UINT16 op) { DIVS(A); }
551		static void divs_b(tms34010_state *tms, UINT16 op) { DIVS(B); }
	550	void tms340x0_device::divs_a(UINT16 op) { DIVS(A); }
	551	void tms340x0_device::divs_b(UINT16 op) { DIVS(B); }
552	552
553	553	#define DIVU(R) \
554	554	{ \
555		INT32 *rs = &R##REG(tms,SRCREG(op)); \
556		INT32 *rd1 = &R##REG(tms,DSTREG(op)); \
557		CLR_ZV(tms); \
	555	INT32 *rs = &R##REG(SRCREG(op)); \
	556	INT32 *rd1 = &R##REG(DSTREG(op)); \
	557	CLR_ZV(); \
558	558	if (!(DSTREG(op) & 1)) \
559	559	{ \
560	560	if (!*rs) \
561	561	{ \
562		SET_V_LOG(~~tms,~~ 1); \
	562	SET_V_LOG(1); \
563	563	} \
564	564	else \
565	565	{ \
566		INT32 *rd2 = &R##REG(~~tms,~~DSTREG(op)+1); \
	566	INT32 *rd2 = &R##REG(DSTREG(op)+1); \
567	567	UINT64 dividend = ((UINT64)rd1 << 32) \| (UINT32)rd2; \
568	568	UINT64 quotient = dividend / (UINT32)*rs; \
569	569	UINT32 remainder = dividend % (UINT32)*rs; \
570	570	if (EXTRACT_64HI(quotient) != 0) \
571	571	{ \
572		SET_V_LOG(~~tms,~~ 1); \
	572	SET_V_LOG(1); \
573	573	} \
574	574	else \
575	575	{ \
576	576	*rd1 = quotient; \
577	577	*rd2 = remainder; \
578		SET_Z_VAL(~~tms,~~ *rd1); \
	578	SET_Z_VAL(*rd1); \
579	579	} \
580	580	} \
581	581	} \
r31176	r31177
583	583	{ \
584	584	if (!*rs) \
585	585	{ \
586		SET_V_LOG(~~tms,~~ 1); \
	586	SET_V_LOG(1); \
587	587	} \
588	588	else \
589	589	{ \
590	590	rd1 = (UINT32)rd1 / (UINT32)*rs; \
591		SET_Z_VAL(~~tms,~~ *rd1); \
	591	SET_Z_VAL(*rd1); \
592	592	} \
593	593	} \
594		COUNT_CYCLES(~~tms,~~37); \
	594	COUNT_CYCLES(37); \
595	595	}
596		static void divu_a(tms34010_state *tms, UINT16 op) { DIVU(A); }
597		static void divu_b(tms34010_state *tms, UINT16 op) { DIVU(B); }
	596	void tms340x0_device::divu_a(UINT16 op) { DIVU(A); }
	597	void tms340x0_device::divu_b(UINT16 op) { DIVU(B); }
598	598
599		~~static~~ void ~~ein~~t(tms34010_~~stat~~e *t~~ms,~~ UINT16 op)
	599	void tms340x0_device::eint(UINT16 op)
600	600	{
601		tms->st \|= STBIT_IE;
602		check_interrupt(tms);
603		COUNT_CYCLES(tms,3);
	601	m_st \|= STBIT_IE;
	602	check_interrupt();
	603	COUNT_CYCLES(3);
604	604	}
605	605
606	606	#define EXGF(F,R) \
607	607	{ \
608	608	UINT8 shift = F ? 6 : 0; \
609		INT32 *rd = &R##REG(tms,DSTREG(op)); \
610		UINT32 temp = (tms->st >> shift) & 0x3f; \
611		tms->st &= ~(0x3f << shift); \
612		tms->st \|= (*rd & 0x3f) << shift; \
	609	INT32 *rd = &R##REG(DSTREG(op)); \
	610	UINT32 temp = (m_st >> shift) & 0x3f; \
	611	m_st &= ~(0x3f << shift); \
	612	m_st \|= (*rd & 0x3f) << shift; \
613	613	*rd = temp; \
614		COUNT_CYCLES(~~tms,~~1); \
	614	COUNT_CYCLES(1); \
615	615	}
616		static void exgf0_a(tms34010_state *tms, UINT16 op) { EXGF(0,A); }
617		static void exgf0_b(tms34010_state *tms, UINT16 op) { EXGF(0,B); }
618		static void exgf1_a(tms34010_state *tms, UINT16 op) { EXGF(1,A); }
619		static void exgf1_b(tms34010_state *tms, UINT16 op) { EXGF(1,B); }
	616	void tms340x0_device::exgf0_a(UINT16 op) { EXGF(0,A); }
	617	void tms340x0_device::exgf0_b(UINT16 op) { EXGF(0,B); }
	618	void tms340x0_device::exgf1_a(UINT16 op) { EXGF(1,A); }
	619	void tms340x0_device::exgf1_b(UINT16 op) { EXGF(1,B); }
620	620
621	621	#define LMO(R) \
622	622	{ \
623	623	UINT32 res = 0; \
624		UINT32 rs = R##REG(tms,SRCREG(op)); \
625		INT32 *rd = &R##REG(tms,DSTREG(op)); \
626		CLR_Z(tms); \
627		SET_Z_VAL(tms, rs); \
	624	UINT32 rs = R##REG(SRCREG(op)); \
	625	INT32 *rd = &R##REG(DSTREG(op)); \
	626	CLR_Z(); \
	627	SET_Z_VAL(rs); \
628	628	if (rs) \
629	629	{ \
630	630	while (!(rs & 0x80000000)) \
r31176	r31177
634	634	} \
635	635	} \
636	636	*rd = res; \
637		COUNT_CYCLES(~~tms,~~1); \
	637	COUNT_CYCLES(1); \
638	638	}
639		static void lmo_a(tms34010_state *tms, UINT16 op) { LMO(A); }
640		static void lmo_b(tms34010_state *tms, UINT16 op) { LMO(B); }
	639	void tms340x0_device::lmo_a(UINT16 op) { LMO(A); }
	640	void tms340x0_device::lmo_b(UINT16 op) { LMO(B); }
641	641
642	642	#define MMFM(R) \
643	643	{ \
644	644	INT32 i; \
645		UINT16 l = (UINT16) PARAM_WORD(tms); \
646		COUNT_CYCLES(tms,3); \
	645	UINT16 l = (UINT16) PARAM_WORD(); \
	646	COUNT_CYCLES(3); \
647	647	{ \
648	648	INT32 rd = DSTREG(op); \
649	649	for (i = 15; i >= 0 ; i--) \
650	650	{ \
651	651	if (l & 0x8000) \
652	652	{ \
653		R##REG(tms,i) = RLONG(tms, R##REG(tms,rd)); \
654		R##REG(tms,rd) += 0x20; \
655		COUNT_CYCLES(tms,4); \
	653	R##REG(i) = RLONG(R##REG(rd)); \
	654	R##REG(rd) += 0x20; \
	655	COUNT_CYCLES(4); \
656	656	} \
657	657	l <<= 1; \
658	658	} \
659	659	} \
660	660	}
661		static void mmfm_a(tms34010_state *tms, UINT16 op) { MMFM(A); }
662		static void mmfm_b(tms34010_state *tms, UINT16 op) { MMFM(B); }
	661	void tms340x0_device::mmfm_a(UINT16 op) { MMFM(A); }
	662	void tms340x0_device::mmfm_b(UINT16 op) { MMFM(B); }
663	663
664	664	#define MMTM(R) \
665	665	{ \
666	666	UINT32 i; \
667		UINT16 l = (UINT16) PARAM_WORD(tms); \
668		COUNT_CYCLES(tms,2); \
	667	UINT16 l = (UINT16) PARAM_WORD(); \
	668	COUNT_CYCLES(2); \
669	669	{ \
670	670	INT32 rd = DSTREG(op); \
671		if (tm~~s->~~is_34020) \
	671	if (m_is_34020) \
672	672	{ \
673		CLR_N(tms); \
674		SET_N_VAL(tms, R##REG(tms,rd) ^ 0x80000000); \
	673	CLR_N(); \
	674	SET_N_VAL(R##REG(rd) ^ 0x80000000); \
675	675	} \
676	676	for (i = 0; i < 16; i++) \
677	677	{ \
678	678	if (l & 0x8000) \
679	679	{ \
680		R##REG(tms,rd) -= 0x20; \
681		WLONG(tms, R##REG(tms,rd),R##REG(tms,i)); \
682		COUNT_CYCLES(tms,4); \
	680	R##REG(rd) -= 0x20; \
	681	WLONG(R##REG(rd),R##REG(i)); \
	682	COUNT_CYCLES(4); \
683	683	} \
684	684	l <<= 1; \
685	685	} \
686	686	} \
687	687	}
688		static void mmtm_a(tms34010_state *tms, UINT16 op) { MMTM(A); }
689		static void mmtm_b(tms34010_state *tms, UINT16 op) { MMTM(B); }
	688	void tms340x0_device::mmtm_a(UINT16 op) { MMTM(A); }
	689	void tms340x0_device::mmtm_b(UINT16 op) { MMTM(B); }
690	690
691	691	#define MODS(R) \
692	692	{ \
693		INT32 *rs = &R##REG(tms,SRCREG(op)); \
694		INT32 *rd = &R##REG(tms,DSTREG(op)); \
695		CLR_NZV(tms); \
	693	INT32 *rs = &R##REG(SRCREG(op)); \
	694	INT32 *rd = &R##REG(DSTREG(op)); \
	695	CLR_NZV(); \
696	696	if (*rs != 0) \
697	697	{ \
698	698	rd %= rs; \
699		SET_NZ_VAL(~~tms,~~ *rd); \
	699	SET_NZ_VAL(*rd); \
700	700	} \
701	701	else \
702		SET_V_LOG(tms, 1); \
703		COUNT_CYCLES(tms,40); \
	702	SET_V_LOG(1); \
	703	COUNT_CYCLES(40); \
704	704	}
705		static void mods_a(tms34010_state *tms, UINT16 op) { MODS(A); }
706		static void mods_b(tms34010_state *tms, UINT16 op) { MODS(B); }
	705	void tms340x0_device::mods_a(UINT16 op) { MODS(A); }
	706	void tms340x0_device::mods_b(UINT16 op) { MODS(B); }
707	707
708	708	#define MODU(R) \
709	709	{ \
710		INT32 *rs = &R##REG(tms,SRCREG(op)); \
711		INT32 *rd = &R##REG(tms,DSTREG(op)); \
712		CLR_ZV(tms); \
	710	INT32 *rs = &R##REG(SRCREG(op)); \
	711	INT32 *rd = &R##REG(DSTREG(op)); \
	712	CLR_ZV(); \
713	713	if (*rs != 0) \
714	714	{ \
715	715	rd = (UINT32)rd % (UINT32)*rs; \
716		SET_Z_VAL(~~tms,~~ *rd); \
	716	SET_Z_VAL(*rd); \
717	717	} \
718	718	else \
719		SET_V_LOG(tms, 1); \
720		COUNT_CYCLES(tms,35); \
	719	SET_V_LOG(1); \
	720	COUNT_CYCLES(35); \
721	721	}
722		static void modu_a(tms34010_state *tms, UINT16 op) { MODU(A); }
723		static void modu_b(tms34010_state *tms, UINT16 op) { MODU(B); }
	722	void tms340x0_device::modu_a(UINT16 op) { MODU(A); }
	723	void tms340x0_device::modu_b(UINT16 op) { MODU(B); }
724	724
725	725	#define MPYS(R) \
726	726	{ \
727		INT32 *rd1 = &R##REG(tms,DSTREG(op)); \
728		INT32 m1 = R##REG(tms,SRCREG(op)); \
	727	INT32 *rd1 = &R##REG(DSTREG(op)); \
	728	INT32 m1 = R##REG(SRCREG(op)); \
729	729	INT64 product; \
730	730	\
731		SEXTEND(m1, FW(tms,1)); \
732		CLR_NZ(tms); \
	731	SEXTEND(m1, FW(1)); \
	732	CLR_NZ(); \
733	733	product = mul_32x32(m1, *rd1); \
734		SET_Z_LOG(tms, product == 0); \
735		SET_N_BIT(tms, product >> 32, 31); \
	734	SET_Z_LOG(product == 0); \
	735	SET_N_BIT(product >> 32, 31); \
736	736	\
737	737	*rd1 = EXTRACT_64HI(product); \
738		R##REG(~~tms,~~DSTREG(op)\|1) = EXTRACT_64LO(product); \
	738	R##REG(DSTREG(op)\|1) = EXTRACT_64LO(product); \
739	739	\
740		COUNT_CYCLES(~~tms,~~20); \
	740	COUNT_CYCLES(20); \
741	741	}
742		static void mpys_a(tms34010_state *tms, UINT16 op) { MPYS(A); }
743		static void mpys_b(tms34010_state *tms, UINT16 op) { MPYS(B); }
	742	void tms340x0_device::mpys_a(UINT16 op) { MPYS(A); }
	743	void tms340x0_device::mpys_b(UINT16 op) { MPYS(B); }
744	744
745	745	#define MPYU(R) \
746	746	{ \
747		INT32 *rd1 = &R##REG(tms,DSTREG(op)); \
748		UINT32 m1 = R##REG(tms,SRCREG(op)); \
	747	INT32 *rd1 = &R##REG(DSTREG(op)); \
	748	UINT32 m1 = R##REG(SRCREG(op)); \
749	749	UINT64 product; \
750	750	\
751		ZEXTEND(m1, FW(tms,1)); \
752		CLR_Z(tms); \
	751	ZEXTEND(m1, FW(1)); \
	752	CLR_Z(); \
753	753	product = mulu_32x32(m1, *rd1); \
754		SET_Z_LOG(~~tms,~~ product == 0); \
	754	SET_Z_LOG(product == 0); \
755	755	\
756	756	*rd1 = EXTRACT_64HI(product); \
757		R##REG(~~tms,~~DSTREG(op)\|1) = EXTRACT_64LO(product); \
	757	R##REG(DSTREG(op)\|1) = EXTRACT_64LO(product); \
758	758	\
759		COUNT_CYCLES(~~tms,~~21); \
	759	COUNT_CYCLES(21); \
760	760	}
761		static void mpyu_a(tms34010_state *tms, UINT16 op) { MPYU(A); }
762		static void mpyu_b(tms34010_state *tms, UINT16 op) { MPYU(B); }
	761	void tms340x0_device::mpyu_a(UINT16 op) { MPYU(A); }
	762	void tms340x0_device::mpyu_b(UINT16 op) { MPYU(B); }
763	763
764	764	#define NEG(R) \
765	765	{ \
766		INT32 *rd = &R##REG(~~tms,~~DSTREG(op)); \
	766	INT32 *rd = &R##REG(DSTREG(op)); \
767	767	INT32 r = 0 - *rd; \
768		CLR_NCZV(tms); \
769		SET_NZCV_SUB(tms,0,*rd,r); \
	768	CLR_NCZV(); \
	769	SET_NZCV_SUB(0,*rd,r); \
770	770	*rd = r; \
771		COUNT_CYCLES(~~tms,~~1); \
	771	COUNT_CYCLES(1); \
772	772	}
773		static void neg_a(tms34010_state *tms, UINT16 op) { NEG(A); }
774		static void neg_b(tms34010_state *tms, UINT16 op) { NEG(B); }
	773	void tms340x0_device::neg_a(UINT16 op) { NEG(A); }
	774	void tms340x0_device::neg_b(UINT16 op) { NEG(B); }
775	775
776	776	#define NEGB(R) \
777	777	{ \
778		INT32 *rd = &R##REG(tms,DSTREG(op)); \
779		INT32 t = *rd + (C_FLAG(tms) ? 1 : 0); \
	778	INT32 *rd = &R##REG(DSTREG(op)); \
	779	INT32 t = *rd + (C_FLAG() ? 1 : 0); \
780	780	INT32 r = 0 - t; \
781		CLR_NCZV(tms); \
782		SET_NZCV_SUB(tms,0,t,r); \
	781	CLR_NCZV(); \
	782	SET_NZCV_SUB(0,t,r); \
783	783	*rd = r; \
784		COUNT_CYCLES(~~tms,~~1); \
	784	COUNT_CYCLES(1); \
785	785	}
786		static void negb_a(tms34010_state *tms, UINT16 op) { NEGB(A); }
787		static void negb_b(tms34010_state *tms, UINT16 op) { NEGB(B); }
	786	void tms340x0_device::negb_a(UINT16 op) { NEGB(A); }
	787	void tms340x0_device::negb_b(UINT16 op) { NEGB(B); }
788	788
789		~~static~~ void ~~nop(~~tms34010_~~stat~~e *tms, UINT16 op)
	789	void tms340x0_device::nop(UINT16 op)
790	790	{
791		COUNT_CYCLES(~~tms,~~1);
	791	COUNT_CYCLES(1);
792	792	}
793	793
794	794	#define NOT(R) \
795	795	{ \
796		INT32 *rd = &R##REG(tms,DSTREG(op)); \
797		CLR_Z(tms); \
	796	INT32 *rd = &R##REG(DSTREG(op)); \
	797	CLR_Z(); \
798	798	rd = ~(rd); \
799		SET_Z_VAL(tms, *rd); \
800		COUNT_CYCLES(tms,1); \
	799	SET_Z_VAL(*rd); \
	800	COUNT_CYCLES(1); \
801	801	}
802		static void not_a(tms34010_state *tms, UINT16 op) { NOT(A); }
803		static void not_b(tms34010_state *tms, UINT16 op) { NOT(B); }
	802	void tms340x0_device::not_a(UINT16 op) { NOT(A); }
	803	void tms340x0_device::not_b(UINT16 op) { NOT(B); }
804	804
805	805	#define OR(R) \
806	806	{ \
807		INT32 *rd = &R##REG(tms,DSTREG(op)); \
808		CLR_Z(tms); \
809		*rd \|= R##REG(tms,SRCREG(op)); \
810		SET_Z_VAL(tms, *rd); \
811		COUNT_CYCLES(tms,1); \
	807	INT32 *rd = &R##REG(DSTREG(op)); \
	808	CLR_Z(); \
	809	*rd \|= R##REG(SRCREG(op)); \
	810	SET_Z_VAL(*rd); \
	811	COUNT_CYCLES(1); \
812	812	}
813		static void or_a(tms34010_state *tms, UINT16 op) { OR(A); }
814		static void or_b(tms34010_state *tms, UINT16 op) { OR(B); }
	813	void tms340x0_device::or_a(UINT16 op) { OR(A); }
	814	void tms340x0_device::or_b(UINT16 op) { OR(B); }
815	815
816	816	#define ORI(R) \
817	817	{ \
818		INT32 *rd = &R##REG(tms,DSTREG(op)); \
819		CLR_Z(tms); \
820		*rd \|= PARAM_LONG(tms); \
821		SET_Z_VAL(tms, *rd); \
822		COUNT_CYCLES(tms,3); \
	818	INT32 *rd = &R##REG(DSTREG(op)); \
	819	CLR_Z(); \
	820	*rd \|= PARAM_LONG(); \
	821	SET_Z_VAL(*rd); \
	822	COUNT_CYCLES(3); \
823	823	}
824		static void ori_a(tms34010_state *tms, UINT16 op) { ORI(A); }
825		static void ori_b(tms34010_state *tms, UINT16 op) { ORI(B); }
	824	void tms340x0_device::ori_a(UINT16 op) { ORI(A); }
	825	void tms340x0_device::ori_b(UINT16 op) { ORI(B); }
826	826
827		~~static~~ void set~~c(t~~ms34010_s~~tat~~e *t~~ms,~~ UINT16 op)
	827	void tms340x0_device::setc(UINT16 op)
828	828	{
829		SET_C_LOG(tms, 1);
830		COUNT_CYCLES(tms,1);
	829	SET_C_LOG(1);
	830	COUNT_CYCLES(1);
831	831	}
832	832
833	833	#define SETF(F) \
834	834	{ \
835	835	UINT8 shift = F ? 6 : 0; \
836		tms->st &= ~(0x3f << shift); \
837		tms->st \|= (op & 0x3f) << shift; \
838		COUNT_CYCLES(tms,1+F); \
	836	m_st &= ~(0x3f << shift); \
	837	m_st \|= (op & 0x3f) << shift; \
	838	COUNT_CYCLES(1+F); \
839	839	}
840		static void setf0(tms34010_state *tms, UINT16 op) { SETF(0); }
841		static void setf1(tms34010_state *tms, UINT16 op) { SETF(1); }
	840	void tms340x0_device::setf0(UINT16 op) { SETF(0); }
	841	void tms340x0_device::setf1(UINT16 op) { SETF(1); }
842	842
843	843	#define SEXT(F,R) \
844	844	{ \
845		INT32 *rd = &R##REG(tms,DSTREG(op)); \
846		CLR_NZ(tms); \
847		SEXTEND(*rd,FW(tms,F)); \
848		SET_NZ_VAL(tms, *rd); \
849		COUNT_CYCLES(tms,3); \
	845	INT32 *rd = &R##REG(DSTREG(op)); \
	846	CLR_NZ(); \
	847	SEXTEND(*rd,FW(F)); \
	848	SET_NZ_VAL(*rd); \
	849	COUNT_CYCLES(3); \
850	850	}
851		static void sext0_a(tms34010_state *tms, UINT16 op) { SEXT(0,A); }
852		static void sext0_b(tms34010_state *tms, UINT16 op) { SEXT(0,B); }
853		static void sext1_a(tms34010_state *tms, UINT16 op) { SEXT(1,A); }
854		static void sext1_b(tms34010_state *tms, UINT16 op) { SEXT(1,B); }
	851	void tms340x0_device::sext0_a(UINT16 op) { SEXT(0,A); }
	852	void tms340x0_device::sext0_b(UINT16 op) { SEXT(0,B); }
	853	void tms340x0_device::sext1_a(UINT16 op) { SEXT(1,A); }
	854	void tms340x0_device::sext1_b(UINT16 op) { SEXT(1,B); }
855	855
856	856	#define RL(R,K) \
857	857	{ \
858		INT32 *rd = &R##REG(~~tms,~~DSTREG(op)); \
	858	INT32 *rd = &R##REG(DSTREG(op)); \
859	859	INT32 res = *rd; \
860	860	INT32 k = (K); \
861		CLR_CZ(~~tms~~); \
	861	CLR_CZ(); \
862	862	if (k) \
863	863	{ \
864	864	res<<=(k-1); \
865		SET_C_BIT_HI(~~tms,~~ res, 31); \
	865	SET_C_BIT_HI(res, 31); \
866	866	res<<=1; \
867	867	res \|= (((UINT32)*rd)>>((-k)&0x1f)); \
868	868	*rd = res; \
869	869	} \
870		SET_Z_VAL(tms, res); \
871		COUNT_CYCLES(tms,1); \
	870	SET_Z_VAL(res); \
	871	COUNT_CYCLES(1); \
872	872	}
873		static void rl_k_a(tms34010_state *tms, UINT16 op) { RL(A,PARAM_K(op)); }
874		static void rl_k_b(tms34010_state *tms, UINT16 op) { RL(B,PARAM_K(op)); }
875		static void rl_r_a(tms34010_state *tms, UINT16 op) { RL(A,AREG(tms,SRCREG(op))&0x1f); }
876		static void rl_r_b(tms34010_state *tms, UINT16 op) { RL(B,BREG(tms,SRCREG(op))&0x1f); }
	873	void tms340x0_device::rl_k_a(UINT16 op) { RL(A,PARAM_K(op)); }
	874	void tms340x0_device::rl_k_b(UINT16 op) { RL(B,PARAM_K(op)); }
	875	void tms340x0_device::rl_r_a(UINT16 op) { RL(A,AREG(SRCREG(op))&0x1f); }
	876	void tms340x0_device::rl_r_b(UINT16 op) { RL(B,BREG(SRCREG(op))&0x1f); }
877	877
878	878	#define SLA(R,K) \
879	879	{ \
880		INT32 *rd = &R##REG(~~tms,~~DSTREG(op)); \
	880	INT32 *rd = &R##REG(DSTREG(op)); \
881	881	UINT32 res = *rd; \
882	882	INT32 k = K; \
883		CLR_NCZV(~~tms~~); \
	883	CLR_NCZV(); \
884	884	if (k) \
885	885	{ \
886	886	UINT32 mask = (0xffffffff<<(31-k))&0x7fffffff; \
887	887	UINT32 res2 = SIGN(res) ? res^mask : res; \
888		SET_V_LOG(~~tms,~~ (res2 & mask) != 0); \
	888	SET_V_LOG((res2 & mask) != 0); \
889	889	\
890	890	res<<=(k-1); \
891		SET_C_BIT_HI(~~tms,~~ res, 31); \
	891	SET_C_BIT_HI(res, 31); \
892	892	res<<=1; \
893	893	*rd = res; \
894	894	} \
895		SET_NZ_VAL(tms, res); \
896		COUNT_CYCLES(tms,3); \
	895	SET_NZ_VAL(res); \
	896	COUNT_CYCLES(3); \
897	897	}
898		static void sla_k_a(tms34010_state *tms, UINT16 op) { SLA(A,PARAM_K(op)); }
899		static void sla_k_b(tms34010_state *tms, UINT16 op) { SLA(B,PARAM_K(op)); }
900		static void sla_r_a(tms34010_state *tms, UINT16 op) { SLA(A,AREG(tms,SRCREG(op))&0x1f); }
901		static void sla_r_b(tms34010_state *tms, UINT16 op) { SLA(B,BREG(tms,SRCREG(op))&0x1f); }
	898	void tms340x0_device::sla_k_a(UINT16 op) { SLA(A,PARAM_K(op)); }
	899	void tms340x0_device::sla_k_b(UINT16 op) { SLA(B,PARAM_K(op)); }
	900	void tms340x0_device::sla_r_a(UINT16 op) { SLA(A,AREG(SRCREG(op))&0x1f); }
	901	void tms340x0_device::sla_r_b(UINT16 op) { SLA(B,BREG(SRCREG(op))&0x1f); }
902	902
903	903	#define SLL(R,K) \
904	904	{ \
905		INT32 *rd = &R##REG(~~tms,~~DSTREG(op)); \
	905	INT32 *rd = &R##REG(DSTREG(op)); \
906	906	UINT32 res = *rd; \
907	907	INT32 k = K; \
908		CLR_CZ(~~tms~~); \
	908	CLR_CZ(); \
909	909	if (k) \
910	910	{ \
911	911	res<<=(k-1); \
912		SET_C_BIT_HI(~~tms,~~ res, 31); \
	912	SET_C_BIT_HI(res, 31); \
913	913	res<<=1; \
914	914	*rd = res; \
915	915	} \
916		SET_Z_VAL(tms, res); \
917		COUNT_CYCLES(tms,1); \
	916	SET_Z_VAL(res); \
	917	COUNT_CYCLES(1); \
918	918	}
919		static void sll_k_a(tms34010_state *tms, UINT16 op) { SLL(A,PARAM_K(op)); }
920		static void sll_k_b(tms34010_state *tms, UINT16 op) { SLL(B,PARAM_K(op)); }
921		static void sll_r_a(tms34010_state *tms, UINT16 op) { SLL(A,AREG(tms,SRCREG(op))&0x1f); }
922		static void sll_r_b(tms34010_state *tms, UINT16 op) { SLL(B,BREG(tms,SRCREG(op))&0x1f); }
	919	void tms340x0_device::sll_k_a(UINT16 op) { SLL(A,PARAM_K(op)); }
	920	void tms340x0_device::sll_k_b(UINT16 op) { SLL(B,PARAM_K(op)); }
	921	void tms340x0_device::sll_r_a(UINT16 op) { SLL(A,AREG(SRCREG(op))&0x1f); }
	922	void tms340x0_device::sll_r_b(UINT16 op) { SLL(B,BREG(SRCREG(op))&0x1f); }
923	923
924	924	#define SRA(R,K) \
925	925	{ \
926		INT32 *rd = &R##REG(~~tms,~~DSTREG(op)); \
	926	INT32 *rd = &R##REG(DSTREG(op)); \
927	927	INT32 res = *rd; \
928	928	INT32 k = (-(K)) & 0x1f; \
929		CLR_NCZ(~~tms~~); \
	929	CLR_NCZ(); \
930	930	if (k) \
931	931	{ \
932	932	res>>=(k-1); \
933		SET_C_BIT_LO(~~tms,~~ res, 0); \
	933	SET_C_BIT_LO(res, 0); \
934	934	res>>=1; \
935	935	*rd = res; \
936	936	} \
937		SET_NZ_VAL(tms, res); \
938		COUNT_CYCLES(tms,1); \
	937	SET_NZ_VAL(res); \
	938	COUNT_CYCLES(1); \
939	939	}
940		static void sra_k_a(tms34010_state *tms, UINT16 op) { SRA(A,PARAM_K(op)); }
941		static void sra_k_b(tms34010_state *tms, UINT16 op) { SRA(B,PARAM_K(op)); }
942		static void sra_r_a(tms34010_state *tms, UINT16 op) { SRA(A,AREG(tms,SRCREG(op))); }
943		static void sra_r_b(tms34010_state *tms, UINT16 op) { SRA(B,BREG(tms,SRCREG(op))); }
	940	void tms340x0_device::sra_k_a(UINT16 op) { SRA(A,PARAM_K(op)); }
	941	void tms340x0_device::sra_k_b(UINT16 op) { SRA(B,PARAM_K(op)); }
	942	void tms340x0_device::sra_r_a(UINT16 op) { SRA(A,AREG(SRCREG(op))); }
	943	void tms340x0_device::sra_r_b(UINT16 op) { SRA(B,BREG(SRCREG(op))); }
944	944
945	945	#define SRL(R,K) \
946	946	{ \
947		INT32 *rd = &R##REG(~~tms,~~DSTREG(op)); \
	947	INT32 *rd = &R##REG(DSTREG(op)); \
948	948	UINT32 res = *rd; \
949	949	INT32 k = (-(K)) & 0x1f; \
950		CLR_CZ(~~tms~~); \
	950	CLR_CZ(); \
951	951	if (k) \
952	952	{ \
953	953	res>>=(k-1); \
954		SET_C_BIT_LO(~~tms,~~ res, 0); \
	954	SET_C_BIT_LO(res, 0); \
955	955	res>>=1; \
956	956	*rd = res; \
957	957	} \
958		SET_Z_VAL(tms, res); \
959		COUNT_CYCLES(tms,1); \
	958	SET_Z_VAL(res); \
	959	COUNT_CYCLES(1); \
960	960	}
961		static void srl_k_a(tms34010_state *tms, UINT16 op) { SRL(A,PARAM_K(op)); }
962		static void srl_k_b(tms34010_state *tms, UINT16 op) { SRL(B,PARAM_K(op)); }
963		static void srl_r_a(tms34010_state *tms, UINT16 op) { SRL(A,AREG(tms,SRCREG(op))); }
964		static void srl_r_b(tms34010_state *tms, UINT16 op) { SRL(B,BREG(tms,SRCREG(op))); }
	961	void tms340x0_device::srl_k_a(UINT16 op) { SRL(A,PARAM_K(op)); }
	962	void tms340x0_device::srl_k_b(UINT16 op) { SRL(B,PARAM_K(op)); }
	963	void tms340x0_device::srl_r_a(UINT16 op) { SRL(A,AREG(SRCREG(op))); }
	964	void tms340x0_device::srl_r_b(UINT16 op) { SRL(B,BREG(SRCREG(op))); }
965	965
966	966	#define SUB(R) \
967	967	{ \
968		INT32 *rs = &R##REG(tms,SRCREG(op)); \
969		INT32 *rd = &R##REG(tms,DSTREG(op)); \
	968	INT32 *rs = &R##REG(SRCREG(op)); \
	969	INT32 *rd = &R##REG(DSTREG(op)); \
970	970	INT32 r = rd - rs; \
971		CLR_NCZV(tms); \
972		SET_NZCV_SUB(tms,rd,rs,r); \
	971	CLR_NCZV(); \
	972	SET_NZCV_SUB(rd,rs,r); \
973	973	*rd = r; \
974		COUNT_CYCLES(~~tms,~~1); \
	974	COUNT_CYCLES(1); \
975	975	}
976		static void sub_a(tms34010_state *tms, UINT16 op) { SUB(A); }
977		static void sub_b(tms34010_state *tms, UINT16 op) { SUB(B); }
	976	void tms340x0_device::sub_a(UINT16 op) { SUB(A); }
	977	void tms340x0_device::sub_b(UINT16 op) { SUB(B); }
978	978
979	979	#define SUBB(R) \
980	980	{ \
981		INT32 *rd = &R##REG(tms,DSTREG(op)); \
982		INT32 t = R##REG(tms,SRCREG(op)); \
983		INT32 r = *rd - t - (C_FLAG(tms) ? 1 : 0); \
984		CLR_NCZV(tms); \
985		SET_NZCV_SUB(tms,*rd,t,r); \
	981	INT32 *rd = &R##REG(DSTREG(op)); \
	982	INT32 t = R##REG(SRCREG(op)); \
	983	INT32 r = *rd - t - (C_FLAG() ? 1 : 0); \
	984	CLR_NCZV(); \
	985	SET_NZCV_SUB(*rd,t,r); \
986	986	*rd = r; \
987		COUNT_CYCLES(~~tms,~~1); \
	987	COUNT_CYCLES(1); \
988	988	}
989		static void subb_a(tms34010_state *tms, UINT16 op) { SUBB(A); }
990		static void subb_b(tms34010_state *tms, UINT16 op) { SUBB(B); }
	989	void tms340x0_device::subb_a(UINT16 op) { SUBB(A); }
	990	void tms340x0_device::subb_b(UINT16 op) { SUBB(B); }
991	991
992	992	#define SUBI_W(R) \
993	993	{ \
994		INT32 *rd = &R##REG(~~tms,~~DSTREG(op)); \
	994	INT32 *rd = &R##REG(DSTREG(op)); \
995	995	INT32 r; \
996		INT32 t = ~PARAM_WORD(tms); \
997		CLR_NCZV(tms); \
	996	INT32 t = ~PARAM_WORD(); \
	997	CLR_NCZV(); \
998	998	r = *rd - t; \
999		SET_NZCV_SUB(~~tms,~~*rd,t,r); \
	999	SET_NZCV_SUB(*rd,t,r); \
1000	1000	*rd = r; \
1001		COUNT_CYCLES(~~tms,~~2); \
	1001	COUNT_CYCLES(2); \
1002	1002	}
1003		static void subi_w_a(tms34010_state *tms, UINT16 op) { SUBI_W(A); }
1004		static void subi_w_b(tms34010_state *tms, UINT16 op) { SUBI_W(B); }
	1003	void tms340x0_device::subi_w_a(UINT16 op) { SUBI_W(A); }
	1004	void tms340x0_device::subi_w_b(UINT16 op) { SUBI_W(B); }
1005	1005
1006	1006	#define SUBI_L(R) \
1007	1007	{ \
1008		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1009		INT32 t = ~PARAM_LONG(tms); \
	1008	INT32 *rd = &R##REG(DSTREG(op)); \
	1009	INT32 t = ~PARAM_LONG(); \
1010	1010	INT32 r = *rd - t; \
1011		CLR_NCZV(tms); \
1012		SET_NZCV_SUB(tms,*rd,t,r); \
	1011	CLR_NCZV(); \
	1012	SET_NZCV_SUB(*rd,t,r); \
1013	1013	*rd = r; \
1014		COUNT_CYCLES(~~tms,~~3); \
	1014	COUNT_CYCLES(3); \
1015	1015	}
1016		static void subi_l_a(tms34010_state *tms, UINT16 op) { SUBI_L(A); }
1017		static void subi_l_b(tms34010_state *tms, UINT16 op) { SUBI_L(B); }
	1016	void tms340x0_device::subi_l_a(UINT16 op) { SUBI_L(A); }
	1017	void tms340x0_device::subi_l_b(UINT16 op) { SUBI_L(B); }
1018	1018
1019	1019	#define SUBK(R) \
1020	1020	{ \
1021		INT32 *rd = &R##REG(~~tms,~~DSTREG(op)); \
	1021	INT32 *rd = &R##REG(DSTREG(op)); \
1022	1022	INT32 t = fw_inc[PARAM_K(op)]; \
1023	1023	INT32 r = *rd - t; \
1024		CLR_NCZV(tms); \
1025		SET_NZCV_SUB(tms,*rd,t,r); \
	1024	CLR_NCZV(); \
	1025	SET_NZCV_SUB(*rd,t,r); \
1026	1026	*rd = r; \
1027		COUNT_CYCLES(~~tms,~~1); \
	1027	COUNT_CYCLES(1); \
1028	1028	}
1029		static void subk_a(tms34010_state *tms, UINT16 op) { SUBK(A); }
1030		static void subk_b(tms34010_state *tms, UINT16 op) { SUBK(B); }
	1029	void tms340x0_device::subk_a(UINT16 op) { SUBK(A); }
	1030	void tms340x0_device::subk_b(UINT16 op) { SUBK(B); }
1031	1031
1032	1032	#define XOR(R) \
1033	1033	{ \
1034		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1035		CLR_Z(tms); \
1036		*rd ^= R##REG(tms,SRCREG(op)); \
1037		SET_Z_VAL(tms, *rd); \
1038		COUNT_CYCLES(tms,1); \
	1034	INT32 *rd = &R##REG(DSTREG(op)); \
	1035	CLR_Z(); \
	1036	*rd ^= R##REG(SRCREG(op)); \
	1037	SET_Z_VAL(*rd); \
	1038	COUNT_CYCLES(1); \
1039	1039	}
1040		static void xor_a(tms34010_state *tms, UINT16 op) { XOR(A); }
1041		static void xor_b(tms34010_state *tms, UINT16 op) { XOR(B); }
	1040	void tms340x0_device::xor_a(UINT16 op) { XOR(A); }
	1041	void tms340x0_device::xor_b(UINT16 op) { XOR(B); }
1042	1042
1043	1043	#define XORI(R) \
1044	1044	{ \
1045		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1046		CLR_Z(tms); \
1047		*rd ^= PARAM_LONG(tms); \
1048		SET_Z_VAL(tms, *rd); \
1049		COUNT_CYCLES(tms,3); \
	1045	INT32 *rd = &R##REG(DSTREG(op)); \
	1046	CLR_Z(); \
	1047	*rd ^= PARAM_LONG(); \
	1048	SET_Z_VAL(*rd); \
	1049	COUNT_CYCLES(3); \
1050	1050	}
1051		static void xori_a(tms34010_state *tms, UINT16 op) { XORI(A); }
1052		static void xori_b(tms34010_state *tms, UINT16 op) { XORI(B); }
	1051	void tms340x0_device::xori_a(UINT16 op) { XORI(A); }
	1052	void tms340x0_device::xori_b(UINT16 op) { XORI(B); }
1053	1053
1054	1054	#define ZEXT(F,R) \
1055	1055	{ \
1056		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1057		CLR_Z(tms); \
1058		ZEXTEND(*rd,FW(tms,F)); \
1059		SET_Z_VAL(tms, *rd); \
1060		COUNT_CYCLES(tms,1); \
	1056	INT32 *rd = &R##REG(DSTREG(op)); \
	1057	CLR_Z(); \
	1058	ZEXTEND(*rd,FW(F)); \
	1059	SET_Z_VAL(*rd); \
	1060	COUNT_CYCLES(1); \
1061	1061	}
1062		static void zext0_a(tms34010_state *tms, UINT16 op) { ZEXT(0,A); }
1063		static void zext0_b(tms34010_state *tms, UINT16 op) { ZEXT(0,B); }
1064		static void zext1_a(tms34010_state *tms, UINT16 op) { ZEXT(1,A); }
1065		static void zext1_b(tms34010_state *tms, UINT16 op) { ZEXT(1,B); }
	1062	void tms340x0_device::zext0_a(UINT16 op) { ZEXT(0,A); }
	1063	void tms340x0_device::zext0_b(UINT16 op) { ZEXT(0,B); }
	1064	void tms340x0_device::zext1_a(UINT16 op) { ZEXT(1,A); }
	1065	void tms340x0_device::zext1_b(UINT16 op) { ZEXT(1,B); }
1066	1066
1067	1067
1068	1068
r31176	r31177
1072	1072
1073	1073	#define MOVI_W(R) \
1074	1074	{ \
1075		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1076		CLR_NZV(tms); \
1077		*rd=PARAM_WORD(tms); \
1078		SET_NZ_VAL(tms, *rd); \
1079		COUNT_CYCLES(tms,2); \
	1075	INT32 *rd = &R##REG(DSTREG(op)); \
	1076	CLR_NZV(); \
	1077	*rd=PARAM_WORD(); \
	1078	SET_NZ_VAL(*rd); \
	1079	COUNT_CYCLES(2); \
1080	1080	}
1081		static void movi_w_a(tms34010_state *tms, UINT16 op) { MOVI_W(A); }
1082		static void movi_w_b(tms34010_state *tms, UINT16 op) { MOVI_W(B); }
	1081	void tms340x0_device::movi_w_a(UINT16 op) { MOVI_W(A); }
	1082	void tms340x0_device::movi_w_b(UINT16 op) { MOVI_W(B); }
1083	1083
1084	1084	#define MOVI_L(R) \
1085	1085	{ \
1086		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1087		CLR_NZV(tms); \
1088		*rd=PARAM_LONG(tms); \
1089		SET_NZ_VAL(tms, *rd); \
1090		COUNT_CYCLES(tms,3); \
	1086	INT32 *rd = &R##REG(DSTREG(op)); \
	1087	CLR_NZV(); \
	1088	*rd=PARAM_LONG(); \
	1089	SET_NZ_VAL(*rd); \
	1090	COUNT_CYCLES(3); \
1091	1091	}
1092		static void movi_l_a(tms34010_state *tms, UINT16 op) { MOVI_L(A); }
1093		static void movi_l_b(tms34010_state *tms, UINT16 op) { MOVI_L(B); }
	1092	void tms340x0_device::movi_l_a(UINT16 op) { MOVI_L(A); }
	1093	void tms340x0_device::movi_l_b(UINT16 op) { MOVI_L(B); }
1094	1094
1095	1095	#define MOVK(R) \
1096	1096	{ \
1097	1097	INT32 k = PARAM_K(op); if (!k) k = 32; \
1098		R##REG(tms,DSTREG(op)) = k; \
1099		COUNT_CYCLES(tms,1); \
	1098	R##REG(DSTREG(op)) = k; \
	1099	COUNT_CYCLES(1); \
1100	1100	}
1101		static void movk_a(tms34010_state *tms, UINT16 op) { MOVK(A); }
1102		static void movk_b(tms34010_state *tms, UINT16 op) { MOVK(B); }
	1101	void tms340x0_device::movk_a(UINT16 op) { MOVK(A); }
	1102	void tms340x0_device::movk_b(UINT16 op) { MOVK(B); }
1103	1103
1104	1104	#define MOVB_RN(R) \
1105	1105	{ \
1106		WBYTE(tms, R##REG(tms,DSTREG(op)),R##REG(tms,SRCREG(op))); \
1107		COUNT_CYCLES(tms,1); \
	1106	WBYTE(R##REG(DSTREG(op)),R##REG(SRCREG(op))); \
	1107	COUNT_CYCLES(1); \
1108	1108	}
1109		static void movb_rn_a(tms34010_state *tms, UINT16 op) { MOVB_RN(A); }
1110		static void movb_rn_b(tms34010_state *tms, UINT16 op) { MOVB_RN(B); }
	1109	void tms340x0_device::movb_rn_a(UINT16 op) { MOVB_RN(A); }
	1110	void tms340x0_device::movb_rn_b(UINT16 op) { MOVB_RN(B); }
1111	1111
1112	1112	#define MOVB_NR(R) \
1113	1113	{ \
1114		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1115		CLR_NZV(tms); \
1116		*rd = (INT8)RBYTE(tms, R##REG(tms,SRCREG(op))); \
1117		SET_NZ_VAL(tms, *rd); \
1118		COUNT_CYCLES(tms,3); \
	1114	INT32 *rd = &R##REG(DSTREG(op)); \
	1115	CLR_NZV(); \
	1116	*rd = (INT8)RBYTE(R##REG(SRCREG(op))); \
	1117	SET_NZ_VAL(*rd); \
	1118	COUNT_CYCLES(3); \
1119	1119	}
1120		static void movb_nr_a(tms34010_state *tms, UINT16 op) { MOVB_NR(A); }
1121		static void movb_nr_b(tms34010_state *tms, UINT16 op) { MOVB_NR(B); }
	1120	void tms340x0_device::movb_nr_a(UINT16 op) { MOVB_NR(A); }
	1121	void tms340x0_device::movb_nr_b(UINT16 op) { MOVB_NR(B); }
1122	1122
1123	1123	#define MOVB_NN(R) \
1124	1124	{ \
1125		WBYTE(tms, R##REG(tms,DSTREG(op)),(UINT32)(UINT8)RBYTE(tms, R##REG(tms,SRCREG(op))));\
1126		COUNT_CYCLES(tms,3); \
	1125	WBYTE(R##REG(DSTREG(op)),(UINT32)(UINT8)RBYTE(R##REG(SRCREG(op))));\
	1126	COUNT_CYCLES(3); \
1127	1127	}
1128		static void movb_nn_a(tms34010_state *tms, UINT16 op) { MOVB_NN(A); }
1129		static void movb_nn_b(tms34010_state *tms, UINT16 op) { MOVB_NN(B); }
	1128	void tms340x0_device::movb_nn_a(UINT16 op) { MOVB_NN(A); }
	1129	void tms340x0_device::movb_nn_b(UINT16 op) { MOVB_NN(B); }
1130	1130
1131	1131	#define MOVB_R_NO(R) \
1132	1132	{ \
1133		INT32 o = PARAM_WORD(tms); \
1134		WBYTE(tms, R##REG(tms,DSTREG(op))+o,R##REG(tms,SRCREG(op))); \
1135		COUNT_CYCLES(tms,3); \
	1133	INT32 o = PARAM_WORD(); \
	1134	WBYTE(R##REG(DSTREG(op))+o,R##REG(SRCREG(op))); \
	1135	COUNT_CYCLES(3); \
1136	1136	}
1137		static void movb_r_no_a(tms34010_state *tms, UINT16 op) { MOVB_R_NO(A); }
1138		static void movb_r_no_b(tms34010_state *tms, UINT16 op) { MOVB_R_NO(B); }
	1137	void tms340x0_device::movb_r_no_a(UINT16 op) { MOVB_R_NO(A); }
	1138	void tms340x0_device::movb_r_no_b(UINT16 op) { MOVB_R_NO(B); }
1139	1139
1140	1140	#define MOVB_NO_R(R) \
1141	1141	{ \
1142		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1143		INT32 o = PARAM_WORD(tms); \
1144		CLR_NZV(tms); \
1145		*rd = (INT8)RBYTE(tms, R##REG(tms,SRCREG(op))+o); \
1146		SET_NZ_VAL(tms, *rd); \
1147		COUNT_CYCLES(tms,5); \
	1142	INT32 *rd = &R##REG(DSTREG(op)); \
	1143	INT32 o = PARAM_WORD(); \
	1144	CLR_NZV(); \
	1145	*rd = (INT8)RBYTE(R##REG(SRCREG(op))+o); \
	1146	SET_NZ_VAL(*rd); \
	1147	COUNT_CYCLES(5); \
1148	1148	}
1149		static void movb_no_r_a(tms34010_state *tms, UINT16 op) { MOVB_NO_R(A); }
1150		static void movb_no_r_b(tms34010_state *tms, UINT16 op) { MOVB_NO_R(B); }
	1149	void tms340x0_device::movb_no_r_a(UINT16 op) { MOVB_NO_R(A); }
	1150	void tms340x0_device::movb_no_r_b(UINT16 op) { MOVB_NO_R(B); }
1151	1151
1152	1152	#define MOVB_NO_NO(R) \
1153	1153	{ \
1154		INT32 o1 = PARAM_WORD(tms); \
1155		INT32 o2 = PARAM_WORD(tms); \
1156		WBYTE(tms, R##REG(tms,DSTREG(op))+o2,(UINT32)(UINT8)RBYTE(tms, R##REG(tms,SRCREG(op))+o1)); \
1157		COUNT_CYCLES(tms,5); \
	1154	INT32 o1 = PARAM_WORD(); \
	1155	INT32 o2 = PARAM_WORD(); \
	1156	WBYTE(R##REG(DSTREG(op))+o2,(UINT32)(UINT8)RBYTE(R##REG(SRCREG(op))+o1)); \
	1157	COUNT_CYCLES(5); \
1158	1158	}
1159		static void movb_no_no_a(tms34010_state *tms, UINT16 op) { MOVB_NO_NO(A); }
1160		static void movb_no_no_b(tms34010_state *tms, UINT16 op) { MOVB_NO_NO(B); }
	1159	void tms340x0_device::movb_no_no_a(UINT16 op) { MOVB_NO_NO(A); }
	1160	void tms340x0_device::movb_no_no_b(UINT16 op) { MOVB_NO_NO(B); }
1161	1161
1162	1162	#define MOVB_RA(R) \
1163	1163	{ \
1164		WBYTE(tms, PARAM_LONG(tms),R##REG(tms,DSTREG(op))); \
1165		COUNT_CYCLES(tms,1); \
	1164	WBYTE(PARAM_LONG(),R##REG(DSTREG(op))); \
	1165	COUNT_CYCLES(1); \
1166	1166	}
1167		static void movb_ra_a(tms34010_state *tms, UINT16 op) { MOVB_RA(A); }
1168		static void movb_ra_b(tms34010_state *tms, UINT16 op) { MOVB_RA(B); }
	1167	void tms340x0_device::movb_ra_a(UINT16 op) { MOVB_RA(A); }
	1168	void tms340x0_device::movb_ra_b(UINT16 op) { MOVB_RA(B); }
1169	1169
1170	1170	#define MOVB_AR(R) \
1171	1171	{ \
1172		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1173		CLR_NZV(tms); \
1174		*rd = (INT8)RBYTE(tms, PARAM_LONG(tms)); \
1175		SET_NZ_VAL(tms, *rd); \
1176		COUNT_CYCLES(tms,5); \
	1172	INT32 *rd = &R##REG(DSTREG(op)); \
	1173	CLR_NZV(); \
	1174	*rd = (INT8)RBYTE(PARAM_LONG()); \
	1175	SET_NZ_VAL(*rd); \
	1176	COUNT_CYCLES(5); \
1177	1177	}
1178		static void movb_ar_a(tms34010_state *tms, UINT16 op) { MOVB_AR(A); }
1179		static void movb_ar_b(tms34010_state *tms, UINT16 op) { MOVB_AR(B); }
	1178	void tms340x0_device::movb_ar_a(UINT16 op) { MOVB_AR(A); }
	1179	void tms340x0_device::movb_ar_b(UINT16 op) { MOVB_AR(B); }
1180	1180
1181		~~static~~ void ~~movb_aa(~~tms34010_~~stat~~e *tms, UINT16 op)
	1181	void tms340x0_device::movb_aa(UINT16 op)
1182	1182	{
1183		UINT32 bitaddrs=PARAM_LONG(tms);
1184		WBYTE(tms, PARAM_LONG(tms),(UINT32)(UINT8)RBYTE(tms, bitaddrs));
1185		COUNT_CYCLES(tms,6);
	1183	UINT32 bitaddrs=PARAM_LONG();
	1184	WBYTE(PARAM_LONG(),(UINT32)(UINT8)RBYTE(bitaddrs));
	1185	COUNT_CYCLES(6);
1186	1186	}
1187	1187
1188	1188	#define MOVE_RR(RS,RD) \
1189	1189	{ \
1190		INT32 *rd = &RD##REG(tms,DSTREG(op)); \
1191		CLR_NZV(tms); \
1192		*rd = RS##REG(tms,SRCREG(op)); \
1193		SET_NZ_VAL(tms, *rd); \
1194		COUNT_CYCLES(tms,1); \
	1190	INT32 *rd = &RD##REG(DSTREG(op)); \
	1191	CLR_NZV(); \
	1192	*rd = RS##REG(SRCREG(op)); \
	1193	SET_NZ_VAL(*rd); \
	1194	COUNT_CYCLES(1); \
1195	1195	}
1196		static void move_rr_a (tms34010_state *tms, UINT16 op) { MOVE_RR(A,A); }
1197		static void move_rr_b (tms34010_state *tms, UINT16 op) { MOVE_RR(B,B); }
1198		static void move_rr_ax(tms34010_state *tms, UINT16 op) { MOVE_RR(A,B); }
1199		static void move_rr_bx(tms34010_state *tms, UINT16 op) { MOVE_RR(B,A); }
	1196	void tms340x0_device::move_rr_a (UINT16 op) { MOVE_RR(A,A); }
	1197	void tms340x0_device::move_rr_b (UINT16 op) { MOVE_RR(B,B); }
	1198	void tms340x0_device::move_rr_ax(UINT16 op) { MOVE_RR(A,B); }
	1199	void tms340x0_device::move_rr_bx(UINT16 op) { MOVE_RR(B,A); }
1200	1200
1201	1201	#define MOVE_RN(F,R) \
1202	1202	{ \
1203		WFIELD##F(tms,R##REG(tms,DSTREG(op)),R##REG(tms,SRCREG(op))); \
1204		COUNT_CYCLES(tms,1); \
	1203	WFIELD##F(R##REG(DSTREG(op)),R##REG(SRCREG(op))); \
	1204	COUNT_CYCLES(1); \
1205	1205	}
1206		static void move0_rn_a (tms34010_state *tms, UINT16 op) { MOVE_RN(0,A); }
1207		static void move0_rn_b (tms34010_state *tms, UINT16 op) { MOVE_RN(0,B); }
1208		static void move1_rn_a (tms34010_state *tms, UINT16 op) { MOVE_RN(1,A); }
1209		static void move1_rn_b (tms34010_state *tms, UINT16 op) { MOVE_RN(1,B); }
	1206	void tms340x0_device::move0_rn_a (UINT16 op) { MOVE_RN(0,A); }
	1207	void tms340x0_device::move0_rn_b (UINT16 op) { MOVE_RN(0,B); }
	1208	void tms340x0_device::move1_rn_a (UINT16 op) { MOVE_RN(1,A); }
	1209	void tms340x0_device::move1_rn_b (UINT16 op) { MOVE_RN(1,B); }
1210	1210
1211	1211	#define MOVE_R_DN(F,R) \
1212	1212	{ \
1213		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1214		*rd-=fw_inc[FW(tms,F)]; \
1215		WFIELD##F(tms,*rd,R##REG(tms,SRCREG(op))); \
1216		COUNT_CYCLES(tms,2); \
	1213	INT32 *rd = &R##REG(DSTREG(op)); \
	1214	*rd-=fw_inc[FW(F)]; \
	1215	WFIELD##F(*rd,R##REG(SRCREG(op))); \
	1216	COUNT_CYCLES(2); \
1217	1217	}
1218		static void move0_r_dn_a (tms34010_state *tms, UINT16 op) { MOVE_R_DN(0,A); }
1219		static void move0_r_dn_b (tms34010_state *tms, UINT16 op) { MOVE_R_DN(0,B); }
1220		static void move1_r_dn_a (tms34010_state *tms, UINT16 op) { MOVE_R_DN(1,A); }
1221		static void move1_r_dn_b (tms34010_state *tms, UINT16 op) { MOVE_R_DN(1,B); }
	1218	void tms340x0_device::move0_r_dn_a (UINT16 op) { MOVE_R_DN(0,A); }
	1219	void tms340x0_device::move0_r_dn_b (UINT16 op) { MOVE_R_DN(0,B); }
	1220	void tms340x0_device::move1_r_dn_a (UINT16 op) { MOVE_R_DN(1,A); }
	1221	void tms340x0_device::move1_r_dn_b (UINT16 op) { MOVE_R_DN(1,B); }
1222	1222
1223	1223	#define MOVE_R_NI(F,R) \
1224	1224	{ \
1225		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1226		WFIELD##F(tms,*rd,R##REG(tms,SRCREG(op))); \
1227		*rd+=fw_inc[FW(tms,F)]; \
1228		COUNT_CYCLES(tms,1); \
	1225	INT32 *rd = &R##REG(DSTREG(op)); \
	1226	WFIELD##F(*rd,R##REG(SRCREG(op))); \
	1227	*rd+=fw_inc[FW(F)]; \
	1228	COUNT_CYCLES(1); \
1229	1229	}
1230		static void move0_r_ni_a (tms34010_state *tms, UINT16 op) { MOVE_R_NI(0,A); }
1231		static void move0_r_ni_b (tms34010_state *tms, UINT16 op) { MOVE_R_NI(0,B); }
1232		static void move1_r_ni_a (tms34010_state *tms, UINT16 op) { MOVE_R_NI(1,A); }
1233		static void move1_r_ni_b (tms34010_state *tms, UINT16 op) { MOVE_R_NI(1,B); }
	1230	void tms340x0_device::move0_r_ni_a (UINT16 op) { MOVE_R_NI(0,A); }
	1231	void tms340x0_device::move0_r_ni_b (UINT16 op) { MOVE_R_NI(0,B); }
	1232	void tms340x0_device::move1_r_ni_a (UINT16 op) { MOVE_R_NI(1,A); }
	1233	void tms340x0_device::move1_r_ni_b (UINT16 op) { MOVE_R_NI(1,B); }
1234	1234
1235	1235	#define MOVE_NR(F,R) \
1236	1236	{ \
1237		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1238		CLR_NZV(tms); \
1239		*rd = RFIELD##F(tms,R##REG(tms,SRCREG(op))); \
1240		SET_NZ_VAL(tms, *rd); \
1241		COUNT_CYCLES(tms,3); \
	1237	INT32 *rd = &R##REG(DSTREG(op)); \
	1238	CLR_NZV(); \
	1239	*rd = RFIELD##F(R##REG(SRCREG(op))); \
	1240	SET_NZ_VAL(*rd); \
	1241	COUNT_CYCLES(3); \
1242	1242	}
1243		static void move0_nr_a (tms34010_state *tms, UINT16 op) { MOVE_NR(0,A); }
1244		static void move0_nr_b (tms34010_state *tms, UINT16 op) { MOVE_NR(0,B); }
1245		static void move1_nr_a (tms34010_state *tms, UINT16 op) { MOVE_NR(1,A); }
1246		static void move1_nr_b (tms34010_state *tms, UINT16 op) { MOVE_NR(1,B); }
	1243	void tms340x0_device::move0_nr_a (UINT16 op) { MOVE_NR(0,A); }
	1244	void tms340x0_device::move0_nr_b (UINT16 op) { MOVE_NR(0,B); }
	1245	void tms340x0_device::move1_nr_a (UINT16 op) { MOVE_NR(1,A); }
	1246	void tms340x0_device::move1_nr_b (UINT16 op) { MOVE_NR(1,B); }
1247	1247
1248	1248	#define MOVE_DN_R(F,R) \
1249	1249	{ \
1250		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1251		INT32 *rs = &R##REG(tms,SRCREG(op)); \
1252		CLR_NZV(tms); \
1253		*rs-=fw_inc[FW(tms,F)]; \
1254		rd = RFIELD##F(tms,rs); \
1255		SET_NZ_VAL(tms, *rd); \
1256		COUNT_CYCLES(tms,4); \
	1250	INT32 *rd = &R##REG(DSTREG(op)); \
	1251	INT32 *rs = &R##REG(SRCREG(op)); \
	1252	CLR_NZV(); \
	1253	*rs-=fw_inc[FW(F)]; \
	1254	rd = RFIELD##F(rs); \
	1255	SET_NZ_VAL(*rd); \
	1256	COUNT_CYCLES(4); \
1257	1257	}
1258		static void move0_dn_r_a (tms34010_state *tms, UINT16 op) { MOVE_DN_R(0,A); }
1259		static void move0_dn_r_b (tms34010_state *tms, UINT16 op) { MOVE_DN_R(0,B); }
1260		static void move1_dn_r_a (tms34010_state *tms, UINT16 op) { MOVE_DN_R(1,A); }
1261		static void move1_dn_r_b (tms34010_state *tms, UINT16 op) { MOVE_DN_R(1,B); }
	1258	void tms340x0_device::move0_dn_r_a (UINT16 op) { MOVE_DN_R(0,A); }
	1259	void tms340x0_device::move0_dn_r_b (UINT16 op) { MOVE_DN_R(0,B); }
	1260	void tms340x0_device::move1_dn_r_a (UINT16 op) { MOVE_DN_R(1,A); }
	1261	void tms340x0_device::move1_dn_r_b (UINT16 op) { MOVE_DN_R(1,B); }
1262	1262
1263	1263	#define MOVE_NI_R(F,R) \
1264	1264	{ \
1265		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1266		INT32 *rs = &R##REG(tms,SRCREG(op)); \
1267		INT32 data = RFIELD##F(tms,*rs); \
1268		CLR_NZV(tms); \
1269		*rs+=fw_inc[FW(tms,F)]; \
	1265	INT32 *rd = &R##REG(DSTREG(op)); \
	1266	INT32 *rs = &R##REG(SRCREG(op)); \
	1267	INT32 data = RFIELD##F(*rs); \
	1268	CLR_NZV(); \
	1269	*rs+=fw_inc[FW(F)]; \
1270	1270	*rd = data; \
1271		SET_NZ_VAL(tms, *rd); \
1272		COUNT_CYCLES(tms,3); \
	1271	SET_NZ_VAL(*rd); \
	1272	COUNT_CYCLES(3); \
1273	1273	}
1274		static void move0_ni_r_a (tms34010_state *tms, UINT16 op) { MOVE_NI_R(0,A); }
1275		static void move0_ni_r_b (tms34010_state *tms, UINT16 op) { MOVE_NI_R(0,B); }
1276		static void move1_ni_r_a (tms34010_state *tms, UINT16 op) { MOVE_NI_R(1,A); }
1277		static void move1_ni_r_b (tms34010_state *tms, UINT16 op) { MOVE_NI_R(1,B); }
	1274	void tms340x0_device::move0_ni_r_a (UINT16 op) { MOVE_NI_R(0,A); }
	1275	void tms340x0_device::move0_ni_r_b (UINT16 op) { MOVE_NI_R(0,B); }
	1276	void tms340x0_device::move1_ni_r_a (UINT16 op) { MOVE_NI_R(1,A); }
	1277	void tms340x0_device::move1_ni_r_b (UINT16 op) { MOVE_NI_R(1,B); }
1278	1278
1279	1279	#define MOVE_NN(F,R) \
1280	1280	{ \
1281		WFIELD##F(tms,R##REG(tms,DSTREG(op)),RFIELD##F(tms,R##REG(tms,SRCREG(op)))); \
1282		COUNT_CYCLES(tms,3); \
	1281	WFIELD##F(R##REG(DSTREG(op)),RFIELD##F(R##REG(SRCREG(op)))); \
	1282	COUNT_CYCLES(3); \
1283	1283	}
1284		static void move0_nn_a (tms34010_state *tms, UINT16 op) { MOVE_NN(0,A); }
1285		static void move0_nn_b (tms34010_state *tms, UINT16 op) { MOVE_NN(0,B); }
1286		static void move1_nn_a (tms34010_state *tms, UINT16 op) { MOVE_NN(1,A); }
1287		static void move1_nn_b (tms34010_state *tms, UINT16 op) { MOVE_NN(1,B); }
	1284	void tms340x0_device::move0_nn_a (UINT16 op) { MOVE_NN(0,A); }
	1285	void tms340x0_device::move0_nn_b (UINT16 op) { MOVE_NN(0,B); }
	1286	void tms340x0_device::move1_nn_a (UINT16 op) { MOVE_NN(1,A); }
	1287	void tms340x0_device::move1_nn_b (UINT16 op) { MOVE_NN(1,B); }
1288	1288
1289	1289	#define MOVE_DN_DN(F,R) \
1290	1290	{ \
1291		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1292		INT32 *rs = &R##REG(tms,SRCREG(op)); \
	1291	INT32 *rd = &R##REG(DSTREG(op)); \
	1292	INT32 *rs = &R##REG(SRCREG(op)); \
1293	1293	INT32 data; \
1294		*rs-=fw_inc[FW(tms,F)]; \
1295		data = RFIELD##F(tms,*rs); \
1296		*rd-=fw_inc[FW(tms,F)]; \
1297		WFIELD##F(tms,*rd,data); \
1298		COUNT_CYCLES(tms,4); \
	1294	*rs-=fw_inc[FW(F)]; \
	1295	data = RFIELD##F(*rs); \
	1296	*rd-=fw_inc[FW(F)]; \
	1297	WFIELD##F(*rd,data); \
	1298	COUNT_CYCLES(4); \
1299	1299	}
1300		static void move0_dn_dn_a (tms34010_state *tms, UINT16 op) { MOVE_DN_DN(0,A); }
1301		static void move0_dn_dn_b (tms34010_state *tms, UINT16 op) { MOVE_DN_DN(0,B); }
1302		static void move1_dn_dn_a (tms34010_state *tms, UINT16 op) { MOVE_DN_DN(1,A); }
1303		static void move1_dn_dn_b (tms34010_state *tms, UINT16 op) { MOVE_DN_DN(1,B); }
	1300	void tms340x0_device::move0_dn_dn_a (UINT16 op) { MOVE_DN_DN(0,A); }
	1301	void tms340x0_device::move0_dn_dn_b (UINT16 op) { MOVE_DN_DN(0,B); }
	1302	void tms340x0_device::move1_dn_dn_a (UINT16 op) { MOVE_DN_DN(1,A); }
	1303	void tms340x0_device::move1_dn_dn_b (UINT16 op) { MOVE_DN_DN(1,B); }
1304	1304
1305	1305	#define MOVE_NI_NI(F,R) \
1306	1306	{ \
1307		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1308		INT32 *rs = &R##REG(tms,SRCREG(op)); \
1309		INT32 data = RFIELD##F(tms,*rs); \
1310		*rs+=fw_inc[FW(tms,F)]; \
1311		WFIELD##F(tms,*rd,data); \
1312		*rd+=fw_inc[FW(tms,F)]; \
1313		COUNT_CYCLES(tms,4); \
	1307	INT32 *rd = &R##REG(DSTREG(op)); \
	1308	INT32 *rs = &R##REG(SRCREG(op)); \
	1309	INT32 data = RFIELD##F(*rs); \
	1310	*rs+=fw_inc[FW(F)]; \
	1311	WFIELD##F(*rd,data); \
	1312	*rd+=fw_inc[FW(F)]; \
	1313	COUNT_CYCLES(4); \
1314	1314	}
1315		static void move0_ni_ni_a (tms34010_state *tms, UINT16 op) { MOVE_NI_NI(0,A); }
1316		static void move0_ni_ni_b (tms34010_state *tms, UINT16 op) { MOVE_NI_NI(0,B); }
1317		static void move1_ni_ni_a (tms34010_state *tms, UINT16 op) { MOVE_NI_NI(1,A); }
1318		static void move1_ni_ni_b (tms34010_state *tms, UINT16 op) { MOVE_NI_NI(1,B); }
	1315	void tms340x0_device::move0_ni_ni_a (UINT16 op) { MOVE_NI_NI(0,A); }
	1316	void tms340x0_device::move0_ni_ni_b (UINT16 op) { MOVE_NI_NI(0,B); }
	1317	void tms340x0_device::move1_ni_ni_a (UINT16 op) { MOVE_NI_NI(1,A); }
	1318	void tms340x0_device::move1_ni_ni_b (UINT16 op) { MOVE_NI_NI(1,B); }
1319	1319
1320	1320	#define MOVE_R_NO(F,R) \
1321	1321	{ \
1322		INT32 o = PARAM_WORD(tms); \
1323		WFIELD##F(tms,R##REG(tms,DSTREG(op))+o,R##REG(tms,SRCREG(op))); \
1324		COUNT_CYCLES(tms,3); \
	1322	INT32 o = PARAM_WORD(); \
	1323	WFIELD##F(R##REG(DSTREG(op))+o,R##REG(SRCREG(op))); \
	1324	COUNT_CYCLES(3); \
1325	1325	}
1326		static void move0_r_no_a (tms34010_state *tms, UINT16 op) { MOVE_R_NO(0,A); }
1327		static void move0_r_no_b (tms34010_state *tms, UINT16 op) { MOVE_R_NO(0,B); }
1328		static void move1_r_no_a (tms34010_state *tms, UINT16 op) { MOVE_R_NO(1,A); }
1329		static void move1_r_no_b (tms34010_state *tms, UINT16 op) { MOVE_R_NO(1,B); }
	1326	void tms340x0_device::move0_r_no_a (UINT16 op) { MOVE_R_NO(0,A); }
	1327	void tms340x0_device::move0_r_no_b (UINT16 op) { MOVE_R_NO(0,B); }
	1328	void tms340x0_device::move1_r_no_a (UINT16 op) { MOVE_R_NO(1,A); }
	1329	void tms340x0_device::move1_r_no_b (UINT16 op) { MOVE_R_NO(1,B); }
1330	1330
1331	1331	#define MOVE_NO_R(F,R) \
1332	1332	{ \
1333		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1334		INT32 o = PARAM_WORD(tms); \
1335		CLR_NZV(tms); \
1336		*rd = RFIELD##F(tms,R##REG(tms,SRCREG(op))+o); \
1337		SET_NZ_VAL(tms, *rd); \
1338		COUNT_CYCLES(tms,5); \
	1333	INT32 *rd = &R##REG(DSTREG(op)); \
	1334	INT32 o = PARAM_WORD(); \
	1335	CLR_NZV(); \
	1336	*rd = RFIELD##F(R##REG(SRCREG(op))+o); \
	1337	SET_NZ_VAL(*rd); \
	1338	COUNT_CYCLES(5); \
1339	1339	}
1340		static void move0_no_r_a (tms34010_state *tms, UINT16 op) { MOVE_NO_R(0,A); }
1341		static void move0_no_r_b (tms34010_state *tms, UINT16 op) { MOVE_NO_R(0,B); }
1342		static void move1_no_r_a (tms34010_state *tms, UINT16 op) { MOVE_NO_R(1,A); }
1343		static void move1_no_r_b (tms34010_state *tms, UINT16 op) { MOVE_NO_R(1,B); }
	1340	void tms340x0_device::move0_no_r_a (UINT16 op) { MOVE_NO_R(0,A); }
	1341	void tms340x0_device::move0_no_r_b (UINT16 op) { MOVE_NO_R(0,B); }
	1342	void tms340x0_device::move1_no_r_a (UINT16 op) { MOVE_NO_R(1,A); }
	1343	void tms340x0_device::move1_no_r_b (UINT16 op) { MOVE_NO_R(1,B); }
1344	1344
1345	1345	#define MOVE_NO_NI(F,R) \
1346	1346	{ \
1347		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1348		INT32 o = PARAM_WORD(tms); \
1349		INT32 data = RFIELD##F(tms,R##REG(tms,SRCREG(op))+o); \
1350		WFIELD##F(tms,*rd,data); \
1351		*rd+=fw_inc[FW(tms,F)]; \
1352		COUNT_CYCLES(tms,5); \
	1347	INT32 *rd = &R##REG(DSTREG(op)); \
	1348	INT32 o = PARAM_WORD(); \
	1349	INT32 data = RFIELD##F(R##REG(SRCREG(op))+o); \
	1350	WFIELD##F(*rd,data); \
	1351	*rd+=fw_inc[FW(F)]; \
	1352	COUNT_CYCLES(5); \
1353	1353	}
1354		static void move0_no_ni_a (tms34010_state *tms, UINT16 op) { MOVE_NO_NI(0,A); }
1355		static void move0_no_ni_b (tms34010_state *tms, UINT16 op) { MOVE_NO_NI(0,B); }
1356		static void move1_no_ni_a (tms34010_state *tms, UINT16 op) { MOVE_NO_NI(1,A); }
1357		static void move1_no_ni_b (tms34010_state *tms, UINT16 op) { MOVE_NO_NI(1,B); }
	1354	void tms340x0_device::move0_no_ni_a (UINT16 op) { MOVE_NO_NI(0,A); }
	1355	void tms340x0_device::move0_no_ni_b (UINT16 op) { MOVE_NO_NI(0,B); }
	1356	void tms340x0_device::move1_no_ni_a (UINT16 op) { MOVE_NO_NI(1,A); }
	1357	void tms340x0_device::move1_no_ni_b (UINT16 op) { MOVE_NO_NI(1,B); }
1358	1358
1359	1359	#define MOVE_NO_NO(F,R) \
1360	1360	{ \
1361		INT32 o1 = PARAM_WORD(tms); \
1362		INT32 o2 = PARAM_WORD(tms); \
1363		INT32 data = RFIELD##F(tms,R##REG(tms,SRCREG(op))+o1); \
1364		WFIELD##F(tms,R##REG(tms,DSTREG(op))+o2,data); \
1365		COUNT_CYCLES(tms,5); \
	1361	INT32 o1 = PARAM_WORD(); \
	1362	INT32 o2 = PARAM_WORD(); \
	1363	INT32 data = RFIELD##F(R##REG(SRCREG(op))+o1); \
	1364	WFIELD##F(R##REG(DSTREG(op))+o2,data); \
	1365	COUNT_CYCLES(5); \
1366	1366	}
1367		static void move0_no_no_a (tms34010_state *tms, UINT16 op) { MOVE_NO_NO(0,A); }
1368		static void move0_no_no_b (tms34010_state *tms, UINT16 op) { MOVE_NO_NO(0,B); }
1369		static void move1_no_no_a (tms34010_state *tms, UINT16 op) { MOVE_NO_NO(1,A); }
1370		static void move1_no_no_b (tms34010_state *tms, UINT16 op) { MOVE_NO_NO(1,B); }
	1367	void tms340x0_device::move0_no_no_a (UINT16 op) { MOVE_NO_NO(0,A); }
	1368	void tms340x0_device::move0_no_no_b (UINT16 op) { MOVE_NO_NO(0,B); }
	1369	void tms340x0_device::move1_no_no_a (UINT16 op) { MOVE_NO_NO(1,A); }
	1370	void tms340x0_device::move1_no_no_b (UINT16 op) { MOVE_NO_NO(1,B); }
1371	1371
1372	1372	#define MOVE_RA(F,R) \
1373	1373	{ \
1374		WFIELD##F(tms,PARAM_LONG(tms),R##REG(tms,DSTREG(op))); \
1375		COUNT_CYCLES(tms,3); \
	1374	WFIELD##F(PARAM_LONG(),R##REG(DSTREG(op))); \
	1375	COUNT_CYCLES(3); \
1376	1376	}
1377		static void move0_ra_a (tms34010_state *tms, UINT16 op) { MOVE_RA(0,A); }
1378		static void move0_ra_b (tms34010_state *tms, UINT16 op) { MOVE_RA(0,B); }
1379		static void move1_ra_a (tms34010_state *tms, UINT16 op) { MOVE_RA(1,A); }
1380		static void move1_ra_b (tms34010_state *tms, UINT16 op) { MOVE_RA(1,B); }
	1377	void tms340x0_device::move0_ra_a (UINT16 op) { MOVE_RA(0,A); }
	1378	void tms340x0_device::move0_ra_b (UINT16 op) { MOVE_RA(0,B); }
	1379	void tms340x0_device::move1_ra_a (UINT16 op) { MOVE_RA(1,A); }
	1380	void tms340x0_device::move1_ra_b (UINT16 op) { MOVE_RA(1,B); }
1381	1381
1382	1382	#define MOVE_AR(F,R) \
1383	1383	{ \
1384		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1385		CLR_NZV(tms); \
1386		*rd = RFIELD##F(tms,PARAM_LONG(tms)); \
1387		SET_NZ_VAL(tms, *rd); \
1388		COUNT_CYCLES(tms,5); \
	1384	INT32 *rd = &R##REG(DSTREG(op)); \
	1385	CLR_NZV(); \
	1386	*rd = RFIELD##F(PARAM_LONG()); \
	1387	SET_NZ_VAL(*rd); \
	1388	COUNT_CYCLES(5); \
1389	1389	}
1390		static void move0_ar_a (tms34010_state *tms, UINT16 op) { MOVE_AR(0,A); }
1391		static void move0_ar_b (tms34010_state *tms, UINT16 op) { MOVE_AR(0,B); }
1392		static void move1_ar_a (tms34010_state *tms, UINT16 op) { MOVE_AR(1,A); }
1393		static void move1_ar_b (tms34010_state *tms, UINT16 op) { MOVE_AR(1,B); }
	1390	void tms340x0_device::move0_ar_a (UINT16 op) { MOVE_AR(0,A); }
	1391	void tms340x0_device::move0_ar_b (UINT16 op) { MOVE_AR(0,B); }
	1392	void tms340x0_device::move1_ar_a (UINT16 op) { MOVE_AR(1,A); }
	1393	void tms340x0_device::move1_ar_b (UINT16 op) { MOVE_AR(1,B); }
1394	1394
1395	1395	#define MOVE_A_NI(F,R) \
1396	1396	{ \
1397		INT32 *rd = &R##REG(tms,DSTREG(op)); \
1398		WFIELD##F(tms,*rd,RFIELD##F(tms,PARAM_LONG(tms))); \
1399		*rd+=fw_inc[FW(tms,F)]; \
1400		COUNT_CYCLES(tms,5); \
	1397	INT32 *rd = &R##REG(DSTREG(op)); \
	1398	WFIELD##F(*rd,RFIELD##F(PARAM_LONG())); \
	1399	*rd+=fw_inc[FW(F)]; \
	1400	COUNT_CYCLES(5); \
1401	1401	}
1402		static void move0_a_ni_a (tms34010_state *tms, UINT16 op) { MOVE_A_NI(0,A); }
1403		static void move0_a_ni_b (tms34010_state *tms, UINT16 op) { MOVE_A_NI(0,B); }
1404		static void move1_a_ni_a (tms34010_state *tms, UINT16 op) { MOVE_A_NI(1,A); }
1405		static void move1_a_ni_b (tms34010_state *tms, UINT16 op) { MOVE_A_NI(1,B); }
	1402	void tms340x0_device::move0_a_ni_a (UINT16 op) { MOVE_A_NI(0,A); }
	1403	void tms340x0_device::move0_a_ni_b (UINT16 op) { MOVE_A_NI(0,B); }
	1404	void tms340x0_device::move1_a_ni_a (UINT16 op) { MOVE_A_NI(1,A); }
	1405	void tms340x0_device::move1_a_ni_b (UINT16 op) { MOVE_A_NI(1,B); }
1406	1406
1407	1407	#define MOVE_AA(F) \
1408	1408	{ \
1409		UINT32 bitaddrs=PARAM_LONG(tms); \
1410		WFIELD##F(tms,PARAM_LONG(tms),RFIELD##F(tms,bitaddrs)); \
1411		COUNT_CYCLES(tms,7); \
	1409	UINT32 bitaddrs=PARAM_LONG(); \
	1410	WFIELD##F(PARAM_LONG(),RFIELD##F(bitaddrs)); \
	1411	COUNT_CYCLES(7); \
1412	1412	}
1413		static void move0_aa (tms34010_state *tms, UINT16 op) { MOVE_AA(0); }
1414		static void move1_aa (tms34010_state *tms, UINT16 op) { MOVE_AA(1); }
	1413	void tms340x0_device::move0_aa (UINT16 op) { MOVE_AA(0); }
	1414	void tms340x0_device::move1_aa (UINT16 op) { MOVE_AA(1); }
1415	1415
1416	1416
1417	1417
r31176	r31177
1421	1421
1422	1422	#define CALL(R) \
1423	1423	{ \
1424		PUSH(tms, tms->pc); \
1425		tms->pc = R##REG(tms,DSTREG(op)); \
1426		CORRECT_ODD_PC(tms,"CALL"); \
1427		COUNT_CYCLES(tms,3); \
	1424	PUSH(m_pc); \
	1425	m_pc = R##REG(DSTREG(op)); \
	1426	CORRECT_ODD_PC("CALL"); \
	1427	COUNT_CYCLES(3); \
1428	1428	}
1429		static void call_a (tms34010_state *tms, UINT16 op) { CALL(A); }
1430		static void call_b (tms34010_state *tms, UINT16 op) { CALL(B); }
	1429	void tms340x0_device::call_a (UINT16 op) { CALL(A); }
	1430	void tms340x0_device::call_b (UINT16 op) { CALL(B); }
1431	1431
1432		~~static~~ void ~~callr(~~tms34010_~~stat~~e *tms, UINT16 op)
	1432	void tms340x0_device::callr(UINT16 op)
1433	1433	{
1434		PUSH(tms, tms->pc+0x10);
1435		tms->pc += (PARAM_WORD_NO_INC(tms)<<4)+0x10;
1436		COUNT_CYCLES(tms,3);
	1434	PUSH(m_pc+0x10);
	1435	m_pc += (PARAM_WORD_NO_INC()<<4)+0x10;
	1436	COUNT_CYCLES(3);
1437	1437	}
1438	1438
1439		~~static~~ void ~~calla(~~tms34010_~~stat~~e *tms, UINT16 op)
	1439	void tms340x0_device::calla(UINT16 op)
1440	1440	{
1441		PUSH(tms, tms->pc+0x20);
1442		tms->pc = PARAM_LONG_NO_INC(tms);
1443		CORRECT_ODD_PC(tms,"CALLA");
1444		COUNT_CYCLES(tms,4);
	1441	PUSH(m_pc+0x20);
	1442	m_pc = PARAM_LONG_NO_INC();
	1443	CORRECT_ODD_PC("CALLA");
	1444	COUNT_CYCLES(4);
1445	1445	}
1446	1446
1447	1447	#define DSJ(R) \
1448	1448	{ \
1449		if (--R##REG(~~tms,~~DSTREG(op))) \
	1449	if (--R##REG(DSTREG(op))) \
1450	1450	{ \
1451		tms->pc += (PARAM_WORD_NO_INC(tms)<<4)+0x10; \
1452		COUNT_CYCLES(tms,3); \
	1451	m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; \
	1452	COUNT_CYCLES(3); \
1453	1453	} \
1454	1454	else \
1455	1455	{ \
1456		SKIP_WORD(tms); \
1457		COUNT_CYCLES(tms,2); \
	1456	SKIP_WORD(); \
	1457	COUNT_CYCLES(2); \
1458	1458	} \
1459	1459	}
1460		static void dsj_a (tms34010_state *tms, UINT16 op) { DSJ(A); }
1461		static void dsj_b (tms34010_state *tms, UINT16 op) { DSJ(B); }
	1460	void tms340x0_device::dsj_a (UINT16 op) { DSJ(A); }
	1461	void tms340x0_device::dsj_b (UINT16 op) { DSJ(B); }
1462	1462
1463	1463	#define DSJEQ(R) \
1464	1464	{ \
1465		if (Z_FLAG(~~tms~~)) \
	1465	if (Z_FLAG()) \
1466	1466	{ \
1467		if (--R##REG(~~tms,~~DSTREG(op))) \
	1467	if (--R##REG(DSTREG(op))) \
1468	1468	{ \
1469		tms->pc += (PARAM_WORD_NO_INC(tms)<<4)+0x10; \
1470		COUNT_CYCLES(tms,3); \
	1469	m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; \
	1470	COUNT_CYCLES(3); \
1471	1471	} \
1472	1472	else \
1473	1473	{ \
1474		SKIP_WORD(tms); \
1475		COUNT_CYCLES(tms,2); \
	1474	SKIP_WORD(); \
	1475	COUNT_CYCLES(2); \
1476	1476	} \
1477	1477	} \
1478	1478	else \
1479	1479	{ \
1480		SKIP_WORD(tms); \
1481		COUNT_CYCLES(tms,2); \
	1480	SKIP_WORD(); \
	1481	COUNT_CYCLES(2); \
1482	1482	} \
1483	1483	}
1484		static void dsjeq_a (tms34010_state *tms, UINT16 op) { DSJEQ(A); }
1485		static void dsjeq_b (tms34010_state *tms, UINT16 op) { DSJEQ(B); }
	1484	void tms340x0_device::dsjeq_a (UINT16 op) { DSJEQ(A); }
	1485	void tms340x0_device::dsjeq_b (UINT16 op) { DSJEQ(B); }
1486	1486
1487	1487	#define DSJNE(R) \
1488	1488	{ \
1489		if (!Z_FLAG(~~tms~~)) \
	1489	if (!Z_FLAG()) \
1490	1490	{ \
1491		if (--R##REG(~~tms,~~DSTREG(op))) \
	1491	if (--R##REG(DSTREG(op))) \
1492	1492	{ \
1493		tms->pc += (PARAM_WORD_NO_INC(tms)<<4)+0x10; \
1494		COUNT_CYCLES(tms,3); \
	1493	m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; \
	1494	COUNT_CYCLES(3); \
1495	1495	} \
1496	1496	else \
1497	1497	{ \
1498		SKIP_WORD(tms); \
1499		COUNT_CYCLES(tms,2); \
	1498	SKIP_WORD(); \
	1499	COUNT_CYCLES(2); \
1500	1500	} \
1501	1501	} \
1502	1502	else \
1503	1503	{ \
1504		SKIP_WORD(tms); \
1505		COUNT_CYCLES(tms,2); \
	1504	SKIP_WORD(); \
	1505	COUNT_CYCLES(2); \
1506	1506	} \
1507	1507	}
1508		static void dsjne_a (tms34010_state *tms, UINT16 op) { DSJNE(A); }
1509		static void dsjne_b (tms34010_state *tms, UINT16 op) { DSJNE(B); }
	1508	void tms340x0_device::dsjne_a (UINT16 op) { DSJNE(A); }
	1509	void tms340x0_device::dsjne_b (UINT16 op) { DSJNE(B); }
1510	1510
1511	1511	#define DSJS(R) \
1512	1512	{ \
1513	1513	if (op & 0x0400) \
1514	1514	{ \
1515		if (--R##REG(~~tms,~~DSTREG(op))) \
	1515	if (--R##REG(DSTREG(op))) \
1516	1516	{ \
1517		tms->pc -= ((PARAM_K(op))<<4); \
1518		COUNT_CYCLES(tms,2); \
	1517	m_pc -= ((PARAM_K(op))<<4); \
	1518	COUNT_CYCLES(2); \
1519	1519	} \
1520	1520	else \
1521		COUNT_CYCLES(~~tms,~~3); \
	1521	COUNT_CYCLES(3); \
1522	1522	} \
1523	1523	else \
1524	1524	{ \
1525		if (--R##REG(~~tms,~~DSTREG(op))) \
	1525	if (--R##REG(DSTREG(op))) \
1526	1526	{ \
1527		tms->pc += ((PARAM_K(op))<<4); \
1528		COUNT_CYCLES(tms,2); \
	1527	m_pc += ((PARAM_K(op))<<4); \
	1528	COUNT_CYCLES(2); \
1529	1529	} \
1530	1530	else \
1531		COUNT_CYCLES(~~tms,~~3); \
	1531	COUNT_CYCLES(3); \
1532	1532	} \
1533	1533	}
1534		static void dsjs_a (tms34010_state *tms, UINT16 op) { DSJS(A); }
1535		static void dsjs_b (tms34010_state *tms, UINT16 op) { DSJS(B); }
	1534	void tms340x0_device::dsjs_a (UINT16 op) { DSJS(A); }
	1535	void tms340x0_device::dsjs_b (UINT16 op) { DSJS(B); }
1536	1536
1537		~~static~~ void ~~emu(~~tms34010_~~stat~~e *tms, UINT16 op)
	1537	void tms340x0_device::emu(UINT16 op)
1538	1538	{
1539	1539	/* in RUN state, this instruction is a NOP */
1540		COUNT_CYCLES(~~tms,~~6);
	1540	COUNT_CYCLES(6);
1541	1541	}
1542	1542
1543	1543	#define EXGPC(R) \
1544	1544	{ \
1545		INT32 *rd = &R##REG(~~tms,~~DSTREG(op)); \
	1545	INT32 *rd = &R##REG(DSTREG(op)); \
1546	1546	INT32 temppc = *rd; \
1547		*rd = tms->pc; \
1548		tms->pc = temppc; \
1549		CORRECT_ODD_PC(tms,"EXGPC"); \
1550		COUNT_CYCLES(tms,2); \
	1547	*rd = m_pc; \
	1548	m_pc = temppc; \
	1549	CORRECT_ODD_PC("EXGPC"); \
	1550	COUNT_CYCLES(2); \
1551	1551	}
1552		static void exgpc_a (tms34010_state *tms, UINT16 op) { EXGPC(A); }
1553		static void exgpc_b (tms34010_state *tms, UINT16 op) { EXGPC(B); }
	1552	void tms340x0_device::exgpc_a (UINT16 op) { EXGPC(A); }
	1553	void tms340x0_device::exgpc_b (UINT16 op) { EXGPC(B); }
1554	1554
1555	1555	#define GETPC(R) \
1556	1556	{ \
1557		R##REG(tms,DSTREG(op)) = tms->pc; \
1558		COUNT_CYCLES(tms,1); \
	1557	R##REG(DSTREG(op)) = m_pc; \
	1558	COUNT_CYCLES(1); \
1559	1559	}
1560		static void getpc_a (tms34010_state *tms, UINT16 op) { GETPC(A); }
1561		static void getpc_b (tms34010_state *tms, UINT16 op) { GETPC(B); }
	1560	void tms340x0_device::getpc_a (UINT16 op) { GETPC(A); }
	1561	void tms340x0_device::getpc_b (UINT16 op) { GETPC(B); }
1562	1562
1563	1563	#define GETST(R) \
1564	1564	{ \
1565		R##REG(tms,DSTREG(op)) = tms->st; \
1566		COUNT_CYCLES(tms,1); \
	1565	R##REG(DSTREG(op)) = m_st; \
	1566	COUNT_CYCLES(1); \
1567	1567	}
1568		static void getst_a (tms34010_state *tms, UINT16 op) { GETST(A); }
1569		static void getst_b (tms34010_state *tms, UINT16 op) { GETST(B); }
	1568	void tms340x0_device::getst_a (UINT16 op) { GETST(A); }
	1569	void tms340x0_device::getst_b (UINT16 op) { GETST(B); }
1570	1570
1571	1571	#define j_xx_8(TAKE) \
1572	1572	{ \
r31176	r31177
1574	1574	{ \
1575	1575	if (TAKE) \
1576	1576	{ \
1577		tms->pc += (PARAM_REL8(op) << 4); \
1578		COUNT_CYCLES(tms,2); \
	1577	m_pc += (PARAM_REL8(op) << 4); \
	1578	COUNT_CYCLES(2); \
1579	1579	} \
1580	1580	else \
1581		COUNT_CYCLES(~~tms,~~1); \
	1581	COUNT_CYCLES(1); \
1582	1582	} \
1583	1583	else \
1584	1584	{ \
1585	1585	if (TAKE) \
1586	1586	{ \
1587		tms->pc = PARAM_LONG_NO_INC(tms); \
1588		CORRECT_ODD_PC(tms,"J_XX_8"); \
1589		COUNT_CYCLES(tms,3); \
	1587	m_pc = PARAM_LONG_NO_INC(); \
	1588	CORRECT_ODD_PC("J_XX_8"); \
	1589	COUNT_CYCLES(3); \
1590	1590	} \
1591	1591	else \
1592	1592	{ \
1593		SKIP_LONG(tms); \
1594		COUNT_CYCLES(tms,4); \
	1593	SKIP_LONG(); \
	1594	COUNT_CYCLES(4); \
1595	1595	} \
1596	1596	} \
1597	1597	}
r31176	r31177
1602	1602	{ \
1603	1603	if (TAKE) \
1604	1604	{ \
1605		tms->pc += (PARAM_REL8(op) << 4); \
1606		COUNT_CYCLES(tms,2); \
	1605	m_pc += (PARAM_REL8(op) << 4); \
	1606	COUNT_CYCLES(2); \
1607	1607	} \
1608	1608	else \
1609		COUNT_CYCLES(~~tms,~~1); \
	1609	COUNT_CYCLES(1); \
1610	1610	} \
1611	1611	else \
1612	1612	{ \
1613	1613	if (TAKE) \
1614	1614	{ \
1615		tms->pc += (PARAM_WORD_NO_INC(tms)<<4)+0x10; \
1616		COUNT_CYCLES(tms,3); \
	1615	m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; \
	1616	COUNT_CYCLES(3); \
1617	1617	} \
1618	1618	else \
1619	1619	{ \
1620		SKIP_WORD(tms); \
1621		COUNT_CYCLES(tms,2); \
	1620	SKIP_WORD(); \
	1621	COUNT_CYCLES(2); \
1622	1622	} \
1623	1623	} \
1624	1624	}
r31176	r31177
1627	1627	{ \
1628	1628	if (TAKE) \
1629	1629	{ \
1630		tms->pc += (PARAM_REL8(op) << 4); \
1631		COUNT_CYCLES(tms,2); \
	1630	m_pc += (PARAM_REL8(op) << 4); \
	1631	COUNT_CYCLES(2); \
1632	1632	} \
1633	1633	else \
1634		COUNT_CYCLES(~~tms,~~1); \
	1634	COUNT_CYCLES(1); \
1635	1635	}
1636	1636
1637		~~static~~ void ~~j_UC_0(~~tms34010_~~stat~~e *tms, UINT16 op)
	1637	void tms340x0_device::j_UC_0(UINT16 op)
1638	1638	{
1639	1639	j_xx_0(1);
1640	1640	}
1641		~~static~~ void ~~j_UC_8(~~tms34010_~~stat~~e *tms, UINT16 op)
	1641	void tms340x0_device::j_UC_8(UINT16 op)
1642	1642	{
1643	1643	j_xx_8(1);
1644	1644	}
1645		~~static~~ void ~~j_UC_x(~~tms34010_~~stat~~e *tms, UINT16 op)
	1645	void tms340x0_device::j_UC_x(UINT16 op)
1646	1646	{
1647	1647	j_xx_x(1);
1648	1648	}
1649		~~static~~ void ~~j_P_0(~~tms34010_~~stat~~e *tms, UINT16 op)
	1649	void tms340x0_device::j_P_0(UINT16 op)
1650	1650	{
1651		j_xx_0(!N_FLAG(~~tms~~) && !Z_FLAG(~~tms~~));
	1651	j_xx_0(!N_FLAG() && !Z_FLAG());
1652	1652	}
1653		~~static~~ void ~~j_P_8(~~tms34010_~~stat~~e *tms, UINT16 op)
	1653	void tms340x0_device::j_P_8(UINT16 op)
1654	1654	{
1655		j_xx_8(!N_FLAG(~~tms~~) && !Z_FLAG(~~tms~~));
	1655	j_xx_8(!N_FLAG() && !Z_FLAG());
1656	1656	}
1657		~~static~~ void ~~j_P_x(~~tms34010_~~stat~~e *tms, UINT16 op)
	1657	void tms340x0_device::j_P_x(UINT16 op)
1658	1658	{
1659		j_xx_x(!N_FLAG(~~tms~~) && !Z_FLAG(~~tms~~));
	1659	j_xx_x(!N_FLAG() && !Z_FLAG());
1660	1660	}
1661		~~static~~ void ~~j_LS_0(~~tms34010_~~stat~~e *tms, UINT16 op)
	1661	void tms340x0_device::j_LS_0(UINT16 op)
1662	1662	{
1663		j_xx_0(C_FLAG(~~tms~~) \|\| Z_FLAG(~~tms~~));
	1663	j_xx_0(C_FLAG() \|\| Z_FLAG());
1664	1664	}
1665		~~static~~ void ~~j_LS_8(~~tms34010_~~stat~~e *tms, UINT16 op)
	1665	void tms340x0_device::j_LS_8(UINT16 op)
1666	1666	{
1667		j_xx_8(C_FLAG(~~tms~~) \|\| Z_FLAG(~~tms~~));
	1667	j_xx_8(C_FLAG() \|\| Z_FLAG());
1668	1668	}
1669		~~static~~ void ~~j_LS_x(~~tms34010_~~stat~~e *tms, UINT16 op)
	1669	void tms340x0_device::j_LS_x(UINT16 op)
1670	1670	{
1671		j_xx_x(C_FLAG(~~tms~~) \|\| Z_FLAG(~~tms~~));
	1671	j_xx_x(C_FLAG() \|\| Z_FLAG());
1672	1672	}
1673		~~static~~ void ~~j_HI_0(~~tms34010_~~stat~~e *tms, UINT16 op)
	1673	void tms340x0_device::j_HI_0(UINT16 op)
1674	1674	{
1675		j_xx_0(!C_FLAG(~~tms~~) && !Z_FLAG(~~tms~~));
	1675	j_xx_0(!C_FLAG() && !Z_FLAG());
1676	1676	}
1677		~~static~~ void ~~j_HI_8(~~tms34010_~~stat~~e *tms, UINT16 op)
	1677	void tms340x0_device::j_HI_8(UINT16 op)
1678	1678	{
1679		j_xx_8(!C_FLAG(~~tms~~) && !Z_FLAG(~~tms~~));
	1679	j_xx_8(!C_FLAG() && !Z_FLAG());
1680	1680	}
1681		~~static~~ void ~~j_HI_x(~~tms34010_~~stat~~e *tms, UINT16 op)
	1681	void tms340x0_device::j_HI_x(UINT16 op)
1682	1682	{
1683		j_xx_x(!C_FLAG(~~tms~~) && !Z_FLAG(~~tms~~));
	1683	j_xx_x(!C_FLAG() && !Z_FLAG());
1684	1684	}
1685		~~static~~ void ~~j_LT_0(~~tms34010_~~stat~~e *tms, UINT16 op)
	1685	void tms340x0_device::j_LT_0(UINT16 op)
1686	1686	{
1687		j_xx_0((N_FLAG(~~tms~~) && !V_FLAG(~~tms~~)) \|\| (!N_FLAG(~~tms~~) && V_FLAG(~~tms~~)));
	1687	j_xx_0((N_FLAG() && !V_FLAG()) \|\| (!N_FLAG() && V_FLAG()));
1688	1688	}
1689		~~static~~ void ~~j_LT_8(~~tms34010_~~stat~~e *tms, UINT16 op)
	1689	void tms340x0_device::j_LT_8(UINT16 op)
1690	1690	{
1691		j_xx_8((N_FLAG(~~tms~~) && !V_FLAG(~~tms~~)) \|\| (!N_FLAG(~~tms~~) && V_FLAG(~~tms~~)));
	1691	j_xx_8((N_FLAG() && !V_FLAG()) \|\| (!N_FLAG() && V_FLAG()));
1692	1692	}
1693		~~static~~ void ~~j_LT_x(~~tms34010_~~stat~~e *tms, UINT16 op)
	1693	void tms340x0_device::j_LT_x(UINT16 op)
1694	1694	{
1695		j_xx_x((N_FLAG(~~tms~~) && !V_FLAG(~~tms~~)) \|\| (!N_FLAG(~~tms~~) && V_FLAG(~~tms~~)));
	1695	j_xx_x((N_FLAG() && !V_FLAG()) \|\| (!N_FLAG() && V_FLAG()));
1696	1696	}
1697		~~static~~ void ~~j_GE_0(~~tms34010_~~stat~~e *tms, UINT16 op)
	1697	void tms340x0_device::j_GE_0(UINT16 op)
1698	1698	{
1699		j_xx_0((N_FLAG(~~tms~~) && V_FLAG(~~tms~~)) \|\| (!N_FLAG(~~tms~~) && !V_FLAG(~~tms~~)));
	1699	j_xx_0((N_FLAG() && V_FLAG()) \|\| (!N_FLAG() && !V_FLAG()));
1700	1700	}
1701		~~static~~ void ~~j_GE_8(~~tms34010_~~stat~~e *tms, UINT16 op)
	1701	void tms340x0_device::j_GE_8(UINT16 op)
1702	1702	{
1703		j_xx_8((N_FLAG(~~tms~~) && V_FLAG(~~tms~~)) \|\| (!N_FLAG(~~tms~~) && !V_FLAG(~~tms~~)));
	1703	j_xx_8((N_FLAG() && V_FLAG()) \|\| (!N_FLAG() && !V_FLAG()));
1704	1704	}
1705		~~static~~ void ~~j_GE_x(~~tms34010_~~stat~~e *tms, UINT16 op)
	1705	void tms340x0_device::j_GE_x(UINT16 op)
1706	1706	{
1707		j_xx_x((N_FLAG(~~tms~~) && V_FLAG(~~tms~~)) \|\| (!N_FLAG(~~tms~~) && !V_FLAG(~~tms~~)));
	1707	j_xx_x((N_FLAG() && V_FLAG()) \|\| (!N_FLAG() && !V_FLAG()));
1708	1708	}
1709		~~static~~ void ~~j_LE_0(~~tms34010_~~stat~~e *tms, UINT16 op)
	1709	void tms340x0_device::j_LE_0(UINT16 op)
1710	1710	{
1711		j_xx_0((N_FLAG(~~tms~~) && !V_FLAG(~~tms~~)) \|\| (!N_FLAG(~~tms~~) && V_FLAG(~~tms~~)) \|\| Z_FLAG(~~tms~~));
	1711	j_xx_0((N_FLAG() && !V_FLAG()) \|\| (!N_FLAG() && V_FLAG()) \|\| Z_FLAG());
1712	1712	}
1713		~~static~~ void ~~j_LE_8(~~tms34010_~~stat~~e *tms, UINT16 op)
	1713	void tms340x0_device::j_LE_8(UINT16 op)
1714	1714	{
1715		j_xx_8((N_FLAG(~~tms~~) && !V_FLAG(~~tms~~)) \|\| (!N_FLAG(~~tms~~) && V_FLAG(~~tms~~)) \|\| Z_FLAG(~~tms~~));
	1715	j_xx_8((N_FLAG() && !V_FLAG()) \|\| (!N_FLAG() && V_FLAG()) \|\| Z_FLAG());
1716	1716	}
1717		~~static~~ void ~~j_LE_x(~~tms34010_~~stat~~e *tms, UINT16 op)
	1717	void tms340x0_device::j_LE_x(UINT16 op)
1718	1718	{
1719		j_xx_x((N_FLAG(~~tms~~) && !V_FLAG(~~tms~~)) \|\| (!N_FLAG(~~tms~~) && V_FLAG(~~tms~~)) \|\| Z_FLAG(~~tms~~));
	1719	j_xx_x((N_FLAG() && !V_FLAG()) \|\| (!N_FLAG() && V_FLAG()) \|\| Z_FLAG());
1720	1720	}
1721		~~static~~ void ~~j_GT_0(~~tms34010_~~stat~~e *tms, UINT16 op)
	1721	void tms340x0_device::j_GT_0(UINT16 op)
1722	1722	{
1723		j_xx_0((N_FLAG(~~tms~~) && V_FLAG(~~tms~~) && !Z_FLAG(~~tms~~)) \|\| (!N_FLAG(~~tms~~) && !V_FLAG(~~tms~~) && !Z_FLAG(~~tms~~)));
	1723	j_xx_0((N_FLAG() && V_FLAG() && !Z_FLAG()) \|\| (!N_FLAG() && !V_FLAG() && !Z_FLAG()));
1724	1724	}
1725		~~static~~ void ~~j_GT_8(~~tms34010_~~stat~~e *tms, UINT16 op)
	1725	void tms340x0_device::j_GT_8(UINT16 op)
1726	1726	{
1727		j_xx_8((N_FLAG(~~tms~~) && V_FLAG(~~tms~~) && !Z_FLAG(~~tms~~)) \|\| (!N_FLAG(~~tms~~) && !V_FLAG(~~tms~~) && !Z_FLAG(~~tms~~)));
	1727	j_xx_8((N_FLAG() && V_FLAG() && !Z_FLAG()) \|\| (!N_FLAG() && !V_FLAG() && !Z_FLAG()));
1728	1728	}
1729		~~static~~ void ~~j_GT_x(~~tms34010_~~stat~~e *tms, UINT16 op)
	1729	void tms340x0_device::j_GT_x(UINT16 op)
1730	1730	{
1731		j_xx_x((N_FLAG(~~tms~~) && V_FLAG(~~tms~~) && !Z_FLAG(~~tms~~)) \|\| (!N_FLAG(~~tms~~) && !V_FLAG(~~tms~~) && !Z_FLAG(~~tms~~)));
	1731	j_xx_x((N_FLAG() && V_FLAG() && !Z_FLAG()) \|\| (!N_FLAG() && !V_FLAG() && !Z_FLAG()));
1732	1732	}
1733		~~static~~ void ~~j_C_0(~~tms34010_~~stat~~e *tms, UINT16 op)
	1733	void tms340x0_device::j_C_0(UINT16 op)
1734	1734	{
1735		j_xx_0(C_FLAG(~~tms~~));
	1735	j_xx_0(C_FLAG());
1736	1736	}
1737		~~static~~ void ~~j_C_8(~~tms34010_~~stat~~e *tms, UINT16 op)
	1737	void tms340x0_device::j_C_8(UINT16 op)
1738	1738	{
1739		j_xx_8(C_FLAG(~~tms~~));
	1739	j_xx_8(C_FLAG());
1740	1740	}
1741		~~static~~ void ~~j_C_x(~~tms34010_~~stat~~e *tms, UINT16 op)
	1741	void tms340x0_device::j_C_x(UINT16 op)
1742	1742	{
1743		j_xx_x(C_FLAG(~~tms~~));
	1743	j_xx_x(C_FLAG());
1744	1744	}
1745		~~static~~ void ~~j_NC_0(~~tms34010_~~stat~~e *tms, UINT16 op)
	1745	void tms340x0_device::j_NC_0(UINT16 op)
1746	1746	{
1747		j_xx_0(!C_FLAG(~~tms~~));
	1747	j_xx_0(!C_FLAG());
1748	1748	}
1749		~~static~~ void ~~j_NC_8(~~tms34010_~~stat~~e *tms, UINT16 op)
	1749	void tms340x0_device::j_NC_8(UINT16 op)
1750	1750	{
1751		j_xx_8(!C_FLAG(~~tms~~));
	1751	j_xx_8(!C_FLAG());
1752	1752	}
1753		~~static~~ void ~~j_NC_x(~~tms34010_~~stat~~e *tms, UINT16 op)
	1753	void tms340x0_device::j_NC_x(UINT16 op)
1754	1754	{
1755		j_xx_x(!C_FLAG(~~tms~~));
	1755	j_xx_x(!C_FLAG());
1756	1756	}
1757		~~static~~ void ~~j_EQ_0(~~tms34010_~~stat~~e *tms, UINT16 op)
	1757	void tms340x0_device::j_EQ_0(UINT16 op)
1758	1758	{
1759		j_xx_0(Z_FLAG(~~tms~~));
	1759	j_xx_0(Z_FLAG());
1760	1760	}
1761		~~static~~ void ~~j_EQ_8(~~tms34010_~~stat~~e *tms, UINT16 op)
	1761	void tms340x0_device::j_EQ_8(UINT16 op)
1762	1762	{
1763		j_xx_8(Z_FLAG(~~tms~~));
	1763	j_xx_8(Z_FLAG());
1764	1764	}
1765		~~static~~ void ~~j_EQ_x(~~tms34010_~~stat~~e *tms, UINT16 op)
	1765	void tms340x0_device::j_EQ_x(UINT16 op)
1766	1766	{
1767		j_xx_x(Z_FLAG(~~tms~~));
	1767	j_xx_x(Z_FLAG());
1768	1768	}
1769		~~static~~ void ~~j_NE_0(~~tms34010_~~stat~~e *tms, UINT16 op)
	1769	void tms340x0_device::j_NE_0(UINT16 op)
1770	1770	{
1771		j_xx_0(!Z_FLAG(~~tms~~));
	1771	j_xx_0(!Z_FLAG());
1772	1772	}
1773		~~static~~ void ~~j_NE_8(~~tms34010_~~stat~~e *tms, UINT16 op)
	1773	void tms340x0_device::j_NE_8(UINT16 op)
1774	1774	{
1775		j_xx_8(!Z_FLAG(~~tms~~));
	1775	j_xx_8(!Z_FLAG());
1776	1776	}
1777		~~static~~ void ~~j_NE_x(~~tms34010_~~stat~~e *tms, UINT16 op)
	1777	void tms340x0_device::j_NE_x(UINT16 op)
1778	1778	{
1779		j_xx_x(!Z_FLAG(~~tms~~));
	1779	j_xx_x(!Z_FLAG());
1780	1780	}
1781		~~static~~ void ~~j_V_0(~~tms34010_~~stat~~e *tms, UINT16 op)
	1781	void tms340x0_device::j_V_0(UINT16 op)
1782	1782	{
1783		j_xx_0(V_FLAG(~~tms~~));
	1783	j_xx_0(V_FLAG());
1784	1784	}
1785		~~static~~ void ~~j_V_8(~~tms34010_~~stat~~e *tms, UINT16 op)
	1785	void tms340x0_device::j_V_8(UINT16 op)
1786	1786	{
1787		j_xx_8(V_FLAG(~~tms~~));
	1787	j_xx_8(V_FLAG());
1788	1788	}
1789		~~static~~ void ~~j_V_x(~~tms34010_~~stat~~e *tms, UINT16 op)
	1789	void tms340x0_device::j_V_x(UINT16 op)
1790	1790	{
1791		j_xx_x(V_FLAG(~~tms~~));
	1791	j_xx_x(V_FLAG());
1792	1792	}
1793		~~static~~ void ~~j_NV_0(~~tms34010_~~stat~~e *tms, UINT16 op)
	1793	void tms340x0_device::j_NV_0(UINT16 op)
1794	1794	{
1795		j_xx_0(!V_FLAG(~~tms~~));
	1795	j_xx_0(!V_FLAG());
1796	1796	}
1797		~~static~~ void ~~j_NV_8(~~tms34010_~~stat~~e *tms, UINT16 op)
	1797	void tms340x0_device::j_NV_8(UINT16 op)
1798	1798	{
1799		j_xx_8(!V_FLAG(~~tms~~));
	1799	j_xx_8(!V_FLAG());
1800	1800	}
1801		~~static~~ void ~~j_NV_x(~~tms34010_~~stat~~e *tms, UINT16 op)
	1801	void tms340x0_device::j_NV_x(UINT16 op)
1802	1802	{
1803		j_xx_x(!V_FLAG(~~tms~~));
	1803	j_xx_x(!V_FLAG());
1804	1804	}
1805		~~static~~ void ~~j_N_0(~~tms34010_~~stat~~e *tms, UINT16 op)
	1805	void tms340x0_device::j_N_0(UINT16 op)
1806	1806	{
1807		j_xx_0(N_FLAG(~~tms~~));
	1807	j_xx_0(N_FLAG());
1808	1808	}
1809		~~static~~ void ~~j_N_8(~~tms34010_~~stat~~e *tms, UINT16 op)
	1809	void tms340x0_device::j_N_8(UINT16 op)
1810	1810	{
1811		j_xx_8(N_FLAG(~~tms~~));
	1811	j_xx_8(N_FLAG());
1812	1812	}
1813		~~static~~ void ~~j_N_x(~~tms34010_~~stat~~e *tms, UINT16 op)
	1813	void tms340x0_device::j_N_x(UINT16 op)
1814	1814	{
1815		j_xx_x(N_FLAG(~~tms~~));
	1815	j_xx_x(N_FLAG());
1816	1816	}
1817		~~static~~ void ~~j_NN_0(~~tms34010_~~stat~~e *tms, UINT16 op)
	1817	void tms340x0_device::j_NN_0(UINT16 op)
1818	1818	{
1819		j_xx_0(!N_FLAG(~~tms~~));
	1819	j_xx_0(!N_FLAG());
1820	1820	}
1821		~~static~~ void ~~j_NN_8(~~tms34010_~~stat~~e *tms, UINT16 op)
	1821	void tms340x0_device::j_NN_8(UINT16 op)
1822	1822	{
1823		j_xx_8(!N_FLAG(~~tms~~));
	1823	j_xx_8(!N_FLAG());
1824	1824	}
1825		~~static~~ void ~~j_NN_x(~~tms34010_~~stat~~e *tms, UINT16 op)
	1825	void tms340x0_device::j_NN_x(UINT16 op)
1826	1826	{
1827		j_xx_x(!N_FLAG(~~tms~~));
	1827	j_xx_x(!N_FLAG());
1828	1828	}
1829	1829
1830	1830	#define JUMP(R) \
1831	1831	{ \
1832		tms->pc = R##REG(tms,DSTREG(op)); \
1833		CORRECT_ODD_PC(tms,"JUMP"); \
1834		COUNT_CYCLES(tms,2); \
	1832	m_pc = R##REG(DSTREG(op)); \
	1833	CORRECT_ODD_PC("JUMP"); \
	1834	COUNT_CYCLES(2); \
1835	1835	}
1836		static void jump_a (tms34010_state *tms, UINT16 op) { JUMP(A); }
1837		static void jump_b (tms34010_state *tms, UINT16 op) { JUMP(B); }
	1836	void tms340x0_device::jump_a (UINT16 op) { JUMP(A); }
	1837	void tms340x0_device::jump_b (UINT16 op) { JUMP(B); }
1838	1838
1839		~~static~~ void ~~pops~~t(tms34010_~~stat~~e *tms, UINT16 op)
	1839	void tms340x0_device::popst(UINT16 op)
1840	1840	{
1841		SET_ST(tms, POP(tms));
1842		COUNT_CYCLES(tms,8);
	1841	SET_ST(POP());
	1842	COUNT_CYCLES(8);
1843	1843	}
1844	1844
1845		~~static~~ void ~~pushs~~t(tms34010_~~stat~~e *tms, UINT16 op)
	1845	void tms340x0_device::pushst(UINT16 op)
1846	1846	{
1847		PUSH(tms, tms->st);
1848		COUNT_CYCLES(tms,2);
	1847	PUSH(m_st);
	1848	COUNT_CYCLES(2);
1849	1849	}
1850	1850
1851	1851	#define PUTST(R) \
1852	1852	{ \
1853		SET_ST(tms, R##REG(tms,DSTREG(op))); \
1854		COUNT_CYCLES(tms,3); \
	1853	SET_ST(R##REG(DSTREG(op))); \
	1854	COUNT_CYCLES(3); \
1855	1855	}
1856		static void putst_a (tms34010_state *tms, UINT16 op) { PUTST(A); }
1857		static void putst_b (tms34010_state *tms, UINT16 op) { PUTST(B); }
	1856	void tms340x0_device::putst_a (UINT16 op) { PUTST(A); }
	1857	void tms340x0_device::putst_b (UINT16 op) { PUTST(B); }
1858	1858
1859		~~static~~ void ret~~i(t~~ms34010_~~stat~~e *t~~ms,~~ UINT16 op)
	1859	void tms340x0_device::reti(UINT16 op)
1860	1860	{
1861		INT32 st = POP(tms);
1862		tms->pc = POP(tms);
1863		CORRECT_ODD_PC(tms,"RETI");
1864		SET_ST(tms, st);
1865		COUNT_CYCLES(tms,11);
	1861	INT32 st = POP();
	1862	m_pc = POP();
	1863	CORRECT_ODD_PC("RETI");
	1864	SET_ST(st);
	1865	COUNT_CYCLES(11);
1866	1866	}
1867	1867
1868		~~static~~ void ret~~s(t~~ms34010_~~stat~~e *tms, UINT16 op)
	1868	void tms340x0_device::rets(UINT16 op)
1869	1869	{
1870	1870	UINT32 offs;
1871		tms->pc = POP(tms);
1872		CORRECT_ODD_PC(tms,"RETS");
	1871	m_pc = POP();
	1872	CORRECT_ODD_PC("RETS");
1873	1873	offs = PARAM_N(op);
1874	1874	if (offs)
1875	1875	{
1876		SP(~~tms~~)+=(offs<<4);
	1876	SP()+=(offs<<4);
1877	1877	}
1878		COUNT_CYCLES(~~tms,~~7);
	1878	COUNT_CYCLES(7);
1879	1879	}
1880	1880
1881	1881	#define REV(R) \
1882	1882	{ \
1883		R##REG(tms,DSTREG(op)) = 0x0008; \
1884		COUNT_CYCLES(tms,1); \
	1883	R##REG(DSTREG(op)) = 0x0008; \
	1884	COUNT_CYCLES(1); \
1885	1885	}
1886		static void rev_a (tms34010_state *tms, UINT16 op) { REV(A); }
1887		static void rev_b (tms34010_state *tms, UINT16 op) { REV(B); }
	1886	void tms340x0_device::rev_a (UINT16 op) { REV(A); }
	1887	void tms340x0_device::rev_b (UINT16 op) { REV(B); }
1888	1888
1889		~~static~~ void t~~rap(t~~ms34010_~~stat~~e *t~~ms,~~ UINT16 op)
	1889	void tms340x0_device::trap(UINT16 op)
1890	1890	{
1891	1891	UINT32 t = PARAM_N(op);
1892	1892	if (t)
1893	1893	{
1894		PUSH(tms, tms->pc);
1895		PUSH(tms, tms->st);
	1894	PUSH(m_pc);
	1895	PUSH(m_st);
1896	1896	}
1897		RESET_ST(tms);
1898		tms->pc = RLONG(tms, 0xffffffe0-(t<<5));
1899		CORRECT_ODD_PC(tms,"TRAP");
1900		COUNT_CYCLES(tms,16);
	1897	RESET_ST();
	1898	m_pc = RLONG(0xffffffe0-(t<<5));
	1899	CORRECT_ODD_PC("TRAP");
	1900	COUNT_CYCLES(16);
1901	1901	}
1902	1902
1903	1903
r31176	r31177
2018	2018
2019	2019	#define ADD_XYI(R) \
2020	2020	{ \
2021		UINT32 a = PARAM_LONG(tms); \
2022		XY *b = &R##REG_XY(tms,DSTREG(op)); \
2023		CLR_NCZV(tms); \
	2021	UINT32 a = PARAM_LONG(); \
	2022	XY *b = &R##REG_XY(DSTREG(op)); \
	2023	CLR_NCZV(); \
2024	2024	b->x += (INT16)(a & 0xffff); \
2025	2025	b->y += ((INT32)a >> 16); \
2026		SET_N_LOG(tms, b->x == 0); \
2027		SET_C_BIT_LO(tms, b->y, 15); \
2028		SET_Z_LOG(tms, b->y == 0); \
2029		SET_V_BIT_LO(tms, b->x, 15); \
2030		COUNT_CYCLES(tms,1); \
	2026	SET_N_LOG(b->x == 0); \
	2027	SET_C_BIT_LO(b->y, 15); \
	2028	SET_Z_LOG(b->y == 0); \
	2029	SET_V_BIT_LO(b->x, 15); \
	2030	COUNT_CYCLES(1); \
2031	2031	}
2032		~~static~~ void ~~addxyi_a(~~tms34010_~~stat~~e *tms, UINT16 op)
	2032	void tms340x0_device::addxyi_a(UINT16 op)
2033	2033	{
2034		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2034	if (!m_is_34020) { unimpl(op); return; }
2035	2035	ADD_XYI(A);
2036	2036	}
2037		~~static~~ void ~~addxyi_b(~~tms34010_~~stat~~e *tms, UINT16 op)
	2037	void tms340x0_device::addxyi_b(UINT16 op)
2038	2038	{
2039		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2039	if (!m_is_34020) { unimpl(op); return; }
2040	2040	ADD_XYI(B);
2041	2041	}
2042	2042
2043		~~static~~ void ~~blmove(~~tms34010_~~stat~~e *tms, UINT16 op)
	2043	void tms340x0_device::blmove(UINT16 op)
2044	2044	{
2045		offs_t src = BREG(tms,0);
2046		offs_t dst = BREG(tms,2);
2047		offs_t bits = BREG(tms,7);
	2045	offs_t src = BREG(0);
	2046	offs_t dst = BREG(2);
	2047	offs_t bits = BREG(7);
2048	2048
2049		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2049	if (!m_is_34020) { unimpl(op); return; }
2050	2050
2051	2051	/* src and dst are aligned */
2052	2052	if (!(src & 0x0f) && !(dst & 0x0f))
2053	2053	{
2054		while (bits >= 16 && tm~~s->~~icount > 0)
	2054	while (bits >= 16 && m_icount > 0)
2055	2055	{
2056		TMS34010_WRMEM_WORD(~~tms,~~ TOBYTE(dst), TMS34010_RDMEM_WORD(~~tms,~~ TOBYTE(src)));
	2056	TMS34010_WRMEM_WORD(TOBYTE(dst), TMS34010_RDMEM_WORD(TOBYTE(src)));
2057	2057	src += 0x10;
2058	2058	dst += 0x10;
2059	2059	bits -= 0x10;
2060		tm~~s->~~icount -= 2;
	2060	m_icount -= 2;
2061	2061	}
2062		if (bits != 0 && tm~~s->~~icount > 0)
	2062	if (bits != 0 && m_icount > 0)
2063	2063	{
2064		(tms~~34010~~_wfield_functions[bits])(~~tms,~~ dst, (tms~~34010~~_rfield_functions[bits])(~~tms,~~ src));
	2064	(this->s_wfield_functions[bits])(dst, (this->s_rfield_functions[bits])(src));
2065	2065	dst += bits;
2066	2066	src += bits;
2067	2067	bits = 0;
2068		tm~~s->~~icount -= 2;
	2068	m_icount -= 2;
2069	2069	}
2070	2070	}
2071	2071
r31176	r31177
2088	2088	}
2089	2089
2090	2090	/* update the final results */
2091		BREG(tms,0) = src;
2092		BREG(tms,2) = dst;
2093		BREG(tms,7) = bits;
	2091	BREG(0) = src;
	2092	BREG(2) = dst;
	2093	BREG(7) = bits;
2094	2094
2095	2095	/* if we're not done yet, back up the PC */
2096	2096	if (bits != 0)
2097		tm~~s->~~pc -= 0x10;
	2097	m_pc -= 0x10;
2098	2098	}
2099	2099
2100		~~static~~ void ~~cexec_l(~~tms34010_~~stat~~e *tms, UINT16 op)
	2100	void tms340x0_device::cexec_l(UINT16 op)
2101	2101	{
2102		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2102	if (!m_is_34020) { unimpl(op); return; }
2103	2103	logerror("020:cexec_l\n");
2104	2104	}
2105	2105
2106		~~static~~ void ~~cexec_s(~~tms34010_~~stat~~e *tms, UINT16 op)
	2106	void tms340x0_device::cexec_s(UINT16 op)
2107	2107	{
2108		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2108	if (!m_is_34020) { unimpl(op); return; }
2109	2109	logerror("020:cexec_s\n");
2110	2110	}
2111	2111
2112		~~static~~ void ~~clip(~~tms34010_~~stat~~e *tms, UINT16 op)
	2112	void tms340x0_device::clip(UINT16 op)
2113	2113	{
2114		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2114	if (!m_is_34020) { unimpl(op); return; }
2115	2115	logerror("020:clip\n");
2116	2116	}
2117	2117
2118		~~static~~ void ~~cmovcg_a(~~tms34010_~~stat~~e *tms, UINT16 op)
	2118	void tms340x0_device::cmovcg_a(UINT16 op)
2119	2119	{
2120		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2120	if (!m_is_34020) { unimpl(op); return; }
2121	2121	logerror("020:cmovcg_a\n");
2122	2122	}
2123	2123
2124		~~static~~ void ~~cmovcg_b(~~tms34010_~~stat~~e *tms, UINT16 op)
	2124	void tms340x0_device::cmovcg_b(UINT16 op)
2125	2125	{
2126		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2126	if (!m_is_34020) { unimpl(op); return; }
2127	2127	logerror("020:cmovcg_b\n");
2128	2128	}
2129	2129
2130		~~static~~ void ~~cmovcm_f(~~tms34010_~~stat~~e *tms, UINT16 op)
	2130	void tms340x0_device::cmovcm_f(UINT16 op)
2131	2131	{
2132		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2132	if (!m_is_34020) { unimpl(op); return; }
2133	2133	logerror("020:cmovcm_f\n");
2134	2134	}
2135	2135
2136		~~static~~ void ~~cmovcm_b(~~tms34010_~~stat~~e *tms, UINT16 op)
	2136	void tms340x0_device::cmovcm_b(UINT16 op)
2137	2137	{
2138		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2138	if (!m_is_34020) { unimpl(op); return; }
2139	2139	logerror("020:cmovcm_b\n");
2140	2140	}
2141	2141
2142		~~static~~ void ~~cmovgc_a(~~tms34010_~~stat~~e *tms, UINT16 op)
	2142	void tms340x0_device::cmovgc_a(UINT16 op)
2143	2143	{
2144		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2144	if (!m_is_34020) { unimpl(op); return; }
2145	2145	logerror("020:cmovgc_a\n");
2146	2146	}
2147	2147
2148		~~static~~ void ~~cmovgc_b(~~tms34010_~~stat~~e *tms, UINT16 op)
	2148	void tms340x0_device::cmovgc_b(UINT16 op)
2149	2149	{
2150		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2150	if (!m_is_34020) { unimpl(op); return; }
2151	2151	logerror("020:cmovgc_b\n");
2152	2152	}
2153	2153
2154		~~static~~ void ~~cmovgc_a_s(~~tms34010_~~stat~~e *tms, UINT16 op)
	2154	void tms340x0_device::cmovgc_a_s(UINT16 op)
2155	2155	{
2156		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2156	if (!m_is_34020) { unimpl(op); return; }
2157	2157	logerror("020:cmovgc_a_s\n");
2158	2158	}
2159	2159
2160		~~static~~ void ~~cmovgc_b_s(~~tms34010_~~stat~~e *tms, UINT16 op)
	2160	void tms340x0_device::cmovgc_b_s(UINT16 op)
2161	2161	{
2162		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2162	if (!m_is_34020) { unimpl(op); return; }
2163	2163	logerror("020:cmovgc_b_s\n");
2164	2164	}
2165	2165
2166		~~static~~ void ~~cmovmc_f(~~tms34010_~~stat~~e *tms, UINT16 op)
	2166	void tms340x0_device::cmovmc_f(UINT16 op)
2167	2167	{
2168		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2168	if (!m_is_34020) { unimpl(op); return; }
2169	2169	logerror("020:cmovmc_f\n");
2170	2170	}
2171	2171
2172		~~static~~ void cmovmc_f_va(~~tms34010_state *tms,~~ UINT16 op)
	2172	void tms340x0_device::cmovmc_f_va(UINT16 op)
2173	2173	{
2174		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2174	if (!m_is_34020) { unimpl(op); return; }
2175	2175	logerror("020:cmovmc_f_va\n");
2176	2176	}
2177	2177
2178		~~static~~ void cmovmc_f_vb(~~tms34010_state *tms,~~ UINT16 op)
	2178	void tms340x0_device::cmovmc_f_vb(UINT16 op)
2179	2179	{
2180		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2180	if (!m_is_34020) { unimpl(op); return; }
2181	2181	logerror("020:cmovmc_f_vb\n");
2182	2182	}
2183	2183
2184		~~static~~ void ~~cmovmc_b(~~tms34010_~~stat~~e *tms, UINT16 op)
	2184	void tms340x0_device::cmovmc_b(UINT16 op)
2185	2185	{
2186		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2186	if (!m_is_34020) { unimpl(op); return; }
2187	2187	logerror("020:cmovmc_b\n");
2188	2188	}
2189	2189
2190	2190	#define CMPK(R) \
2191	2191	{ \
2192	2192	INT32 r; \
2193		INT32 *rd = &R##REG(~~tms,~~DSTREG(op)); \
	2193	INT32 *rd = &R##REG(DSTREG(op)); \
2194	2194	INT32 t = PARAM_K(op); if (!t) t = 32; \
2195		CLR_NCZV(~~tms~~); \
	2195	CLR_NCZV(); \
2196	2196	r = *rd - t; \
2197		SET_NZCV_SUB(tms,*rd,t,r); \
2198		COUNT_CYCLES(tms,1); \
	2197	SET_NZCV_SUB(*rd,t,r); \
	2198	COUNT_CYCLES(1); \
2199	2199	}
2200		~~static~~ void ~~cmp_k_a(~~tms34010_~~stat~~e *tms, UINT16 op)
	2200	void tms340x0_device::cmp_k_a(UINT16 op)
2201	2201	{
2202		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2202	if (!m_is_34020) { unimpl(op); return; }
2203	2203	CMPK(A);
2204	2204	}
2205		~~static~~ void ~~cmp_k_b(~~tms34010_~~stat~~e *tms, UINT16 op)
	2205	void tms340x0_device::cmp_k_b(UINT16 op)
2206	2206	{
2207		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2207	if (!m_is_34020) { unimpl(op); return; }
2208	2208	CMPK(B);
2209	2209	}
2210	2210
2211		~~static~~ void ~~cvdxyl_a(~~tms34010_~~stat~~e *tms, UINT16 op)
	2211	void tms340x0_device::cvdxyl_a(UINT16 op)
2212	2212	{
2213		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2213	if (!m_is_34020) { unimpl(op); return; }
2214	2214	logerror("020:cvdxyl_a\n");
2215	2215	}
2216	2216
2217		~~static~~ void ~~cvdxyl_b(~~tms34010_~~stat~~e *tms, UINT16 op)
	2217	void tms340x0_device::cvdxyl_b(UINT16 op)
2218	2218	{
2219		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2219	if (!m_is_34020) { unimpl(op); return; }
2220	2220	logerror("020:cvdxyl_b\n");
2221	2221	}
2222	2222
2223		~~static~~ void ~~cvmxyl_a(~~tms34010_~~stat~~e *tms, UINT16 op)
	2223	void tms340x0_device::cvmxyl_a(UINT16 op)
2224	2224	{
2225		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2225	if (!m_is_34020) { unimpl(op); return; }
2226	2226	logerror("020:cvmxyl_a\n");
2227	2227	}
2228	2228
2229		~~static~~ void ~~cvmxyl_b(~~tms34010_~~stat~~e *tms, UINT16 op)
	2229	void tms340x0_device::cvmxyl_b(UINT16 op)
2230	2230	{
2231		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2231	if (!m_is_34020) { unimpl(op); return; }
2232	2232	logerror("020:cvmxyl_b\n");
2233	2233	}
2234	2234
2235		~~static~~ void ~~cvsxyl_a(~~tms34010_~~stat~~e *tms, UINT16 op)
	2235	void tms340x0_device::cvsxyl_a(UINT16 op)
2236	2236	{
2237		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2237	if (!m_is_34020) { unimpl(op); return; }
2238	2238	logerror("020:cvsxyl_a\n");
2239	2239	}
2240	2240
2241		~~static~~ void ~~cvsxyl_b(~~tms34010_~~stat~~e *tms, UINT16 op)
	2241	void tms340x0_device::cvsxyl_b(UINT16 op)
2242	2242	{
2243		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2243	if (!m_is_34020) { unimpl(op); return; }
2244	2244	logerror("020:cvsxyl_b\n");
2245	2245	}
2246	2246
2247		~~static~~ void ~~exgps_a(~~tms34010_~~stat~~e *tms, UINT16 op)
	2247	void tms340x0_device::exgps_a(UINT16 op)
2248	2248	{
2249		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2249	if (!m_is_34020) { unimpl(op); return; }
2250	2250	logerror("020:exgps_a\n");
2251	2251	}
2252	2252
2253		~~static~~ void ~~exgps_b(~~tms34010_~~stat~~e *tms, UINT16 op)
	2253	void tms340x0_device::exgps_b(UINT16 op)
2254	2254	{
2255		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2255	if (!m_is_34020) { unimpl(op); return; }
2256	2256	logerror("020:exgps_b\n");
2257	2257	}
2258	2258
2259		~~static~~ void ~~fline(~~tms34010_~~stat~~e *tms, UINT16 op)
	2259	void tms340x0_device::fline(UINT16 op)
2260	2260	{
2261		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2261	if (!m_is_34020) { unimpl(op); return; }
2262	2262	logerror("020:fline\n");
2263	2263	}
2264	2264
2265		~~static~~ void ~~fpixeq(~~tms34010_~~stat~~e *tms, UINT16 op)
	2265	void tms340x0_device::fpixeq(UINT16 op)
2266	2266	{
2267		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2267	if (!m_is_34020) { unimpl(op); return; }
2268	2268	logerror("020:fpixeq\n");
2269	2269	}
2270	2270
2271		~~static~~ void ~~fpixne(~~tms34010_~~stat~~e *tms, UINT16 op)
	2271	void tms340x0_device::fpixne(UINT16 op)
2272	2272	{
2273		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2273	if (!m_is_34020) { unimpl(op); return; }
2274	2274	logerror("020:fpixne\n");
2275	2275	}
2276	2276
2277		~~static~~ void get~~ps_a(t~~ms34010_~~stat~~e *tms, UINT16 op)
	2277	void tms340x0_device::getps_a(UINT16 op)
2278	2278	{
2279		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2279	if (!m_is_34020) { unimpl(op); return; }
2280	2280	logerror("020:getps_a\n");
2281	2281	}
2282	2282
2283		~~static~~ void get~~ps_b(t~~ms34010_~~stat~~e *tms, UINT16 op)
	2283	void tms340x0_device::getps_b(UINT16 op)
2284	2284	{
2285		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2285	if (!m_is_34020) { unimpl(op); return; }
2286	2286	logerror("020:getps_b\n");
2287	2287	}
2288	2288
2289		~~static~~ void ~~idle(~~tms34010_~~stat~~e *tms, UINT16 op)
	2289	void tms340x0_device::idle(UINT16 op)
2290	2290	{
2291		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2291	if (!m_is_34020) { unimpl(op); return; }
2292	2292	logerror("020:idle\n");
2293	2293	}
2294	2294
2295		~~static~~ void ~~lini~~t(tms34010_~~stat~~e *t~~ms,~~ UINT16 op)
	2295	void tms340x0_device::linit(UINT16 op)
2296	2296	{
2297		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2297	if (!m_is_34020) { unimpl(op); return; }
2298	2298	logerror("020:linit\n");
2299	2299	}
2300	2300
2301		~~static~~ void ~~mwai~~t(tms34010_~~stat~~e *tms, UINT16 op)
	2301	void tms340x0_device::mwait(UINT16 op)
2302	2302	{
2303		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2303	if (!m_is_34020) { unimpl(op); return; }
2304	2304	}
2305	2305
2306		~~static~~ void ~~pfill_xy(~~tms34010_~~stat~~e *tms, UINT16 op)
	2306	void tms340x0_device::pfill_xy(UINT16 op)
2307	2307	{
2308		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2308	if (!m_is_34020) { unimpl(op); return; }
2309	2309	logerror("020:pfill_xy\n");
2310	2310	}
2311	2311
2312		~~static~~ void pixblt_l_m_l(~~tms34010_state *tms,~~ UINT16 op)
	2312	void tms340x0_device::pixblt_l_m_l(UINT16 op)
2313	2313	{
2314		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2314	if (!m_is_34020) { unimpl(op); return; }
2315	2315	logerror("020:pixblt_l_m_l\n");
2316	2316	}
2317	2317
2318		~~static~~ void retm~~(tm~~s34010_~~stat~~e *tms, UINT16 op)
	2318	void tms340x0_device::retm(UINT16 op)
2319	2319	{
2320		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2320	if (!m_is_34020) { unimpl(op); return; }
2321	2321	logerror("020:retm\n");
2322	2322	}
2323	2323
2324	2324	#define RMO(R) \
2325	2325	{ \
2326	2326	UINT32 res = 0; \
2327		UINT32 rs = R##REG(tms,SRCREG(op)); \
2328		INT32 *rd = &R##REG(tms,DSTREG(op)); \
2329		CLR_Z(tms); \
2330		SET_Z_VAL(tms, rs); \
	2327	UINT32 rs = R##REG(SRCREG(op)); \
	2328	INT32 *rd = &R##REG(DSTREG(op)); \
	2329	CLR_Z(); \
	2330	SET_Z_VAL(rs); \
2331	2331	if (rs) \
2332	2332	{ \
2333	2333	while (!(rs & 0x00000001)) \
r31176	r31177
2337	2337	} \
2338	2338	} \
2339	2339	*rd = res; \
2340		COUNT_CYCLES(~~tms,~~1); \
	2340	COUNT_CYCLES(1); \
2341	2341	}
2342	2342
2343		static void rmo_a(tms34010_state *tms, UINT16 op) { RMO(A); }
2344		static void rmo_b(tms34010_state *tms, UINT16 op) { RMO(B); }
	2343	void tms340x0_device::rmo_a(UINT16 op) { RMO(A); }
	2344	void tms340x0_device::rmo_b(UINT16 op) { RMO(B); }
2345	2345
2346	2346	#define RPIX(R) \
2347	2347	{ \
2348		UINT32 v = R##REG(tms,DSTREG(op)); \
2349		switch (tms->pixelshift) \
	2348	UINT32 v = R##REG(DSTREG(op)); \
	2349	switch (m_pixelshift) \
2350	2350	{ \
2351	2351	case 0: \
2352	2352	v = (v & 1) ? 0xffffffff : 0x00000000;\
2353		COUNT_CYCLES(~~tms,~~8); \
	2353	COUNT_CYCLES(8); \
2354	2354	break; \
2355	2355	case 1: \
2356	2356	v &= 3; \
r31176	r31177
2358	2358	v \|= v << 4; \
2359	2359	v \|= v << 8; \
2360	2360	v \|= v << 16; \
2361		COUNT_CYCLES(~~tms,~~7); \
	2361	COUNT_CYCLES(7); \
2362	2362	break; \
2363	2363	case 2: \
2364	2364	v &= 0x0f; \
2365	2365	v \|= v << 4; \
2366	2366	v \|= v << 8; \
2367	2367	v \|= v << 16; \
2368		COUNT_CYCLES(~~tms,~~6); \
	2368	COUNT_CYCLES(6); \
2369	2369	break; \
2370	2370	case 3: \
2371	2371	v &= 0xff; \
2372	2372	v \|= v << 8; \
2373	2373	v \|= v << 16; \
2374		COUNT_CYCLES(~~tms,~~5); \
	2374	COUNT_CYCLES(5); \
2375	2375	break; \
2376	2376	case 4: \
2377	2377	v &= 0xffff; \
2378	2378	v \|= v << 16; \
2379		COUNT_CYCLES(~~tms,~~4); \
	2379	COUNT_CYCLES(4); \
2380	2380	break; \
2381	2381	case 5: \
2382		COUNT_CYCLES(~~tms,~~2); \
	2382	COUNT_CYCLES(2); \
2383	2383	break; \
2384	2384	} \
2385		R##REG(~~tms,~~DSTREG(op)) = v; \
	2385	R##REG(DSTREG(op)) = v; \
2386	2386	}
2387	2387
2388		~~static~~ void ~~rpix_a(~~tms34010_~~stat~~e *tms, UINT16 op)
	2388	void tms340x0_device::rpix_a(UINT16 op)
2389	2389	{
2390		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2390	if (!m_is_34020) { unimpl(op); return; }
2391	2391	RPIX(A);
2392	2392	}
2393	2393
2394		~~static~~ void ~~rpix_b(~~tms34010_~~stat~~e *tms, UINT16 op)
	2394	void tms340x0_device::rpix_b(UINT16 op)
2395	2395	{
2396		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2396	if (!m_is_34020) { unimpl(op); return; }
2397	2397	RPIX(B);
2398	2398	}
2399	2399
2400		~~static~~ void set~~cdp(t~~ms34010_s~~tat~~e *t~~ms,~~ UINT16 op)
	2400	void tms340x0_device::setcdp(UINT16 op)
2401	2401	{
2402		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2402	if (!m_is_34020) { unimpl(op); return; }
2403	2403	logerror("020:setcdp\n");
2404	2404	}
2405	2405
2406		~~static~~ void setcm~~p(tm~~s34010_s~~tat~~e *tms, UINT16 op)
	2406	void tms340x0_device::setcmp(UINT16 op)
2407	2407	{
2408		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2408	if (!m_is_34020) { unimpl(op); return; }
2409	2409	logerror("020:setcmp\n");
2410	2410	}
2411	2411
2412		~~static~~ void set~~csp(t~~ms34010_s~~tat~~e *tms, UINT16 op)
	2412	void tms340x0_device::setcsp(UINT16 op)
2413	2413	{
2414		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2414	if (!m_is_34020) { unimpl(op); return; }
2415	2415	logerror("020:setcsp\n");
2416	2416	}
2417	2417
2418		~~static~~ void ~~swapf_a(~~tms34010_~~stat~~e *tms, UINT16 op)
	2418	void tms340x0_device::swapf_a(UINT16 op)
2419	2419	{
2420		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2420	if (!m_is_34020) { unimpl(op); return; }
2421	2421	logerror("020:swapf_a\n");
2422	2422	}
2423	2423
2424		~~static~~ void ~~swapf_b(~~tms34010_~~stat~~e *tms, UINT16 op)
	2424	void tms340x0_device::swapf_b(UINT16 op)
2425	2425	{
2426		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2426	if (!m_is_34020) { unimpl(op); return; }
2427	2427	logerror("020:swapf_b\n");
2428	2428	}
2429	2429
2430		~~static~~ void t~~fill_xy(t~~ms34010_~~stat~~e *t~~ms,~~ UINT16 op)
	2430	void tms340x0_device::tfill_xy(UINT16 op)
2431	2431	{
2432		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2432	if (!m_is_34020) { unimpl(op); return; }
2433	2433	logerror("020:tfill_xy\n");
2434	2434	}
2435	2435
2436		~~static~~ void t~~rapl(t~~ms34010_~~stat~~e *t~~ms,~~ UINT16 op)
	2436	void tms340x0_device::trapl(UINT16 op)
2437	2437	{
2438		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2438	if (!m_is_34020) { unimpl(op); return; }
2439	2439	logerror("020:trapl\n");
2440	2440	}
2441	2441
2442		~~static~~ void ~~vbl~~t~~_b_l(t~~ms34010_~~stat~~e *t~~ms,~~ UINT16 op)
	2442	void tms340x0_device::vblt_b_l(UINT16 op)
2443	2443	{
2444		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2444	if (!m_is_34020) { unimpl(op); return; }
2445	2445	logerror("020:vblt_b_l\n");
2446	2446	}
2447	2447
2448		~~static~~ void ~~vfill_l(~~tms34010_~~stat~~e *tms, UINT16 op)
	2448	void tms340x0_device::vfill_l(UINT16 op)
2449	2449	{
2450		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2450	if (!m_is_34020) { unimpl(op); return; }
2451	2451	logerror("020:vfill_l\n");
2452	2452	}
2453	2453
2454		~~static~~ void ~~vlcol(~~tms34010_~~stat~~e *tms, UINT16 op)
	2454	void tms340x0_device::vlcol(UINT16 op)
2455	2455	{
2456		if (!tm~~s->~~is_34020) { unimpl(~~tms,~~ op); return; }
	2456	if (!m_is_34020) { unimpl(op); return; }
2457	2457	logerror("020:vlcol\n");
2458	2458	}

trunk/src/emu/cpu/tms34010/34010tbl.c
r31176	r31177
6	6
7	7	*****************************************************************************/
8	8
9		static void unimpl(tms34010_state *tms, UINT16 op);
10
11		/* Graphics Instructions */
12
13		static void pixblt_l_l(tms34010_state tms, UINT16 op); / 0f00 */
14		static void pixblt_l_xy(tms34010_state tms, UINT16 op); / 0f20 */
15		static void pixblt_xy_l(tms34010_state tms, UINT16 op); / 0f40 */
16		static void pixblt_xy_xy(tms34010_state tms, UINT16 op); / 0f60 */
17		static void pixblt_b_l(tms34010_state tms, UINT16 op); / 0f80 */
18		static void pixblt_b_xy(tms34010_state tms, UINT16 op); / 0fa0 */
19		static void fill_l(tms34010_state tms, UINT16 op); / 0fc0 */
20		static void fill_xy(tms34010_state tms, UINT16 op); / 0fe0 */
21		static void line(tms34010_state tms, UINT16 op); / df10/df90 */
22		static void add_xy_a(tms34010_state tms, UINT16 op); / e000/e100 */
23		static void add_xy_b(tms34010_state tms, UINT16 op); / e000/e100 */
24		static void sub_xy_a(tms34010_state tms, UINT16 op); / e200/e300 */
25		static void sub_xy_b(tms34010_state tms, UINT16 op); / e200/e300 */
26		static void cmp_xy_a(tms34010_state tms, UINT16 op); / e400/e500 */
27		static void cmp_xy_b(tms34010_state tms, UINT16 op); / e400/e500 */
28		static void cpw_a(tms34010_state tms, UINT16 op); / e600/e700 */
29		static void cpw_b(tms34010_state tms, UINT16 op); / e600/e700 */
30		static void cvxyl_a(tms34010_state tms, UINT16 op); / e800/e900 */
31		static void cvxyl_b(tms34010_state tms, UINT16 op); / e800/e900 */
32		static void movx_a(tms34010_state tms, UINT16 op); / ec00/ed00 */
33		static void movx_b(tms34010_state tms, UINT16 op); / ec00/ed00 */
34		static void movy_a(tms34010_state tms, UINT16 op); / ee00/ef00 */
35		static void movy_b(tms34010_state tms, UINT16 op); / ee00/ef00 */
36		static void pixt_ri_a(tms34010_state tms, UINT16 op); / f800/f900 */
37		static void pixt_ri_b(tms34010_state tms, UINT16 op); / f800/f900 */
38		static void pixt_rixy_a(tms34010_state tms, UINT16 op); / f000/f100 */
39		static void pixt_rixy_b(tms34010_state tms, UINT16 op); / f000/f100 */
40		static void pixt_ir_a(tms34010_state tms, UINT16 op); / fa00/fb00 */
41		static void pixt_ir_b(tms34010_state tms, UINT16 op); / fa00/fb00 */
42		static void pixt_ii_a(tms34010_state tms, UINT16 op); / fc00/fd00 */
43		static void pixt_ii_b(tms34010_state tms, UINT16 op); / fc00/fd00 */
44		static void pixt_ixyr_a(tms34010_state tms, UINT16 op); / f200/f300 */
45		static void pixt_ixyr_b(tms34010_state tms, UINT16 op); / f200/f300 */
46		static void pixt_ixyixy_a(tms34010_state tms, UINT16 op); / f400/f500 */
47		static void pixt_ixyixy_b(tms34010_state tms, UINT16 op); / f400/f500 */
48		static void drav_a(tms34010_state tms, UINT16 op); / f600/f700 */
49		static void drav_b(tms34010_state tms, UINT16 op); / f600/f700 */
50
51		/* General Instructions */
52		static void abs_a(tms34010_state tms, UINT16 op); / 0380 */
53		static void abs_b(tms34010_state tms, UINT16 op); / 0390 */
54		static void add_a(tms34010_state tms, UINT16 op); / 4000/4100 */
55		static void add_b(tms34010_state tms, UINT16 op); / 4000/4100 */
56		static void addc_a(tms34010_state tms, UINT16 op); / 4200/4200 */
57		static void addc_b(tms34010_state tms, UINT16 op); / 4200/4200 */
58		static void addi_w_a(tms34010_state tms, UINT16 op); / 0b00 */
59		static void addi_w_b(tms34010_state tms, UINT16 op); / 0b10 */
60		static void addi_l_a(tms34010_state tms, UINT16 op); / 0b20 */
61		static void addi_l_b(tms34010_state tms, UINT16 op); / 0b30 */
62		static void addk_a(tms34010_state tms, UINT16 op); / 1000-1300 */
63		static void addk_b(tms34010_state tms, UINT16 op); / 1000-1300 */
64		static void and_a(tms34010_state tms, UINT16 op); / 5000/5100 */
65		static void and_b(tms34010_state tms, UINT16 op); / 5000/5100 */
66		static void andi_a(tms34010_state tms, UINT16 op); / 0b80 */
67		static void andi_b(tms34010_state tms, UINT16 op); / 0b90 */
68		static void andn_a(tms34010_state tms, UINT16 op); / 5200-5300 */
69		static void andn_b(tms34010_state tms, UINT16 op); / 5200-5300 */
70		static void btst_k_a(tms34010_state tms, UINT16 op); / 1c00-1f00 */
71		static void btst_k_b(tms34010_state tms, UINT16 op); / 1c00-1f00 */
72		static void btst_r_a(tms34010_state tms, UINT16 op); / 4a00-4b00 */
73		static void btst_r_b(tms34010_state tms, UINT16 op); / 4a00-4b00 */
74		static void clrc(tms34010_state tms, UINT16 op); / 0320 */
75		static void cmp_a(tms34010_state tms, UINT16 op); / 4800/4900 */
76		static void cmp_b(tms34010_state tms, UINT16 op); / 4800/4900 */
77		static void cmpi_w_a(tms34010_state tms, UINT16 op); / 0b40 */
78		static void cmpi_w_b(tms34010_state tms, UINT16 op); / 0b50 */
79		static void cmpi_l_a(tms34010_state tms, UINT16 op); / 0b60 */
80		static void cmpi_l_b(tms34010_state tms, UINT16 op); / 0b70 */
81		static void dint(tms34010_state *tms, UINT16 op);
82		static void divs_a(tms34010_state tms, UINT16 op); / 5800/5900 */
83		static void divs_b(tms34010_state tms, UINT16 op); / 5800/5900 */
84		static void divu_a(tms34010_state tms, UINT16 op); / 5a00/5b00 */
85		static void divu_b(tms34010_state tms, UINT16 op); / 5a00/5b00 */
86		static void eint(tms34010_state *tms, UINT16 op);
87		static void exgf0_a(tms34010_state tms, UINT16 op); / d500 */
88		static void exgf0_b(tms34010_state tms, UINT16 op); / d510 */
89		static void exgf1_a(tms34010_state tms, UINT16 op); / d700 */
90		static void exgf1_b(tms34010_state tms, UINT16 op); / d710 */
91		static void lmo_a(tms34010_state tms, UINT16 op); / 6a00/6b00 */
92		static void lmo_b(tms34010_state tms, UINT16 op); / 6a00/6b00 */
93		static void mmfm_a(tms34010_state tms, UINT16 op); / 09a0 */
94		static void mmfm_b(tms34010_state tms, UINT16 op); / 09b0 */
95		static void mmtm_a(tms34010_state tms, UINT16 op); / 0980 */
96		static void mmtm_b(tms34010_state tms, UINT16 op); / 0990 */
97		static void mods_a(tms34010_state tms, UINT16 op); / 6c00/6d00 */
98		static void mods_b(tms34010_state tms, UINT16 op); / 6c00/6d00 */
99		static void modu_a(tms34010_state tms, UINT16 op); / 6e00/6f00 */
100		static void modu_b(tms34010_state tms, UINT16 op); / 6e00/6f00 */
101		static void mpys_a(tms34010_state tms, UINT16 op); / 5c00/5d00 */
102		static void mpys_b(tms34010_state tms, UINT16 op); / 5c00/5d00 */
103		static void mpyu_a(tms34010_state tms, UINT16 op); / 5e00/5e00 */
104		static void mpyu_b(tms34010_state tms, UINT16 op); / 5e00/5f00 */
105		static void neg_a(tms34010_state tms, UINT16 op); / 03a0 */
106		static void neg_b(tms34010_state tms, UINT16 op); / 03b0 */
107		static void negb_a(tms34010_state tms, UINT16 op); / 03c0 */
108		static void negb_b(tms34010_state tms, UINT16 op); / 03d0 */
109		static void nop(tms34010_state tms, UINT16 op); / 0300 */
110		static void not_a(tms34010_state tms, UINT16 op); / 03e0 */
111		static void not_b(tms34010_state tms, UINT16 op); / 03f0 */
112		static void or_a(tms34010_state tms, UINT16 op); / 5400-5500 */
113		static void or_b(tms34010_state tms, UINT16 op); / 5400-5500 */
114		static void ori_a(tms34010_state tms, UINT16 op); / 0ba0 */
115		static void ori_b(tms34010_state tms, UINT16 op); / 0bb0 */
116		static void rl_k_a(tms34010_state tms, UINT16 op); / 3000-3300 */
117		static void rl_k_b(tms34010_state tms, UINT16 op); / 3000-3300 */
118		static void rl_r_a(tms34010_state tms, UINT16 op); / 6800/6900 */
119		static void rl_r_b(tms34010_state tms, UINT16 op); / 6800/6900 */
120		static void setc(tms34010_state tms, UINT16 op); / 0de0 */
121		static void setf0(tms34010_state *tms, UINT16 op);
122		static void setf1(tms34010_state *tms, UINT16 op);
123		static void sext0_a(tms34010_state tms, UINT16 op); / 0500 */
124		static void sext0_b(tms34010_state tms, UINT16 op); / 0510 */
125		static void sext1_a(tms34010_state tms, UINT16 op); / 0700 */
126		static void sext1_b(tms34010_state tms, UINT16 op); / 0710 */
127		static void sla_k_a(tms34010_state tms, UINT16 op); / 2000-2300 */
128		static void sla_k_b(tms34010_state tms, UINT16 op); / 2000-2300 */
129		static void sla_r_a(tms34010_state tms, UINT16 op); / 6000/6100 */
130		static void sla_r_b(tms34010_state tms, UINT16 op); / 6000/6100 */
131		static void sll_k_a(tms34010_state tms, UINT16 op); / 2400-2700 */
132		static void sll_k_b(tms34010_state tms, UINT16 op); / 2400-2700 */
133		static void sll_r_a(tms34010_state tms, UINT16 op); / 6200/6300 */
134		static void sll_r_b(tms34010_state tms, UINT16 op); / 6200/6300 */
135		static void sra_k_a(tms34010_state tms, UINT16 op); / 2800-2b00 */
136		static void sra_k_b(tms34010_state tms, UINT16 op); / 2800-2b00 */
137		static void sra_r_a(tms34010_state tms, UINT16 op); / 6400/6500 */
138		static void sra_r_b(tms34010_state tms, UINT16 op); / 6400/6500 */
139		static void srl_k_a(tms34010_state tms, UINT16 op); / 2c00-2f00 */
140		static void srl_k_b(tms34010_state tms, UINT16 op); / 2c00-2f00 */
141		static void srl_r_a(tms34010_state tms, UINT16 op); / 6600/6700 */
142		static void srl_r_b(tms34010_state tms, UINT16 op); / 6600/6700 */
143		static void sub_a(tms34010_state tms, UINT16 op); / 4400/4500 */
144		static void sub_b(tms34010_state tms, UINT16 op); / 4400/4500 */
145		static void subb_a(tms34010_state tms, UINT16 op); / 4600/4700 */
146		static void subb_b(tms34010_state tms, UINT16 op); / 4600/4700 */
147		static void subi_w_a(tms34010_state tms, UINT16 op); / 0be0 */
148		static void subi_w_b(tms34010_state tms, UINT16 op); / 0bf0 */
149		static void subi_l_a(tms34010_state tms, UINT16 op); / 0d00 */
150		static void subi_l_b(tms34010_state tms, UINT16 op); / 0d10 */
151		static void subk_a(tms34010_state tms, UINT16 op); / 1400-1700 */
152		static void subk_b(tms34010_state tms, UINT16 op); / 1400-1700 */
153		static void xor_a(tms34010_state tms, UINT16 op); / 5600-5700 */
154		static void xor_b(tms34010_state tms, UINT16 op); / 5600-5700 */
155		static void xori_a(tms34010_state tms, UINT16 op); / 0bc0 */
156		static void xori_b(tms34010_state tms, UINT16 op); / 0bd0 */
157		static void zext0_a(tms34010_state tms, UINT16 op); / 0520 */
158		static void zext0_b(tms34010_state tms, UINT16 op); / 0530 */
159		static void zext1_a(tms34010_state tms, UINT16 op); / 0720 */
160		static void zext1_b(tms34010_state tms, UINT16 op); / 0720 */
161
162
163		/* Move Instructions */
164		static void movi_w_a(tms34010_state *tms, UINT16 op);
165		static void movi_w_b(tms34010_state *tms, UINT16 op);
166		static void movi_l_a(tms34010_state *tms, UINT16 op);
167		static void movi_l_b(tms34010_state *tms, UINT16 op);
168		static void movk_a(tms34010_state *tms, UINT16 op);
169		static void movk_b(tms34010_state *tms, UINT16 op);
170		static void movb_rn_a(tms34010_state tms, UINT16 op); / 8c00-8d00 */
171		static void movb_rn_b(tms34010_state tms, UINT16 op); / 8c00-8d00 */
172		static void movb_nr_a(tms34010_state tms, UINT16 op); / 8e00-8f00 */
173		static void movb_nr_b(tms34010_state tms, UINT16 op); / 8e00-8f00 */
174		static void movb_nn_a(tms34010_state tms, UINT16 op); / 9c00-9d00 */
175		static void movb_nn_b(tms34010_state tms, UINT16 op); / 9c00-9d00 */
176		static void movb_r_no_a(tms34010_state tms, UINT16 op); / ac00-ad00 */
177		static void movb_r_no_b(tms34010_state tms, UINT16 op); / ac00-ad00 */
178		static void movb_no_r_a(tms34010_state tms, UINT16 op); / ae00-af00 */
179		static void movb_no_r_b(tms34010_state tms, UINT16 op); / ae00-af00 */
180		static void movb_no_no_a(tms34010_state tms, UINT16 op); / bc00-bd00 */
181		static void movb_no_no_b(tms34010_state tms, UINT16 op); / bc00-bd00 */
182		static void movb_ra_a(tms34010_state *tms, UINT16 op);
183		static void movb_ra_b(tms34010_state *tms, UINT16 op);
184		static void movb_ar_a(tms34010_state *tms, UINT16 op);
185		static void movb_ar_b(tms34010_state *tms, UINT16 op);
186		static void movb_aa(tms34010_state *tms, UINT16 op);
187		static void move_rr_a(tms34010_state tms, UINT16 op); / 4c00/d00 */
188		static void move_rr_b(tms34010_state tms, UINT16 op); / 4c00/d00 */
189		static void move_rr_ax(tms34010_state tms, UINT16 op); / 4e00/f00 */
190		static void move_rr_bx(tms34010_state tms, UINT16 op); / 4e00/f00 */
191		static void move0_rn_a(tms34010_state tms, UINT16 op); / 8000 */
192		static void move0_rn_b(tms34010_state *tms, UINT16 op);
193		static void move1_rn_a(tms34010_state *tms, UINT16 op);
194		static void move1_rn_b(tms34010_state *tms, UINT16 op);
195		static void move0_r_dn_a(tms34010_state tms, UINT16 op); / a000 */
196		static void move0_r_dn_b(tms34010_state *tms, UINT16 op);
197		static void move1_r_dn_a(tms34010_state *tms, UINT16 op);
198		static void move1_r_dn_b(tms34010_state *tms, UINT16 op);
199		static void move0_r_ni_a(tms34010_state tms, UINT16 op); / 9000 */
200		static void move0_r_ni_b(tms34010_state *tms, UINT16 op);
201		static void move1_r_ni_a(tms34010_state *tms, UINT16 op);
202		static void move1_r_ni_b(tms34010_state *tms, UINT16 op);
203		static void move0_nr_a(tms34010_state tms, UINT16 op); / 8400-500 */
204		static void move0_nr_b(tms34010_state tms, UINT16 op); / 8400-500 */
205		static void move1_nr_a(tms34010_state tms, UINT16 op); / 8600-700 */
206		static void move1_nr_b(tms34010_state tms, UINT16 op); / 8600-700 */
207		static void move0_dn_r_a(tms34010_state tms, UINT16 op); / A400-500 */
208		static void move0_dn_r_b(tms34010_state tms, UINT16 op); / A400-500 */
209		static void move1_dn_r_a(tms34010_state tms, UINT16 op); / A600-700 */
210		static void move1_dn_r_b(tms34010_state tms, UINT16 op); / A600-700 */
211		static void move0_ni_r_a(tms34010_state tms, UINT16 op); / 9400-500 */
212		static void move0_ni_r_b(tms34010_state tms, UINT16 op); / 9400-500 */
213		static void move1_ni_r_a(tms34010_state tms, UINT16 op); / 9600-700 */
214		static void move1_ni_r_b(tms34010_state tms, UINT16 op); / 9600-700 */
215		static void move0_nn_a(tms34010_state tms, UINT16 op); / 8800 */
216		static void move0_nn_b(tms34010_state *tms, UINT16 op);
217		static void move1_nn_a(tms34010_state *tms, UINT16 op);
218		static void move1_nn_b(tms34010_state *tms, UINT16 op);
219		static void move0_dn_dn_a(tms34010_state tms, UINT16 op); / a800 */
220		static void move0_dn_dn_b(tms34010_state *tms, UINT16 op);
221		static void move1_dn_dn_a(tms34010_state *tms, UINT16 op);
222		static void move1_dn_dn_b(tms34010_state *tms, UINT16 op);
223		static void move0_ni_ni_a(tms34010_state tms, UINT16 op); / 9800 */
224		static void move0_ni_ni_b(tms34010_state *tms, UINT16 op);
225		static void move1_ni_ni_a(tms34010_state *tms, UINT16 op);
226		static void move1_ni_ni_b(tms34010_state *tms, UINT16 op);
227		static void move0_r_no_a(tms34010_state tms, UINT16 op); / b000 */
228		static void move0_r_no_b(tms34010_state *tms, UINT16 op);
229		static void move1_r_no_a(tms34010_state *tms, UINT16 op);
230		static void move1_r_no_b(tms34010_state *tms, UINT16 op);
231		static void move0_no_r_a(tms34010_state tms, UINT16 op); / b400 */
232		static void move0_no_r_b(tms34010_state *tms, UINT16 op);
233		static void move1_no_r_a(tms34010_state *tms, UINT16 op);
234		static void move1_no_r_b(tms34010_state *tms, UINT16 op);
235		static void move0_no_ni_a(tms34010_state tms, UINT16 op); / d000 */
236		static void move0_no_ni_b(tms34010_state *tms, UINT16 op);
237		static void move1_no_ni_a(tms34010_state *tms, UINT16 op);
238		static void move1_no_ni_b(tms34010_state *tms, UINT16 op);
239		static void move0_no_no_a(tms34010_state tms, UINT16 op); / b800 */
240		static void move0_no_no_b(tms34010_state *tms, UINT16 op);
241		static void move1_no_no_a(tms34010_state *tms, UINT16 op);
242		static void move1_no_no_b(tms34010_state *tms, UINT16 op);
243		static void move0_ra_a(tms34010_state *tms, UINT16 op);
244		static void move0_ra_b(tms34010_state *tms, UINT16 op);
245		static void move1_ra_a(tms34010_state *tms, UINT16 op);
246		static void move1_ra_b(tms34010_state *tms, UINT16 op);
247		static void move0_ar_a(tms34010_state *tms, UINT16 op);
248		static void move0_ar_b(tms34010_state *tms, UINT16 op);
249		static void move1_ar_a(tms34010_state *tms, UINT16 op);
250		static void move1_ar_b(tms34010_state *tms, UINT16 op);
251		static void move0_a_ni_a(tms34010_state tms, UINT16 op); / d400 */
252		static void move0_a_ni_b(tms34010_state tms, UINT16 op); / d410 */
253		static void move1_a_ni_a(tms34010_state tms, UINT16 op); / d600 */
254		static void move1_a_ni_b(tms34010_state tms, UINT16 op); / d610 */
255		static void move0_aa(tms34010_state tms, UINT16 op); / 05c0 */
256		static void move1_aa(tms34010_state tms, UINT16 op); / 07c0 */
257
258
259		/* Program Control and Context Switching */
260		static void call_a(tms34010_state tms, UINT16 op); / 0920 */
261		static void call_b(tms34010_state tms, UINT16 op); / 0930 */
262		static void callr(tms34010_state tms, UINT16 op); / 0d3f */
263		static void calla(tms34010_state tms, UINT16 op); / 0d5f */
264		static void dsj_a(tms34010_state tms, UINT16 op); / 0d80 */
265		static void dsj_b(tms34010_state tms, UINT16 op); / 0d90 */
266		static void dsjeq_a(tms34010_state tms, UINT16 op); / 0da0 */
267		static void dsjeq_b(tms34010_state tms, UINT16 op); / 0db0 */
268		static void dsjne_a(tms34010_state tms, UINT16 op); / 0dc0 */
269		static void dsjne_b(tms34010_state tms, UINT16 op); / 0dd0 */
270		static void dsjs_a(tms34010_state *tms, UINT16 op);
271		static void dsjs_b(tms34010_state *tms, UINT16 op);
272		static void emu(tms34010_state tms, UINT16 op); / 0100 */
273		static void exgpc_a(tms34010_state tms, UINT16 op); / 0120 */
274		static void exgpc_b(tms34010_state tms, UINT16 op); / 0130 */
275		static void getpc_a(tms34010_state tms, UINT16 op); / 0140 */
276		static void getpc_b(tms34010_state tms, UINT16 op); / 0150 */
277		static void getst_a(tms34010_state tms, UINT16 op); / 0180 */
278		static void getst_b(tms34010_state tms, UINT16 op); / 0190 */
279		static void j_UC_0(tms34010_state *tms, UINT16 op);
280		static void j_UC_8(tms34010_state *tms, UINT16 op);
281		static void j_UC_x(tms34010_state *tms, UINT16 op);
282		static void j_P_0(tms34010_state *tms, UINT16 op);
283		static void j_P_8(tms34010_state *tms, UINT16 op);
284		static void j_P_x(tms34010_state *tms, UINT16 op);
285		static void j_LS_0(tms34010_state *tms, UINT16 op);
286		static void j_LS_8(tms34010_state *tms, UINT16 op);
287		static void j_LS_x(tms34010_state *tms, UINT16 op);
288		static void j_HI_0(tms34010_state *tms, UINT16 op);
289		static void j_HI_8(tms34010_state *tms, UINT16 op);
290		static void j_HI_x(tms34010_state *tms, UINT16 op);
291		static void j_LT_0(tms34010_state *tms, UINT16 op);
292		static void j_LT_8(tms34010_state *tms, UINT16 op);
293		static void j_LT_x(tms34010_state *tms, UINT16 op);
294		static void j_GE_0(tms34010_state *tms, UINT16 op);
295		static void j_GE_8(tms34010_state *tms, UINT16 op);
296		static void j_GE_x(tms34010_state *tms, UINT16 op);
297		static void j_LE_0(tms34010_state *tms, UINT16 op);
298		static void j_LE_8(tms34010_state *tms, UINT16 op);
299		static void j_LE_x(tms34010_state *tms, UINT16 op);
300		static void j_GT_0(tms34010_state *tms, UINT16 op);
301		static void j_GT_8(tms34010_state *tms, UINT16 op);
302		static void j_GT_x(tms34010_state *tms, UINT16 op);
303		static void j_C_0(tms34010_state *tms, UINT16 op);
304		static void j_C_8(tms34010_state *tms, UINT16 op);
305		static void j_C_x(tms34010_state *tms, UINT16 op);
306		static void j_NC_0(tms34010_state *tms, UINT16 op);
307		static void j_NC_8(tms34010_state *tms, UINT16 op);
308		static void j_NC_x(tms34010_state *tms, UINT16 op);
309		static void j_EQ_0(tms34010_state *tms, UINT16 op);
310		static void j_EQ_8(tms34010_state *tms, UINT16 op);
311		static void j_EQ_x(tms34010_state *tms, UINT16 op);
312		static void j_NE_0(tms34010_state *tms, UINT16 op);
313		static void j_NE_8(tms34010_state *tms, UINT16 op);
314		static void j_NE_x(tms34010_state *tms, UINT16 op);
315		static void j_V_0(tms34010_state *tms, UINT16 op);
316		static void j_V_8(tms34010_state *tms, UINT16 op);
317		static void j_V_x(tms34010_state *tms, UINT16 op);
318		static void j_NV_0(tms34010_state *tms, UINT16 op);
319		static void j_NV_8(tms34010_state *tms, UINT16 op);
320		static void j_NV_x(tms34010_state *tms, UINT16 op);
321		static void j_N_0(tms34010_state *tms, UINT16 op);
322		static void j_N_8(tms34010_state *tms, UINT16 op);
323		static void j_N_x(tms34010_state *tms, UINT16 op);
324		static void j_NN_0(tms34010_state *tms, UINT16 op);
325		static void j_NN_8(tms34010_state *tms, UINT16 op);
326		static void j_NN_x(tms34010_state *tms, UINT16 op);
327		static void jump_a(tms34010_state tms, UINT16 op); / 0160 */
328		static void jump_b(tms34010_state tms, UINT16 op); / 0170 */
329		static void popst(tms34010_state tms, UINT16 op); / 01c0 */
330		static void pushst(tms34010_state tms, UINT16 op); / 01e0 */
331		static void putst_a(tms34010_state tms, UINT16 op); / 01a0 */
332		static void putst_b(tms34010_state tms, UINT16 op); / 01b0 */
333		static void reti(tms34010_state tms, UINT16 op); / 0940 */
334		static void rets(tms34010_state tms, UINT16 op); / 0960/70 */
335		static void rev_a(tms34010_state tms, UINT16 op); / 0020 */
336		static void rev_b(tms34010_state tms, UINT16 op); / 0030 */
337		static void trap(tms34010_state tms, UINT16 op); / 0900/10 */
338
339
340		/* 34020 instructions */
341		static void addxyi_a(tms34010_state *tms, UINT16 op);
342		static void addxyi_b(tms34010_state *tms, UINT16 op);
343		static void blmove(tms34010_state *tms, UINT16 op);
344		static void cexec_l(tms34010_state *tms, UINT16 op);
345		static void cexec_s(tms34010_state *tms, UINT16 op);
346		static void clip(tms34010_state *tms, UINT16 op);
347		static void cmovcg_a(tms34010_state *tms, UINT16 op);
348		static void cmovcg_b(tms34010_state *tms, UINT16 op);
349		static void cmovcm_f(tms34010_state *tms, UINT16 op);
350		static void cmovcm_b(tms34010_state *tms, UINT16 op);
351		static void cmovgc_a(tms34010_state *tms, UINT16 op);
352		static void cmovgc_b(tms34010_state *tms, UINT16 op);
353		static void cmovgc_a_s(tms34010_state *tms, UINT16 op);
354		static void cmovgc_b_s(tms34010_state *tms, UINT16 op);
355		static void cmovmc_f(tms34010_state *tms, UINT16 op);
356		static void cmovmc_f_va(tms34010_state *tms, UINT16 op);
357		static void cmovmc_f_vb(tms34010_state *tms, UINT16 op);
358		static void cmovmc_b(tms34010_state *tms, UINT16 op);
359		static void cmp_k_a(tms34010_state *tms, UINT16 op);
360		static void cmp_k_b(tms34010_state *tms, UINT16 op);
361		static void cvdxyl_a(tms34010_state *tms, UINT16 op);
362		static void cvdxyl_b(tms34010_state *tms, UINT16 op);
363		static void cvmxyl_a(tms34010_state *tms, UINT16 op);
364		static void cvmxyl_b(tms34010_state *tms, UINT16 op);
365		static void cvsxyl_a(tms34010_state *tms, UINT16 op);
366		static void cvsxyl_b(tms34010_state *tms, UINT16 op);
367		static void exgps_a(tms34010_state *tms, UINT16 op);
368		static void exgps_b(tms34010_state *tms, UINT16 op);
369		static void fline(tms34010_state *tms, UINT16 op);
370		static void fpixeq(tms34010_state *tms, UINT16 op);
371		static void fpixne(tms34010_state *tms, UINT16 op);
372		static void getps_a(tms34010_state *tms, UINT16 op);
373		static void getps_b(tms34010_state *tms, UINT16 op);
374		static void idle(tms34010_state *tms, UINT16 op);
375		static void linit(tms34010_state *tms, UINT16 op);
376		static void mwait(tms34010_state *tms, UINT16 op);
377		static void pfill_xy(tms34010_state *tms, UINT16 op);
378		static void pixblt_l_m_l(tms34010_state *tms, UINT16 op);
379		static void retm(tms34010_state *tms, UINT16 op);
380		static void rmo_a(tms34010_state *tms, UINT16 op);
381		static void rmo_b(tms34010_state *tms, UINT16 op);
382		static void rpix_a(tms34010_state *tms, UINT16 op);
383		static void rpix_b(tms34010_state *tms, UINT16 op);
384		static void setcdp(tms34010_state *tms, UINT16 op);
385		static void setcmp(tms34010_state *tms, UINT16 op);
386		static void setcsp(tms34010_state *tms, UINT16 op);
387		static void swapf_a(tms34010_state *tms, UINT16 op);
388		static void swapf_b(tms34010_state *tms, UINT16 op);
389		static void tfill_xy(tms34010_state *tms, UINT16 op);
390		static void trapl(tms34010_state *tms, UINT16 op);
391		static void vblt_b_l(tms34010_state *tms, UINT16 op);
392		static void vfill_l(tms34010_state *tms, UINT16 op);
393		static void vlcol(tms34010_state *tms, UINT16 op);
394
395
396	9	/* Opcode Table */
397		static void (const opcode_table[65536 >> 4]~~)(tms34010_state tms, UINT16 op)~~ =
	10	const tms340x0_device::opcode_func tms340x0_device::s_opcode_table[65536 >> 4] =
398	11	{
399	12	/* 0x0000 0x0010 0x0020 0x0030 ... 0x00f0 */
400		unimpl, unimpl, rev_a, rev_b, idle, unimpl, unimpl, unimpl,
401		mwait, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, blmove,
	13	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::rev_a, &tms340x0_device::rev_b, &tms340x0_device::idle, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	14	&tms340x0_device::mwait, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::blmove,
402	15	/* 0x0100 */
403		emu, unimpl, exgpc_a, exgpc_b, getpc_a, getpc_b, jump_a, jump_b,
404		getst_a, getst_b, putst_a, putst_b, popst, unimpl, pushst, unimpl,
	16	&tms340x0_device::emu, &tms340x0_device::unimpl, &tms340x0_device::exgpc_a, &tms340x0_device::exgpc_b, &tms340x0_device::getpc_a, &tms340x0_device::getpc_b, &tms340x0_device::jump_a, &tms340x0_device::jump_b,
	17	&tms340x0_device::getst_a, &tms340x0_device::getst_b, &tms340x0_device::putst_a, &tms340x0_device::putst_b, &tms340x0_device::popst, &tms340x0_device::unimpl, &tms340x0_device::pushst, &tms340x0_device::unimpl,
405	18	/* 0x0200 */
406		unimpl, unimpl, unimpl, unimpl, unimpl, setcsp, unimpl, setcdp,
407		rpix_a, rpix_b, exgps_a, exgps_b, getps_a, getps_b, unimpl, setcmp,
	19	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::setcsp, &tms340x0_device::unimpl, &tms340x0_device::setcdp,
	20	&tms340x0_device::rpix_a, &tms340x0_device::rpix_b, &tms340x0_device::exgps_a, &tms340x0_device::exgps_b, &tms340x0_device::getps_a, &tms340x0_device::getps_b, &tms340x0_device::unimpl, &tms340x0_device::setcmp,
408	21	/* 0x0300 */
409		nop, unimpl, clrc, unimpl, movb_aa, unimpl, dint, unimpl,
410		abs_a, abs_b, neg_a, neg_b, negb_a, negb_b, not_a, not_b,
	22	&tms340x0_device::nop, &tms340x0_device::unimpl, &tms340x0_device::clrc, &tms340x0_device::unimpl, &tms340x0_device::movb_aa, &tms340x0_device::unimpl, &tms340x0_device::dint, &tms340x0_device::unimpl,
	23	&tms340x0_device::abs_a, &tms340x0_device::abs_b, &tms340x0_device::neg_a, &tms340x0_device::neg_b, &tms340x0_device::negb_a, &tms340x0_device::negb_b, &tms340x0_device::not_a, &tms340x0_device::not_b,
411	24	/* 0x0400 */
412		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
413		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	25	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	26	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
414	27	/* 0x0500 */
415		sext0_a, sext0_b, zext0_a, zext0_b, setf0, setf0, setf0, setf0,
416		move0_ra_a, move0_ra_b, move0_ar_a, move0_ar_b, move0_aa, unimpl, movb_ra_a, movb_ra_b,
	28	&tms340x0_device::sext0_a, &tms340x0_device::sext0_b, &tms340x0_device::zext0_a, &tms340x0_device::zext0_b, &tms340x0_device::setf0, &tms340x0_device::setf0, &tms340x0_device::setf0, &tms340x0_device::setf0,
	29	&tms340x0_device::move0_ra_a, &tms340x0_device::move0_ra_b, &tms340x0_device::move0_ar_a, &tms340x0_device::move0_ar_b, &tms340x0_device::move0_aa, &tms340x0_device::unimpl, &tms340x0_device::movb_ra_a, &tms340x0_device::movb_ra_b,
417	30	/* 0x0600 */
418		cexec_l, unimpl, cmovgc_a, cmovgc_b, cmovgc_a_s, cmovgc_b_s, cmovcg_a, cmovcg_b,
419		cmovmc_f, cmovmc_f, cmovcm_f, cmovcm_f, cmovcm_b, cmovcm_b, cmovmc_f_va,cmovmc_f_vb,
	31	&tms340x0_device::cexec_l, &tms340x0_device::unimpl, &tms340x0_device::cmovgc_a, &tms340x0_device::cmovgc_b, &tms340x0_device::cmovgc_a_s, &tms340x0_device::cmovgc_b_s, &tms340x0_device::cmovcg_a, &tms340x0_device::cmovcg_b,
	32	&tms340x0_device::cmovmc_f, &tms340x0_device::cmovmc_f, &tms340x0_device::cmovcm_f, &tms340x0_device::cmovcm_f, &tms340x0_device::cmovcm_b, &tms340x0_device::cmovcm_b, &tms340x0_device::cmovmc_f_va,&tms340x0_device::cmovmc_f_vb,
420	33	/* 0x0700 */
421		sext1_a, sext1_b, zext1_a, zext1_b, setf1, setf1, setf1, setf1,
422		move1_ra_a, move1_ra_b, move1_ar_a, move1_ar_b, move1_aa, unimpl, movb_ar_a, movb_ar_b,
	34	&tms340x0_device::sext1_a, &tms340x0_device::sext1_b, &tms340x0_device::zext1_a, &tms340x0_device::zext1_b, &tms340x0_device::setf1, &tms340x0_device::setf1, &tms340x0_device::setf1, &tms340x0_device::setf1,
	35	&tms340x0_device::move1_ra_a, &tms340x0_device::move1_ra_b, &tms340x0_device::move1_ar_a, &tms340x0_device::move1_ar_b, &tms340x0_device::move1_aa, &tms340x0_device::unimpl, &tms340x0_device::movb_ar_a, &tms340x0_device::movb_ar_b,
423	36	/* 0x0800 */
424		trapl, unimpl, cmovmc_b, cmovmc_b, unimpl, vblt_b_l, retm, unimpl,
425		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, clip,
	37	&tms340x0_device::trapl, &tms340x0_device::unimpl, &tms340x0_device::cmovmc_b, &tms340x0_device::cmovmc_b, &tms340x0_device::unimpl, &tms340x0_device::vblt_b_l, &tms340x0_device::retm, &tms340x0_device::unimpl,
	38	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::clip,
426	39	/* 0x0900 */
427		trap, trap, call_a, call_b, reti, unimpl, rets, rets,
428		mmtm_a, mmtm_b, mmfm_a, mmfm_b, movi_w_a, movi_w_b, movi_l_a, movi_l_b,
	40	&tms340x0_device::trap, &tms340x0_device::trap, &tms340x0_device::call_a, &tms340x0_device::call_b, &tms340x0_device::reti, &tms340x0_device::unimpl, &tms340x0_device::rets, &tms340x0_device::rets,
	41	&tms340x0_device::mmtm_a, &tms340x0_device::mmtm_b, &tms340x0_device::mmfm_a, &tms340x0_device::mmfm_b, &tms340x0_device::movi_w_a, &tms340x0_device::movi_w_b, &tms340x0_device::movi_l_a, &tms340x0_device::movi_l_b,
429	42	/* 0x0a00 */
430		vlcol, unimpl, unimpl, pfill_xy, unimpl, vfill_l, cvmxyl_a, cvmxyl_b,
431		cvdxyl_a, cvdxyl_b, unimpl, fpixeq, unimpl, fpixne, unimpl, unimpl,
	43	&tms340x0_device::vlcol, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::pfill_xy, &tms340x0_device::unimpl, &tms340x0_device::vfill_l, &tms340x0_device::cvmxyl_a, &tms340x0_device::cvmxyl_b,
	44	&tms340x0_device::cvdxyl_a, &tms340x0_device::cvdxyl_b, &tms340x0_device::unimpl, &tms340x0_device::fpixeq, &tms340x0_device::unimpl, &tms340x0_device::fpixne, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
432	45	/* 0x0b00 */
433		addi_w_a, addi_w_b, addi_l_a, addi_l_b, cmpi_w_a, cmpi_w_b, cmpi_l_a, cmpi_l_b,
434		andi_a, andi_b, ori_a, ori_b, xori_a, xori_b, subi_w_a, subi_w_b,
	46	&tms340x0_device::addi_w_a, &tms340x0_device::addi_w_b, &tms340x0_device::addi_l_a, &tms340x0_device::addi_l_b, &tms340x0_device::cmpi_w_a, &tms340x0_device::cmpi_w_b, &tms340x0_device::cmpi_l_a, &tms340x0_device::cmpi_l_b,
	47	&tms340x0_device::andi_a, &tms340x0_device::andi_b, &tms340x0_device::ori_a, &tms340x0_device::ori_b, &tms340x0_device::xori_a, &tms340x0_device::xori_b, &tms340x0_device::subi_w_a, &tms340x0_device::subi_w_b,
435	48	/* 0x0c00 */
436		addxyi_a, addxyi_b, unimpl, unimpl, unimpl, linit, unimpl, unimpl,
437		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	49	&tms340x0_device::addxyi_a, &tms340x0_device::addxyi_b, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::linit, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	50	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
438	51	/* 0x0d00 */
439		subi_l_a, subi_l_b, unimpl, callr, unimpl, calla, eint, unimpl,
440		dsj_a, dsj_b, dsjeq_a, dsjeq_b, dsjne_a, dsjne_b, setc, unimpl,
	52	&tms340x0_device::subi_l_a, &tms340x0_device::subi_l_b, &tms340x0_device::unimpl, &tms340x0_device::callr, &tms340x0_device::unimpl, &tms340x0_device::calla, &tms340x0_device::eint, &tms340x0_device::unimpl,
	53	&tms340x0_device::dsj_a, &tms340x0_device::dsj_b, &tms340x0_device::dsjeq_a, &tms340x0_device::dsjeq_b, &tms340x0_device::dsjne_a, &tms340x0_device::dsjne_b, &tms340x0_device::setc, &tms340x0_device::unimpl,
441	54	/* 0x0e00 */
442		unimpl, pixblt_l_m_l,unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
443		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, tfill_xy,
	55	&tms340x0_device::unimpl, &tms340x0_device::pixblt_l_m_l,&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	56	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::tfill_xy,
444	57	/* 0x0f00 */
445		pixblt_l_l, unimpl, pixblt_l_xy,unimpl, pixblt_xy_l,unimpl, pixblt_xy_xy,unimpl,
446		pixblt_b_l, unimpl, pixblt_b_xy,unimpl, fill_l, unimpl, fill_xy, unimpl,
	58	&tms340x0_device::pixblt_l_l, &tms340x0_device::unimpl, &tms340x0_device::pixblt_l_xy,&tms340x0_device::unimpl, &tms340x0_device::pixblt_xy_l,&tms340x0_device::unimpl, &tms340x0_device::pixblt_xy_xy,&tms340x0_device::unimpl,
	59	&tms340x0_device::pixblt_b_l, &tms340x0_device::unimpl, &tms340x0_device::pixblt_b_xy,&tms340x0_device::unimpl, &tms340x0_device::fill_l, &tms340x0_device::unimpl, &tms340x0_device::fill_xy, &tms340x0_device::unimpl,
447	60	/* 0x1000 */
448		addk_a, addk_b, addk_a, addk_b, addk_a, addk_b, addk_a, addk_b,
449		addk_a, addk_b, addk_a, addk_b, addk_a, addk_b, addk_a, addk_b,
	61	&tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b,
	62	&tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b,
450	63	/* 0x1100 */
451		addk_a, addk_b, addk_a, addk_b, addk_a, addk_b, addk_a, addk_b,
452		addk_a, addk_b, addk_a, addk_b, addk_a, addk_b, addk_a, addk_b,
	64	&tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b,
	65	&tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b,
453	66	/* 0x1200 */
454		addk_a, addk_b, addk_a, addk_b, addk_a, addk_b, addk_a, addk_b,
455		addk_a, addk_b, addk_a, addk_b, addk_a, addk_b, addk_a, addk_b,
	67	&tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b,
	68	&tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b,
456	69	/* 0x1300 */
457		addk_a, addk_b, addk_a, addk_b, addk_a, addk_b, addk_a, addk_b,
458		addk_a, addk_b, addk_a, addk_b, addk_a, addk_b, addk_a, addk_b,
	70	&tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b,
	71	&tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b,
459	72	/* 0x1400 */
460		subk_a, subk_b, subk_a, subk_b, subk_a, subk_b, subk_a, subk_b,
461		subk_a, subk_b, subk_a, subk_b, subk_a, subk_b, subk_a, subk_b,
	73	&tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b,
	74	&tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b,
462	75	/* 0x1500 */
463		subk_a, subk_b, subk_a, subk_b, subk_a, subk_b, subk_a, subk_b,
464		subk_a, subk_b, subk_a, subk_b, subk_a, subk_b, subk_a, subk_b,
	76	&tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b,
	77	&tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b,
465	78	/* 0x1600 */
466		subk_a, subk_b, subk_a, subk_b, subk_a, subk_b, subk_a, subk_b,
467		subk_a, subk_b, subk_a, subk_b, subk_a, subk_b, subk_a, subk_b,
	79	&tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b,
	80	&tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b,
468	81	/* 0x1700 */
469		subk_a, subk_b, subk_a, subk_b, subk_a, subk_b, subk_a, subk_b,
470		subk_a, subk_b, subk_a, subk_b, subk_a, subk_b, subk_a, subk_b,
	82	&tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b,
	83	&tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b,
471	84	/* 0x1800 */
472		movk_a, movk_b, movk_a, movk_b, movk_a, movk_b, movk_a, movk_b,
473		movk_a, movk_b, movk_a, movk_b, movk_a, movk_b, movk_a, movk_b,
	85	&tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b,
	86	&tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b,
474	87	/* 0x1900 */
475		movk_a, movk_b, movk_a, movk_b, movk_a, movk_b, movk_a, movk_b,
476		movk_a, movk_b, movk_a, movk_b, movk_a, movk_b, movk_a, movk_b,
	88	&tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b,
	89	&tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b,
477	90	/* 0x1a00 */
478		movk_a, movk_b, movk_a, movk_b, movk_a, movk_b, movk_a, movk_b,
479		movk_a, movk_b, movk_a, movk_b, movk_a, movk_b, movk_a, movk_b,
	91	&tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b,
	92	&tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b,
480	93	/* 0x1b00 */
481		movk_a, movk_b, movk_a, movk_b, movk_a, movk_b, movk_a, movk_b,
482		movk_a, movk_b, movk_a, movk_b, movk_a, movk_b, movk_a, movk_b,
	94	&tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b,
	95	&tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b,
483	96	/* 0x1c00 */
484		btst_k_a, btst_k_b, btst_k_a, btst_k_b, btst_k_a, btst_k_b, btst_k_a, btst_k_b,
485		btst_k_a, btst_k_b, btst_k_a, btst_k_b, btst_k_a, btst_k_b, btst_k_a, btst_k_b,
	97	&tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b,
	98	&tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b,
486	99	/* 0x1d00 */
487		btst_k_a, btst_k_b, btst_k_a, btst_k_b, btst_k_a, btst_k_b, btst_k_a, btst_k_b,
488		btst_k_a, btst_k_b, btst_k_a, btst_k_b, btst_k_a, btst_k_b, btst_k_a, btst_k_b,
	100	&tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b,
	101	&tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b,
489	102	/* 0x1e00 */
490		btst_k_a, btst_k_b, btst_k_a, btst_k_b, btst_k_a, btst_k_b, btst_k_a, btst_k_b,
491		btst_k_a, btst_k_b, btst_k_a, btst_k_b, btst_k_a, btst_k_b, btst_k_a, btst_k_b,
	103	&tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b,
	104	&tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b,
492	105	/* 0x1f00 */
493		btst_k_a, btst_k_b, btst_k_a, btst_k_b, btst_k_a, btst_k_b, btst_k_a, btst_k_b,
494		btst_k_a, btst_k_b, btst_k_a, btst_k_b, btst_k_a, btst_k_b, btst_k_a, btst_k_b,
	106	&tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b,
	107	&tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b,
495	108	/* 0x2000 */
496		sla_k_a, sla_k_b, sla_k_a, sla_k_b, sla_k_a, sla_k_b, sla_k_a, sla_k_b,
497		sla_k_a, sla_k_b, sla_k_a, sla_k_b, sla_k_a, sla_k_b, sla_k_a, sla_k_b,
	109	&tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b,
	110	&tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b,
498	111	/* 0x2100 */
499		sla_k_a, sla_k_b, sla_k_a, sla_k_b, sla_k_a, sla_k_b, sla_k_a, sla_k_b,
500		sla_k_a, sla_k_b, sla_k_a, sla_k_b, sla_k_a, sla_k_b, sla_k_a, sla_k_b,
	112	&tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b,
	113	&tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b,
501	114	/* 0x2200 */
502		sla_k_a, sla_k_b, sla_k_a, sla_k_b, sla_k_a, sla_k_b, sla_k_a, sla_k_b,
503		sla_k_a, sla_k_b, sla_k_a, sla_k_b, sla_k_a, sla_k_b, sla_k_a, sla_k_b,
	115	&tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b,
	116	&tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b,
504	117	/* 0x2300 */
505		sla_k_a, sla_k_b, sla_k_a, sla_k_b, sla_k_a, sla_k_b, sla_k_a, sla_k_b,
506		sla_k_a, sla_k_b, sla_k_a, sla_k_b, sla_k_a, sla_k_b, sla_k_a, sla_k_b,
	118	&tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b,
	119	&tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b,
507	120	/* 0x2400 */
508		sll_k_a, sll_k_b, sll_k_a, sll_k_b, sll_k_a, sll_k_b, sll_k_a, sll_k_b,
509		sll_k_a, sll_k_b, sll_k_a, sll_k_b, sll_k_a, sll_k_b, sll_k_a, sll_k_b,
	121	&tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b,
	122	&tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b,
510	123	/* 0x2500 */
511		sll_k_a, sll_k_b, sll_k_a, sll_k_b, sll_k_a, sll_k_b, sll_k_a, sll_k_b,
512		sll_k_a, sll_k_b, sll_k_a, sll_k_b, sll_k_a, sll_k_b, sll_k_a, sll_k_b,
	124	&tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b,
	125	&tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b,
513	126	/* 0x2600 */
514		sll_k_a, sll_k_b, sll_k_a, sll_k_b, sll_k_a, sll_k_b, sll_k_a, sll_k_b,
515		sll_k_a, sll_k_b, sll_k_a, sll_k_b, sll_k_a, sll_k_b, sll_k_a, sll_k_b,
	127	&tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b,
	128	&tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b,
516	129	/* 0x2700 */
517		sll_k_a, sll_k_b, sll_k_a, sll_k_b, sll_k_a, sll_k_b, sll_k_a, sll_k_b,
518		sll_k_a, sll_k_b, sll_k_a, sll_k_b, sll_k_a, sll_k_b, sll_k_a, sll_k_b,
	130	&tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b,
	131	&tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b,
519	132	/* 0x2800 */
520		sra_k_a, sra_k_b, sra_k_a, sra_k_b, sra_k_a, sra_k_b, sra_k_a, sra_k_b,
521		sra_k_a, sra_k_b, sra_k_a, sra_k_b, sra_k_a, sra_k_b, sra_k_a, sra_k_b,
	133	&tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b,
	134	&tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b,
522	135	/* 0x2900 */
523		sra_k_a, sra_k_b, sra_k_a, sra_k_b, sra_k_a, sra_k_b, sra_k_a, sra_k_b,
524		sra_k_a, sra_k_b, sra_k_a, sra_k_b, sra_k_a, sra_k_b, sra_k_a, sra_k_b,
	136	&tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b,
	137	&tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b,
525	138	/* 0x2a00 */
526		sra_k_a, sra_k_b, sra_k_a, sra_k_b, sra_k_a, sra_k_b, sra_k_a, sra_k_b,
527		sra_k_a, sra_k_b, sra_k_a, sra_k_b, sra_k_a, sra_k_b, sra_k_a, sra_k_b,
	139	&tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b,
	140	&tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b,
528	141	/* 0x2b00 */
529		sra_k_a, sra_k_b, sra_k_a, sra_k_b, sra_k_a, sra_k_b, sra_k_a, sra_k_b,
530		sra_k_a, sra_k_b, sra_k_a, sra_k_b, sra_k_a, sra_k_b, sra_k_a, sra_k_b,
	142	&tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b,
	143	&tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b,
531	144	/* 0x2c00 */
532		srl_k_a, srl_k_b, srl_k_a, srl_k_b, srl_k_a, srl_k_b, srl_k_a, srl_k_b,
533		srl_k_a, srl_k_b, srl_k_a, srl_k_b, srl_k_a, srl_k_b, srl_k_a, srl_k_b,
	145	&tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b,
	146	&tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b,
534	147	/* 0x2d00 */
535		srl_k_a, srl_k_b, srl_k_a, srl_k_b, srl_k_a, srl_k_b, srl_k_a, srl_k_b,
536		srl_k_a, srl_k_b, srl_k_a, srl_k_b, srl_k_a, srl_k_b, srl_k_a, srl_k_b,
	148	&tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b,
	149	&tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b,
537	150	/* 0x2e00 */
538		srl_k_a, srl_k_b, srl_k_a, srl_k_b, srl_k_a, srl_k_b, srl_k_a, srl_k_b,
539		srl_k_a, srl_k_b, srl_k_a, srl_k_b, srl_k_a, srl_k_b, srl_k_a, srl_k_b,
	151	&tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b,
	152	&tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b,
540	153	/* 0x2f00 */
541		srl_k_a, srl_k_b, srl_k_a, srl_k_b, srl_k_a, srl_k_b, srl_k_a, srl_k_b,
542		srl_k_a, srl_k_b, srl_k_a, srl_k_b, srl_k_a, srl_k_b, srl_k_a, srl_k_b,
	154	&tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b,
	155	&tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b,
543	156	/* 0x3000 */
544		rl_k_a, rl_k_b, rl_k_a, rl_k_b, rl_k_a, rl_k_b, rl_k_a, rl_k_b,
545		rl_k_a, rl_k_b, rl_k_a, rl_k_b, rl_k_a, rl_k_b, rl_k_a, rl_k_b,
	157	&tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b,
	158	&tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b,
546	159	/* 0x3100 */
547		rl_k_a, rl_k_b, rl_k_a, rl_k_b, rl_k_a, rl_k_b, rl_k_a, rl_k_b,
548		rl_k_a, rl_k_b, rl_k_a, rl_k_b, rl_k_a, rl_k_b, rl_k_a, rl_k_b,
	160	&tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b,
	161	&tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b,
549	162	/* 0x3200 */
550		rl_k_a, rl_k_b, rl_k_a, rl_k_b, rl_k_a, rl_k_b, rl_k_a, rl_k_b,
551		rl_k_a, rl_k_b, rl_k_a, rl_k_b, rl_k_a, rl_k_b, rl_k_a, rl_k_b,
	163	&tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b,
	164	&tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b,
552	165	/* 0x3300 */
553		rl_k_a, rl_k_b, rl_k_a, rl_k_b, rl_k_a, rl_k_b, rl_k_a, rl_k_b,
554		rl_k_a, rl_k_b, rl_k_a, rl_k_b, rl_k_a, rl_k_b, rl_k_a, rl_k_b,
	166	&tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b,
	167	&tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b,
555	168	/* 0x3400 */
556		cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b,
557		cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b,
	169	&tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b,
	170	&tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b,
558	171	/* 0x3500 */
559		cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b,
560		cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b,
	172	&tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b,
	173	&tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b,
561	174	/* 0x3600 */
562		cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b,
563		cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b,
	175	&tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b,
	176	&tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b,
564	177	/* 0x3700 */
565		cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b,
566		cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b, cmp_k_a, cmp_k_b,
	178	&tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b,
	179	&tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b,
567	180	/* 0x3800 */
568		dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b,
569		dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b,
	181	&tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b,
	182	&tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b,
570	183	/* 0x3900 */
571		dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b,
572		dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b,
	184	&tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b,
	185	&tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b,
573	186	/* 0x3a00 */
574		dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b,
575		dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b,
	187	&tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b,
	188	&tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b,
576	189	/* 0x3b00 */
577		dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b,
578		dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b,
	190	&tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b,
	191	&tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b,
579	192	/* 0x3c00 */
580		dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b,
581		dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b,
	193	&tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b,
	194	&tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b,
582	195	/* 0x3d00 */
583		dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b,
584		dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b,
	196	&tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b,
	197	&tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b,
585	198	/* 0x3e00 */
586		dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b,
587		dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b,
	199	&tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b,
	200	&tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b,
588	201	/* 0x3f00 */
589		dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b,
590		dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b, dsjs_a, dsjs_b,
	202	&tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b,
	203	&tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b,
591	204	/* 0x4000 */
592		add_a, add_b, add_a, add_b, add_a, add_b, add_a, add_b,
593		add_a, add_b, add_a, add_b, add_a, add_b, add_a, add_b,
	205	&tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b,
	206	&tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b,
594	207	/* 0x4100 */
595		add_a, add_b, add_a, add_b, add_a, add_b, add_a, add_b,
596		add_a, add_b, add_a, add_b, add_a, add_b, add_a, add_b,
	208	&tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b,
	209	&tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b,
597	210	/* 0x4200 */
598		addc_a, addc_b, addc_a, addc_b, addc_a, addc_b, addc_a, addc_b,
599		addc_a, addc_b, addc_a, addc_b, addc_a, addc_b, addc_a, addc_b,
	211	&tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b,
	212	&tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b,
600	213	/* 0x4300 */
601		addc_a, addc_b, addc_a, addc_b, addc_a, addc_b, addc_a, addc_b,
602		addc_a, addc_b, addc_a, addc_b, addc_a, addc_b, addc_a, addc_b,
	214	&tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b,
	215	&tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b,
603	216	/* 0x4400 */
604		sub_a, sub_b, sub_a, sub_b, sub_a, sub_b, sub_a, sub_b,
605		sub_a, sub_b, sub_a, sub_b, sub_a, sub_b, sub_a, sub_b,
	217	&tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b,
	218	&tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b,
606	219	/* 0x4500 */
607		sub_a, sub_b, sub_a, sub_b, sub_a, sub_b, sub_a, sub_b,
608		sub_a, sub_b, sub_a, sub_b, sub_a, sub_b, sub_a, sub_b,
	220	&tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b,
	221	&tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b,
609	222	/* 0x4600 */
610		subb_a, subb_b, subb_a, subb_b, subb_a, subb_b, subb_a, subb_b,
611		subb_a, subb_b, subb_a, subb_b, subb_a, subb_b, subb_a, subb_b,
	223	&tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b,
	224	&tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b,
612	225	/* 0x4700 */
613		subb_a, subb_b, subb_a, subb_b, subb_a, subb_b, subb_a, subb_b,
614		subb_a, subb_b, subb_a, subb_b, subb_a, subb_b, subb_a, subb_b,
	226	&tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b,
	227	&tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b,
615	228	/* 0x4800 */
616		cmp_a, cmp_b, cmp_a, cmp_b, cmp_a, cmp_b, cmp_a, cmp_b,
617		cmp_a, cmp_b, cmp_a, cmp_b, cmp_a, cmp_b, cmp_a, cmp_b,
	229	&tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b,
	230	&tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b,
618	231	/* 0x4900 */
619		cmp_a, cmp_b, cmp_a, cmp_b, cmp_a, cmp_b, cmp_a, cmp_b,
620		cmp_a, cmp_b, cmp_a, cmp_b, cmp_a, cmp_b, cmp_a, cmp_b,
	232	&tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b,
	233	&tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b,
621	234	/* 0x4a00 */
622		btst_r_a, btst_r_b, btst_r_a, btst_r_b, btst_r_a, btst_r_b, btst_r_a, btst_r_b,
623		btst_r_a, btst_r_b, btst_r_a, btst_r_b, btst_r_a, btst_r_b, btst_r_a, btst_r_b,
	235	&tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b,
	236	&tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b,
624	237	/* 0x4b00 */
625		btst_r_a, btst_r_b, btst_r_a, btst_r_b, btst_r_a, btst_r_b, btst_r_a, btst_r_b,
626		btst_r_a, btst_r_b, btst_r_a, btst_r_b, btst_r_a, btst_r_b, btst_r_a, btst_r_b,
	238	&tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b,
	239	&tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b,
627	240	/* 0x4c00 */
628		move_rr_a, move_rr_b, move_rr_a, move_rr_b, move_rr_a, move_rr_b, move_rr_a, move_rr_b,
629		move_rr_a, move_rr_b, move_rr_a, move_rr_b, move_rr_a, move_rr_b, move_rr_a, move_rr_b,
	241	&tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b,
	242	&tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b,
630	243	/* 0x4d00 */
631		move_rr_a, move_rr_b, move_rr_a, move_rr_b, move_rr_a, move_rr_b, move_rr_a, move_rr_b,
632		move_rr_a, move_rr_b, move_rr_a, move_rr_b, move_rr_a, move_rr_b, move_rr_a, move_rr_b,
	244	&tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b,
	245	&tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b,
633	246	/* 0x4e00 */
634		move_rr_ax, move_rr_bx, move_rr_ax, move_rr_bx, move_rr_ax, move_rr_bx, move_rr_ax, move_rr_bx,
635		move_rr_ax, move_rr_bx, move_rr_ax, move_rr_bx, move_rr_ax, move_rr_bx, move_rr_ax, move_rr_bx,
	247	&tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx,
	248	&tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx,
636	249	/* 0x4f00 */
637		move_rr_ax, move_rr_bx, move_rr_ax, move_rr_bx, move_rr_ax, move_rr_bx, move_rr_ax, move_rr_bx,
638		move_rr_ax, move_rr_bx, move_rr_ax, move_rr_bx, move_rr_ax, move_rr_bx, move_rr_ax, move_rr_bx,
	250	&tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx,
	251	&tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx,
639	252	/* 0x5000 */
640		and_a, and_b, and_a, and_b, and_a, and_b, and_a, and_b,
641		and_a, and_b, and_a, and_b, and_a, and_b, and_a, and_b,
	253	&tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b,
	254	&tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b,
642	255	/* 0x5100 */
643		and_a, and_b, and_a, and_b, and_a, and_b, and_a, and_b,
644		and_a, and_b, and_a, and_b, and_a, and_b, and_a, and_b,
	256	&tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b,
	257	&tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b,
645	258	/* 0x5200 */
646		andn_a, andn_b, andn_a, andn_b, andn_a, andn_b, andn_a, andn_b,
647		andn_a, andn_b, andn_a, andn_b, andn_a, andn_b, andn_a, andn_b,
	259	&tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b,
	260	&tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b,
648	261	/* 0x5300 */
649		andn_a, andn_b, andn_a, andn_b, andn_a, andn_b, andn_a, andn_b,
650		andn_a, andn_b, andn_a, andn_b, andn_a, andn_b, andn_a, andn_b,
	262	&tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b,
	263	&tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b,
651	264	/* 0x5400 */
652		or_a, or_b, or_a, or_b, or_a, or_b, or_a, or_b,
653		or_a, or_b, or_a, or_b, or_a, or_b, or_a, or_b,
	265	&tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b,
	266	&tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b,
654	267	/* 0x5500 */
655		or_a, or_b, or_a, or_b, or_a, or_b, or_a, or_b,
656		or_a, or_b, or_a, or_b, or_a, or_b, or_a, or_b,
	268	&tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b,
	269	&tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b,
657	270	/* 0x5600 */
658		xor_a, xor_b, xor_a, xor_b, xor_a, xor_b, xor_a, xor_b,
659		xor_a, xor_b, xor_a, xor_b, xor_a, xor_b, xor_a, xor_b,
	271	&tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b,
	272	&tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b,
660	273	/* 0x5700 */
661		xor_a, xor_b, xor_a, xor_b, xor_a, xor_b, xor_a, xor_b,
662		xor_a, xor_b, xor_a, xor_b, xor_a, xor_b, xor_a, xor_b,
	274	&tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b,
	275	&tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b,
663	276	/* 0x5800 */
664		divs_a, divs_b, divs_a, divs_b, divs_a, divs_b, divs_a, divs_b,
665		divs_a, divs_b, divs_a, divs_b, divs_a, divs_b, divs_a, divs_b,
	277	&tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b,
	278	&tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b,
666	279	/* 0x5900 */
667		divs_a, divs_b, divs_a, divs_b, divs_a, divs_b, divs_a, divs_b,
668		divs_a, divs_b, divs_a, divs_b, divs_a, divs_b, divs_a, divs_b,
	280	&tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b,
	281	&tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b,
669	282	/* 0x5a00 */
670		divu_a, divu_b, divu_a, divu_b, divu_a, divu_b, divu_a, divu_b,
671		divu_a, divu_b, divu_a, divu_b, divu_a, divu_b, divu_a, divu_b,
	283	&tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b,
	284	&tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b,
672	285	/* 0x5b00 */
673		divu_a, divu_b, divu_a, divu_b, divu_a, divu_b, divu_a, divu_b,
674		divu_a, divu_b, divu_a, divu_b, divu_a, divu_b, divu_a, divu_b,
	286	&tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b,
	287	&tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b,
675	288	/* 0x5c00 */
676		mpys_a, mpys_b, mpys_a, mpys_b, mpys_a, mpys_b, mpys_a, mpys_b,
677		mpys_a, mpys_b, mpys_a, mpys_b, mpys_a, mpys_b, mpys_a, mpys_b,
	289	&tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b,
	290	&tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b,
678	291	/* 0x5d00 */
679		mpys_a, mpys_b, mpys_a, mpys_b, mpys_a, mpys_b, mpys_a, mpys_b,
680		mpys_a, mpys_b, mpys_a, mpys_b, mpys_a, mpys_b, mpys_a, mpys_b,
	292	&tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b,
	293	&tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b,
681	294	/* 0x5e00 */
682		mpyu_a, mpyu_b, mpyu_a, mpyu_b, mpyu_a, mpyu_b, mpyu_a, mpyu_b,
683		mpyu_a, mpyu_b, mpyu_a, mpyu_b, mpyu_a, mpyu_b, mpyu_a, mpyu_b,
	295	&tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b,
	296	&tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b,
684	297	/* 0x5f00 */
685		mpyu_a, mpyu_b, mpyu_a, mpyu_b, mpyu_a, mpyu_b, mpyu_a, mpyu_b,
686		mpyu_a, mpyu_b, mpyu_a, mpyu_b, mpyu_a, mpyu_b, mpyu_a, mpyu_b,
	298	&tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b,
	299	&tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b,
687	300	/* 0x6000 */
688		sla_r_a, sla_r_b, sla_r_a, sla_r_b, sla_r_a, sla_r_b, sla_r_a, sla_r_b,
689		sla_r_a, sla_r_b, sla_r_a, sla_r_b, sla_r_a, sla_r_b, sla_r_a, sla_r_b,
	301	&tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b,
	302	&tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b,
690	303	/* 0x6100 */
691		sla_r_a, sla_r_b, sla_r_a, sla_r_b, sla_r_a, sla_r_b, sla_r_a, sla_r_b,
692		sla_r_a, sla_r_b, sla_r_a, sla_r_b, sla_r_a, sla_r_b, sla_r_a, sla_r_b,
	304	&tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b,
	305	&tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b,
693	306	/* 0x6200 */
694		sll_r_a, sll_r_b, sll_r_a, sll_r_b, sll_r_a, sll_r_b, sll_r_a, sll_r_b,
695		sll_r_a, sll_r_b, sll_r_a, sll_r_b, sll_r_a, sll_r_b, sll_r_a, sll_r_b,
	307	&tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b,
	308	&tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b,
696	309	/* 0x6300 */
697		sll_r_a, sll_r_b, sll_r_a, sll_r_b, sll_r_a, sll_r_b, sll_r_a, sll_r_b,
698		sll_r_a, sll_r_b, sll_r_a, sll_r_b, sll_r_a, sll_r_b, sll_r_a, sll_r_b,
	310	&tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b,
	311	&tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b,
699	312	/* 0x6400 */
700		sra_r_a, sra_r_b, sra_r_a, sra_r_b, sra_r_a, sra_r_b, sra_r_a, sra_r_b,
701		sra_r_a, sra_r_b, sra_r_a, sra_r_b, sra_r_a, sra_r_b, sra_r_a, sra_r_b,
	313	&tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b,
	314	&tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b,
702	315	/* 0x6500 */
703		sra_r_a, sra_r_b, sra_r_a, sra_r_b, sra_r_a, sra_r_b, sra_r_a, sra_r_b,
704		sra_r_a, sra_r_b, sra_r_a, sra_r_b, sra_r_a, sra_r_b, sra_r_a, sra_r_b,
	316	&tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b,
	317	&tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b,
705	318	/* 0x6600 */
706		srl_r_a, srl_r_b, srl_r_a, srl_r_b, srl_r_a, srl_r_b, srl_r_a, srl_r_b,
707		srl_r_a, srl_r_b, srl_r_a, srl_r_b, srl_r_a, srl_r_b, srl_r_a, srl_r_b,
	319	&tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b,
	320	&tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b,
708	321	/* 0x6700 */
709		srl_r_a, srl_r_b, srl_r_a, srl_r_b, srl_r_a, srl_r_b, srl_r_a, srl_r_b,
710		srl_r_a, srl_r_b, srl_r_a, srl_r_b, srl_r_a, srl_r_b, srl_r_a, srl_r_b,
	322	&tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b,
	323	&tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b,
711	324	/* 0x6800 */
712		rl_r_a, rl_r_b, rl_r_a, rl_r_b, rl_r_a, rl_r_b, rl_r_a, rl_r_b,
713		rl_r_a, rl_r_b, rl_r_a, rl_r_b, rl_r_a, rl_r_b, rl_r_a, rl_r_b,
	325	&tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b,
	326	&tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b,
714	327	/* 0x6900 */
715		rl_r_a, rl_r_b, rl_r_a, rl_r_b, rl_r_a, rl_r_b, rl_r_a, rl_r_b,
716		rl_r_a, rl_r_b, rl_r_a, rl_r_b, rl_r_a, rl_r_b, rl_r_a, rl_r_b,
	328	&tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b,
	329	&tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b,
717	330	/* 0x6a00 */
718		lmo_a, lmo_b, lmo_a, lmo_b, lmo_a, lmo_b, lmo_a, lmo_b,
719		lmo_a, lmo_b, lmo_a, lmo_b, lmo_a, lmo_b, lmo_a, lmo_b,
	331	&tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b,
	332	&tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b,
720	333	/* 0x6b00 */
721		lmo_a, lmo_b, lmo_a, lmo_b, lmo_a, lmo_b, lmo_a, lmo_b,
722		lmo_a, lmo_b, lmo_a, lmo_b, lmo_a, lmo_b, lmo_a, lmo_b,
	334	&tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b,
	335	&tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b,
723	336	/* 0x6c00 */
724		mods_a, mods_b, mods_a, mods_b, mods_a, mods_b, mods_a, mods_b,
725		mods_a, mods_b, mods_a, mods_b, mods_a, mods_b, mods_a, mods_b,
	337	&tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b,
	338	&tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b,
726	339	/* 0x6d00 */
727		mods_a, mods_b, mods_a, mods_b, mods_a, mods_b, mods_a, mods_b,
728		mods_a, mods_b, mods_a, mods_b, mods_a, mods_b, mods_a, mods_b,
	340	&tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b,
	341	&tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b,
729	342	/* 0x6e00 */
730		modu_a, modu_b, modu_a, modu_b, modu_a, modu_b, modu_a, modu_b,
731		modu_a, modu_b, modu_a, modu_b, modu_a, modu_b, modu_a, modu_b,
	343	&tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b,
	344	&tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b,
732	345	/* 0x6f00 */
733		modu_a, modu_b, modu_a, modu_b, modu_a, modu_b, modu_a, modu_b,
734		modu_a, modu_b, modu_a, modu_b, modu_a, modu_b, modu_a, modu_b,
	346	&tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b,
	347	&tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b,
735	348	/* 0x7000 */
736		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
737		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	349	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	350	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
738	351	/* 0x7100 */
739		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
740		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	352	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	353	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
741	354	/* 0x7200 */
742		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
743		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	355	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	356	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
744	357	/* 0x7300 */
745		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
746		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	358	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	359	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
747	360	/* 0x7400 */
748		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
749		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	361	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	362	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
750	363	/* 0x7500 */
751		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
752		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	364	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	365	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
753	366	/* 0x7600 */
754		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
755		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	367	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	368	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
756	369	/* 0x7700 */
757		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
758		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	370	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	371	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
759	372	/* 0x7800 */
760		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
761		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	373	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	374	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
762	375	/* 0x7900 */
763		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
764		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	376	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	377	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
765	378	/* 0x7a00 */
766		rmo_a, rmo_b, rmo_a, rmo_b, rmo_a, rmo_b, rmo_a, rmo_b,
767		rmo_a, rmo_b, rmo_a, rmo_b, rmo_a, rmo_b, rmo_a, rmo_b,
	379	&tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b,
	380	&tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b,
768	381	/* 0x7b00 */
769		rmo_a, rmo_b, rmo_a, rmo_b, rmo_a, rmo_b, rmo_a, rmo_b,
770		rmo_a, rmo_b, rmo_a, rmo_b, rmo_a, rmo_b, rmo_a, rmo_b,
	382	&tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b,
	383	&tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b,
771	384	/* 0x7c00 */
772		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
773		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	385	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	386	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
774	387	/* 0x7d00 */
775		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
776		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	388	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	389	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
777	390	/* 0x7e00 */
778		swapf_a, swapf_b, swapf_a, swapf_b, swapf_a, swapf_b, swapf_a, swapf_b,
779		swapf_a, swapf_b, swapf_a, swapf_b, swapf_a, swapf_b, swapf_a, swapf_b,
	391	&tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b,
	392	&tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b,
780	393	/* 0x7f00 */
781		swapf_a, swapf_b, swapf_a, swapf_b, swapf_a, swapf_b, swapf_a, swapf_b,
782		swapf_a, swapf_b, swapf_a, swapf_b, swapf_a, swapf_b, swapf_a, swapf_b,
	394	&tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b,
	395	&tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b,
783	396	/* 0x8000 */
784		move0_rn_a, move0_rn_b, move0_rn_a, move0_rn_b, move0_rn_a, move0_rn_b, move0_rn_a, move0_rn_b,
785		move0_rn_a, move0_rn_b, move0_rn_a, move0_rn_b, move0_rn_a, move0_rn_b, move0_rn_a, move0_rn_b,
	397	&tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b,
	398	&tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b,
786	399	/* 0x8100 */
787		move0_rn_a, move0_rn_b, move0_rn_a, move0_rn_b, move0_rn_a, move0_rn_b, move0_rn_a, move0_rn_b,
788		move0_rn_a, move0_rn_b, move0_rn_a, move0_rn_b, move0_rn_a, move0_rn_b, move0_rn_a, move0_rn_b,
	400	&tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b,
	401	&tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b,
789	402	/* 0x8200 */
790		move1_rn_a, move1_rn_b, move1_rn_a, move1_rn_b, move1_rn_a, move1_rn_b, move1_rn_a, move1_rn_b,
791		move1_rn_a, move1_rn_b, move1_rn_a, move1_rn_b, move1_rn_a, move1_rn_b, move1_rn_a, move1_rn_b,
	403	&tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b,
	404	&tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b,
792	405	/* 0x8300 */
793		move1_rn_a, move1_rn_b, move1_rn_a, move1_rn_b, move1_rn_a, move1_rn_b, move1_rn_a, move1_rn_b,
794		move1_rn_a, move1_rn_b, move1_rn_a, move1_rn_b, move1_rn_a, move1_rn_b, move1_rn_a, move1_rn_b,
	406	&tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b,
	407	&tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b,
795	408	/* 0x8400 */
796		move0_nr_a, move0_nr_b, move0_nr_a, move0_nr_b, move0_nr_a, move0_nr_b, move0_nr_a, move0_nr_b,
797		move0_nr_a, move0_nr_b, move0_nr_a, move0_nr_b, move0_nr_a, move0_nr_b, move0_nr_a, move0_nr_b,
	409	&tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b,
	410	&tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b,
798	411	/* 0x8500 */
799		move0_nr_a, move0_nr_b, move0_nr_a, move0_nr_b, move0_nr_a, move0_nr_b, move0_nr_a, move0_nr_b,
800		move0_nr_a, move0_nr_b, move0_nr_a, move0_nr_b, move0_nr_a, move0_nr_b, move0_nr_a, move0_nr_b,
	412	&tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b,
	413	&tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b,
801	414	/* 0x8600 */
802		move1_nr_a, move1_nr_b, move1_nr_a, move1_nr_b, move1_nr_a, move1_nr_b, move1_nr_a, move1_nr_b,
803		move1_nr_a, move1_nr_b, move1_nr_a, move1_nr_b, move1_nr_a, move1_nr_b, move1_nr_a, move1_nr_b,
	415	&tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b,
	416	&tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b,
804	417	/* 0x8700 */
805		move1_nr_a, move1_nr_b, move1_nr_a, move1_nr_b, move1_nr_a, move1_nr_b, move1_nr_a, move1_nr_b,
806		move1_nr_a, move1_nr_b, move1_nr_a, move1_nr_b, move1_nr_a, move1_nr_b, move1_nr_a, move1_nr_b,
	418	&tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b,
	419	&tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b,
807	420	/* 0x8800 */
808		move0_nn_a, move0_nn_b, move0_nn_a, move0_nn_b, move0_nn_a, move0_nn_b, move0_nn_a, move0_nn_b,
809		move0_nn_a, move0_nn_b, move0_nn_a, move0_nn_b, move0_nn_a, move0_nn_b, move0_nn_a, move0_nn_b,
	421	&tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b,
	422	&tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b,
810	423	/* 0x8900 */
811		move0_nn_a, move0_nn_b, move0_nn_a, move0_nn_b, move0_nn_a, move0_nn_b, move0_nn_a, move0_nn_b,
812		move0_nn_a, move0_nn_b, move0_nn_a, move0_nn_b, move0_nn_a, move0_nn_b, move0_nn_a, move0_nn_b,
	424	&tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b,
	425	&tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b,
813	426	/* 0x8a00 */
814		move1_nn_a, move1_nn_b, move1_nn_a, move1_nn_b, move1_nn_a, move1_nn_b, move1_nn_a, move1_nn_b,
815		move1_nn_a, move1_nn_b, move1_nn_a, move1_nn_b, move1_nn_a, move1_nn_b, move1_nn_a, move1_nn_b,
	427	&tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b,
	428	&tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b,
816	429	/* 0x8b00 */
817		move1_nn_a, move1_nn_b, move1_nn_a, move1_nn_b, move1_nn_a, move1_nn_b, move1_nn_a, move1_nn_b,
818		move1_nn_a, move1_nn_b, move1_nn_a, move1_nn_b, move1_nn_a, move1_nn_b, move1_nn_a, move1_nn_b,
	430	&tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b,
	431	&tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b,
819	432	/* 0x8c00 */
820		movb_rn_a, movb_rn_b, movb_rn_a, movb_rn_b, movb_rn_a, movb_rn_b, movb_rn_a, movb_rn_b,
821		movb_rn_a, movb_rn_b, movb_rn_a, movb_rn_b, movb_rn_a, movb_rn_b, movb_rn_a, movb_rn_b,
	433	&tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b,
	434	&tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b,
822	435	/* 0x8d00 */
823		movb_rn_a, movb_rn_b, movb_rn_a, movb_rn_b, movb_rn_a, movb_rn_b, movb_rn_a, movb_rn_b,
824		movb_rn_a, movb_rn_b, movb_rn_a, movb_rn_b, movb_rn_a, movb_rn_b, movb_rn_a, movb_rn_b,
	436	&tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b,
	437	&tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b,
825	438	/* 0x8e00 */
826		movb_nr_a, movb_nr_b, movb_nr_a, movb_nr_b, movb_nr_a, movb_nr_b, movb_nr_a, movb_nr_b,
827		movb_nr_a, movb_nr_b, movb_nr_a, movb_nr_b, movb_nr_a, movb_nr_b, movb_nr_a, movb_nr_b,
	439	&tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b,
	440	&tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b,
828	441	/* 0x8f00 */
829		movb_nr_a, movb_nr_b, movb_nr_a, movb_nr_b, movb_nr_a, movb_nr_b, movb_nr_a, movb_nr_b,
830		movb_nr_a, movb_nr_b, movb_nr_a, movb_nr_b, movb_nr_a, movb_nr_b, movb_nr_a, movb_nr_b,
	442	&tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b,
	443	&tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b,
831	444	/* 0x9000 */
832		move0_r_ni_a, move0_r_ni_b, move0_r_ni_a, move0_r_ni_b, move0_r_ni_a, move0_r_ni_b, move0_r_ni_a, move0_r_ni_b,
833		move0_r_ni_a, move0_r_ni_b, move0_r_ni_a, move0_r_ni_b, move0_r_ni_a, move0_r_ni_b, move0_r_ni_a, move0_r_ni_b,
	445	&tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b,
	446	&tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b,
834	447	/* 0x9100 */
835		move0_r_ni_a, move0_r_ni_b, move0_r_ni_a, move0_r_ni_b, move0_r_ni_a, move0_r_ni_b, move0_r_ni_a, move0_r_ni_b,
836		move0_r_ni_a, move0_r_ni_b, move0_r_ni_a, move0_r_ni_b, move0_r_ni_a, move0_r_ni_b, move0_r_ni_a, move0_r_ni_b,
	448	&tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b,
	449	&tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b,
837	450	/* 0x9200 */
838		move1_r_ni_a, move1_r_ni_b, move1_r_ni_a, move1_r_ni_b, move1_r_ni_a, move1_r_ni_b, move1_r_ni_a, move1_r_ni_b,
839		move1_r_ni_a, move1_r_ni_b, move1_r_ni_a, move1_r_ni_b, move1_r_ni_a, move1_r_ni_b, move1_r_ni_a, move1_r_ni_b,
	451	&tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b,
	452	&tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b,
840	453	/* 0x9300 */
841		move1_r_ni_a, move1_r_ni_b, move1_r_ni_a, move1_r_ni_b, move1_r_ni_a, move1_r_ni_b, move1_r_ni_a, move1_r_ni_b,
842		move1_r_ni_a, move1_r_ni_b, move1_r_ni_a, move1_r_ni_b, move1_r_ni_a, move1_r_ni_b, move1_r_ni_a, move1_r_ni_b,
	454	&tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b,
	455	&tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b,
843	456	/* 0x9400 */
844		move0_ni_r_a, move0_ni_r_b, move0_ni_r_a, move0_ni_r_b, move0_ni_r_a, move0_ni_r_b, move0_ni_r_a, move0_ni_r_b,
845		move0_ni_r_a, move0_ni_r_b, move0_ni_r_a, move0_ni_r_b, move0_ni_r_a, move0_ni_r_b, move0_ni_r_a, move0_ni_r_b,
	457	&tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b,
	458	&tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b,
846	459	/* 0x9500 */
847		move0_ni_r_a, move0_ni_r_b, move0_ni_r_a, move0_ni_r_b, move0_ni_r_a, move0_ni_r_b, move0_ni_r_a, move0_ni_r_b,
848		move0_ni_r_a, move0_ni_r_b, move0_ni_r_a, move0_ni_r_b, move0_ni_r_a, move0_ni_r_b, move0_ni_r_a, move0_ni_r_b,
	460	&tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b,
	461	&tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b,
849	462	/* 0x9600 */
850		move1_ni_r_a, move1_ni_r_b, move1_ni_r_a, move1_ni_r_b, move1_ni_r_a, move1_ni_r_b, move1_ni_r_a, move1_ni_r_b,
851		move1_ni_r_a, move1_ni_r_b, move1_ni_r_a, move1_ni_r_b, move1_ni_r_a, move1_ni_r_b, move1_ni_r_a, move1_ni_r_b,
	463	&tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b,
	464	&tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b,
852	465	/* 0x9700 */
853		move1_ni_r_a, move1_ni_r_b, move1_ni_r_a, move1_ni_r_b, move1_ni_r_a, move1_ni_r_b, move1_ni_r_a, move1_ni_r_b,
854		move1_ni_r_a, move1_ni_r_b, move1_ni_r_a, move1_ni_r_b, move1_ni_r_a, move1_ni_r_b, move1_ni_r_a, move1_ni_r_b,
	466	&tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b,
	467	&tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b,
855	468	/* 0x9800 */
856		move0_ni_ni_a, move0_ni_ni_b, move0_ni_ni_a, move0_ni_ni_b, move0_ni_ni_a, move0_ni_ni_b, move0_ni_ni_a, move0_ni_ni_b,
857		move0_ni_ni_a, move0_ni_ni_b, move0_ni_ni_a, move0_ni_ni_b, move0_ni_ni_a, move0_ni_ni_b, move0_ni_ni_a, move0_ni_ni_b,
	469	&tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b,
	470	&tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b,
858	471	/* 0x9900 */
859		move0_ni_ni_a, move0_ni_ni_b, move0_ni_ni_a, move0_ni_ni_b, move0_ni_ni_a, move0_ni_ni_b, move0_ni_ni_a, move0_ni_ni_b,
860		move0_ni_ni_a, move0_ni_ni_b, move0_ni_ni_a, move0_ni_ni_b, move0_ni_ni_a, move0_ni_ni_b, move0_ni_ni_a, move0_ni_ni_b,
	472	&tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b,
	473	&tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b,
861	474	/* 0x9a00 */
862		move1_ni_ni_a, move1_ni_ni_b, move1_ni_ni_a, move1_ni_ni_b, move1_ni_ni_a, move1_ni_ni_b, move1_ni_ni_a, move1_ni_ni_b,
863		move1_ni_ni_a, move1_ni_ni_b, move1_ni_ni_a, move1_ni_ni_b, move1_ni_ni_a, move1_ni_ni_b, move1_ni_ni_a, move1_ni_ni_b,
	475	&tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b,
	476	&tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b,
864	477	/* 0x9b00 */
865		move1_ni_ni_a, move1_ni_ni_b, move1_ni_ni_a, move1_ni_ni_b, move1_ni_ni_a, move1_ni_ni_b, move1_ni_ni_a, move1_ni_ni_b,
866		move1_ni_ni_a, move1_ni_ni_b, move1_ni_ni_a, move1_ni_ni_b, move1_ni_ni_a, move1_ni_ni_b, move1_ni_ni_a, move1_ni_ni_b,
	478	&tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b,
	479	&tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b,
867	480	/* 0x9c00 */
868		movb_nn_a, movb_nn_b, movb_nn_a, movb_nn_b, movb_nn_a, movb_nn_b, movb_nn_a, movb_nn_b,
869		movb_nn_a, movb_nn_b, movb_nn_a, movb_nn_b, movb_nn_a, movb_nn_b, movb_nn_a, movb_nn_b,
	481	&tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b,
	482	&tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b,
870	483	/* 0x9d00 */
871		movb_nn_a, movb_nn_b, movb_nn_a, movb_nn_b, movb_nn_a, movb_nn_b, movb_nn_a, movb_nn_b,
872		movb_nn_a, movb_nn_b, movb_nn_a, movb_nn_b, movb_nn_a, movb_nn_b, movb_nn_a, movb_nn_b,
	484	&tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b,
	485	&tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b,
873	486	/* 0x9e00 */
874		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
875		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	487	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	488	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
876	489	/* 0x9f00 */
877		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
878		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	490	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	491	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
879	492	/* 0xa000 */
880		move0_r_dn_a, move0_r_dn_b, move0_r_dn_a, move0_r_dn_b, move0_r_dn_a, move0_r_dn_b, move0_r_dn_a, move0_r_dn_b,
881		move0_r_dn_a, move0_r_dn_b, move0_r_dn_a, move0_r_dn_b, move0_r_dn_a, move0_r_dn_b, move0_r_dn_a, move0_r_dn_b,
	493	&tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b,
	494	&tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b,
882	495	/* 0xa100 */
883		move0_r_dn_a, move0_r_dn_b, move0_r_dn_a, move0_r_dn_b, move0_r_dn_a, move0_r_dn_b, move0_r_dn_a, move0_r_dn_b,
884		move0_r_dn_a, move0_r_dn_b, move0_r_dn_a, move0_r_dn_b, move0_r_dn_a, move0_r_dn_b, move0_r_dn_a, move0_r_dn_b,
	496	&tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b,
	497	&tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b,
885	498	/* 0xa200 */
886		move1_r_dn_a, move1_r_dn_b, move1_r_dn_a, move1_r_dn_b, move1_r_dn_a, move1_r_dn_b, move1_r_dn_a, move1_r_dn_b,
887		move1_r_dn_a, move1_r_dn_b, move1_r_dn_a, move1_r_dn_b, move1_r_dn_a, move1_r_dn_b, move1_r_dn_a, move1_r_dn_b,
	499	&tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b,
	500	&tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b,
888	501	/* 0xa300 */
889		move1_r_dn_a, move1_r_dn_b, move1_r_dn_a, move1_r_dn_b, move1_r_dn_a, move1_r_dn_b, move1_r_dn_a, move1_r_dn_b,
890		move1_r_dn_a, move1_r_dn_b, move1_r_dn_a, move1_r_dn_b, move1_r_dn_a, move1_r_dn_b, move1_r_dn_a, move1_r_dn_b,
	502	&tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b,
	503	&tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b,
891	504	/* 0xa400 */
892		move0_dn_r_a, move0_dn_r_b, move0_dn_r_a, move0_dn_r_b, move0_dn_r_a, move0_dn_r_b, move0_dn_r_a, move0_dn_r_b,
893		move0_dn_r_a, move0_dn_r_b, move0_dn_r_a, move0_dn_r_b, move0_dn_r_a, move0_dn_r_b, move0_dn_r_a, move0_dn_r_b,
	505	&tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b,
	506	&tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b,
894	507	/* 0xa500 */
895		move0_dn_r_a, move0_dn_r_b, move0_dn_r_a, move0_dn_r_b, move0_dn_r_a, move0_dn_r_b, move0_dn_r_a, move0_dn_r_b,
896		move0_dn_r_a, move0_dn_r_b, move0_dn_r_a, move0_dn_r_b, move0_dn_r_a, move0_dn_r_b, move0_dn_r_a, move0_dn_r_b,
	508	&tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b,
	509	&tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b,
897	510	/* 0xa600 */
898		move1_dn_r_a, move1_dn_r_b, move1_dn_r_a, move1_dn_r_b, move1_dn_r_a, move1_dn_r_b, move1_dn_r_a, move1_dn_r_b,
899		move1_dn_r_a, move1_dn_r_b, move1_dn_r_a, move1_dn_r_b, move1_dn_r_a, move1_dn_r_b, move1_dn_r_a, move1_dn_r_b,
	511	&tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b,
	512	&tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b,
900	513	/* 0xa700 */
901		move1_dn_r_a, move1_dn_r_b, move1_dn_r_a, move1_dn_r_b, move1_dn_r_a, move1_dn_r_b, move1_dn_r_a, move1_dn_r_b,
902		move1_dn_r_a, move1_dn_r_b, move1_dn_r_a, move1_dn_r_b, move1_dn_r_a, move1_dn_r_b, move1_dn_r_a, move1_dn_r_b,
	514	&tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b,
	515	&tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b,
903	516	/* 0xa800 */
904		move0_dn_dn_a, move0_dn_dn_b, move0_dn_dn_a, move0_dn_dn_b, move0_dn_dn_a, move0_dn_dn_b, move0_dn_dn_a, move0_dn_dn_b,
905		move0_dn_dn_a, move0_dn_dn_b, move0_dn_dn_a, move0_dn_dn_b, move0_dn_dn_a, move0_dn_dn_b, move0_dn_dn_a, move0_dn_dn_b,
	517	&tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b,
	518	&tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b,
906	519	/* 0xa900 */
907		move0_dn_dn_a, move0_dn_dn_b, move0_dn_dn_a, move0_dn_dn_b, move0_dn_dn_a, move0_dn_dn_b, move0_dn_dn_a, move0_dn_dn_b,
908		move0_dn_dn_a, move0_dn_dn_b, move0_dn_dn_a, move0_dn_dn_b, move0_dn_dn_a, move0_dn_dn_b, move0_dn_dn_a, move0_dn_dn_b,
	520	&tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b,
	521	&tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b,
909	522	/* 0xaa00 */
910		move1_dn_dn_a, move1_dn_dn_b, move1_dn_dn_a, move1_dn_dn_b, move1_dn_dn_a, move1_dn_dn_b, move1_dn_dn_a, move1_dn_dn_b,
911		move1_dn_dn_a, move1_dn_dn_b, move1_dn_dn_a, move1_dn_dn_b, move1_dn_dn_a, move1_dn_dn_b, move1_dn_dn_a, move1_dn_dn_b,
	523	&tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b,
	524	&tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b,
912	525	/* 0xab00 */
913		move1_dn_dn_a, move1_dn_dn_b, move1_dn_dn_a, move1_dn_dn_b, move1_dn_dn_a, move1_dn_dn_b, move1_dn_dn_a, move1_dn_dn_b,
914		move1_dn_dn_a, move1_dn_dn_b, move1_dn_dn_a, move1_dn_dn_b, move1_dn_dn_a, move1_dn_dn_b, move1_dn_dn_a, move1_dn_dn_b,
	526	&tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b,
	527	&tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b,
915	528	/* 0xac00 */
916		movb_r_no_a, movb_r_no_b, movb_r_no_a, movb_r_no_b, movb_r_no_a, movb_r_no_b, movb_r_no_a, movb_r_no_b,
917		movb_r_no_a, movb_r_no_b, movb_r_no_a, movb_r_no_b, movb_r_no_a, movb_r_no_b, movb_r_no_a, movb_r_no_b,
	529	&tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b,
	530	&tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b,
918	531	/* 0xad00 */
919		movb_r_no_a, movb_r_no_b, movb_r_no_a, movb_r_no_b, movb_r_no_a, movb_r_no_b, movb_r_no_a, movb_r_no_b,
920		movb_r_no_a, movb_r_no_b, movb_r_no_a, movb_r_no_b, movb_r_no_a, movb_r_no_b, movb_r_no_a, movb_r_no_b,
	532	&tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b,
	533	&tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b,
921	534	/* 0xae00 */
922		movb_no_r_a, movb_no_r_b, movb_no_r_a, movb_no_r_b, movb_no_r_a, movb_no_r_b, movb_no_r_a, movb_no_r_b,
923		movb_no_r_a, movb_no_r_b, movb_no_r_a, movb_no_r_b, movb_no_r_a, movb_no_r_b, movb_no_r_a, movb_no_r_b,
	535	&tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b,
	536	&tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b,
924	537	/* 0xaf00 */
925		movb_no_r_a, movb_no_r_b, movb_no_r_a, movb_no_r_b, movb_no_r_a, movb_no_r_b, movb_no_r_a, movb_no_r_b,
926		movb_no_r_a, movb_no_r_b, movb_no_r_a, movb_no_r_b, movb_no_r_a, movb_no_r_b, movb_no_r_a, movb_no_r_b,
	538	&tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b,
	539	&tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b,
927	540	/* 0xb000 */
928		move0_r_no_a, move0_r_no_b, move0_r_no_a, move0_r_no_b, move0_r_no_a, move0_r_no_b, move0_r_no_a, move0_r_no_b,
929		move0_r_no_a, move0_r_no_b, move0_r_no_a, move0_r_no_b, move0_r_no_a, move0_r_no_b, move0_r_no_a, move0_r_no_b,
	541	&tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b,
	542	&tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b,
930	543	/* 0xb100 */
931		move0_r_no_a, move0_r_no_b, move0_r_no_a, move0_r_no_b, move0_r_no_a, move0_r_no_b, move0_r_no_a, move0_r_no_b,
932		move0_r_no_a, move0_r_no_b, move0_r_no_a, move0_r_no_b, move0_r_no_a, move0_r_no_b, move0_r_no_a, move0_r_no_b,
	544	&tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b,
	545	&tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b,
933	546	/* 0xb200 */
934		move1_r_no_a, move1_r_no_b, move1_r_no_a, move1_r_no_b, move1_r_no_a, move1_r_no_b, move1_r_no_a, move1_r_no_b,
935		move1_r_no_a, move1_r_no_b, move1_r_no_a, move1_r_no_b, move1_r_no_a, move1_r_no_b, move1_r_no_a, move1_r_no_b,
	547	&tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b,
	548	&tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b,
936	549	/* 0xb300 */
937		move1_r_no_a, move1_r_no_b, move1_r_no_a, move1_r_no_b, move1_r_no_a, move1_r_no_b, move1_r_no_a, move1_r_no_b,
938		move1_r_no_a, move1_r_no_b, move1_r_no_a, move1_r_no_b, move1_r_no_a, move1_r_no_b, move1_r_no_a, move1_r_no_b,
	550	&tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b,
	551	&tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b,
939	552	/* 0xb400 */
940		move0_no_r_a, move0_no_r_b, move0_no_r_a, move0_no_r_b, move0_no_r_a, move0_no_r_b, move0_no_r_a, move0_no_r_b,
941		move0_no_r_a, move0_no_r_b, move0_no_r_a, move0_no_r_b, move0_no_r_a, move0_no_r_b, move0_no_r_a, move0_no_r_b,
	553	&tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b,
	554	&tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b,
942	555	/* 0xb500 */
943		move0_no_r_a, move0_no_r_b, move0_no_r_a, move0_no_r_b, move0_no_r_a, move0_no_r_b, move0_no_r_a, move0_no_r_b,
944		move0_no_r_a, move0_no_r_b, move0_no_r_a, move0_no_r_b, move0_no_r_a, move0_no_r_b, move0_no_r_a, move0_no_r_b,
	556	&tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b,
	557	&tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b,
945	558	/* 0xb600 */
946		move1_no_r_a, move1_no_r_b, move1_no_r_a, move1_no_r_b, move1_no_r_a, move1_no_r_b, move1_no_r_a, move1_no_r_b,
947		move1_no_r_a, move1_no_r_b, move1_no_r_a, move1_no_r_b, move1_no_r_a, move1_no_r_b, move1_no_r_a, move1_no_r_b,
	559	&tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b,
	560	&tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b,
948	561	/* 0xb700 */
949		move1_no_r_a, move1_no_r_b, move1_no_r_a, move1_no_r_b, move1_no_r_a, move1_no_r_b, move1_no_r_a, move1_no_r_b,
950		move1_no_r_a, move1_no_r_b, move1_no_r_a, move1_no_r_b, move1_no_r_a, move1_no_r_b, move1_no_r_a, move1_no_r_b,
	562	&tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b,
	563	&tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b,
951	564	/* 0xb800 */
952		move0_no_no_a, move0_no_no_b, move0_no_no_a, move0_no_no_b, move0_no_no_a, move0_no_no_b, move0_no_no_a, move0_no_no_b,
953		move0_no_no_a, move0_no_no_b, move0_no_no_a, move0_no_no_b, move0_no_no_a, move0_no_no_b, move0_no_no_a, move0_no_no_b,
	565	&tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b,
	566	&tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b,
954	567	/* 0xb900 */
955		move0_no_no_a, move0_no_no_b, move0_no_no_a, move0_no_no_b, move0_no_no_a, move0_no_no_b, move0_no_no_a, move0_no_no_b,
956		move0_no_no_a, move0_no_no_b, move0_no_no_a, move0_no_no_b, move0_no_no_a, move0_no_no_b, move0_no_no_a, move0_no_no_b,
	568	&tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b,
	569	&tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b,
957	570	/* 0xba00 */
958		move1_no_no_a, move1_no_no_b, move1_no_no_a, move1_no_no_b, move1_no_no_a, move1_no_no_b, move1_no_no_a, move1_no_no_b,
959		move1_no_no_a, move1_no_no_b, move1_no_no_a, move1_no_no_b, move1_no_no_a, move1_no_no_b, move1_no_no_a, move1_no_no_b,
	571	&tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b,
	572	&tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b,
960	573	/* 0xbb00 */
961		move1_no_no_a, move1_no_no_b, move1_no_no_a, move1_no_no_b, move1_no_no_a, move1_no_no_b, move1_no_no_a, move1_no_no_b,
962		move1_no_no_a, move1_no_no_b, move1_no_no_a, move1_no_no_b, move1_no_no_a, move1_no_no_b, move1_no_no_a, move1_no_no_b,
	574	&tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b,
	575	&tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b,
963	576	/* 0xbc00 */
964		movb_no_no_a, movb_no_no_b, movb_no_no_a, movb_no_no_b, movb_no_no_a, movb_no_no_b, movb_no_no_a, movb_no_no_b,
965		movb_no_no_a, movb_no_no_b, movb_no_no_a, movb_no_no_b, movb_no_no_a, movb_no_no_b, movb_no_no_a, movb_no_no_b,
	577	&tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b,
	578	&tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b,
966	579	/* 0xbd00 */
967		movb_no_no_a, movb_no_no_b, movb_no_no_a, movb_no_no_b, movb_no_no_a, movb_no_no_b, movb_no_no_a, movb_no_no_b,
968		movb_no_no_a, movb_no_no_b, movb_no_no_a, movb_no_no_b, movb_no_no_a, movb_no_no_b, movb_no_no_a, movb_no_no_b,
	580	&tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b,
	581	&tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b,
969	582	/* 0xbe00 */
970		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
971		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	583	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	584	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
972	585	/* 0xbf00 */
973		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
974		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	586	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	587	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
975	588	/* 0xc000 */
976		j_UC_0, j_UC_x, j_UC_x, j_UC_x, j_UC_x, j_UC_x, j_UC_x, j_UC_x,
977		j_UC_8, j_UC_x, j_UC_x, j_UC_x, j_UC_x, j_UC_x, j_UC_x, j_UC_x,
	589	&tms340x0_device::j_UC_0, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x,
	590	&tms340x0_device::j_UC_8, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x,
978	591	/* 0xc100 */
979		j_P_0, j_P_x, j_P_x, j_P_x, j_P_x, j_P_x, j_P_x, j_P_x,
980		j_P_8, j_P_x, j_P_x, j_P_x, j_P_x, j_P_x, j_P_x, j_P_x,
	592	&tms340x0_device::j_P_0, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x,
	593	&tms340x0_device::j_P_8, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x,
981	594	/* 0xc200 */
982		j_LS_0, j_LS_x, j_LS_x, j_LS_x, j_LS_x, j_LS_x, j_LS_x, j_LS_x,
983		j_LS_8, j_LS_x, j_LS_x, j_LS_x, j_LS_x, j_LS_x, j_LS_x, j_LS_x,
	595	&tms340x0_device::j_LS_0, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x,
	596	&tms340x0_device::j_LS_8, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x,
984	597	/* 0xc300 */
985		j_HI_0, j_HI_x, j_HI_x, j_HI_x, j_HI_x, j_HI_x, j_HI_x, j_HI_x,
986		j_HI_8, j_HI_x, j_HI_x, j_HI_x, j_HI_x, j_HI_x, j_HI_x, j_HI_x,
	598	&tms340x0_device::j_HI_0, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x,
	599	&tms340x0_device::j_HI_8, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x,
987	600	/* 0xc400 */
988		j_LT_0, j_LT_x, j_LT_x, j_LT_x, j_LT_x, j_LT_x, j_LT_x, j_LT_x,
989		j_LT_8, j_LT_x, j_LT_x, j_LT_x, j_LT_x, j_LT_x, j_LT_x, j_LT_x,
	601	&tms340x0_device::j_LT_0, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x,
	602	&tms340x0_device::j_LT_8, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x,
990	603	/* 0xc500 */
991		j_GE_0, j_GE_x, j_GE_x, j_GE_x, j_GE_x, j_GE_x, j_GE_x, j_GE_x,
992		j_GE_8, j_GE_x, j_GE_x, j_GE_x, j_GE_x, j_GE_x, j_GE_x, j_GE_x,
	604	&tms340x0_device::j_GE_0, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x,
	605	&tms340x0_device::j_GE_8, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x,
993	606	/* 0xc600 */
994		j_LE_0, j_LE_x, j_LE_x, j_LE_x, j_LE_x, j_LE_x, j_LE_x, j_LE_x,
995		j_LE_8, j_LE_x, j_LE_x, j_LE_x, j_LE_x, j_LE_x, j_LE_x, j_LE_x,
	607	&tms340x0_device::j_LE_0, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x,
	608	&tms340x0_device::j_LE_8, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x,
996	609	/* 0xc700 */
997		j_GT_0, j_GT_x, j_GT_x, j_GT_x, j_GT_x, j_GT_x, j_GT_x, j_GT_x,
998		j_GT_8, j_GT_x, j_GT_x, j_GT_x, j_GT_x, j_GT_x, j_GT_x, j_GT_x,
	610	&tms340x0_device::j_GT_0, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x,
	611	&tms340x0_device::j_GT_8, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x,
999	612	/* 0xc800 */
1000		j_C_0, j_C_x, j_C_x, j_C_x, j_C_x, j_C_x, j_C_x, j_C_x,
1001		j_C_8, j_C_x, j_C_x, j_C_x, j_C_x, j_C_x, j_C_x, j_C_x,
	613	&tms340x0_device::j_C_0, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x,
	614	&tms340x0_device::j_C_8, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x,
1002	615	/* 0xc900 */
1003		j_NC_0, j_NC_x, j_NC_x, j_NC_x, j_NC_x, j_NC_x, j_NC_x, j_NC_x,
1004		j_NC_8, j_NC_x, j_NC_x, j_NC_x, j_NC_x, j_NC_x, j_NC_x, j_NC_x,
	616	&tms340x0_device::j_NC_0, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x,
	617	&tms340x0_device::j_NC_8, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x,
1005	618	/* 0xca00 */
1006		j_EQ_0, j_EQ_x, j_EQ_x, j_EQ_x, j_EQ_x, j_EQ_x, j_EQ_x, j_EQ_x,
1007		j_EQ_8, j_EQ_x, j_EQ_x, j_EQ_x, j_EQ_x, j_EQ_x, j_EQ_x, j_EQ_x,
	619	&tms340x0_device::j_EQ_0, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x,
	620	&tms340x0_device::j_EQ_8, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x,
1008	621	/* 0xcb00 */
1009		j_NE_0, j_NE_x, j_NE_x, j_NE_x, j_NE_x, j_NE_x, j_NE_x, j_NE_x,
1010		j_NE_8, j_NE_x, j_NE_x, j_NE_x, j_NE_x, j_NE_x, j_NE_x, j_NE_x,
	622	&tms340x0_device::j_NE_0, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x,
	623	&tms340x0_device::j_NE_8, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x,
1011	624	/* 0xcc00 */
1012		j_V_0, j_V_x, j_V_x, j_V_x, j_V_x, j_V_x, j_V_x, j_V_x,
1013		j_V_8, j_V_x, j_V_x, j_V_x, j_V_x, j_V_x, j_V_x, j_V_x,
	625	&tms340x0_device::j_V_0, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x,
	626	&tms340x0_device::j_V_8, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x,
1014	627	/* 0xcd00 */
1015		j_NV_0, j_NV_x, j_NV_x, j_NV_x, j_NV_x, j_NV_x, j_NV_x, j_NV_x,
1016		j_NV_8, j_NV_x, j_NV_x, j_NV_x, j_NV_x, j_NV_x, j_NV_x, j_NV_x,
	628	&tms340x0_device::j_NV_0, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x,
	629	&tms340x0_device::j_NV_8, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x,
1017	630	/* 0xce00 */
1018		j_N_0, j_N_x, j_N_x, j_N_x, j_N_x, j_N_x, j_N_x, j_N_x,
1019		j_N_8, j_N_x, j_N_x, j_N_x, j_N_x, j_N_x, j_N_x, j_N_x,
	631	&tms340x0_device::j_N_0, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x,
	632	&tms340x0_device::j_N_8, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x,
1020	633	/* 0xcf00 */
1021		j_NN_0, j_NN_x, j_NN_x, j_NN_x, j_NN_x, j_NN_x, j_NN_x, j_NN_x,
1022		j_NN_8, j_NN_x, j_NN_x, j_NN_x, j_NN_x, j_NN_x, j_NN_x, j_NN_x,
	634	&tms340x0_device::j_NN_0, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x,
	635	&tms340x0_device::j_NN_8, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x,
1023	636	/* 0xd000 */
1024		move0_no_ni_a, move0_no_ni_b, move0_no_ni_a, move0_no_ni_b, move0_no_ni_a, move0_no_ni_b, move0_no_ni_a, move0_no_ni_b,
1025		move0_no_ni_a, move0_no_ni_b, move0_no_ni_a, move0_no_ni_b, move0_no_ni_a, move0_no_ni_b, move0_no_ni_a, move0_no_ni_b,
	637	&tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b,
	638	&tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b,
1026	639	/* 0xd100 */
1027		move0_no_ni_a, move0_no_ni_b, move0_no_ni_a, move0_no_ni_b, move0_no_ni_a, move0_no_ni_b, move0_no_ni_a, move0_no_ni_b,
1028		move0_no_ni_a, move0_no_ni_b, move0_no_ni_a, move0_no_ni_b, move0_no_ni_a, move0_no_ni_b, move0_no_ni_a, move0_no_ni_b,
	640	&tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b,
	641	&tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b,
1029	642	/* 0xd200 */
1030		move1_no_ni_a, move1_no_ni_b, move1_no_ni_a, move1_no_ni_b, move1_no_ni_a, move1_no_ni_b, move1_no_ni_a, move1_no_ni_b,
1031		move1_no_ni_a, move1_no_ni_b, move1_no_ni_a, move1_no_ni_b, move1_no_ni_a, move1_no_ni_b, move1_no_ni_a, move1_no_ni_b,
	643	&tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b,
	644	&tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b,
1032	645	/* 0xd300 */
1033		move1_no_ni_a, move1_no_ni_b, move1_no_ni_a, move1_no_ni_b, move1_no_ni_a, move1_no_ni_b, move1_no_ni_a, move1_no_ni_b,
1034		move1_no_ni_a, move1_no_ni_b, move1_no_ni_a, move1_no_ni_b, move1_no_ni_a, move1_no_ni_b, move1_no_ni_a, move1_no_ni_b,
	646	&tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b,
	647	&tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b,
1035	648	/* 0xd400 */
1036		move0_a_ni_a,move0_a_ni_b,unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
1037		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	649	&tms340x0_device::move0_a_ni_a,&tms340x0_device::move0_a_ni_b,&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	650	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
1038	651	/* 0xd500 */
1039		exgf0_a, exgf0_b, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
1040		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	652	&tms340x0_device::exgf0_a, &tms340x0_device::exgf0_b, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	653	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
1041	654	/* 0xd600 */
1042		move1_a_ni_a,move1_a_ni_b,unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
1043		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	655	&tms340x0_device::move1_a_ni_a,&tms340x0_device::move1_a_ni_b,&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	656	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
1044	657	/* 0xd700 */
1045		exgf1_a, exgf1_b, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
1046		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	658	&tms340x0_device::exgf1_a, &tms340x0_device::exgf1_b, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	659	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
1047	660	/* 0xd800 */
1048		cexec_s, cexec_s, cexec_s, cexec_s, cexec_s, cexec_s, cexec_s, cexec_s,
1049		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	661	&tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s,
	662	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
1050	663	/* 0xd900 */
1051		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
1052		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	664	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	665	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
1053	666	/* 0xda00 */
1054		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
1055		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	667	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	668	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
1056	669	/* 0xdb00 */
1057		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
1058		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	670	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	671	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
1059	672	/* 0xdc00 */
1060		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
1061		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	673	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	674	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
1062	675	/* 0xdd00 */
1063		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
1064		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	676	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	677	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
1065	678	/* 0xde00 */
1066		unimpl, fline, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
1067		unimpl, fline, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	679	&tms340x0_device::unimpl, &tms340x0_device::fline, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	680	&tms340x0_device::unimpl, &tms340x0_device::fline, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
1068	681	/* 0xdf00 */
1069		unimpl, line, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
1070		unimpl, line, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	682	&tms340x0_device::unimpl, &tms340x0_device::line, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	683	&tms340x0_device::unimpl, &tms340x0_device::line, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
1071	684	/* 0xe000 */
1072		add_xy_a, add_xy_b, add_xy_a, add_xy_b, add_xy_a, add_xy_b, add_xy_a, add_xy_b,
1073		add_xy_a, add_xy_b, add_xy_a, add_xy_b, add_xy_a, add_xy_b, add_xy_a, add_xy_b,
	685	&tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b,
	686	&tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b,
1074	687	/* 0xe100 */
1075		add_xy_a, add_xy_b, add_xy_a, add_xy_b, add_xy_a, add_xy_b, add_xy_a, add_xy_b,
1076		add_xy_a, add_xy_b, add_xy_a, add_xy_b, add_xy_a, add_xy_b, add_xy_a, add_xy_b,
	688	&tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b,
	689	&tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b,
1077	690	/* 0xe200 */
1078		sub_xy_a, sub_xy_b, sub_xy_a, sub_xy_b, sub_xy_a, sub_xy_b, sub_xy_a, sub_xy_b,
1079		sub_xy_a, sub_xy_b, sub_xy_a, sub_xy_b, sub_xy_a, sub_xy_b, sub_xy_a, sub_xy_b,
	691	&tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b,
	692	&tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b,
1080	693	/* 0xe300 */
1081		sub_xy_a, sub_xy_b, sub_xy_a, sub_xy_b, sub_xy_a, sub_xy_b, sub_xy_a, sub_xy_b,
1082		sub_xy_a, sub_xy_b, sub_xy_a, sub_xy_b, sub_xy_a, sub_xy_b, sub_xy_a, sub_xy_b,
	694	&tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b,
	695	&tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b,
1083	696	/* 0xe400 */
1084		cmp_xy_a, cmp_xy_b, cmp_xy_a, cmp_xy_b, cmp_xy_a, cmp_xy_b, cmp_xy_a, cmp_xy_b,
1085		cmp_xy_a, cmp_xy_b, cmp_xy_a, cmp_xy_b, cmp_xy_a, cmp_xy_b, cmp_xy_a, cmp_xy_b,
	697	&tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b,
	698	&tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b,
1086	699	/* 0xe500 */
1087		cmp_xy_a, cmp_xy_b, cmp_xy_a, cmp_xy_b, cmp_xy_a, cmp_xy_b, cmp_xy_a, cmp_xy_b,
1088		cmp_xy_a, cmp_xy_b, cmp_xy_a, cmp_xy_b, cmp_xy_a, cmp_xy_b, cmp_xy_a, cmp_xy_b,
	700	&tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b,
	701	&tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b,
1089	702	/* 0xe600 */
1090		cpw_a, cpw_b, cpw_a, cpw_b, cpw_a, cpw_b, cpw_a, cpw_b,
1091		cpw_a, cpw_b, cpw_a, cpw_b, cpw_a, cpw_b, cpw_a, cpw_b,
	703	&tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b,
	704	&tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b,
1092	705	/* 0xe700 */
1093		cpw_a, cpw_b, cpw_a, cpw_b, cpw_a, cpw_b, cpw_a, cpw_b,
1094		cpw_a, cpw_b, cpw_a, cpw_b, cpw_a, cpw_b, cpw_a, cpw_b,
	706	&tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b,
	707	&tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b,
1095	708	/* 0xe800 */
1096		cvxyl_a, cvxyl_b, cvxyl_a, cvxyl_b, cvxyl_a, cvxyl_b, cvxyl_a, cvxyl_b,
1097		cvxyl_a, cvxyl_b, cvxyl_a, cvxyl_b, cvxyl_a, cvxyl_b, cvxyl_a, cvxyl_b,
	709	&tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b,
	710	&tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b,
1098	711	/* 0xe900 */
1099		cvxyl_a, cvxyl_b, cvxyl_a, cvxyl_b, cvxyl_a, cvxyl_b, cvxyl_a, cvxyl_b,
1100		cvxyl_a, cvxyl_b, cvxyl_a, cvxyl_b, cvxyl_a, cvxyl_b, cvxyl_a, cvxyl_b,
	712	&tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b,
	713	&tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b,
1101	714	/* 0xea00 */
1102		cvsxyl_a, cvsxyl_b, cvsxyl_a, cvsxyl_b, cvsxyl_a, cvsxyl_b, cvsxyl_a, cvsxyl_b,
1103		cvsxyl_a, cvsxyl_b, cvsxyl_a, cvsxyl_b, cvsxyl_a, cvsxyl_b, cvsxyl_a, cvsxyl_b,
	715	&tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b,
	716	&tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b,
1104	717	/* 0xeb00 */
1105		cvsxyl_a, cvsxyl_b, cvsxyl_a, cvsxyl_b, cvsxyl_a, cvsxyl_b, cvsxyl_a, cvsxyl_b,
1106		cvsxyl_a, cvsxyl_b, cvsxyl_a, cvsxyl_b, cvsxyl_a, cvsxyl_b, cvsxyl_a, cvsxyl_b,
	718	&tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b,
	719	&tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b,
1107	720	/* 0xec00 */
1108		movx_a, movx_b, movx_a, movx_b, movx_a, movx_b, movx_a, movx_b,
1109		movx_a, movx_b, movx_a, movx_b, movx_a, movx_b, movx_a, movx_b,
	721	&tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b,
	722	&tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b,
1110	723	/* 0xed00 */
1111		movx_a, movx_b, movx_a, movx_b, movx_a, movx_b, movx_a, movx_b,
1112		movx_a, movx_b, movx_a, movx_b, movx_a, movx_b, movx_a, movx_b,
	724	&tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b,
	725	&tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b,
1113	726	/* 0xee00 */
1114		movy_a, movy_b, movy_a, movy_b, movy_a, movy_b, movy_a, movy_b,
1115		movy_a, movy_b, movy_a, movy_b, movy_a, movy_b, movy_a, movy_b,
	727	&tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b,
	728	&tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b,
1116	729	/* 0xef00 */
1117		movy_a, movy_b, movy_a, movy_b, movy_a, movy_b, movy_a, movy_b,
1118		movy_a, movy_b, movy_a, movy_b, movy_a, movy_b, movy_a, movy_b,
	730	&tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b,
	731	&tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b,
1119	732	/* 0xf000 */
1120		pixt_rixy_a, pixt_rixy_b, pixt_rixy_a, pixt_rixy_b, pixt_rixy_a, pixt_rixy_b, pixt_rixy_a, pixt_rixy_b,
1121		pixt_rixy_a, pixt_rixy_b, pixt_rixy_a, pixt_rixy_b, pixt_rixy_a, pixt_rixy_b, pixt_rixy_a, pixt_rixy_b,
	733	&tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b,
	734	&tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b,
1122	735	/* 0xf100 */
1123		pixt_rixy_a, pixt_rixy_b, pixt_rixy_a, pixt_rixy_b, pixt_rixy_a, pixt_rixy_b, pixt_rixy_a, pixt_rixy_b,
1124		pixt_rixy_a, pixt_rixy_b, pixt_rixy_a, pixt_rixy_b, pixt_rixy_a, pixt_rixy_b, pixt_rixy_a, pixt_rixy_b,
	736	&tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b,
	737	&tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b,
1125	738	/* 0xf200 */
1126		pixt_ixyr_a, pixt_ixyr_b, pixt_ixyr_a, pixt_ixyr_b, pixt_ixyr_a, pixt_ixyr_b, pixt_ixyr_a, pixt_ixyr_b,
1127		pixt_ixyr_a, pixt_ixyr_b, pixt_ixyr_a, pixt_ixyr_b, pixt_ixyr_a, pixt_ixyr_b, pixt_ixyr_a, pixt_ixyr_b,
	739	&tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b,
	740	&tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b,
1128	741	/* 0xf300 */
1129		pixt_ixyr_a, pixt_ixyr_b, pixt_ixyr_a, pixt_ixyr_b, pixt_ixyr_a, pixt_ixyr_b, pixt_ixyr_a, pixt_ixyr_b,
1130		pixt_ixyr_a, pixt_ixyr_b, pixt_ixyr_a, pixt_ixyr_b, pixt_ixyr_a, pixt_ixyr_b, pixt_ixyr_a, pixt_ixyr_b,
	742	&tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b,
	743	&tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b,
1131	744	/* 0xf400 */
1132		pixt_ixyixy_a, pixt_ixyixy_b, pixt_ixyixy_a, pixt_ixyixy_b, pixt_ixyixy_a, pixt_ixyixy_b, pixt_ixyixy_a, pixt_ixyixy_b,
1133		pixt_ixyixy_a, pixt_ixyixy_b, pixt_ixyixy_a, pixt_ixyixy_b, pixt_ixyixy_a, pixt_ixyixy_b, pixt_ixyixy_a, pixt_ixyixy_b,
	745	&tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b,
	746	&tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b,
1134	747	/* 0xf500 */
1135		pixt_ixyixy_a, pixt_ixyixy_b, pixt_ixyixy_a, pixt_ixyixy_b, pixt_ixyixy_a, pixt_ixyixy_b, pixt_ixyixy_a, pixt_ixyixy_b,
1136		pixt_ixyixy_a, pixt_ixyixy_b, pixt_ixyixy_a, pixt_ixyixy_b, pixt_ixyixy_a, pixt_ixyixy_b, pixt_ixyixy_a, pixt_ixyixy_b,
	748	&tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b,
	749	&tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b,
1137	750	/* 0xf600 */
1138		drav_a, drav_b, drav_a, drav_b, drav_a, drav_b, drav_a, drav_b,
1139		drav_a, drav_b, drav_a, drav_b, drav_a, drav_b, drav_a, drav_b,
	751	&tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b,
	752	&tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b,
1140	753	/* 0xf700 */
1141		drav_a, drav_b, drav_a, drav_b, drav_a, drav_b, drav_a, drav_b,
1142		drav_a, drav_b, drav_a, drav_b, drav_a, drav_b, drav_a, drav_b,
	754	&tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b,
	755	&tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b,
1143	756	/* 0xf800 */
1144		pixt_ri_a, pixt_ri_b, pixt_ri_a, pixt_ri_b, pixt_ri_a, pixt_ri_b, pixt_ri_a, pixt_ri_b,
1145		pixt_ri_a, pixt_ri_b, pixt_ri_a, pixt_ri_b, pixt_ri_a, pixt_ri_b, pixt_ri_a, pixt_ri_b,
	757	&tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b,
	758	&tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b,
1146	759	/* 0xf900 */
1147		pixt_ri_a, pixt_ri_b, pixt_ri_a, pixt_ri_b, pixt_ri_a, pixt_ri_b, pixt_ri_a, pixt_ri_b,
1148		pixt_ri_a, pixt_ri_b, pixt_ri_a, pixt_ri_b, pixt_ri_a, pixt_ri_b, pixt_ri_a, pixt_ri_b,
	760	&tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b,
	761	&tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b,
1149	762	/* 0xfa00 */
1150		pixt_ir_a, pixt_ir_b, pixt_ir_a, pixt_ir_b, pixt_ir_a, pixt_ir_b, pixt_ir_a, pixt_ir_b,
1151		pixt_ir_a, pixt_ir_b, pixt_ir_a, pixt_ir_b, pixt_ir_a, pixt_ir_b, pixt_ir_a, pixt_ir_b,
	763	&tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b,
	764	&tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b,
1152	765	/* 0xfb00 */
1153		pixt_ir_a, pixt_ir_b, pixt_ir_a, pixt_ir_b, pixt_ir_a, pixt_ir_b, pixt_ir_a, pixt_ir_b,
1154		pixt_ir_a, pixt_ir_b, pixt_ir_a, pixt_ir_b, pixt_ir_a, pixt_ir_b, pixt_ir_a, pixt_ir_b,
	766	&tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b,
	767	&tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b,
1155	768	/* 0xfc00 */
1156		pixt_ii_a, pixt_ii_b, pixt_ii_a, pixt_ii_b, pixt_ii_a, pixt_ii_b, pixt_ii_a, pixt_ii_b,
1157		pixt_ii_a, pixt_ii_b, pixt_ii_a, pixt_ii_b, pixt_ii_a, pixt_ii_b, pixt_ii_a, pixt_ii_b,
	769	&tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b,
	770	&tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b,
1158	771	/* 0xfd00 */
1159		pixt_ii_a, pixt_ii_b, pixt_ii_a, pixt_ii_b, pixt_ii_a, pixt_ii_b, pixt_ii_a, pixt_ii_b,
1160		pixt_ii_a, pixt_ii_b, pixt_ii_a, pixt_ii_b, pixt_ii_a, pixt_ii_b, pixt_ii_a, pixt_ii_b,
	772	&tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b,
	773	&tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b,
1161	774	/* 0xfe00 */
1162		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
1163		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
	775	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	776	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
1164	777	/* 0xff00 */
1165		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl,
1166		unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl, unimpl
	778	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl,
	779	&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl
1167	780	};

trunk/src/emu/cpu/tms34010/tms34010.c
r31176	r31177
23	23	#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
24	24
25	25
	26	const device_type TMS34010 = &device_creator<tms34010_device>;
	27	const device_type TMS34020 = &device_creator<tms34020_device>;
26	28
	29
27	30	/***************************************************************************
28		CORE STATE
	31	GLOBAL VARIABLES
29	32	***************************************************************************/
30	33
31		/* Size of the memory buffer allocated for the shiftr register */
32		#define SHIFTREG_SIZE (8 * 512 * sizeof(UINT16))
33
34		/* TMS34010 State */
35		struct XY
	34	/* default configuration */
	35	static const tms340x0_config default_config =
36	36	{
37		#ifdef LSB_FIRST
38		INT16 x;
39		INT16 y;
40		#else
41		INT16 y;
42		INT16 x;
43		#endif
	37	0
44	38	};
45	39
46		struct tms34010_state
	40
	41	tms340x0_device::tms340x0_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname)
	42	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__)
	43	, m_program_config("program", ENDIANNESS_LITTLE, 16, 32, 3)
	44	, m_config(&default_config)
47	45	{
48		UINT32 pc;
49		UINT32 ppc;
50		UINT32 st;
51		void (pixel_write)(tms34010_state tms, offs_t offset, UINT32 data);
52		UINT32 (pixel_read)(tms34010_state tms, offs_t offset);
53		UINT32 (raster_op)(tms34010_state tms, UINT32 newpix, UINT32 oldpix);
54		UINT32 convsp;
55		UINT32 convdp;
56		UINT32 convmp;
57		INT32 gfxcycles;
58		UINT8 pixelshift;
59		UINT8 is_34020;
60		UINT8 reset_deferred;
61		UINT8 hblank_stable;
62		UINT8 external_host_access;
63		UINT8 executing;
64		device_irq_acknowledge_delegate irq_callback;
65		legacy_cpu_device *device;
66		address_space *program;
67		direct_read_data *direct;
68		const tms34010_config *config;
69		screen_device *screen;
70		emu_timer * scantimer;
71		int icount;
	46	}
72	47
73		/* A registers 0-15 map to regs[0]-regs[15] */
74		/* B registers 0-15 map to regs[30]-regs[15] */
75		union
76		{
77		INT32 reg;
78		XY xy;
79		} regs[31];
80	48
81		UINT16 IOregs[64];
82		UINT16 shiftreg[SHIFTREG_SIZE/2];
83		};
84
85		INLINE tms34010_state get_safe_token(device_t device)
	49	tms34010_device::tms34010_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	50	: tms340x0_device(mconfig, TMS34010, "TMS34010", tag, owner, clock, "tms34010")
86	51	{
87		assert(device != NULL);
88		assert(device->type() == TMS34010 \|\|
89		device->type() == TMS34020);
90		return (tms34010_state )downcast<legacy_cpu_device >(device)->token();
	52	m_is_34020 = 0;
91	53	}
92	54
93		#include "34010ops.h"
94	55
95
96
97		/***************************************************************************
98		GLOBAL VARIABLES
99		***************************************************************************/
100
101		/* default configuration */
102		static const tms34010_config default_config =
	56	tms34020_device::tms34020_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	57	: tms340x0_device(mconfig, TMS34020, "TMS34020", tag, owner, clock, "tms34020")
103	58	{
104		0
105		};
	59	m_is_34020 = 1;
	60	}
106	61
107		static void check_interrupt(tms34010_state *tms);
108		static TIMER_CALLBACK( scanline_callback );
109		static void tms34010_state_postload(tms34010_state *tms);
110	62
	63	#include "34010ops.h"
111	64
112	65
113	66	/***************************************************************************
r31176	r31177
127	80	#define STBITS_F0 (0x1f << 0)
128	81
129	82	/* register definitions and shortcuts */
130		#define N_FLAG(T) ((T)->st & STBIT_N)
131		#define Z_FLAG(T) ((T)->st & STBIT_Z)
132		#define C_FLAG(T) ((T)->st & STBIT_C)
133		#define V_FLAG(T) ((T)->st & STBIT_V)
134		#define P_FLAG(T) ((T)->st & STBIT_P)
135		#define IE_FLAG(T) ((T)->st & STBIT_IE)
136		#define FE0_FLAG(T) ((T)->st & STBIT_FE0)
137		#define FE1_FLAG(T) ((T)->st & STBIT_FE1)
	83	#define N_FLAG() (m_st & STBIT_N)
	84	#define Z_FLAG() (m_st & STBIT_Z)
	85	#define C_FLAG() (m_st & STBIT_C)
	86	#define V_FLAG() (m_st & STBIT_V)
	87	#define P_FLAG() (m_st & STBIT_P)
	88	#define IE_FLAG() (m_st & STBIT_IE)
	89	#define FE0_FLAG() (m_st & STBIT_FE0)
	90	#define FE1_FLAG() (m_st & STBIT_FE1)
138	91
139	92	/* register file access */
140		#define AREG(T,i) ((T)->regs[i].reg)
141		#define AREG_XY(T,i) ((T)->regs[i].xy)
142		#define AREG_X(T,i) ((T)->regs[i].xy.x)
143		#define AREG_Y(T,i) ((T)->regs[i].xy.y)
144		#define BREG(T,i) ((T)->regs[30 - (i)].reg)
145		#define BREG_XY(T,i) ((T)->regs[30 - (i)].xy)
146		#define BREG_X(T,i) ((T)->regs[30 - (i)].xy.x)
147		#define BREG_Y(T,i) ((T)->regs[30 - (i)].xy.y)
148		#define SP(T) AREG(T,15)
149		#define FW(T,i) (((T)->st >> (i ? 6 : 0)) & 0x1f)
150		#define FWEX(T,i) (((T)->st >> (i ? 6 : 0)) & 0x3f)
	93	#define AREG(i) (m_regs[i].reg)
	94	#define AREG_XY(i) (m_regs[i].xy)
	95	#define AREG_X(i) (m_regs[i].xy.x)
	96	#define AREG_Y(i) (m_regs[i].xy.y)
	97	#define BREG(i) (m_regs[30 - (i)].reg)
	98	#define BREG_XY(i) (m_regs[30 - (i)].xy)
	99	#define BREG_X(i) (m_regs[30 - (i)].xy.x)
	100	#define BREG_Y(i) (m_regs[30 - (i)].xy.y)
	101	#define SP() AREG(15)
	102	#define FW(i) ((m_st >> (i ? 6 : 0)) & 0x1f)
	103	#define FWEX(i) ((m_st >> (i ? 6 : 0)) & 0x3f)
151	104
152	105	/* opcode decode helpers */
153	106	#define SRCREG(O) (((O) >> 5) & 0x0f)
154	107	#define DSTREG(O) ((O) & 0x0f)
155		#define SKIP_WORD(T) ((T)->pc += (2 << 3))
156		#define SKIP_LONG(T) ((T)->pc += (4 << 3))
	108	#define SKIP_WORD() (m_pc += (2 << 3))
	109	#define SKIP_LONG() (m_pc += (4 << 3))
157	110	#define PARAM_K(O) (((O) >> 5) & 0x1f)
158	111	#define PARAM_N(O) ((O) & 0x1f)
159	112	#define PARAM_REL8(O) ((INT8)(O))
160	113
161	114	/* memory I/O */
162		#define WFIELD0(T,a,b) (*tms34010_wfield_functions[FW(T,0)])(T,a,b)
163		#define WFIELD1(T,a,b) (*tms34010_wfield_functions[FW(T,1)])(T,a,b)
164		#define RFIELD0(T,a) (*tms34010_rfield_functions[FWEX(T,0)])(T,a)
165		#define RFIELD1(T,a) (*tms34010_rfield_functions[FWEX(T,1)])(T,a)
166		#define WPIXEL(T,a,b) (*(T)->pixel_write)(T,a,b)
167		#define RPIXEL(T,a) (*(T)->pixel_read)(T,a)
	115	#define WFIELD0(a,b) (this->*s_wfield_functions[FW(0)])(a,b)
	116	#define WFIELD1(a,b) (this->*s_wfield_functions[FW(1)])(a,b)
	117	#define RFIELD0(a) (this->*s_rfield_functions[FWEX(0)])(a)
	118	#define RFIELD1(a) (this->*s_rfield_functions[FWEX(1)])(a)
	119	#define WPIXEL(a,b) (this->*m_pixel_write)(a,b)
	120	#define RPIXEL(a) (this->*m_pixel_read)(a)
168	121
169	122	/* Implied Operands */
170		#define SADDR(T) BREG(T,0)
171		#define SADDR_X(T) BREG_X(T,0)
172		#define SADDR_Y(T) BREG_Y(T,0)
173		#define SADDR_XY(T) BREG_XY(T,0)
174		#define SPTCH(T) BREG(T,1)
175		#define DADDR(T) BREG(T,2)
176		#define DADDR_X(T) BREG_X(T,2)
177		#define DADDR_Y(T) BREG_Y(T,2)
178		#define DADDR_XY(T) BREG_XY(T,2)
179		#define DPTCH(T) BREG(T,3)
180		#define OFFSET(T) BREG(T,4)
181		#define WSTART_X(T) BREG_X(T,5)
182		#define WSTART_Y(T) BREG_Y(T,5)
183		#define WEND_X(T) BREG_X(T,6)
184		#define WEND_Y(T) BREG_Y(T,6)
185		#define DYDX_X(T) BREG_X(T,7)
186		#define DYDX_Y(T) BREG_Y(T,7)
187		#define COLOR0(T) BREG(T,8)
188		#define COLOR1(T) BREG(T,9)
189		#define COUNT(T) BREG(T,10)
190		#define INC1_X(T) BREG_X(T,11)
191		#define INC1_Y(T) BREG_Y(T,11)
192		#define INC2_X(T) BREG_X(T,12)
193		#define INC2_Y(T) BREG_Y(T,12)
194		#define PATTRN(T) BREG(T,13)
195		#define TEMP(T) BREG(T,14)
	123	#define SADDR() BREG(0)
	124	#define SADDR_X() BREG_X(0)
	125	#define SADDR_Y() BREG_Y(0)
	126	#define SADDR_XY() BREG_XY(0)
	127	#define SPTCH() BREG(1)
	128	#define DADDR() BREG(2)
	129	#define DADDR_X() BREG_X(2)
	130	#define DADDR_Y() BREG_Y(2)
	131	#define DADDR_XY() BREG_XY(2)
	132	#define DPTCH() BREG(3)
	133	#define OFFSET() BREG(4)
	134	#define WSTART_X() BREG_X(5)
	135	#define WSTART_Y() BREG_Y(5)
	136	#define WEND_X() BREG_X(6)
	137	#define WEND_Y() BREG_Y(6)
	138	#define DYDX_X() BREG_X(7)
	139	#define DYDX_Y() BREG_Y(7)
	140	#define COLOR0() BREG(8)
	141	#define COLOR1() BREG(9)
	142	#define COUNT() BREG(10)
	143	#define INC1_X() BREG_X(11)
	144	#define INC1_Y() BREG_Y(11)
	145	#define INC2_X() BREG_X(12)
	146	#define INC2_Y() BREG_Y(12)
	147	#define PATTRN() BREG(13)
	148	#define TEMP() BREG(14)
196	149
197	150	/* I/O registers */
198		#define WINDOW_CHECKING(T) ((IOREG(T, REG_CONTROL) >> 6) & 0x03)
	151	#define WINDOW_CHECKING() ((IOREG(REG_CONTROL) >> 6) & 0x03)
199	152
200	153
201	154
r31176	r31177
204	157	***************************************************************************/
205	158
206	159	/* Break up Status Register into indiviual flags */
207		~~INLINE~~ void ~~SET_ST(~~tms34010_~~stat~~e *tms, UINT32 st)
	160	inline void tms340x0_device::SET_ST(UINT32 st)
208	161	{
209		tm~~s->~~st = st;
	162	m_st = st;
210	163	/* interrupts might have been enabled, check it */
211		check_interrupt(~~tms~~);
	164	check_interrupt();
212	165	}
213	166
214	167	/* Intialize Status to 0x0010 */
215		~~INLINE~~ void ~~RESET_ST(~~tms34010_~~stat~~e *tms)
	168	inline void tms340x0_device::RESET_ST()
216	169	{
217		SET_ST(~~tms,~~ 0x00000010);
	170	SET_ST(0x00000010);
218	171	}
219	172
220	173	/* shortcuts for reading opcodes */
221		~~INLINE~~ UINT32 ~~ROPCODE(~~tms34010_~~stat~~e *tms)
	174	inline UINT32 tms340x0_device::ROPCODE()
222	175	{
223		UINT32 pc = TOBYTE(tms->pc);
224		tms->pc += 2 << 3;
225		return tms->direct->read_decrypted_word(pc);
	176	UINT32 pc = TOBYTE(m_pc);
	177	m_pc += 2 << 3;
	178	return m_direct->read_decrypted_word(pc);
226	179	}
227	180
228		~~INLINE~~ INT16 PARAM_WORD(~~tms34010_state *tms~~)
	181	inline INT16 tms340x0_device::PARAM_WORD()
229	182	{
230		UINT32 pc = TOBYTE(tms->pc);
231		tms->pc += 2 << 3;
232		return tms->direct->read_raw_word(pc);
	183	UINT32 pc = TOBYTE(m_pc);
	184	m_pc += 2 << 3;
	185	return m_direct->read_raw_word(pc);
233	186	}
234	187
235		~~INLINE~~ INT32 PARAM_LONG(~~tms34010_state *tms~~)
	188	inline INT32 tms340x0_device::PARAM_LONG()
236	189	{
237		UINT32 pc = TOBYTE(tms->pc);
238		tms->pc += 4 << 3;
239		return (UINT16)tms->direct->read_raw_word(pc) \| (tms->direct->read_raw_word(pc + 2) << 16);
	190	UINT32 pc = TOBYTE(m_pc);
	191	m_pc += 4 << 3;
	192	return (UINT16)m_direct->read_raw_word(pc) \| (m_direct->read_raw_word(pc + 2) << 16);
240	193	}
241	194
242		~~INLINE~~ INT16 PARAM_WORD_NO_INC(~~tms34010_state *tms~~)
	195	inline INT16 tms340x0_device::PARAM_WORD_NO_INC()
243	196	{
244		return tm~~s->~~direct->read_raw_word(TOBYTE(tm~~s->~~pc));
	197	return m_direct->read_raw_word(TOBYTE(m_pc));
245	198	}
246	199
247		~~INLINE~~ INT32 PARAM_LONG_NO_INC(~~tms34010_state *tms~~)
	200	inline INT32 tms340x0_device::PARAM_LONG_NO_INC()
248	201	{
249		UINT32 pc = TOBYTE(tms->pc);
250		return (UINT16)tms->direct->read_raw_word(pc) \| (tms->direct->read_raw_word(pc + 2) << 16);
	202	UINT32 pc = TOBYTE(m_pc);
	203	return (UINT16)m_direct->read_raw_word(pc) \| (m_direct->read_raw_word(pc + 2) << 16);
251	204	}
252	205
253	206	/* read memory byte */
254		~~INLINE~~ UINT32 ~~RBYTE(~~tms34010_~~stat~~e *tms, offs_t offset)
	207	inline UINT32 tms340x0_device::RBYTE(offs_t offset)
255	208	{
256	209	UINT32 ret;
257		RFIELDMAC_8(~~tms~~);
	210	RFIELDMAC_8();
258	211	return ret;
259	212	}
260	213
261	214	/* write memory byte */
262		~~INLINE~~ void ~~WBYTE(~~tms34010_~~stat~~e *tms, offs_t offset, UINT32 data)
	215	inline void tms340x0_device::WBYTE(offs_t offset, UINT32 data)
263	216	{
264		WFIELDMAC_8(~~tms~~);
	217	WFIELDMAC_8();
265	218	}
266	219
267	220	/* read memory long */
268		~~INLINE~~ UINT32 ~~RLONG(~~tms34010_~~stat~~e *tms, offs_t offset)
	221	inline UINT32 tms340x0_device::RLONG(offs_t offset)
269	222	{
270		RFIELDMAC_32(~~tms~~);
	223	RFIELDMAC_32();
271	224	}
272	225
273	226	/* write memory long */
274		~~INLINE~~ void ~~WLONG(~~tms34010_~~stat~~e *tms, offs_t offset, UINT32 data)
	227	inline void tms340x0_device::WLONG(offs_t offset, UINT32 data)
275	228	{
276		WFIELDMAC_32(~~tms~~);
	229	WFIELDMAC_32();
277	230	}
278	231
279	232	/* pushes/pops a value from the stack */
280		~~INLINE~~ void ~~PUSH(~~tms34010_~~stat~~e *tms, UINT32 data)
	233	inline void tms340x0_device::PUSH(UINT32 data)
281	234	{
282		SP(tms) -= 0x20;
283		WLONG(tms, SP(tms), data);
	235	SP() -= 0x20;
	236	WLONG(SP(), data);
284	237	}
285	238
286		~~INLINE~~ INT32 ~~POP(~~tms34010_~~stat~~e *tms)
	239	inline INT32 tms340x0_device::POP()
287	240	{
288		INT32 ret = RLONG(tms, SP(tms));
289		SP(tms) += 0x20;
	241	INT32 ret = RLONG(SP());
	242	SP() += 0x20;
290	243	return ret;
291	244	}
292	245
r31176	r31177
296	249	PIXEL READS
297	250	***************************************************************************/
298	251
299		#define RP(T,m1,m2) \
	252	#define RP(m1,m2) \
300	253	/* TODO: Plane masking */ \
301		return (TMS34010_RDMEM_WORD(T~~, T~~OBYTE(offset & 0xfffffff0)) >> (offset & m1)) & m2;
	254	return (TMS34010_RDMEM_WORD(TOBYTE(offset & 0xfffffff0)) >> (offset & m1)) & m2;
302	255
303		static UINT32 read_pixel_1(tms34010_state *tms, offs_t offset) { RP(tms,0x0f,0x01) }
304		static UINT32 read_pixel_2(tms34010_state *tms, offs_t offset) { RP(tms,0x0e,0x03) }
305		static UINT32 read_pixel_4(tms34010_state *tms, offs_t offset) { RP(tms,0x0c,0x0f) }
306		static UINT32 read_pixel_8(tms34010_state *tms, offs_t offset) { RP(tms,0x08,0xff) }
307		static UINT32 read_pixel_16(tms34010_state *tms, offs_t offset)
	256	UINT32 tms340x0_device::read_pixel_1(offs_t offset) { RP(0x0f,0x01) }
	257	UINT32 tms340x0_device::read_pixel_2(offs_t offset) { RP(0x0e,0x03) }
	258	UINT32 tms340x0_device::read_pixel_4(offs_t offset) { RP(0x0c,0x0f) }
	259	UINT32 tms340x0_device::read_pixel_8(offs_t offset) { RP(0x08,0xff) }
	260	UINT32 tms340x0_device::read_pixel_16(offs_t offset)
308	261	{
309	262	/* TODO: Plane masking */
310		return TMS34010_RDMEM_WORD(~~tms,~~ TOBYTE(offset & 0xfffffff0));
	263	return TMS34010_RDMEM_WORD(TOBYTE(offset & 0xfffffff0));
311	264	}
312		~~static~~ UINT32 read_pixel_32(~~tms34010_state *tms,~~ offs_t offset)
	265	UINT32 tms340x0_device::read_pixel_32(offs_t offset)
313	266	{
314	267	/* TODO: Plane masking */
315		return TMS34010_RDMEM_DWORD(~~tms,~~ TOBYTE(offset & 0xffffffe0));
	268	return TMS34010_RDMEM_DWORD(TOBYTE(offset & 0xffffffe0));
316	269	}
317	270
318	271	/* Shift register read */
319		~~static~~ UINT32 read_pixel_shiftreg(~~tms34010_state *tms,~~ offs_t offset)
	272	UINT32 tms340x0_device::read_pixel_shiftreg(offs_t offset)
320	273	{
321		if (tms->config->to_shiftreg)
322		tms->config->to_shiftreg(*tms->program, offset, &tms->shiftreg[0]);
	274	if (m_config->to_shiftreg)
	275	m_config->to_shiftreg(*m_program, offset, &m_shiftreg[0]);
323	276	else
324		fatalerror("To ShiftReg function not set. PC = %08X\n", tms->pc);
325		return tms->shiftreg[0];
	277	fatalerror("To ShiftReg function not set. PC = %08X\n", m_pc);
	278	return m_shiftreg[0];
326	279	}
327	280
328	281
r31176	r31177
332	285	***************************************************************************/
333	286
334	287	/* No Raster Op + No Transparency */
335		#define WP(T,m1,m2) \
	288	#define WP(m1,m2) \
336	289	UINT32 a = TOBYTE(offset & 0xfffffff0); \
337		UINT32 pix = TMS34010_RDMEM_WORD(T,a); \
	290	UINT32 pix = TMS34010_RDMEM_WORD(a); \
338	291	UINT32 shiftcount = offset & m1; \
339	292	\
340	293	/* TODO: plane masking */ \
341	294	data &= m2; \
342	295	pix = (pix & ~(m2 << shiftcount)) \| (data << shiftcount); \
343		TMS34010_WRMEM_WORD(T, a, pix);
	296	TMS34010_WRMEM_WORD(a, pix);
	297
344	298	/* No Raster Op + Transparency */
345		#define WP_T(T,m1,m2) \
	299	#define WP_T(m1,m2) \
346	300	/* TODO: plane masking */ \
347	301	data &= m2; \
348	302	if (data) \
349	303	{ \
350	304	UINT32 a = TOBYTE(offset & 0xfffffff0); \
351		UINT32 pix = TMS34010_RDMEM_WORD(T,a); \
	305	UINT32 pix = TMS34010_RDMEM_WORD(a); \
352	306	UINT32 shiftcount = offset & m1; \
353	307	\
354	308	/* TODO: plane masking */ \
355	309	pix = (pix & ~(m2 << shiftcount)) \| (data << shiftcount); \
356		TMS34010_WRMEM_WORD(T, a, pix); \
	310	TMS34010_WRMEM_WORD(a, pix); \
357	311	}
358	312	/* Raster Op + No Transparency */
359		#define WP_R(T,m1,m2) \
	313	#define WP_R(m1,m2) \
360	314	UINT32 a = TOBYTE(offset & 0xfffffff0); \
361		UINT32 pix = TMS34010_RDMEM_WORD(T,a); \
	315	UINT32 pix = TMS34010_RDMEM_WORD(a); \
362	316	UINT32 shiftcount = offset & m1; \
363	317	\
364	318	/* TODO: plane masking */ \
365		data = (*(T)->raster_op)(~~tms,~~ data & m2, (pix >> shiftcount) & m2) & m2; \
	319	data = (this->*m_raster_op)(data & m2, (pix >> shiftcount) & m2) & m2; \
366	320	pix = (pix & ~(m2 << shiftcount)) \| (data << shiftcount); \
367		TMS34010_WRMEM_WORD(T, a, pix);
	321	TMS34010_WRMEM_WORD(a, pix);
	322
368	323	/* Raster Op + Transparency */
369		#define WP_R_T(T,m1,m2) \
	324	#define WP_R_T(m1,m2) \
370	325	UINT32 a = TOBYTE(offset & 0xfffffff0); \
371		UINT32 pix = TMS34010_RDMEM_WORD(T,a); \
	326	UINT32 pix = TMS34010_RDMEM_WORD(a); \
372	327	UINT32 shiftcount = offset & m1; \
373	328	\
374	329	/* TODO: plane masking */ \
375		data = (*(T)->raster_op)(~~tms,~~ data & m2, (pix >> shiftcount) & m2) & m2; \
	330	data = (this->*m_raster_op)(data & m2, (pix >> shiftcount) & m2) & m2; \
376	331	if (data) \
377	332	{ \
378	333	pix = (pix & ~(m2 << shiftcount)) \| (data << shiftcount); \
379		TMS34010_WRMEM_WORD(T, a, pix); \
	334	TMS34010_WRMEM_WORD(a, pix); \
380	335	}
381	336
382	337	/* No Raster Op + No Transparency */
383		static void write_pixel_1(tms34010_state *tms, offs_t offset, UINT32 data) { WP(tms, 0x0f, 0x01); }
384		static void write_pixel_2(tms34010_state *tms, offs_t offset, UINT32 data) { WP(tms, 0x0e, 0x03); }
385		static void write_pixel_4(tms34010_state *tms, offs_t offset, UINT32 data) { WP(tms, 0x0c, 0x0f); }
386		static void write_pixel_8(tms34010_state *tms, offs_t offset, UINT32 data) { WP(tms, 0x08, 0xff); }
387		static void write_pixel_16(tms34010_state *tms, offs_t offset, UINT32 data)
	338	void tms340x0_device::write_pixel_1(offs_t offset, UINT32 data) { WP(0x0f, 0x01); }
	339	void tms340x0_device::write_pixel_2(offs_t offset, UINT32 data) { WP(0x0e, 0x03); }
	340	void tms340x0_device::write_pixel_4(offs_t offset, UINT32 data) { WP(0x0c, 0x0f); }
	341	void tms340x0_device::write_pixel_8(offs_t offset, UINT32 data) { WP(0x08, 0xff); }
	342	void tms340x0_device::write_pixel_16(offs_t offset, UINT32 data)
388	343	{
389	344	/* TODO: plane masking */
390		TMS34010_WRMEM_WORD(~~tms,~~ TOBYTE(offset & 0xfffffff0), data);
	345	TMS34010_WRMEM_WORD(TOBYTE(offset & 0xfffffff0), data);
391	346	}
392		~~static~~ void write_pixel_32(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	347	void tms340x0_device::write_pixel_32(offs_t offset, UINT32 data)
393	348	{
394	349	/* TODO: plane masking */
395		TMS34010_WRMEM_WORD(~~tms,~~ TOBYTE(offset & 0xffffffe0), data);
	350	TMS34010_WRMEM_WORD(TOBYTE(offset & 0xffffffe0), data);
396	351	}
397	352
398	353	/* No Raster Op + Transparency */
399		static void write_pixel_t_1(tms34010_state *tms, offs_t offset, UINT32 data) { WP_T(tms, 0x0f, 0x01); }
400		static void write_pixel_t_2(tms34010_state *tms, offs_t offset, UINT32 data) { WP_T(tms, 0x0e, 0x03); }
401		static void write_pixel_t_4(tms34010_state *tms, offs_t offset, UINT32 data) { WP_T(tms, 0x0c, 0x0f); }
402		static void write_pixel_t_8(tms34010_state *tms, offs_t offset, UINT32 data) { WP_T(tms, 0x08, 0xff); }
403		static void write_pixel_t_16(tms34010_state *tms, offs_t offset, UINT32 data)
	354	void tms340x0_device::write_pixel_t_1(offs_t offset, UINT32 data) { WP_T(0x0f, 0x01); }
	355	void tms340x0_device::write_pixel_t_2(offs_t offset, UINT32 data) { WP_T(0x0e, 0x03); }
	356	void tms340x0_device::write_pixel_t_4(offs_t offset, UINT32 data) { WP_T(0x0c, 0x0f); }
	357	void tms340x0_device::write_pixel_t_8(offs_t offset, UINT32 data) { WP_T(0x08, 0xff); }
	358	void tms340x0_device::write_pixel_t_16(offs_t offset, UINT32 data)
404	359	{
405	360	/* TODO: plane masking */
406	361	if (data)
407		TMS34010_WRMEM_WORD(~~tms,~~ TOBYTE(offset & 0xfffffff0), data);
	362	TMS34010_WRMEM_WORD(TOBYTE(offset & 0xfffffff0), data);
408	363	}
409		~~static~~ void write_pixel_t_32(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	364	void tms340x0_device::write_pixel_t_32(offs_t offset, UINT32 data)
410	365	{
411	366	/* TODO: plane masking */
412	367	if (data)
413		TMS34010_WRMEM_DWORD(~~tms,~~ TOBYTE(offset & 0xffffffe0), data);
	368	TMS34010_WRMEM_DWORD(TOBYTE(offset & 0xffffffe0), data);
414	369	}
415	370
416	371	/* Raster Op + No Transparency */
417		static void write_pixel_r_1(tms34010_state *tms, offs_t offset, UINT32 data) { WP_R(tms, 0x0f, 0x01); }
418		static void write_pixel_r_2(tms34010_state *tms, offs_t offset, UINT32 data) { WP_R(tms, 0x0e, 0x03); }
419		static void write_pixel_r_4(tms34010_state *tms, offs_t offset, UINT32 data) { WP_R(tms, 0x0c, 0x0f); }
420		static void write_pixel_r_8(tms34010_state *tms, offs_t offset, UINT32 data) { WP_R(tms, 0x08, 0xff); }
421		static void write_pixel_r_16(tms34010_state *tms, offs_t offset, UINT32 data)
	372	void tms340x0_device::write_pixel_r_1(offs_t offset, UINT32 data) { WP_R(0x0f, 0x01); }
	373	void tms340x0_device::write_pixel_r_2(offs_t offset, UINT32 data) { WP_R(0x0e, 0x03); }
	374	void tms340x0_device::write_pixel_r_4(offs_t offset, UINT32 data) { WP_R(0x0c, 0x0f); }
	375	void tms340x0_device::write_pixel_r_8(offs_t offset, UINT32 data) { WP_R(0x08, 0xff); }
	376	void tms340x0_device::write_pixel_r_16(offs_t offset, UINT32 data)
422	377	{
423	378	/* TODO: plane masking */
424	379	UINT32 a = TOBYTE(offset & 0xfffffff0);
425		TMS34010_WRMEM_WORD(~~tms,~~ a, (*tms->raster_op)(~~tms,~~ data, TMS34010_RDMEM_WORD(~~tms,~~ a)));
	380	TMS34010_WRMEM_WORD(a, (this->*m_raster_op)(data, TMS34010_RDMEM_WORD(a)));
426	381	}
427		~~static~~ void write_pixel_r_32(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	382	void tms340x0_device::write_pixel_r_32(offs_t offset, UINT32 data)
428	383	{
429	384	/* TODO: plane masking */
430	385	UINT32 a = TOBYTE(offset & 0xffffffe0);
431		TMS34010_WRMEM_DWORD(~~tms,~~ a, (*tms->raster_op)(~~tms,~~ data, TMS34010_RDMEM_DWORD(~~tms,~~ a)));
	386	TMS34010_WRMEM_DWORD(a, (this->*m_raster_op)(data, TMS34010_RDMEM_DWORD(a)));
432	387	}
433	388
434	389	/* Raster Op + Transparency */
435		static void write_pixel_r_t_1(tms34010_state *tms, offs_t offset, UINT32 data) { WP_R_T(tms, 0x0f,0x01); }
436		static void write_pixel_r_t_2(tms34010_state *tms, offs_t offset, UINT32 data) { WP_R_T(tms, 0x0e,0x03); }
437		static void write_pixel_r_t_4(tms34010_state *tms, offs_t offset, UINT32 data) { WP_R_T(tms, 0x0c,0x0f); }
438		static void write_pixel_r_t_8(tms34010_state *tms, offs_t offset, UINT32 data) { WP_R_T(tms, 0x08,0xff); }
439		static void write_pixel_r_t_16(tms34010_state *tms, offs_t offset, UINT32 data)
	390	void tms340x0_device::write_pixel_r_t_1(offs_t offset, UINT32 data) { WP_R_T(0x0f,0x01); }
	391	void tms340x0_device::write_pixel_r_t_2(offs_t offset, UINT32 data) { WP_R_T(0x0e,0x03); }
	392	void tms340x0_device::write_pixel_r_t_4(offs_t offset, UINT32 data) { WP_R_T(0x0c,0x0f); }
	393	void tms340x0_device::write_pixel_r_t_8(offs_t offset, UINT32 data) { WP_R_T(0x08,0xff); }
	394	void tms340x0_device::write_pixel_r_t_16(offs_t offset, UINT32 data)
440	395	{
441	396	/* TODO: plane masking */
442	397	UINT32 a = TOBYTE(offset & 0xfffffff0);
443		data = (*tms->raster_op)(~~tms,~~ data, TMS34010_RDMEM_WORD(~~tms,~~ a));
	398	data = (this->*m_raster_op)(data, TMS34010_RDMEM_WORD(a));
444	399
445	400	if (data)
446		TMS34010_WRMEM_WORD(~~tms,~~ a, data);
	401	TMS34010_WRMEM_WORD(a, data);
447	402	}
448		~~static~~ void write_pixel_r_t_32(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	403	void tms340x0_device::write_pixel_r_t_32(offs_t offset, UINT32 data)
449	404	{
450	405	/* TODO: plane masking */
451	406	UINT32 a = TOBYTE(offset & 0xffffffe0);
452		data = (*tms->raster_op)(~~tms,~~ data, TMS34010_RDMEM_DWORD(~~tms,~~ a));
	407	data = (this->*m_raster_op)(data, TMS34010_RDMEM_DWORD(a));
453	408
454	409	if (data)
455		TMS34010_WRMEM_DWORD(~~tms,~~ a, data);
	410	TMS34010_WRMEM_DWORD(a, data);
456	411	}
457	412
458	413	/* Shift register write */
459		~~static~~ void write_pixel_shiftreg(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	414	void tms340x0_device::write_pixel_shiftreg(offs_t offset, UINT32 data)
460	415	{
461		if (tms->config->from_shiftreg)
462		tms->config->from_shiftreg(*tms->program, offset, &tms->shiftreg[0]);
	416	if (m_config->from_shiftreg)
	417	m_config->from_shiftreg(*m_program, offset, &m_shiftreg[0]);
463	418	else
464		fatalerror("From ShiftReg function not set. PC = %08X\n", tm~~s->~~pc);
	419	fatalerror("From ShiftReg function not set. PC = %08X\n", m_pc);
465	420	}
466	421
467	422
r31176	r31177
471	426	***************************************************************************/
472	427
473	428	/* Raster operations */
474		static UINT32 raster_op_1(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return newpix & oldpix; }
475		static UINT32 raster_op_2(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return newpix & ~oldpix; }
476		static UINT32 raster_op_3(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return 0; }
477		static UINT32 raster_op_4(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return newpix \| ~oldpix; }
478		static UINT32 raster_op_5(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return ~(newpix ^ oldpix); }
479		static UINT32 raster_op_6(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return ~oldpix; }
480		static UINT32 raster_op_7(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return ~(newpix \| oldpix); }
481		static UINT32 raster_op_8(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return newpix \| oldpix; }
482		static UINT32 raster_op_9(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return oldpix; }
483		static UINT32 raster_op_10(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return newpix ^ oldpix; }
484		static UINT32 raster_op_11(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return ~newpix & oldpix; }
485		static UINT32 raster_op_12(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return 0xffff; }
486		static UINT32 raster_op_13(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return ~newpix \| oldpix; }
487		static UINT32 raster_op_14(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return ~(newpix & oldpix); }
488		static UINT32 raster_op_15(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return ~newpix; }
489		static UINT32 raster_op_16(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return newpix + oldpix; }
490		static UINT32 raster_op_17(tms34010_state *tms, UINT32 newpix, UINT32 oldpix)
	429	UINT32 tms340x0_device::raster_op_1(UINT32 newpix, UINT32 oldpix) { return newpix & oldpix; }
	430	UINT32 tms340x0_device::raster_op_2(UINT32 newpix, UINT32 oldpix) { return newpix & ~oldpix; }
	431	UINT32 tms340x0_device::raster_op_3(UINT32 newpix, UINT32 oldpix) { return 0; }
	432	UINT32 tms340x0_device::raster_op_4(UINT32 newpix, UINT32 oldpix) { return newpix \| ~oldpix; }
	433	UINT32 tms340x0_device::raster_op_5(UINT32 newpix, UINT32 oldpix) { return ~(newpix ^ oldpix); }
	434	UINT32 tms340x0_device::raster_op_6(UINT32 newpix, UINT32 oldpix) { return ~oldpix; }
	435	UINT32 tms340x0_device::raster_op_7(UINT32 newpix, UINT32 oldpix) { return ~(newpix \| oldpix); }
	436	UINT32 tms340x0_device::raster_op_8(UINT32 newpix, UINT32 oldpix) { return newpix \| oldpix; }
	437	UINT32 tms340x0_device::raster_op_9(UINT32 newpix, UINT32 oldpix) { return oldpix; }
	438	UINT32 tms340x0_device::raster_op_10(UINT32 newpix, UINT32 oldpix) { return newpix ^ oldpix; }
	439	UINT32 tms340x0_device::raster_op_11(UINT32 newpix, UINT32 oldpix) { return ~newpix & oldpix; }
	440	UINT32 tms340x0_device::raster_op_12(UINT32 newpix, UINT32 oldpix) { return 0xffff; }
	441	UINT32 tms340x0_device::raster_op_13(UINT32 newpix, UINT32 oldpix) { return ~newpix \| oldpix; }
	442	UINT32 tms340x0_device::raster_op_14(UINT32 newpix, UINT32 oldpix) { return ~(newpix & oldpix); }
	443	UINT32 tms340x0_device::raster_op_15(UINT32 newpix, UINT32 oldpix) { return ~newpix; }
	444	UINT32 tms340x0_device::raster_op_16(UINT32 newpix, UINT32 oldpix) { return newpix + oldpix; }
	445	UINT32 tms340x0_device::raster_op_17(UINT32 newpix, UINT32 oldpix)
491	446	{
492		UINT32 max = (UINT32)0xffffffff >> (32 - IOREG(~~tms,~~ REG_PSIZE));
	447	UINT32 max = (UINT32)0xffffffff >> (32 - IOREG(REG_PSIZE));
493	448	UINT32 res = newpix + oldpix;
494	449	return (res > max) ? max : res;
495	450	}
496		static UINT32 raster_op_18(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return oldpix - newpix; }
497		static UINT32 raster_op_19(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return (oldpix > newpix) ? oldpix - newpix : 0; }
498		static UINT32 raster_op_20(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return (oldpix > newpix) ? oldpix : newpix; }
499		static UINT32 raster_op_21(tms34010_state *tms, UINT32 newpix, UINT32 oldpix) { return (oldpix > newpix) ? newpix : oldpix; }
	451	UINT32 tms340x0_device::raster_op_18(UINT32 newpix, UINT32 oldpix) { return oldpix - newpix; }
	452	UINT32 tms340x0_device::raster_op_19(UINT32 newpix, UINT32 oldpix) { return (oldpix > newpix) ? oldpix - newpix : 0; }
	453	UINT32 tms340x0_device::raster_op_20(UINT32 newpix, UINT32 oldpix) { return (oldpix > newpix) ? oldpix : newpix; }
	454	UINT32 tms340x0_device::raster_op_21(UINT32 newpix, UINT32 oldpix) { return (oldpix > newpix) ? newpix : oldpix; }
500	455
501	456
502	457
r31176	r31177
520	475	****************************************************************************/
521	476
522	477	/* Generate pending interrupts. */
523		~~static~~ void check_interrupt(~~tms34010_state *tms~~)
	478	void tms340x0_device::check_interrupt()
524	479	{
525	480	int vector = 0;
526	481	int irqline = -1;
527	482	int irq;
528	483
529	484	/* if we're not actively executing, skip it */
530		if (!tm~~s->~~executing)
	485	if (!m_executing)
531	486	return;
532	487
533	488	/* check for NMI first */
534		if (IOREG(~~tms,~~ REG_HSTCTLH) & 0x0100)
	489	if (IOREG(REG_HSTCTLH) & 0x0100)
535	490	{
536		LOG(("TMS34010 '%s' takes NMI\n", t~~ms->device->t~~ag()));
	491	LOG(("TMS34010 '%s' takes NMI\n", tag()));
537	492
538	493	/* ack the NMI */
539		IOREG(~~tms,~~ REG_HSTCTLH) &= ~0x0100;
	494	IOREG(REG_HSTCTLH) &= ~0x0100;
540	495
541	496	/* handle NMI mode bit */
542		if (!(IOREG(~~tms,~~ REG_HSTCTLH) & 0x0200))
	497	if (!(IOREG(REG_HSTCTLH) & 0x0200))
543	498	{
544		PUSH(tms, tms->pc);
545		PUSH(tms, tms->st);
	499	PUSH(m_pc);
	500	PUSH(m_st);
546	501	}
547	502
548	503	/* leap to the vector */
549		RESET_ST(tms);
550		tms->pc = RLONG(tms, 0xfffffee0);
551		COUNT_CYCLES(tms,16);
	504	RESET_ST();
	505	m_pc = RLONG(0xfffffee0);
	506	COUNT_CYCLES(16);
552	507	return;
553	508	}
554	509
555	510	/* early out if everything else is disabled */
556		irq = IOREG(tms, REG_INTPEND) & IOREG(tms, REG_INTENB);
557		if (!IE_FLAG(tms) \|\| !irq)
	511	irq = IOREG(REG_INTPEND) & IOREG(REG_INTENB);
	512	if (!IE_FLAG() \|\| !irq)
558	513	return;
559	514
560	515	/* host interrupt */
561	516	if (irq & TMS34010_HI)
562	517	{
563		LOG(("TMS34010 '%s' takes HI\n", t~~ms->device->t~~ag()));
	518	LOG(("TMS34010 '%s' takes HI\n", tag()));
564	519	vector = 0xfffffec0;
565	520	}
566	521
567	522	/* display interrupt */
568	523	else if (irq & TMS34010_DI)
569	524	{
570		LOG(("TMS34010 '%s' takes DI\n", t~~ms->device->t~~ag()));
	525	LOG(("TMS34010 '%s' takes DI\n", tag()));
571	526	vector = 0xfffffea0;
572	527	}
573	528
574	529	/* window violation interrupt */
575	530	else if (irq & TMS34010_WV)
576	531	{
577		LOG(("TMS34010 '%s' takes WV\n", t~~ms->device->t~~ag()));
	532	LOG(("TMS34010 '%s' takes WV\n", tag()));
578	533	vector = 0xfffffe80;
579	534	}
580	535
581	536	/* external 1 interrupt */
582	537	else if (irq & TMS34010_INT1)
583	538	{
584		LOG(("TMS34010 '%s' takes INT1\n", t~~ms->device->t~~ag()));
	539	LOG(("TMS34010 '%s' takes INT1\n", tag()));
585	540	vector = 0xffffffc0;
586	541	irqline = 0;
587	542	}
r31176	r31177
589	544	/* external 2 interrupt */
590	545	else if (irq & TMS34010_INT2)
591	546	{
592		LOG(("TMS34010 '%s' takes INT2\n", t~~ms->device->t~~ag()));
	547	LOG(("TMS34010 '%s' takes INT2\n", tag()));
593	548	vector = 0xffffffa0;
594	549	irqline = 1;
595	550	}
r31176	r31177
597	552	/* if we took something, generate it */
598	553	if (vector)
599	554	{
600		PUSH(tms, tms->pc);
601		PUSH(tms, tms->st);
602		RESET_ST(tms);
603		tms->pc = RLONG(tms, vector);
604		COUNT_CYCLES(tms,16);
	555	PUSH(m_pc);
	556	PUSH(m_st);
	557	RESET_ST();
	558	m_pc = RLONG(vector);
	559	COUNT_CYCLES(16);
605	560
606	561	/* call the callback for externals */
607	562	if (irqline >= 0)
608		~~(void)(tm~~s->irq_callback)(*tms->device, irqline);
	563	standard_irq_callback(irqline);
609	564	}
610	565	}
611	566
r31176	r31177
615	570	Reset the CPU emulation
616	571	***************************************************************************/
617	572
618		~~stat~~ic ~~CPU_INIT(~~ tms34010 )
	573	void tms340x0_device::device_start()
619	574	{
620		const tms34010_config configdata = device->static_config() ? (const tms34010_config )device->static_config() : &default_config;
621		tms34010_state *tms = get_safe_token(device);
	575	m_external_host_access = FALSE;
622	576
623		tms->external_host_access = FALSE;
	577	m_program = &space(AS_PROGRAM);
	578	m_direct = &m_program->direct();
	579	m_screen = downcast<screen_device *>(machine().device(m_config->screen_tag));
624	580
625		tms->config = configdata;
626		tms->irq_callback = irqcallback;
627		tms->device = device;
628		tms->program = &device->space(AS_PROGRAM);
629		tms->direct = &tms->program->direct();
630		tms->screen = downcast<screen_device *>(device->machine().device(configdata->screen_tag));
631
632	581	/* set up the state table */
633	582	{
634		device_state_interface *state;
635		device->interface(state);
636		state->state_add(TMS34010_PC, "PC", tms->pc);
637		state->state_add(STATE_GENPC, "GENPC", tms->pc).noshow();
638		state->state_add(STATE_GENPCBASE, "GENPCBASE", tms->ppc).noshow();
639		state->state_add(TMS34010_SP, "SP", tms->regs[15].reg);
640		state->state_add(STATE_GENSP, "GENSP", tms->regs[15].reg).noshow();
641		state->state_add(TMS34010_ST, "ST", tms->st);
642		state->state_add(STATE_GENFLAGS, "GENFLAGS", tms->st).noshow().formatstr("%18s");
	583	state_add(TMS34010_PC, "PC", m_pc);
	584	state_add(STATE_GENPC, "GENPC", m_pc).noshow();
	585	state_add(STATE_GENPCBASE, "GENPCBASE", m_ppc).noshow();
	586	state_add(TMS34010_SP, "SP", m_regs[15].reg);
	587	state_add(STATE_GENSP, "GENSP", m_regs[15].reg).noshow();
	588	state_add(TMS34010_ST, "ST", m_st);
	589	state_add(STATE_GENFLAGS, "GENFLAGS", m_st).noshow().formatstr("%18s");
643	590
644	591	astring tempstr;
645	592	for (int regnum = 0; regnum < 15; regnum++)
646		state->state_add(TMS34010_A0 + regnum, tempstr.format("A%d", regnum), tms->regs[regnum].reg);
	593	{
	594	state_add(TMS34010_A0 + regnum, tempstr.format("A%d", regnum), m_regs[regnum].reg);
	595	}
647	596	for (int regnum = 0; regnum < 15; regnum++)
648		state->state_add(TMS34010_B0 + regnum, tempstr.format("B%d", regnum), tms->regs[30 - regnum].reg);
	597	{
	598	state_add(TMS34010_B0 + regnum, tempstr.format("B%d", regnum), m_regs[30 - regnum].reg);
	599	}
649	600	}
650	601
651	602	/* allocate a scanline timer and set it to go off at the start */
652		tms->scantimer = device->machine().scheduler().timer_alloc(FUNC(scanline_callback), tms);
653		tms->scantimer->adjust(attotime::zero);
	603	m_scantimer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(tms340x0_device::scanline_callback), this));
	604	m_scantimer->adjust(attotime::zero);
654	605
655		device->save_item(NAME(tms->pc));
656		device->save_item(NAME(tms->st));
657		device->save_item(NAME(tms->reset_deferred));
658		device->save_item(NAME(tms->shiftreg));
659		device->save_item(NAME(tms->IOregs));
660		device->save_item(NAME(tms->convsp));
661		device->save_item(NAME(tms->convdp));
662		device->save_item(NAME(tms->convmp));
663		device->save_item(NAME(tms->pixelshift));
664		device->save_item(NAME(tms->gfxcycles));
665		device->save_pointer(NAME(&tms->regs[0].reg), ARRAY_LENGTH(tms->regs));
666		device->machine().save().register_postload(save_prepost_delegate(FUNC(tms34010_state_postload), tms));
	606	save_item(NAME(m_pc));
	607	save_item(NAME(m_st));
	608	save_item(NAME(m_reset_deferred));
	609	save_item(NAME(m_shiftreg));
	610	save_item(NAME(m_IOregs));
	611	save_item(NAME(m_convsp));
	612	save_item(NAME(m_convdp));
	613	save_item(NAME(m_convmp));
	614	save_item(NAME(m_pixelshift));
	615	save_item(NAME(m_gfxcycles));
	616	save_pointer(NAME(&m_regs[0].reg), ARRAY_LENGTH(m_regs));
	617	machine().save().register_postload(save_prepost_delegate(FUNC(tms340x0_device::tms34010_state_postload), this));
	618
	619	m_icountptr = &m_icount;
667	620	}
668	621
669		~~stat~~ic ~~CPU_RESET(~~ tms34010 )
	622	void tms340x0_device::device_reset()
670	623	{
671		/* zap the state and copy in the config pointer */
672		tms34010_state *tms = get_safe_token(device);
673		const tms34010_config *config = tms->config;
674		screen_device *screen = tms->screen;
675		device_irq_acknowledge_delegate save_irqcallback = tms->irq_callback;
676		emu_timer *save_scantimer = tms->scantimer;
	624	m_ppc = 0;
	625	m_st = 0;
	626	m_pixel_write = NULL;
	627	m_pixel_read = NULL;
	628	m_raster_op = NULL;
	629	m_pixel_op = NULL;
	630	m_pixel_op_timing = 0;
	631	m_convsp = 0;
	632	m_convdp = 0;
	633	m_convmp = 0;
	634	m_gfxcycles = 0;
	635	m_pixelshift = 0;
	636	m_hblank_stable = 0;
	637	m_external_host_access = 0;
	638	m_executing = 0;
	639	memset(m_regs, 0, sizeof(m_regs));
	640	memset(m_IOregs, 0, sizeof(m_IOregs));
	641	memset(m_shiftreg, 0, sizeof(m_shiftreg));
677	642
678		memset(tms, 0, sizeof(*tms));
679
680		tms->config = config;
681		tms->screen = screen;
682		tms->irq_callback = save_irqcallback;
683		tms->scantimer = save_scantimer;
684		tms->device = device;
685		tms->program = &device->space(AS_PROGRAM);
686		tms->direct = &tms->program->direct();
687
688	643	/* fetch the initial PC and reset the state */
689		tms->pc = RLONG(tms, 0xffffffe0) & 0xfffffff0;
690		RESET_ST(tms);
	644	m_pc = RLONG(0xffffffe0) & 0xfffffff0;
	645	RESET_ST();
691	646
692	647	/* HALT the CPU if requested, and remember to re-read the starting PC */
693	648	/* the first time we are run */
694		tms->reset_deferred = tms->config->halt_on_reset;
695		if (tms->config->halt_on_reset)
696		(downcast<tms34010_device*>(device))->io_register_w(device->space(AS_PROGRAM), REG_HSTCTLH, 0x8000, 0xffff);
	649	m_reset_deferred = m_config->halt_on_reset;
	650	if (m_config->halt_on_reset)
	651	{
	652	io_register_w(*m_program, REG_HSTCTLH, 0x8000, 0xffff);
	653	}
697	654	}
698	655
699	656
700		static CPU_RESET( tms34020 )
701		{
702		tms34010_state *tms = get_safe_token(device);
703		CPU_RESET_CALL(tms34010);
704		tms->is_34020 = 1;
705		}
706
707
708
709	657	/***************************************************************************
710		Shut down the CPU emulation
711		***************************************************************************/
712
713		static CPU_EXIT( tms34010 )
714		{
715		}
716
717
718
719		/***************************************************************************
720	658	Set IRQ line state
721	659	***************************************************************************/
722	660
723		~~static~~ void set~~_irq_line(t~~ms34010_~~stat~~e *tms, int i~~rqli~~ne, int linestate)
	661	void tms340x0_device::execute_set_input(int inputnum, int state)
724	662	{
725		LOG(("TMS34010 '%s' set irq line %d state %d\n", t~~ms->device->t~~ag(), i~~rqli~~ne, ~~line~~state));
	663	LOG(("TMS34010 '%s' set irq line %d state %d\n", tag(), inputnum, state));
726	664
727	665	/* set the pending interrupt */
728		switch (i~~rqli~~ne)
	666	switch (inputnum)
729	667	{
730	668	case 0:
731		if (linestate != CLEAR_LINE)
732		IOREG(tms, REG_INTPEND) \|= TMS34010_INT1;
	669	if (state != CLEAR_LINE)
	670	IOREG(REG_INTPEND) \|= TMS34010_INT1;
733	671	else
734		IOREG(~~tms,~~ REG_INTPEND) &= ~TMS34010_INT1;
	672	IOREG(REG_INTPEND) &= ~TMS34010_INT1;
735	673	break;
736	674
737	675	case 1:
738		if (linestate != CLEAR_LINE)
739		IOREG(tms, REG_INTPEND) \|= TMS34010_INT2;
	676	if (state != CLEAR_LINE)
	677	IOREG(REG_INTPEND) \|= TMS34010_INT2;
740	678	else
741		IOREG(~~tms,~~ REG_INTPEND) &= ~TMS34010_INT2;
	679	IOREG(REG_INTPEND) &= ~TMS34010_INT2;
742	680	break;
743	681	}
744	682	}
r31176	r31177
749	687	Generate internal interrupt
750	688	***************************************************************************/
751	689
752		~~static~~ TIMER_CALLBACK( internal_interrupt_callback )
	690	TIMER_CALLBACK_MEMBER( tms340x0_device::internal_interrupt_callback )
753	691	{
754		tms34010_state tms = (tms34010_state )ptr;
755	692	int type = param;
756	693
757	694	/* call through to the CPU to generate the int */
758		IOREG(tms, REG_INTPEND) \|= type;
759		LOG(("TMS34010 '%s' set internal interrupt $%04x\n", tms->device->tag(), type));
	695	IOREG(REG_INTPEND) \|= type;
	696	LOG(("TMS34010 '%s' set internal interrupt $%04x\n", tag(), type));
760	697
761	698	/* generate triggers so that spin loops can key off them */
762		~~tms->device->~~signal_interrupt_trigger();
	699	signal_interrupt_trigger();
763	700	}
764	701
765	702
r31176	r31177
768	705	Execute
769	706	***************************************************************************/
770	707
771		~~stat~~ic ~~CPU_EXECUTE(~~ tms34010 )
	708	void tms340x0_device::execute_run()
772	709	{
773		tms34010_state *tms = get_safe_token(device);
774
775	710	/* Get out if CPU is halted. Absolutely no interrupts must be taken!!! */
776		if (IOREG(~~tms,~~ REG_HSTCTLH) & 0x8000)
	711	if (IOREG(REG_HSTCTLH) & 0x8000)
777	712	{
778		tm~~s->~~icount = 0;
	713	m_icount = 0;
779	714	return;
780	715	}
781	716
782	717	/* if the CPU's reset was deferred, do it now */
783		if (tm~~s->~~reset_deferred)
	718	if (m_reset_deferred)
784	719	{
785		tms->reset_deferred = 0;
786		tms->pc = RLONG(tms, 0xffffffe0);
	720	m_reset_deferred = 0;
	721	m_pc = RLONG(0xffffffe0);
787	722	}
788	723
789	724	/* check interrupts first */
790		tms->executing = TRUE;
791		check_interrupt(tms);
792		if ((tms->device->machine().debug_flags & DEBUG_FLAG_ENABLED) == 0)
	725	m_executing = TRUE;
	726	check_interrupt();
	727	if ((machine().debug_flags & DEBUG_FLAG_ENABLED) == 0)
793	728	{
794	729	do
795	730	{
796	731	UINT16 op;
797		tms->ppc = tms->pc;
798		op = ROPCODE(tms);
799		(*opcode_table[op >> 4])(tms, op);
800		} while (tms->icount > 0);
	732	m_ppc = m_pc;
	733	op = ROPCODE();
	734	(this->*s_opcode_table[op >> 4])(op);
	735	} while (m_icount > 0);
801	736	}
802	737	else
803	738	{
804	739	do
805	740	{
806	741	UINT16 op;
807		debugger_instruction_hook(tms->device, tms->pc);
808		tms->ppc = tms->pc;
809		op = ROPCODE(tms);
810		(*opcode_table[op >> 4])(tms, op);
811		} while (tms->icount > 0);
	742	debugger_instruction_hook(this, m_pc);
	743	m_ppc = m_pc;
	744	op = ROPCODE();
	745	(this->*s_opcode_table[op >> 4])(op);
	746	} while (m_icount > 0);
812	747	}
813		tm~~s->~~executing = FALSE;
	748	m_executing = FALSE;
814	749	}
815	750
816	751
r31176	r31177
819	754	PIXEL OPS
820	755	***************************************************************************/
821	756
822		~~stati~~c vo~~id (co~~nst pixel_write_~~ops[4][6])(~~tms34010_~~stat~~e tms~~, offs~~_t offs~~et, UINT32 data)~~ =
	757	const tms340x0_device::pixel_write_func tms340x0_device::s_pixel_write_ops[4][6] =
823	758	{
824		{ write_pixel_1, write_pixel_2, write_pixel_4, write_pixel_8, write_pixel_16, write_pixel_32 },
825		{ write_pixel_r_1, write_pixel_r_2, write_pixel_r_4, write_pixel_r_8, write_pixel_r_16, write_pixel_r_32 },
826		{ write_pixel_t_1, write_pixel_t_2, write_pixel_t_4, write_pixel_t_8, write_pixel_t_16, write_pixel_t_32 },
827		{ write_pixel_r_t_1, write_pixel_r_t_2, write_pixel_r_t_4, write_pixel_r_t_8, write_pixel_r_t_16, write_pixel_r_t_32 }
	759	{ &tms340x0_device::write_pixel_1, &tms340x0_device::write_pixel_2, &tms340x0_device::write_pixel_4, &tms340x0_device::write_pixel_8, &tms340x0_device::write_pixel_16, &tms340x0_device::write_pixel_32 },
	760	{ &tms340x0_device::write_pixel_r_1, &tms340x0_device::write_pixel_r_2, &tms340x0_device::write_pixel_r_4, &tms340x0_device::write_pixel_r_8, &tms340x0_device::write_pixel_r_16, &tms340x0_device::write_pixel_r_32 },
	761	{ &tms340x0_device::write_pixel_t_1, &tms340x0_device::write_pixel_t_2, &tms340x0_device::write_pixel_t_4, &tms340x0_device::write_pixel_t_8, &tms340x0_device::write_pixel_t_16, &tms340x0_device::write_pixel_t_32 },
	762	{ &tms340x0_device::write_pixel_r_t_1, &tms340x0_device::write_pixel_r_t_2, &tms340x0_device::write_pixel_r_t_4, &tms340x0_device::write_pixel_r_t_8, &tms340x0_device::write_pixel_r_t_16, &tms340x0_device::write_pixel_r_t_32 }
828	763	};
829	764
830		~~stati~~c ~~UINT32 (c~~onst pixel_read_~~ops[6])(~~tms34010_~~stat~~e tms~~, offs~~_t offs~~et)~~ =
	765	const tms340x0_device::pixel_read_func tms340x0_device::s_pixel_read_ops[6] =
831	766	{
832		read_pixel_1, read_pixel_2, read_pixel_4, read_pixel_8, read_pixel_16, read_pixel_32
	767	&tms340x0_device::read_pixel_1, &tms340x0_device::read_pixel_2, &tms340x0_device::read_pixel_4, &tms340x0_device::read_pixel_8, &tms340x0_device::read_pixel_16, &tms340x0_device::read_pixel_32
833	768	};
834	769
835	770
836		~~static~~ void set_pixel_function(~~tms34010_state *tms~~)
	771	void tms340x0_device::set_pixel_function()
837	772	{
838	773	UINT32 i1,i2;
839	774
840		if (IOREG(~~tms,~~ REG_DPYCTL) & 0x0800)
	775	if (IOREG(REG_DPYCTL) & 0x0800)
841	776	{
842	777	/* Shift Register Transfer */
843		tms->pixel_write = write_pixel_shiftreg;
844		tms->pixel_read = read_pixel_shiftreg;
	778	m_pixel_write = &tms340x0_device::write_pixel_shiftreg;
	779	m_pixel_read = &tms340x0_device::read_pixel_shiftreg;
845	780	return;
846	781	}
847	782
848		switch (IOREG(~~tms,~~ REG_PSIZE))
	783	switch (IOREG(REG_PSIZE))
849	784	{
850	785	default:
851	786	case 0x01: i2 = 0; break;
r31176	r31177
856	791	case 0x20: i2 = 5; break;
857	792	}
858	793
859		if (IOREG(tms, REG_CONTROL) & 0x20)
860		i1 = tms->raster_op ? 3 : 2;
	794	if (IOREG(REG_CONTROL) & 0x20)
	795	i1 = m_raster_op ? 3 : 2;
861	796	else
862		i1 = tm~~s->~~raster_op ? 1 : 0;
	797	i1 = m_raster_op ? 1 : 0;
863	798
864		tms->pixel_write = pixel_write_ops[i1][i2];
865		tms->pixel_read = pixel_read_ops [i2];
	799	m_pixel_write = s_pixel_write_ops[i1][i2];
	800	m_pixel_read = s_pixel_read_ops [i2];
866	801	}
867	802
868	803
r31176	r31177
871	806	RASTER OPS
872	807	***************************************************************************/
873	808
874		~~stati~~c ~~UINT32 (c~~onst raster_op~~s[32])~~ (tms34010_state tms~~, UINT~~32 ~~newpix, UINT32 oldpix)~~ =
	809	const tms340x0_device::raster_op_func tms340x0_device::s_raster_ops[32] =
875	810	{
876		0, raster_op_1 , raster_op_2 , raster_op_3,
877		raster_op_4 , raster_op_5 , raster_op_6 , raster_op_7,
878		raster_op_8 , raster_op_9 , raster_op_10, raster_op_11,
879		raster_op_12, raster_op_13, raster_op_14, raster_op_15,
880		raster_op_16, raster_op_17, raster_op_18, raster_op_19,
881		raster_op_20, raster_op_21, 0, 0,
882		0, 0, 0, 0,
883		0, 0, 0, 0,
	811	NULL, &tms340x0_device::raster_op_1 , &tms340x0_device::raster_op_2 , &tms340x0_device::raster_op_3,
	812	&tms340x0_device::raster_op_4 , &tms340x0_device::raster_op_5 , &tms340x0_device::raster_op_6 , &tms340x0_device::raster_op_7,
	813	&tms340x0_device::raster_op_8 , &tms340x0_device::raster_op_9 , &tms340x0_device::raster_op_10, &tms340x0_device::raster_op_11,
	814	&tms340x0_device::raster_op_12, &tms340x0_device::raster_op_13, &tms340x0_device::raster_op_14, &tms340x0_device::raster_op_15,
	815	&tms340x0_device::raster_op_16, &tms340x0_device::raster_op_17, &tms340x0_device::raster_op_18, &tms340x0_device::raster_op_19,
	816	&tms340x0_device::raster_op_20, &tms340x0_device::raster_op_21, NULL, NULL,
	817	NULL, NULL, NULL, NULL,
	818	NULL, NULL, NULL, NULL,
884	819	};
885	820
886	821
887		~~static~~ void set_raster_op(~~tms34010_state *tms~~)
	822	void tms340x0_device::set_raster_op()
888	823	{
889		tm~~s->~~raster_op = raster_ops[(IOREG(~~tms,~~ REG_CONTROL) >> 10) & 0x1f];
	824	m_raster_op = s_raster_ops[(IOREG(REG_CONTROL) >> 10) & 0x1f];
890	825	}
891	826
892	827
r31176	r31177
895	830	VIDEO TIMING HELPERS
896	831	***************************************************************************/
897	832
898		~~static~~ TIMER_CALLBACK( scanline_callback )
	833	TIMER_CALLBACK_MEMBER( tms340x0_device::scanline_callback )
899	834	{
900		tms34010_state tms = (tms34010_state )ptr;
901	835	int vsblnk, veblnk, vtotal;
902	836	int vcount = param;
903	837	int enabled;
904	838	int master;
905	839
906	840	/* fetch the core timing parameters */
907		const rectangle &current_visarea = tms->screen->visible_area();
908		enabled = SMART_IOREG(tms, DPYCTL) & 0x8000;
909		master = (tms->is_34020 \|\| (SMART_IOREG(tms, DPYCTL) & 0x2000));
910		vsblnk = SMART_IOREG(tms, VSBLNK);
911		veblnk = SMART_IOREG(tms, VEBLNK);
912		vtotal = SMART_IOREG(tms, VTOTAL);
	841	const rectangle &current_visarea = m_screen->visible_area();
	842	enabled = SMART_IOREG(DPYCTL) & 0x8000;
	843	master = (m_is_34020 \|\| (SMART_IOREG(DPYCTL) & 0x2000));
	844	vsblnk = SMART_IOREG(VSBLNK);
	845	veblnk = SMART_IOREG(VEBLNK);
	846	vtotal = SMART_IOREG(VTOTAL);
913	847	if (!master)
914	848	{
915		vtotal = MIN(tms->screen->height() - 1, vtotal);
916		vcount = tms->screen->vpos();
	849	vtotal = MIN(m_screen->height() - 1, vtotal);
	850	vcount = m_screen->vpos();
917	851	}
918	852
919	853	/* update the VCOUNT */
920		SMART_IOREG(~~tms,~~ VCOUNT) = vcount;
	854	SMART_IOREG(VCOUNT) = vcount;
921	855
922	856	/* if we match the display interrupt scanline, signal an interrupt */
923		if (enabled && vcount == SMART_IOREG(~~tms,~~ DPYINT))
	857	if (enabled && vcount == SMART_IOREG(DPYINT))
924	858	{
925	859	/* generate the display interrupt signal */
926		internal_interrupt_callback(~~machine, tms~~, TMS34010_DI);
	860	internal_interrupt_callback(NULL, TMS34010_DI);
927	861	}
928	862
929	863	/* at the start of VBLANK, load the starting display address */
930	864	if (vcount == vsblnk)
931	865	{
932	866	/* 34010 loads DPYADR with DPYSTRT, and inverts if the origin is 0 */
933		if (!tm~~s->~~is_34020)
	867	if (!m_is_34020)
934	868	{
935		IOREG(tms, REG_DPYADR) = IOREG(tms, REG_DPYSTRT);
936		LOG(("Start of VBLANK, DPYADR = %04X\n", IOREG(tms, REG_DPYADR)));
	869	IOREG(REG_DPYADR) = IOREG(REG_DPYSTRT);
	870	LOG(("Start of VBLANK, DPYADR = %04X\n", IOREG(REG_DPYADR)));
937	871	}
938	872
939	873	/* 34020 loads DPYNXx with DPYSTx */
940	874	else
941	875	{
942		IOREG(tms, REG020_DPYNXL) = IOREG(tms, REG020_DPYSTL) & 0xffe0;
943		IOREG(tms, REG020_DPYNXH) = IOREG(tms, REG020_DPYSTH);
	876	IOREG(REG020_DPYNXL) = IOREG(REG020_DPYSTL) & 0xffe0;
	877	IOREG(REG020_DPYNXH) = IOREG(REG020_DPYSTH);
944	878	}
945	879	}
946	880
r31176	r31177
949	883	{
950	884	/* only do this if we have an incoming pixel clock */
951	885	/* also, only do it if the HEBLNK/HSBLNK values are stable */
952		if (master && (tm~~s->~~config->scanline_callback_ind16 != NULL \|\| tm~~s->~~config->scanline_callback_rgb32 != NULL))
	886	if (master && (m_config->scanline_callback_ind16 != NULL \|\| m_config->scanline_callback_rgb32 != NULL))
953	887	{
954		int htotal = SMART_IOREG(~~tms,~~ HTOTAL);
	888	int htotal = SMART_IOREG(HTOTAL);
955	889	if (htotal > 0 && vtotal > 0)
956	890	{
957		attoseconds_t refresh = HZ_TO_ATTOSECONDS(tms->config->pixclock) * (htotal + 1) * (vtotal + 1);
958		int width = (htotal + 1) * tms->config->pixperclock;
	891	attoseconds_t refresh = HZ_TO_ATTOSECONDS(m_config->pixclock) * (htotal + 1) * (vtotal + 1);
	892	int width = (htotal + 1) * m_config->pixperclock;
959	893	int height = vtotal + 1;
960	894	rectangle visarea;
961	895
962	896	/* extract the visible area */
963		visarea.min_x = SMART_IOREG(tms, HEBLNK) * tms->config->pixperclock;
964		visarea.max_x = SMART_IOREG(tms, HSBLNK) * tms->config->pixperclock - 1;
	897	visarea.min_x = SMART_IOREG(HEBLNK) * m_config->pixperclock;
	898	visarea.max_x = SMART_IOREG(HSBLNK) * m_config->pixperclock - 1;
965	899	visarea.min_y = veblnk;
966	900	visarea.max_y = vsblnk - 1;
967	901
r31176	r31177
971	905	/* because many games play with the HEBLNK/HSBLNK for effects, we don't change
972	906	if they are the only thing that has changed, unless they are stable for a couple
973	907	of frames */
974		int current_width = tms->screen->width();
975		int current_height = tms->screen->height();
	908	int current_width = m_screen->width();
	909	int current_height = m_screen->height();
976	910
977	911	if (width != current_width \|\| height != current_height \|\| visarea.min_y != current_visarea.min_y \|\| visarea.max_y != current_visarea.max_y \|\|
978		(tm~~s->~~hblank_stable > 2 && (visarea.min_x != current_visarea.min_x \|\| visarea.max_x != current_visarea.max_x)))
	912	(m_hblank_stable > 2 && (visarea.min_x != current_visarea.min_x \|\| visarea.max_x != current_visarea.max_x)))
979	913	{
980		tm~~s->~~screen->configure(width, height, visarea, refresh);
	914	m_screen->configure(width, height, visarea, refresh);
981	915	}
982		tm~~s->~~hblank_stable++;
	916	m_hblank_stable++;
983	917	}
984	918
985	919	LOG(("Configuring screen: HTOTAL=%3d BLANK=%3d-%3d VTOTAL=%3d BLANK=%3d-%3d refresh=%f\n",
986		htotal, SMART_IOREG(~~tms,~~ HEBLNK), SMART_IOREG(~~tms,~~ HSBLNK), vtotal, veblnk, vsblnk, ATTOSECONDS_TO_HZ(refresh)));
	920	htotal, SMART_IOREG(HEBLNK), SMART_IOREG(HSBLNK), vtotal, veblnk, vsblnk, ATTOSECONDS_TO_HZ(refresh)));
987	921
988	922	/* interlaced timing not supported */
989		if ((SMART_IOREG(~~tms,~~ DPYCTL) & 0x4000) == 0)
	923	if ((SMART_IOREG(DPYCTL) & 0x4000) == 0)
990	924	fatalerror("Interlaced video configured on the TMS34010 (unsupported)\n");
991	925	}
992	926	}
993	927	}
994	928
995	929	/* force a partial update within the visible area */
996		if (vcount >= current_visarea.min_y && vcount <= current_visarea.max_y && (tms->config->scanline_callback_ind16 != NULL \|\| tms->config->scanline_callback_rgb32 != NULL))
997		tms->screen->update_partial(vcount);
	930	if (vcount >= current_visarea.min_y && vcount <= current_visarea.max_y && (m_config->scanline_callback_ind16 != NULL \|\| m_config->scanline_callback_rgb32 != NULL))
	931	m_screen->update_partial(vcount);
998	932
999	933	/* if we are in the visible area, increment DPYADR by DUDATE */
1000	934	if (vcount >= veblnk && vcount < vsblnk)
1001	935	{
1002	936	/* 34010 increments by the DUDATE field in DPYCTL */
1003		if (!tm~~s->~~is_34020)
	937	if (!m_is_34020)
1004	938	{
1005		UINT16 dpyadr = IOREG(~~tms,~~ REG_DPYADR);
	939	UINT16 dpyadr = IOREG(REG_DPYADR);
1006	940	if ((dpyadr & 3) == 0)
1007		dpyadr = ((dpyadr & 0xfffc) - (IOREG(~~tms,~~ REG_DPYCTL) & 0x03fc)) \| (IOREG(~~tms,~~ REG_DPYSTRT) & 0x0003);
	941	dpyadr = ((dpyadr & 0xfffc) - (IOREG(REG_DPYCTL) & 0x03fc)) \| (IOREG(REG_DPYSTRT) & 0x0003);
1008	942	else
1009	943	dpyadr = (dpyadr & 0xfffc) \| ((dpyadr - 1) & 3);
1010		IOREG(~~tms,~~ REG_DPYADR) = dpyadr;
	944	IOREG(REG_DPYADR) = dpyadr;
1011	945	}
1012	946
1013	947	/* 34020 updates based on the DINC register, including zoom */
1014	948	else
1015	949	{
1016		UINT32 dpynx = IOREG(tms, REG020_DPYNXL) \| (IOREG(tms, REG020_DPYNXH) << 16);
1017		UINT32 dinc = IOREG(tms, REG020_DINCL) \| (IOREG(tms, REG020_DINCH) << 16);
	950	UINT32 dpynx = IOREG(REG020_DPYNXL) \| (IOREG(REG020_DPYNXH) << 16);
	951	UINT32 dinc = IOREG(REG020_DINCL) \| (IOREG(REG020_DINCH) << 16);
1018	952	dpynx = (dpynx & 0xffffffe0) \| ((dpynx + dinc) & 0x1f);
1019	953	if ((dpynx & 0x1f) == 0)
1020	954	dpynx += dinc & 0xffffffe0;
1021		IOREG(tms, REG020_DPYNXL) = dpynx;
1022		IOREG(tms, REG020_DPYNXH) = dpynx >> 16;
	955	IOREG(REG020_DPYNXL) = dpynx;
	956	IOREG(REG020_DPYNXH) = dpynx >> 16;
1023	957	}
1024	958	}
1025	959
r31176	r31177
1030	964
1031	965	/* note that we add !master (0 or 1) as a attoseconds value; this makes no practical difference */
1032	966	/* but helps ensure that masters are updated first before slaves */
1033		tms~~->s~~cantimer->adjust(tm~~s->~~screen->time_until_pos(vcount) + attotime(0, !master), vcount);
	967	m_scantimer->adjust(m_screen->time_until_pos(vcount) + attotime(0, !master), vcount);
1034	968	}
1035	969
1036	970
1037		void tms34010_get_display_params(~~device_t cpu,~~ tms34010_display_params params)
	971	void tms340x0_device::get_display_params(tms34010_display_params *params)
1038	972	{
1039		tms34010_state *tms = get_safe_token(cpu);
	973	params->enabled = ((SMART_IOREG(DPYCTL) & 0x8000) != 0);
	974	params->vcount = SMART_IOREG(VCOUNT);
	975	params->veblnk = SMART_IOREG(VEBLNK);
	976	params->vsblnk = SMART_IOREG(VSBLNK);
	977	params->heblnk = SMART_IOREG(HEBLNK) * m_config->pixperclock;
	978	params->hsblnk = SMART_IOREG(HSBLNK) * m_config->pixperclock;
1040	979
1041		params->enabled = ((SMART_IOREG(tms, DPYCTL) & 0x8000) != 0);
1042		params->vcount = SMART_IOREG(tms, VCOUNT);
1043		params->veblnk = SMART_IOREG(tms, VEBLNK);
1044		params->vsblnk = SMART_IOREG(tms, VSBLNK);
1045		params->heblnk = SMART_IOREG(tms, HEBLNK) * tms->config->pixperclock;
1046		params->hsblnk = SMART_IOREG(tms, HSBLNK) * tms->config->pixperclock;
1047
1048	980	/* 34010 gets its address from DPYADR and DPYTAP */
1049		if (!tm~~s->~~is_34020)
	981	if (!m_is_34020)
1050	982	{
1051		UINT16 dpyadr = IOREG(tms, REG_DPYADR);
1052		if (!(IOREG(tms, REG_DPYCTL) & 0x0400))
	983	UINT16 dpyadr = IOREG(REG_DPYADR);
	984	if (!(IOREG(REG_DPYCTL) & 0x0400))
1053	985	dpyadr ^= 0xfffc;
1054	986	params->rowaddr = dpyadr >> 4;
1055		params->coladdr = ((dpyadr & 0x007c) << 4) \| (IOREG(tms, REG_DPYTAP) & 0x3fff);
1056		params->yoffset = (IOREG(tms, REG_DPYSTRT) - IOREG(tms, REG_DPYADR)) & 3;
	987	params->coladdr = ((dpyadr & 0x007c) << 4) \| (IOREG(REG_DPYTAP) & 0x3fff);
	988	params->yoffset = (IOREG(REG_DPYSTRT) - IOREG(REG_DPYADR)) & 3;
1057	989	}
1058	990
1059	991	/* 34020 gets its address from DPYNX */
1060	992	else
1061	993	{
1062		params->rowaddr = IOREG(tms, REG020_DPYNXH);
1063		params->coladdr = IOREG(tms, REG020_DPYNXL) & 0xffe0;
	994	params->rowaddr = IOREG(REG020_DPYNXH);
	995	params->coladdr = IOREG(REG020_DPYNXL) & 0xffe0;
1064	996	params->yoffset = 0;
1065		if ((IOREG(tms, REG020_DINCL) & 0x1f) != 0)
1066		params->yoffset = (IOREG(tms, REG020_DPYNXL) & 0x1f) / (IOREG(tms, REG020_DINCL) & 0x1f);
	997	if ((IOREG(REG020_DINCL) & 0x1f) != 0)
	998	params->yoffset = (IOREG(REG020_DPYNXL) & 0x1f) / (IOREG(REG020_DINCL) & 0x1f);
1067	999	}
1068	1000	}
1069	1001
1070		UINT32 tms34010_device::tms340x0_ind16(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
	1002	UINT32 tms340x0_device::tms340x0_ind16(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
1071	1003	{
1072	1004	pen_t blackpen = screen.palette()->black_pen();
1073	1005	tms34010_display_params params;
1074		tms34010_state *tms = NULL;
1075		device_t *cpu;
1076	1006	int x;
1077	1007
1078		/* find the owning CPU */
1079		device_iterator iter(machine().root_device());
1080		for (cpu = iter.first(); cpu != NULL; cpu = iter.next())
1081		{
1082		device_type type = cpu->type();
1083		if (type == TMS34010 \|\| type == TMS34020)
1084		{
1085		tms = get_safe_token(cpu);
1086		if (tms->config != NULL && tms->config->scanline_callback_ind16 != NULL && tms->screen == &screen)
1087		break;
1088		tms = NULL;
1089		}
1090		}
1091		if (tms == NULL)
1092		fatalerror("Unable to locate matching CPU for screen '%s'\n", screen.tag());
1093
1094	1008	/* get the display parameters for the screen */
1095		~~tms34010_~~get_display_params(~~tms->device,~~ &params);
	1009	get_display_params(&params);
1096	1010
1097	1011	/* if the display is enabled, call the scanline callback */
1098	1012	if (params.enabled)
1099	1013	{
1100	1014	/* call through to the callback */
1101	1015	LOG((" Update: scan=%3d ROW=%04X COL=%04X\n", cliprect.min_y, params.rowaddr, params.coladdr));
1102		(*tm~~s->~~config->scanline_callback_ind16)(screen, bitmap, cliprect.min_y, &params);
	1016	(*m_config->scanline_callback_ind16)(screen, bitmap, cliprect.min_y, &params);
1103	1017	}
1104	1018
1105	1019	/* otherwise, just blank the current scanline */
r31176	r31177
1116	1030
1117	1031	}
1118	1032
1119		UINT32 tms34010_device::tms340x0_rgb32(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
	1033	UINT32 tms340x0_device::tms340x0_rgb32(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
1120	1034	{
1121	1035	pen_t blackpen = rgb_t::black;
1122	1036	tms34010_display_params params;
1123		tms34010_state *tms = NULL;
1124		device_t *cpu;
1125	1037	int x;
1126	1038
1127		/* find the owning CPU */
1128		device_iterator iter(machine().root_device());
1129		for (cpu = iter.first(); cpu != NULL; cpu = iter.next())
1130		{
1131		device_type type = cpu->type();
1132		if (type == TMS34010 \|\| type == TMS34020)
1133		{
1134		tms = get_safe_token(cpu);
1135		if (tms->config != NULL && tms->config->scanline_callback_rgb32 != NULL && tms->screen == &screen)
1136		break;
1137		tms = NULL;
1138		}
1139		}
1140		if (tms == NULL)
1141		fatalerror("Unable to locate matching CPU for screen '%s'\n", screen.tag());
1142
1143	1039	/* get the display parameters for the screen */
1144		~~tms34010_~~get_display_params(~~tms->device,~~ &params);
	1040	get_display_params(&params);
1145	1041
1146	1042	/* if the display is enabled, call the scanline callback */
1147	1043	if (params.enabled)
1148	1044	{
1149	1045	/* call through to the callback */
1150	1046	LOG((" Update: scan=%3d ROW=%04X COL=%04X\n", cliprect.min_y, params.rowaddr, params.coladdr));
1151		(*tm~~s->~~config->scanline_callback_rgb32)(screen, bitmap, cliprect.min_y, &params);
	1047	(*m_config->scanline_callback_rgb32)(screen, bitmap, cliprect.min_y, &params);
1152	1048	}
1153	1049
1154	1050	/* otherwise, just blank the current scanline */
r31176	r31177
1186	1082
1187	1083	WRITE16_MEMBER( tms34010_device::io_register_w )
1188	1084	{
1189		tms34010_state *tms = get_safe_token(this);
1190	1085	int oldreg, newreg;
1191	1086
1192	1087	/* Set register */
1193		oldreg = IOREG(tms, offset);
1194		IOREG(tms, offset) = data;
	1088	oldreg = IOREG(offset);
	1089	IOREG(offset) = data;
1195	1090
1196	1091	switch (offset)
1197	1092	{
1198	1093	case REG_CONTROL:
1199		set_raster_op(tms);
1200		set_pixel_function(tms);
	1094	set_raster_op();
	1095	set_pixel_function();
1201	1096	break;
1202	1097
1203	1098	case REG_PSIZE:
1204		set_pixel_function(~~tms~~);
	1099	set_pixel_function();
1205	1100
1206	1101	switch (data)
1207	1102	{
1208	1103	default:
1209		case 0x01: tms->pixelshift = 0; break;
1210		case 0x02: tms->pixelshift = 1; break;
1211		case 0x04: tms->pixelshift = 2; break;
1212		case 0x08: tms->pixelshift = 3; break;
1213		case 0x10: tms->pixelshift = 4; break;
	1104	case 0x01: m_pixelshift = 0; break;
	1105	case 0x02: m_pixelshift = 1; break;
	1106	case 0x04: m_pixelshift = 2; break;
	1107	case 0x08: m_pixelshift = 3; break;
	1108	case 0x10: m_pixelshift = 4; break;
1214	1109	}
1215	1110	break;
1216	1111
r31176	r31177
1219	1114	break;
1220	1115
1221	1116	case REG_DPYCTL:
1222		set_pixel_function(~~tms~~);
	1117	set_pixel_function();
1223	1118	break;
1224	1119
1225	1120	case REG_HSTCTLH:
1226	1121	/* if the CPU is halting itself, stop execution right away */
1227	1122	if (mem_mask & 0xff00)
1228	1123	{
1229		if ((data & 0x8000) && !tms->external_host_access)
1230		tms->icount = 0;
	1124	if ((data & 0x8000) && !m_external_host_access)
	1125	m_icount = 0;
1231	1126
1232		~~tms->device->~~set_input_line(INPUT_LINE_HALT, (data & 0x8000) ? ASSERT_LINE : CLEAR_LINE);
	1127	set_input_line(INPUT_LINE_HALT, (data & 0x8000) ? ASSERT_LINE : CLEAR_LINE);
1233	1128
1234	1129	/* NMI issued? */
1235	1130	if (data & 0x0100)
1236		tm~~s->device->m~~achine().scheduler().synchronize(FUNC(internal_interrupt_callback), 0, tms);
	1131	machine().scheduler().synchronize(timer_expired_delegate(FUNC(tms340x0_device::internal_interrupt_callback), this), 0);
1237	1132	}
1238	1133	break;
1239	1134
r31176	r31177
1241	1136	if (mem_mask & 0x00ff)
1242	1137	{
1243	1138	/* the TMS34010 can change MSGOUT, can set INTOUT, and can clear INTIN */
1244		if (!tm~~s->~~external_host_access)
	1139	if (!m_external_host_access)
1245	1140	{
1246	1141	newreg = (oldreg & 0xff8f) \| (data & 0x0070);
1247	1142	newreg \|= data & 0x0080;
r31176	r31177
1255	1150	newreg &= data \| ~0x0080;
1256	1151	newreg \|= data & 0x0008;
1257	1152	}
1258		IOREG(~~tms,~~ offset) = newreg;
	1153	IOREG(offset) = newreg;
1259	1154
1260	1155	/* the TMS34010 can set output interrupt? */
1261	1156	if (!(oldreg & 0x0080) && (newreg & 0x0080))
1262	1157	{
1263		if (tms->config->output_int)
1264		(*tms->config->output_int)(&space.device(), 1);
	1158	if (m_config->output_int)
	1159	(*m_config->output_int)(&space.device(), 1);
1265	1160	}
1266	1161	else if ((oldreg & 0x0080) && !(newreg & 0x0080))
1267	1162	{
1268		if (tms->config->output_int)
1269		(*tms->config->output_int)(&space.device(), 0);
	1163	if (m_config->output_int)
	1164	(*m_config->output_int)(&space.device(), 0);
1270	1165	}
1271	1166
1272	1167	/* input interrupt? (should really be state-based, but the functions don't exist!) */
1273	1168	if (!(oldreg & 0x0008) && (newreg & 0x0008))
1274		tm~~s->device->m~~achine().scheduler().synchronize(FUNC(internal_interrupt_callback), TMS34010_HI~~, tms~~);
	1169	machine().scheduler().synchronize(timer_expired_delegate(FUNC(tms340x0_device::internal_interrupt_callback), this), TMS34010_HI);
1275	1170	else if ((oldreg & 0x0008) && !(newreg & 0x0008))
1276		IOREG(~~tms,~~ REG_INTPEND) &= ~TMS34010_HI;
	1171	IOREG(REG_INTPEND) &= ~TMS34010_HI;
1277	1172	}
1278	1173	break;
1279	1174
1280	1175	case REG_CONVSP:
1281		tm~~s->~~convsp = 1 << (~data & 0x1f);
	1176	m_convsp = 1 << (~data & 0x1f);
1282	1177	break;
1283	1178
1284	1179	case REG_CONVDP:
1285		tm~~s->~~convdp = 1 << (~data & 0x1f);
	1180	m_convdp = 1 << (~data & 0x1f);
1286	1181	break;
1287	1182
1288	1183	case REG_INTENB:
1289		check_interrupt(~~tms~~);
	1184	check_interrupt();
1290	1185	break;
1291	1186
1292	1187	case REG_INTPEND:
1293	1188	/* X1P, X2P and HIP are read-only */
1294	1189	/* WVP and DIP can only have 0's written to them */
1295		IOREG(~~tms,~~ REG_INTPEND) = oldreg;
	1190	IOREG(REG_INTPEND) = oldreg;
1296	1191	if (!(data & TMS34010_WV))
1297		IOREG(~~tms,~~ REG_INTPEND) &= ~TMS34010_WV;
	1192	IOREG(REG_INTPEND) &= ~TMS34010_WV;
1298	1193	if (!(data & TMS34010_DI))
1299		IOREG(~~tms,~~ REG_INTPEND) &= ~TMS34010_DI;
	1194	IOREG(REG_INTPEND) &= ~TMS34010_DI;
1300	1195	break;
1301	1196
1302	1197	case REG_HEBLNK:
1303	1198	case REG_HSBLNK:
1304	1199	if (oldreg != data)
1305		tm~~s->~~hblank_stable = 0;
	1200	m_hblank_stable = 0;
1306	1201	break;
1307	1202	}
1308	1203
1309	1204	// if (LOG_CONTROL_REGS)
1310		// logerror("%s: %s = %04X (%d)\n", tm~~s->device->m~~achine().describe_context(), ioreg_name[offset], IOREG(~~tms,~~ offset), tm~~s->~~screen.vpos());
	1205	// logerror("%s: %s = %04X (%d)\n", machine().describe_context(), ioreg_name[offset], IOREG(offset), m_screen.vpos());
1311	1206	}
1312	1207
1313	1208
r31176	r31177
1338	1233
1339	1234	WRITE16_MEMBER( tms34020_device::io_register_w )
1340	1235	{
1341		tms34010_state *tms = get_safe_token(this);
1342	1236	int oldreg, newreg;
1343	1237
1344	1238	/* Set register */
1345		oldreg = IOREG(tms, offset);
1346		IOREG(tms, offset) = data;
	1239	oldreg = IOREG(offset);
	1240	IOREG(offset) = data;
1347	1241
1348	1242	// if (LOG_CONTROL_REGS)
1349		// logerror("%s: %s = %04X (%d)\n", ~~device->~~machine().describe_context(), ioreg020_name[offset], IOREG(~~tms,~~ offset), tm~~s->~~screen.vpos());
	1243	// logerror("%s: %s = %04X (%d)\n", machine().describe_context(), ioreg020_name[offset], IOREG(offset), m_screen.vpos());
1350	1244
1351	1245	switch (offset)
1352	1246	{
1353	1247	case REG020_CONTROL:
1354	1248	case REG020_CONTROL2:
1355		IOREG(tms, REG020_CONTROL) = data;
1356		IOREG(tms, REG020_CONTROL2) = data;
1357		set_raster_op(tms);
1358		set_pixel_function(tms);
	1249	IOREG(REG020_CONTROL) = data;
	1250	IOREG(REG020_CONTROL2) = data;
	1251	set_raster_op();
	1252	set_pixel_function();
1359	1253	break;
1360	1254
1361	1255	case REG020_PSIZE:
1362		set_pixel_function(~~tms~~);
	1256	set_pixel_function();
1363	1257
1364	1258	switch (data)
1365	1259	{
1366	1260	default:
1367		case 0x01: tms->pixelshift = 0; break;
1368		case 0x02: tms->pixelshift = 1; break;
1369		case 0x04: tms->pixelshift = 2; break;
1370		case 0x08: tms->pixelshift = 3; break;
1371		case 0x10: tms->pixelshift = 4; break;
1372		case 0x20: tms->pixelshift = 5; break;
	1261	case 0x01: m_pixelshift = 0; break;
	1262	case 0x02: m_pixelshift = 1; break;
	1263	case 0x04: m_pixelshift = 2; break;
	1264	case 0x08: m_pixelshift = 3; break;
	1265	case 0x10: m_pixelshift = 4; break;
	1266	case 0x20: m_pixelshift = 5; break;
1373	1267	}
1374	1268	break;
1375	1269
r31176	r31177
1379	1273	break;
1380	1274
1381	1275	case REG020_DPYCTL:
1382		set_pixel_function(~~tms~~);
	1276	set_pixel_function();
1383	1277	break;
1384	1278
1385	1279	case REG020_HSTCTLH:
1386	1280	/* if the CPU is halting itself, stop execution right away */
1387		if ((data & 0x8000) && !tms->external_host_access)
1388		tms->icount = 0;
1389		tms->device->set_input_line(INPUT_LINE_HALT, (data & 0x8000) ? ASSERT_LINE : CLEAR_LINE);
	1281	if ((data & 0x8000) && !m_external_host_access)
	1282	m_icount = 0;
	1283	set_input_line(INPUT_LINE_HALT, (data & 0x8000) ? ASSERT_LINE : CLEAR_LINE);
1390	1284
1391	1285	/* NMI issued? */
1392	1286	if (data & 0x0100)
1393		tm~~s->device->m~~achine().scheduler().synchronize(FUNC(internal_interrupt_callback), 0, tms);
	1287	machine().scheduler().synchronize(timer_expired_delegate(FUNC(tms340x0_device::internal_interrupt_callback), this), 0);
1394	1288	break;
1395	1289
1396	1290	case REG020_HSTCTLL:
1397	1291	/* the TMS34010 can change MSGOUT, can set INTOUT, and can clear INTIN */
1398		if (!tm~~s->~~external_host_access)
	1292	if (!m_external_host_access)
1399	1293	{
1400	1294	newreg = (oldreg & 0xff8f) \| (data & 0x0070);
1401	1295	newreg \|= data & 0x0080;
r31176	r31177
1409	1303	newreg &= data \| ~0x0080;
1410	1304	newreg \|= data & 0x0008;
1411	1305	}
1412		IOREG(~~tms,~~ offset) = newreg;
	1306	IOREG(offset) = newreg;
1413	1307
1414	1308	/* the TMS34010 can set output interrupt? */
1415	1309	if (!(oldreg & 0x0080) && (newreg & 0x0080))
1416	1310	{
1417		if (tms->config->output_int)
1418		(*tms->config->output_int)(&space.device(), 1);
	1311	if (m_config->output_int)
	1312	(*m_config->output_int)(&space.device(), 1);
1419	1313	}
1420	1314	else if ((oldreg & 0x0080) && !(newreg & 0x0080))
1421	1315	{
1422		if (tms->config->output_int)
1423		(*tms->config->output_int)(&space.device(), 0);
	1316	if (m_config->output_int)
	1317	(*m_config->output_int)(&space.device(), 0);
1424	1318	}
1425	1319
1426	1320	/* input interrupt? (should really be state-based, but the functions don't exist!) */
1427	1321	if (!(oldreg & 0x0008) && (newreg & 0x0008))
1428		tm~~s->device->m~~achine().scheduler().synchronize(FUNC(internal_interrupt_callback), TMS34010_HI~~, tms~~);
	1322	machine().scheduler().synchronize(timer_expired_delegate(FUNC(tms340x0_device::internal_interrupt_callback), this), TMS34010_HI);
1429	1323	else if ((oldreg & 0x0008) && !(newreg & 0x0008))
1430		IOREG(~~tms,~~ REG020_INTPEND) &= ~TMS34010_HI;
	1324	IOREG(REG020_INTPEND) &= ~TMS34010_HI;
1431	1325	break;
1432	1326
1433	1327	case REG020_INTENB:
1434		check_interrupt(~~tms~~);
	1328	check_interrupt();
1435	1329	break;
1436	1330
1437	1331	case REG020_INTPEND:
1438	1332	/* X1P, X2P and HIP are read-only */
1439	1333	/* WVP and DIP can only have 0's written to them */
1440		IOREG(~~tms,~~ REG020_INTPEND) = oldreg;
	1334	IOREG(REG020_INTPEND) = oldreg;
1441	1335	if (!(data & TMS34010_WV))
1442		IOREG(~~tms,~~ REG020_INTPEND) &= ~TMS34010_WV;
	1336	IOREG(REG020_INTPEND) &= ~TMS34010_WV;
1443	1337	if (!(data & TMS34010_DI))
1444		IOREG(~~tms,~~ REG020_INTPEND) &= ~TMS34010_DI;
	1338	IOREG(REG020_INTPEND) &= ~TMS34010_DI;
1445	1339	break;
1446	1340
1447	1341	case REG020_CONVSP:
1448	1342	if (data & 0x001f)
1449	1343	{
1450	1344	if (data & 0x1f00)
1451		tm~~s->~~convsp = (1 << (~data & 0x1f)) + (1 << (~(data >> 8) & 0x1f));
	1345	m_convsp = (1 << (~data & 0x1f)) + (1 << (~(data >> 8) & 0x1f));
1452	1346	else
1453		tm~~s->~~convsp = 1 << (~data & 0x1f);
	1347	m_convsp = 1 << (~data & 0x1f);
1454	1348	}
1455	1349	else
1456		tm~~s->~~convsp = data;
	1350	m_convsp = data;
1457	1351	break;
1458	1352
1459	1353	case REG020_CONVDP:
1460	1354	if (data & 0x001f)
1461	1355	{
1462	1356	if (data & 0x1f00)
1463		tm~~s->~~convdp = (1 << (~data & 0x1f)) + (1 << (~(data >> 8) & 0x1f));
	1357	m_convdp = (1 << (~data & 0x1f)) + (1 << (~(data >> 8) & 0x1f));
1464	1358	else
1465		tm~~s->~~convdp = 1 << (~data & 0x1f);
	1359	m_convdp = 1 << (~data & 0x1f);
1466	1360	}
1467	1361	else
1468		tm~~s->~~convdp = data;
	1362	m_convdp = data;
1469	1363	break;
1470	1364
1471	1365	case REG020_CONVMP:
1472	1366	if (data & 0x001f)
1473	1367	{
1474	1368	if (data & 0x1f00)
1475		tm~~s->~~convmp = (1 << (~data & 0x1f)) + (1 << (~(data >> 8) & 0x1f));
	1369	m_convmp = (1 << (~data & 0x1f)) + (1 << (~(data >> 8) & 0x1f));
1476	1370	else
1477		tm~~s->~~convmp = 1 << (~data & 0x1f);
	1371	m_convmp = 1 << (~data & 0x1f);
1478	1372	}
1479	1373	else
1480		tm~~s->~~convmp = data;
	1374	m_convmp = data;
1481	1375	break;
1482	1376
1483	1377	case REG020_DPYSTRT:
r31176	r31177
1488	1382	case REG020_HEBLNK:
1489	1383	case REG020_HSBLNK:
1490	1384	if (oldreg != data)
1491		tm~~s->~~hblank_stable = 0;
	1385	m_hblank_stable = 0;
1492	1386	break;
1493	1387	}
1494	1388	}
r31176	r31177
1501	1395
1502	1396	READ16_MEMBER( tms34010_device::io_register_r )
1503	1397	{
1504		tms34010_state *tms = get_safe_token(this);
1505	1398	int result, total;
1506	1399
1507	1400	// if (LOG_CONTROL_REGS)
1508		// logerror("%s: read %s\n", ~~device->~~machine().describe_context(), ioreg_name[offset]);
	1401	// logerror("%s: read %s\n", machine().describe_context(), ioreg_name[offset]);
1509	1402
1510	1403	switch (offset)
1511	1404	{
1512	1405	case REG_HCOUNT:
1513	1406	/* scale the horizontal position from screen width to HTOTAL */
1514		result = tms->screen->hpos();
1515		total = IOREG(tms, REG_HTOTAL) + 1;
1516		result = result * total / tms->screen->width();
	1407	result = m_screen->hpos();
	1408	total = IOREG(REG_HTOTAL) + 1;
	1409	result = result * total / m_screen->width();
1517	1410
1518	1411	/* offset by the HBLANK end */
1519		result += IOREG(~~tms,~~ REG_HEBLNK);
	1412	result += IOREG(REG_HEBLNK);
1520	1413
1521	1414	/* wrap around */
1522	1415	if (result > total)
r31176	r31177
1524	1417	return result;
1525	1418
1526	1419	case REG_REFCNT:
1527		return (t~~ms->device->t~~otal_cycles() / 16) & 0xfffc;
	1420	return (total_cycles() / 16) & 0xfffc;
1528	1421
1529	1422	case REG_INTPEND:
1530		result = IOREG(~~tms,~~ offset);
	1423	result = IOREG(offset);
1531	1424
1532	1425	/* Cool Pool loops in mainline code on the appearance of the DI, even though they */
1533	1426	/* have an IRQ handler. For this reason, we return it signalled a bit early in order */
1534	1427	/* to make it past these loops. */
1535		if (SMART_IOREG(tms, VCOUNT) + 1 == SMART_IOREG(tms, DPYINT) &&
1536		tms->scantimer->remaining() < attotime::from_hz(40000000/8/3))
	1428	if (SMART_IOREG(VCOUNT) + 1 == SMART_IOREG(DPYINT) &&
	1429	m_scantimer->remaining() < attotime::from_hz(40000000/8/3))
1537	1430	result \|= TMS34010_DI;
1538	1431	return result;
1539	1432	}
1540	1433
1541		return IOREG(~~tms,~~ offset);
	1434	return IOREG(offset);
1542	1435	}
1543	1436
1544	1437
1545	1438	READ16_MEMBER( tms34020_device::io_register_r )
1546	1439	{
1547		tms34010_state *tms = get_safe_token(this);
1548	1440	int result, total;
1549	1441
1550	1442	// if (LOG_CONTROL_REGS)
1551		// logerror("%s: read %s\n", ~~device->~~machine().describe_context(), ioreg_name[offset]);
	1443	// logerror("%s: read %s\n", machine().describe_context(), ioreg_name[offset]);
1552	1444
1553	1445	switch (offset)
1554	1446	{
1555	1447	case REG020_HCOUNT:
1556	1448	/* scale the horizontal position from screen width to HTOTAL */
1557		result = tms->screen->hpos();
1558		total = IOREG(tms, REG020_HTOTAL) + 1;
1559		result = result * total / tms->screen->width();
	1449	result = m_screen->hpos();
	1450	total = IOREG(REG020_HTOTAL) + 1;
	1451	result = result * total / m_screen->width();
1560	1452
1561	1453	/* offset by the HBLANK end */
1562		result += IOREG(~~tms,~~ REG020_HEBLNK);
	1454	result += IOREG(REG020_HEBLNK);
1563	1455
1564	1456	/* wrap around */
1565	1457	if (result > total)
r31176	r31177
1568	1460
1569	1461	case REG020_REFADR:
1570	1462	{
1571		int refreshrate = (IOREG(~~tms,~~ REG020_CONFIG) >> 8) & 7;
	1463	int refreshrate = (IOREG(REG020_CONFIG) >> 8) & 7;
1572	1464	if (refreshrate < 6)
1573		return (t~~ms->device->t~~otal_cycles() / refreshrate) & 0xffff;
	1465	return (total_cycles() / refreshrate) & 0xffff;
1574	1466	break;
1575	1467	}
1576	1468	}
1577	1469
1578		return IOREG(~~tms,~~ offset);
	1470	return IOREG(offset);
1579	1471	}
1580	1472
1581	1473
r31176	r31177
1584	1476	SAVE STATE
1585	1477	***************************************************************************/
1586	1478
1587		~~static~~ void tms34010_~~stat~~e~~_pos~~t~~load(t~~ms34010_state *tms)
	1479	void tms340x0_device::tms34010_state_postload()
1588	1480	{
1589		set_raster_op(tms);
1590		set_pixel_function(tms);
	1481	set_raster_op();
	1482	set_pixel_function();
1591	1483	}
1592	1484
1593	1485
r31176	r31177
1595	1487	HOST INTERFACE WRITES
1596	1488	***************************************************************************/
1597	1489
1598		WRITE16_MEMBER( tms34010_device::host_w )
	1490	WRITE16_MEMBER( tms340x0_device::host_w )
1599	1491	{
1600	1492	int reg = offset;
1601		tms34010_state *tms = get_safe_token(this);
1602	1493	unsigned int addr;
1603	1494
1604	1495	switch (reg)
1605	1496	{
1606	1497	/* upper 16 bits of the address */
1607	1498	case TMS34010_HOST_ADDRESS_H:
1608		IOREG(~~tms,~~ REG_HSTADRH) = data;
	1499	IOREG(REG_HSTADRH) = data;
1609	1500	break;
1610	1501
1611	1502	/* lower 16 bits of the address */
1612	1503	case TMS34010_HOST_ADDRESS_L:
1613		IOREG(~~tms,~~ REG_HSTADRL) = data;
	1504	IOREG(REG_HSTADRL) = data;
1614	1505	break;
1615	1506
1616	1507	/* actual data */
1617	1508	case TMS34010_HOST_DATA:
1618	1509
1619	1510	/* write to the address */
1620		addr = (IOREG(tms, REG_HSTADRH) << 16) \| IOREG(tms, REG_HSTADRL);
1621		TMS34010_WRMEM_WORD(tms, TOBYTE(addr & 0xfffffff0), data);
	1511	addr = (IOREG(REG_HSTADRH) << 16) \| IOREG(REG_HSTADRL);
	1512	TMS34010_WRMEM_WORD(TOBYTE(addr & 0xfffffff0), data);
1622	1513
1623	1514	/* optional postincrement */
1624		if (IOREG(~~tms,~~ REG_HSTCTLH) & 0x0800)
	1515	if (IOREG(REG_HSTCTLH) & 0x0800)
1625	1516	{
1626	1517	addr += 0x10;
1627		IOREG(tms, REG_HSTADRH) = addr >> 16;
1628		IOREG(tms, REG_HSTADRL) = (UINT16)addr;
	1518	IOREG(REG_HSTADRH) = addr >> 16;
	1519	IOREG(REG_HSTADRL) = (UINT16)addr;
1629	1520	}
1630	1521	break;
1631	1522
1632	1523	/* control register */
1633	1524	case TMS34010_HOST_CONTROL:
1634	1525	{
1635		tms->external_host_access = TRUE;
1636		address_space &space = tms->device->space(AS_PROGRAM);
1637		if (mem_mask&0xff00) io_register_w(space, REG_HSTCTLH, data & 0xff00, 0xff00);
1638		if (mem_mask&0x00ff) io_register_w(space, REG_HSTCTLL, data & 0x00ff, 0x00ff);
1639		tms->external_host_access = FALSE;
	1526	m_external_host_access = TRUE;
	1527	if (mem_mask&0xff00) io_register_w(*m_program, REG_HSTCTLH, data & 0xff00, 0xff00);
	1528	if (mem_mask&0x00ff) io_register_w(*m_program, REG_HSTCTLL, data & 0x00ff, 0x00ff);
	1529	m_external_host_access = FALSE;
1640	1530	break;
1641	1531	}
1642	1532
r31176	r31177
1653	1543	HOST INTERFACE READS
1654	1544	***************************************************************************/
1655	1545
1656		READ16_MEMBER( tms34010_device::host_r )
	1546	READ16_MEMBER( tms340x0_device::host_r )
1657	1547	{
1658	1548	int reg = offset;
1659		tms34010_state *tms = get_safe_token(this);
1660	1549	unsigned int addr;
1661	1550	int result = 0;
1662	1551
r31176	r31177
1666	1555	{
1667	1556	/* upper 16 bits of the address */
1668	1557	case TMS34010_HOST_ADDRESS_H:
1669		result = IOREG(~~tms,~~ REG_HSTADRH);
	1558	result = IOREG(REG_HSTADRH);
1670	1559	break;
1671	1560
1672	1561	/* lower 16 bits of the address */
1673	1562	case TMS34010_HOST_ADDRESS_L:
1674		result = IOREG(~~tms,~~ REG_HSTADRL);
	1563	result = IOREG(REG_HSTADRL);
1675	1564	break;
1676	1565
1677	1566	/* actual data */
1678	1567	case TMS34010_HOST_DATA:
1679	1568
1680	1569	/* read from the address */
1681		addr = (IOREG(tms, REG_HSTADRH) << 16) \| IOREG(tms, REG_HSTADRL);
1682		result = TMS34010_RDMEM_WORD(tms, TOBYTE(addr & 0xfffffff0));
	1570	addr = (IOREG(REG_HSTADRH) << 16) \| IOREG(REG_HSTADRL);
	1571	result = TMS34010_RDMEM_WORD(TOBYTE(addr & 0xfffffff0));
1683	1572
1684	1573	/* optional postincrement (it says preincrement, but data is preloaded, so it
1685	1574	is effectively a postincrement */
1686		if (IOREG(~~tms,~~ REG_HSTCTLH) & 0x1000)
	1575	if (IOREG(REG_HSTCTLH) & 0x1000)
1687	1576	{
1688	1577	addr += 0x10;
1689		IOREG(tms, REG_HSTADRH) = addr >> 16;
1690		IOREG(tms, REG_HSTADRL) = (UINT16)addr;
	1578	IOREG(REG_HSTADRH) = addr >> 16;
	1579	IOREG(REG_HSTADRL) = (UINT16)addr;
1691	1580	}
1692	1581	break;
1693	1582
1694	1583	/* control register */
1695	1584	case TMS34010_HOST_CONTROL:
1696		result = (IOREG(~~tms,~~ REG_HSTCTLH) & 0xff00) \| (IOREG(~~tms,~~ REG_HSTCTLL) & 0x00ff);
	1585	result = (IOREG(REG_HSTCTLH) & 0xff00) \| (IOREG(REG_HSTCTLL) & 0x00ff);
1697	1586	break;
1698	1587
1699	1588	/* error case */
r31176	r31177
1706	1595	}
1707	1596
1708	1597
1709
1710		/**************************************************************************
1711		* Generic set_info
1712		**************************************************************************/
1713
1714		static CPU_SET_INFO( tms34010 )
	1598	void tms340x0_device::state_string_export(const device_state_entry &entry, astring &string)
1715	1599	{
1716		tms34010_state *tms = get_safe_token(device);
1717
1718		switch (state)
1719		{
1720		/* --- the following bits of info are set as 64-bit signed integers --- */
1721		case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(tms, 0, info->i); break;
1722		case CPUINFO_INT_INPUT_STATE + 1: set_irq_line(tms, 1, info->i); break;
1723		}
1724		}
1725
1726
1727
1728		/**************************************************************************
1729		* Generic get_info
1730		**************************************************************************/
1731
1732		CPU_EXPORT_STRING( tms34010 )
1733		{
1734		tms34010_state *tms = get_safe_token(device);
1735
1736	1600	switch (entry.index())
1737	1601	{
1738	1602	case STATE_GENFLAGS:
1739	1603	string.printf("%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
1740		tms->st & 0x80000000 ? 'N':'.',
1741		tms->st & 0x40000000 ? 'C':'.',
1742		tms->st & 0x20000000 ? 'Z':'.',
1743		tms->st & 0x10000000 ? 'V':'.',
1744		tms->st & 0x02000000 ? 'P':'.',
1745		tms->st & 0x00200000 ? 'I':'.',
1746		tms->st & 0x00000800 ? 'E':'.',
1747		tms->st & 0x00000400 ? 'F':'.',
1748		tms->st & 0x00000200 ? 'F':'.',
1749		tms->st & 0x00000100 ? 'F':'.',
1750		tms->st & 0x00000080 ? 'F':'.',
1751		tms->st & 0x00000040 ? 'F':'.',
1752		tms->st & 0x00000020 ? 'E':'.',
1753		tms->st & 0x00000010 ? 'F':'.',
1754		tms->st & 0x00000008 ? 'F':'.',
1755		tms->st & 0x00000004 ? 'F':'.',
1756		tms->st & 0x00000002 ? 'F':'.',
1757		tms->st & 0x00000001 ? 'F':'.');
	1604	m_st & 0x80000000 ? 'N':'.',
	1605	m_st & 0x40000000 ? 'C':'.',
	1606	m_st & 0x20000000 ? 'Z':'.',
	1607	m_st & 0x10000000 ? 'V':'.',
	1608	m_st & 0x02000000 ? 'P':'.',
	1609	m_st & 0x00200000 ? 'I':'.',
	1610	m_st & 0x00000800 ? 'E':'.',
	1611	m_st & 0x00000400 ? 'F':'.',
	1612	m_st & 0x00000200 ? 'F':'.',
	1613	m_st & 0x00000100 ? 'F':'.',
	1614	m_st & 0x00000080 ? 'F':'.',
	1615	m_st & 0x00000040 ? 'F':'.',
	1616	m_st & 0x00000020 ? 'E':'.',
	1617	m_st & 0x00000010 ? 'F':'.',
	1618	m_st & 0x00000008 ? 'F':'.',
	1619	m_st & 0x00000004 ? 'F':'.',
	1620	m_st & 0x00000002 ? 'F':'.',
	1621	m_st & 0x00000001 ? 'F':'.');
1758	1622	break;
1759	1623	}
1760	1624	}
1761	1625
1762		CPU_GET_INFO( tms34010 )
1763		{
1764		tms34010_state *tms = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
1765	1626
1766		switch (state)
1767		{
1768		/* --- the following bits of info are returned as 64-bit signed integers --- */
1769		case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(tms34010_state); break;
1770		case CPUINFO_INT_INPUT_LINES: info->i = 2; break;
1771		case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
1772		case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
1773		case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
1774		case CPUINFO_INT_CLOCK_DIVIDER: info->i = 8; break;
1775		case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break;
1776		case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 10; break;
1777		case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
1778		case CPUINFO_INT_MAX_CYCLES: info->i = 10000; break;
1779
1780		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break;
1781		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break;
1782		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 3; break;
1783
1784		case CPUINFO_INT_INPUT_STATE + 0: info->i = (IOREG(tms, REG_INTPEND) & TMS34010_INT1) ? ASSERT_LINE : CLEAR_LINE; break;
1785		case CPUINFO_INT_INPUT_STATE + 1: info->i = (IOREG(tms, REG_INTPEND) & TMS34010_INT2) ? ASSERT_LINE : CLEAR_LINE; break;
1786
1787		/* --- the following bits of info are returned as pointers to functions --- */
1788		case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(tms34010); break;
1789		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(tms34010); break;
1790		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(tms34010); break;
1791		case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(tms34010); break;
1792		case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(tms34010); break;
1793		case CPUINFO_FCT_BURN: info->burn = NULL; break;
1794		case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(tms34010); break;
1795		case CPUINFO_FCT_EXPORT_STRING: info->export_string = CPU_EXPORT_STRING_NAME(tms34010); break;
1796
1797		/* --- the following bits of info are returned as pointers --- */
1798		case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &tms->icount; break;
1799
1800		/* --- the following bits of info are returned as NULL-terminated strings --- */
1801		case CPUINFO_STR_NAME: strcpy(info->s, "TMS34010"); break;
1802		case CPUINFO_STR_SHORTNAME: strcpy(info->s, "tms34010"); break;
1803		case CPUINFO_STR_FAMILY: strcpy(info->s, "Texas Instruments 340x0"); break;
1804		case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break;
1805		case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
1806		case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Alex Pasadyn/Zsolt Vasvari\nParts based on code by Aaron Giles"); break;
1807		}
1808		}
1809
1810
1811		/**************************************************************************
1812		* CPU-specific set_info
1813		**************************************************************************/
1814
1815		CPU_GET_INFO( tms34020 )
	1627	offs_t tms34010_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
1816	1628	{
1817		switch (state)
1818		{
1819		/* --- the following bits of info are returned as 64-bit signed integers --- */
1820		case CPUINFO_INT_CLOCK_DIVIDER: info->i = 4; break;
	1629	extern CPU_DISASSEMBLE( tms34010 );
1821	1630
1822		/* --- the following bits of info are returned as pointers to data or functions --- */
1823		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(tms34020); break;
1824		case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(tms34020); break;
1825
1826		/* --- the following bits of info are returned as NULL-terminated strings --- */
1827		case CPUINFO_STR_NAME: strcpy(info->s, "TMS34020"); break;
1828		case CPUINFO_STR_SHORTNAME: strcpy(info->s, "tms34020"); break;
1829
1830		default: CPU_GET_INFO_CALL(tms34010); break;
1831		}
	1631	return CPU_DISASSEMBLE_NAME(tms34010)(this, buffer, pc, oprom, opram, options);
1832	1632	}
1833	1633
1834		tms34010_device::tms34010_device(const machine_config &mconfig, device_type type, const char tag, device_t owner, UINT32 clock)
1835		: legacy_cpu_device(mconfig, type, tag, owner, clock, CPU_GET_INFO_NAME(tms34010))
1836		{
1837		}
1838	1634
1839		tms34010_device::tms34010_device(const machine_config &mconfig, device_type type, const char tag, device_t owner, UINT32 clock, cpu_get_info_func get_info)
1840		: legacy_cpu_device(mconfig, type, tag, owner, clock, get_info)
	1635	offs_t tms34020_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
1841	1636	{
1842		}
	1637	extern CPU_DISASSEMBLE( tms34020 );
1843	1638
1844		const device_type TMS34010 = &legacy_device_creator<tms34010_device>;
1845
1846
1847
1848		tms34020_device::tms34020_device(const machine_config &mconfig, device_type type, const char tag, device_t owner, UINT32 clock)
1849		: tms34010_device(mconfig, type, tag, owner, clock, CPU_GET_INFO_NAME(tms34020))
1850		{
	1639	return CPU_DISASSEMBLE_NAME(tms34020)(this, buffer, pc, oprom, opram, options);
1851	1640	}
1852	1641
1853		const device_type TMS34020 = &legacy_device_creator<tms34020_device>;

trunk/src/emu/cpu/tms34010/34010gfx.c
r31176	r31177
11	11
12	12
13	13	#define LOG_GFX_OPS 0
14		#define LOGGFX(x) do { if (LOG_GFX_OPS && ~~tms->device->~~machine().input().code_pressed(KEYCODE_L)) logerror x; } while (0)
	14	#define LOGGFX(x) do { if (LOG_GFX_OPS && machine().input().code_pressed(KEYCODE_L)) logerror x; } while (0)
15	15
16	16
17	17	/* Graphics Instructions */
18	18
19		~~static~~ void ~~line(~~tms34010_~~stat~~e *tms, UINT16 op)
	19	void tms340x0_device::line(UINT16 op)
20	20	{
21		if (!P_FLAG(~~tms~~))
	21	if (!P_FLAG())
22	22	{
23		if (WINDOW_CHECKING(tms) != 0 && WINDOW_CHECKING(tms) != 3)
24		logerror("LINE XY %08X - Window Checking Mode %d not supported\n", tms->pc, WINDOW_CHECKING(tms));
	23	if (WINDOW_CHECKING() != 0 && WINDOW_CHECKING() != 3)
	24	logerror("LINE XY %08X - Window Checking Mode %d not supported\n", m_pc, WINDOW_CHECKING());
25	25
26		tms->st \|= STBIT_P;
27		TEMP(tms) = (op & 0x80) ? 1 : 0; /* boundary value depends on the algorithm */
28		LOGGFX(("%08X(%3d):LINE (%d,%d)-(%d,%d)\n", tms->pc, tms->screen->vpos(), DADDR_X(tms), DADDR_Y(tms), DADDR_X(tms) + DYDX_X(tms), DADDR_Y(tms) + DYDX_Y(tms)));
	26	m_st \|= STBIT_P;
	27	TEMP() = (op & 0x80) ? 1 : 0; /* boundary value depends on the algorithm */
	28	LOGGFX(("%08X(%3d):LINE (%d,%d)-(%d,%d)\n", m_pc, m_screen->vpos(), DADDR_X(), DADDR_Y(), DADDR_X() + DYDX_X(), DADDR_Y() + DYDX_Y()));
29	29	}
30	30
31		if (COUNT(~~tms~~) > 0)
	31	if (COUNT() > 0)
32	32	{
33	33	INT16 x1,y1;
34	34
35		COUNT(tms)--;
36		if (WINDOW_CHECKING(tms) != 3 \|\|
37		(DADDR_X(tms) >= WSTART_X(tms) && DADDR_X(tms) <= WEND_X(tms) &&
38		DADDR_Y(tms) >= WSTART_Y(tms) && DADDR_Y(tms) <= WEND_Y(tms)))
39		WPIXEL(tms,DXYTOL(tms,DADDR_XY(tms)),COLOR1(tms));
	35	COUNT()--;
	36	if (WINDOW_CHECKING() != 3 \|\|
	37	(DADDR_X() >= WSTART_X() && DADDR_X() <= WEND_X() &&
	38	DADDR_Y() >= WSTART_Y() && DADDR_Y() <= WEND_Y()))
	39	WPIXEL(DXYTOL(DADDR_XY()),COLOR1());
40	40
41		if (SADDR(~~tms~~) >= TEMP(~~tms~~))
	41	if (SADDR() >= TEMP())
42	42	{
43		SADDR(tms) += DYDX_Y(tms)2 - DYDX_X(tms)2;
44		x1 = INC1_X(tms);
45		y1 = INC1_Y(tms);
	43	SADDR() += DYDX_Y()2 - DYDX_X()2;
	44	x1 = INC1_X();
	45	y1 = INC1_Y();
46	46	}
47	47	else
48	48	{
49		SADDR(tms) += DYDX_Y(tms)*2;
50		x1 = INC2_X(tms);
51		y1 = INC2_Y(tms);
	49	SADDR() += DYDX_Y()*2;
	50	x1 = INC2_X();
	51	y1 = INC2_Y();
52	52	}
53		DADDR_X(tms) += x1;
54		DADDR_Y(tms) += y1;
	53	DADDR_X() += x1;
	54	DADDR_Y() += y1;
55	55
56		COUNT_UNKNOWN_CYCLES(tms,2);
57		tms->pc -= 0x10; /* not done yet, check for interrupts and restart instruction */
	56	COUNT_UNKNOWN_CYCLES(2);
	57	m_pc -= 0x10; /* not done yet, check for interrupts and restart instruction */
58	58	return;
59	59	}
60		tm~~s->~~st &= ~STBIT_P;
	60	m_st &= ~STBIT_P;
61	61	}
62	62
63	63
r31176	r31177
70	70	* directions (left->right/right->left, top->bottom/bottom->top)
71	71	*/
72	72
73		~~stat~~i~~c i~~nt apply_window(~~tms34010_state tms,~~ const char inst_name,int srcbpp, UINT32 srcaddr, XY dst, int dx, int dy)
	73	int tms340x0_device::apply_window(const char inst_name,int srcbpp, UINT32 srcaddr, XY dst, int dx, int *dy)
74	74	{
75	75	/* apply the window */
76		if (WINDOW_CHECKING(~~tms~~) == 0)
	76	if (WINDOW_CHECKING() == 0)
77	77	return 0;
78	78	else
79	79	{
r31176	r31177
83	83	int ey = sy + *dy - 1;
84	84	int diff, cycles = 3;
85	85
86		if (WINDOW_CHECKING(tms) == 2)
87		logerror("%08x: %s apply_window window mode %d not supported!\n", tms->device->pc(), inst_name, WINDOW_CHECKING(tms));
	86	if (WINDOW_CHECKING() == 2)
	87	logerror("%08x: %s apply_window window mode %d not supported!\n", pc(), inst_name, WINDOW_CHECKING());
88	88
89		CLR_V(tms);
90		if (WINDOW_CHECKING(tms) == 1)
91		SET_V_LOG(tms, 1);
	89	CLR_V();
	90	if (WINDOW_CHECKING() == 1)
	91	SET_V_LOG(1);
92	92
93	93	/* clip X */
94		diff = WSTART_X(~~tms~~) - sx;
	94	diff = WSTART_X() - sx;
95	95	if (diff > 0)
96	96	{
97	97	if (srcaddr)
98	98	srcaddr += diff srcbpp;
99	99	sx += diff;
100		SET_V_LOG(~~tms,~~ 1);
	100	SET_V_LOG(1);
101	101	}
102		diff = ex - WEND_X(~~tms~~);
	102	diff = ex - WEND_X();
103	103	if (diff > 0)
104	104	{
105	105	ex -= diff;
106		SET_V_LOG(~~tms,~~ 1);
	106	SET_V_LOG(1);
107	107	}
108	108
109	109
110	110	/* clip Y */
111		diff = WSTART_Y(~~tms~~) - sy;
	111	diff = WSTART_Y() - sy;
112	112	if (diff > 0)
113	113	{
114	114	if (srcaddr)
115		srcaddr += diff tm~~s->~~convsp;
	115	srcaddr += diff m_convsp;
116	116
117	117	sy += diff;
118		SET_V_LOG(~~tms,~~ 1);
	118	SET_V_LOG(1);
119	119	}
120		diff = ey - WEND_Y(~~tms~~);
	120	diff = ey - WEND_Y();
121	121	if (diff > 0)
122	122	{
123	123	ey -= diff;
124		SET_V_LOG(~~tms,~~ 1);
	124	SET_V_LOG(1);
125	125	}
126	126
127	127	/* compute cycles */
r31176	r31177
166	166
167	167	*******************************************************************/
168	168
169		~~stat~~i~~c i~~nt compute_fill_cycles(int left_partials, int right_partials, int full_words, int op_timing)
	169	int tms340x0_device::compute_fill_cycles(int left_partials, int right_partials, int full_words, int op_timing)
170	170	{
171	171	int dstwords;
172	172
r31176	r31177
177	177	return (dstwords * op_timing);
178	178	}
179	179
180		~~stat~~i~~c i~~nt compute_pixblt_cycles(int left_partials, int right_partials, int full_words, int op_timing)
	180	int tms340x0_device::compute_pixblt_cycles(int left_partials, int right_partials, int full_words, int op_timing)
181	181	{
182	182	int srcwords, dstwords;
183	183
r31176	r31177
189	189	return (dstwords * op_timing + srcwords * 2) + 2;
190	190	}
191	191
192		~~stat~~i~~c i~~nt compute_pixblt_b_cycles(int left_partials, int right_partials, int full_words, int rows, int op_timing, int bpp)
	192	int tms340x0_device::compute_pixblt_b_cycles(int left_partials, int right_partials, int full_words, int rows, int op_timing, int bpp)
193	193	{
194	194	int srcwords, dstwords;
195	195
r31176	r31177
203	203
204	204
205	205	/* Shift register handling */
206		~~static~~ void memory_w(address_space &space, offs_t offset,UINT16 data)
	206	void tms340x0_device::memory_w(address_space &space, offs_t offset,UINT16 data)
207	207	{
208	208	space.write_word(offset, data);
209	209	}
210	210
211		~~static~~ UINT16 memory_r(address_space &space, offs_t offset)
	211	UINT16 tms340x0_device::memory_r(address_space &space, offs_t offset)
212	212	{
213	213	return space.read_word(offset);
214	214	}
215	215
216		~~static~~ void shiftreg_w(address_space &space, offs_t offset,UINT16 data)
	216	void tms340x0_device::shiftreg_w(address_space &space, offs_t offset,UINT16 data)
217	217	{
218		tms34010_state *tms = get_safe_token(&space.device());
219		if (tms->config->from_shiftreg)
220		(*tms->config->from_shiftreg)(space, (UINT32)(offset << 3) & ~15, &tms->shiftreg[0]);
	218	if (m_config->from_shiftreg)
	219	(*m_config->from_shiftreg)(space, (UINT32)(offset << 3) & ~15, &m_shiftreg[0]);
221	220	else
222		logerror("From ShiftReg function not set. PC = %08X\n", tm~~s->~~pc);
	221	logerror("From ShiftReg function not set. PC = %08X\n", m_pc);
223	222	}
224	223
225		~~static~~ UINT16 shiftreg_r(address_space &space, offs_t offset)
	224	UINT16 tms340x0_device::shiftreg_r(address_space &space, offs_t offset)
226	225	{
227		tms34010_state *tms = get_safe_token(&space.device());
228		if (tms->config->to_shiftreg)
229		(*tms->config->to_shiftreg)(space, (UINT32)(offset << 3) & ~15, &tms->shiftreg[0]);
	226	if (m_config->to_shiftreg)
	227	(*m_config->to_shiftreg)(space, (UINT32)(offset << 3) & ~15, &m_shiftreg[0]);
230	228	else
231		logerror("To ShiftReg function not set. PC = %08X\n", tms->pc);
232		return tms->shiftreg[0];
	229	logerror("To ShiftReg function not set. PC = %08X\n", m_pc);
	230	return m_shiftreg[0];
233	231	}
234	232
235		~~static~~ UINT16 dummy_shiftreg_r(address_space &space, offs_t offset)
	233	UINT16 tms340x0_device::dummy_shiftreg_r(address_space &space, offs_t offset)
236	234	{
237		tms34010_state *tms = get_safe_token(&space.device());
238		return tms->shiftreg[0];
	235	return m_shiftreg[0];
239	236	}
240	237
241	238
242	239
243	240	/* Pixel operations */
244		static UINT32 pixel_op00(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix; }
245		static UINT32 pixel_op01(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix & dstpix; }
246		static UINT32 pixel_op02(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix & ~dstpix; }
247		static UINT32 pixel_op03(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return 0; }
248		static UINT32 pixel_op04(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix \| ~dstpix) & mask; }
249		static UINT32 pixel_op05(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~(srcpix ^ dstpix) & mask; }
250		static UINT32 pixel_op06(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~dstpix & mask; }
251		static UINT32 pixel_op07(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~(srcpix \| dstpix) & mask; }
252		static UINT32 pixel_op08(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix \| dstpix) & mask; }
253		static UINT32 pixel_op09(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return dstpix & mask; }
254		static UINT32 pixel_op10(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix ^ dstpix) & mask; }
255		static UINT32 pixel_op11(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (~srcpix & dstpix) & mask; }
256		static UINT32 pixel_op12(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return mask; }
257		static UINT32 pixel_op13(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (~srcpix & dstpix) & mask; }
258		static UINT32 pixel_op14(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~(srcpix & dstpix) & mask; }
259		static UINT32 pixel_op15(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix ^ mask; }
260		static UINT32 pixel_op16(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix + dstpix) & mask; }
261		static UINT32 pixel_op17(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { INT32 tmp = srcpix + (dstpix & mask); return (tmp > mask) ? mask : tmp; }
262		static UINT32 pixel_op18(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (dstpix - srcpix) & mask; }
263		static UINT32 pixel_op19(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { INT32 tmp = srcpix - (dstpix & mask); return (tmp < 0) ? 0 : tmp; }
264		static UINT32 pixel_op20(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { dstpix &= mask; return (srcpix > dstpix) ? srcpix : dstpix; }
265		static UINT32 pixel_op21(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { dstpix &= mask; return (srcpix < dstpix) ? srcpix : dstpix; }
	241	UINT32 tms340x0_device::pixel_op00(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix; }
	242	UINT32 tms340x0_device::pixel_op01(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix & dstpix; }
	243	UINT32 tms340x0_device::pixel_op02(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix & ~dstpix; }
	244	UINT32 tms340x0_device::pixel_op03(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return 0; }
	245	UINT32 tms340x0_device::pixel_op04(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix \| ~dstpix) & mask; }
	246	UINT32 tms340x0_device::pixel_op05(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~(srcpix ^ dstpix) & mask; }
	247	UINT32 tms340x0_device::pixel_op06(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~dstpix & mask; }
	248	UINT32 tms340x0_device::pixel_op07(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~(srcpix \| dstpix) & mask; }
	249	UINT32 tms340x0_device::pixel_op08(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix \| dstpix) & mask; }
	250	UINT32 tms340x0_device::pixel_op09(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return dstpix & mask; }
	251	UINT32 tms340x0_device::pixel_op10(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix ^ dstpix) & mask; }
	252	UINT32 tms340x0_device::pixel_op11(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (~srcpix & dstpix) & mask; }
	253	UINT32 tms340x0_device::pixel_op12(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return mask; }
	254	UINT32 tms340x0_device::pixel_op13(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (~srcpix & dstpix) & mask; }
	255	UINT32 tms340x0_device::pixel_op14(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~(srcpix & dstpix) & mask; }
	256	UINT32 tms340x0_device::pixel_op15(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix ^ mask; }
	257	UINT32 tms340x0_device::pixel_op16(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix + dstpix) & mask; }
	258	UINT32 tms340x0_device::pixel_op17(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { INT32 tmp = srcpix + (dstpix & mask); return (tmp > mask) ? mask : tmp; }
	259	UINT32 tms340x0_device::pixel_op18(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (dstpix - srcpix) & mask; }
	260	UINT32 tms340x0_device::pixel_op19(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { INT32 tmp = srcpix - (dstpix & mask); return (tmp < 0) ? 0 : tmp; }
	261	UINT32 tms340x0_device::pixel_op20(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { dstpix &= mask; return (srcpix > dstpix) ? srcpix : dstpix; }
	262	UINT32 tms340x0_device::pixel_op21(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { dstpix &= mask; return (srcpix < dstpix) ? srcpix : dstpix; }
266	263
267		static ~~UINT~~32 (*const pixel_op_table[~~])(UINT~~32~~, UINT32, UINT32)~~ =
	264	const tms340x0_device::pixel_op_func tms340x0_device::s_pixel_op_table[32] =
268	265	{
269		pixel_op00, pixel_op01, pixel_op02, pixel_op03, pixel_op04, pixel_op05, pixel_op06, pixel_op07,
270		pixel_op08, pixel_op09, pixel_op10, pixel_op11, pixel_op12, pixel_op13, pixel_op14, pixel_op15,
271		pixel_op16, pixel_op17, pixel_op18, pixel_op19, pixel_op20, pixel_op21, pixel_op00, pixel_op00,
272		pixel_op00, pixel_op00, pixel_op00, pixel_op00, pixel_op00, pixel_op00, pixel_op00, pixel_op00
	266	&tms340x0_device::pixel_op00, &tms340x0_device::pixel_op01, &tms340x0_device::pixel_op02, &tms340x0_device::pixel_op03, &tms340x0_device::pixel_op04, &tms340x0_device::pixel_op05, &tms340x0_device::pixel_op06, &tms340x0_device::pixel_op07,
	267	&tms340x0_device::pixel_op08, &tms340x0_device::pixel_op09, &tms340x0_device::pixel_op10, &tms340x0_device::pixel_op11, &tms340x0_device::pixel_op12, &tms340x0_device::pixel_op13, &tms340x0_device::pixel_op14, &tms340x0_device::pixel_op15,
	268	&tms340x0_device::pixel_op16, &tms340x0_device::pixel_op17, &tms340x0_device::pixel_op18, &tms340x0_device::pixel_op19, &tms340x0_device::pixel_op20, &tms340x0_device::pixel_op21, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00,
	269	&tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00
273	270	};
274		~~stati~~c const UINT8 pixel_op_timing_table[] =
	271	const UINT8 tms340x0_device::s_pixel_op_timing_table[33] =
275	272	{
276	273	2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,6,5,5,2,2,2,2,2,2,2,2,2,2,2
277	274	};
278		static UINT32 (*pixel_op)(UINT32, UINT32, UINT32);
279		static UINT32 pixel_op_timing;
280	275
281	276
282		/* Blitters/fillers */
283		static void pixblt_1_op0(tms34010_state *tms, int src_is_linear, int dst_is_linear);
284		static void pixblt_2_op0(tms34010_state *tms, int src_is_linear, int dst_is_linear);
285		static void pixblt_4_op0(tms34010_state *tms, int src_is_linear, int dst_is_linear);
286		static void pixblt_8_op0(tms34010_state *tms, int src_is_linear, int dst_is_linear);
287		static void pixblt_16_op0(tms34010_state *tms, int src_is_linear, int dst_is_linear);
288		static void pixblt_r_1_op0(tms34010_state *tms, int src_is_linear, int dst_is_linear);
289		static void pixblt_r_2_op0(tms34010_state *tms, int src_is_linear, int dst_is_linear);
290		static void pixblt_r_4_op0(tms34010_state *tms, int src_is_linear, int dst_is_linear);
291		static void pixblt_r_8_op0(tms34010_state *tms, int src_is_linear, int dst_is_linear);
292		static void pixblt_r_16_op0(tms34010_state *tms, int src_is_linear, int dst_is_linear);
293		static void pixblt_b_1_op0(tms34010_state *tms, int dst_is_linear);
294		static void pixblt_b_2_op0(tms34010_state *tms, int dst_is_linear);
295		static void pixblt_b_4_op0(tms34010_state *tms, int dst_is_linear);
296		static void pixblt_b_8_op0(tms34010_state *tms, int dst_is_linear);
297		static void pixblt_b_16_op0(tms34010_state *tms, int dst_is_linear);
298		static void fill_1_op0(tms34010_state *tms, int dst_is_linear);
299		static void fill_2_op0(tms34010_state *tms, int dst_is_linear);
300		static void fill_4_op0(tms34010_state *tms, int dst_is_linear);
301		static void fill_8_op0(tms34010_state *tms, int dst_is_linear);
302		static void fill_16_op0(tms34010_state *tms, int dst_is_linear);
303
304		static void pixblt_1_op0_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
305		static void pixblt_2_op0_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
306		static void pixblt_4_op0_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
307		static void pixblt_8_op0_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
308		static void pixblt_16_op0_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
309		static void pixblt_r_1_op0_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
310		static void pixblt_r_2_op0_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
311		static void pixblt_r_4_op0_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
312		static void pixblt_r_8_op0_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
313		static void pixblt_r_16_op0_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
314		static void pixblt_b_1_op0_trans(tms34010_state *tms, int dst_is_linear);
315		static void pixblt_b_2_op0_trans(tms34010_state *tms, int dst_is_linear);
316		static void pixblt_b_4_op0_trans(tms34010_state *tms, int dst_is_linear);
317		static void pixblt_b_8_op0_trans(tms34010_state *tms, int dst_is_linear);
318		static void pixblt_b_16_op0_trans(tms34010_state *tms, int dst_is_linear);
319		static void fill_1_op0_trans(tms34010_state *tms, int dst_is_linear);
320		static void fill_2_op0_trans(tms34010_state *tms, int dst_is_linear);
321		static void fill_4_op0_trans(tms34010_state *tms, int dst_is_linear);
322		static void fill_8_op0_trans(tms34010_state *tms, int dst_is_linear);
323		static void fill_16_op0_trans(tms34010_state *tms, int dst_is_linear);
324
325		static void pixblt_1_opx(tms34010_state *tms, int src_is_linear, int dst_is_linear);
326		static void pixblt_2_opx(tms34010_state *tms, int src_is_linear, int dst_is_linear);
327		static void pixblt_4_opx(tms34010_state *tms, int src_is_linear, int dst_is_linear);
328		static void pixblt_8_opx(tms34010_state *tms, int src_is_linear, int dst_is_linear);
329		static void pixblt_16_opx(tms34010_state *tms, int src_is_linear, int dst_is_linear);
330		static void pixblt_r_1_opx(tms34010_state *tms, int src_is_linear, int dst_is_linear);
331		static void pixblt_r_2_opx(tms34010_state *tms, int src_is_linear, int dst_is_linear);
332		static void pixblt_r_4_opx(tms34010_state *tms, int src_is_linear, int dst_is_linear);
333		static void pixblt_r_8_opx(tms34010_state *tms, int src_is_linear, int dst_is_linear);
334		static void pixblt_r_16_opx(tms34010_state *tms, int src_is_linear, int dst_is_linear);
335		static void pixblt_b_1_opx(tms34010_state *tms, int dst_is_linear);
336		static void pixblt_b_2_opx(tms34010_state *tms, int dst_is_linear);
337		static void pixblt_b_4_opx(tms34010_state *tms, int dst_is_linear);
338		static void pixblt_b_8_opx(tms34010_state *tms, int dst_is_linear);
339		static void pixblt_b_16_opx(tms34010_state *tms, int dst_is_linear);
340		static void fill_1_opx(tms34010_state *tms, int dst_is_linear);
341		static void fill_2_opx(tms34010_state *tms, int dst_is_linear);
342		static void fill_4_opx(tms34010_state *tms, int dst_is_linear);
343		static void fill_8_opx(tms34010_state *tms, int dst_is_linear);
344		static void fill_16_opx(tms34010_state *tms, int dst_is_linear);
345
346		static void pixblt_1_opx_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
347		static void pixblt_2_opx_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
348		static void pixblt_4_opx_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
349		static void pixblt_8_opx_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
350		static void pixblt_16_opx_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
351		static void pixblt_r_1_opx_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
352		static void pixblt_r_2_opx_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
353		static void pixblt_r_4_opx_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
354		static void pixblt_r_8_opx_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
355		static void pixblt_r_16_opx_trans(tms34010_state *tms, int src_is_linear, int dst_is_linear);
356		static void pixblt_b_1_opx_trans(tms34010_state *tms, int dst_is_linear);
357		static void pixblt_b_2_opx_trans(tms34010_state *tms, int dst_is_linear);
358		static void pixblt_b_4_opx_trans(tms34010_state *tms, int dst_is_linear);
359		static void pixblt_b_8_opx_trans(tms34010_state *tms, int dst_is_linear);
360		static void pixblt_b_16_opx_trans(tms34010_state *tms, int dst_is_linear);
361		static void fill_1_opx_trans(tms34010_state *tms, int dst_is_linear);
362		static void fill_2_opx_trans(tms34010_state *tms, int dst_is_linear);
363		static void fill_4_opx_trans(tms34010_state *tms, int dst_is_linear);
364		static void fill_8_opx_trans(tms34010_state *tms, int dst_is_linear);
365		static void fill_16_opx_trans(tms34010_state *tms, int dst_is_linear);
366
367
368	277	/* tables */
369		~~stati~~c vo~~id (co~~nst pixblt_op_t~~able[])(t~~ms34010_~~stat~~e , i~~nt,~~ int) =
	278	const tms340x0_device::pixblt_op_func tms340x0_device::s_pixblt_op_table[] =
370	279	{
371		pixblt_1_op0, pixblt_1_op0_trans, pixblt_1_opx, pixblt_1_opx_trans,
372		pixblt_1_opx, pixblt_1_opx_trans, pixblt_1_opx, pixblt_1_opx_trans,
373		pixblt_1_opx, pixblt_1_opx_trans, pixblt_1_opx, pixblt_1_opx_trans,
374		pixblt_1_opx, pixblt_1_opx_trans, pixblt_1_opx, pixblt_1_opx_trans,
375		pixblt_1_opx, pixblt_1_opx_trans, pixblt_1_opx, pixblt_1_opx_trans,
376		pixblt_1_opx, pixblt_1_opx_trans, pixblt_1_opx, pixblt_1_opx_trans,
377		pixblt_1_opx, pixblt_1_opx_trans, pixblt_1_opx, pixblt_1_opx_trans,
378		pixblt_1_opx, pixblt_1_opx_trans, pixblt_1_opx, pixblt_1_opx_trans,
379		pixblt_1_opx, pixblt_1_opx_trans, pixblt_1_opx, pixblt_1_opx_trans,
380		pixblt_1_opx, pixblt_1_opx_trans, pixblt_1_opx, pixblt_1_opx_trans,
381		pixblt_1_opx, pixblt_1_opx_trans, pixblt_1_opx, pixblt_1_opx_trans,
382		pixblt_1_opx, pixblt_1_opx_trans, pixblt_1_opx, pixblt_1_opx_trans,
383		pixblt_1_opx, pixblt_1_opx_trans, pixblt_1_opx, pixblt_1_opx_trans,
384		pixblt_1_opx, pixblt_1_opx_trans, pixblt_1_opx, pixblt_1_opx_trans,
385		pixblt_1_opx, pixblt_1_opx_trans, pixblt_1_opx, pixblt_1_opx_trans,
386		pixblt_1_opx, pixblt_1_opx_trans, pixblt_1_opx, pixblt_1_opx_trans,
	280	&tms340x0_device::pixblt_1_op0, &tms340x0_device::pixblt_1_op0_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans,
	281	&tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans,
	282	&tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans,
	283	&tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans,
	284	&tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans,
	285	&tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans,
	286	&tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans,
	287	&tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans,
	288	&tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans,
	289	&tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans,
	290	&tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans,
	291	&tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans,
	292	&tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans,
	293	&tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans,
	294	&tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans,
	295	&tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans,
387	296
388		pixblt_2_op0, pixblt_2_op0_trans, pixblt_2_opx, pixblt_2_opx_trans,
389		pixblt_2_opx, pixblt_2_opx_trans, pixblt_2_opx, pixblt_2_opx_trans,
390		pixblt_2_opx, pixblt_2_opx_trans, pixblt_2_opx, pixblt_2_opx_trans,
391		pixblt_2_opx, pixblt_2_opx_trans, pixblt_2_opx, pixblt_2_opx_trans,
392		pixblt_2_opx, pixblt_2_opx_trans, pixblt_2_opx, pixblt_2_opx_trans,
393		pixblt_2_opx, pixblt_2_opx_trans, pixblt_2_opx, pixblt_2_opx_trans,
394		pixblt_2_opx, pixblt_2_opx_trans, pixblt_2_opx, pixblt_2_opx_trans,
395		pixblt_2_opx, pixblt_2_opx_trans, pixblt_2_opx, pixblt_2_opx_trans,
396		pixblt_2_opx, pixblt_2_opx_trans, pixblt_2_opx, pixblt_2_opx_trans,
397		pixblt_2_opx, pixblt_2_opx_trans, pixblt_2_opx, pixblt_2_opx_trans,
398		pixblt_2_opx, pixblt_2_opx_trans, pixblt_2_opx, pixblt_2_opx_trans,
399		pixblt_2_opx, pixblt_2_opx_trans, pixblt_2_opx, pixblt_2_opx_trans,
400		pixblt_2_opx, pixblt_2_opx_trans, pixblt_2_opx, pixblt_2_opx_trans,
401		pixblt_2_opx, pixblt_2_opx_trans, pixblt_2_opx, pixblt_2_opx_trans,
402		pixblt_2_opx, pixblt_2_opx_trans, pixblt_2_opx, pixblt_2_opx_trans,
403		pixblt_2_opx, pixblt_2_opx_trans, pixblt_2_opx, pixblt_2_opx_trans,
	297	&tms340x0_device::pixblt_2_op0, &tms340x0_device::pixblt_2_op0_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans,
	298	&tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans,
	299	&tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans,
	300	&tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans,
	301	&tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans,
	302	&tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans,
	303	&tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans,
	304	&tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans,
	305	&tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans,
	306	&tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans,
	307	&tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans,
	308	&tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans,
	309	&tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans,
	310	&tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans,
	311	&tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans,
	312	&tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans,
404	313
405		pixblt_4_op0, pixblt_4_op0_trans, pixblt_4_opx, pixblt_4_opx_trans,
406		pixblt_4_opx, pixblt_4_opx_trans, pixblt_4_opx, pixblt_4_opx_trans,
407		pixblt_4_opx, pixblt_4_opx_trans, pixblt_4_opx, pixblt_4_opx_trans,
408		pixblt_4_opx, pixblt_4_opx_trans, pixblt_4_opx, pixblt_4_opx_trans,
409		pixblt_4_opx, pixblt_4_opx_trans, pixblt_4_opx, pixblt_4_opx_trans,
410		pixblt_4_opx, pixblt_4_opx_trans, pixblt_4_opx, pixblt_4_opx_trans,
411		pixblt_4_opx, pixblt_4_opx_trans, pixblt_4_opx, pixblt_4_opx_trans,
412		pixblt_4_opx, pixblt_4_opx_trans, pixblt_4_opx, pixblt_4_opx_trans,
413		pixblt_4_opx, pixblt_4_opx_trans, pixblt_4_opx, pixblt_4_opx_trans,
414		pixblt_4_opx, pixblt_4_opx_trans, pixblt_4_opx, pixblt_4_opx_trans,
415		pixblt_4_opx, pixblt_4_opx_trans, pixblt_4_opx, pixblt_4_opx_trans,
416		pixblt_4_opx, pixblt_4_opx_trans, pixblt_4_opx, pixblt_4_opx_trans,
417		pixblt_4_opx, pixblt_4_opx_trans, pixblt_4_opx, pixblt_4_opx_trans,
418		pixblt_4_opx, pixblt_4_opx_trans, pixblt_4_opx, pixblt_4_opx_trans,
419		pixblt_4_opx, pixblt_4_opx_trans, pixblt_4_opx, pixblt_4_opx_trans,
420		pixblt_4_opx, pixblt_4_opx_trans, pixblt_4_opx, pixblt_4_opx_trans,
	314	&tms340x0_device::pixblt_4_op0, &tms340x0_device::pixblt_4_op0_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans,
	315	&tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans,
	316	&tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans,
	317	&tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans,
	318	&tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans,
	319	&tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans,
	320	&tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans,
	321	&tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans,
	322	&tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans,
	323	&tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans,
	324	&tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans,
	325	&tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans,
	326	&tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans,
	327	&tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans,
	328	&tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans,
	329	&tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans,
421	330
422		pixblt_8_op0, pixblt_8_op0_trans, pixblt_8_opx, pixblt_8_opx_trans,
423		pixblt_8_opx, pixblt_8_opx_trans, pixblt_8_opx, pixblt_8_opx_trans,
424		pixblt_8_opx, pixblt_8_opx_trans, pixblt_8_opx, pixblt_8_opx_trans,
425		pixblt_8_opx, pixblt_8_opx_trans, pixblt_8_opx, pixblt_8_opx_trans,
426		pixblt_8_opx, pixblt_8_opx_trans, pixblt_8_opx, pixblt_8_opx_trans,
427		pixblt_8_opx, pixblt_8_opx_trans, pixblt_8_opx, pixblt_8_opx_trans,
428		pixblt_8_opx, pixblt_8_opx_trans, pixblt_8_opx, pixblt_8_opx_trans,
429		pixblt_8_opx, pixblt_8_opx_trans, pixblt_8_opx, pixblt_8_opx_trans,
430		pixblt_8_opx, pixblt_8_opx_trans, pixblt_8_opx, pixblt_8_opx_trans,
431		pixblt_8_opx, pixblt_8_opx_trans, pixblt_8_opx, pixblt_8_opx_trans,
432		pixblt_8_opx, pixblt_8_opx_trans, pixblt_8_opx, pixblt_8_opx_trans,
433		pixblt_8_opx, pixblt_8_opx_trans, pixblt_8_opx, pixblt_8_opx_trans,
434		pixblt_8_opx, pixblt_8_opx_trans, pixblt_8_opx, pixblt_8_opx_trans,
435		pixblt_8_opx, pixblt_8_opx_trans, pixblt_8_opx, pixblt_8_opx_trans,
436		pixblt_8_opx, pixblt_8_opx_trans, pixblt_8_opx, pixblt_8_opx_trans,
437		pixblt_8_opx, pixblt_8_opx_trans, pixblt_8_opx, pixblt_8_opx_trans,
	331	&tms340x0_device::pixblt_8_op0, &tms340x0_device::pixblt_8_op0_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans,
	332	&tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans,
	333	&tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans,
	334	&tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans,
	335	&tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans,
	336	&tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans,
	337	&tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans,
	338	&tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans,
	339	&tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans,
	340	&tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans,
	341	&tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans,
	342	&tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans,
	343	&tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans,
	344	&tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans,
	345	&tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans,
	346	&tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans,
438	347
439		pixblt_16_op0, pixblt_16_op0_trans, pixblt_16_opx, pixblt_16_opx_trans,
440		pixblt_16_opx, pixblt_16_opx_trans, pixblt_16_opx, pixblt_16_opx_trans,
441		pixblt_16_opx, pixblt_16_opx_trans, pixblt_16_opx, pixblt_16_opx_trans,
442		pixblt_16_opx, pixblt_16_opx_trans, pixblt_16_opx, pixblt_16_opx_trans,
443		pixblt_16_opx, pixblt_16_opx_trans, pixblt_16_opx, pixblt_16_opx_trans,
444		pixblt_16_opx, pixblt_16_opx_trans, pixblt_16_opx, pixblt_16_opx_trans,
445		pixblt_16_opx, pixblt_16_opx_trans, pixblt_16_opx, pixblt_16_opx_trans,
446		pixblt_16_opx, pixblt_16_opx_trans, pixblt_16_opx, pixblt_16_opx_trans,
447		pixblt_16_opx, pixblt_16_opx_trans, pixblt_16_opx, pixblt_16_opx_trans,
448		pixblt_16_opx, pixblt_16_opx_trans, pixblt_16_opx, pixblt_16_opx_trans,
449		pixblt_16_opx, pixblt_16_opx_trans, pixblt_16_opx, pixblt_16_opx_trans,
450		pixblt_16_opx, pixblt_16_opx_trans, pixblt_16_opx, pixblt_16_opx_trans,
451		pixblt_16_opx, pixblt_16_opx_trans, pixblt_16_opx, pixblt_16_opx_trans,
452		pixblt_16_opx, pixblt_16_opx_trans, pixblt_16_opx, pixblt_16_opx_trans,
453		pixblt_16_opx, pixblt_16_opx_trans, pixblt_16_opx, pixblt_16_opx_trans,
454		pixblt_16_opx, pixblt_16_opx_trans, pixblt_16_opx, pixblt_16_opx_trans
	348	&tms340x0_device::pixblt_16_op0, &tms340x0_device::pixblt_16_op0_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans,
	349	&tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans,
	350	&tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans,
	351	&tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans,
	352	&tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans,
	353	&tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans,
	354	&tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans,
	355	&tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans,
	356	&tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans,
	357	&tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans,
	358	&tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans,
	359	&tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans,
	360	&tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans,
	361	&tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans,
	362	&tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans,
	363	&tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans
455	364	};
456	365
457		static void (const pixblt_r_op_table[]~~)(tms34010_state , int, int)~~ =
	366	const tms340x0_device::pixblt_op_func tms340x0_device::s_pixblt_r_op_table[] =
458	367	{
459		pixblt_r_1_op0, pixblt_r_1_op0_trans, pixblt_r_1_opx, pixblt_r_1_opx_trans,
460		pixblt_r_1_opx, pixblt_r_1_opx_trans, pixblt_r_1_opx, pixblt_r_1_opx_trans,
461		pixblt_r_1_opx, pixblt_r_1_opx_trans, pixblt_r_1_opx, pixblt_r_1_opx_trans,
462		pixblt_r_1_opx, pixblt_r_1_opx_trans, pixblt_r_1_opx, pixblt_r_1_opx_trans,
463		pixblt_r_1_opx, pixblt_r_1_opx_trans, pixblt_r_1_opx, pixblt_r_1_opx_trans,
464		pixblt_r_1_opx, pixblt_r_1_opx_trans, pixblt_r_1_opx, pixblt_r_1_opx_trans,
465		pixblt_r_1_opx, pixblt_r_1_opx_trans, pixblt_r_1_opx, pixblt_r_1_opx_trans,
466		pixblt_r_1_opx, pixblt_r_1_opx_trans, pixblt_r_1_opx, pixblt_r_1_opx_trans,
467		pixblt_r_1_opx, pixblt_r_1_opx_trans, pixblt_r_1_opx, pixblt_r_1_opx_trans,
468		pixblt_r_1_opx, pixblt_r_1_opx_trans, pixblt_r_1_opx, pixblt_r_1_opx_trans,
469		pixblt_r_1_opx, pixblt_r_1_opx_trans, pixblt_r_1_opx, pixblt_r_1_opx_trans,
470		pixblt_r_1_opx, pixblt_r_1_opx_trans, pixblt_r_1_opx, pixblt_r_1_opx_trans,
471		pixblt_r_1_opx, pixblt_r_1_opx_trans, pixblt_r_1_opx, pixblt_r_1_opx_trans,
472		pixblt_r_1_opx, pixblt_r_1_opx_trans, pixblt_r_1_opx, pixblt_r_1_opx_trans,
473		pixblt_r_1_opx, pixblt_r_1_opx_trans, pixblt_r_1_opx, pixblt_r_1_opx_trans,
474		pixblt_r_1_opx, pixblt_r_1_opx_trans, pixblt_r_1_opx, pixblt_r_1_opx_trans,
	368	&tms340x0_device::pixblt_r_1_op0, &tms340x0_device::pixblt_r_1_op0_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans,
	369	&tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans,
	370	&tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans,
	371	&tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans,
	372	&tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans,
	373	&tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans,
	374	&tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans,
	375	&tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans,
	376	&tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans,
	377	&tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans,
	378	&tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans,
	379	&tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans,
	380	&tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans,
	381	&tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans,
	382	&tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans,
	383	&tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans,
475	384
476		pixblt_r_2_op0, pixblt_r_2_op0_trans, pixblt_r_2_opx, pixblt_r_2_opx_trans,
477		pixblt_r_2_opx, pixblt_r_2_opx_trans, pixblt_r_2_opx, pixblt_r_2_opx_trans,
478		pixblt_r_2_opx, pixblt_r_2_opx_trans, pixblt_r_2_opx, pixblt_r_2_opx_trans,
479		pixblt_r_2_opx, pixblt_r_2_opx_trans, pixblt_r_2_opx, pixblt_r_2_opx_trans,
480		pixblt_r_2_opx, pixblt_r_2_opx_trans, pixblt_r_2_opx, pixblt_r_2_opx_trans,
481		pixblt_r_2_opx, pixblt_r_2_opx_trans, pixblt_r_2_opx, pixblt_r_2_opx_trans,
482		pixblt_r_2_opx, pixblt_r_2_opx_trans, pixblt_r_2_opx, pixblt_r_2_opx_trans,
483		pixblt_r_2_opx, pixblt_r_2_opx_trans, pixblt_r_2_opx, pixblt_r_2_opx_trans,
484		pixblt_r_2_opx, pixblt_r_2_opx_trans, pixblt_r_2_opx, pixblt_r_2_opx_trans,
485		pixblt_r_2_opx, pixblt_r_2_opx_trans, pixblt_r_2_opx, pixblt_r_2_opx_trans,
486		pixblt_r_2_opx, pixblt_r_2_opx_trans, pixblt_r_2_opx, pixblt_r_2_opx_trans,
487		pixblt_r_2_opx, pixblt_r_2_opx_trans, pixblt_r_2_opx, pixblt_r_2_opx_trans,
488		pixblt_r_2_opx, pixblt_r_2_opx_trans, pixblt_r_2_opx, pixblt_r_2_opx_trans,
489		pixblt_r_2_opx, pixblt_r_2_opx_trans, pixblt_r_2_opx, pixblt_r_2_opx_trans,
490		pixblt_r_2_opx, pixblt_r_2_opx_trans, pixblt_r_2_opx, pixblt_r_2_opx_trans,
491		pixblt_r_2_opx, pixblt_r_2_opx_trans, pixblt_r_2_opx, pixblt_r_2_opx_trans,
	385	&tms340x0_device::pixblt_r_2_op0, &tms340x0_device::pixblt_r_2_op0_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans,
	386	&tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans,
	387	&tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans,
	388	&tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans,
	389	&tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans,
	390	&tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans,
	391	&tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans,
	392	&tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans,
	393	&tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans,
	394	&tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans,
	395	&tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans,
	396	&tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans,
	397	&tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans,
	398	&tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans,
	399	&tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans,
	400	&tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans,
492	401
493		pixblt_r_4_op0, pixblt_r_4_op0_trans, pixblt_r_4_opx, pixblt_r_4_opx_trans,
494		pixblt_r_4_opx, pixblt_r_4_opx_trans, pixblt_r_4_opx, pixblt_r_4_opx_trans,
495		pixblt_r_4_opx, pixblt_r_4_opx_trans, pixblt_r_4_opx, pixblt_r_4_opx_trans,
496		pixblt_r_4_opx, pixblt_r_4_opx_trans, pixblt_r_4_opx, pixblt_r_4_opx_trans,
497		pixblt_r_4_opx, pixblt_r_4_opx_trans, pixblt_r_4_opx, pixblt_r_4_opx_trans,
498		pixblt_r_4_opx, pixblt_r_4_opx_trans, pixblt_r_4_opx, pixblt_r_4_opx_trans,
499		pixblt_r_4_opx, pixblt_r_4_opx_trans, pixblt_r_4_opx, pixblt_r_4_opx_trans,
500		pixblt_r_4_opx, pixblt_r_4_opx_trans, pixblt_r_4_opx, pixblt_r_4_opx_trans,
501		pixblt_r_4_opx, pixblt_r_4_opx_trans, pixblt_r_4_opx, pixblt_r_4_opx_trans,
502		pixblt_r_4_opx, pixblt_r_4_opx_trans, pixblt_r_4_opx, pixblt_r_4_opx_trans,
503		pixblt_r_4_opx, pixblt_r_4_opx_trans, pixblt_r_4_opx, pixblt_r_4_opx_trans,
504		pixblt_r_4_opx, pixblt_r_4_opx_trans, pixblt_r_4_opx, pixblt_r_4_opx_trans,
505		pixblt_r_4_opx, pixblt_r_4_opx_trans, pixblt_r_4_opx, pixblt_r_4_opx_trans,
506		pixblt_r_4_opx, pixblt_r_4_opx_trans, pixblt_r_4_opx, pixblt_r_4_opx_trans,
507		pixblt_r_4_opx, pixblt_r_4_opx_trans, pixblt_r_4_opx, pixblt_r_4_opx_trans,
508		pixblt_r_4_opx, pixblt_r_4_opx_trans, pixblt_r_4_opx, pixblt_r_4_opx_trans,
	402	&tms340x0_device::pixblt_r_4_op0, &tms340x0_device::pixblt_r_4_op0_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans,
	403	&tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans,
	404	&tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans,
	405	&tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans,
	406	&tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans,
	407	&tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans,
	408	&tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans,
	409	&tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans,
	410	&tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans,
	411	&tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans,
	412	&tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans,
	413	&tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans,
	414	&tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans,
	415	&tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans,
	416	&tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans,
	417	&tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans,
509	418
510		pixblt_r_8_op0, pixblt_r_8_op0_trans, pixblt_r_8_opx, pixblt_r_8_opx_trans,
511		pixblt_r_8_opx, pixblt_r_8_opx_trans, pixblt_r_8_opx, pixblt_r_8_opx_trans,
512		pixblt_r_8_opx, pixblt_r_8_opx_trans, pixblt_r_8_opx, pixblt_r_8_opx_trans,
513		pixblt_r_8_opx, pixblt_r_8_opx_trans, pixblt_r_8_opx, pixblt_r_8_opx_trans,
514		pixblt_r_8_opx, pixblt_r_8_opx_trans, pixblt_r_8_opx, pixblt_r_8_opx_trans,
515		pixblt_r_8_opx, pixblt_r_8_opx_trans, pixblt_r_8_opx, pixblt_r_8_opx_trans,
516		pixblt_r_8_opx, pixblt_r_8_opx_trans, pixblt_r_8_opx, pixblt_r_8_opx_trans,
517		pixblt_r_8_opx, pixblt_r_8_opx_trans, pixblt_r_8_opx, pixblt_r_8_opx_trans,
518		pixblt_r_8_opx, pixblt_r_8_opx_trans, pixblt_r_8_opx, pixblt_r_8_opx_trans,
519		pixblt_r_8_opx, pixblt_r_8_opx_trans, pixblt_r_8_opx, pixblt_r_8_opx_trans,
520		pixblt_r_8_opx, pixblt_r_8_opx_trans, pixblt_r_8_opx, pixblt_r_8_opx_trans,
521		pixblt_r_8_opx, pixblt_r_8_opx_trans, pixblt_r_8_opx, pixblt_r_8_opx_trans,
522		pixblt_r_8_opx, pixblt_r_8_opx_trans, pixblt_r_8_opx, pixblt_r_8_opx_trans,
523		pixblt_r_8_opx, pixblt_r_8_opx_trans, pixblt_r_8_opx, pixblt_r_8_opx_trans,
524		pixblt_r_8_opx, pixblt_r_8_opx_trans, pixblt_r_8_opx, pixblt_r_8_opx_trans,
525		pixblt_r_8_opx, pixblt_r_8_opx_trans, pixblt_r_8_opx, pixblt_r_8_opx_trans,
	419	&tms340x0_device::pixblt_r_8_op0, &tms340x0_device::pixblt_r_8_op0_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans,
	420	&tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans,
	421	&tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans,
	422	&tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans,
	423	&tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans,
	424	&tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans,
	425	&tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans,
	426	&tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans,
	427	&tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans,
	428	&tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans,
	429	&tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans,
	430	&tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans,
	431	&tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans,
	432	&tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans,
	433	&tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans,
	434	&tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans,
526	435
527		pixblt_r_16_op0,pixblt_r_16_op0_trans, pixblt_r_16_opx,pixblt_r_16_opx_trans,
528		pixblt_r_16_opx,pixblt_r_16_opx_trans, pixblt_r_16_opx,pixblt_r_16_opx_trans,
529		pixblt_r_16_opx,pixblt_r_16_opx_trans, pixblt_r_16_opx,pixblt_r_16_opx_trans,
530		pixblt_r_16_opx,pixblt_r_16_opx_trans, pixblt_r_16_opx,pixblt_r_16_opx_trans,
531		pixblt_r_16_opx,pixblt_r_16_opx_trans, pixblt_r_16_opx,pixblt_r_16_opx_trans,
532		pixblt_r_16_opx,pixblt_r_16_opx_trans, pixblt_r_16_opx,pixblt_r_16_opx_trans,
533		pixblt_r_16_opx,pixblt_r_16_opx_trans, pixblt_r_16_opx,pixblt_r_16_opx_trans,
534		pixblt_r_16_opx,pixblt_r_16_opx_trans, pixblt_r_16_opx,pixblt_r_16_opx_trans,
535		pixblt_r_16_opx,pixblt_r_16_opx_trans, pixblt_r_16_opx,pixblt_r_16_opx_trans,
536		pixblt_r_16_opx,pixblt_r_16_opx_trans, pixblt_r_16_opx,pixblt_r_16_opx_trans,
537		pixblt_r_16_opx,pixblt_r_16_opx_trans, pixblt_r_16_opx,pixblt_r_16_opx_trans,
538		pixblt_r_16_opx,pixblt_r_16_opx_trans, pixblt_r_16_opx,pixblt_r_16_opx_trans,
539		pixblt_r_16_opx,pixblt_r_16_opx_trans, pixblt_r_16_opx,pixblt_r_16_opx_trans,
540		pixblt_r_16_opx,pixblt_r_16_opx_trans, pixblt_r_16_opx,pixblt_r_16_opx_trans,
541		pixblt_r_16_opx,pixblt_r_16_opx_trans, pixblt_r_16_opx,pixblt_r_16_opx_trans,
542		pixblt_r_16_opx,pixblt_r_16_opx_trans, pixblt_r_16_opx,pixblt_r_16_opx_trans
	436	&tms340x0_device::pixblt_r_16_op0,&tms340x0_device::pixblt_r_16_op0_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans,
	437	&tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans,
	438	&tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans,
	439	&tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans,
	440	&tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans,
	441	&tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans,
	442	&tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans,
	443	&tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans,
	444	&tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans,
	445	&tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans,
	446	&tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans,
	447	&tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans,
	448	&tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans,
	449	&tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans,
	450	&tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans,
	451	&tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans
543	452	};
544	453
545		~~stati~~c vo~~id (co~~nst pixblt_b_op_t~~able[])(t~~ms34010_state , int) =
	454	const tms340x0_device::pixblt_b_op_func tms340x0_device::s_pixblt_b_op_table[] =
546	455	{
547		pixblt_b_1_op0, pixblt_b_1_op0_trans, pixblt_b_1_opx, pixblt_b_1_opx_trans,
548		pixblt_b_1_opx, pixblt_b_1_opx_trans, pixblt_b_1_opx, pixblt_b_1_opx_trans,
549		pixblt_b_1_opx, pixblt_b_1_opx_trans, pixblt_b_1_opx, pixblt_b_1_opx_trans,
550		pixblt_b_1_opx, pixblt_b_1_opx_trans, pixblt_b_1_opx, pixblt_b_1_opx_trans,
551		pixblt_b_1_opx, pixblt_b_1_opx_trans, pixblt_b_1_opx, pixblt_b_1_opx_trans,
552		pixblt_b_1_opx, pixblt_b_1_opx_trans, pixblt_b_1_opx, pixblt_b_1_opx_trans,
553		pixblt_b_1_opx, pixblt_b_1_opx_trans, pixblt_b_1_opx, pixblt_b_1_opx_trans,
554		pixblt_b_1_opx, pixblt_b_1_opx_trans, pixblt_b_1_opx, pixblt_b_1_opx_trans,
555		pixblt_b_1_opx, pixblt_b_1_opx_trans, pixblt_b_1_opx, pixblt_b_1_opx_trans,
556		pixblt_b_1_opx, pixblt_b_1_opx_trans, pixblt_b_1_opx, pixblt_b_1_opx_trans,
557		pixblt_b_1_opx, pixblt_b_1_opx_trans, pixblt_b_1_opx, pixblt_b_1_opx_trans,
558		pixblt_b_1_opx, pixblt_b_1_opx_trans, pixblt_b_1_opx, pixblt_b_1_opx_trans,
559		pixblt_b_1_opx, pixblt_b_1_opx_trans, pixblt_b_1_opx, pixblt_b_1_opx_trans,
560		pixblt_b_1_opx, pixblt_b_1_opx_trans, pixblt_b_1_opx, pixblt_b_1_opx_trans,
561		pixblt_b_1_opx, pixblt_b_1_opx_trans, pixblt_b_1_opx, pixblt_b_1_opx_trans,
562		pixblt_b_1_opx, pixblt_b_1_opx_trans, pixblt_b_1_opx, pixblt_b_1_opx_trans,
	456	&tms340x0_device::pixblt_b_1_op0, &tms340x0_device::pixblt_b_1_op0_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans,
	457	&tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans,
	458	&tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans,
	459	&tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans,
	460	&tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans,
	461	&tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans,
	462	&tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans,
	463	&tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans,
	464	&tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans,
	465	&tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans,
	466	&tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans,
	467	&tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans,
	468	&tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans,
	469	&tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans,
	470	&tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans,
	471	&tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans,
563	472
564		pixblt_b_2_op0, pixblt_b_2_op0_trans, pixblt_b_2_opx, pixblt_b_2_opx_trans,
565		pixblt_b_2_opx, pixblt_b_2_opx_trans, pixblt_b_2_opx, pixblt_b_2_opx_trans,
566		pixblt_b_2_opx, pixblt_b_2_opx_trans, pixblt_b_2_opx, pixblt_b_2_opx_trans,
567		pixblt_b_2_opx, pixblt_b_2_opx_trans, pixblt_b_2_opx, pixblt_b_2_opx_trans,
568		pixblt_b_2_opx, pixblt_b_2_opx_trans, pixblt_b_2_opx, pixblt_b_2_opx_trans,
569		pixblt_b_2_opx, pixblt_b_2_opx_trans, pixblt_b_2_opx, pixblt_b_2_opx_trans,
570		pixblt_b_2_opx, pixblt_b_2_opx_trans, pixblt_b_2_opx, pixblt_b_2_opx_trans,
571		pixblt_b_2_opx, pixblt_b_2_opx_trans, pixblt_b_2_opx, pixblt_b_2_opx_trans,
572		pixblt_b_2_opx, pixblt_b_2_opx_trans, pixblt_b_2_opx, pixblt_b_2_opx_trans,
573		pixblt_b_2_opx, pixblt_b_2_opx_trans, pixblt_b_2_opx, pixblt_b_2_opx_trans,
574		pixblt_b_2_opx, pixblt_b_2_opx_trans, pixblt_b_2_opx, pixblt_b_2_opx_trans,
575		pixblt_b_2_opx, pixblt_b_2_opx_trans, pixblt_b_2_opx, pixblt_b_2_opx_trans,
576		pixblt_b_2_opx, pixblt_b_2_opx_trans, pixblt_b_2_opx, pixblt_b_2_opx_trans,
577		pixblt_b_2_opx, pixblt_b_2_opx_trans, pixblt_b_2_opx, pixblt_b_2_opx_trans,
578		pixblt_b_2_opx, pixblt_b_2_opx_trans, pixblt_b_2_opx, pixblt_b_2_opx_trans,
579		pixblt_b_2_opx, pixblt_b_2_opx_trans, pixblt_b_2_opx, pixblt_b_2_opx_trans,
	473	&tms340x0_device::pixblt_b_2_op0, &tms340x0_device::pixblt_b_2_op0_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans,
	474	&tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans,
	475	&tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans,
	476	&tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans,
	477	&tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans,
	478	&tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans,
	479	&tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans,
	480	&tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans,
	481	&tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans,
	482	&tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans,
	483	&tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans,
	484	&tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans,
	485	&tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans,
	486	&tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans,
	487	&tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans,
	488	&tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans,
580	489
581		pixblt_b_4_op0, pixblt_b_4_op0_trans, pixblt_b_4_opx, pixblt_b_4_opx_trans,
582		pixblt_b_4_opx, pixblt_b_4_opx_trans, pixblt_b_4_opx, pixblt_b_4_opx_trans,
583		pixblt_b_4_opx, pixblt_b_4_opx_trans, pixblt_b_4_opx, pixblt_b_4_opx_trans,
584		pixblt_b_4_opx, pixblt_b_4_opx_trans, pixblt_b_4_opx, pixblt_b_4_opx_trans,
585		pixblt_b_4_opx, pixblt_b_4_opx_trans, pixblt_b_4_opx, pixblt_b_4_opx_trans,
586		pixblt_b_4_opx, pixblt_b_4_opx_trans, pixblt_b_4_opx, pixblt_b_4_opx_trans,
587		pixblt_b_4_opx, pixblt_b_4_opx_trans, pixblt_b_4_opx, pixblt_b_4_opx_trans,
588		pixblt_b_4_opx, pixblt_b_4_opx_trans, pixblt_b_4_opx, pixblt_b_4_opx_trans,
589		pixblt_b_4_opx, pixblt_b_4_opx_trans, pixblt_b_4_opx, pixblt_b_4_opx_trans,
590		pixblt_b_4_opx, pixblt_b_4_opx_trans, pixblt_b_4_opx, pixblt_b_4_opx_trans,
591		pixblt_b_4_opx, pixblt_b_4_opx_trans, pixblt_b_4_opx, pixblt_b_4_opx_trans,
592		pixblt_b_4_opx, pixblt_b_4_opx_trans, pixblt_b_4_opx, pixblt_b_4_opx_trans,
593		pixblt_b_4_opx, pixblt_b_4_opx_trans, pixblt_b_4_opx, pixblt_b_4_opx_trans,
594		pixblt_b_4_opx, pixblt_b_4_opx_trans, pixblt_b_4_opx, pixblt_b_4_opx_trans,
595		pixblt_b_4_opx, pixblt_b_4_opx_trans, pixblt_b_4_opx, pixblt_b_4_opx_trans,
596		pixblt_b_4_opx, pixblt_b_4_opx_trans, pixblt_b_4_opx, pixblt_b_4_opx_trans,
	490	&tms340x0_device::pixblt_b_4_op0, &tms340x0_device::pixblt_b_4_op0_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans,
	491	&tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans,
	492	&tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans,
	493	&tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans,
	494	&tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans,
	495	&tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans,
	496	&tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans,
	497	&tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans,
	498	&tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans,
	499	&tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans,
	500	&tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans,
	501	&tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans,
	502	&tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans,
	503	&tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans,
	504	&tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans,
	505	&tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans,
597	506
598		pixblt_b_8_op0, pixblt_b_8_op0_trans, pixblt_b_8_opx, pixblt_b_8_opx_trans,
599		pixblt_b_8_opx, pixblt_b_8_opx_trans, pixblt_b_8_opx, pixblt_b_8_opx_trans,
600		pixblt_b_8_opx, pixblt_b_8_opx_trans, pixblt_b_8_opx, pixblt_b_8_opx_trans,
601		pixblt_b_8_opx, pixblt_b_8_opx_trans, pixblt_b_8_opx, pixblt_b_8_opx_trans,
602		pixblt_b_8_opx, pixblt_b_8_opx_trans, pixblt_b_8_opx, pixblt_b_8_opx_trans,
603		pixblt_b_8_opx, pixblt_b_8_opx_trans, pixblt_b_8_opx, pixblt_b_8_opx_trans,
604		pixblt_b_8_opx, pixblt_b_8_opx_trans, pixblt_b_8_opx, pixblt_b_8_opx_trans,
605		pixblt_b_8_opx, pixblt_b_8_opx_trans, pixblt_b_8_opx, pixblt_b_8_opx_trans,
606		pixblt_b_8_opx, pixblt_b_8_opx_trans, pixblt_b_8_opx, pixblt_b_8_opx_trans,
607		pixblt_b_8_opx, pixblt_b_8_opx_trans, pixblt_b_8_opx, pixblt_b_8_opx_trans,
608		pixblt_b_8_opx, pixblt_b_8_opx_trans, pixblt_b_8_opx, pixblt_b_8_opx_trans,
609		pixblt_b_8_opx, pixblt_b_8_opx_trans, pixblt_b_8_opx, pixblt_b_8_opx_trans,
610		pixblt_b_8_opx, pixblt_b_8_opx_trans, pixblt_b_8_opx, pixblt_b_8_opx_trans,
611		pixblt_b_8_opx, pixblt_b_8_opx_trans, pixblt_b_8_opx, pixblt_b_8_opx_trans,
612		pixblt_b_8_opx, pixblt_b_8_opx_trans, pixblt_b_8_opx, pixblt_b_8_opx_trans,
613		pixblt_b_8_opx, pixblt_b_8_opx_trans, pixblt_b_8_opx, pixblt_b_8_opx_trans,
	507	&tms340x0_device::pixblt_b_8_op0, &tms340x0_device::pixblt_b_8_op0_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans,
	508	&tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans,
	509	&tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans,
	510	&tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans,
	511	&tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans,
	512	&tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans,
	513	&tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans,
	514	&tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans,
	515	&tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans,
	516	&tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans,
	517	&tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans,
	518	&tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans,
	519	&tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans,
	520	&tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans,
	521	&tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans,
	522	&tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans,
614	523
615		pixblt_b_16_op0,pixblt_b_16_op0_trans, pixblt_b_16_opx,pixblt_b_16_opx_trans,
616		pixblt_b_16_opx,pixblt_b_16_opx_trans, pixblt_b_16_opx,pixblt_b_16_opx_trans,
617		pixblt_b_16_opx,pixblt_b_16_opx_trans, pixblt_b_16_opx,pixblt_b_16_opx_trans,
618		pixblt_b_16_opx,pixblt_b_16_opx_trans, pixblt_b_16_opx,pixblt_b_16_opx_trans,
619		pixblt_b_16_opx,pixblt_b_16_opx_trans, pixblt_b_16_opx,pixblt_b_16_opx_trans,
620		pixblt_b_16_opx,pixblt_b_16_opx_trans, pixblt_b_16_opx,pixblt_b_16_opx_trans,
621		pixblt_b_16_opx,pixblt_b_16_opx_trans, pixblt_b_16_opx,pixblt_b_16_opx_trans,
622		pixblt_b_16_opx,pixblt_b_16_opx_trans, pixblt_b_16_opx,pixblt_b_16_opx_trans,
623		pixblt_b_16_opx,pixblt_b_16_opx_trans, pixblt_b_16_opx,pixblt_b_16_opx_trans,
624		pixblt_b_16_opx,pixblt_b_16_opx_trans, pixblt_b_16_opx,pixblt_b_16_opx_trans,
625		pixblt_b_16_opx,pixblt_b_16_opx_trans, pixblt_b_16_opx,pixblt_b_16_opx_trans,
626		pixblt_b_16_opx,pixblt_b_16_opx_trans, pixblt_b_16_opx,pixblt_b_16_opx_trans,
627		pixblt_b_16_opx,pixblt_b_16_opx_trans, pixblt_b_16_opx,pixblt_b_16_opx_trans,
628		pixblt_b_16_opx,pixblt_b_16_opx_trans, pixblt_b_16_opx,pixblt_b_16_opx_trans,
629		pixblt_b_16_opx,pixblt_b_16_opx_trans, pixblt_b_16_opx,pixblt_b_16_opx_trans,
630		pixblt_b_16_opx,pixblt_b_16_opx_trans, pixblt_b_16_opx,pixblt_b_16_opx_trans
	524	&tms340x0_device::pixblt_b_16_op0,&tms340x0_device::pixblt_b_16_op0_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans,
	525	&tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans,
	526	&tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans,
	527	&tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans,
	528	&tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans,
	529	&tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans,
	530	&tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans,
	531	&tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans,
	532	&tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans,
	533	&tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans,
	534	&tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans,
	535	&tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans,
	536	&tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans,
	537	&tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans,
	538	&tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans,
	539	&tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans
631	540	};
632	541
633		static void (const fill_op_table[]~~)(tms34010_state tms, int)~~ =
	542	const tms340x0_device::pixblt_b_op_func tms340x0_device::s_fill_op_table[] =
634	543	{
635		fill_1_op0, fill_1_op0_trans, fill_1_opx, fill_1_opx_trans,
636		fill_1_opx, fill_1_opx_trans, fill_1_opx, fill_1_opx_trans,
637		fill_1_opx, fill_1_opx_trans, fill_1_opx, fill_1_opx_trans,
638		fill_1_opx, fill_1_opx_trans, fill_1_opx, fill_1_opx_trans,
639		fill_1_opx, fill_1_opx_trans, fill_1_opx, fill_1_opx_trans,
640		fill_1_opx, fill_1_opx_trans, fill_1_opx, fill_1_opx_trans,
641		fill_1_opx, fill_1_opx_trans, fill_1_opx, fill_1_opx_trans,
642		fill_1_opx, fill_1_opx_trans, fill_1_opx, fill_1_opx_trans,
643		fill_1_opx, fill_1_opx_trans, fill_1_opx, fill_1_opx_trans,
644		fill_1_opx, fill_1_opx_trans, fill_1_opx, fill_1_opx_trans,
645		fill_1_opx, fill_1_opx_trans, fill_1_opx, fill_1_opx_trans,
646		fill_1_opx, fill_1_opx_trans, fill_1_opx, fill_1_opx_trans,
647		fill_1_opx, fill_1_opx_trans, fill_1_opx, fill_1_opx_trans,
648		fill_1_opx, fill_1_opx_trans, fill_1_opx, fill_1_opx_trans,
649		fill_1_opx, fill_1_opx_trans, fill_1_opx, fill_1_opx_trans,
650		fill_1_opx, fill_1_opx_trans, fill_1_opx, fill_1_opx_trans,
	544	&tms340x0_device::fill_1_op0, &tms340x0_device::fill_1_op0_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans,
	545	&tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans,
	546	&tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans,
	547	&tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans,
	548	&tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans,
	549	&tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans,
	550	&tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans,
	551	&tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans,
	552	&tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans,
	553	&tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans,
	554	&tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans,
	555	&tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans,
	556	&tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans,
	557	&tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans,
	558	&tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans,
	559	&tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans,
651	560
652		fill_2_op0, fill_2_op0_trans, fill_2_opx, fill_2_opx_trans,
653		fill_2_opx, fill_2_opx_trans, fill_2_opx, fill_2_opx_trans,
654		fill_2_opx, fill_2_opx_trans, fill_2_opx, fill_2_opx_trans,
655		fill_2_opx, fill_2_opx_trans, fill_2_opx, fill_2_opx_trans,
656		fill_2_opx, fill_2_opx_trans, fill_2_opx, fill_2_opx_trans,
657		fill_2_opx, fill_2_opx_trans, fill_2_opx, fill_2_opx_trans,
658		fill_2_opx, fill_2_opx_trans, fill_2_opx, fill_2_opx_trans,
659		fill_2_opx, fill_2_opx_trans, fill_2_opx, fill_2_opx_trans,
660		fill_2_opx, fill_2_opx_trans, fill_2_opx, fill_2_opx_trans,
661		fill_2_opx, fill_2_opx_trans, fill_2_opx, fill_2_opx_trans,
662		fill_2_opx, fill_2_opx_trans, fill_2_opx, fill_2_opx_trans,
663		fill_2_opx, fill_2_opx_trans, fill_2_opx, fill_2_opx_trans,
664		fill_2_opx, fill_2_opx_trans, fill_2_opx, fill_2_opx_trans,
665		fill_2_opx, fill_2_opx_trans, fill_2_opx, fill_2_opx_trans,
666		fill_2_opx, fill_2_opx_trans, fill_2_opx, fill_2_opx_trans,
667		fill_2_opx, fill_2_opx_trans, fill_2_opx, fill_2_opx_trans,
	561	&tms340x0_device::fill_2_op0, &tms340x0_device::fill_2_op0_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans,
	562	&tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans,
	563	&tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans,
	564	&tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans,
	565	&tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans,
	566	&tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans,
	567	&tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans,
	568	&tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans,
	569	&tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans,
	570	&tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans,
	571	&tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans,
	572	&tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans,
	573	&tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans,
	574	&tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans,
	575	&tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans,
	576	&tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans,
668	577
669		fill_4_op0, fill_4_op0_trans, fill_4_opx, fill_4_opx_trans,
670		fill_4_opx, fill_4_opx_trans, fill_4_opx, fill_4_opx_trans,
671		fill_4_opx, fill_4_opx_trans, fill_4_opx, fill_4_opx_trans,
672		fill_4_opx, fill_4_opx_trans, fill_4_opx, fill_4_opx_trans,
673		fill_4_opx, fill_4_opx_trans, fill_4_opx, fill_4_opx_trans,
674		fill_4_opx, fill_4_opx_trans, fill_4_opx, fill_4_opx_trans,
675		fill_4_opx, fill_4_opx_trans, fill_4_opx, fill_4_opx_trans,
676		fill_4_opx, fill_4_opx_trans, fill_4_opx, fill_4_opx_trans,
677		fill_4_opx, fill_4_opx_trans, fill_4_opx, fill_4_opx_trans,
678		fill_4_opx, fill_4_opx_trans, fill_4_opx, fill_4_opx_trans,
679		fill_4_opx, fill_4_opx_trans, fill_4_opx, fill_4_opx_trans,
680		fill_4_opx, fill_4_opx_trans, fill_4_opx, fill_4_opx_trans,
681		fill_4_opx, fill_4_opx_trans, fill_4_opx, fill_4_opx_trans,
682		fill_4_opx, fill_4_opx_trans, fill_4_opx, fill_4_opx_trans,
683		fill_4_opx, fill_4_opx_trans, fill_4_opx, fill_4_opx_trans,
684		fill_4_opx, fill_4_opx_trans, fill_4_opx, fill_4_opx_trans,
	578	&tms340x0_device::fill_4_op0, &tms340x0_device::fill_4_op0_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans,
	579	&tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans,
	580	&tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans,
	581	&tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans,
	582	&tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans,
	583	&tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans,
	584	&tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans,
	585	&tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans,
	586	&tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans,
	587	&tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans,
	588	&tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans,
	589	&tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans,
	590	&tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans,
	591	&tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans,
	592	&tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans,
	593	&tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans,
685	594
686		fill_8_op0, fill_8_op0_trans, fill_8_opx, fill_8_opx_trans,
687		fill_8_opx, fill_8_opx_trans, fill_8_opx, fill_8_opx_trans,
688		fill_8_opx, fill_8_opx_trans, fill_8_opx, fill_8_opx_trans,
689		fill_8_opx, fill_8_opx_trans, fill_8_opx, fill_8_opx_trans,
690		fill_8_opx, fill_8_opx_trans, fill_8_opx, fill_8_opx_trans,
691		fill_8_opx, fill_8_opx_trans, fill_8_opx, fill_8_opx_trans,
692		fill_8_opx, fill_8_opx_trans, fill_8_opx, fill_8_opx_trans,
693		fill_8_opx, fill_8_opx_trans, fill_8_opx, fill_8_opx_trans,
694		fill_8_opx, fill_8_opx_trans, fill_8_opx, fill_8_opx_trans,
695		fill_8_opx, fill_8_opx_trans, fill_8_opx, fill_8_opx_trans,
696		fill_8_opx, fill_8_opx_trans, fill_8_opx, fill_8_opx_trans,
697		fill_8_opx, fill_8_opx_trans, fill_8_opx, fill_8_opx_trans,
698		fill_8_opx, fill_8_opx_trans, fill_8_opx, fill_8_opx_trans,
699		fill_8_opx, fill_8_opx_trans, fill_8_opx, fill_8_opx_trans,
700		fill_8_opx, fill_8_opx_trans, fill_8_opx, fill_8_opx_trans,
701		fill_8_opx, fill_8_opx_trans, fill_8_opx, fill_8_opx_trans,
	595	&tms340x0_device::fill_8_op0, &tms340x0_device::fill_8_op0_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans,
	596	&tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans,
	597	&tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans,
	598	&tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans,
	599	&tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans,
	600	&tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans,
	601	&tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans,
	602	&tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans,
	603	&tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans,
	604	&tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans,
	605	&tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans,
	606	&tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans,
	607	&tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans,
	608	&tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans,
	609	&tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans,
	610	&tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans,
702	611
703		fill_16_op0, fill_16_op0_trans, fill_16_opx, fill_16_opx_trans,
704		fill_16_opx, fill_16_opx_trans, fill_16_opx, fill_16_opx_trans,
705		fill_16_opx, fill_16_opx_trans, fill_16_opx, fill_16_opx_trans,
706		fill_16_opx, fill_16_opx_trans, fill_16_opx, fill_16_opx_trans,
707		fill_16_opx, fill_16_opx_trans, fill_16_opx, fill_16_opx_trans,
708		fill_16_opx, fill_16_opx_trans, fill_16_opx, fill_16_opx_trans,
709		fill_16_opx, fill_16_opx_trans, fill_16_opx, fill_16_opx_trans,
710		fill_16_opx, fill_16_opx_trans, fill_16_opx, fill_16_opx_trans,
711		fill_16_opx, fill_16_opx_trans, fill_16_opx, fill_16_opx_trans,
712		fill_16_opx, fill_16_opx_trans, fill_16_opx, fill_16_opx_trans,
713		fill_16_opx, fill_16_opx_trans, fill_16_opx, fill_16_opx_trans,
714		fill_16_opx, fill_16_opx_trans, fill_16_opx, fill_16_opx_trans,
715		fill_16_opx, fill_16_opx_trans, fill_16_opx, fill_16_opx_trans,
716		fill_16_opx, fill_16_opx_trans, fill_16_opx, fill_16_opx_trans,
717		fill_16_opx, fill_16_opx_trans, fill_16_opx, fill_16_opx_trans,
718		fill_16_opx, fill_16_opx_trans, fill_16_opx, fill_16_opx_trans
	612	&tms340x0_device::fill_16_op0, &tms340x0_device::fill_16_op0_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans,
	613	&tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans,
	614	&tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans,
	615	&tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans,
	616	&tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans,
	617	&tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans,
	618	&tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans,
	619	&tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans,
	620	&tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans,
	621	&tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans,
	622	&tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans,
	623	&tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans,
	624	&tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans,
	625	&tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans,
	626	&tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans,
	627	&tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans
719	628	};
720	629
721	630
r31176	r31177
768	677	#undef PIXEL_OP
769	678
770	679
771		#define PIXEL_OP(src, mask, pixel) pixel = (*pixel_op)(src, mask, pixel)
772		#define PIXEL_OP_TIMING pixel_op_timing
	680	#define PIXEL_OP(src, mask, pixel) pixel = (this->*m_pixel_op)(src, mask, pixel)
	681	#define PIXEL_OP_TIMING m_pixel_op_timing
773	682	#define PIXEL_OP_REQUIRES_SOURCE 1
774	683	#define TRANSPARENCY 0
775	684
r31176	r31177
861	770	#undef PIXEL_OP
862	771
863	772
864		#define PIXEL_OP(src, mask, pixel) pixel = (*pixel_op)(src, mask, pixel)
	773	#define PIXEL_OP(src, mask, pixel) pixel = (this->*m_pixel_op)(src, mask, pixel)
865	774	#define PIXEL_OP_REQUIRES_SOURCE 1
866		#define PIXEL_OP_TIMING (2+pixel_op_timing)
	775	#define PIXEL_OP_TIMING (2+m_pixel_op_timing)
867	776	#define TRANSPARENCY 1
868	777
869	778	/* 1bpp cases */
r31176	r31177
912	821	};
913	822
914	823
915		~~static~~ void pixblt_b_l(~~tms34010_state *tms,~~ UINT16 op)
	824	void tms340x0_device::pixblt_b_l(UINT16 op)
916	825	{
917		int psize = pixelsize_lookup[IOREG(tms, REG_PSIZE) & 0x1f];
918		int trans = (IOREG(tms, REG_CONTROL) & 0x20) >> 5;
919		int rop = (IOREG(tms, REG_CONTROL) >> 10) & 0x1f;
	826	int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f];
	827	int trans = (IOREG(REG_CONTROL) & 0x20) >> 5;
	828	int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f;
920	829	int ix = trans \| (rop << 1) \| (psize << 6);
921		if (!P_FLAG(tms)) LOGGFX(("%08X(%3d):PIXBLT B,L (%dx%d) depth=%d\n", tms->pc, tms->screen->vpos(), DYDX_X(tms), DYDX_Y(tms), IOREG(tms, REG_PSIZE) ? IOREG(tms, REG_PSIZE) : 32));
922		pixel_op = pixel_op_table[rop];
923		pixel_op_timing = pixel_op_timing_table[rop];
924		(*pixblt_b_op_table[ix])(tms, 1);
	830	if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT B,L (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32));
	831	m_pixel_op = s_pixel_op_table[rop];
	832	m_pixel_op_timing = s_pixel_op_timing_table[rop];
	833	(this->*s_pixblt_b_op_table[ix])(1);
925	834	}
926	835
927		~~static~~ void pixblt_b_xy(~~tms34010_state *tms,~~ UINT16 op)
	836	void tms340x0_device::pixblt_b_xy(UINT16 op)
928	837	{
929		int psize = pixelsize_lookup[IOREG(tms, REG_PSIZE) & 0x1f];
930		int trans = (IOREG(tms, REG_CONTROL) & 0x20) >> 5;
931		int rop = (IOREG(tms, REG_CONTROL) >> 10) & 0x1f;
	838	int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f];
	839	int trans = (IOREG(REG_CONTROL) & 0x20) >> 5;
	840	int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f;
932	841	int ix = trans \| (rop << 1) \| (psize << 6);
933		if (!P_FLAG(tms)) LOGGFX(("%08X(%3d):PIXBLT B,XY (%d,%d) (%dx%d) depth=%d\n", tms->pc, tms->screen->vpos(), DADDR_X(tms), DADDR_Y(tms), DYDX_X(tms), DYDX_Y(tms), IOREG(tms, REG_PSIZE) ? IOREG(tms, REG_PSIZE) : 32));
934		pixel_op = pixel_op_table[rop];
935		pixel_op_timing = pixel_op_timing_table[rop];
936		(*pixblt_b_op_table[ix])(tms, 0);
	842	if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT B,XY (%d,%d) (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DADDR_X(), DADDR_Y(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32));
	843	m_pixel_op = s_pixel_op_table[rop];
	844	m_pixel_op_timing = s_pixel_op_timing_table[rop];
	845	(this->*s_pixblt_b_op_table[ix])(0);
937	846	}
938	847
939		~~static~~ void pixblt_l_l(~~tms34010_state *tms,~~ UINT16 op)
	848	void tms340x0_device::pixblt_l_l(UINT16 op)
940	849	{
941		int psize = pixelsize_lookup[IOREG(tms, REG_PSIZE) & 0x1f];
942		int trans = (IOREG(tms, REG_CONTROL) & 0x20) >> 5;
943		int rop = (IOREG(tms, REG_CONTROL) >> 10) & 0x1f;
944		int pbh = (IOREG(tms, REG_CONTROL) >> 8) & 1;
	850	int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f];
	851	int trans = (IOREG(REG_CONTROL) & 0x20) >> 5;
	852	int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f;
	853	int pbh = (IOREG(REG_CONTROL) >> 8) & 1;
945	854	int ix = trans \| (rop << 1) \| (psize << 6);
946		if (!P_FLAG(tms)) LOGGFX(("%08X(%3d):PIXBLT L,L (%dx%d) depth=%d\n", tms->pc, tms->screen->vpos(), DYDX_X(tms), DYDX_Y(tms), IOREG(tms, REG_PSIZE) ? IOREG(tms, REG_PSIZE) : 32));
947		pixel_op = pixel_op_table[rop];
948		pixel_op_timing = pixel_op_timing_table[rop];
	855	if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT L,L (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32));
	856	m_pixel_op = s_pixel_op_table[rop];
	857	m_pixel_op_timing = s_pixel_op_timing_table[rop];
949	858	if (!pbh)
950		(*pixblt_op_table[ix])(~~tms,~~ 1, 1);
	859	(this->*s_pixblt_op_table[ix])(1, 1);
951	860	else
952		(*pixblt_r_op_table[ix])(~~tms,~~ 1, 1);
	861	(this->*s_pixblt_r_op_table[ix])(1, 1);
953	862	}
954	863
955		~~static~~ void pixblt_l_xy(~~tms34010_state *tms,~~ UINT16 op)
	864	void tms340x0_device::pixblt_l_xy(UINT16 op)
956	865	{
957		int psize = pixelsize_lookup[IOREG(tms, REG_PSIZE) & 0x1f];
958		int trans = (IOREG(tms, REG_CONTROL) & 0x20) >> 5;
959		int rop = (IOREG(tms, REG_CONTROL) >> 10) & 0x1f;
960		int pbh = (IOREG(tms, REG_CONTROL) >> 8) & 1;
	866	int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f];
	867	int trans = (IOREG(REG_CONTROL) & 0x20) >> 5;
	868	int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f;
	869	int pbh = (IOREG(REG_CONTROL) >> 8) & 1;
961	870	int ix = trans \| (rop << 1) \| (psize << 6);
962		if (!P_FLAG(tms)) LOGGFX(("%08X(%3d):PIXBLT L,XY (%d,%d) (%dx%d) depth=%d\n", tms->pc, tms->screen->vpos(), DADDR_X(tms), DADDR_Y(tms), DYDX_X(tms), DYDX_Y(tms), IOREG(tms, REG_PSIZE) ? IOREG(tms, REG_PSIZE) : 32));
963		pixel_op = pixel_op_table[rop];
964		pixel_op_timing = pixel_op_timing_table[rop];
	871	if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT L,XY (%d,%d) (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DADDR_X(), DADDR_Y(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32));
	872	m_pixel_op = s_pixel_op_table[rop];
	873	m_pixel_op_timing = s_pixel_op_timing_table[rop];
965	874	if (!pbh)
966		(*pixblt_op_table[ix])(~~tms,~~ 1, 0);
	875	(this->*s_pixblt_op_table[ix])(1, 0);
967	876	else
968		(*pixblt_r_op_table[ix])(~~tms,~~ 1, 0);
	877	(this->*s_pixblt_r_op_table[ix])(1, 0);
969	878	}
970	879
971		~~static~~ void pixblt_xy_l(~~tms34010_state *tms,~~ UINT16 op)
	880	void tms340x0_device::pixblt_xy_l(UINT16 op)
972	881	{
973		int psize = pixelsize_lookup[IOREG(tms, REG_PSIZE) & 0x1f];
974		int trans = (IOREG(tms, REG_CONTROL) & 0x20) >> 5;
975		int rop = (IOREG(tms, REG_CONTROL) >> 10) & 0x1f;
976		int pbh = (IOREG(tms, REG_CONTROL) >> 8) & 1;
	882	int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f];
	883	int trans = (IOREG(REG_CONTROL) & 0x20) >> 5;
	884	int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f;
	885	int pbh = (IOREG(REG_CONTROL) >> 8) & 1;
977	886	int ix = trans \| (rop << 1) \| (psize << 6);
978		if (!P_FLAG(tms)) LOGGFX(("%08X(%3d):PIXBLT XY,L (%dx%d) depth=%d\n", tms->pc, tms->screen->vpos(), DYDX_X(tms), DYDX_Y(tms), IOREG(tms, REG_PSIZE) ? IOREG(tms, REG_PSIZE) : 32));
979		pixel_op = pixel_op_table[rop];
980		pixel_op_timing = pixel_op_timing_table[rop];
	887	if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT XY,L (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32));
	888	m_pixel_op = s_pixel_op_table[rop];
	889	m_pixel_op_timing = s_pixel_op_timing_table[rop];
981	890	if (!pbh)
982		(*pixblt_op_table[ix])(~~tms,~~ 0, 1);
	891	(this->*s_pixblt_op_table[ix])(0, 1);
983	892	else
984		(*pixblt_r_op_table[ix])(~~tms,~~ 0, 1);
	893	(this->*s_pixblt_r_op_table[ix])(0, 1);
985	894	}
986	895
987		~~static~~ void pixblt_xy_xy(~~tms34010_state *tms,~~ UINT16 op)
	896	void tms340x0_device::pixblt_xy_xy(UINT16 op)
988	897	{
989		int psize = pixelsize_lookup[IOREG(tms, REG_PSIZE) & 0x1f];
990		int trans = (IOREG(tms, REG_CONTROL) & 0x20) >> 5;
991		int rop = (IOREG(tms, REG_CONTROL) >> 10) & 0x1f;
992		int pbh = (IOREG(tms, REG_CONTROL) >> 8) & 1;
	898	int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f];
	899	int trans = (IOREG(REG_CONTROL) & 0x20) >> 5;
	900	int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f;
	901	int pbh = (IOREG(REG_CONTROL) >> 8) & 1;
993	902	int ix = trans \| (rop << 1) \| (psize << 6);
994		if (!P_FLAG(tms)) LOGGFX(("%08X(%3d):PIXBLT XY,XY (%dx%d) depth=%d\n", tms->pc, tms->screen->vpos(), DYDX_X(tms), DYDX_Y(tms), IOREG(tms, REG_PSIZE) ? IOREG(tms, REG_PSIZE) : 32));
995		pixel_op = pixel_op_table[rop];
996		pixel_op_timing = pixel_op_timing_table[rop];
	903	if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT XY,XY (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32));
	904	m_pixel_op = s_pixel_op_table[rop];
	905	m_pixel_op_timing = s_pixel_op_timing_table[rop];
997	906	if (!pbh)
998		(*pixblt_op_table[ix])(~~tms,~~ 0, 0);
	907	(this->*s_pixblt_op_table[ix])(0, 0);
999	908	else
1000		(*pixblt_r_op_table[ix])(~~tms,~~ 0, 0);
	909	(this->*s_pixblt_r_op_table[ix])(0, 0);
1001	910	}
1002	911
1003		~~static~~ void ~~fill_l(~~tms34010_~~stat~~e *tms, UINT16 op)
	912	void tms340x0_device::fill_l(UINT16 op)
1004	913	{
1005		int psize = pixelsize_lookup[IOREG(tms, REG_PSIZE) & 0x1f];
1006		int trans = (IOREG(tms, REG_CONTROL) & 0x20) >> 5;
1007		int rop = (IOREG(tms, REG_CONTROL) >> 10) & 0x1f;
	914	int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f];
	915	int trans = (IOREG(REG_CONTROL) & 0x20) >> 5;
	916	int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f;
1008	917	int ix = trans \| (rop << 1) \| (psize << 6);
1009		if (!P_FLAG(tms)) LOGGFX(("%08X(%3d):FILL L (%dx%d) depth=%d\n", tms->pc, tms->screen->vpos(), DYDX_X(tms), DYDX_Y(tms), IOREG(tms, REG_PSIZE) ? IOREG(tms, REG_PSIZE) : 32));
1010		pixel_op = pixel_op_table[rop];
1011		pixel_op_timing = pixel_op_timing_table[rop];
1012		(*fill_op_table[ix])(tms, 1);
	918	if (!P_FLAG()) LOGGFX(("%08X(%3d):FILL L (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32));
	919	m_pixel_op = s_pixel_op_table[rop];
	920	m_pixel_op_timing = s_pixel_op_timing_table[rop];
	921	(this->*s_fill_op_table[ix])(1);
1013	922	}
1014	923
1015		~~static~~ void ~~fill_xy(~~tms34010_~~stat~~e *tms, UINT16 op)
	924	void tms340x0_device::fill_xy(UINT16 op)
1016	925	{
1017		int psize = pixelsize_lookup[IOREG(tms, REG_PSIZE) & 0x1f];
1018		int trans = (IOREG(tms, REG_CONTROL) & 0x20) >> 5;
1019		int rop = (IOREG(tms, REG_CONTROL) >> 10) & 0x1f;
	926	int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f];
	927	int trans = (IOREG(REG_CONTROL) & 0x20) >> 5;
	928	int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f;
1020	929	int ix = trans \| (rop << 1) \| (psize << 6);
1021		if (!P_FLAG(tms)) LOGGFX(("%08X(%3d):FILL XY (%d,%d) (%dx%d) depth=%d\n", tms->pc, tms->screen->vpos(), DADDR_X(tms), DADDR_Y(tms), DYDX_X(tms), DYDX_Y(tms), IOREG(tms, REG_PSIZE) ? IOREG(tms, REG_PSIZE) : 32));
1022		pixel_op = pixel_op_table[rop];
1023		pixel_op_timing = pixel_op_timing_table[rop];
1024		(*fill_op_table[ix])(tms, 0);
	930	if (!P_FLAG()) LOGGFX(("%08X(%3d):FILL XY (%d,%d) (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DADDR_X(), DADDR_Y(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32));
	931	m_pixel_op = s_pixel_op_table[rop];
	932	m_pixel_op_timing = s_pixel_op_timing_table[rop];
	933	(this->*s_fill_op_table[ix])(0);
1025	934	}
1026	935
1027	936
r31176	r31177
1034	943	#define PIXELS_PER_WORD (16 / BITS_PER_PIXEL)
1035	944	#define PIXEL_MASK ((1 << BITS_PER_PIXEL) - 1)
1036	945
1037		~~static~~ void FUNCTION_NAME(~~pixbl~~t~~)(t~~ms34010_~~stat~~e *t~~ms,~~ int src_is_linear, int dst_is_linear)
	946	void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear)
1038	947	{
1039	948	/* if this is the first time through, perform the operation */
1040		if (!P_FLAG(~~tms~~))
	949	if (!P_FLAG())
1041	950	{
1042	951	int dx, dy, x, y, /words,/ yreverse;
1043		void (*word_write)(address_space &space,offs_t address,UINT16 data);
1044		UINT16 (*word_read)(address_space &space,offs_t address);
	952	word_write_func word_write;
	953	word_read_func word_read;
1045	954	UINT32 readwrites = 0;
1046	955	UINT32 saddr, daddr;
1047	956	XY dstxy = { 0 };
1048	957
1049	958	/* determine read/write functions */
1050		if (IOREG(~~tms,~~ REG_DPYCTL) & 0x0800)
	959	if (IOREG(REG_DPYCTL) & 0x0800)
1051	960	{
1052		word_write = shiftreg_w;
1053		word_read = shiftreg_r;
	961	word_write = &tms340x0_device::shiftreg_w;
	962	word_read = &tms340x0_device::shiftreg_r;
1054	963	}
1055	964	else
1056	965	{
1057		word_write = memory_w;
1058		word_read = memory_r;
	966	word_write = &tms340x0_device::memory_w;
	967	word_read = &tms340x0_device::memory_r;
1059	968	}
1060	969
1061	970	/* compute the starting addresses */
1062		saddr = src_is_linear ? SADDR(~~tms~~) : SXYTOL(~~tms,~~SADDR_XY(~~tms~~));
	971	saddr = src_is_linear ? SADDR() : SXYTOL(SADDR_XY());
1063	972
1064	973	/* compute the bounds of the operation */
1065		dx = (INT16)DYDX_X(tms);
1066		dy = (INT16)DYDX_Y(tms);
	974	dx = (INT16)DYDX_X();
	975	dy = (INT16)DYDX_Y();
1067	976
1068	977	/* apply the window for non-linear destinations */
1069		tm~~s->~~gfxcycles = 7 + (src_is_linear ? 0 : 2);
	978	m_gfxcycles = 7 + (src_is_linear ? 0 : 2);
1070	979	if (!dst_is_linear)
1071	980	{
1072		dstxy = DADDR_XY(tms);
1073		tms->gfxcycles += 2 + (!src_is_linear) + apply_window(tms, "PIXBLT", BITS_PER_PIXEL, &saddr, &dstxy, &dx, &dy);
1074		daddr = DXYTOL(tms,dstxy);
	981	dstxy = DADDR_XY();
	982	m_gfxcycles += 2 + (!src_is_linear) + apply_window("PIXBLT", BITS_PER_PIXEL, &saddr, &dstxy, &dx, &dy);
	983	daddr = DXYTOL(dstxy);
1075	984	}
1076	985	else
1077		daddr = DADDR(~~tms~~);
	986	daddr = DADDR();
1078	987	daddr &= ~(BITS_PER_PIXEL - 1);
1079		LOGGFX((" saddr=%08X daddr=%08X sptch=%08X dptch=%08X\n", saddr, daddr, SPTCH(~~tms~~), DPTCH(~~tms~~)));
	988	LOGGFX((" saddr=%08X daddr=%08X sptch=%08X dptch=%08X\n", saddr, daddr, SPTCH(), DPTCH()));
1080	989
1081	990	/* bail if we're clipped */
1082	991	if (dx <= 0 \|\| dy <= 0)
1083	992	return;
1084	993
1085	994	/* window mode 1: just return and interrupt if we are within the window */
1086		if (WINDOW_CHECKING(~~tms~~) == 1 && !dst_is_linear)
	995	if (WINDOW_CHECKING() == 1 && !dst_is_linear)
1087	996	{
1088		CLR_V(tms);
1089		DADDR_XY(tms) = dstxy;
1090		DYDX_X(tms) = dx;
1091		DYDX_Y(tms) = dy;
1092		IOREG(tms, REG_INTPEND) \|= TMS34010_WV;
1093		check_interrupt(tms);
	997	CLR_V();
	998	DADDR_XY() = dstxy;
	999	DYDX_X() = dx;
	1000	DYDX_Y() = dy;
	1001	IOREG(REG_INTPEND) \|= TMS34010_WV;
	1002	check_interrupt();
1094	1003	return;
1095	1004	}
1096	1005
1097	1006	/* handle flipping the addresses */
1098		yreverse = (IOREG(~~tms,~~ REG_CONTROL) >> 9) & 1;
	1007	yreverse = (IOREG(REG_CONTROL) >> 9) & 1;
1099	1008	if (!src_is_linear \|\| !dst_is_linear)
1100	1009	{
1101	1010	if (yreverse)
1102	1011	{
1103		saddr += (dy - 1) * tms->convsp;
1104		daddr += (dy - 1) * tms->convdp;
	1012	saddr += (dy - 1) * m_convsp;
	1013	daddr += (dy - 1) * m_convdp;
1105	1014	}
1106	1015	}
1107	1016
1108		tm~~s->~~st \|= STBIT_P;
	1017	m_st \|= STBIT_P;
1109	1018
1110	1019	/* loop over rows */
1111	1020	for (y = 0; y < dy; y++)
r31176	r31177
1117	1026	UINT32 srcword, dstword = 0;
1118	1027
1119	1028	/* fetch the initial source word */
1120		srcword = (word_read)(tm~~s->~~program, srcwordaddr++ << 1);
	1029	srcword = (this->word_read)(m_program, srcwordaddr++ << 1);
1121	1030	readwrites++;
1122	1031
1123	1032	/* fetch the initial dest word */
1124	1033	if (PIXEL_OP_REQUIRES_SOURCE \|\| TRANSPARENCY \|\| (daddr & 0x0f) != 0)
1125	1034	{
1126		dstword = (word_read)(tm~~s->~~program, dstwordaddr << 1);
	1035	dstword = (this->word_read)(m_program, dstwordaddr << 1);
1127	1036	readwrites++;
1128	1037	}
1129	1038
r31176	r31177
1136	1045	/* fetch more words if necessary */
1137	1046	if (srcbit + BITS_PER_PIXEL > 16)
1138	1047	{
1139		srcword \|= (word_read)(tm~~s->~~program, srcwordaddr++ << 1) << 16;
	1048	srcword \|= (this->word_read)(m_program, srcwordaddr++ << 1) << 16;
1140	1049	readwrites++;
1141	1050	}
1142	1051
r31176	r31177
1153	1062	if (PIXEL_OP_REQUIRES_SOURCE \|\| TRANSPARENCY)
1154	1063	if (dstbit + BITS_PER_PIXEL > 16)
1155	1064	{
1156		dstword \|= (word_read)(tm~~s->~~program, (dstwordaddr + 1) << 1) << 16;
	1065	dstword \|= (this->word_read)(m_program, (dstwordaddr + 1) << 1) << 16;
1157	1066	readwrites++;
1158	1067	}
1159	1068
r31176	r31177
1168	1077	dstbit += BITS_PER_PIXEL;
1169	1078	if (dstbit > 16)
1170	1079	{
1171		(word_write)(tm~~s->~~program, dstwordaddr++ << 1, dstword);
	1080	(this->word_write)(m_program, dstwordaddr++ << 1, dstword);
1172	1081	readwrites++;
1173	1082	dstbit -= 16;
1174	1083	dstword >>= 16;
r31176	r31177
1181	1090	/* if we're right-partial, read and mask the remaining bits */
1182	1091	if (dstbit != 16)
1183	1092	{
1184		UINT16 origdst = (word_read)(tm~~s->~~program, dstwordaddr << 1);
	1093	UINT16 origdst = (this->word_read)(m_program, dstwordaddr << 1);
1185	1094	UINT16 mask = 0xffff << dstbit;
1186	1095	dstword = (dstword & ~mask) \| (origdst & mask);
1187	1096	readwrites++;
1188	1097	}
1189	1098
1190		(word_write)(tm~~s->~~program, dstwordaddr++ << 1, dstword);
	1099	(this->word_write)(m_program, dstwordaddr++ << 1, dstword);
1191	1100	readwrites++;
1192	1101	}
1193	1102
r31176	r31177
1212	1121	full_words /= PIXELS_PER_WORD;
1213	1122
1214	1123	/* compute cycles */
1215		tm~~s->~~gfxcycles += compute_pixblt_cycles(left_partials, right_partials, full_words, PIXEL_OP_TIMING);
	1124	m_gfxcycles += compute_pixblt_cycles(left_partials, right_partials, full_words, PIXEL_OP_TIMING);
1216	1125
1217	1126	/* use word addresses each row */
1218	1127	swordaddr = saddr >> 4;
1219	1128	dwordaddr = daddr >> 4;
1220	1129
1221	1130	/* fetch the initial source word */
1222		srcword = (word_read)(tm~~s->~~program, swordaddr++ << 1);
	1131	srcword = (this->word_read)(m_program, swordaddr++ << 1);
1223	1132	srcmask = PIXEL_MASK << (saddr & 15);
1224	1133
1225	1134	/* handle the left partial word */
1226	1135	if (left_partials != 0)
1227	1136	{
1228	1137	/* fetch the destination word */
1229		dstword = (word_read)(tm~~s->~~program, dwordaddr << 1);
	1138	dstword = (this->word_read)(m_program, dwordaddr << 1);
1230	1139	dstmask = PIXEL_MASK << (daddr & 15);
1231	1140
1232	1141	/* loop over partials */
r31176	r31177
1235	1144	/* fetch another word if necessary */
1236	1145	if (srcmask == 0)
1237	1146	{
1238		srcword = (word_read)(tm~~s->~~program, swordaddr++ << 1);
	1147	srcword = (this->word_read)(m_program, swordaddr++ << 1);
1239	1148	srcmask = PIXEL_MASK;
1240	1149	}
1241	1150
r31176	r31177
1257	1166	}
1258	1167
1259	1168	/* write the result */
1260		(word_write)(tm~~s->~~program, dwordaddr++ << 1, dstword);
	1169	(this->word_write)(m_program, dwordaddr++ << 1, dstword);
1261	1170	}
1262	1171
1263	1172	/* loop over full words */
r31176	r31177
1265	1174	{
1266	1175	/* fetch the destination word (if necessary) */
1267	1176	if (PIXEL_OP_REQUIRES_SOURCE \|\| TRANSPARENCY)
1268		dstword = (word_read)(tm~~s->~~program, dwordaddr << 1);
	1177	dstword = (this->word_read)(m_program, dwordaddr << 1);
1269	1178	else
1270	1179	dstword = 0;
1271	1180	dstmask = PIXEL_MASK;
r31176	r31177
1276	1185	/* fetch another word if necessary */
1277	1186	if (srcmask == 0)
1278	1187	{
1279		srcword = (word_read)(tm~~s->~~program, swordaddr++ << 1);
	1188	srcword = (this->word_read)(m_program, swordaddr++ << 1);
1280	1189	srcmask = PIXEL_MASK;
1281	1190	}
1282	1191
r31176	r31177
1298	1207	}
1299	1208
1300	1209	/* write the result */
1301		(word_write)(tm~~s->~~program, dwordaddr++ << 1, dstword);
	1210	(this->word_write)(m_program, dwordaddr++ << 1, dstword);
1302	1211	}
1303	1212
1304	1213	/* handle the right partial word */
1305	1214	if (right_partials != 0)
1306	1215	{
1307	1216	/* fetch the destination word */
1308		dstword = (word_read)(tm~~s->~~program, dwordaddr << 1);
	1217	dstword = (this->word_read)(m_program, dwordaddr << 1);
1309	1218	dstmask = PIXEL_MASK;
1310	1219
1311	1220	/* loop over partials */
r31176	r31177
1315	1224	if (srcmask == 0)
1316	1225	{
1317	1226	LOGGFX((" right fetch @ %08x\n", swordaddr));
1318		srcword = (word_read)(tm~~s->~~program, swordaddr++ << 1);
	1227	srcword = (this->word_read)(m_program, swordaddr++ << 1);
1319	1228	srcmask = PIXEL_MASK;
1320	1229	}
1321	1230
r31176	r31177
1337	1246	}
1338	1247
1339	1248	/* write the result */
1340		(word_write)(tm~~s->~~program, dwordaddr++ << 1, dstword);
	1249	(this->word_write)(m_program, dwordaddr++ << 1, dstword);
1341	1250	}
1342	1251	#endif
1343	1252
1344	1253	/* update for next row */
1345	1254	if (!yreverse)
1346	1255	{
1347		saddr += SPTCH(tms);
1348		daddr += DPTCH(tms);
	1256	saddr += SPTCH();
	1257	daddr += DPTCH();
1349	1258	}
1350	1259	else
1351	1260	{
1352		saddr -= SPTCH(tms);
1353		daddr -= DPTCH(tms);
	1261	saddr -= SPTCH();
	1262	daddr -= DPTCH();
1354	1263	}
1355	1264	}
1356	1265
1357		tm~~s->~~gfxcycles += readwrites * 2 + dx * dy * (PIXEL_OP_TIMING - 2);
	1266	m_gfxcycles += readwrites * 2 + dx * dy * (PIXEL_OP_TIMING - 2);
1358	1267
1359		LOGGFX((" (%d cycles)\n", tm~~s->~~gfxcycles));
	1268	LOGGFX((" (%d cycles)\n", m_gfxcycles));
1360	1269	}
1361	1270
1362	1271	/* eat cycles */
1363		if (tm~~s->~~gfxcycles > tm~~s->~~icount)
	1272	if (m_gfxcycles > m_icount)
1364	1273	{
1365		tms->gfxcycles -= tms->icount;
1366		tms->icount = 0;
1367		tms->pc -= 0x10;
	1274	m_gfxcycles -= m_icount;
	1275	m_icount = 0;
	1276	m_pc -= 0x10;
1368	1277	}
1369	1278	else
1370	1279	{
1371		tms->icount -= tms->gfxcycles;
1372		tms->st &= ~STBIT_P;
	1280	m_icount -= m_gfxcycles;
	1281	m_st &= ~STBIT_P;
1373	1282	if (src_is_linear && dst_is_linear)
1374		SADDR(~~tms~~) += DYDX_Y(~~tms~~) * SPTCH(~~tms~~);
	1283	SADDR() += DYDX_Y() * SPTCH();
1375	1284	else if (src_is_linear)
1376		SADDR(~~tms~~) += DYDX_Y(~~tms~~) * SPTCH(~~tms~~);
	1285	SADDR() += DYDX_Y() * SPTCH();
1377	1286	else
1378		SADDR_Y(~~tms~~) += DYDX_Y(~~tms~~);
	1287	SADDR_Y() += DYDX_Y();
1379	1288	if (dst_is_linear)
1380		DADDR(~~tms~~) += DYDX_Y(~~tms~~) * DPTCH(~~tms~~);
	1289	DADDR() += DYDX_Y() * DPTCH();
1381	1290	else
1382		DADDR_Y(~~tms~~) += DYDX_Y(~~tms~~);
	1291	DADDR_Y() += DYDX_Y();
1383	1292	}
1384	1293	}
1385	1294
1386		~~static~~ void FUNCTION_NAME(~~pixbl~~t~~_r)(t~~ms34010_~~stat~~e *t~~ms,~~ int src_is_linear, int dst_is_linear)
	1295	void FUNCTION_NAME(tms340x0_device::pixblt_r)(int src_is_linear, int dst_is_linear)
1387	1296	{
1388	1297	/* if this is the first time through, perform the operation */
1389		if (!P_FLAG(~~tms~~))
	1298	if (!P_FLAG())
1390	1299	{
1391	1300	int dx, dy, x, y, words, yreverse;
1392		void (*word_write)(address_space &space,offs_t address,UINT16 data);
1393		UINT16 (*word_read)(address_space &space,offs_t address);
	1301	word_write_func word_write;
	1302	word_read_func word_read;
1394	1303	UINT32 saddr, daddr;
1395	1304	XY dstxy = { 0 };
1396	1305
1397	1306	/* determine read/write functions */
1398		if (IOREG(~~tms,~~ REG_DPYCTL) & 0x0800)
	1307	if (IOREG(REG_DPYCTL) & 0x0800)
1399	1308	{
1400		word_write = shiftreg_w;
1401		word_read = shiftreg_r;
	1309	word_write = &tms340x0_device::shiftreg_w;
	1310	word_read = &tms340x0_device::shiftreg_r;
1402	1311	}
1403	1312	else
1404	1313	{
1405		word_write = memory_w;
1406		word_read = memory_r;
	1314	word_write = &tms340x0_device::memory_w;
	1315	word_read = &tms340x0_device::memory_r;
1407	1316	}
1408	1317
1409	1318	/* compute the starting addresses */
1410		saddr = src_is_linear ? SADDR(~~tms~~) : SXYTOL(~~tms,~~SADDR_XY(~~tms~~));
	1319	saddr = src_is_linear ? SADDR() : SXYTOL(SADDR_XY());
1411	1320	if ((saddr & (BITS_PER_PIXEL - 1)) != 0) osd_printf_debug("PIXBLT_R%d with odd saddr\n", BITS_PER_PIXEL);
1412	1321	saddr &= ~(BITS_PER_PIXEL - 1);
1413	1322
1414	1323	/* compute the bounds of the operation */
1415		dx = (INT16)DYDX_X(tms);
1416		dy = (INT16)DYDX_Y(tms);
	1324	dx = (INT16)DYDX_X();
	1325	dy = (INT16)DYDX_Y();
1417	1326
1418	1327	/* apply the window for non-linear destinations */
1419		tm~~s->~~gfxcycles = 7 + (src_is_linear ? 0 : 2);
	1328	m_gfxcycles = 7 + (src_is_linear ? 0 : 2);
1420	1329	if (!dst_is_linear)
1421	1330	{
1422		dstxy = DADDR_XY(tms);
1423		tms->gfxcycles += 2 + (!src_is_linear) + apply_window(tms, "PIXBLT R", BITS_PER_PIXEL, &saddr, &dstxy, &dx, &dy);
1424		daddr = DXYTOL(tms,dstxy);
	1331	dstxy = DADDR_XY();
	1332	m_gfxcycles += 2 + (!src_is_linear) + apply_window("PIXBLT R", BITS_PER_PIXEL, &saddr, &dstxy, &dx, &dy);
	1333	daddr = DXYTOL(dstxy);
1425	1334	}
1426	1335	else
1427		daddr = DADDR(~~tms~~);
	1336	daddr = DADDR();
1428	1337	if ((daddr & (BITS_PER_PIXEL - 1)) != 0) osd_printf_debug("PIXBLT_R%d with odd daddr\n", BITS_PER_PIXEL);
1429	1338	daddr &= ~(BITS_PER_PIXEL - 1);
1430		LOGGFX((" saddr=%08X daddr=%08X sptch=%08X dptch=%08X\n", saddr, daddr, SPTCH(~~tms~~), DPTCH(~~tms~~)));
	1339	LOGGFX((" saddr=%08X daddr=%08X sptch=%08X dptch=%08X\n", saddr, daddr, SPTCH(), DPTCH()));
1431	1340
1432	1341	/* bail if we're clipped */
1433	1342	if (dx <= 0 \|\| dy <= 0)
1434	1343	return;
1435	1344
1436	1345	/* window mode 1: just return and interrupt if we are within the window */
1437		if (WINDOW_CHECKING(~~tms~~) == 1 && !dst_is_linear)
	1346	if (WINDOW_CHECKING() == 1 && !dst_is_linear)
1438	1347	{
1439		CLR_V(tms);
1440		DADDR_XY(tms) = dstxy;
1441		DYDX_X(tms) = dx;
1442		DYDX_Y(tms) = dy;
1443		IOREG(tms, REG_INTPEND) \|= TMS34010_WV;
1444		check_interrupt(tms);
	1348	CLR_V();
	1349	DADDR_XY() = dstxy;
	1350	DYDX_X() = dx;
	1351	DYDX_Y() = dy;
	1352	IOREG(REG_INTPEND) \|= TMS34010_WV;
	1353	check_interrupt();
1445	1354	return;
1446	1355	}
1447	1356
1448	1357	/* handle flipping the addresses */
1449		yreverse = (IOREG(~~tms,~~ REG_CONTROL) >> 9) & 1;
	1358	yreverse = (IOREG(REG_CONTROL) >> 9) & 1;
1450	1359	if (!src_is_linear \|\| !dst_is_linear)
1451	1360	{
1452	1361	saddr += dx * BITS_PER_PIXEL;
1453	1362	daddr += dx * BITS_PER_PIXEL;
1454	1363	if (yreverse)
1455	1364	{
1456		saddr += (dy - 1) * tms->convsp;
1457		daddr += (dy - 1) * tms->convdp;
	1365	saddr += (dy - 1) * m_convsp;
	1366	daddr += (dy - 1) * m_convdp;
1458	1367	}
1459	1368	}
1460	1369
1461		tm~~s->~~st \|= STBIT_P;
	1370	m_st \|= STBIT_P;
1462	1371
1463	1372	/* loop over rows */
1464	1373	for (y = 0; y < dy; y++)
r31176	r31177
1481	1390	full_words /= PIXELS_PER_WORD;
1482	1391
1483	1392	/* compute cycles */
1484		tm~~s->~~gfxcycles += compute_pixblt_cycles(left_partials, right_partials, full_words, PIXEL_OP_TIMING);
	1393	m_gfxcycles += compute_pixblt_cycles(left_partials, right_partials, full_words, PIXEL_OP_TIMING);
1485	1394
1486	1395	/* use word addresses each row */
1487	1396	swordaddr = (saddr + 15) >> 4;
1488	1397	dwordaddr = (daddr + 15) >> 4;
1489	1398
1490	1399	/* fetch the initial source word */
1491		srcword = (word_read)(tm~~s->~~program, --swordaddr << 1);
	1400	srcword = (this->word_read)(m_program, --swordaddr << 1);
1492	1401	srcmask = PIXEL_MASK << ((saddr - BITS_PER_PIXEL) & 15);
1493	1402
1494	1403	/* handle the right partial word */
1495	1404	if (right_partials != 0)
1496	1405	{
1497	1406	/* fetch the destination word */
1498		dstword = (word_read)(tm~~s->~~program, --dwordaddr << 1);
	1407	dstword = (this->word_read)(m_program, --dwordaddr << 1);
1499	1408	dstmask = PIXEL_MASK << ((daddr - BITS_PER_PIXEL) & 15);
1500	1409
1501	1410	/* loop over partials */
r31176	r31177
1504	1413	/* fetch source pixel if necessary */
1505	1414	if (srcmask == 0)
1506	1415	{
1507		srcword = (word_read)(tm~~s->~~program, --swordaddr << 1);
	1416	srcword = (this->word_read)(m_program, --swordaddr << 1);
1508	1417	srcmask = PIXEL_MASK << (16 - BITS_PER_PIXEL);
1509	1418	}
1510	1419
r31176	r31177
1526	1435	}
1527	1436
1528	1437	/* write the result */
1529		(word_write)(tm~~s->~~program, dwordaddr << 1, dstword);
	1438	(this->word_write)(m_program, dwordaddr << 1, dstword);
1530	1439	}
1531	1440
1532	1441	/* loop over full words */
r31176	r31177
1535	1444	/* fetch the destination word (if necessary) */
1536	1445	dwordaddr--;
1537	1446	if (PIXEL_OP_REQUIRES_SOURCE \|\| TRANSPARENCY)
1538		dstword = (word_read)(tm~~s->~~program, dwordaddr << 1);
	1447	dstword = (this->word_read)(m_program, dwordaddr << 1);
1539	1448	else
1540	1449	dstword = 0;
1541	1450	dstmask = PIXEL_MASK << (16 - BITS_PER_PIXEL);
r31176	r31177
1546	1455	/* fetch source pixel if necessary */
1547	1456	if (srcmask == 0)
1548	1457	{
1549		srcword = (word_read)(tm~~s->~~program, --swordaddr << 1);
	1458	srcword = (this->word_read)(m_program, --swordaddr << 1);
1550	1459	srcmask = PIXEL_MASK << (16 - BITS_PER_PIXEL);
1551	1460	}
1552	1461
r31176	r31177
1568	1477	}
1569	1478
1570	1479	/* write the result */
1571		(word_write)(tm~~s->~~program, dwordaddr << 1, dstword);
	1480	(this->word_write)(m_program, dwordaddr << 1, dstword);
1572	1481	}
1573	1482
1574	1483	/* handle the left partial word */
1575	1484	if (left_partials != 0)
1576	1485	{
1577	1486	/* fetch the destination word */
1578		dstword = (word_read)(tm~~s->~~program, --dwordaddr << 1);
	1487	dstword = (this->word_read)(m_program, --dwordaddr << 1);
1579	1488	dstmask = PIXEL_MASK << (16 - BITS_PER_PIXEL);
1580	1489
1581	1490	/* loop over partials */
r31176	r31177
1584	1493	/* fetch the source pixel if necessary */
1585	1494	if (srcmask == 0)
1586	1495	{
1587		srcword = (word_read)(tm~~s->~~program, --swordaddr << 1);
	1496	srcword = (this->word_read)(m_program, --swordaddr << 1);
1588	1497	srcmask = PIXEL_MASK << (16 - BITS_PER_PIXEL);
1589	1498	}
1590	1499
r31176	r31177
1606	1515	}
1607	1516
1608	1517	/* write the result */
1609		(word_write)(tm~~s->~~program, dwordaddr << 1, dstword);
	1518	(this->word_write)(m_program, dwordaddr << 1, dstword);
1610	1519	}
1611	1520
1612	1521	/* update for next row */
1613	1522	if (!yreverse)
1614	1523	{
1615		saddr += SPTCH(tms);
1616		daddr += DPTCH(tms);
	1524	saddr += SPTCH();
	1525	daddr += DPTCH();
1617	1526	}
1618	1527	else
1619	1528	{
1620		saddr -= SPTCH(tms);
1621		daddr -= DPTCH(tms);
	1529	saddr -= SPTCH();
	1530	daddr -= DPTCH();
1622	1531	}
1623	1532	}
1624		LOGGFX((" (%d cycles)\n", tm~~s->~~gfxcycles));
	1533	LOGGFX((" (%d cycles)\n", m_gfxcycles));
1625	1534	}
1626	1535
1627	1536	/* eat cycles */
1628		if (tm~~s->~~gfxcycles > tm~~s->~~icount)
	1537	if (m_gfxcycles > m_icount)
1629	1538	{
1630		tms->gfxcycles -= tms->icount;
1631		tms->icount = 0;
1632		tms->pc -= 0x10;
	1539	m_gfxcycles -= m_icount;
	1540	m_icount = 0;
	1541	m_pc -= 0x10;
1633	1542	}
1634	1543	else
1635	1544	{
1636		tms->icount -= tms->gfxcycles;
1637		tms->st &= ~STBIT_P;
	1545	m_icount -= m_gfxcycles;
	1546	m_st &= ~STBIT_P;
1638	1547	if (src_is_linear && dst_is_linear)
1639		SADDR(~~tms~~) += DYDX_Y(~~tms~~) * SPTCH(~~tms~~);
	1548	SADDR() += DYDX_Y() * SPTCH();
1640	1549	else if (src_is_linear)
1641		SADDR(~~tms~~) += DYDX_Y(~~tms~~) * SPTCH(~~tms~~);
	1550	SADDR() += DYDX_Y() * SPTCH();
1642	1551	else
1643		SADDR_Y(~~tms~~) += DYDX_Y(~~tms~~);
	1552	SADDR_Y() += DYDX_Y();
1644	1553	if (dst_is_linear)
1645		DADDR(~~tms~~) += DYDX_Y(~~tms~~) * DPTCH(~~tms~~);
	1554	DADDR() += DYDX_Y() * DPTCH();
1646	1555	else
1647		DADDR_Y(~~tms~~) += DYDX_Y(~~tms~~);
	1556	DADDR_Y() += DYDX_Y();
1648	1557	}
1649	1558	}
1650	1559
1651		~~static~~ void FUNCTION_NAME(~~pixbl~~t~~_b)(t~~ms34010_~~stat~~e *t~~ms,~~ int dst_is_linear)
	1560	void FUNCTION_NAME(tms340x0_device::pixblt_b)(int dst_is_linear)
1652	1561	{
1653	1562	/* if this is the first time through, perform the operation */
1654		if (!P_FLAG(~~tms~~))
	1563	if (!P_FLAG())
1655	1564	{
1656	1565	int dx, dy, x, y, words, left_partials, right_partials, full_words;
1657		void (*word_write)(address_space &space,offs_t address,UINT16 data);
1658		UINT16 (*word_read)(address_space &space,offs_t address);
	1566	word_write_func word_write;
	1567	word_read_func word_read;
1659	1568	UINT32 saddr, daddr;
1660	1569	XY dstxy = { 0 };
1661	1570
1662	1571	/* determine read/write functions */
1663		if (IOREG(~~tms,~~ REG_DPYCTL) & 0x0800)
	1572	if (IOREG(REG_DPYCTL) & 0x0800)
1664	1573	{
1665		word_write = shiftreg_w;
1666		word_read = shiftreg_r;
	1574	word_write = &tms340x0_device::shiftreg_w;
	1575	word_read = &tms340x0_device::shiftreg_r;
1667	1576	}
1668	1577	else
1669	1578	{
1670		word_write = memory_w;
1671		word_read = memory_r;
	1579	word_write = &tms340x0_device::memory_w;
	1580	word_read = &tms340x0_device::memory_r;
1672	1581	}
1673	1582
1674	1583	/* compute the starting addresses */
1675		saddr = SADDR(~~tms~~);
	1584	saddr = SADDR();
1676	1585
1677	1586	/* compute the bounds of the operation */
1678		dx = (INT16)DYDX_X(tms);
1679		dy = (INT16)DYDX_Y(tms);
	1587	dx = (INT16)DYDX_X();
	1588	dy = (INT16)DYDX_Y();
1680	1589
1681	1590	/* apply the window for non-linear destinations */
1682		tm~~s->~~gfxcycles = 4;
	1591	m_gfxcycles = 4;
1683	1592	if (!dst_is_linear)
1684	1593	{
1685		dstxy = DADDR_XY(tms);
1686		tms->gfxcycles += 2 + apply_window(tms, "PIXBLT B", 1, &saddr, &dstxy, &dx, &dy);
1687		daddr = DXYTOL(tms,dstxy);
	1594	dstxy = DADDR_XY();
	1595	m_gfxcycles += 2 + apply_window("PIXBLT B", 1, &saddr, &dstxy, &dx, &dy);
	1596	daddr = DXYTOL(dstxy);
1688	1597	}
1689	1598	else
1690		daddr = DADDR(~~tms~~);
	1599	daddr = DADDR();
1691	1600	daddr &= ~(BITS_PER_PIXEL - 1);
1692		LOGGFX((" saddr=%08X daddr=%08X sptch=%08X dptch=%08X\n", saddr, daddr, SPTCH(~~tms~~), DPTCH(~~tms~~)));
	1601	LOGGFX((" saddr=%08X daddr=%08X sptch=%08X dptch=%08X\n", saddr, daddr, SPTCH(), DPTCH()));
1693	1602
1694	1603	/* bail if we're clipped */
1695	1604	if (dx <= 0 \|\| dy <= 0)
1696	1605	return;
1697	1606
1698	1607	/* window mode 1: just return and interrupt if we are within the window */
1699		if (WINDOW_CHECKING(~~tms~~) == 1 && !dst_is_linear)
	1608	if (WINDOW_CHECKING() == 1 && !dst_is_linear)
1700	1609	{
1701		CLR_V(tms);
1702		DADDR_XY(tms) = dstxy;
1703		DYDX_X(tms) = dx;
1704		DYDX_Y(tms) = dy;
1705		IOREG(tms, REG_INTPEND) \|= TMS34010_WV;
1706		check_interrupt(tms);
	1610	CLR_V();
	1611	DADDR_XY() = dstxy;
	1612	DYDX_X() = dx;
	1613	DYDX_Y() = dy;
	1614	IOREG(REG_INTPEND) \|= TMS34010_WV;
	1615	check_interrupt();
1707	1616	return;
1708	1617	}
1709	1618
r31176	r31177
1717	1626	full_words /= PIXELS_PER_WORD;
1718	1627
1719	1628	/* compute cycles */
1720		tms->gfxcycles += compute_pixblt_b_cycles(left_partials, right_partials, full_words, dy, PIXEL_OP_TIMING, BITS_PER_PIXEL);
1721		tms->st \|= STBIT_P;
	1629	m_gfxcycles += compute_pixblt_b_cycles(left_partials, right_partials, full_words, dy, PIXEL_OP_TIMING, BITS_PER_PIXEL);
	1630	m_st \|= STBIT_P;
1722	1631
1723	1632	/* loop over rows */
1724	1633	for (y = 0; y < dy; y++)
r31176	r31177
1731	1640	dwordaddr = daddr >> 4;
1732	1641
1733	1642	/* fetch the initial source word */
1734		srcword = (word_read)(tm~~s->~~program, swordaddr++ << 1);
	1643	srcword = (this->word_read)(m_program, swordaddr++ << 1);
1735	1644	srcmask = 1 << (saddr & 15);
1736	1645
1737	1646	/* handle the left partial word */
1738	1647	if (left_partials != 0)
1739	1648	{
1740	1649	/* fetch the destination word */
1741		dstword = (word_read)(tm~~s->~~program, dwordaddr << 1);
	1650	dstword = (this->word_read)(m_program, dwordaddr << 1);
1742	1651	dstmask = PIXEL_MASK << (daddr & 15);
1743	1652
1744	1653	/* loop over partials */
1745	1654	for (x = 0; x < left_partials; x++)
1746	1655	{
1747	1656	/* process the pixel */
1748		pixel = (srcword & srcmask) ? COLOR1(~~tms~~) : COLOR0(~~tms~~);
	1657	pixel = (srcword & srcmask) ? COLOR1() : COLOR0();
1749	1658	pixel &= dstmask;
1750	1659	PIXEL_OP(dstword, dstmask, pixel);
1751	1660	if (!TRANSPARENCY \|\| pixel != 0)
r31176	r31177
1755	1664	srcmask <<= 1;
1756	1665	if (srcmask == 0)
1757	1666	{
1758		srcword = (word_read)(tm~~s->~~program, swordaddr++ << 1);
	1667	srcword = (this->word_read)(m_program, swordaddr++ << 1);
1759	1668	srcmask = 0x0001;
1760	1669	}
1761	1670
r31176	r31177
1764	1673	}
1765	1674
1766	1675	/* write the result */
1767		(word_write)(tm~~s->~~program, dwordaddr++ << 1, dstword);
	1676	(this->word_write)(m_program, dwordaddr++ << 1, dstword);
1768	1677	}
1769	1678
1770	1679	/* loop over full words */
r31176	r31177
1772	1681	{
1773	1682	/* fetch the destination word (if necessary) */
1774	1683	if (PIXEL_OP_REQUIRES_SOURCE \|\| TRANSPARENCY)
1775		dstword = (word_read)(tm~~s->~~program, dwordaddr << 1);
	1684	dstword = (this->word_read)(m_program, dwordaddr << 1);
1776	1685	else
1777	1686	dstword = 0;
1778	1687	dstmask = PIXEL_MASK;
r31176	r31177
1781	1690	for (x = 0; x < PIXELS_PER_WORD; x++)
1782	1691	{
1783	1692	/* process the pixel */
1784		pixel = (srcword & srcmask) ? COLOR1(~~tms~~) : COLOR0(~~tms~~);
	1693	pixel = (srcword & srcmask) ? COLOR1() : COLOR0();
1785	1694	pixel &= dstmask;
1786	1695	PIXEL_OP(dstword, dstmask, pixel);
1787	1696	if (!TRANSPARENCY \|\| pixel != 0)
r31176	r31177
1791	1700	srcmask <<= 1;
1792	1701	if (srcmask == 0)
1793	1702	{
1794		srcword = (word_read)(tm~~s->~~program, swordaddr++ << 1);
	1703	srcword = (this->word_read)(m_program, swordaddr++ << 1);
1795	1704	srcmask = 0x0001;
1796	1705	}
1797	1706
r31176	r31177
1800	1709	}
1801	1710
1802	1711	/* write the result */
1803		(word_write)(tm~~s->~~program, dwordaddr++ << 1, dstword);
	1712	(this->word_write)(m_program, dwordaddr++ << 1, dstword);
1804	1713	}
1805	1714
1806	1715	/* handle the right partial word */
1807	1716	if (right_partials != 0)
1808	1717	{
1809	1718	/* fetch the destination word */
1810		dstword = (word_read)(tm~~s->~~program, dwordaddr << 1);
	1719	dstword = (this->word_read)(m_program, dwordaddr << 1);
1811	1720	dstmask = PIXEL_MASK;
1812	1721
1813	1722	/* loop over partials */
1814	1723	for (x = 0; x < right_partials; x++)
1815	1724	{
1816	1725	/* process the pixel */
1817		pixel = (srcword & srcmask) ? COLOR1(~~tms~~) : COLOR0(~~tms~~);
	1726	pixel = (srcword & srcmask) ? COLOR1() : COLOR0();
1818	1727	pixel &= dstmask;
1819	1728	PIXEL_OP(dstword, dstmask, pixel);
1820	1729	if (!TRANSPARENCY \|\| pixel != 0)
r31176	r31177
1824	1733	srcmask <<= 1;
1825	1734	if (srcmask == 0)
1826	1735	{
1827		srcword = (word_read)(tm~~s->~~program, swordaddr++ << 1);
	1736	srcword = (this->word_read)(m_program, swordaddr++ << 1);
1828	1737	srcmask = 0x0001;
1829	1738	}
1830	1739
r31176	r31177
1833	1742	}
1834	1743
1835	1744	/* write the result */
1836		(word_write)(tm~~s->~~program, dwordaddr++ << 1, dstword);
	1745	(this->word_write)(m_program, dwordaddr++ << 1, dstword);
1837	1746	}
1838	1747
1839	1748	/* update for next row */
1840		saddr += SPTCH(tms);
1841		daddr += DPTCH(tms);
	1749	saddr += SPTCH();
	1750	daddr += DPTCH();
1842	1751	}
1843		LOGGFX((" (%d cycles)\n", tm~~s->~~gfxcycles));
	1752	LOGGFX((" (%d cycles)\n", m_gfxcycles));
1844	1753	}
1845	1754
1846	1755	/* eat cycles */
1847		if (tm~~s->~~gfxcycles > tm~~s->~~icount)
	1756	if (m_gfxcycles > m_icount)
1848	1757	{
1849		tms->gfxcycles -= tms->icount;
1850		tms->icount = 0;
1851		tms->pc -= 0x10;
	1758	m_gfxcycles -= m_icount;
	1759	m_icount = 0;
	1760	m_pc -= 0x10;
1852	1761	}
1853	1762	else
1854	1763	{
1855		tms->icount -= tms->gfxcycles;
1856		tms->st &= ~STBIT_P;
1857		SADDR(tms) += DYDX_Y(tms) * SPTCH(tms);
	1764	m_icount -= m_gfxcycles;
	1765	m_st &= ~STBIT_P;
	1766	SADDR() += DYDX_Y() * SPTCH();
1858	1767	if (dst_is_linear)
1859		DADDR(~~tms~~) += DYDX_Y(~~tms~~) * DPTCH(~~tms~~);
	1768	DADDR() += DYDX_Y() * DPTCH();
1860	1769	else
1861		DADDR_Y(~~tms~~) += DYDX_Y(~~tms~~);
	1770	DADDR_Y() += DYDX_Y();
1862	1771	}
1863	1772	}
1864	1773
1865		~~static~~ void FUNCTION_NAME(~~fill)(~~tms34010_~~stat~~e *tms, int dst_is_linear)
	1774	void FUNCTION_NAME(tms340x0_device::fill)(int dst_is_linear)
1866	1775	{
1867	1776	/* if this is the first time through, perform the operation */
1868		if (!P_FLAG(~~tms~~))
	1777	if (!P_FLAG())
1869	1778	{
1870	1779	int dx, dy, x, y, words, left_partials, right_partials, full_words;
1871		void (*word_write)(address_space &space,offs_t address,UINT16 data);
1872		UINT16 (*word_read)(address_space &space,offs_t address);
	1780	word_write_func word_write;
	1781	word_read_func word_read;
1873	1782	UINT32 daddr;
1874	1783	XY dstxy = { 0 };
1875	1784
1876	1785	/* determine read/write functions */
1877		if (IOREG(~~tms,~~ REG_DPYCTL) & 0x0800)
	1786	if (IOREG(REG_DPYCTL) & 0x0800)
1878	1787	{
1879		word_write = shiftreg_w;
1880		word_read = dummy_shiftreg_r;
	1788	word_write = &tms340x0_device::shiftreg_w;
	1789	word_read = &tms340x0_device::dummy_shiftreg_r;
1881	1790	}
1882	1791	else
1883	1792	{
1884		word_write = memory_w;
1885		word_read = memory_r;
	1793	word_write = &tms340x0_device::memory_w;
	1794	word_read = &tms340x0_device::memory_r;
1886	1795	}
1887	1796
1888	1797	/* compute the bounds of the operation */
1889		dx = (INT16)DYDX_X(tms);
1890		dy = (INT16)DYDX_Y(tms);
	1798	dx = (INT16)DYDX_X();
	1799	dy = (INT16)DYDX_Y();
1891	1800
1892	1801	/* apply the window for non-linear destinations */
1893		tm~~s->~~gfxcycles = 4;
	1802	m_gfxcycles = 4;
1894	1803	if (!dst_is_linear)
1895	1804	{
1896		dstxy = DADDR_XY(tms);
1897		tms->gfxcycles += 2 + apply_window(tms, "FILL", 0, NULL, &dstxy, &dx, &dy);
1898		daddr = DXYTOL(tms,dstxy);
	1805	dstxy = DADDR_XY();
	1806	m_gfxcycles += 2 + apply_window("FILL", 0, NULL, &dstxy, &dx, &dy);
	1807	daddr = DXYTOL(dstxy);
1899	1808	}
1900	1809	else
1901		daddr = DADDR(~~tms~~);
	1810	daddr = DADDR();
1902	1811	daddr &= ~(BITS_PER_PIXEL - 1);
1903	1812	LOGGFX((" daddr=%08X\n", daddr));
1904	1813
r31176	r31177
1907	1816	return;
1908	1817
1909	1818	/* window mode 1: just return and interrupt if we are within the window */
1910		if (WINDOW_CHECKING(~~tms~~) == 1 && !dst_is_linear)
	1819	if (WINDOW_CHECKING() == 1 && !dst_is_linear)
1911	1820	{
1912		CLR_V(tms);
1913		DADDR_XY(tms) = dstxy;
1914		DYDX_X(tms) = dx;
1915		DYDX_Y(tms) = dy;
1916		IOREG(tms, REG_INTPEND) \|= TMS34010_WV;
1917		check_interrupt(tms);
	1821	CLR_V();
	1822	DADDR_XY() = dstxy;
	1823	DYDX_X() = dx;
	1824	DYDX_Y() = dy;
	1825	IOREG(REG_INTPEND) \|= TMS34010_WV;
	1826	check_interrupt();
1918	1827	return;
1919	1828	}
1920	1829
r31176	r31177
1928	1837	full_words /= PIXELS_PER_WORD;
1929	1838
1930	1839	/* compute cycles */
1931		tms->gfxcycles += 2;
1932		tms->st \|= STBIT_P;
	1840	m_gfxcycles += 2;
	1841	m_st \|= STBIT_P;
1933	1842
1934	1843	/* loop over rows */
1935	1844	for (y = 0; y < dy; y++)
r31176	r31177
1941	1850	dwordaddr = daddr >> 4;
1942	1851
1943	1852	/* compute cycles */
1944		tm~~s->~~gfxcycles += compute_fill_cycles(left_partials, right_partials, full_words, PIXEL_OP_TIMING);
	1853	m_gfxcycles += compute_fill_cycles(left_partials, right_partials, full_words, PIXEL_OP_TIMING);
1945	1854
1946	1855	/* handle the left partial word */
1947	1856	if (left_partials != 0)
1948	1857	{
1949	1858	/* fetch the destination word */
1950		dstword = (word_read)(tm~~s->~~program, dwordaddr << 1);
	1859	dstword = (this->word_read)(m_program, dwordaddr << 1);
1951	1860	dstmask = PIXEL_MASK << (daddr & 15);
1952	1861
1953	1862	/* loop over partials */
1954	1863	for (x = 0; x < left_partials; x++)
1955	1864	{
1956	1865	/* process the pixel */
1957		pixel = COLOR1(~~tms~~) & dstmask;
	1866	pixel = COLOR1() & dstmask;
1958	1867	PIXEL_OP(dstword, dstmask, pixel);
1959	1868	if (!TRANSPARENCY \|\| pixel != 0)
1960	1869	dstword = (dstword & ~dstmask) \| pixel;
r31176	r31177
1964	1873	}
1965	1874
1966	1875	/* write the result */
1967		(word_write)(tm~~s->~~program, dwordaddr++ << 1, dstword);
	1876	(this->word_write)(m_program, dwordaddr++ << 1, dstword);
1968	1877	}
1969	1878
1970	1879	/* loop over full words */
r31176	r31177
1972	1881	{
1973	1882	/* fetch the destination word (if necessary) */
1974	1883	if (PIXEL_OP_REQUIRES_SOURCE \|\| TRANSPARENCY)
1975		dstword = (word_read)(tm~~s->~~program, dwordaddr << 1);
	1884	dstword = (this->word_read)(m_program, dwordaddr << 1);
1976	1885	else
1977	1886	dstword = 0;
1978	1887	dstmask = PIXEL_MASK;
r31176	r31177
1981	1890	for (x = 0; x < PIXELS_PER_WORD; x++)
1982	1891	{
1983	1892	/* process the pixel */
1984		pixel = COLOR1(~~tms~~) & dstmask;
	1893	pixel = COLOR1() & dstmask;
1985	1894	PIXEL_OP(dstword, dstmask, pixel);
1986	1895	if (!TRANSPARENCY \|\| pixel != 0)
1987	1896	dstword = (dstword & ~dstmask) \| pixel;
r31176	r31177
1991	1900	}
1992	1901
1993	1902	/* write the result */
1994		(word_write)(tm~~s->~~program, dwordaddr++ << 1, dstword);
	1903	(this->word_write)(m_program, dwordaddr++ << 1, dstword);
1995	1904	}
1996	1905
1997	1906	/* handle the right partial word */
1998	1907	if (right_partials != 0)
1999	1908	{
2000	1909	/* fetch the destination word */
2001		dstword = (word_read)(tm~~s->~~program, dwordaddr << 1);
	1910	dstword = (this->word_read)(m_program, dwordaddr << 1);
2002	1911	dstmask = PIXEL_MASK;
2003	1912
2004	1913	/* loop over partials */
2005	1914	for (x = 0; x < right_partials; x++)
2006	1915	{
2007	1916	/* process the pixel */
2008		pixel = COLOR1(~~tms~~) & dstmask;
	1917	pixel = COLOR1() & dstmask;
2009	1918	PIXEL_OP(dstword, dstmask, pixel);
2010	1919	if (!TRANSPARENCY \|\| pixel != 0)
2011	1920	dstword = (dstword & ~dstmask) \| pixel;
r31176	r31177
2015	1924	}
2016	1925
2017	1926	/* write the result */
2018		(word_write)(tm~~s->~~program, dwordaddr++ << 1, dstword);
	1927	(this->word_write)(m_program, dwordaddr++ << 1, dstword);
2019	1928	}
2020	1929
2021	1930	/* update for next row */
2022		daddr += DPTCH(~~tms~~);
	1931	daddr += DPTCH();
2023	1932	}
2024	1933
2025		LOGGFX((" (%d cycles)\n", tm~~s->~~gfxcycles));
	1934	LOGGFX((" (%d cycles)\n", m_gfxcycles));
2026	1935	}
2027	1936
2028	1937	/* eat cycles */
2029		if (tm~~s->~~gfxcycles > tm~~s->~~icount)
	1938	if (m_gfxcycles > m_icount)
2030	1939	{
2031		tms->gfxcycles -= tms->icount;
2032		tms->icount = 0;
2033		tms->pc -= 0x10;
	1940	m_gfxcycles -= m_icount;
	1941	m_icount = 0;
	1942	m_pc -= 0x10;
2034	1943	}
2035	1944	else
2036	1945	{
2037		tms->icount -= tms->gfxcycles;
2038		tms->st &= ~STBIT_P;
	1946	m_icount -= m_gfxcycles;
	1947	m_st &= ~STBIT_P;
2039	1948	if (dst_is_linear)
2040		DADDR(~~tms~~) += DYDX_Y(~~tms~~) * DPTCH(~~tms~~);
	1949	DADDR() += DYDX_Y() * DPTCH();
2041	1950	else
2042		DADDR_Y(~~tms~~) += DYDX_Y(~~tms~~);
	1951	DADDR_Y() += DYDX_Y();
2043	1952	}
2044	1953	}
2045	1954

trunk/src/emu/cpu/tms34010/34010fld.c
r31176	r31177
13	13	FIELD WRITE FUNCTIONS
14	14	***************************************************************************/
15	15
16		~~static~~ void wfield_01(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	16	void tms340x0_device::wfield_01(offs_t offset, UINT32 data)
17	17	{
18		WFIELDMAC(~~tms,~~0x01,16);
	18	WFIELDMAC(0x01,16);
19	19	}
20	20
21		~~static~~ void wfield_02(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	21	void tms340x0_device::wfield_02(offs_t offset, UINT32 data)
22	22	{
23		WFIELDMAC(~~tms,~~0x03,15);
	23	WFIELDMAC(0x03,15);
24	24	}
25	25
26		~~static~~ void wfield_03(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	26	void tms340x0_device::wfield_03(offs_t offset, UINT32 data)
27	27	{
28		WFIELDMAC(~~tms,~~0x07,14);
	28	WFIELDMAC(0x07,14);
29	29	}
30	30
31		~~static~~ void wfield_04(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	31	void tms340x0_device::wfield_04(offs_t offset, UINT32 data)
32	32	{
33		WFIELDMAC(~~tms,~~0x0f,13);
	33	WFIELDMAC(0x0f,13);
34	34	}
35	35
36		~~static~~ void wfield_05(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	36	void tms340x0_device::wfield_05(offs_t offset, UINT32 data)
37	37	{
38		WFIELDMAC(~~tms,~~0x1f,12);
	38	WFIELDMAC(0x1f,12);
39	39	}
40	40
41		~~static~~ void wfield_06(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	41	void tms340x0_device::wfield_06(offs_t offset, UINT32 data)
42	42	{
43		WFIELDMAC(~~tms,~~0x3f,11);
	43	WFIELDMAC(0x3f,11);
44	44	}
45	45
46		~~static~~ void wfield_07(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	46	void tms340x0_device::wfield_07(offs_t offset, UINT32 data)
47	47	{
48		WFIELDMAC(~~tms,~~0x7f,10);
	48	WFIELDMAC(0x7f,10);
49	49	}
50	50
51		~~static~~ void wfield_08(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	51	void tms340x0_device::wfield_08(offs_t offset, UINT32 data)
52	52	{
53		WFIELDMAC_8(~~tms~~);
	53	WFIELDMAC_8();
54	54	}
55	55
56		~~static~~ void wfield_09(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	56	void tms340x0_device::wfield_09(offs_t offset, UINT32 data)
57	57	{
58		WFIELDMAC(~~tms,~~0x1ff,8);
	58	WFIELDMAC(0x1ff,8);
59	59	}
60	60
61		~~static~~ void wfield_10(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	61	void tms340x0_device::wfield_10(offs_t offset, UINT32 data)
62	62	{
63		WFIELDMAC(~~tms,~~0x3ff,7);
	63	WFIELDMAC(0x3ff,7);
64	64	}
65	65
66		~~static~~ void wfield_11(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	66	void tms340x0_device::wfield_11(offs_t offset, UINT32 data)
67	67	{
68		WFIELDMAC(~~tms,~~0x7ff,6);
	68	WFIELDMAC(0x7ff,6);
69	69	}
70	70
71		~~static~~ void wfield_12(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	71	void tms340x0_device::wfield_12(offs_t offset, UINT32 data)
72	72	{
73		WFIELDMAC(~~tms,~~0xfff,5);
	73	WFIELDMAC(0xfff,5);
74	74	}
75	75
76		~~static~~ void wfield_13(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	76	void tms340x0_device::wfield_13(offs_t offset, UINT32 data)
77	77	{
78		WFIELDMAC(~~tms,~~0x1fff,4);
	78	WFIELDMAC(0x1fff,4);
79	79	}
80	80
81		~~static~~ void wfield_14(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	81	void tms340x0_device::wfield_14(offs_t offset, UINT32 data)
82	82	{
83		WFIELDMAC(~~tms,~~0x3fff,3);
	83	WFIELDMAC(0x3fff,3);
84	84	}
85	85
86		~~static~~ void wfield_15(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	86	void tms340x0_device::wfield_15(offs_t offset, UINT32 data)
87	87	{
88		WFIELDMAC(~~tms,~~0x7fff,2);
	88	WFIELDMAC(0x7fff,2);
89	89	}
90	90
91		~~static~~ void wfield_16(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	91	void tms340x0_device::wfield_16(offs_t offset, UINT32 data)
92	92	{
93	93	if (offset & 0x0f)
94	94	{
95		WFIELDMAC(~~tms,~~0xffff,1);
	95	WFIELDMAC(0xffff,1);
96	96	}
97	97	else
98	98	{
99		TMS34010_WRMEM_WORD(~~tms,~~TOBYTE(offset),data);
	99	TMS34010_WRMEM_WORD(TOBYTE(offset),data);
100	100	}
101	101	}
102	102
103		~~static~~ void wfield_17(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	103	void tms340x0_device::wfield_17(offs_t offset, UINT32 data)
104	104	{
105		WFIELDMAC(~~tms,~~0x1ffff,0);
	105	WFIELDMAC(0x1ffff,0);
106	106	}
107	107
108		~~static~~ void wfield_18(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	108	void tms340x0_device::wfield_18(offs_t offset, UINT32 data)
109	109	{
110		WFIELDMAC_BIG(~~tms,~~0x3ffff,15);
	110	WFIELDMAC_BIG(0x3ffff,15);
111	111	}
112	112
113		~~static~~ void wfield_19(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	113	void tms340x0_device::wfield_19(offs_t offset, UINT32 data)
114	114	{
115		WFIELDMAC_BIG(~~tms,~~0x7ffff,14);
	115	WFIELDMAC_BIG(0x7ffff,14);
116	116	}
117	117
118		~~static~~ void wfield_20(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	118	void tms340x0_device::wfield_20(offs_t offset, UINT32 data)
119	119	{
120		WFIELDMAC_BIG(~~tms,~~0xfffff,13);
	120	WFIELDMAC_BIG(0xfffff,13);
121	121	}
122	122
123		~~static~~ void wfield_21(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	123	void tms340x0_device::wfield_21(offs_t offset, UINT32 data)
124	124	{
125		WFIELDMAC_BIG(~~tms,~~0x1fffff,12);
	125	WFIELDMAC_BIG(0x1fffff,12);
126	126	}
127	127
128		~~static~~ void wfield_22(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	128	void tms340x0_device::wfield_22(offs_t offset, UINT32 data)
129	129	{
130		WFIELDMAC_BIG(~~tms,~~0x3fffff,11);
	130	WFIELDMAC_BIG(0x3fffff,11);
131	131	}
132	132
133		~~static~~ void wfield_23(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	133	void tms340x0_device::wfield_23(offs_t offset, UINT32 data)
134	134	{
135		WFIELDMAC_BIG(~~tms,~~0x7fffff,10);
	135	WFIELDMAC_BIG(0x7fffff,10);
136	136	}
137	137
138		~~static~~ void wfield_24(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	138	void tms340x0_device::wfield_24(offs_t offset, UINT32 data)
139	139	{
140		WFIELDMAC_BIG(~~tms,~~0xffffff,9);
	140	WFIELDMAC_BIG(0xffffff,9);
141	141	}
142	142
143		~~static~~ void wfield_25(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	143	void tms340x0_device::wfield_25(offs_t offset, UINT32 data)
144	144	{
145		WFIELDMAC_BIG(~~tms,~~0x1ffffff,8);
	145	WFIELDMAC_BIG(0x1ffffff,8);
146	146	}
147	147
148		~~static~~ void wfield_26(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	148	void tms340x0_device::wfield_26(offs_t offset, UINT32 data)
149	149	{
150		WFIELDMAC_BIG(~~tms,~~0x3ffffff,7);
	150	WFIELDMAC_BIG(0x3ffffff,7);
151	151	}
152	152
153		~~static~~ void wfield_27(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	153	void tms340x0_device::wfield_27(offs_t offset, UINT32 data)
154	154	{
155		WFIELDMAC_BIG(~~tms,~~0x7ffffff,6);
	155	WFIELDMAC_BIG(0x7ffffff,6);
156	156	}
157	157
158		~~static~~ void wfield_28(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	158	void tms340x0_device::wfield_28(offs_t offset, UINT32 data)
159	159	{
160		WFIELDMAC_BIG(~~tms,~~0xfffffff,5);
	160	WFIELDMAC_BIG(0xfffffff,5);
161	161	}
162	162
163		~~static~~ void wfield_29(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	163	void tms340x0_device::wfield_29(offs_t offset, UINT32 data)
164	164	{
165		WFIELDMAC_BIG(~~tms,~~0x1fffffff,4);
	165	WFIELDMAC_BIG(0x1fffffff,4);
166	166	}
167	167
168		~~static~~ void wfield_30(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	168	void tms340x0_device::wfield_30(offs_t offset, UINT32 data)
169	169	{
170		WFIELDMAC_BIG(~~tms,~~0x3fffffff,3);
	170	WFIELDMAC_BIG(0x3fffffff,3);
171	171	}
172	172
173		~~static~~ void wfield_31(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	173	void tms340x0_device::wfield_31(offs_t offset, UINT32 data)
174	174	{
175		WFIELDMAC_BIG(~~tms,~~0x7fffffff,2);
	175	WFIELDMAC_BIG(0x7fffffff,2);
176	176	}
177	177
178		~~static~~ void wfield_32(~~tms34010_state *tms,~~ offs_t offset, UINT32 data)
	178	void tms340x0_device::wfield_32(offs_t offset, UINT32 data)
179	179	{
180		WFIELDMAC_32(~~tms~~);
	180	WFIELDMAC_32();
181	181	}
182	182
183	183
184		~~stati~~c vo~~id (co~~nst tms34010_wfield_funct~~ions[32])(t~~ms34010_~~stat~~e tms~~, o~~ffs_t offs~~et, UINT~~32 ~~data)~~ =
	184	const tms340x0_device::wfield_func tms340x0_device::s_wfield_functions[32] =
185	185	{
186		wfield_32, wfield_01, wfield_02, wfield_03, wfield_04, wfield_05,
187		wfield_06, wfield_07, wfield_08, wfield_09, wfield_10, wfield_11,
188		wfield_12, wfield_13, wfield_14, wfield_15, wfield_16, wfield_17,
189		wfield_18, wfield_19, wfield_20, wfield_21, wfield_22, wfield_23,
190		wfield_24, wfield_25, wfield_26, wfield_27, wfield_28, wfield_29,
191		wfield_30, wfield_31
	186	&tms340x0_device::wfield_32, &tms340x0_device::wfield_01, &tms340x0_device::wfield_02, &tms340x0_device::wfield_03, &tms340x0_device::wfield_04, &tms340x0_device::wfield_05,
	187	&tms340x0_device::wfield_06, &tms340x0_device::wfield_07, &tms340x0_device::wfield_08, &tms340x0_device::wfield_09, &tms340x0_device::wfield_10, &tms340x0_device::wfield_11,
	188	&tms340x0_device::wfield_12, &tms340x0_device::wfield_13, &tms340x0_device::wfield_14, &tms340x0_device::wfield_15, &tms340x0_device::wfield_16, &tms340x0_device::wfield_17,
	189	&tms340x0_device::wfield_18, &tms340x0_device::wfield_19, &tms340x0_device::wfield_20, &tms340x0_device::wfield_21, &tms340x0_device::wfield_22, &tms340x0_device::wfield_23,
	190	&tms340x0_device::wfield_24, &tms340x0_device::wfield_25, &tms340x0_device::wfield_26, &tms340x0_device::wfield_27, &tms340x0_device::wfield_28, &tms340x0_device::wfield_29,
	191	&tms340x0_device::wfield_30, &tms340x0_device::wfield_31
192	192	};
193	193
194	194
r31176	r31177
197	197	FIELD READ FUNCTIONS (ZERO-EXTEND)
198	198	***************************************************************************/
199	199
200		~~static~~ UINT32 rfield_z_01(~~tms34010_state *tms,~~ offs_t offset)
	200	UINT32 tms340x0_device::rfield_z_01(offs_t offset)
201	201	{
202	202	UINT32 ret;
203		RFIELDMAC(~~tms,~~0x01,16);
	203	RFIELDMAC(0x01,16);
204	204	return ret;
205	205	}
206	206
207		~~static~~ UINT32 rfield_z_02(~~tms34010_state *tms,~~ offs_t offset)
	207	UINT32 tms340x0_device::rfield_z_02(offs_t offset)
208	208	{
209	209	UINT32 ret;
210		RFIELDMAC(~~tms,~~0x03,15);
	210	RFIELDMAC(0x03,15);
211	211	return ret;
212	212	}
213	213
214		~~static~~ UINT32 rfield_z_03(~~tms34010_state *tms,~~ offs_t offset)
	214	UINT32 tms340x0_device::rfield_z_03(offs_t offset)
215	215	{
216	216	UINT32 ret;
217		RFIELDMAC(~~tms,~~0x07,14);
	217	RFIELDMAC(0x07,14);
218	218	return ret;
219	219	}
220	220
221		~~static~~ UINT32 rfield_z_04(~~tms34010_state *tms,~~ offs_t offset)
	221	UINT32 tms340x0_device::rfield_z_04(offs_t offset)
222	222	{
223	223	UINT32 ret;
224		RFIELDMAC(~~tms,~~0x0f,13);
	224	RFIELDMAC(0x0f,13);
225	225	return ret;
226	226	}
227	227
228		~~static~~ UINT32 rfield_z_05(~~tms34010_state *tms,~~ offs_t offset)
	228	UINT32 tms340x0_device::rfield_z_05(offs_t offset)
229	229	{
230	230	UINT32 ret;
231		RFIELDMAC(~~tms,~~0x1f,12);
	231	RFIELDMAC(0x1f,12);
232	232	return ret;
233	233	}
234	234
235		~~static~~ UINT32 rfield_z_06(~~tms34010_state *tms,~~ offs_t offset)
	235	UINT32 tms340x0_device::rfield_z_06(offs_t offset)
236	236	{
237	237	UINT32 ret;
238		RFIELDMAC(~~tms,~~0x3f,11);
	238	RFIELDMAC(0x3f,11);
239	239	return ret;
240	240	}
241	241
242		~~static~~ UINT32 rfield_z_07(~~tms34010_state *tms,~~ offs_t offset)
	242	UINT32 tms340x0_device::rfield_z_07(offs_t offset)
243	243	{
244	244	UINT32 ret;
245		RFIELDMAC(~~tms,~~0x7f,10);
	245	RFIELDMAC(0x7f,10);
246	246	return ret;
247	247	}
248	248
249		~~static~~ UINT32 rfield_z_08(~~tms34010_state *tms,~~ offs_t offset)
	249	UINT32 tms340x0_device::rfield_z_08(offs_t offset)
250	250	{
251	251	UINT32 ret;
252		RFIELDMAC_8(~~tms~~);
	252	RFIELDMAC_8();
253	253	return ret;
254	254	}
255	255
256		~~static~~ UINT32 rfield_z_09(~~tms34010_state *tms,~~ offs_t offset)
	256	UINT32 tms340x0_device::rfield_z_09(offs_t offset)
257	257	{
258	258	UINT32 ret;
259		RFIELDMAC(~~tms,~~0x1ff,8);
	259	RFIELDMAC(0x1ff,8);
260	260	return ret;
261	261	}
262	262
263		~~static~~ UINT32 rfield_z_10(~~tms34010_state *tms,~~ offs_t offset)
	263	UINT32 tms340x0_device::rfield_z_10(offs_t offset)
264	264	{
265	265	UINT32 ret;
266		RFIELDMAC(~~tms,~~0x3ff,7);
	266	RFIELDMAC(0x3ff,7);
267	267	return ret;
268	268	}
269	269
270		~~static~~ UINT32 rfield_z_11(~~tms34010_state *tms,~~ offs_t offset)
	270	UINT32 tms340x0_device::rfield_z_11(offs_t offset)
271	271	{
272	272	UINT32 ret;
273		RFIELDMAC(~~tms,~~0x7ff,6);
	273	RFIELDMAC(0x7ff,6);
274	274	return ret;
275	275	}
276	276
277		~~static~~ UINT32 rfield_z_12(~~tms34010_state *tms,~~ offs_t offset)
	277	UINT32 tms340x0_device::rfield_z_12(offs_t offset)
278	278	{
279	279	UINT32 ret;
280		RFIELDMAC(~~tms,~~0xfff,5);
	280	RFIELDMAC(0xfff,5);
281	281	return ret;
282	282	}
283	283
284		~~static~~ UINT32 rfield_z_13(~~tms34010_state *tms,~~ offs_t offset)
	284	UINT32 tms340x0_device::rfield_z_13(offs_t offset)
285	285	{
286	286	UINT32 ret;
287		RFIELDMAC(~~tms,~~0x1fff,4);
	287	RFIELDMAC(0x1fff,4);
288	288	return ret;
289	289	}
290	290
291		~~static~~ UINT32 rfield_z_14(~~tms34010_state *tms,~~ offs_t offset)
	291	UINT32 tms340x0_device::rfield_z_14(offs_t offset)
292	292	{
293	293	UINT32 ret;
294		RFIELDMAC(~~tms,~~0x3fff,3);
	294	RFIELDMAC(0x3fff,3);
295	295	return ret;
296	296	}
297	297
298		~~static~~ UINT32 rfield_z_15(~~tms34010_state *tms,~~ offs_t offset)
	298	UINT32 tms340x0_device::rfield_z_15(offs_t offset)
299	299	{
300	300	UINT32 ret;
301		RFIELDMAC(~~tms,~~0x7fff,2);
	301	RFIELDMAC(0x7fff,2);
302	302	return ret;
303	303	}
304	304
305		~~static~~ UINT32 rfield_z_16(~~tms34010_state *tms,~~ offs_t offset)
	305	UINT32 tms340x0_device::rfield_z_16(offs_t offset)
306	306	{
307	307	UINT32 ret;
308	308	if (offset & 0x0f)
309	309	{
310		RFIELDMAC(~~tms,~~0xffff,1);
	310	RFIELDMAC(0xffff,1);
311	311	}
312	312
313	313	else
314		ret = TMS34010_RDMEM_WORD(~~tms,~~TOBYTE(offset));
	314	ret = TMS34010_RDMEM_WORD(TOBYTE(offset));
315	315	return ret;
316	316	}
317	317
318		~~static~~ UINT32 rfield_z_17(~~tms34010_state *tms,~~ offs_t offset)
	318	UINT32 tms340x0_device::rfield_z_17(offs_t offset)
319	319	{
320	320	UINT32 ret;
321		RFIELDMAC(~~tms,~~0x1ffff,0);
	321	RFIELDMAC(0x1ffff,0);
322	322	return ret;
323	323	}
324	324
325		~~static~~ UINT32 rfield_z_18(~~tms34010_state *tms,~~ offs_t offset)
	325	UINT32 tms340x0_device::rfield_z_18(offs_t offset)
326	326	{
327	327	UINT32 ret;
328		RFIELDMAC_BIG(~~tms,~~0x3ffff,15);
	328	RFIELDMAC_BIG(0x3ffff,15);
329	329	return ret;
330	330	}
331	331
332		~~static~~ UINT32 rfield_z_19(~~tms34010_state *tms,~~ offs_t offset)
	332	UINT32 tms340x0_device::rfield_z_19(offs_t offset)
333	333	{
334	334	UINT32 ret;
335		RFIELDMAC_BIG(~~tms,~~0x7ffff,14);
	335	RFIELDMAC_BIG(0x7ffff,14);
336	336	return ret;
337	337	}
338	338
339		~~static~~ UINT32 rfield_z_20(~~tms34010_state *tms,~~ offs_t offset)
	339	UINT32 tms340x0_device::rfield_z_20(offs_t offset)
340	340	{
341	341	UINT32 ret;
342		RFIELDMAC_BIG(~~tms,~~0xfffff,13);
	342	RFIELDMAC_BIG(0xfffff,13);
343	343	return ret;
344	344	}
345	345
346		~~static~~ UINT32 rfield_z_21(~~tms34010_state *tms,~~ offs_t offset)
	346	UINT32 tms340x0_device::rfield_z_21(offs_t offset)
347	347	{
348	348	UINT32 ret;
349		RFIELDMAC_BIG(~~tms,~~0x1fffff,12);
	349	RFIELDMAC_BIG(0x1fffff,12);
350	350	return ret;
351	351	}
352	352
353		~~static~~ UINT32 rfield_z_22(~~tms34010_state *tms,~~ offs_t offset)
	353	UINT32 tms340x0_device::rfield_z_22(offs_t offset)
354	354	{
355	355	UINT32 ret;
356		RFIELDMAC_BIG(~~tms,~~0x3fffff,11);
	356	RFIELDMAC_BIG(0x3fffff,11);
357	357	return ret;
358	358	}
359	359
360		~~static~~ UINT32 rfield_z_23(~~tms34010_state *tms,~~ offs_t offset)
	360	UINT32 tms340x0_device::rfield_z_23(offs_t offset)
361	361	{
362	362	UINT32 ret;
363		RFIELDMAC_BIG(~~tms,~~0x7fffff,10);
	363	RFIELDMAC_BIG(0x7fffff,10);
364	364	return ret;
365	365	}
366	366
367		~~static~~ UINT32 rfield_z_24(~~tms34010_state *tms,~~ offs_t offset)
	367	UINT32 tms340x0_device::rfield_z_24(offs_t offset)
368	368	{
369	369	UINT32 ret;
370		RFIELDMAC_BIG(~~tms,~~0xffffff,9);
	370	RFIELDMAC_BIG(0xffffff,9);
371	371	return ret;
372	372	}
373	373
374		~~static~~ UINT32 rfield_z_25(~~tms34010_state *tms,~~ offs_t offset)
	374	UINT32 tms340x0_device::rfield_z_25(offs_t offset)
375	375	{
376	376	UINT32 ret;
377		RFIELDMAC_BIG(~~tms,~~0x1ffffff,8);
	377	RFIELDMAC_BIG(0x1ffffff,8);
378	378	return ret;
379	379	}
380	380
381		~~static~~ UINT32 rfield_z_26(~~tms34010_state *tms,~~ offs_t offset)
	381	UINT32 tms340x0_device::rfield_z_26(offs_t offset)
382	382	{
383	383	UINT32 ret;
384		RFIELDMAC_BIG(~~tms,~~0x3ffffff,7);
	384	RFIELDMAC_BIG(0x3ffffff,7);
385	385	return ret;
386	386	}
387	387
388		~~static~~ UINT32 rfield_z_27(~~tms34010_state *tms,~~ offs_t offset)
	388	UINT32 tms340x0_device::rfield_z_27(offs_t offset)
389	389	{
390	390	UINT32 ret;
391		RFIELDMAC_BIG(~~tms,~~0x7ffffff,6);
	391	RFIELDMAC_BIG(0x7ffffff,6);
392	392	return ret;
393	393	}
394	394
395		~~static~~ UINT32 rfield_z_28(~~tms34010_state *tms,~~ offs_t offset)
	395	UINT32 tms340x0_device::rfield_z_28(offs_t offset)
396	396	{
397	397	UINT32 ret;
398		RFIELDMAC_BIG(~~tms,~~0xfffffff,5);
	398	RFIELDMAC_BIG(0xfffffff,5);
399	399	return ret;
400	400	}
401	401
402		~~static~~ UINT32 rfield_z_29(~~tms34010_state *tms,~~ offs_t offset)
	402	UINT32 tms340x0_device::rfield_z_29(offs_t offset)
403	403	{
404	404	UINT32 ret;
405		RFIELDMAC_BIG(~~tms,~~0x1fffffff,4);
	405	RFIELDMAC_BIG(0x1fffffff,4);
406	406	return ret;
407	407	}
408	408
409		~~static~~ UINT32 rfield_z_30(~~tms34010_state *tms,~~ offs_t offset)
	409	UINT32 tms340x0_device::rfield_z_30(offs_t offset)
410	410	{
411	411	UINT32 ret;
412		RFIELDMAC_BIG(~~tms,~~0x3fffffff,3);
	412	RFIELDMAC_BIG(0x3fffffff,3);
413	413	return ret;
414	414	}
415	415
416		~~static~~ UINT32 rfield_z_31(~~tms34010_state *tms,~~ offs_t offset)
	416	UINT32 tms340x0_device::rfield_z_31(offs_t offset)
417	417	{
418	418	UINT32 ret;
419		RFIELDMAC_BIG(~~tms,~~0x7fffffff,2);
	419	RFIELDMAC_BIG(0x7fffffff,2);
420	420	return ret;
421	421	}
422	422
423		~~static~~ UINT32 rfield_32(~~tms34010_state *tms,~~ offs_t offset)
	423	UINT32 tms340x0_device::rfield_32(offs_t offset)
424	424	{
425		RFIELDMAC_32(~~tms~~);
	425	RFIELDMAC_32();
426	426	}
427	427
428	428
r31176	r31177
430	430	FIELD READ FUNCTIONS (SIGN-EXTEND)
431	431	***************************************************************************/
432	432
433		~~static~~ UINT32 rfield_s_01(~~tms34010_state *tms,~~ offs_t offset)
	433	UINT32 tms340x0_device::rfield_s_01(offs_t offset)
434	434	{
435	435	UINT32 ret;
436		RFIELDMAC(~~tms,~~0x01,16);
	436	RFIELDMAC(0x01,16);
437	437	return ((INT32)(ret << 31)) >> 31;
438	438	}
439	439
440		~~static~~ UINT32 rfield_s_02(~~tms34010_state *tms,~~ offs_t offset)
	440	UINT32 tms340x0_device::rfield_s_02(offs_t offset)
441	441	{
442	442	UINT32 ret;
443		RFIELDMAC(~~tms,~~0x03,15);
	443	RFIELDMAC(0x03,15);
444	444	return ((INT32)(ret << 30)) >> 30;
445	445	}
446	446
447		~~static~~ UINT32 rfield_s_03(~~tms34010_state *tms,~~ offs_t offset)
	447	UINT32 tms340x0_device::rfield_s_03(offs_t offset)
448	448	{
449	449	UINT32 ret;
450		RFIELDMAC(~~tms,~~0x07,14);
	450	RFIELDMAC(0x07,14);
451	451	return ((INT32)(ret << 29)) >> 29;
452	452	}
453	453
454		~~static~~ UINT32 rfield_s_04(~~tms34010_state *tms,~~ offs_t offset)
	454	UINT32 tms340x0_device::rfield_s_04(offs_t offset)
455	455	{
456	456	UINT32 ret;
457		RFIELDMAC(~~tms,~~0x0f,13);
	457	RFIELDMAC(0x0f,13);
458	458	return ((INT32)(ret << 28)) >> 28;
459	459	}
460	460
461		~~static~~ UINT32 rfield_s_05(~~tms34010_state *tms,~~ offs_t offset)
	461	UINT32 tms340x0_device::rfield_s_05(offs_t offset)
462	462	{
463	463	UINT32 ret;
464		RFIELDMAC(~~tms,~~0x1f,12);
	464	RFIELDMAC(0x1f,12);
465	465	return ((INT32)(ret << 27)) >> 27;
466	466	}
467	467
468		~~static~~ UINT32 rfield_s_06(~~tms34010_state *tms,~~ offs_t offset)
	468	UINT32 tms340x0_device::rfield_s_06(offs_t offset)
469	469	{
470	470	UINT32 ret;
471		RFIELDMAC(~~tms,~~0x3f,11);
	471	RFIELDMAC(0x3f,11);
472	472	return ((INT32)(ret << 26)) >> 26;
473	473	}
474	474
475		~~static~~ UINT32 rfield_s_07(~~tms34010_state *tms,~~ offs_t offset)
	475	UINT32 tms340x0_device::rfield_s_07(offs_t offset)
476	476	{
477	477	UINT32 ret;
478		RFIELDMAC(~~tms,~~0x7f,10);
	478	RFIELDMAC(0x7f,10);
479	479	return ((INT32)(ret << 25)) >> 25;
480	480	}
481	481
482		~~static~~ UINT32 rfield_s_08(~~tms34010_state *tms,~~ offs_t offset)
	482	UINT32 tms340x0_device::rfield_s_08(offs_t offset)
483	483	{
484	484	UINT32 ret;
485	485	if (offset & 0x07)
486	486	{
487		RFIELDMAC(~~tms,~~0xff,9);
	487	RFIELDMAC(0xff,9);
488	488	}
489	489
490	490	else
491		ret = TMS34010_RDMEM(~~tms,~~TOBYTE(offset));
	491	ret = TMS34010_RDMEM(TOBYTE(offset));
492	492	return (INT32)(INT8)ret;
493	493	}
494	494
495		~~static~~ UINT32 rfield_s_09(~~tms34010_state *tms,~~ offs_t offset)
	495	UINT32 tms340x0_device::rfield_s_09(offs_t offset)
496	496	{
497	497	UINT32 ret;
498		RFIELDMAC(~~tms,~~0x1ff,8);
	498	RFIELDMAC(0x1ff,8);
499	499	return ((INT32)(ret << 23)) >> 23;
500	500	}
501	501
502		~~static~~ UINT32 rfield_s_10(~~tms34010_state *tms,~~ offs_t offset)
	502	UINT32 tms340x0_device::rfield_s_10(offs_t offset)
503	503	{
504	504	UINT32 ret;
505		RFIELDMAC(~~tms,~~0x3ff,7);
	505	RFIELDMAC(0x3ff,7);
506	506	return ((INT32)(ret << 22)) >> 22;
507	507	}
508	508
509		~~static~~ UINT32 rfield_s_11(~~tms34010_state *tms,~~ offs_t offset)
	509	UINT32 tms340x0_device::rfield_s_11(offs_t offset)
510	510	{
511	511	UINT32 ret;
512		RFIELDMAC(~~tms,~~0x7ff,6);
	512	RFIELDMAC(0x7ff,6);
513	513	return ((INT32)(ret << 21)) >> 21;
514	514	}
515	515
516		~~static~~ UINT32 rfield_s_12(~~tms34010_state *tms,~~ offs_t offset)
	516	UINT32 tms340x0_device::rfield_s_12(offs_t offset)
517	517	{
518	518	UINT32 ret;
519		RFIELDMAC(~~tms,~~0xfff,5);
	519	RFIELDMAC(0xfff,5);
520	520	return ((INT32)(ret << 20)) >> 20;
521	521	}
522	522
523		~~static~~ UINT32 rfield_s_13(~~tms34010_state *tms,~~ offs_t offset)
	523	UINT32 tms340x0_device::rfield_s_13(offs_t offset)
524	524	{
525	525	UINT32 ret;
526		RFIELDMAC(~~tms,~~0x1fff,4);
	526	RFIELDMAC(0x1fff,4);
527	527	return ((INT32)(ret << 19)) >> 19;
528	528	}
529	529
530		~~static~~ UINT32 rfield_s_14(~~tms34010_state *tms,~~ offs_t offset)
	530	UINT32 tms340x0_device::rfield_s_14(offs_t offset)
531	531	{
532	532	UINT32 ret;
533		RFIELDMAC(~~tms,~~0x3fff,3);
	533	RFIELDMAC(0x3fff,3);
534	534	return ((INT32)(ret << 18)) >> 18;
535	535	}
536	536
537		~~static~~ UINT32 rfield_s_15(~~tms34010_state *tms,~~ offs_t offset)
	537	UINT32 tms340x0_device::rfield_s_15(offs_t offset)
538	538	{
539	539	UINT32 ret;
540		RFIELDMAC(~~tms,~~0x7fff,2);
	540	RFIELDMAC(0x7fff,2);
541	541	return ((INT32)(ret << 17)) >> 17;
542	542	}
543	543
544		~~static~~ UINT32 rfield_s_16(~~tms34010_state *tms,~~ offs_t offset)
	544	UINT32 tms340x0_device::rfield_s_16(offs_t offset)
545	545	{
546	546	UINT32 ret;
547	547	if (offset & 0x0f)
548	548	{
549		RFIELDMAC(~~tms,~~0xffff,1);
	549	RFIELDMAC(0xffff,1);
550	550	}
551	551
552	552	else
553	553	{
554		ret = TMS34010_RDMEM_WORD(~~tms,~~TOBYTE(offset));
	554	ret = TMS34010_RDMEM_WORD(TOBYTE(offset));
555	555	}
556	556
557	557	return (INT32)(INT16)ret;
558	558	}
559	559
560		~~static~~ UINT32 rfield_s_17(~~tms34010_state *tms,~~ offs_t offset)
	560	UINT32 tms340x0_device::rfield_s_17(offs_t offset)
561	561	{
562	562	UINT32 ret;
563		RFIELDMAC(~~tms,~~0x1ffff,0);
	563	RFIELDMAC(0x1ffff,0);
564	564	return ((INT32)(ret << 15)) >> 15;
565	565	}
566	566
567		~~static~~ UINT32 rfield_s_18(~~tms34010_state *tms,~~ offs_t offset)
	567	UINT32 tms340x0_device::rfield_s_18(offs_t offset)
568	568	{
569	569	UINT32 ret;
570		RFIELDMAC_BIG(~~tms,~~0x3ffff,15);
	570	RFIELDMAC_BIG(0x3ffff,15);
571	571	return ((INT32)(ret << 14)) >> 14;
572	572	}
573	573
574		~~static~~ UINT32 rfield_s_19(~~tms34010_state *tms,~~ offs_t offset)
	574	UINT32 tms340x0_device::rfield_s_19(offs_t offset)
575	575	{
576	576	UINT32 ret;
577		RFIELDMAC_BIG(~~tms,~~0x7ffff,14);
	577	RFIELDMAC_BIG(0x7ffff,14);
578	578	return ((INT32)(ret << 13)) >> 13;
579	579	}
580	580
581		~~static~~ UINT32 rfield_s_20(~~tms34010_state *tms,~~ offs_t offset)
	581	UINT32 tms340x0_device::rfield_s_20(offs_t offset)
582	582	{
583	583	UINT32 ret;
584		RFIELDMAC_BIG(~~tms,~~0xfffff,13);
	584	RFIELDMAC_BIG(0xfffff,13);
585	585	return ((INT32)(ret << 12)) >> 12;
586	586	}
587	587
588		~~static~~ UINT32 rfield_s_21(~~tms34010_state *tms,~~ offs_t offset)
	588	UINT32 tms340x0_device::rfield_s_21(offs_t offset)
589	589	{
590	590	UINT32 ret;
591		RFIELDMAC_BIG(~~tms,~~0x1fffff,12);
	591	RFIELDMAC_BIG(0x1fffff,12);
592	592	return ((INT32)(ret << 11)) >> 11;
593	593	}
594	594
595		~~static~~ UINT32 rfield_s_22(~~tms34010_state *tms,~~ offs_t offset)
	595	UINT32 tms340x0_device::rfield_s_22(offs_t offset)
596	596	{
597	597	UINT32 ret;
598		RFIELDMAC_BIG(~~tms,~~0x3fffff,11);
	598	RFIELDMAC_BIG(0x3fffff,11);
599	599	return ((INT32)(ret << 10)) >> 10;
600	600	}
601	601
602		~~static~~ UINT32 rfield_s_23(~~tms34010_state *tms,~~ offs_t offset)
	602	UINT32 tms340x0_device::rfield_s_23(offs_t offset)
603	603	{
604	604	UINT32 ret;
605		RFIELDMAC_BIG(~~tms,~~0x7fffff,10);
	605	RFIELDMAC_BIG(0x7fffff,10);
606	606	return ((INT32)(ret << 9)) >> 9;
607	607	}
608	608
609		~~static~~ UINT32 rfield_s_24(~~tms34010_state *tms,~~ offs_t offset)
	609	UINT32 tms340x0_device::rfield_s_24(offs_t offset)
610	610	{
611	611	UINT32 ret;
612		RFIELDMAC_BIG(~~tms,~~0xffffff,9);
	612	RFIELDMAC_BIG(0xffffff,9);
613	613	return ((INT32)(ret << 8)) >> 8;
614	614	}
615	615
616		~~static~~ UINT32 rfield_s_25(~~tms34010_state *tms,~~ offs_t offset)
	616	UINT32 tms340x0_device::rfield_s_25(offs_t offset)
617	617	{
618	618	UINT32 ret;
619		RFIELDMAC_BIG(~~tms,~~0x1ffffff,8);
	619	RFIELDMAC_BIG(0x1ffffff,8);
620	620	return ((INT32)(ret << 7)) >> 7;
621	621	}
622	622
623		~~static~~ UINT32 rfield_s_26(~~tms34010_state *tms,~~ offs_t offset)
	623	UINT32 tms340x0_device::rfield_s_26(offs_t offset)
624	624	{
625	625	UINT32 ret;
626		RFIELDMAC_BIG(~~tms,~~0x3ffffff,7);
	626	RFIELDMAC_BIG(0x3ffffff,7);
627	627	return ((INT32)(ret << 6)) >> 6;
628	628	}
629	629
630		~~static~~ UINT32 rfield_s_27(~~tms34010_state *tms,~~ offs_t offset)
	630	UINT32 tms340x0_device::rfield_s_27(offs_t offset)
631	631	{
632	632	UINT32 ret;
633		RFIELDMAC_BIG(~~tms,~~0x7ffffff,6);
	633	RFIELDMAC_BIG(0x7ffffff,6);
634	634	return ((INT32)(ret << 5)) >> 5;
635	635	}
636	636
637		~~static~~ UINT32 rfield_s_28(~~tms34010_state *tms,~~ offs_t offset)
	637	UINT32 tms340x0_device::rfield_s_28(offs_t offset)
638	638	{
639	639	UINT32 ret;
640		RFIELDMAC_BIG(~~tms,~~0xfffffff,5);
	640	RFIELDMAC_BIG(0xfffffff,5);
641	641	return ((INT32)(ret << 4)) >> 4;
642	642	}
643	643
644		~~static~~ UINT32 rfield_s_29(~~tms34010_state *tms,~~ offs_t offset)
	644	UINT32 tms340x0_device::rfield_s_29(offs_t offset)
645	645	{
646	646	UINT32 ret;
647		RFIELDMAC_BIG(~~tms,~~0x1fffffff,4);
	647	RFIELDMAC_BIG(0x1fffffff,4);
648	648	return ((INT32)(ret << 3)) >> 3;
649	649	}
650	650
651		~~static~~ UINT32 rfield_s_30(~~tms34010_state *tms,~~ offs_t offset)
	651	UINT32 tms340x0_device::rfield_s_30(offs_t offset)
652	652	{
653	653	UINT32 ret;
654		RFIELDMAC_BIG(~~tms,~~0x3fffffff,3);
	654	RFIELDMAC_BIG(0x3fffffff,3);
655	655	return ((INT32)(ret << 2)) >> 2;
656	656	}
657	657
658		~~static~~ UINT32 rfield_s_31(~~tms34010_state *tms,~~ offs_t offset)
	658	UINT32 tms340x0_device::rfield_s_31(offs_t offset)
659	659	{
660	660	UINT32 ret;
661		RFIELDMAC_BIG(~~tms,~~0x7fffffff,2);
	661	RFIELDMAC_BIG(0x7fffffff,2);
662	662	return ((INT32)(ret << 1)) >> 1;
663	663	}
664	664
665		~~stati~~c ~~UINT32 (c~~onst tms34010_rfield_funct~~ions[64])(t~~ms34010_~~stat~~e tms~~, o~~ffs_t offs~~et)~~ =
	665	const tms340x0_device::rfield_func tms340x0_device::s_rfield_functions[64] =
666	666	{
667		rfield_32 , rfield_z_01, rfield_z_02, rfield_z_03, rfield_z_04, rfield_z_05,
668		rfield_z_06, rfield_z_07, rfield_z_08, rfield_z_09, rfield_z_10, rfield_z_11,
669		rfield_z_12, rfield_z_13, rfield_z_14, rfield_z_15, rfield_z_16, rfield_z_17,
670		rfield_z_18, rfield_z_19, rfield_z_20, rfield_z_21, rfield_z_22, rfield_z_23,
671		rfield_z_24, rfield_z_25, rfield_z_26, rfield_z_27, rfield_z_28, rfield_z_29,
672		rfield_z_30, rfield_z_31,
673		rfield_32 , rfield_s_01, rfield_s_02, rfield_s_03, rfield_s_04, rfield_s_05,
674		rfield_s_06, rfield_s_07, rfield_s_08, rfield_s_09, rfield_s_10, rfield_s_11,
675		rfield_s_12, rfield_s_13, rfield_s_14, rfield_s_15, rfield_s_16, rfield_s_17,
676		rfield_s_18, rfield_s_19, rfield_s_20, rfield_s_21, rfield_s_22, rfield_s_23,
677		rfield_s_24, rfield_s_25, rfield_s_26, rfield_s_27, rfield_s_28, rfield_s_29,
678		rfield_s_30, rfield_s_31
	667	&tms340x0_device::rfield_32 , &tms340x0_device::rfield_z_01, &tms340x0_device::rfield_z_02, &tms340x0_device::rfield_z_03, &tms340x0_device::rfield_z_04, &tms340x0_device::rfield_z_05,
	668	&tms340x0_device::rfield_z_06, &tms340x0_device::rfield_z_07, &tms340x0_device::rfield_z_08, &tms340x0_device::rfield_z_09, &tms340x0_device::rfield_z_10, &tms340x0_device::rfield_z_11,
	669	&tms340x0_device::rfield_z_12, &tms340x0_device::rfield_z_13, &tms340x0_device::rfield_z_14, &tms340x0_device::rfield_z_15, &tms340x0_device::rfield_z_16, &tms340x0_device::rfield_z_17,
	670	&tms340x0_device::rfield_z_18, &tms340x0_device::rfield_z_19, &tms340x0_device::rfield_z_20, &tms340x0_device::rfield_z_21, &tms340x0_device::rfield_z_22, &tms340x0_device::rfield_z_23,
	671	&tms340x0_device::rfield_z_24, &tms340x0_device::rfield_z_25, &tms340x0_device::rfield_z_26, &tms340x0_device::rfield_z_27, &tms340x0_device::rfield_z_28, &tms340x0_device::rfield_z_29,
	672	&tms340x0_device::rfield_z_30, &tms340x0_device::rfield_z_31,
	673	&tms340x0_device::rfield_32 , &tms340x0_device::rfield_s_01, &tms340x0_device::rfield_s_02, &tms340x0_device::rfield_s_03, &tms340x0_device::rfield_s_04, &tms340x0_device::rfield_s_05,
	674	&tms340x0_device::rfield_s_06, &tms340x0_device::rfield_s_07, &tms340x0_device::rfield_s_08, &tms340x0_device::rfield_s_09, &tms340x0_device::rfield_s_10, &tms340x0_device::rfield_s_11,
	675	&tms340x0_device::rfield_s_12, &tms340x0_device::rfield_s_13, &tms340x0_device::rfield_s_14, &tms340x0_device::rfield_s_15, &tms340x0_device::rfield_s_16, &tms340x0_device::rfield_s_17,
	676	&tms340x0_device::rfield_s_18, &tms340x0_device::rfield_s_19, &tms340x0_device::rfield_s_20, &tms340x0_device::rfield_s_21, &tms340x0_device::rfield_s_22, &tms340x0_device::rfield_s_23,
	677	&tms340x0_device::rfield_s_24, &tms340x0_device::rfield_s_25, &tms340x0_device::rfield_s_26, &tms340x0_device::rfield_s_27, &tms340x0_device::rfield_s_28, &tms340x0_device::rfield_s_29,
	678	&tms340x0_device::rfield_s_30, &tms340x0_device::rfield_s_31
679	679	};

trunk/src/emu/cpu/tms34010/34010ops.h
r31176	r31177
19	19	MEMORY I/O MACROS
20	20	***************************************************************************/
21	21
22		#define TMS34010_RDMEM(T,A) ((unsigned)(T)->program->read_byte (A))
23		#define TMS34010_RDMEM_WORD(T,A) ((unsigned)(T)->program->read_word (A))
24		INLINE UINT32 TMS34010_RDMEM_DWORD(tms34010_state *tms, offs_t A)
	22	#define TMS34010_RDMEM(A) ((unsigned)m_program->read_byte (A))
	23	#define TMS34010_RDMEM_WORD(A) ((unsigned)m_program->read_word (A))
	24	inline UINT32 tms340x0_device::TMS34010_RDMEM_DWORD(offs_t A)
25	25	{
26		UINT32 result = tms->program->read_word(A);
27		return result \| (tms->program->read_word(A+2)<<16);
	26	UINT32 result = m_program->read_word(A);
	27	return result \| (m_program->read_word(A+2)<<16);
28	28	}
29	29
30		#define TMS34010_WRMEM(T,A,V) ((T)->program->write_byte(A,V))
31		#define TMS34010_WRMEM_WORD(T,A,V) ((T)->program->write_word(A,V))
32		INLINE void TMS34010_WRMEM_DWORD(tms34010_state *tms, offs_t A,UINT32 V)
	30	#define TMS34010_WRMEM(A,V) (m_program->write_byte(A,V))
	31	#define TMS34010_WRMEM_WORD(A,V) (m_program->write_word(A,V))
	32	inline void tms340x0_device::TMS34010_WRMEM_DWORD(offs_t A, UINT32 V)
33	33	{
34		tms->program->write_word(A,V);
35		tms->program->write_word(A+2,V>>16);
	34	m_program->write_word(A,V);
	35	m_program->write_word(A+2,V>>16);
36	36	}
37	37
38	38
39	39
40	40	/* IO registers accessor */
41		#define IOREG(T,reg) ((T)->IOregs[reg])
42		#define SMART_IOREG(T,reg) ((T)->IOregs[(T)->is_34020 ? (int)REG020_##reg : (int)REG_##reg])
43		#define PBH(T) (IOREG(T, REG_CONTROL) & 0x0100)
44		#define PBV(T) (IOREG(T, REG_CONTROL) & 0x0200)
	41	#define IOREG(reg) (m_IOregs[reg])
	42	#define SMART_IOREG(reg) (m_IOregs[m_is_34020 ? (int)REG020_##reg : (int)REG_##reg])
	43	#define PBH() (IOREG(REG_CONTROL) & 0x0100)
	44	#define PBV() (IOREG(REG_CONTROL) & 0x0200)
45	45
46	46
47	47
r31176	r31177
49	49	FIELD WRITE MACROS
50	50	***************************************************************************/
51	51
52		#define WFIELDMAC(T,MASK,MAX) \
	52	#define WFIELDMAC(MASK,MAX) \
53	53	UINT32 shift = offset & 0x0f; \
54	54	UINT32 masked_data = data & (MASK); \
55	55	UINT32 old; \
r31176	r31177
58	58	\
59	59	if (shift >= MAX) \
60	60	{ \
61		old = (UINT32)TMS34010_RDMEM_DWORD(T, offset) & ~((MASK) << shift); \
62		TMS34010_WRMEM_DWORD(T, offset, (masked_data << shift) \| old); \
	61	old = (UINT32)TMS34010_RDMEM_DWORD(offset) & ~((MASK) << shift); \
	62	TMS34010_WRMEM_DWORD(offset, (masked_data << shift) \| old); \
63	63	} \
64	64	else \
65	65	{ \
66		old = (UINT32)TMS34010_RDMEM_WORD(T, offset) & ~((MASK) << shift); \
67		TMS34010_WRMEM_WORD(T, offset, ((masked_data & (MASK)) << shift) \| old); \
	66	old = (UINT32)TMS34010_RDMEM_WORD(offset) & ~((MASK) << shift); \
	67	TMS34010_WRMEM_WORD(offset, ((masked_data & (MASK)) << shift) \| old); \
68	68	}
69		#define WFIELDMAC_BIG(T,MASK,MAX) \
	69
	70	#define WFIELDMAC_BIG(MASK,MAX) \
70	71	UINT32 shift = offset & 0x0f; \
71	72	UINT32 masked_data = data & (MASK); \
72	73	UINT32 old; \
73	74	\
74	75	offset = TOBYTE(offset & 0xfffffff0); \
75	76	\
76		old = (UINT32)TMS34010_RDMEM_DWORD(T, offset) & ~(UINT32)((MASK) << shift); \
77		TMS34010_WRMEM_DWORD(T, offset, (UINT32)(masked_data << shift) \| old); \
	77	old = (UINT32)TMS34010_RDMEM_DWORD(offset) & ~(UINT32)((MASK) << shift); \
	78	TMS34010_WRMEM_DWORD(offset, (UINT32)(masked_data << shift) \| old); \
78	79	if (shift >= MAX) \
79	80	{ \
80	81	shift = 32 - shift; \
81		old = (UINT32)TMS34010_RDMEM_WORD(T, offset + 4) & ~((MASK) >> shift); \
82		TMS34010_WRMEM_WORD(T, offset, (masked_data >> shift) \| old); \
	82	old = (UINT32)TMS34010_RDMEM_WORD(offset + 4) & ~((MASK) >> shift); \
	83	TMS34010_WRMEM_WORD(offset, (masked_data >> shift) \| old); \
83	84	}
84		#define WFIELDMAC_8(T) \
	85
	86	#define WFIELDMAC_8() \
85	87	if (offset & 0x07) \
86	88	{ \
87		WFIELDMAC(T,0xff,9); \
	89	WFIELDMAC(0xff,9); \
88	90	} \
89	91	else \
90		TMS34010_WRMEM(T, TOBYTE(offset), data);
91		#define RFIELDMAC_8(T) \
	92	TMS34010_WRMEM(TOBYTE(offset), data);
	93
	94	#define RFIELDMAC_8() \
92	95	if (offset & 0x07) \
93	96	{ \
94		RFIELDMAC(T,0xff,9); \
	97	RFIELDMAC(0xff,9); \
95	98	} \
96	99	else \
97		return TMS34010_RDMEM(T, TOBYTE(offset));
98		#define WFIELDMAC_32(T) \
	100	return TMS34010_RDMEM(TOBYTE(offset));
	101
	102	#define WFIELDMAC_32() \
99	103	if (offset & 0x0f) \
100	104	{ \
101	105	UINT32 shift = offset&0x0f; \
102	106	UINT32 old; \
103	107	UINT32 hiword; \
104	108	offset &= 0xfffffff0; \
105		old = ((UINT32) TMS34010_RDMEM_DWORD (T, TOBYTE(offset ))&(0xffffffff>>(0x20-shift))); \
106		hiword = ((UINT32) TMS34010_RDMEM_DWORD (T, TOBYTE(offset+0x20))&(0xffffffff<<shift)); \
107		TMS34010_WRMEM_DWORD(T, TOBYTE(offset ),(data<< shift) \|old); \
108		TMS34010_WRMEM_DWORD(T, TOBYTE(offset+0x20),(data>>(0x20-shift))\|hiword); \
	109	old = ((UINT32) TMS34010_RDMEM_DWORD (TOBYTE(offset ))&(0xffffffff>>(0x20-shift))); \
	110	hiword = ((UINT32) TMS34010_RDMEM_DWORD (TOBYTE(offset+0x20))&(0xffffffff<<shift)); \
	111	TMS34010_WRMEM_DWORD(TOBYTE(offset ),(data<< shift) \|old); \
	112	TMS34010_WRMEM_DWORD(TOBYTE(offset+0x20),(data>>(0x20-shift))\|hiword); \
109	113	} \
110	114	else \
111		TMS34010_WRMEM_DWORD(T~~, T~~OBYTE(offset),data);
	115	TMS34010_WRMEM_DWORD(TOBYTE(offset),data);
112	116
113	117
114	118	/***************************************************************************
115	119	FIELD READ MACROS
116	120	***************************************************************************/
117	121
118		#define RFIELDMAC(T,MASK,MAX) \
	122	#define RFIELDMAC(MASK,MAX) \
119	123	UINT32 shift = offset & 0x0f; \
120	124	offset = TOBYTE(offset & 0xfffffff0); \
121	125	\
122	126	if (shift >= MAX) \
123		ret = (TMS34010_RDMEM_DWORD(T, offset) >> shift) & (MASK); \
	127	ret = (TMS34010_RDMEM_DWORD(offset) >> shift) & (MASK); \
124	128	else \
125		ret = (TMS34010_RDMEM_WORD(T, offset) >> shift) & (MASK);
126		#define RFIELDMAC_BIG(T,MASK,MAX) \
	129	ret = (TMS34010_RDMEM_WORD(offset) >> shift) & (MASK);
	130
	131	#define RFIELDMAC_BIG(MASK,MAX) \
127	132	UINT32 shift = offset & 0x0f; \
128	133	offset = TOBYTE(offset & 0xfffffff0); \
129	134	\
130		ret = (UINT32)TMS34010_RDMEM_DWORD(T, offset) >> shift; \
	135	ret = (UINT32)TMS34010_RDMEM_DWORD(offset) >> shift; \
131	136	if (shift >= MAX) \
132		ret \|= (TMS34010_RDMEM_WORD(T, offset + 4) << (32 - shift)); \
	137	ret \|= (TMS34010_RDMEM_WORD(offset + 4) << (32 - shift)); \
133	138	ret &= MASK;
134		#define RFIELDMAC_32(T) \
	139
	140	#define RFIELDMAC_32() \
135	141	if (offset&0x0f) \
136	142	{ \
137	143	UINT32 shift = offset&0x0f; \
138	144	offset &= 0xfffffff0; \
139		return (((UINT32)TMS34010_RDMEM_DWORD (T, TOBYTE(offset ))>> shift) \| \
140		(TMS34010_RDMEM_DWORD (T, TOBYTE(offset+0x20))<<(0x20-shift)));\
	145	return (((UINT32)TMS34010_RDMEM_DWORD (TOBYTE(offset ))>> shift) \| \
	146	(TMS34010_RDMEM_DWORD (TOBYTE(offset+0x20))<<(0x20-shift)));\
141	147	} \
142	148	else \
143		return TMS34010_RDMEM_DWORD(T~~, T~~OBYTE(offset));
	149	return TMS34010_RDMEM_DWORD(TOBYTE(offset));
144	150
145	151
146	152	#endif /* __34010OPS_H__ */

trunk/src/emu/cpu/tms34010/tms34010.h
r31176	r31177
188	188	};
189	189
190	190
191		struct tms34010_config
	191	struct tms340x0_config
192	192	{
193	193	UINT8 halt_on_reset; /* /HCS pin, which determines HALT state after reset */
194	194	const char screen_tag; / the screen operated on */
r31176	r31177
202	202	};
203	203
204	204
205		/* PUBLIC FUNCTIONS - 34010 */
206		void tms34010_get_display_params(device_t cpu, tms34010_display_params params);
	205	#define MCFG_TMS340X0_CONFIG(_config) \
	206	tms340x0_device::set_tms340x0_config(*device, &_config);
207	207
208		class tms34010_device : public legacy_cpu_device
	208
	209	class tms340x0_device : public cpu_device
209	210	{
210	211	public:
211		tms34010_device(const machine_config &mconfig, device_type type, const char tag, device_t owner, UINT32 clock);
212		tms34010_device(const machine_config &mconfig, device_type type, const char tag, device_t owner, UINT32 clock, cpu_get_info_func get_info);
	212	// construction/destruction
	213	tms340x0_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname);
213	214
	215	static void set_tms340x0_config(device_t &device, const tms340x0_config *config) { downcast<tms340x0_device &>(device).m_config = config; }
	216
	217	void get_display_params(tms34010_display_params *params);
	218	void tms34010_state_postload();
	219
214	220	UINT32 tms340x0_ind16(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
215	221	UINT32 tms340x0_rgb32(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
216		/* Reads & writes to the 34010 I/O registers; place at 0xc0000000 */
217		DECLARE_WRITE16_MEMBER( io_register_w );
218		DECLARE_READ16_MEMBER( io_register_r );
219	222
	223	virtual DECLARE_WRITE16_MEMBER(io_register_w) = 0;
	224	virtual DECLARE_READ16_MEMBER(io_register_r) = 0;
	225
220	226	DECLARE_WRITE16_MEMBER(host_w);
221	227	DECLARE_READ16_MEMBER(host_r);
	228
	229	TIMER_CALLBACK_MEMBER(internal_interrupt_callback);
	230	TIMER_CALLBACK_MEMBER(scanline_callback);
	231
	232	protected:
	233	// device-level overrides
	234	virtual void device_start();
	235	virtual void device_reset();
	236
	237	// device_execute_interface overrides
	238	virtual UINT32 execute_min_cycles() const { return 1; }
	239	virtual UINT32 execute_max_cycles() const { return 10000; }
	240	virtual UINT32 execute_input_lines() const { return 2; }
	241	virtual void execute_run();
	242	virtual void execute_set_input(int inputnum, int state);
	243
	244	// device_memory_interface overrides
	245	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
	246
	247	// device_state_interface overrides
	248	virtual void state_string_export(const device_state_entry &entry, astring &string);
	249
	250	// device_disasm_interface overrides
	251	virtual UINT32 disasm_min_opcode_bytes() const { return 2; }
	252	virtual UINT32 disasm_max_opcode_bytes() const { return 10; }
	253
	254	typedef void (tms340x0_device::*pixel_write_func)(offs_t offset, UINT32 data);
	255	typedef UINT32 (tms340x0_device::*pixel_read_func)(offs_t offset);
	256	typedef UINT32 (tms340x0_device::*raster_op_func)(UINT32 newpix, UINT32 oldpix);
	257	typedef void (tms340x0_device::*wfield_func)(offs_t offset, UINT32 data);
	258	typedef UINT32 (tms340x0_device::*rfield_func)(offs_t offset);
	259	typedef void (tms340x0_device::*opcode_func)(UINT16 op);
	260	typedef UINT32 (tms340x0_device::*pixel_op_func)(UINT32, UINT32, UINT32);
	261	typedef void (tms340x0_device::*pixblt_op_func)(int, int);
	262	typedef void (tms340x0_device::*pixblt_b_op_func)(int);
	263	typedef void (tms340x0_device::*word_write_func)(address_space &space, offs_t offset,UINT16 data);
	264	typedef UINT16 (tms340x0_device::*word_read_func)(address_space &space, offs_t offset);
	265
	266	static const wfield_func s_wfield_functions[32];
	267	static const rfield_func s_rfield_functions[64];
	268	static const opcode_func s_opcode_table[65536 >> 4];
	269	static const pixel_op_func s_pixel_op_table[32];
	270	static const UINT8 s_pixel_op_timing_table[33];
	271	static const pixblt_op_func s_pixblt_op_table[];
	272	static const pixblt_op_func s_pixblt_r_op_table[];
	273	static const pixblt_b_op_func s_pixblt_b_op_table[];
	274	static const pixblt_b_op_func s_fill_op_table[];
	275	static const pixel_write_func s_pixel_write_ops[4][6];
	276	static const pixel_read_func s_pixel_read_ops[6];
	277	static const raster_op_func s_raster_ops[32];
	278
	279	address_space_config m_program_config;
	280
	281	UINT32 m_pc;
	282	UINT32 m_ppc;
	283	UINT32 m_st;
	284	pixel_write_func m_pixel_write;
	285	pixel_read_func m_pixel_read;
	286	raster_op_func m_raster_op;
	287	pixel_op_func m_pixel_op;
	288	UINT32 m_pixel_op_timing;
	289	UINT32 m_convsp;
	290	UINT32 m_convdp;
	291	UINT32 m_convmp;
	292	INT32 m_gfxcycles;
	293	UINT8 m_pixelshift;
	294	UINT8 m_is_34020;
	295	UINT8 m_reset_deferred;
	296	UINT8 m_hblank_stable;
	297	UINT8 m_external_host_access;
	298	UINT8 m_executing;
	299	address_space *m_program;
	300	direct_read_data *m_direct;
	301	const tms340x0_config *m_config;
	302	screen_device *m_screen;
	303	emu_timer *m_scantimer;
	304	int m_icount;
	305
	306	struct XY
	307	{
	308	#ifdef LSB_FIRST
	309	INT16 x;
	310	INT16 y;
	311	#else
	312	INT16 y;
	313	INT16 x;
	314	#endif
	315	};
	316
	317	/* A registers 0-15 map to regs[0]-regs[15] */
	318	/* B registers 0-15 map to regs[30]-regs[15] */
	319	union
	320	{
	321	INT32 reg;
	322	XY xy;
	323	} m_regs[31];
	324
	325	UINT16 m_IOregs[64];
	326	UINT16 m_shiftreg[(8 * 512 * sizeof(UINT16))/2];
	327
	328	UINT32 TMS34010_RDMEM_DWORD(offs_t A);
	329	void TMS34010_WRMEM_DWORD(offs_t A, UINT32 V);
	330	void SET_ST(UINT32 st);
	331	void RESET_ST();
	332	UINT32 ROPCODE();
	333	INT16 PARAM_WORD();
	334	INT32 PARAM_LONG();
	335	INT16 PARAM_WORD_NO_INC();
	336	INT32 PARAM_LONG_NO_INC();
	337	UINT32 RBYTE(offs_t offset);
	338	void WBYTE(offs_t offset, UINT32 data);
	339	UINT32 RLONG(offs_t offset);
	340	void WLONG(offs_t offset, UINT32 data);
	341	void PUSH(UINT32 data);
	342	INT32 POP();
	343	UINT32 read_pixel_1(offs_t offset);
	344	UINT32 read_pixel_2(offs_t offset);
	345	UINT32 read_pixel_4(offs_t offset);
	346	UINT32 read_pixel_8(offs_t offset);
	347	UINT32 read_pixel_16(offs_t offset);
	348	UINT32 read_pixel_32(offs_t offset);
	349	UINT32 read_pixel_shiftreg(offs_t offset);
	350	void write_pixel_1(offs_t offset, UINT32 data);
	351	void write_pixel_2(offs_t offset, UINT32 data);
	352	void write_pixel_4(offs_t offset, UINT32 data);
	353	void write_pixel_8(offs_t offset, UINT32 data);
	354	void write_pixel_16(offs_t offset, UINT32 data);
	355	void write_pixel_32(offs_t offset, UINT32 data);
	356	void write_pixel_t_1(offs_t offset, UINT32 data);
	357	void write_pixel_t_2(offs_t offset, UINT32 data);
	358	void write_pixel_t_4(offs_t offset, UINT32 data);
	359	void write_pixel_t_8(offs_t offset, UINT32 data);
	360	void write_pixel_t_16(offs_t offset, UINT32 data);
	361	void write_pixel_t_32(offs_t offset, UINT32 data);
	362	void write_pixel_r_1(offs_t offset, UINT32 data);
	363	void write_pixel_r_2(offs_t offset, UINT32 data);
	364	void write_pixel_r_4(offs_t offset, UINT32 data);
	365	void write_pixel_r_8(offs_t offset, UINT32 data);
	366	void write_pixel_r_16(offs_t offset, UINT32 data);
	367	void write_pixel_r_32(offs_t offset, UINT32 data);
	368	void write_pixel_r_t_1(offs_t offset, UINT32 data);
	369	void write_pixel_r_t_2(offs_t offset, UINT32 data);
	370	void write_pixel_r_t_4(offs_t offset, UINT32 data);
	371	void write_pixel_r_t_8(offs_t offset, UINT32 data);
	372	void write_pixel_r_t_16(offs_t offset, UINT32 data);
	373	void write_pixel_r_t_32(offs_t offset, UINT32 data);
	374	void write_pixel_shiftreg(offs_t offset, UINT32 data);
	375	UINT32 raster_op_1(UINT32 newpix, UINT32 oldpix);
	376	UINT32 raster_op_2(UINT32 newpix, UINT32 oldpix);
	377	UINT32 raster_op_3(UINT32 newpix, UINT32 oldpix);
	378	UINT32 raster_op_4(UINT32 newpix, UINT32 oldpix);
	379	UINT32 raster_op_5(UINT32 newpix, UINT32 oldpix);
	380	UINT32 raster_op_6(UINT32 newpix, UINT32 oldpix);
	381	UINT32 raster_op_7(UINT32 newpix, UINT32 oldpix);
	382	UINT32 raster_op_8(UINT32 newpix, UINT32 oldpix);
	383	UINT32 raster_op_9(UINT32 newpix, UINT32 oldpix);
	384	UINT32 raster_op_10(UINT32 newpix, UINT32 oldpix);
	385	UINT32 raster_op_11(UINT32 newpix, UINT32 oldpix);
	386	UINT32 raster_op_12(UINT32 newpix, UINT32 oldpix);
	387	UINT32 raster_op_13(UINT32 newpix, UINT32 oldpix);
	388	UINT32 raster_op_14(UINT32 newpix, UINT32 oldpix);
	389	UINT32 raster_op_15(UINT32 newpix, UINT32 oldpix);
	390	UINT32 raster_op_16(UINT32 newpix, UINT32 oldpix);
	391	UINT32 raster_op_17(UINT32 newpix, UINT32 oldpix);
	392	UINT32 raster_op_18(UINT32 newpix, UINT32 oldpix);
	393	UINT32 raster_op_19(UINT32 newpix, UINT32 oldpix);
	394	UINT32 raster_op_20(UINT32 newpix, UINT32 oldpix);
	395	UINT32 raster_op_21(UINT32 newpix, UINT32 oldpix);
	396	void wfield_01(offs_t offset, UINT32 data);
	397	void wfield_02(offs_t offset, UINT32 data);
	398	void wfield_03(offs_t offset, UINT32 data);
	399	void wfield_04(offs_t offset, UINT32 data);
	400	void wfield_05(offs_t offset, UINT32 data);
	401	void wfield_06(offs_t offset, UINT32 data);
	402	void wfield_07(offs_t offset, UINT32 data);
	403	void wfield_08(offs_t offset, UINT32 data);
	404	void wfield_09(offs_t offset, UINT32 data);
	405	void wfield_10(offs_t offset, UINT32 data);
	406	void wfield_11(offs_t offset, UINT32 data);
	407	void wfield_12(offs_t offset, UINT32 data);
	408	void wfield_13(offs_t offset, UINT32 data);
	409	void wfield_14(offs_t offset, UINT32 data);
	410	void wfield_15(offs_t offset, UINT32 data);
	411	void wfield_16(offs_t offset, UINT32 data);
	412	void wfield_17(offs_t offset, UINT32 data);
	413	void wfield_18(offs_t offset, UINT32 data);
	414	void wfield_19(offs_t offset, UINT32 data);
	415	void wfield_20(offs_t offset, UINT32 data);
	416	void wfield_21(offs_t offset, UINT32 data);
	417	void wfield_22(offs_t offset, UINT32 data);
	418	void wfield_23(offs_t offset, UINT32 data);
	419	void wfield_24(offs_t offset, UINT32 data);
	420	void wfield_25(offs_t offset, UINT32 data);
	421	void wfield_26(offs_t offset, UINT32 data);
	422	void wfield_27(offs_t offset, UINT32 data);
	423	void wfield_28(offs_t offset, UINT32 data);
	424	void wfield_29(offs_t offset, UINT32 data);
	425	void wfield_30(offs_t offset, UINT32 data);
	426	void wfield_31(offs_t offset, UINT32 data);
	427	void wfield_32(offs_t offset, UINT32 data);
	428	UINT32 rfield_z_01(offs_t offset);
	429	UINT32 rfield_z_02(offs_t offset);
	430	UINT32 rfield_z_03(offs_t offset);
	431	UINT32 rfield_z_04(offs_t offset);
	432	UINT32 rfield_z_05(offs_t offset);
	433	UINT32 rfield_z_06(offs_t offset);
	434	UINT32 rfield_z_07(offs_t offset);
	435	UINT32 rfield_z_08(offs_t offset);
	436	UINT32 rfield_z_09(offs_t offset);
	437	UINT32 rfield_z_10(offs_t offset);
	438	UINT32 rfield_z_11(offs_t offset);
	439	UINT32 rfield_z_12(offs_t offset);
	440	UINT32 rfield_z_13(offs_t offset);
	441	UINT32 rfield_z_14(offs_t offset);
	442	UINT32 rfield_z_15(offs_t offset);
	443	UINT32 rfield_z_16(offs_t offset);
	444	UINT32 rfield_z_17(offs_t offset);
	445	UINT32 rfield_z_18(offs_t offset);
	446	UINT32 rfield_z_19(offs_t offset);
	447	UINT32 rfield_z_20(offs_t offset);
	448	UINT32 rfield_z_21(offs_t offset);
	449	UINT32 rfield_z_22(offs_t offset);
	450	UINT32 rfield_z_23(offs_t offset);
	451	UINT32 rfield_z_24(offs_t offset);
	452	UINT32 rfield_z_25(offs_t offset);
	453	UINT32 rfield_z_26(offs_t offset);
	454	UINT32 rfield_z_27(offs_t offset);
	455	UINT32 rfield_z_28(offs_t offset);
	456	UINT32 rfield_z_29(offs_t offset);
	457	UINT32 rfield_z_30(offs_t offset);
	458	UINT32 rfield_z_31(offs_t offset);
	459	UINT32 rfield_32(offs_t offset);
	460	UINT32 rfield_s_01(offs_t offset);
	461	UINT32 rfield_s_02(offs_t offset);
	462	UINT32 rfield_s_03(offs_t offset);
	463	UINT32 rfield_s_04(offs_t offset);
	464	UINT32 rfield_s_05(offs_t offset);
	465	UINT32 rfield_s_06(offs_t offset);
	466	UINT32 rfield_s_07(offs_t offset);
	467	UINT32 rfield_s_08(offs_t offset);
	468	UINT32 rfield_s_09(offs_t offset);
	469	UINT32 rfield_s_10(offs_t offset);
	470	UINT32 rfield_s_11(offs_t offset);
	471	UINT32 rfield_s_12(offs_t offset);
	472	UINT32 rfield_s_13(offs_t offset);
	473	UINT32 rfield_s_14(offs_t offset);
	474	UINT32 rfield_s_15(offs_t offset);
	475	UINT32 rfield_s_16(offs_t offset);
	476	UINT32 rfield_s_17(offs_t offset);
	477	UINT32 rfield_s_18(offs_t offset);
	478	UINT32 rfield_s_19(offs_t offset);
	479	UINT32 rfield_s_20(offs_t offset);
	480	UINT32 rfield_s_21(offs_t offset);
	481	UINT32 rfield_s_22(offs_t offset);
	482	UINT32 rfield_s_23(offs_t offset);
	483	UINT32 rfield_s_24(offs_t offset);
	484	UINT32 rfield_s_25(offs_t offset);
	485	UINT32 rfield_s_26(offs_t offset);
	486	UINT32 rfield_s_27(offs_t offset);
	487	UINT32 rfield_s_28(offs_t offset);
	488	UINT32 rfield_s_29(offs_t offset);
	489	UINT32 rfield_s_30(offs_t offset);
	490	UINT32 rfield_s_31(offs_t offset);
	491	void unimpl(UINT16 op);
	492	void pixblt_l_l(UINT16 op); /* 0f00 */
	493	void pixblt_l_xy(UINT16 op); /* 0f20 */
	494	void pixblt_xy_l(UINT16 op); /* 0f40 */
	495	void pixblt_xy_xy(UINT16 op); /* 0f60 */
	496	void pixblt_b_l(UINT16 op); /* 0f80 */
	497	void pixblt_b_xy(UINT16 op); /* 0fa0 */
	498	void fill_l(UINT16 op); /* 0fc0 */
	499	void fill_xy(UINT16 op); /* 0fe0 */
	500	void line(UINT16 op); /* df10/df90 */
	501	void add_xy_a(UINT16 op); /* e000/e100 */
	502	void add_xy_b(UINT16 op); /* e000/e100 */
	503	void sub_xy_a(UINT16 op); /* e200/e300 */
	504	void sub_xy_b(UINT16 op); /* e200/e300 */
	505	void cmp_xy_a(UINT16 op); /* e400/e500 */
	506	void cmp_xy_b(UINT16 op); /* e400/e500 */
	507	void cpw_a(UINT16 op); /* e600/e700 */
	508	void cpw_b(UINT16 op); /* e600/e700 */
	509	void cvxyl_a(UINT16 op); /* e800/e900 */
	510	void cvxyl_b(UINT16 op); /* e800/e900 */
	511	void movx_a(UINT16 op); /* ec00/ed00 */
	512	void movx_b(UINT16 op); /* ec00/ed00 */
	513	void movy_a(UINT16 op); /* ee00/ef00 */
	514	void movy_b(UINT16 op); /* ee00/ef00 */
	515	void pixt_ri_a(UINT16 op); /* f800/f900 */
	516	void pixt_ri_b(UINT16 op); /* f800/f900 */
	517	void pixt_rixy_a(UINT16 op); /* f000/f100 */
	518	void pixt_rixy_b(UINT16 op); /* f000/f100 */
	519	void pixt_ir_a(UINT16 op); /* fa00/fb00 */
	520	void pixt_ir_b(UINT16 op); /* fa00/fb00 */
	521	void pixt_ii_a(UINT16 op); /* fc00/fd00 */
	522	void pixt_ii_b(UINT16 op); /* fc00/fd00 */
	523	void pixt_ixyr_a(UINT16 op); /* f200/f300 */
	524	void pixt_ixyr_b(UINT16 op); /* f200/f300 */
	525	void pixt_ixyixy_a(UINT16 op); /* f400/f500 */
	526	void pixt_ixyixy_b(UINT16 op); /* f400/f500 */
	527	void drav_a(UINT16 op); /* f600/f700 */
	528	void drav_b(UINT16 op); /* f600/f700 */
	529	void abs_a(UINT16 op); /* 0380 */
	530	void abs_b(UINT16 op); /* 0390 */
	531	void add_a(UINT16 op); /* 4000/4100 */
	532	void add_b(UINT16 op); /* 4000/4100 */
	533	void addc_a(UINT16 op); /* 4200/4200 */
	534	void addc_b(UINT16 op); /* 4200/4200 */
	535	void addi_w_a(UINT16 op); /* 0b00 */
	536	void addi_w_b(UINT16 op); /* 0b10 */
	537	void addi_l_a(UINT16 op); /* 0b20 */
	538	void addi_l_b(UINT16 op); /* 0b30 */
	539	void addk_a(UINT16 op); /* 1000-1300 */
	540	void addk_b(UINT16 op); /* 1000-1300 */
	541	void and_a(UINT16 op); /* 5000/5100 */
	542	void and_b(UINT16 op); /* 5000/5100 */
	543	void andi_a(UINT16 op); /* 0b80 */
	544	void andi_b(UINT16 op); /* 0b90 */
	545	void andn_a(UINT16 op); /* 5200-5300 */
	546	void andn_b(UINT16 op); /* 5200-5300 */
	547	void btst_k_a(UINT16 op); /* 1c00-1f00 */
	548	void btst_k_b(UINT16 op); /* 1c00-1f00 */
	549	void btst_r_a(UINT16 op); /* 4a00-4b00 */
	550	void btst_r_b(UINT16 op); /* 4a00-4b00 */
	551	void clrc(UINT16 op); /* 0320 */
	552	void cmp_a(UINT16 op); /* 4800/4900 */
	553	void cmp_b(UINT16 op); /* 4800/4900 */
	554	void cmpi_w_a(UINT16 op); /* 0b40 */
	555	void cmpi_w_b(UINT16 op); /* 0b50 */
	556	void cmpi_l_a(UINT16 op); /* 0b60 */
	557	void cmpi_l_b(UINT16 op); /* 0b70 */
	558	void dint(UINT16 op);
	559	void divs_a(UINT16 op); /* 5800/5900 */
	560	void divs_b(UINT16 op); /* 5800/5900 */
	561	void divu_a(UINT16 op); /* 5a00/5b00 */
	562	void divu_b(UINT16 op); /* 5a00/5b00 */
	563	void eint(UINT16 op);
	564	void exgf0_a(UINT16 op); /* d500 */
	565	void exgf0_b(UINT16 op); /* d510 */
	566	void exgf1_a(UINT16 op); /* d700 */
	567	void exgf1_b(UINT16 op); /* d710 */
	568	void lmo_a(UINT16 op); /* 6a00/6b00 */
	569	void lmo_b(UINT16 op); /* 6a00/6b00 */
	570	void mmfm_a(UINT16 op); /* 09a0 */
	571	void mmfm_b(UINT16 op); /* 09b0 */
	572	void mmtm_a(UINT16 op); /* 0980 */
	573	void mmtm_b(UINT16 op); /* 0990 */
	574	void mods_a(UINT16 op); /* 6c00/6d00 */
	575	void mods_b(UINT16 op); /* 6c00/6d00 */
	576	void modu_a(UINT16 op); /* 6e00/6f00 */
	577	void modu_b(UINT16 op); /* 6e00/6f00 */
	578	void mpys_a(UINT16 op); /* 5c00/5d00 */
	579	void mpys_b(UINT16 op); /* 5c00/5d00 */
	580	void mpyu_a(UINT16 op); /* 5e00/5e00 */
	581	void mpyu_b(UINT16 op); /* 5e00/5f00 */
	582	void neg_a(UINT16 op); /* 03a0 */
	583	void neg_b(UINT16 op); /* 03b0 */
	584	void negb_a(UINT16 op); /* 03c0 */
	585	void negb_b(UINT16 op); /* 03d0 */
	586	void nop(UINT16 op); /* 0300 */
	587	void not_a(UINT16 op); /* 03e0 */
	588	void not_b(UINT16 op); /* 03f0 */
	589	void or_a(UINT16 op); /* 5400-5500 */
	590	void or_b(UINT16 op); /* 5400-5500 */
	591	void ori_a(UINT16 op); /* 0ba0 */
	592	void ori_b(UINT16 op); /* 0bb0 */
	593	void rl_k_a(UINT16 op); /* 3000-3300 */
	594	void rl_k_b(UINT16 op); /* 3000-3300 */
	595	void rl_r_a(UINT16 op); /* 6800/6900 */
	596	void rl_r_b(UINT16 op); /* 6800/6900 */
	597	void setc(UINT16 op); /* 0de0 */
	598	void setf0(UINT16 op);
	599	void setf1(UINT16 op);
	600	void sext0_a(UINT16 op); /* 0500 */
	601	void sext0_b(UINT16 op); /* 0510 */
	602	void sext1_a(UINT16 op); /* 0700 */
	603	void sext1_b(UINT16 op); /* 0710 */
	604	void sla_k_a(UINT16 op); /* 2000-2300 */
	605	void sla_k_b(UINT16 op); /* 2000-2300 */
	606	void sla_r_a(UINT16 op); /* 6000/6100 */
	607	void sla_r_b(UINT16 op); /* 6000/6100 */
	608	void sll_k_a(UINT16 op); /* 2400-2700 */
	609	void sll_k_b(UINT16 op); /* 2400-2700 */
	610	void sll_r_a(UINT16 op); /* 6200/6300 */
	611	void sll_r_b(UINT16 op); /* 6200/6300 */
	612	void sra_k_a(UINT16 op); /* 2800-2b00 */
	613	void sra_k_b(UINT16 op); /* 2800-2b00 */
	614	void sra_r_a(UINT16 op); /* 6400/6500 */
	615	void sra_r_b(UINT16 op); /* 6400/6500 */
	616	void srl_k_a(UINT16 op); /* 2c00-2f00 */
	617	void srl_k_b(UINT16 op); /* 2c00-2f00 */
	618	void srl_r_a(UINT16 op); /* 6600/6700 */
	619	void srl_r_b(UINT16 op); /* 6600/6700 */
	620	void sub_a(UINT16 op); /* 4400/4500 */
	621	void sub_b(UINT16 op); /* 4400/4500 */
	622	void subb_a(UINT16 op); /* 4600/4700 */
	623	void subb_b(UINT16 op); /* 4600/4700 */
	624	void subi_w_a(UINT16 op); /* 0be0 */
	625	void subi_w_b(UINT16 op); /* 0bf0 */
	626	void subi_l_a(UINT16 op); /* 0d00 */
	627	void subi_l_b(UINT16 op); /* 0d10 */
	628	void subk_a(UINT16 op); /* 1400-1700 */
	629	void subk_b(UINT16 op); /* 1400-1700 */
	630	void xor_a(UINT16 op); /* 5600-5700 */
	631	void xor_b(UINT16 op); /* 5600-5700 */
	632	void xori_a(UINT16 op); /* 0bc0 */
	633	void xori_b(UINT16 op); /* 0bd0 */
	634	void zext0_a(UINT16 op); /* 0520 */
	635	void zext0_b(UINT16 op); /* 0530 */
	636	void zext1_a(UINT16 op); /* 0720 */
	637	void zext1_b(UINT16 op); /* 0720 */
	638	void movi_w_a(UINT16 op);
	639	void movi_w_b(UINT16 op);
	640	void movi_l_a(UINT16 op);
	641	void movi_l_b(UINT16 op);
	642	void movk_a(UINT16 op);
	643	void movk_b(UINT16 op);
	644	void movb_rn_a(UINT16 op); /* 8c00-8d00 */
	645	void movb_rn_b(UINT16 op); /* 8c00-8d00 */
	646	void movb_nr_a(UINT16 op); /* 8e00-8f00 */
	647	void movb_nr_b(UINT16 op); /* 8e00-8f00 */
	648	void movb_nn_a(UINT16 op); /* 9c00-9d00 */
	649	void movb_nn_b(UINT16 op); /* 9c00-9d00 */
	650	void movb_r_no_a(UINT16 op); /* ac00-ad00 */
	651	void movb_r_no_b(UINT16 op); /* ac00-ad00 */
	652	void movb_no_r_a(UINT16 op); /* ae00-af00 */
	653	void movb_no_r_b(UINT16 op); /* ae00-af00 */
	654	void movb_no_no_a(UINT16 op); /* bc00-bd00 */
	655	void movb_no_no_b(UINT16 op); /* bc00-bd00 */
	656	void movb_ra_a(UINT16 op);
	657	void movb_ra_b(UINT16 op);
	658	void movb_ar_a(UINT16 op);
	659	void movb_ar_b(UINT16 op);
	660	void movb_aa(UINT16 op);
	661	void move_rr_a(UINT16 op); /* 4c00/d00 */
	662	void move_rr_b(UINT16 op); /* 4c00/d00 */
	663	void move_rr_ax(UINT16 op); /* 4e00/f00 */
	664	void move_rr_bx(UINT16 op); /* 4e00/f00 */
	665	void move0_rn_a(UINT16 op); /* 8000 */
	666	void move0_rn_b(UINT16 op);
	667	void move1_rn_a(UINT16 op);
	668	void move1_rn_b(UINT16 op);
	669	void move0_r_dn_a(UINT16 op); /* a000 */
	670	void move0_r_dn_b(UINT16 op);
	671	void move1_r_dn_a(UINT16 op);
	672	void move1_r_dn_b(UINT16 op);
	673	void move0_r_ni_a(UINT16 op); /* 9000 */
	674	void move0_r_ni_b(UINT16 op);
	675	void move1_r_ni_a(UINT16 op);
	676	void move1_r_ni_b(UINT16 op);
	677	void move0_nr_a(UINT16 op); /* 8400-500 */
	678	void move0_nr_b(UINT16 op); /* 8400-500 */
	679	void move1_nr_a(UINT16 op); /* 8600-700 */
	680	void move1_nr_b(UINT16 op); /* 8600-700 */
	681	void move0_dn_r_a(UINT16 op); /* A400-500 */
	682	void move0_dn_r_b(UINT16 op); /* A400-500 */
	683	void move1_dn_r_a(UINT16 op); /* A600-700 */
	684	void move1_dn_r_b(UINT16 op); /* A600-700 */
	685	void move0_ni_r_a(UINT16 op); /* 9400-500 */
	686	void move0_ni_r_b(UINT16 op); /* 9400-500 */
	687	void move1_ni_r_a(UINT16 op); /* 9600-700 */
	688	void move1_ni_r_b(UINT16 op); /* 9600-700 */
	689	void move0_nn_a(UINT16 op); /* 8800 */
	690	void move0_nn_b(UINT16 op);
	691	void move1_nn_a(UINT16 op);
	692	void move1_nn_b(UINT16 op);
	693	void move0_dn_dn_a(UINT16 op); /* a800 */
	694	void move0_dn_dn_b(UINT16 op);
	695	void move1_dn_dn_a(UINT16 op);
	696	void move1_dn_dn_b(UINT16 op);
	697	void move0_ni_ni_a(UINT16 op); /* 9800 */
	698	void move0_ni_ni_b(UINT16 op);
	699	void move1_ni_ni_a(UINT16 op);
	700	void move1_ni_ni_b(UINT16 op);
	701	void move0_r_no_a(UINT16 op); /* b000 */
	702	void move0_r_no_b(UINT16 op);
	703	void move1_r_no_a(UINT16 op);
	704	void move1_r_no_b(UINT16 op);
	705	void move0_no_r_a(UINT16 op); /* b400 */
	706	void move0_no_r_b(UINT16 op);
	707	void move1_no_r_a(UINT16 op);
	708	void move1_no_r_b(UINT16 op);
	709	void move0_no_ni_a(UINT16 op); /* d000 */
	710	void move0_no_ni_b(UINT16 op);
	711	void move1_no_ni_a(UINT16 op);
	712	void move1_no_ni_b(UINT16 op);
	713	void move0_no_no_a(UINT16 op); /* b800 */
	714	void move0_no_no_b(UINT16 op);
	715	void move1_no_no_a(UINT16 op);
	716	void move1_no_no_b(UINT16 op);
	717	void move0_ra_a(UINT16 op);
	718	void move0_ra_b(UINT16 op);
	719	void move1_ra_a(UINT16 op);
	720	void move1_ra_b(UINT16 op);
	721	void move0_ar_a(UINT16 op);
	722	void move0_ar_b(UINT16 op);
	723	void move1_ar_a(UINT16 op);
	724	void move1_ar_b(UINT16 op);
	725	void move0_a_ni_a(UINT16 op); /* d400 */
	726	void move0_a_ni_b(UINT16 op); /* d410 */
	727	void move1_a_ni_a(UINT16 op); /* d600 */
	728	void move1_a_ni_b(UINT16 op); /* d610 */
	729	void move0_aa(UINT16 op); /* 05c0 */
	730	void move1_aa(UINT16 op); /* 07c0 */
	731	void call_a(UINT16 op); /* 0920 */
	732	void call_b(UINT16 op); /* 0930 */
	733	void callr(UINT16 op); /* 0d3f */
	734	void calla(UINT16 op); /* 0d5f */
	735	void dsj_a(UINT16 op); /* 0d80 */
	736	void dsj_b(UINT16 op); /* 0d90 */
	737	void dsjeq_a(UINT16 op); /* 0da0 */
	738	void dsjeq_b(UINT16 op); /* 0db0 */
	739	void dsjne_a(UINT16 op); /* 0dc0 */
	740	void dsjne_b(UINT16 op); /* 0dd0 */
	741	void dsjs_a(UINT16 op);
	742	void dsjs_b(UINT16 op);
	743	void emu(UINT16 op); /* 0100 */
	744	void exgpc_a(UINT16 op); /* 0120 */
	745	void exgpc_b(UINT16 op); /* 0130 */
	746	void getpc_a(UINT16 op); /* 0140 */
	747	void getpc_b(UINT16 op); /* 0150 */
	748	void getst_a(UINT16 op); /* 0180 */
	749	void getst_b(UINT16 op); /* 0190 */
	750	void j_UC_0(UINT16 op);
	751	void j_UC_8(UINT16 op);
	752	void j_UC_x(UINT16 op);
	753	void j_P_0(UINT16 op);
	754	void j_P_8(UINT16 op);
	755	void j_P_x(UINT16 op);
	756	void j_LS_0(UINT16 op);
	757	void j_LS_8(UINT16 op);
	758	void j_LS_x(UINT16 op);
	759	void j_HI_0(UINT16 op);
	760	void j_HI_8(UINT16 op);
	761	void j_HI_x(UINT16 op);
	762	void j_LT_0(UINT16 op);
	763	void j_LT_8(UINT16 op);
	764	void j_LT_x(UINT16 op);
	765	void j_GE_0(UINT16 op);
	766	void j_GE_8(UINT16 op);
	767	void j_GE_x(UINT16 op);
	768	void j_LE_0(UINT16 op);
	769	void j_LE_8(UINT16 op);
	770	void j_LE_x(UINT16 op);
	771	void j_GT_0(UINT16 op);
	772	void j_GT_8(UINT16 op);
	773	void j_GT_x(UINT16 op);
	774	void j_C_0(UINT16 op);
	775	void j_C_8(UINT16 op);
	776	void j_C_x(UINT16 op);
	777	void j_NC_0(UINT16 op);
	778	void j_NC_8(UINT16 op);
	779	void j_NC_x(UINT16 op);
	780	void j_EQ_0(UINT16 op);
	781	void j_EQ_8(UINT16 op);
	782	void j_EQ_x(UINT16 op);
	783	void j_NE_0(UINT16 op);
	784	void j_NE_8(UINT16 op);
	785	void j_NE_x(UINT16 op);
	786	void j_V_0(UINT16 op);
	787	void j_V_8(UINT16 op);
	788	void j_V_x(UINT16 op);
	789	void j_NV_0(UINT16 op);
	790	void j_NV_8(UINT16 op);
	791	void j_NV_x(UINT16 op);
	792	void j_N_0(UINT16 op);
	793	void j_N_8(UINT16 op);
	794	void j_N_x(UINT16 op);
	795	void j_NN_0(UINT16 op);
	796	void j_NN_8(UINT16 op);
	797	void j_NN_x(UINT16 op);
	798	void jump_a(UINT16 op); /* 0160 */
	799	void jump_b(UINT16 op); /* 0170 */
	800	void popst(UINT16 op); /* 01c0 */
	801	void pushst(UINT16 op); /* 01e0 */
	802	void putst_a(UINT16 op); /* 01a0 */
	803	void putst_b(UINT16 op); /* 01b0 */
	804	void reti(UINT16 op); /* 0940 */
	805	void rets(UINT16 op); /* 0960/70 */
	806	void rev_a(UINT16 op); /* 0020 */
	807	void rev_b(UINT16 op); /* 0030 */
	808	void trap(UINT16 op); /* 0900/10 */
	809	void addxyi_a(UINT16 op);
	810	void addxyi_b(UINT16 op);
	811	void blmove(UINT16 op);
	812	void cexec_l(UINT16 op);
	813	void cexec_s(UINT16 op);
	814	void clip(UINT16 op);
	815	void cmovcg_a(UINT16 op);
	816	void cmovcg_b(UINT16 op);
	817	void cmovcm_f(UINT16 op);
	818	void cmovcm_b(UINT16 op);
	819	void cmovgc_a(UINT16 op);
	820	void cmovgc_b(UINT16 op);
	821	void cmovgc_a_s(UINT16 op);
	822	void cmovgc_b_s(UINT16 op);
	823	void cmovmc_f(UINT16 op);
	824	void cmovmc_f_va(UINT16 op);
	825	void cmovmc_f_vb(UINT16 op);
	826	void cmovmc_b(UINT16 op);
	827	void cmp_k_a(UINT16 op);
	828	void cmp_k_b(UINT16 op);
	829	void cvdxyl_a(UINT16 op);
	830	void cvdxyl_b(UINT16 op);
	831	void cvmxyl_a(UINT16 op);
	832	void cvmxyl_b(UINT16 op);
	833	void cvsxyl_a(UINT16 op);
	834	void cvsxyl_b(UINT16 op);
	835	void exgps_a(UINT16 op);
	836	void exgps_b(UINT16 op);
	837	void fline(UINT16 op);
	838	void fpixeq(UINT16 op);
	839	void fpixne(UINT16 op);
	840	void getps_a(UINT16 op);
	841	void getps_b(UINT16 op);
	842	void idle(UINT16 op);
	843	void linit(UINT16 op);
	844	void mwait(UINT16 op);
	845	void pfill_xy(UINT16 op);
	846	void pixblt_l_m_l(UINT16 op);
	847	void retm(UINT16 op);
	848	void rmo_a(UINT16 op);
	849	void rmo_b(UINT16 op);
	850	void rpix_a(UINT16 op);
	851	void rpix_b(UINT16 op);
	852	void setcdp(UINT16 op);
	853	void setcmp(UINT16 op);
	854	void setcsp(UINT16 op);
	855	void swapf_a(UINT16 op);
	856	void swapf_b(UINT16 op);
	857	void tfill_xy(UINT16 op);
	858	void trapl(UINT16 op);
	859	void vblt_b_l(UINT16 op);
	860	void vfill_l(UINT16 op);
	861	void vlcol(UINT16 op);
	862	int apply_window(const char inst_name,int srcbpp, UINT32 srcaddr, XY dst, int dx, int *dy);
	863	int compute_fill_cycles(int left_partials, int right_partials, int full_words, int op_timing);
	864	int compute_pixblt_cycles(int left_partials, int right_partials, int full_words, int op_timing);
	865	int compute_pixblt_b_cycles(int left_partials, int right_partials, int full_words, int rows, int op_timing, int bpp);
	866	void memory_w(address_space &space, offs_t offset,UINT16 data);
	867	UINT16 memory_r(address_space &space, offs_t offset);
	868	void shiftreg_w(address_space &space, offs_t offset, UINT16 data);
	869	UINT16 shiftreg_r(address_space &space, offs_t offset);
	870	UINT16 dummy_shiftreg_r(address_space &space, offs_t offset);
	871	UINT32 pixel_op00(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	872	UINT32 pixel_op01(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	873	UINT32 pixel_op02(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	874	UINT32 pixel_op03(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	875	UINT32 pixel_op04(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	876	UINT32 pixel_op05(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	877	UINT32 pixel_op06(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	878	UINT32 pixel_op07(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	879	UINT32 pixel_op08(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	880	UINT32 pixel_op09(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	881	UINT32 pixel_op10(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	882	UINT32 pixel_op11(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	883	UINT32 pixel_op12(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	884	UINT32 pixel_op13(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	885	UINT32 pixel_op14(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	886	UINT32 pixel_op15(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	887	UINT32 pixel_op16(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	888	UINT32 pixel_op17(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	889	UINT32 pixel_op18(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	890	UINT32 pixel_op19(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	891	UINT32 pixel_op20(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	892	UINT32 pixel_op21(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
	893	void pixblt_1_op0(int src_is_linear, int dst_is_linear);
	894	void pixblt_2_op0(int src_is_linear, int dst_is_linear);
	895	void pixblt_4_op0(int src_is_linear, int dst_is_linear);
	896	void pixblt_8_op0(int src_is_linear, int dst_is_linear);
	897	void pixblt_16_op0(int src_is_linear, int dst_is_linear);
	898	void pixblt_r_1_op0(int src_is_linear, int dst_is_linear);
	899	void pixblt_r_2_op0(int src_is_linear, int dst_is_linear);
	900	void pixblt_r_4_op0(int src_is_linear, int dst_is_linear);
	901	void pixblt_r_8_op0(int src_is_linear, int dst_is_linear);
	902	void pixblt_r_16_op0(int src_is_linear, int dst_is_linear);
	903	void pixblt_b_1_op0(int dst_is_linear);
	904	void pixblt_b_2_op0(int dst_is_linear);
	905	void pixblt_b_4_op0(int dst_is_linear);
	906	void pixblt_b_8_op0(int dst_is_linear);
	907	void pixblt_b_16_op0(int dst_is_linear);
	908	void fill_1_op0(int dst_is_linear);
	909	void fill_2_op0(int dst_is_linear);
	910	void fill_4_op0(int dst_is_linear);
	911	void fill_8_op0(int dst_is_linear);
	912	void fill_16_op0(int dst_is_linear);
	913	void pixblt_1_op0_trans(int src_is_linear, int dst_is_linear);
	914	void pixblt_2_op0_trans(int src_is_linear, int dst_is_linear);
	915	void pixblt_4_op0_trans(int src_is_linear, int dst_is_linear);
	916	void pixblt_8_op0_trans(int src_is_linear, int dst_is_linear);
	917	void pixblt_16_op0_trans(int src_is_linear, int dst_is_linear);
	918	void pixblt_r_1_op0_trans(int src_is_linear, int dst_is_linear);
	919	void pixblt_r_2_op0_trans(int src_is_linear, int dst_is_linear);
	920	void pixblt_r_4_op0_trans(int src_is_linear, int dst_is_linear);
	921	void pixblt_r_8_op0_trans(int src_is_linear, int dst_is_linear);
	922	void pixblt_r_16_op0_trans(int src_is_linear, int dst_is_linear);
	923	void pixblt_b_1_op0_trans(int dst_is_linear);
	924	void pixblt_b_2_op0_trans(int dst_is_linear);
	925	void pixblt_b_4_op0_trans(int dst_is_linear);
	926	void pixblt_b_8_op0_trans(int dst_is_linear);
	927	void pixblt_b_16_op0_trans(int dst_is_linear);
	928	void fill_1_op0_trans(int dst_is_linear);
	929	void fill_2_op0_trans(int dst_is_linear);
	930	void fill_4_op0_trans(int dst_is_linear);
	931	void fill_8_op0_trans(int dst_is_linear);
	932	void fill_16_op0_trans(int dst_is_linear);
	933	void pixblt_1_opx(int src_is_linear, int dst_is_linear);
	934	void pixblt_2_opx(int src_is_linear, int dst_is_linear);
	935	void pixblt_4_opx(int src_is_linear, int dst_is_linear);
	936	void pixblt_8_opx(int src_is_linear, int dst_is_linear);
	937	void pixblt_16_opx(int src_is_linear, int dst_is_linear);
	938	void pixblt_r_1_opx(int src_is_linear, int dst_is_linear);
	939	void pixblt_r_2_opx(int src_is_linear, int dst_is_linear);
	940	void pixblt_r_4_opx(int src_is_linear, int dst_is_linear);
	941	void pixblt_r_8_opx(int src_is_linear, int dst_is_linear);
	942	void pixblt_r_16_opx(int src_is_linear, int dst_is_linear);
	943	void pixblt_b_1_opx(int dst_is_linear);
	944	void pixblt_b_2_opx(int dst_is_linear);
	945	void pixblt_b_4_opx(int dst_is_linear);
	946	void pixblt_b_8_opx(int dst_is_linear);
	947	void pixblt_b_16_opx(int dst_is_linear);
	948	void fill_1_opx(int dst_is_linear);
	949	void fill_2_opx(int dst_is_linear);
	950	void fill_4_opx(int dst_is_linear);
	951	void fill_8_opx(int dst_is_linear);
	952	void fill_16_opx(int dst_is_linear);
	953	void pixblt_1_opx_trans(int src_is_linear, int dst_is_linear);
	954	void pixblt_2_opx_trans(int src_is_linear, int dst_is_linear);
	955	void pixblt_4_opx_trans(int src_is_linear, int dst_is_linear);
	956	void pixblt_8_opx_trans(int src_is_linear, int dst_is_linear);
	957	void pixblt_16_opx_trans(int src_is_linear, int dst_is_linear);
	958	void pixblt_r_1_opx_trans(int src_is_linear, int dst_is_linear);
	959	void pixblt_r_2_opx_trans(int src_is_linear, int dst_is_linear);
	960	void pixblt_r_4_opx_trans(int src_is_linear, int dst_is_linear);
	961	void pixblt_r_8_opx_trans(int src_is_linear, int dst_is_linear);
	962	void pixblt_r_16_opx_trans(int src_is_linear, int dst_is_linear);
	963	void pixblt_b_1_opx_trans(int dst_is_linear);
	964	void pixblt_b_2_opx_trans(int dst_is_linear);
	965	void pixblt_b_4_opx_trans(int dst_is_linear);
	966	void pixblt_b_8_opx_trans(int dst_is_linear);
	967	void pixblt_b_16_opx_trans(int dst_is_linear);
	968	void fill_1_opx_trans(int dst_is_linear);
	969	void fill_2_opx_trans(int dst_is_linear);
	970	void fill_4_opx_trans(int dst_is_linear);
	971	void fill_8_opx_trans(int dst_is_linear);
	972	void fill_16_opx_trans(int dst_is_linear);
	973	void check_interrupt();
	974	void set_pixel_function();
	975	void set_raster_op();
	976
222	977	};
223	978
	979
	980	class tms34010_device : public tms340x0_device
	981	{
	982	public:
	983	tms34010_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	984
	985	/* Reads & writes to the 34010 I/O registers; place at 0xc0000000 */
	986	virtual DECLARE_WRITE16_MEMBER( io_register_w );
	987	virtual DECLARE_READ16_MEMBER( io_register_r );
	988
	989	protected:
	990	virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 8 - 1) / 8; }
	991	virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 8); }
	992	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	993	};
	994
224	995	extern const device_type TMS34010;
225	996
226		class tms34020_device : public tms34010_device
	997	class tms34020_device : public tms340x0_device
227	998	{
228	999	public:
229		tms34020_device(const machine_config &mconfig, device_type type, const char tag, device_t owner, UINT32 clock);
	1000	tms34020_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	1001
230	1002	/* Reads & writes to the 34010 I/O registers; place at 0xc0000000 */
231		DECLARE_WRITE16_MEMBER( io_register_w );
232		DECLARE_READ16_MEMBER( io_register_r );
	1003	virtual DECLARE_WRITE16_MEMBER( io_register_w );
	1004	virtual DECLARE_READ16_MEMBER( io_register_r );
	1005
	1006	protected:
	1007	virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 4 - 1) / 4; }
	1008	virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 4); }
	1009	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
233	1010	};
234	1011
235	1012	extern const device_type TMS34020;

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