MAME SVN History

199869 Revisions

r30938 Wednesday 11th June, 2014 at 10:35:47 UTC by Dirk Best
upd7810: reorganize, compile source files seperately instead of including them into the main source

[src/emu/cpu]	cpu.mak
[src/emu/cpu/upd7810]	~~7810dasm.c~~ ~~7810ops.inc~~ ~~7810tbl.inc~~ upd7810.c upd7810.h upd7810_dasm.c* upd7810_macros.h* upd7810_opcodes.c* upd7810_table.c*

trunk/src/emu/cpu/upd7810/7810dasm.c
r30937	r30938
1		/*****************************************************************************
2		*
3		* Portable uPD7810/11, 7810H/11H, 78C10/C11/C14 disassembler
4		* Copyright Juergen Buchmueller, all rights reserved.
5		*
6		* NS20030112: added 7807.
7		*
8		*****************************************************************************/
9
10		#include "emu.h"
11		#include "debugger.h"
12		#include "upd7810.h"
13
14		struct dasm_s {
15		UINT8 token;
16		const void *args;
17		};
18
19		enum
20		{
21		illegal=1,
22		ACI,
23		ADC,
24		ADCW,
25		ADCX,
26		ADD,
27		ADDNC,
28		ADDNCW,
29		ADDNCX,
30		ADDW,
31		ADDX,
32		ADI,
33		ADINC,
34		ANA,
35		ANAW,
36		ANAX,
37		AND,
38		ANI,
39		ANIW,
40		BIT,
41		BLOCK,
42		CALB,
43		CALF,
44		CALL,
45		CALT,
46		CLC,
47		CLR, /* 7807 */
48		CMC, /* 7807 */
49		DAA,
50		DADC,
51		DADD,
52		DADDNC,
53		DAN,
54		DCR,
55		DCRW,
56		DCX,
57		DEQ,
58		DGT,
59		DI,
60		DIV,
61		DLT,
62		DMOV,
63		DNE,
64		DOFF,
65		DON,
66		DOR,
67		DRLL,
68		DRLR,
69		DSBB,
70		DSLL,
71		DSLR,
72		DSUB,
73		DSUBNB,
74		DXR,
75		EADD,
76		EI,
77		EQA,
78		EQAW,
79		EQAX,
80		EQI,
81		EQIW,
82		ESUB,
83		EX, /* 7801 */
84		EXA,
85		EXH,
86		EXX,
87		EXR, /* 7807 */
88		GTA,
89		GTAW,
90		GTAX,
91		GTI,
92		GTIW,
93		HALT,
94		IN, /* 7801 */
95		INR,
96		INRW,
97		INX,
98		JB,
99		JEA,
100		JMP,
101		JR,
102		JRE,
103		LBCD,
104		LDAW,
105		LDAX,
106		LDEAX,
107		LDED,
108		LHLD,
109		LSPD,
110		LTA,
111		LTAW,
112		LTAX,
113		LTI,
114		LTIW,
115		LXI,
116		MOV,
117		MUL,
118		MVI,
119		MVIW,
120		MVIX,
121		NEA,
122		NEAW,
123		NEAX,
124		NEGA,
125		NEI,
126		NEIW,
127		NOP,
128		NOT, /* 7807 */
129		OFFA,
130		OFFAW,
131		OFFAX,
132		OFFI,
133		OFFIW,
134		ONA,
135		ONAW,
136		ONAX,
137		ONI,
138		ONIW,
139		OR, /* 7807 */
140		ORA,
141		ORAW,
142		ORAX,
143		ORI,
144		ORIW,
145		OUT, /* 7801 */
146		PER, /* 7801 */
147		PEX, /* 7801 */
148		POP,
149		PUSH,
150		RET,
151		RETI,
152		RETS,
153		RLD,
154		RLL,
155		RLR,
156		RRD,
157		SBB,
158		SBBW,
159		SBBX,
160		SBCD,
161		SBI,
162		SDED,
163		SETB, /* 7807 */
164		SHLD,
165		SIO, /* 7801 */
166		SK,
167		SKIT,
168		SKN,
169		SKNIT,
170		SLL,
171		SLLC,
172		SLR,
173		SLRC,
174		SOFTI,
175		SSPD,
176		STAW,
177		STAX,
178		STC,
179		STEAX,
180		STM, /* 7801 */
181		STOP,
182		SUB,
183		SUBNB,
184		SUBNBW,
185		SUBNBX,
186		SUBW,
187		SUBX,
188		SUI,
189		SUINB,
190		TABLE,
191		XOR, /* 7807 */
192		XRA,
193		XRAW,
194		XRAX,
195		XRI
196		};
197
198		static const char *const token[] =
199		{
200		"",
201		"illegal",
202		"ACI",
203		"ADC",
204		"ADCW",
205		"ADCX",
206		"ADD",
207		"ADDNC",
208		"ADDNCW",
209		"ADDNCX",
210		"ADDW",
211		"ADDX",
212		"ADI",
213		"ADINC",
214		"ANA",
215		"ANAW",
216		"ANAX",
217		"AND",
218		"ANI",
219		"ANIW",
220		"BIT",
221		"BLOCK",
222		"CALB",
223		"CALF",
224		"CALL",
225		"CALT",
226		"CLC",
227		"CLR", /* 7807 */
228		"CMC", /* 7807 */
229		"DAA",
230		"DADC",
231		"DADD",
232		"DADDNC",
233		"DAN",
234		"DCR",
235		"DCRW",
236		"DCX",
237		"DEQ",
238		"DGT",
239		"DI",
240		"DIV",
241		"DLT",
242		"DMOV",
243		"DNE",
244		"DOFF",
245		"DON",
246		"DOR",
247		"DRLL",
248		"DRLR",
249		"DSBB",
250		"DSLL",
251		"DSLR",
252		"DSUB",
253		"DSUBNB",
254		"DXR",
255		"EADD",
256		"EI",
257		"EQA",
258		"EQAW",
259		"EQAX",
260		"EQI",
261		"EQIW",
262		"ESUB",
263		"EX", /* 7801 */
264		"EXA",
265		"EXH",
266		"EXX",
267		"EXR", /* 7807 */
268		"GTA",
269		"GTAW",
270		"GTAX",
271		"GTI",
272		"GTIW",
273		"HALT",
274		"IN", /* 7801 */
275		"INR",
276		"INRW",
277		"INX",
278		"JB",
279		"JEA",
280		"JMP",
281		"JR",
282		"JRE",
283		"LBCD",
284		"LDAW",
285		"LDAX",
286		"LDEAX",
287		"LDED",
288		"LHLD",
289		"LSPD",
290		"LTA",
291		"LTAW",
292		"LTAX",
293		"LTI",
294		"LTIW",
295		"LXI",
296		"MOV",
297		"MUL",
298		"MVI",
299		"MVIW",
300		"MVIX",
301		"NEA",
302		"NEAW",
303		"NEAX",
304		"NEGA",
305		"NEI",
306		"NEIW",
307		"NOP",
308		"NOT", /* 7807 */
309		"OFFA",
310		"OFFAW",
311		"OFFAX",
312		"OFFI",
313		"OFFIW",
314		"ONA",
315		"ONAW",
316		"ONAX",
317		"ONI",
318		"ONIW",
319		"OR", /* 7807 */
320		"ORA",
321		"ORAW",
322		"ORAX",
323		"ORI",
324		"ORIW",
325		"OUT", /* 7801 */
326		"PER", /* 7801 */
327		"PEX", /* 7801 */
328		"POP",
329		"PUSH",
330		"RET",
331		"RETI",
332		"RETS",
333		"RLD",
334		"RLL",
335		"RLR",
336		"RRD",
337		"SBB",
338		"SBBW",
339		"SBBX",
340		"SBCD",
341		"SBI",
342		"SDED",
343		"SETB", /* 7807 */
344		"SHLD",
345		"SIO", /* 7801 */
346		"SK",
347		"SKIT",
348		"SKN",
349		"SKNIT",
350		"SLL",
351		"SLLC",
352		"SLR",
353		"SLRC",
354		"SOFTI",
355		"SSPD",
356		"STAW",
357		"STAX",
358		"STC",
359		"STEAX",
360		"STM", /7801 /
361		"STOP",
362		"SUB",
363		"SUBNB",
364		"SUBNBW",
365		"SUBNBX",
366		"SUBW",
367		"SUBX",
368		"SUI",
369		"SUINB",
370		"TABLE",
371		"XOR", /* 7807 */
372		"XRA",
373		"XRAW",
374		"XRAX",
375		"XRI"
376		};
377
378
379		/* prefix 48 */
380		static const struct dasm_s dasm48_7810[256] =
381		{
382		{illegal,0 }, /* 00: 0100 1000 0000 0000 */
383		{SLRC,"A" }, /* 01: 0100 1000 0000 0001 */
384		{SLRC,"B" }, /* 02: 0100 1000 0000 0010 */
385		{SLRC,"C" }, /* 03: 0100 1000 0000 0011 */
386		{illegal,0 }, /* 04: 0100 1000 0000 0100 */
387		{SLLC,"A" }, /* 05: 0100 1000 0000 0101 */
388		{SLLC,"B" }, /* 06: 0100 1000 0000 0110 */
389		{SLLC,"C" }, /* 07: 0100 1000 0000 0111 */
390		{SK,"NV" }, /* 08: 0100 1000 0000 1000 */
391		{illegal,0 }, /* 09: 0100 1000 0000 1001 */
392		{SK,"CY" }, /* 0a: 0100 1000 0000 1010 */
393		{SK,"HC" }, /* 0b: 0100 1000 0000 1011 */
394		{SK,"Z" }, /* 0c: 0100 1000 0000 1100 */
395		{illegal,0 }, /* 0d: 0100 1000 0000 1101 */
396		{illegal,0 }, /* 0e: 0100 1000 0000 1110 */
397		{illegal,0 }, /* 0f: 0100 1000 0000 1111 */
398
399		{illegal,0 }, /* 10: 0100 1000 0001 0000 */
400		{illegal,0 }, /* 11: 0100 1000 0001 0001 */
401		{illegal,0 }, /* 12: 0100 1000 0001 0010 */
402		{illegal,0 }, /* 13: 0100 1000 0001 0011 */
403		{illegal,0 }, /* 14: 0100 1000 0001 0100 */
404		{illegal,0 }, /* 15: 0100 1000 0001 0101 */
405		{illegal,0 }, /* 16: 0100 1000 0001 0110 */
406		{illegal,0 }, /* 17: 0100 1000 0001 0111 */
407		{SKN,"NV" }, /* 18: 0100 1000 0001 1000 */
408		{illegal,0 }, /* 19: 0100 1000 0001 1001 */
409		{SKN,"CY" }, /* 1a: 0100 1000 0001 1010 */
410		{SKN,"HC" }, /* 1b: 0100 1000 0001 1011 */
411		{SKN,"Z" }, /* 1c: 0100 1000 0001 1100 */
412		{illegal,0 }, /* 1d: 0100 1000 0001 1101 */
413		{illegal,0 }, /* 1e: 0100 1000 0001 1110 */
414		{illegal,0 }, /* 1f: 0100 1000 0001 1111 */
415
416		{illegal,0 }, /* 20: 0100 1000 0010 0000 */
417		{SLR,"A" }, /* 21: 0100 1000 0010 0001 */
418		{SLR,"B" }, /* 22: 0100 1000 0010 0010 */
419		{SLR,"C" }, /* 23: 0100 1000 0010 0011 */
420		{illegal,0 }, /* 24: 0100 1000 0010 0100 */
421		{SLL,"A" }, /* 25: 0100 1000 0010 0101 */
422		{SLL,"B" }, /* 26: 0100 1000 0010 0110 */
423		{SLL,"C" }, /* 27: 0100 1000 0010 0111 */
424		{JEA,0 }, /* 28: 0100 1000 0010 1000 */
425		{CALB,0 }, /* 29: 0100 1000 0010 1001 */
426		{CLC,0 }, /* 2a: 0100 1000 0010 1010 */
427		{STC,0 }, /* 2b: 0100 1000 0010 1011 */
428		{illegal,0 }, /* 2c: 0100 1000 0010 1100 */
429		{MUL,"A" }, /* 2d: 0100 1000 0010 1101 */
430		{MUL,"B" }, /* 2e: 0100 1000 0010 1110 */
431		{MUL,"C" }, /* 2f: 0100 1000 0010 1111 */
432
433		{illegal,0 }, /* 30: 0100 1000 0011 0000 */
434		{RLR,"A" }, /* 31: 0100 1000 0011 0001 */
435		{RLR,"B" }, /* 32: 0100 1000 0011 0010 */
436		{RLR,"C" }, /* 33: 0100 1000 0011 0011 */
437		{illegal,0 }, /* 34: 0100 1000 0011 0100 */
438		{RLL,"A" }, /* 35: 0100 1000 0011 0101 */
439		{RLL,"B" }, /* 36: 0100 1000 0011 0110 */
440		{RLL,"C" }, /* 37: 0100 1000 0011 0111 */
441		{RLD,0 }, /* 38: 0100 1000 0011 1000 */
442		{RRD,0 }, /* 39: 0100 1000 0011 1001 */
443		{NEGA,0 }, /* 3a: 0100 1000 0011 1010 */
444		{HALT,0 }, /* 3b: 0100 1000 0011 1011 */
445		{illegal,0 }, /* 3c: 0100 1000 0011 1100 */
446		{DIV,"A" }, /* 3d: 0100 1000 0011 1101 */
447		{DIV,"B" }, /* 3e: 0100 1000 0011 1110 */
448		{DIV,"C" }, /* 3f: 0100 1000 0011 1111 */
449
450		{SKIT,"NMI" }, /* 40: 0100 1000 0100 0000 */
451		{SKIT,"FT0" }, /* 41: 0100 1000 0100 0001 */
452		{SKIT,"FT1" }, /* 42: 0100 1000 0100 0010 */
453		{SKIT,"F1" }, /* 43: 0100 1000 0100 0011 */
454		{SKIT,"F2" }, /* 44: 0100 1000 0100 0100 */
455		{SKIT,"FE0" }, /* 45: 0100 1000 0100 0101 */
456		{SKIT,"FE1" }, /* 46: 0100 1000 0100 0110 */
457		{SKIT,"FEIN" }, /* 47: 0100 1000 0100 0111 */
458		{SKIT,"FAD" }, /* 48: 0100 1000 0100 1000 */
459		{SKIT,"FSR" }, /* 49: 0100 1000 0100 1001 */
460		{SKIT,"FST" }, /* 4a: 0100 1000 0100 1010 */
461		{SKIT,"ER" }, /* 4b: 0100 1000 0100 1011 */
462		{SKIT,"OV" }, /* 4c: 0100 1000 0100 1100 */
463		{illegal,0 }, /* 4d: 0100 1000 0100 1101 */
464		{illegal,0 }, /* 4e: 0100 1000 0100 1110 */
465		{illegal,0 }, /* 4f: 0100 1000 0100 1111 */
466
467		{SKIT,"AN4" }, /* 50: 0100 1000 0101 0000 */
468		{SKIT,"AN5" }, /* 51: 0100 1000 0101 0001 */
469		{SKIT,"AN6" }, /* 52: 0100 1000 0101 0010 */
470		{SKIT,"AN7" }, /* 53: 0100 1000 0101 0011 */
471		{SKIT,"SB" }, /* 54: 0100 1000 0101 0100 */
472		{illegal,0 }, /* 55: 0100 1000 0101 0101 */
473		{illegal,0 }, /* 56: 0100 1000 0101 0110 */
474		{illegal,0 }, /* 57: 0100 1000 0101 0111 */
475		{illegal,0 }, /* 58: 0100 1000 0101 1000 */
476		{illegal,0 }, /* 59: 0100 1000 0101 1001 */
477		{illegal,0 }, /* 5a: 0100 1000 0101 1010 */
478		{illegal,0 }, /* 5b: 0100 1000 0101 1011 */
479		{illegal,0 }, /* 5c: 0100 1000 0101 1100 */
480		{illegal,0 }, /* 5d: 0100 1000 0101 1101 */
481		{illegal,0 }, /* 5e: 0100 1000 0101 1110 */
482		{illegal,0 }, /* 5f: 0100 1000 0101 1111 */
483
484		{SKNIT,"NMI" }, /* 60: 0100 1000 0110 0000 */
485		{SKNIT,"FT0" }, /* 61: 0100 1000 0110 0001 */
486		{SKNIT,"FT1" }, /* 62: 0100 1000 0110 0010 */
487		{SKNIT,"F1" }, /* 63: 0100 1000 0110 0011 */
488		{SKNIT,"F2" }, /* 64: 0100 1000 0110 0100 */
489		{SKNIT,"FE0" }, /* 65: 0100 1000 0110 0101 */
490		{SKNIT,"FE1" }, /* 66: 0100 1000 0110 0110 */
491		{SKNIT,"FEIN" }, /* 67: 0100 1000 0110 0111 */
492		{SKNIT,"FAD" }, /* 68: 0100 1000 0110 1000 */
493		{SKNIT,"FSR" }, /* 69: 0100 1000 0110 1001 */
494		{SKNIT,"FST" }, /* 6a: 0100 1000 0110 1010 */
495		{SKNIT,"ER" }, /* 6b: 0100 1000 0110 1011 */
496		{SKNIT,"OV" }, /* 6c: 0100 1000 0110 1100 */
497		{illegal,0 }, /* 6d: 0100 1000 0110 1101 */
498		{illegal,0 }, /* 6e: 0100 1000 0110 1110 */
499		{illegal,0 }, /* 6f: 0100 1000 0110 1111 */
500
501		{SKNIT,"AN4" }, /* 70: 0100 1000 0111 0000 */
502		{SKNIT,"AN5" }, /* 71: 0100 1000 0111 0001 */
503		{SKNIT,"AN6" }, /* 72: 0100 1000 0111 0010 */
504		{SKNIT,"AN7" }, /* 73: 0100 1000 0111 0011 */
505		{SKNIT,"SB" }, /* 74: 0100 1000 0111 0100 */
506		{illegal,0 }, /* 75: 0100 1000 0111 0101 */
507		{illegal,0 }, /* 76: 0100 1000 0111 0110 */
508		{illegal,0 }, /* 77: 0100 1000 0111 0111 */
509		{illegal,0 }, /* 78: 0100 1000 0111 1000 */
510		{illegal,0 }, /* 79: 0100 1000 0111 1001 */
511		{illegal,0 }, /* 7a: 0100 1000 0111 1010 */
512		{illegal,0 }, /* 7b: 0100 1000 0111 1011 */
513		{illegal,0 }, /* 7c: 0100 1000 0111 1100 */
514		{illegal,0 }, /* 7d: 0100 1000 0111 1101 */
515		{illegal,0 }, /* 7e: 0100 1000 0111 1110 */
516		{illegal,0 }, /* 7f: 0100 1000 0111 1111 */
517
518		{illegal,0 }, /* 80: 0100 1000 1000 0000 */
519		{illegal,0 }, /* 81: 0100 1000 1000 0001 */
520		{LDEAX,"(DE)" }, /* 82: 0100 1000 1000 0010 */
521		{LDEAX,"(HL)" }, /* 83: 0100 1000 1000 0011 */
522		{LDEAX,"(DE++)" }, /* 84: 0100 1000 1000 0100 */
523		{LDEAX,"(HL++)" }, /* 85: 0100 1000 1000 0101 */
524		{illegal,0 }, /* 86: 0100 1000 1000 0110 */
525		{illegal,0 }, /* 87: 0100 1000 1000 0111 */
526		{illegal,0 }, /* 88: 0100 1000 1000 1000 */
527		{illegal,0 }, /* 89: 0100 1000 1000 1001 */
528		{illegal,0 }, /* 8a: 0100 1000 1000 1010 */
529		{LDEAX,"(DE+%b)"}, /* 8b: 0100 1000 1000 1011 xxxx xxxx */
530		{LDEAX,"(HL+A)" }, /* 8c: 0100 1000 1000 1100 */
531		{LDEAX,"(HL+B)" }, /* 8d: 0100 1000 1000 1101 */
532		{LDEAX,"(HL+EA)"}, /* 8e: 0100 1000 1000 1110 */
533		{LDEAX,"(HL+%b)"}, /* 8f: 0100 1000 1000 1111 xxxx xxxx */
534
535		{illegal,0 }, /* 90: 0100 1000 1000 0000 */
536		{illegal,0 }, /* 91: 0100 1000 1000 0001 */
537		{STEAX,"(DE)" }, /* 92: 0100 1000 1000 0010 */
538		{STEAX,"(HL)" }, /* 93: 0100 1000 1000 0011 */
539		{STEAX,"(DE++)" }, /* 94: 0100 1000 1000 0100 */
540		{STEAX,"(HL++)" }, /* 95: 0100 1000 1000 0101 */
541		{illegal,0 }, /* 96: 0100 1000 1000 0110 */
542		{illegal,0 }, /* 97: 0100 1000 1000 0111 */
543		{illegal,0 }, /* 98: 0100 1000 1000 1000 */
544		{illegal,0 }, /* 99: 0100 1000 1000 1001 */
545		{illegal,0 }, /* 9a: 0100 1000 1000 1010 */
546		{STEAX,"(DE+%b)"}, /* 9b: 0100 1000 1000 1011 xxxx xxxx */
547		{STEAX,"(HL+A)" }, /* 9c: 0100 1000 1000 1100 */
548		{STEAX,"(HL+B)" }, /* 9d: 0100 1000 1000 1101 */
549		{STEAX,"(HL+EA)"}, /* 9e: 0100 1000 1000 1110 */
550		{STEAX,"(HL+%b)"}, /* 9f: 0100 1000 1000 1111 xxxx xxxx */
551
552		{DSLR,"EA" }, /* a0: 0100 1000 1010 0000 */
553		{illegal,0 }, /* a1: 0100 1000 1010 0001 */
554		{illegal,0 }, /* a2: 0100 1000 1010 0010 */
555		{illegal,0 }, /* a3: 0100 1000 1010 0011 */
556		{DSLL,"EA" }, /* a4: 0100 1000 1010 0100 */
557		{illegal,0 }, /* a5: 0100 1000 1010 0101 */
558		{illegal,0 }, /* a6: 0100 1000 1010 0110 */
559		{illegal,0 }, /* a7: 0100 1000 1010 0111 */
560		{TABLE,0 }, /* a8: 0100 1000 1010 1000 */
561		{illegal,0 }, /* a9: 0100 1000 1010 1001 */
562		{illegal,0 }, /* aa: 0100 1000 1010 1010 */
563		{illegal,0 }, /* ab: 0100 1000 1010 1011 */
564		{illegal,0 }, /* ac: 0100 1000 1010 1100 */
565		{illegal,0 }, /* ad: 0100 1000 1010 1101 */
566		{illegal,0 }, /* ae: 0100 1000 1010 1110 */
567		{illegal,0 }, /* af: 0100 1000 1010 1111 */
568
569		{DRLR,"EA" }, /* b0: 0100 1000 1011 0000 */
570		{illegal,0 }, /* b1: 0100 1000 1011 0001 */
571		{illegal,0 }, /* b2: 0100 1000 1011 0010 */
572		{illegal,0 }, /* b3: 0100 1000 1011 0011 */
573		{DRLL,"EA" }, /* b4: 0100 1000 1011 0100 */
574		{illegal,0 }, /* b5: 0100 1000 1011 0101 */
575		{illegal,0 }, /* b6: 0100 1000 1011 0110 */
576		{illegal,0 }, /* b7: 0100 1000 1011 0111 */
577		{illegal,0 }, /* b8: 0100 1000 1011 1000 */
578		{illegal,0 }, /* b9: 0100 1000 1011 1001 */
579		{illegal,0 }, /* ba: 0100 1000 1011 1010 */
580		{STOP,0 }, /* bb: 0100 1000 1011 1011 / / 7810 */
581		{illegal,0 }, /* bc: 0100 1000 1011 1100 */
582		{illegal,0 }, /* bd: 0100 1000 1011 1101 */
583		{illegal,0 }, /* be: 0100 1000 1011 1110 */
584		{illegal,0 }, /* bf: 0100 1000 1011 1111 */
585
586		{DMOV,"EA,ECNT" }, /* c0: 0100 1000 1100 0000 */
587		{DMOV,"EA,ECPT" }, /* c1: 0100 1000 1100 0001 / / 7810 */
588		{illegal,0 }, /* c2: 0100 1000 1100 0010 */
589		{illegal,0 }, /* c3: 0100 1000 1100 0011 */
590		{illegal,0 }, /* c4: 0100 1000 1100 0100 */
591		{illegal,0 }, /* c5: 0100 1000 1100 0101 */
592		{illegal,0 }, /* c6: 0100 1000 1100 0110 */
593		{illegal,0 }, /* c7: 0100 1000 1100 0111 */
594		{illegal,0 }, /* c8: 0100 1000 1100 1000 */
595		{illegal,0 }, /* c9: 0100 1000 1100 1001 */
596		{illegal,0 }, /* ca: 0100 1000 1100 1010 */
597		{illegal,0 }, /* cb: 0100 1000 1100 1011 */
598		{illegal,0 }, /* cc: 0100 1000 1100 1100 */
599		{illegal,0 }, /* cd: 0100 1000 1100 1101 */
600		{illegal,0 }, /* ce: 0100 1000 1100 1110 */
601		{illegal,0 }, /* cf: 0100 1000 1100 1111 */
602
603		{illegal,0 }, /* d0: 0100 1000 1101 0000 */
604		{illegal,0 }, /* d1: 0100 1000 1101 0001 */
605		{DMOV,"ETM0,EA" }, /* d2: 0100 1000 1101 0010 */
606		{DMOV,"ETM1,EA" }, /* d3: 0100 1000 1101 0011 */
607		{illegal,0 }, /* d4: 0100 1000 1101 0100 */
608		{illegal,0 }, /* d5: 0100 1000 1101 0101 */
609		{illegal,0 }, /* d6: 0100 1000 1101 0110 */
610		{illegal,0 }, /* d7: 0100 1000 1101 0111 */
611		{illegal,0 }, /* d8: 0100 1000 1101 1000 */
612		{illegal,0 }, /* d9: 0100 1000 1101 1001 */
613		{illegal,0 }, /* da: 0100 1000 1101 1010 */
614		{illegal,0 }, /* db: 0100 1000 1101 1011 */
615		{illegal,0 }, /* dc: 0100 1000 1101 1100 */
616		{illegal,0 }, /* dd: 0100 1000 1101 1101 */
617		{illegal,0 }, /* de: 0100 1000 1101 1110 */
618		{illegal,0 }, /* df: 0100 1000 1101 1111 */
619
620		{illegal,0 }, /* e0: 0100 1000 1110 0000 */
621		{illegal,0 }, /* e1: 0100 1000 1110 0001 */
622		{illegal,0 }, /* e2: 0100 1000 1110 0010 */
623		{illegal,0 }, /* e3: 0100 1000 1110 0011 */
624		{illegal,0 }, /* e4: 0100 1000 1110 0100 */
625		{illegal,0 }, /* e5: 0100 1000 1110 0101 */
626		{illegal,0 }, /* e6: 0100 1000 1110 0110 */
627		{illegal,0 }, /* e7: 0100 1000 1110 0111 */
628		{illegal,0 }, /* e8: 0100 1000 1110 1000 */
629		{illegal,0 }, /* e9: 0100 1000 1110 1001 */
630		{illegal,0 }, /* ea: 0100 1000 1110 1010 */
631		{illegal,0 }, /* eb: 0100 1000 1110 1011 */
632		{illegal,0 }, /* ec: 0100 1000 1110 1100 */
633		{illegal,0 }, /* ed: 0100 1000 1110 1101 */
634		{illegal,0 }, /* ee: 0100 1000 1110 1110 */
635		{illegal,0 }, /* ef: 0100 1000 1110 1111 */
636
637		{illegal,0 }, /* f0: 0100 1000 1111 0000 */
638		{illegal,0 }, /* f1: 0100 1000 1111 0001 */
639		{illegal,0 }, /* f2: 0100 1000 1111 0010 */
640		{illegal,0 }, /* f3: 0100 1000 1111 0011 */
641		{illegal,0 }, /* f4: 0100 1000 1111 0100 */
642		{illegal,0 }, /* f5: 0100 1000 1111 0101 */
643		{illegal,0 }, /* f6: 0100 1000 1111 0110 */
644		{illegal,0 }, /* f7: 0100 1000 1111 0111 */
645		{illegal,0 }, /* f8: 0100 1000 1111 1000 */
646		{illegal,0 }, /* f9: 0100 1000 1111 1001 */
647		{illegal,0 }, /* fa: 0100 1000 1111 1010 */
648		{illegal,0 }, /* fb: 0100 1000 1111 1011 */
649		{illegal,0 }, /* fc: 0100 1000 1111 1100 */
650		{illegal,0 }, /* fd: 0100 1000 1111 1101 */
651		{illegal,0 }, /* fe: 0100 1000 1111 1110 */
652		{illegal,0 } /* ff: 0100 1000 1111 1111 */
653		};
654
655		static const struct dasm_s dasm48_7807[256] =
656		{
657		{illegal,0 }, /* 00: 0100 1000 0000 0000 */
658		{SLRC,"A" }, /* 01: 0100 1000 0000 0001 */
659		{SLRC,"B" }, /* 02: 0100 1000 0000 0010 */
660		{SLRC,"C" }, /* 03: 0100 1000 0000 0011 */
661		{illegal,0 }, /* 04: 0100 1000 0000 0100 */
662		{SLLC,"A" }, /* 05: 0100 1000 0000 0101 */
663		{SLLC,"B" }, /* 06: 0100 1000 0000 0110 */
664		{SLLC,"C" }, /* 07: 0100 1000 0000 0111 */
665		{SK,"NV" }, /* 08: 0100 1000 0000 1000 */
666		{illegal,0 }, /* 09: 0100 1000 0000 1001 */
667		{SK,"CY" }, /* 0a: 0100 1000 0000 1010 */
668		{SK,"HC" }, /* 0b: 0100 1000 0000 1011 */
669		{SK,"Z" }, /* 0c: 0100 1000 0000 1100 */
670		{illegal,0 }, /* 0d: 0100 1000 0000 1101 */
671		{illegal,0 }, /* 0e: 0100 1000 0000 1110 */
672		{illegal,0 }, /* 0f: 0100 1000 0000 1111 */
673
674		{illegal,0 }, /* 10: 0100 1000 0001 0000 */
675		{illegal,0 }, /* 11: 0100 1000 0001 0001 */
676		{illegal,0 }, /* 12: 0100 1000 0001 0010 */
677		{illegal,0 }, /* 13: 0100 1000 0001 0011 */
678		{illegal,0 }, /* 14: 0100 1000 0001 0100 */
679		{illegal,0 }, /* 15: 0100 1000 0001 0101 */
680		{illegal,0 }, /* 16: 0100 1000 0001 0110 */
681		{illegal,0 }, /* 17: 0100 1000 0001 0111 */
682		{SKN,"NV" }, /* 18: 0100 1000 0001 1000 */
683		{illegal,0 }, /* 19: 0100 1000 0001 1001 */
684		{SKN,"CY" }, /* 1a: 0100 1000 0001 1010 */
685		{SKN,"HC" }, /* 1b: 0100 1000 0001 1011 */
686		{SKN,"Z" }, /* 1c: 0100 1000 0001 1100 */
687		{illegal,0 }, /* 1d: 0100 1000 0001 1101 */
688		{illegal,0 }, /* 1e: 0100 1000 0001 1110 */
689		{illegal,0 }, /* 1f: 0100 1000 0001 1111 */
690
691		{illegal,0 }, /* 20: 0100 1000 0010 0000 */
692		{SLR,"A" }, /* 21: 0100 1000 0010 0001 */
693		{SLR,"B" }, /* 22: 0100 1000 0010 0010 */
694		{SLR,"C" }, /* 23: 0100 1000 0010 0011 */
695		{illegal,0 }, /* 24: 0100 1000 0010 0100 */
696		{SLL,"A" }, /* 25: 0100 1000 0010 0101 */
697		{SLL,"B" }, /* 26: 0100 1000 0010 0110 */
698		{SLL,"C" }, /* 27: 0100 1000 0010 0111 */
699		{JEA,0 }, /* 28: 0100 1000 0010 1000 */
700		{CALB,0 }, /* 29: 0100 1000 0010 1001 */
701		{CLC,0 }, /* 2a: 0100 1000 0010 1010 */
702		{STC,0 }, /* 2b: 0100 1000 0010 1011 */
703		{illegal,0 }, /* 2c: 0100 1000 0010 1100 */
704		{MUL,"A" }, /* 2d: 0100 1000 0010 1101 */
705		{MUL,"B" }, /* 2e: 0100 1000 0010 1110 */
706		{MUL,"C" }, /* 2f: 0100 1000 0010 1111 */
707
708		{illegal,0 }, /* 30: 0100 1000 0011 0000 */
709		{RLR,"A" }, /* 31: 0100 1000 0011 0001 */
710		{RLR,"B" }, /* 32: 0100 1000 0011 0010 */
711		{RLR,"C" }, /* 33: 0100 1000 0011 0011 */
712		{illegal,0 }, /* 34: 0100 1000 0011 0100 */
713		{RLL,"A" }, /* 35: 0100 1000 0011 0101 */
714		{RLL,"B" }, /* 36: 0100 1000 0011 0110 */
715		{RLL,"C" }, /* 37: 0100 1000 0011 0111 */
716		{RLD,0 }, /* 38: 0100 1000 0011 1000 */
717		{RRD,0 }, /* 39: 0100 1000 0011 1001 */
718		{NEGA,0 }, /* 3a: 0100 1000 0011 1010 */
719		{HALT,0 }, /* 3b: 0100 1000 0011 1011 */
720		{illegal,0 }, /* 3c: 0100 1000 0011 1100 */
721		{DIV,"A" }, /* 3d: 0100 1000 0011 1101 */
722		{DIV,"B" }, /* 3e: 0100 1000 0011 1110 */
723		{DIV,"C" }, /* 3f: 0100 1000 0011 1111 */
724
725		{SKIT,"NMI" }, /* 40: 0100 1000 0100 0000 */
726		{SKIT,"FT0" }, /* 41: 0100 1000 0100 0001 */
727		{SKIT,"FT1" }, /* 42: 0100 1000 0100 0010 */
728		{SKIT,"F1" }, /* 43: 0100 1000 0100 0011 */
729		{SKIT,"F2" }, /* 44: 0100 1000 0100 0100 */
730		{SKIT,"FE0" }, /* 45: 0100 1000 0100 0101 */
731		{SKIT,"FE1" }, /* 46: 0100 1000 0100 0110 */
732		{SKIT,"FEIN" }, /* 47: 0100 1000 0100 0111 */
733		{SKIT,"FAD" }, /* 48: 0100 1000 0100 1000 */
734		{SKIT,"FSR" }, /* 49: 0100 1000 0100 1001 */
735		{SKIT,"FST" }, /* 4a: 0100 1000 0100 1010 */
736		{SKIT,"ER" }, /* 4b: 0100 1000 0100 1011 */
737		{SKIT,"OV" }, /* 4c: 0100 1000 0100 1100 */
738		{illegal,0 }, /* 4d: 0100 1000 0100 1101 */
739		{illegal,0 }, /* 4e: 0100 1000 0100 1110 */
740		{illegal,0 }, /* 4f: 0100 1000 0100 1111 */
741
742		{SKIT,"AN4" }, /* 50: 0100 1000 0101 0000 */
743		{SKIT,"AN5" }, /* 51: 0100 1000 0101 0001 */
744		{SKIT,"AN6" }, /* 52: 0100 1000 0101 0010 */
745		{SKIT,"AN7" }, /* 53: 0100 1000 0101 0011 */
746		{SKIT,"SB" }, /* 54: 0100 1000 0101 0100 */
747		{illegal,0 }, /* 55: 0100 1000 0101 0101 */
748		{illegal,0 }, /* 56: 0100 1000 0101 0110 */
749		{illegal,0 }, /* 57: 0100 1000 0101 0111 */
750		{illegal,0 }, /* 58: 0100 1000 0101 1000 */
751		{illegal,0 }, /* 59: 0100 1000 0101 1001 */
752		{illegal,0 }, /* 5a: 0100 1000 0101 1010 */
753		{illegal,0 }, /* 5b: 0100 1000 0101 1011 */
754		{illegal,0 }, /* 5c: 0100 1000 0101 1100 */
755		{illegal,0 }, /* 5d: 0100 1000 0101 1101 */
756		{illegal,0 }, /* 5e: 0100 1000 0101 1110 */
757		{illegal,0 }, /* 5f: 0100 1000 0101 1111 */
758
759		{SKNIT,"NMI" }, /* 60: 0100 1000 0110 0000 */
760		{SKNIT,"FT0" }, /* 61: 0100 1000 0110 0001 */
761		{SKNIT,"FT1" }, /* 62: 0100 1000 0110 0010 */
762		{SKNIT,"F1" }, /* 63: 0100 1000 0110 0011 */
763		{SKNIT,"F2" }, /* 64: 0100 1000 0110 0100 */
764		{SKNIT,"FE0" }, /* 65: 0100 1000 0110 0101 */
765		{SKNIT,"FE1" }, /* 66: 0100 1000 0110 0110 */
766		{SKNIT,"FEIN" }, /* 67: 0100 1000 0110 0111 */
767		{SKNIT,"FAD" }, /* 68: 0100 1000 0110 1000 */
768		{SKNIT,"FSR" }, /* 69: 0100 1000 0110 1001 */
769		{SKNIT,"FST" }, /* 6a: 0100 1000 0110 1010 */
770		{SKNIT,"ER" }, /* 6b: 0100 1000 0110 1011 */
771		{SKNIT,"OV" }, /* 6c: 0100 1000 0110 1100 */
772		{illegal,0 }, /* 6d: 0100 1000 0110 1101 */
773		{illegal,0 }, /* 6e: 0100 1000 0110 1110 */
774		{illegal,0 }, /* 6f: 0100 1000 0110 1111 */
775
776		{SKNIT,"AN4" }, /* 70: 0100 1000 0111 0000 */
777		{SKNIT,"AN5" }, /* 71: 0100 1000 0111 0001 */
778		{SKNIT,"AN6" }, /* 72: 0100 1000 0111 0010 */
779		{SKNIT,"AN7" }, /* 73: 0100 1000 0111 0011 */
780		{SKNIT,"SB" }, /* 74: 0100 1000 0111 0100 */
781		{illegal,0 }, /* 75: 0100 1000 0111 0101 */
782		{illegal,0 }, /* 76: 0100 1000 0111 0110 */
783		{illegal,0 }, /* 77: 0100 1000 0111 0111 */
784		{illegal,0 }, /* 78: 0100 1000 0111 1000 */
785		{illegal,0 }, /* 79: 0100 1000 0111 1001 */
786		{illegal,0 }, /* 7a: 0100 1000 0111 1010 */
787		{illegal,0 }, /* 7b: 0100 1000 0111 1011 */
788		{illegal,0 }, /* 7c: 0100 1000 0111 1100 */
789		{illegal,0 }, /* 7d: 0100 1000 0111 1101 */
790		{illegal,0 }, /* 7e: 0100 1000 0111 1110 */
791		{illegal,0 }, /* 7f: 0100 1000 0111 1111 */
792
793		{illegal,0 }, /* 80: 0100 1000 1000 0000 */
794		{illegal,0 }, /* 81: 0100 1000 1000 0001 */
795		{LDEAX,"(DE)" }, /* 82: 0100 1000 1000 0010 */
796		{LDEAX,"(HL)" }, /* 83: 0100 1000 1000 0011 */
797		{LDEAX,"(DE++)" }, /* 84: 0100 1000 1000 0100 */
798		{LDEAX,"(HL++)" }, /* 85: 0100 1000 1000 0101 */
799		{illegal,0 }, /* 86: 0100 1000 1000 0110 */
800		{illegal,0 }, /* 87: 0100 1000 1000 0111 */
801		{illegal,0 }, /* 88: 0100 1000 1000 1000 */
802		{illegal,0 }, /* 89: 0100 1000 1000 1001 */
803		{illegal,0 }, /* 8a: 0100 1000 1000 1010 */
804		{LDEAX,"(DE+%b)"}, /* 8b: 0100 1000 1000 1011 xxxx xxxx */
805		{LDEAX,"(HL+A)" }, /* 8c: 0100 1000 1000 1100 */
806		{LDEAX,"(HL+B)" }, /* 8d: 0100 1000 1000 1101 */
807		{LDEAX,"(HL+EA)"}, /* 8e: 0100 1000 1000 1110 */
808		{LDEAX,"(HL+%b)"}, /* 8f: 0100 1000 1000 1111 xxxx xxxx */
809
810		{illegal,0 }, /* 90: 0100 1000 1000 0000 */
811		{illegal,0 }, /* 91: 0100 1000 1000 0001 */
812		{STEAX,"(DE)" }, /* 92: 0100 1000 1000 0010 */
813		{STEAX,"(HL)" }, /* 93: 0100 1000 1000 0011 */
814		{STEAX,"(DE++)" }, /* 94: 0100 1000 1000 0100 */
815		{STEAX,"(HL++)" }, /* 95: 0100 1000 1000 0101 */
816		{illegal,0 }, /* 96: 0100 1000 1000 0110 */
817		{illegal,0 }, /* 97: 0100 1000 1000 0111 */
818		{illegal,0 }, /* 98: 0100 1000 1000 1000 */
819		{illegal,0 }, /* 99: 0100 1000 1000 1001 */
820		{illegal,0 }, /* 9a: 0100 1000 1000 1010 */
821		{STEAX,"(DE+%b)"}, /* 9b: 0100 1000 1000 1011 xxxx xxxx */
822		{STEAX,"(HL+A)" }, /* 9c: 0100 1000 1000 1100 */
823		{STEAX,"(HL+B)" }, /* 9d: 0100 1000 1000 1101 */
824		{STEAX,"(HL+EA)"}, /* 9e: 0100 1000 1000 1110 */
825		{STEAX,"(HL+%b)"}, /* 9f: 0100 1000 1000 1111 xxxx xxxx */
826
827		{DSLR,"EA" }, /* a0: 0100 1000 1010 0000 */
828		{illegal,0 }, /* a1: 0100 1000 1010 0001 */
829		{illegal,0 }, /* a2: 0100 1000 1010 0010 */
830		{illegal,0 }, /* a3: 0100 1000 1010 0011 */
831		{DSLL,"EA" }, /* a4: 0100 1000 1010 0100 */
832		{illegal,0 }, /* a5: 0100 1000 1010 0101 */
833		{illegal,0 }, /* a6: 0100 1000 1010 0110 */
834		{illegal,0 }, /* a7: 0100 1000 1010 0111 */
835		{TABLE,0 }, /* a8: 0100 1000 1010 1000 */
836		{illegal,0 }, /* a9: 0100 1000 1010 1001 */
837		{CMC,0 }, /* aa: 0100 1000 1010 1010 / / 7807 */
838		{illegal,0 }, /* ab: 0100 1000 1010 1011 */
839		{EXA,0 }, /* ac: 0100 1000 1010 1100 / / 7807 */
840		{EXR,0 }, /* ad: 0100 1000 1010 1101 / / 7807 */
841		{EXH,0 }, /* ae: 0100 1000 1010 1110 / / 7807 */
842		{EXX,0 }, /* af: 0100 1000 1010 1111 / / 7807 */
843
844		{DRLR,"EA" }, /* b0: 0100 1000 1011 0000 */
845		{illegal,0 }, /* b1: 0100 1000 1011 0001 */
846		{illegal,0 }, /* b2: 0100 1000 1011 0010 */
847		{illegal,0 }, /* b3: 0100 1000 1011 0011 */
848		{DRLL,"EA" }, /* b4: 0100 1000 1011 0100 */
849		{illegal,0 }, /* b5: 0100 1000 1011 0101 */
850		{illegal,0 }, /* b6: 0100 1000 1011 0110 */
851		{illegal,0 }, /* b7: 0100 1000 1011 0111 */
852		{illegal,0 }, /* b8: 0100 1000 1011 1000 */
853		{illegal,0 }, /* b9: 0100 1000 1011 1001 */
854		{illegal,0 }, /* ba: 0100 1000 1011 1010 */
855		{illegal,0 }, /* bb: 0100 1000 1011 1011 */
856		{illegal,0 }, /* bc: 0100 1000 1011 1100 */
857		{illegal,0 }, /* bd: 0100 1000 1011 1101 */
858		{illegal,0 }, /* be: 0100 1000 1011 1110 */
859		{illegal,0 }, /* bf: 0100 1000 1011 1111 */
860
861		{DMOV,"EA,ECNT" }, /* c0: 0100 1000 1100 0000 */
862		{DMOV,"EA,ECPT0"}, /* c1: 0100 1000 1100 0001 / / 7807 */
863		{DMOV,"EA,ECPT1"}, /* c2: 0100 1000 1100 0010 / / 7807 */
864		{illegal,0 }, /* c3: 0100 1000 1100 0011 */
865		{illegal,0 }, /* c4: 0100 1000 1100 0100 */
866		{illegal,0 }, /* c5: 0100 1000 1100 0101 */
867		{illegal,0 }, /* c6: 0100 1000 1100 0110 */
868		{illegal,0 }, /* c7: 0100 1000 1100 0111 */
869		{illegal,0 }, /* c8: 0100 1000 1100 1000 */
870		{illegal,0 }, /* c9: 0100 1000 1100 1001 */
871		{illegal,0 }, /* ca: 0100 1000 1100 1010 */
872		{illegal,0 }, /* cb: 0100 1000 1100 1011 */
873		{illegal,0 }, /* cc: 0100 1000 1100 1100 */
874		{illegal,0 }, /* cd: 0100 1000 1100 1101 */
875		{illegal,0 }, /* ce: 0100 1000 1100 1110 */
876		{illegal,0 }, /* cf: 0100 1000 1100 1111 */
877
878		{illegal,0 }, /* d0: 0100 1000 1101 0000 */
879		{illegal,0 }, /* d1: 0100 1000 1101 0001 */
880		{DMOV,"ETM0,EA" }, /* d2: 0100 1000 1101 0010 */
881		{DMOV,"ETM1,EA" }, /* d3: 0100 1000 1101 0011 */
882		{illegal,0 }, /* d4: 0100 1000 1101 0100 */
883		{illegal,0 }, /* d5: 0100 1000 1101 0101 */
884		{illegal,0 }, /* d6: 0100 1000 1101 0110 */
885		{illegal,0 }, /* d7: 0100 1000 1101 0111 */
886		{illegal,0 }, /* d8: 0100 1000 1101 1000 */
887		{illegal,0 }, /* d9: 0100 1000 1101 1001 */
888		{illegal,0 }, /* da: 0100 1000 1101 1010 */
889		{illegal,0 }, /* db: 0100 1000 1101 1011 */
890		{illegal,0 }, /* dc: 0100 1000 1101 1100 */
891		{illegal,0 }, /* dd: 0100 1000 1101 1101 */
892		{illegal,0 }, /* de: 0100 1000 1101 1110 */
893		{illegal,0 }, /* df: 0100 1000 1101 1111 */
894
895		{illegal,0 }, /* e0: 0100 1000 1110 0000 */
896		{illegal,0 }, /* e1: 0100 1000 1110 0001 */
897		{illegal,0 }, /* e2: 0100 1000 1110 0010 */
898		{illegal,0 }, /* e3: 0100 1000 1110 0011 */
899		{illegal,0 }, /* e4: 0100 1000 1110 0100 */
900		{illegal,0 }, /* e5: 0100 1000 1110 0101 */
901		{illegal,0 }, /* e6: 0100 1000 1110 0110 */
902		{illegal,0 }, /* e7: 0100 1000 1110 0111 */
903		{illegal,0 }, /* e8: 0100 1000 1110 1000 */
904		{illegal,0 }, /* e9: 0100 1000 1110 1001 */
905		{illegal,0 }, /* ea: 0100 1000 1110 1010 */
906		{illegal,0 }, /* eb: 0100 1000 1110 1011 */
907		{illegal,0 }, /* ec: 0100 1000 1110 1100 */
908		{illegal,0 }, /* ed: 0100 1000 1110 1101 */
909		{illegal,0 }, /* ee: 0100 1000 1110 1110 */
910		{illegal,0 }, /* ef: 0100 1000 1110 1111 */
911
912		{illegal,0 }, /* f0: 0100 1000 1111 0000 */
913		{illegal,0 }, /* f1: 0100 1000 1111 0001 */
914		{illegal,0 }, /* f2: 0100 1000 1111 0010 */
915		{illegal,0 }, /* f3: 0100 1000 1111 0011 */
916		{illegal,0 }, /* f4: 0100 1000 1111 0100 */
917		{illegal,0 }, /* f5: 0100 1000 1111 0101 */
918		{illegal,0 }, /* f6: 0100 1000 1111 0110 */
919		{illegal,0 }, /* f7: 0100 1000 1111 0111 */
920		{illegal,0 }, /* f8: 0100 1000 1111 1000 */
921		{illegal,0 }, /* f9: 0100 1000 1111 1001 */
922		{illegal,0 }, /* fa: 0100 1000 1111 1010 */
923		{illegal,0 }, /* fb: 0100 1000 1111 1011 */
924		{illegal,0 }, /* fc: 0100 1000 1111 1100 */
925		{illegal,0 }, /* fd: 0100 1000 1111 1101 */
926		{illegal,0 }, /* fe: 0100 1000 1111 1110 */
927		{illegal,0 } /* ff: 0100 1000 1111 1111 */
928		};
929
930		/* prefix 4C */
931		static const struct dasm_s dasm4C_7810[256] =
932		{
933		{illegal,0 }, /* 00: 0100 1100 0000 0000 */
934		{illegal,0 }, /* 01: 0100 1100 0000 0001 */
935		{illegal,0 }, /* 02: 0100 1100 0000 0010 */
936		{illegal,0 }, /* 03: 0100 1100 0000 0011 */
937		{illegal,0 }, /* 04: 0100 1100 0000 0100 */
938		{illegal,0 }, /* 05: 0100 1100 0000 0101 */
939		{illegal,0 }, /* 06: 0100 1100 0000 0110 */
940		{illegal,0 }, /* 07: 0100 1100 0000 0111 */
941		{illegal,0 }, /* 08: 0100 1100 0000 1000 */
942		{illegal,0 }, /* 09: 0100 1100 0000 1001 */
943		{illegal,0 }, /* 0a: 0100 1100 0000 1010 */
944		{illegal,0 }, /* 0b: 0100 1100 0000 1011 */
945		{illegal,0 }, /* 0c: 0100 1100 0000 1100 */
946		{illegal,0 }, /* 0d: 0100 1100 0000 1101 */
947		{illegal,0 }, /* 0e: 0100 1100 0000 1110 */
948		{illegal,0 }, /* 0f: 0100 1100 0000 1111 */
949
950		{illegal,0 }, /* 10: 0100 1100 0001 0000 */
951		{illegal,0 }, /* 11: 0100 1100 0001 0001 */
952		{illegal,0 }, /* 12: 0100 1100 0001 0010 */
953		{illegal,0 }, /* 13: 0100 1100 0001 0011 */
954		{illegal,0 }, /* 14: 0100 1100 0001 0100 */
955		{illegal,0 }, /* 15: 0100 1100 0001 0101 */
956		{illegal,0 }, /* 16: 0100 1100 0001 0110 */
957		{illegal,0 }, /* 17: 0100 1100 0001 0111 */
958		{illegal,0 }, /* 18: 0100 1100 0001 1000 */
959		{illegal,0 }, /* 19: 0100 1100 0001 1001 */
960		{illegal,0 }, /* 1a: 0100 1100 0001 1010 */
961		{illegal,0 }, /* 1b: 0100 1100 0001 1011 */
962		{illegal,0 }, /* 1c: 0100 1100 0001 1100 */
963		{illegal,0 }, /* 1d: 0100 1100 0001 1101 */
964		{illegal,0 }, /* 1e: 0100 1100 0001 1110 */
965		{illegal,0 }, /* 1f: 0100 1100 0001 1111 */
966
967		{illegal,0 }, /* 20: 0100 1100 0010 0000 */
968		{illegal,0 }, /* 21: 0100 1100 0010 0001 */
969		{illegal,0 }, /* 22: 0100 1100 0010 0010 */
970		{illegal,0 }, /* 23: 0100 1100 0010 0011 */
971		{illegal,0 }, /* 24: 0100 1100 0010 0100 */
972		{illegal,0 }, /* 25: 0100 1100 0010 0101 */
973		{illegal,0 }, /* 26: 0100 1100 0010 0110 */
974		{illegal,0 }, /* 27: 0100 1100 0010 0111 */
975		{illegal,0 }, /* 28: 0100 1100 0010 1000 */
976		{illegal,0 }, /* 29: 0100 1100 0010 1001 */
977		{illegal,0 }, /* 2a: 0100 1100 0010 1010 */
978		{illegal,0 }, /* 2b: 0100 1100 0010 1011 */
979		{illegal,0 }, /* 2c: 0100 1100 0010 1100 */
980		{illegal,0 }, /* 2d: 0100 1100 0010 1101 */
981		{illegal,0 }, /* 2e: 0100 1100 0010 1110 */
982		{illegal,0 }, /* 2f: 0100 1100 0010 1111 */
983
984		{illegal,0 }, /* 30: 0100 1100 0011 0000 */
985		{illegal,0 }, /* 31: 0100 1100 0011 0001 */
986		{illegal,0 }, /* 32: 0100 1100 0011 0010 */
987		{illegal,0 }, /* 33: 0100 1100 0011 0011 */
988		{illegal,0 }, /* 34: 0100 1100 0011 0100 */
989		{illegal,0 }, /* 35: 0100 1100 0011 0101 */
990		{illegal,0 }, /* 36: 0100 1100 0011 0110 */
991		{illegal,0 }, /* 37: 0100 1100 0011 0111 */
992		{illegal,0 }, /* 38: 0100 1100 0011 1000 */
993		{illegal,0 }, /* 39: 0100 1100 0011 1001 */
994		{illegal,0 }, /* 3a: 0100 1100 0011 1010 */
995		{illegal,0 }, /* 3b: 0100 1100 0011 1011 */
996		{illegal,0 }, /* 3c: 0100 1100 0011 1100 */
997		{illegal,0 }, /* 3d: 0100 1100 0011 1101 */
998		{illegal,0 }, /* 3e: 0100 1100 0011 1110 */
999		{illegal,0 }, /* 3f: 0100 1100 0011 1111 */
1000
1001		{illegal,0 }, /* 40: 0100 1100 0100 0000 */
1002		{illegal,0 }, /* 41: 0100 1100 0100 0001 */
1003		{illegal,0 }, /* 42: 0100 1100 0100 0010 */
1004		{illegal,0 }, /* 43: 0100 1100 0100 0011 */
1005		{illegal,0 }, /* 44: 0100 1100 0100 0100 */
1006		{illegal,0 }, /* 45: 0100 1100 0100 0101 */
1007		{illegal,0 }, /* 46: 0100 1100 0100 0110 */
1008		{illegal,0 }, /* 47: 0100 1100 0100 0111 */
1009		{illegal,0 }, /* 48: 0100 1100 0100 1000 */
1010		{illegal,0 }, /* 49: 0100 1100 0100 1001 */
1011		{illegal,0 }, /* 4a: 0100 1100 0100 1010 */
1012		{illegal,0 }, /* 4b: 0100 1100 0100 1011 */
1013		{illegal,0 }, /* 4c: 0100 1100 0100 1100 */
1014		{illegal,0 }, /* 4d: 0100 1100 0100 1101 */
1015		{illegal,0 }, /* 4e: 0100 1100 0100 1110 */
1016		{illegal,0 }, /* 4f: 0100 1100 0100 1111 */
1017
1018		{illegal,0 }, /* 50: 0100 1100 0101 0000 */
1019		{illegal,0 }, /* 51: 0100 1100 0101 0001 */
1020		{illegal,0 }, /* 52: 0100 1100 0101 0010 */
1021		{illegal,0 }, /* 53: 0100 1100 0101 0011 */
1022		{illegal,0 }, /* 54: 0100 1100 0101 0100 */
1023		{illegal,0 }, /* 55: 0100 1100 0101 0101 */
1024		{illegal,0 }, /* 56: 0100 1100 0101 0110 */
1025		{illegal,0 }, /* 57: 0100 1100 0101 0111 */
1026		{illegal,0 }, /* 58: 0100 1100 0101 1000 */
1027		{illegal,0 }, /* 59: 0100 1100 0101 1001 */
1028		{illegal,0 }, /* 5a: 0100 1100 0101 1010 */
1029		{illegal,0 }, /* 5b: 0100 1100 0101 1011 */
1030		{illegal,0 }, /* 5c: 0100 1100 0101 1100 */
1031		{illegal,0 }, /* 5d: 0100 1100 0101 1101 */
1032		{illegal,0 }, /* 5e: 0100 1100 0101 1110 */
1033		{illegal,0 }, /* 5f: 0100 1100 0101 1111 */
1034
1035		{illegal,0 }, /* 60: 0100 1100 0110 0000 */
1036		{illegal,0 }, /* 61: 0100 1100 0110 0001 */
1037		{illegal,0 }, /* 62: 0100 1100 0110 0010 */
1038		{illegal,0 }, /* 63: 0100 1100 0110 0011 */
1039		{illegal,0 }, /* 64: 0100 1100 0110 0100 */
1040		{illegal,0 }, /* 65: 0100 1100 0110 0101 */
1041		{illegal,0 }, /* 66: 0100 1100 0110 0110 */
1042		{illegal,0 }, /* 67: 0100 1100 0110 0111 */
1043		{illegal,0 }, /* 68: 0100 1100 0110 1000 */
1044		{illegal,0 }, /* 69: 0100 1100 0110 1001 */
1045		{illegal,0 }, /* 6a: 0100 1100 0110 1010 */
1046		{illegal,0 }, /* 6b: 0100 1100 0110 1011 */
1047		{illegal,0 }, /* 6c: 0100 1100 0110 1100 */
1048		{illegal,0 }, /* 6d: 0100 1100 0110 1101 */
1049		{illegal,0 }, /* 6e: 0100 1100 0110 1110 */
1050		{illegal,0 }, /* 6f: 0100 1100 0110 1111 */
1051
1052		{illegal,0 }, /* 70: 0100 1100 0111 0000 */
1053		{illegal,0 }, /* 71: 0100 1100 0111 0001 */
1054		{illegal,0 }, /* 72: 0100 1100 0111 0010 */
1055		{illegal,0 }, /* 73: 0100 1100 0111 0011 */
1056		{illegal,0 }, /* 74: 0100 1100 0111 0100 */
1057		{illegal,0 }, /* 75: 0100 1100 0111 0101 */
1058		{illegal,0 }, /* 76: 0100 1100 0111 0110 */
1059		{illegal,0 }, /* 77: 0100 1100 0111 0111 */
1060		{illegal,0 }, /* 78: 0100 1100 0111 1000 */
1061		{illegal,0 }, /* 79: 0100 1100 0111 1001 */
1062		{illegal,0 }, /* 7a: 0100 1100 0111 1010 */
1063		{illegal,0 }, /* 7b: 0100 1100 0111 1011 */
1064		{illegal,0 }, /* 7c: 0100 1100 0111 1100 */
1065		{illegal,0 }, /* 7d: 0100 1100 0111 1101 */
1066		{illegal,0 }, /* 7e: 0100 1100 0111 1110 */
1067		{illegal,0 }, /* 7f: 0100 1100 0111 1111 */
1068
1069		{illegal,0 }, /* 80: 0100 1100 1000 0000 */
1070		{illegal,0 }, /* 81: 0100 1100 1000 0001 */
1071		{illegal,0 }, /* 82: 0100 1100 1000 0010 */
1072		{illegal,0 }, /* 83: 0100 1100 1000 0011 */
1073		{illegal,0 }, /* 84: 0100 1100 1000 0100 */
1074		{illegal,0 }, /* 85: 0100 1100 1000 0101 */
1075		{illegal,0 }, /* 86: 0100 1100 1000 0110 */
1076		{illegal,0 }, /* 87: 0100 1100 1000 0111 */
1077		{illegal,0 }, /* 88: 0100 1100 1000 1000 */
1078		{illegal,0 }, /* 89: 0100 1100 1000 1001 */
1079		{illegal,0 }, /* 8a: 0100 1100 1000 1010 */
1080		{illegal,0 }, /* 8b: 0100 1100 1000 1011 */
1081		{illegal,0 }, /* 8c: 0100 1100 1000 1100 */
1082		{illegal,0 }, /* 8d: 0100 1100 1000 1101 */
1083		{illegal,0 }, /* 8e: 0100 1100 1000 1110 */
1084		{illegal,0 }, /* 8f: 0100 1100 1000 1111 */
1085
1086		{illegal,0 }, /* 90: 0100 1100 1001 0000 */
1087		{illegal,0 }, /* 91: 0100 1100 1001 0001 */
1088		{illegal,0 }, /* 92: 0100 1100 1001 0010 */
1089		{illegal,0 }, /* 93: 0100 1100 1001 0011 */
1090		{illegal,0 }, /* 94: 0100 1100 1001 0100 */
1091		{illegal,0 }, /* 95: 0100 1100 1001 0101 */
1092		{illegal,0 }, /* 96: 0100 1100 1001 0110 */
1093		{illegal,0 }, /* 97: 0100 1100 1001 0111 */
1094		{illegal,0 }, /* 98: 0100 1100 1001 1000 */
1095		{illegal,0 }, /* 99: 0100 1100 1001 1001 */
1096		{illegal,0 }, /* 9a: 0100 1100 1001 1010 */
1097		{illegal,0 }, /* 9b: 0100 1100 1001 1011 */
1098		{illegal,0 }, /* 9c: 0100 1100 1001 1100 */
1099		{illegal,0 }, /* 9d: 0100 1100 1001 1101 */
1100		{illegal,0 }, /* 9e: 0100 1100 1001 1110 */
1101		{illegal,0 }, /* 9f: 0100 1100 1001 1111 */
1102
1103		{illegal,0 }, /* a0: 0100 1100 1010 0000 */
1104		{illegal,0 }, /* a1: 0100 1100 1010 0001 */
1105		{illegal,0 }, /* a2: 0100 1100 1010 0010 */
1106		{illegal,0 }, /* a3: 0100 1100 1010 0011 */
1107		{illegal,0 }, /* a4: 0100 1100 1010 0100 */
1108		{illegal,0 }, /* a5: 0100 1100 1010 0101 */
1109		{illegal,0 }, /* a6: 0100 1100 1010 0110 */
1110		{illegal,0 }, /* a7: 0100 1100 1010 0111 */
1111		{illegal,0 }, /* a8: 0100 1100 1010 1000 */
1112		{illegal,0 }, /* a9: 0100 1100 1010 1001 */
1113		{illegal,0 }, /* aa: 0100 1100 1010 1010 */
1114		{illegal,0 }, /* ab: 0100 1100 1010 1011 */
1115		{illegal,0 }, /* ac: 0100 1100 1010 1100 */
1116		{illegal,0 }, /* ad: 0100 1100 1010 1101 */
1117		{illegal,0 }, /* ae: 0100 1100 1010 1110 */
1118		{illegal,0 }, /* af: 0100 1100 1010 1111 */
1119
1120		{illegal,0 }, /* b0: 0100 1100 1011 0000 */
1121		{illegal,0 }, /* b1: 0100 1100 1011 0001 */
1122		{illegal,0 }, /* b2: 0100 1100 1011 0010 */
1123		{illegal,0 }, /* b3: 0100 1100 1011 0011 */
1124		{illegal,0 }, /* b4: 0100 1100 1011 0100 */
1125		{illegal,0 }, /* b5: 0100 1100 1011 0101 */
1126		{illegal,0 }, /* b6: 0100 1100 1011 0110 */
1127		{illegal,0 }, /* b7: 0100 1100 1011 0111 */
1128		{illegal,0 }, /* b8: 0100 1100 1011 1000 */
1129		{illegal,0 }, /* b9: 0100 1100 1011 1001 */
1130		{illegal,0 }, /* ba: 0100 1100 1011 1010 */
1131		{illegal,0 }, /* bb: 0100 1100 1011 1011 */
1132		{illegal,0 }, /* bc: 0100 1100 1011 1100 */
1133		{illegal,0 }, /* bd: 0100 1100 1011 1101 */
1134		{illegal,0 }, /* be: 0100 1100 1011 1110 */
1135		{illegal,0 }, /* bf: 0100 1100 1011 1111 */
1136
1137		{MOV,"A,PA" }, /* c0: 0100 1100 1100 0000 */
1138		{MOV,"A,PB" }, /* c1: 0100 1100 1100 0001 */
1139		{MOV,"A,PC" }, /* c2: 0100 1100 1100 0010 */
1140		{MOV,"A,PD" }, /* c3: 0100 1100 1100 0011 */
1141		{illegal,0 }, /* c4: 0100 1100 1100 0100 */
1142		{MOV,"A,PF" }, /* c5: 0100 1100 1100 0101 */
1143		{MOV,"A,MKH" }, /* c6: 0100 1100 1100 0110 */
1144		{MOV,"A,MKL" }, /* c7: 0100 1100 1100 0111 */
1145		{MOV,"A,ANM" }, /* c8: 0100 1100 1100 1000 / / 7810 */
1146		{MOV,"A,SMH" }, /* c9: 0100 1100 1100 1001 */
1147		{illegal,0 }, /* ca: 0100 1100 1100 1010 */
1148		{MOV,"A,EOM" }, /* cb: 0100 1100 1100 1011 */
1149		{illegal,0 }, /* cc: 0100 1100 1100 1100 */
1150		{MOV,"A,TMM" }, /* cd: 0100 1100 1100 1101 */
1151		{illegal,0 }, /* ce: 0100 1100 1100 1110 */
1152		{illegal,0 }, /* cf: 0100 1100 1100 1111 */
1153
1154		{illegal,0 }, /* d0: 0100 1100 1101 0000 */
1155		{illegal,0 }, /* d1: 0100 1100 1101 0001 */
1156		{illegal,0 }, /* d2: 0100 1100 1101 0010 */
1157		{illegal,0 }, /* d3: 0100 1100 1101 0011 */
1158		{illegal,0 }, /* d4: 0100 1100 1101 0100 */
1159		{illegal,0 }, /* d5: 0100 1100 1101 0101 */
1160		{illegal,0 }, /* d6: 0100 1100 1101 0110 */
1161		{illegal,0 }, /* d7: 0100 1100 1101 0111 */
1162		{illegal,0 }, /* d8: 0100 1100 1101 1000 */
1163		{MOV,"A,RXB" }, /* d9: 0100 1100 1101 1001 */
1164		{illegal,0 }, /* da: 0100 1100 1101 1010 */
1165		{illegal,0 }, /* db: 0100 1100 1101 1011 */
1166		{illegal,0 }, /* dc: 0100 1100 1101 1100 */
1167		{illegal,0 }, /* dd: 0100 1100 1101 1101 */
1168		{illegal,0 }, /* de: 0100 1100 1101 1110 */
1169		{illegal,0 }, /* df: 0100 1100 1101 1111 */
1170
1171		{MOV,"A,CR0" }, /* e0: 0100 1100 1110 0000 / / 7810 */
1172		{MOV,"A,CR1" }, /* e1: 0100 1100 1110 0001 / / 7810 */
1173		{MOV,"A,CR2" }, /* e2: 0100 1100 1110 0010 / / 7810 */
1174		{MOV,"A,CR3" }, /* e3: 0100 1100 1110 0011 / / 7810 */
1175		{illegal,0 }, /* e4: 0100 1100 1110 0100 */
1176		{illegal,0 }, /* e5: 0100 1100 1110 0101 */
1177		{illegal,0 }, /* e6: 0100 1100 1110 0110 */
1178		{illegal,0 }, /* e7: 0100 1100 1110 0111 */
1179		{illegal,0 }, /* e8: 0100 1100 1110 1000 */
1180		{illegal,0 }, /* e9: 0100 1100 1110 1001 */
1181		{illegal,0 }, /* ea: 0100 1100 1110 1010 */
1182		{illegal,0 }, /* eb: 0100 1100 1110 1011 */
1183		{illegal,0 }, /* ec: 0100 1100 1110 1100 */
1184		{illegal,0 }, /* ed: 0100 1100 1110 1101 */
1185		{illegal,0 }, /* ee: 0100 1100 1110 1110 */
1186		{illegal,0 }, /* ef: 0100 1100 1110 1111 */
1187
1188		{illegal,0 }, /* f0: 0100 1100 1111 0000 */
1189		{illegal,0 }, /* f1: 0100 1100 1111 0001 */
1190		{illegal,0 }, /* f2: 0100 1100 1111 0010 */
1191		{illegal,0 }, /* f3: 0100 1100 1111 0011 */
1192		{illegal,0 }, /* f4: 0100 1100 1111 0100 */
1193		{illegal,0 }, /* f5: 0100 1100 1111 0101 */
1194		{illegal,0 }, /* f6: 0100 1100 1111 0110 */
1195		{illegal,0 }, /* f7: 0100 1100 1111 0111 */
1196		{illegal,0 }, /* f8: 0100 1100 1111 1000 */
1197		{illegal,0 }, /* f9: 0100 1100 1111 1001 */
1198		{illegal,0 }, /* fa: 0100 1100 1111 1010 */
1199		{illegal,0 }, /* fb: 0100 1100 1111 1011 */
1200		{illegal,0 }, /* fc: 0100 1100 1111 1100 */
1201		{illegal,0 }, /* fd: 0100 1100 1111 1101 */
1202		{illegal,0 }, /* fe: 0100 1100 1111 1110 */
1203		{illegal,0 } /* ff: 0100 1100 1111 1111 */
1204		};
1205
1206		static const struct dasm_s dasm4C_7807[256] =
1207		{
1208		{illegal,0 }, /* 00: 0100 1100 0000 0000 */
1209		{illegal,0 }, /* 01: 0100 1100 0000 0001 */
1210		{illegal,0 }, /* 02: 0100 1100 0000 0010 */
1211		{illegal,0 }, /* 03: 0100 1100 0000 0011 */
1212		{illegal,0 }, /* 04: 0100 1100 0000 0100 */
1213		{illegal,0 }, /* 05: 0100 1100 0000 0101 */
1214		{illegal,0 }, /* 06: 0100 1100 0000 0110 */
1215		{illegal,0 }, /* 07: 0100 1100 0000 0111 */
1216		{illegal,0 }, /* 08: 0100 1100 0000 1000 */
1217		{illegal,0 }, /* 09: 0100 1100 0000 1001 */
1218		{illegal,0 }, /* 0a: 0100 1100 0000 1010 */
1219		{illegal,0 }, /* 0b: 0100 1100 0000 1011 */
1220		{illegal,0 }, /* 0c: 0100 1100 0000 1100 */
1221		{illegal,0 }, /* 0d: 0100 1100 0000 1101 */
1222		{illegal,0 }, /* 0e: 0100 1100 0000 1110 */
1223		{illegal,0 }, /* 0f: 0100 1100 0000 1111 */
1224
1225		{illegal,0 }, /* 10: 0100 1100 0001 0000 */
1226		{illegal,0 }, /* 11: 0100 1100 0001 0001 */
1227		{illegal,0 }, /* 12: 0100 1100 0001 0010 */
1228		{illegal,0 }, /* 13: 0100 1100 0001 0011 */
1229		{illegal,0 }, /* 14: 0100 1100 0001 0100 */
1230		{illegal,0 }, /* 15: 0100 1100 0001 0101 */
1231		{illegal,0 }, /* 16: 0100 1100 0001 0110 */
1232		{illegal,0 }, /* 17: 0100 1100 0001 0111 */
1233		{illegal,0 }, /* 18: 0100 1100 0001 1000 */
1234		{illegal,0 }, /* 19: 0100 1100 0001 1001 */
1235		{illegal,0 }, /* 1a: 0100 1100 0001 1010 */
1236		{illegal,0 }, /* 1b: 0100 1100 0001 1011 */
1237		{illegal,0 }, /* 1c: 0100 1100 0001 1100 */
1238		{illegal,0 }, /* 1d: 0100 1100 0001 1101 */
1239		{illegal,0 }, /* 1e: 0100 1100 0001 1110 */
1240		{illegal,0 }, /* 1f: 0100 1100 0001 1111 */
1241
1242		{illegal,0 }, /* 20: 0100 1100 0010 0000 */
1243		{illegal,0 }, /* 21: 0100 1100 0010 0001 */
1244		{illegal,0 }, /* 22: 0100 1100 0010 0010 */
1245		{illegal,0 }, /* 23: 0100 1100 0010 0011 */
1246		{illegal,0 }, /* 24: 0100 1100 0010 0100 */
1247		{illegal,0 }, /* 25: 0100 1100 0010 0101 */
1248		{illegal,0 }, /* 26: 0100 1100 0010 0110 */
1249		{illegal,0 }, /* 27: 0100 1100 0010 0111 */
1250		{illegal,0 }, /* 28: 0100 1100 0010 1000 */
1251		{illegal,0 }, /* 29: 0100 1100 0010 1001 */
1252		{illegal,0 }, /* 2a: 0100 1100 0010 1010 */
1253		{illegal,0 }, /* 2b: 0100 1100 0010 1011 */
1254		{illegal,0 }, /* 2c: 0100 1100 0010 1100 */
1255		{illegal,0 }, /* 2d: 0100 1100 0010 1101 */
1256		{illegal,0 }, /* 2e: 0100 1100 0010 1110 */
1257		{illegal,0 }, /* 2f: 0100 1100 0010 1111 */
1258
1259		{illegal,0 }, /* 30: 0100 1100 0011 0000 */
1260		{illegal,0 }, /* 31: 0100 1100 0011 0001 */
1261		{illegal,0 }, /* 32: 0100 1100 0011 0010 */
1262		{illegal,0 }, /* 33: 0100 1100 0011 0011 */
1263		{illegal,0 }, /* 34: 0100 1100 0011 0100 */
1264		{illegal,0 }, /* 35: 0100 1100 0011 0101 */
1265		{illegal,0 }, /* 36: 0100 1100 0011 0110 */
1266		{illegal,0 }, /* 37: 0100 1100 0011 0111 */
1267		{illegal,0 }, /* 38: 0100 1100 0011 1000 */
1268		{illegal,0 }, /* 39: 0100 1100 0011 1001 */
1269		{illegal,0 }, /* 3a: 0100 1100 0011 1010 */
1270		{illegal,0 }, /* 3b: 0100 1100 0011 1011 */
1271		{illegal,0 }, /* 3c: 0100 1100 0011 1100 */
1272		{illegal,0 }, /* 3d: 0100 1100 0011 1101 */
1273		{illegal,0 }, /* 3e: 0100 1100 0011 1110 */
1274		{illegal,0 }, /* 3f: 0100 1100 0011 1111 */
1275
1276		{illegal,0 }, /* 40: 0100 1100 0100 0000 */
1277		{illegal,0 }, /* 41: 0100 1100 0100 0001 */
1278		{illegal,0 }, /* 42: 0100 1100 0100 0010 */
1279		{illegal,0 }, /* 43: 0100 1100 0100 0011 */
1280		{illegal,0 }, /* 44: 0100 1100 0100 0100 */
1281		{illegal,0 }, /* 45: 0100 1100 0100 0101 */
1282		{illegal,0 }, /* 46: 0100 1100 0100 0110 */
1283		{illegal,0 }, /* 47: 0100 1100 0100 0111 */
1284		{illegal,0 }, /* 48: 0100 1100 0100 1000 */
1285		{illegal,0 }, /* 49: 0100 1100 0100 1001 */
1286		{illegal,0 }, /* 4a: 0100 1100 0100 1010 */
1287		{illegal,0 }, /* 4b: 0100 1100 0100 1011 */
1288		{illegal,0 }, /* 4c: 0100 1100 0100 1100 */
1289		{illegal,0 }, /* 4d: 0100 1100 0100 1101 */
1290		{illegal,0 }, /* 4e: 0100 1100 0100 1110 */
1291		{illegal,0 }, /* 4f: 0100 1100 0100 1111 */
1292
1293		{illegal,0 }, /* 50: 0100 1100 0101 0000 */
1294		{illegal,0 }, /* 51: 0100 1100 0101 0001 */
1295		{illegal,0 }, /* 52: 0100 1100 0101 0010 */
1296		{illegal,0 }, /* 53: 0100 1100 0101 0011 */
1297		{illegal,0 }, /* 54: 0100 1100 0101 0100 */
1298		{illegal,0 }, /* 55: 0100 1100 0101 0101 */
1299		{illegal,0 }, /* 56: 0100 1100 0101 0110 */
1300		{illegal,0 }, /* 57: 0100 1100 0101 0111 */
1301		{illegal,0 }, /* 58: 0100 1100 0101 1000 */
1302		{illegal,0 }, /* 59: 0100 1100 0101 1001 */
1303		{illegal,0 }, /* 5a: 0100 1100 0101 1010 */
1304		{illegal,0 }, /* 5b: 0100 1100 0101 1011 */
1305		{illegal,0 }, /* 5c: 0100 1100 0101 1100 */
1306		{illegal,0 }, /* 5d: 0100 1100 0101 1101 */
1307		{illegal,0 }, /* 5e: 0100 1100 0101 1110 */
1308		{illegal,0 }, /* 5f: 0100 1100 0101 1111 */
1309
1310		{illegal,0 }, /* 60: 0100 1100 0110 0000 */
1311		{illegal,0 }, /* 61: 0100 1100 0110 0001 */
1312		{illegal,0 }, /* 62: 0100 1100 0110 0010 */
1313		{illegal,0 }, /* 63: 0100 1100 0110 0011 */
1314		{illegal,0 }, /* 64: 0100 1100 0110 0100 */
1315		{illegal,0 }, /* 65: 0100 1100 0110 0101 */
1316		{illegal,0 }, /* 66: 0100 1100 0110 0110 */
1317		{illegal,0 }, /* 67: 0100 1100 0110 0111 */
1318		{illegal,0 }, /* 68: 0100 1100 0110 1000 */
1319		{illegal,0 }, /* 69: 0100 1100 0110 1001 */
1320		{illegal,0 }, /* 6a: 0100 1100 0110 1010 */
1321		{illegal,0 }, /* 6b: 0100 1100 0110 1011 */
1322		{illegal,0 }, /* 6c: 0100 1100 0110 1100 */
1323		{illegal,0 }, /* 6d: 0100 1100 0110 1101 */
1324		{illegal,0 }, /* 6e: 0100 1100 0110 1110 */
1325		{illegal,0 }, /* 6f: 0100 1100 0110 1111 */
1326
1327		{illegal,0 }, /* 70: 0100 1100 0111 0000 */
1328		{illegal,0 }, /* 71: 0100 1100 0111 0001 */
1329		{illegal,0 }, /* 72: 0100 1100 0111 0010 */
1330		{illegal,0 }, /* 73: 0100 1100 0111 0011 */
1331		{illegal,0 }, /* 74: 0100 1100 0111 0100 */
1332		{illegal,0 }, /* 75: 0100 1100 0111 0101 */
1333		{illegal,0 }, /* 76: 0100 1100 0111 0110 */
1334		{illegal,0 }, /* 77: 0100 1100 0111 0111 */
1335		{illegal,0 }, /* 78: 0100 1100 0111 1000 */
1336		{illegal,0 }, /* 79: 0100 1100 0111 1001 */
1337		{illegal,0 }, /* 7a: 0100 1100 0111 1010 */
1338		{illegal,0 }, /* 7b: 0100 1100 0111 1011 */
1339		{illegal,0 }, /* 7c: 0100 1100 0111 1100 */
1340		{illegal,0 }, /* 7d: 0100 1100 0111 1101 */
1341		{illegal,0 }, /* 7e: 0100 1100 0111 1110 */
1342		{illegal,0 }, /* 7f: 0100 1100 0111 1111 */
1343
1344		{illegal,0 }, /* 80: 0100 1100 1000 0000 */
1345		{illegal,0 }, /* 81: 0100 1100 1000 0001 */
1346		{illegal,0 }, /* 82: 0100 1100 1000 0010 */
1347		{illegal,0 }, /* 83: 0100 1100 1000 0011 */
1348		{illegal,0 }, /* 84: 0100 1100 1000 0100 */
1349		{illegal,0 }, /* 85: 0100 1100 1000 0101 */
1350		{illegal,0 }, /* 86: 0100 1100 1000 0110 */
1351		{illegal,0 }, /* 87: 0100 1100 1000 0111 */
1352		{illegal,0 }, /* 88: 0100 1100 1000 1000 */
1353		{illegal,0 }, /* 89: 0100 1100 1000 1001 */
1354		{illegal,0 }, /* 8a: 0100 1100 1000 1010 */
1355		{illegal,0 }, /* 8b: 0100 1100 1000 1011 */
1356		{illegal,0 }, /* 8c: 0100 1100 1000 1100 */
1357		{illegal,0 }, /* 8d: 0100 1100 1000 1101 */
1358		{illegal,0 }, /* 8e: 0100 1100 1000 1110 */
1359		{illegal,0 }, /* 8f: 0100 1100 1000 1111 */
1360
1361		{illegal,0 }, /* 90: 0100 1100 1001 0000 */
1362		{illegal,0 }, /* 91: 0100 1100 1001 0001 */
1363		{illegal,0 }, /* 92: 0100 1100 1001 0010 */
1364		{illegal,0 }, /* 93: 0100 1100 1001 0011 */
1365		{illegal,0 }, /* 94: 0100 1100 1001 0100 */
1366		{illegal,0 }, /* 95: 0100 1100 1001 0101 */
1367		{illegal,0 }, /* 96: 0100 1100 1001 0110 */
1368		{illegal,0 }, /* 97: 0100 1100 1001 0111 */
1369		{illegal,0 }, /* 98: 0100 1100 1001 1000 */
1370		{illegal,0 }, /* 99: 0100 1100 1001 1001 */
1371		{illegal,0 }, /* 9a: 0100 1100 1001 1010 */
1372		{illegal,0 }, /* 9b: 0100 1100 1001 1011 */
1373		{illegal,0 }, /* 9c: 0100 1100 1001 1100 */
1374		{illegal,0 }, /* 9d: 0100 1100 1001 1101 */
1375		{illegal,0 }, /* 9e: 0100 1100 1001 1110 */
1376		{illegal,0 }, /* 9f: 0100 1100 1001 1111 */
1377
1378		{illegal,0 }, /* a0: 0100 1100 1010 0000 */
1379		{illegal,0 }, /* a1: 0100 1100 1010 0001 */
1380		{illegal,0 }, /* a2: 0100 1100 1010 0010 */
1381		{illegal,0 }, /* a3: 0100 1100 1010 0011 */
1382		{illegal,0 }, /* a4: 0100 1100 1010 0100 */
1383		{illegal,0 }, /* a5: 0100 1100 1010 0101 */
1384		{illegal,0 }, /* a6: 0100 1100 1010 0110 */
1385		{illegal,0 }, /* a7: 0100 1100 1010 0111 */
1386		{illegal,0 }, /* a8: 0100 1100 1010 1000 */
1387		{illegal,0 }, /* a9: 0100 1100 1010 1001 */
1388		{illegal,0 }, /* aa: 0100 1100 1010 1010 */
1389		{illegal,0 }, /* ab: 0100 1100 1010 1011 */
1390		{illegal,0 }, /* ac: 0100 1100 1010 1100 */
1391		{illegal,0 }, /* ad: 0100 1100 1010 1101 */
1392		{illegal,0 }, /* ae: 0100 1100 1010 1110 */
1393		{illegal,0 }, /* af: 0100 1100 1010 1111 */
1394
1395		{illegal,0 }, /* b0: 0100 1100 1011 0000 */
1396		{illegal,0 }, /* b1: 0100 1100 1011 0001 */
1397		{illegal,0 }, /* b2: 0100 1100 1011 0010 */
1398		{illegal,0 }, /* b3: 0100 1100 1011 0011 */
1399		{illegal,0 }, /* b4: 0100 1100 1011 0100 */
1400		{illegal,0 }, /* b5: 0100 1100 1011 0101 */
1401		{illegal,0 }, /* b6: 0100 1100 1011 0110 */
1402		{illegal,0 }, /* b7: 0100 1100 1011 0111 */
1403		{illegal,0 }, /* b8: 0100 1100 1011 1000 */
1404		{illegal,0 }, /* b9: 0100 1100 1011 1001 */
1405		{illegal,0 }, /* ba: 0100 1100 1011 1010 */
1406		{illegal,0 }, /* bb: 0100 1100 1011 1011 */
1407		{illegal,0 }, /* bc: 0100 1100 1011 1100 */
1408		{illegal,0 }, /* bd: 0100 1100 1011 1101 */
1409		{illegal,0 }, /* be: 0100 1100 1011 1110 */
1410		{illegal,0 }, /* bf: 0100 1100 1011 1111 */
1411
1412		{MOV,"A,PA" }, /* c0: 0100 1100 1100 0000 */
1413		{MOV,"A,PB" }, /* c1: 0100 1100 1100 0001 */
1414		{MOV,"A,PC" }, /* c2: 0100 1100 1100 0010 */
1415		{MOV,"A,PD" }, /* c3: 0100 1100 1100 0011 */
1416		{illegal,0 }, /* c4: 0100 1100 1100 0100 */
1417		{MOV,"A,PF" }, /* c5: 0100 1100 1100 0101 */
1418		{MOV,"A,MKH" }, /* c6: 0100 1100 1100 0110 */
1419		{MOV,"A,MKL" }, /* c7: 0100 1100 1100 0111 */
1420		{illegal,0 }, /* c8: 0100 1100 1100 1000 */
1421		{MOV,"A,SMH" }, /* c9: 0100 1100 1100 1001 */
1422		{illegal,0 }, /* ca: 0100 1100 1100 1010 */
1423		{MOV,"A,EOM" }, /* cb: 0100 1100 1100 1011 */
1424		{illegal,0 }, /* cc: 0100 1100 1100 1100 */
1425		{MOV,"A,TMM" }, /* cd: 0100 1100 1100 1101 */
1426		{MOV,"A,PT" }, /* ce: 0100 1100 1100 1110 / / 7807 */
1427		{illegal,0 }, /* cf: 0100 1100 1100 1111 */
1428
1429		{illegal,0 }, /* d0: 0100 1100 1101 0000 */
1430		{illegal,0 }, /* d1: 0100 1100 1101 0001 */
1431		{illegal,0 }, /* d2: 0100 1100 1101 0010 */
1432		{illegal,0 }, /* d3: 0100 1100 1101 0011 */
1433		{illegal,0 }, /* d4: 0100 1100 1101 0100 */
1434		{illegal,0 }, /* d5: 0100 1100 1101 0101 */
1435		{illegal,0 }, /* d6: 0100 1100 1101 0110 */
1436		{illegal,0 }, /* d7: 0100 1100 1101 0111 */
1437		{illegal,0 }, /* d8: 0100 1100 1101 1000 */
1438		{MOV,"A,RXB" }, /* d9: 0100 1100 1101 1001 */
1439		{illegal,0 }, /* da: 0100 1100 1101 1010 */
1440		{illegal,0 }, /* db: 0100 1100 1101 1011 */
1441		{illegal,0 }, /* dc: 0100 1100 1101 1100 */
1442		{illegal,0 }, /* dd: 0100 1100 1101 1101 */
1443		{illegal,0 }, /* de: 0100 1100 1101 1110 */
1444		{illegal,0 }, /* df: 0100 1100 1101 1111 */
1445
1446		{illegal,0 }, /* e0: 0100 1100 1110 0000 */
1447		{illegal,0 }, /* e1: 0100 1100 1110 0001 */
1448		{illegal,0 }, /* e2: 0100 1100 1110 0010 */
1449		{illegal,0 }, /* e3: 0100 1100 1110 0011 */
1450		{illegal,0 }, /* e4: 0100 1100 1110 0100 */
1451		{illegal,0 }, /* e5: 0100 1100 1110 0101 */
1452		{illegal,0 }, /* e6: 0100 1100 1110 0110 */
1453		{illegal,0 }, /* e7: 0100 1100 1110 0111 */
1454		{illegal,0 }, /* e8: 0100 1100 1110 1000 */
1455		{illegal,0 }, /* e9: 0100 1100 1110 1001 */
1456		{illegal,0 }, /* ea: 0100 1100 1110 1010 */
1457		{illegal,0 }, /* eb: 0100 1100 1110 1011 */
1458		{illegal,0 }, /* ec: 0100 1100 1110 1100 */
1459		{illegal,0 }, /* ed: 0100 1100 1110 1101 */
1460		{illegal,0 }, /* ee: 0100 1100 1110 1110 */
1461		{illegal,0 }, /* ef: 0100 1100 1110 1111 */
1462
1463		{illegal,0 }, /* f0: 0100 1100 1111 0000 */
1464		{illegal,0 }, /* f1: 0100 1100 1111 0001 */
1465		{illegal,0 }, /* f2: 0100 1100 1111 0010 */
1466		{illegal,0 }, /* f3: 0100 1100 1111 0011 */
1467		{illegal,0 }, /* f4: 0100 1100 1111 0100 */
1468		{illegal,0 }, /* f5: 0100 1100 1111 0101 */
1469		{illegal,0 }, /* f6: 0100 1100 1111 0110 */
1470		{illegal,0 }, /* f7: 0100 1100 1111 0111 */
1471		{illegal,0 }, /* f8: 0100 1100 1111 1000 */
1472		{illegal,0 }, /* f9: 0100 1100 1111 1001 */
1473		{illegal,0 }, /* fa: 0100 1100 1111 1010 */
1474		{illegal,0 }, /* fb: 0100 1100 1111 1011 */
1475		{illegal,0 }, /* fc: 0100 1100 1111 1100 */
1476		{illegal,0 }, /* fd: 0100 1100 1111 1101 */
1477		{illegal,0 }, /* fe: 0100 1100 1111 1110 */
1478		{illegal,0 } /* ff: 0100 1100 1111 1111 */
1479		};
1480
1481		/* prefix 4D */
1482		static const struct dasm_s dasm4D_7810[256] =
1483		{
1484		{illegal,0 }, /* 00: 0100 1101 0000 0000 */
1485		{illegal,0 }, /* 01: 0100 1101 0000 0001 */
1486		{illegal,0 }, /* 02: 0100 1101 0000 0010 */
1487		{illegal,0 }, /* 03: 0100 1101 0000 0011 */
1488		{illegal,0 }, /* 04: 0100 1101 0000 0100 */
1489		{illegal,0 }, /* 05: 0100 1101 0000 0101 */
1490		{illegal,0 }, /* 06: 0100 1101 0000 0110 */
1491		{illegal,0 }, /* 07: 0100 1101 0000 0111 */
1492		{illegal,0 }, /* 08: 0100 1101 0000 1000 */
1493		{illegal,0 }, /* 09: 0100 1101 0000 1001 */
1494		{illegal,0 }, /* 0a: 0100 1101 0000 1010 */
1495		{illegal,0 }, /* 0b: 0100 1101 0000 1011 */
1496		{illegal,0 }, /* 0c: 0100 1101 0000 1100 */
1497		{illegal,0 }, /* 0d: 0100 1101 0000 1101 */
1498		{illegal,0 }, /* 0e: 0100 1101 0000 1110 */
1499		{illegal,0 }, /* 0f: 0100 1101 0000 1111 */
1500
1501		{illegal,0 }, /* 10: 0100 1101 0001 0000 */
1502		{illegal,0 }, /* 11: 0100 1101 0001 0001 */
1503		{illegal,0 }, /* 12: 0100 1101 0001 0010 */
1504		{illegal,0 }, /* 13: 0100 1101 0001 0011 */
1505		{illegal,0 }, /* 14: 0100 1101 0001 0100 */
1506		{illegal,0 }, /* 15: 0100 1101 0001 0101 */
1507		{illegal,0 }, /* 16: 0100 1101 0001 0110 */
1508		{illegal,0 }, /* 17: 0100 1101 0001 0111 */
1509		{illegal,0 }, /* 18: 0100 1101 0001 1000 */
1510		{illegal,0 }, /* 19: 0100 1101 0001 1001 */
1511		{illegal,0 }, /* 1a: 0100 1101 0001 1010 */
1512		{illegal,0 }, /* 1b: 0100 1101 0001 1011 */
1513		{illegal,0 }, /* 1c: 0100 1101 0001 1100 */
1514		{illegal,0 }, /* 1d: 0100 1101 0001 1101 */
1515		{illegal,0 }, /* 1e: 0100 1101 0001 1110 */
1516		{illegal,0 }, /* 1f: 0100 1101 0001 1111 */
1517
1518		{illegal,0 }, /* 20: 0100 1101 0010 0000 */
1519		{illegal,0 }, /* 21: 0100 1101 0010 0001 */
1520		{illegal,0 }, /* 22: 0100 1101 0010 0010 */
1521		{illegal,0 }, /* 23: 0100 1101 0010 0011 */
1522		{illegal,0 }, /* 24: 0100 1101 0010 0100 */
1523		{illegal,0 }, /* 25: 0100 1101 0010 0101 */
1524		{illegal,0 }, /* 26: 0100 1101 0010 0110 */
1525		{illegal,0 }, /* 27: 0100 1101 0010 0111 */
1526		{illegal,0 }, /* 28: 0100 1101 0010 1000 */
1527		{illegal,0 }, /* 29: 0100 1101 0010 1001 */
1528		{illegal,0 }, /* 2a: 0100 1101 0010 1010 */
1529		{illegal,0 }, /* 2b: 0100 1101 0010 1011 */
1530		{illegal,0 }, /* 2c: 0100 1101 0010 1100 */
1531		{illegal,0 }, /* 2d: 0100 1101 0010 1101 */
1532		{illegal,0 }, /* 2e: 0100 1101 0010 1110 */
1533		{illegal,0 }, /* 2f: 0100 1101 0010 1111 */
1534
1535		{illegal,0 }, /* 30: 0100 1101 0011 0000 */
1536		{illegal,0 }, /* 31: 0100 1101 0011 0001 */
1537		{illegal,0 }, /* 32: 0100 1101 0011 0010 */
1538		{illegal,0 }, /* 33: 0100 1101 0011 0011 */
1539		{illegal,0 }, /* 34: 0100 1101 0011 0100 */
1540		{illegal,0 }, /* 35: 0100 1101 0011 0101 */
1541		{illegal,0 }, /* 36: 0100 1101 0011 0110 */
1542		{illegal,0 }, /* 37: 0100 1101 0011 0111 */
1543		{illegal,0 }, /* 38: 0100 1101 0011 1000 */
1544		{illegal,0 }, /* 39: 0100 1101 0011 1001 */
1545		{illegal,0 }, /* 3a: 0100 1101 0011 1010 */
1546		{illegal,0 }, /* 3b: 0100 1101 0011 1011 */
1547		{illegal,0 }, /* 3c: 0100 1101 0011 1100 */
1548		{illegal,0 }, /* 3d: 0100 1101 0011 1101 */
1549		{illegal,0 }, /* 3e: 0100 1101 0011 1110 */
1550		{illegal,0 }, /* 3f: 0100 1101 0011 1111 */
1551
1552		{illegal,0 }, /* 40: 0100 1101 0100 0000 */
1553		{illegal,0 }, /* 41: 0100 1101 0100 0001 */
1554		{illegal,0 }, /* 42: 0100 1101 0100 0010 */
1555		{illegal,0 }, /* 43: 0100 1101 0100 0011 */
1556		{illegal,0 }, /* 44: 0100 1101 0100 0100 */
1557		{illegal,0 }, /* 45: 0100 1101 0100 0101 */
1558		{illegal,0 }, /* 46: 0100 1101 0100 0110 */
1559		{illegal,0 }, /* 47: 0100 1101 0100 0111 */
1560		{illegal,0 }, /* 48: 0100 1101 0100 1000 */
1561		{illegal,0 }, /* 49: 0100 1101 0100 1001 */
1562		{illegal,0 }, /* 4a: 0100 1101 0100 1010 */
1563		{illegal,0 }, /* 4b: 0100 1101 0100 1011 */
1564		{illegal,0 }, /* 4c: 0100 1101 0100 1100 */
1565		{illegal,0 }, /* 4d: 0100 1101 0100 1101 */
1566		{illegal,0 }, /* 4e: 0100 1101 0100 1110 */
1567		{illegal,0 }, /* 4f: 0100 1101 0100 1111 */
1568
1569		{illegal,0 }, /* 50: 0100 1101 0101 0000 */
1570		{illegal,0 }, /* 51: 0100 1101 0101 0001 */
1571		{illegal,0 }, /* 52: 0100 1101 0101 0010 */
1572		{illegal,0 }, /* 53: 0100 1101 0101 0011 */
1573		{illegal,0 }, /* 54: 0100 1101 0101 0100 */
1574		{illegal,0 }, /* 55: 0100 1101 0101 0101 */
1575		{illegal,0 }, /* 56: 0100 1101 0101 0110 */
1576		{illegal,0 }, /* 57: 0100 1101 0101 0111 */
1577		{illegal,0 }, /* 58: 0100 1101 0101 1000 */
1578		{illegal,0 }, /* 59: 0100 1101 0101 1001 */
1579		{illegal,0 }, /* 5a: 0100 1101 0101 1010 */
1580		{illegal,0 }, /* 5b: 0100 1101 0101 1011 */
1581		{illegal,0 }, /* 5c: 0100 1101 0101 1100 */
1582		{illegal,0 }, /* 5d: 0100 1101 0101 1101 */
1583		{illegal,0 }, /* 5e: 0100 1101 0101 1110 */
1584		{illegal,0 }, /* 5f: 0100 1101 0101 1111 */
1585
1586		{illegal,0 }, /* 60: 0100 1101 0110 0000 */
1587		{illegal,0 }, /* 61: 0100 1101 0110 0001 */
1588		{illegal,0 }, /* 62: 0100 1101 0110 0010 */
1589		{illegal,0 }, /* 63: 0100 1101 0110 0011 */
1590		{illegal,0 }, /* 64: 0100 1101 0110 0100 */
1591		{illegal,0 }, /* 65: 0100 1101 0110 0101 */
1592		{illegal,0 }, /* 66: 0100 1101 0110 0110 */
1593		{illegal,0 }, /* 67: 0100 1101 0110 0111 */
1594		{illegal,0 }, /* 68: 0100 1101 0110 1000 */
1595		{illegal,0 }, /* 69: 0100 1101 0110 1001 */
1596		{illegal,0 }, /* 6a: 0100 1101 0110 1010 */
1597		{illegal,0 }, /* 6b: 0100 1101 0110 1011 */
1598		{illegal,0 }, /* 6c: 0100 1101 0110 1100 */
1599		{illegal,0 }, /* 6d: 0100 1101 0110 1101 */
1600		{illegal,0 }, /* 6e: 0100 1101 0110 1110 */
1601		{illegal,0 }, /* 6f: 0100 1101 0110 1111 */
1602
1603		{illegal,0 }, /* 70: 0100 1101 0111 0000 */
1604		{illegal,0 }, /* 71: 0100 1101 0111 0001 */
1605		{illegal,0 }, /* 72: 0100 1101 0111 0010 */
1606		{illegal,0 }, /* 73: 0100 1101 0111 0011 */
1607		{illegal,0 }, /* 74: 0100 1101 0111 0100 */
1608		{illegal,0 }, /* 75: 0100 1101 0111 0101 */
1609		{illegal,0 }, /* 76: 0100 1101 0111 0110 */
1610		{illegal,0 }, /* 77: 0100 1101 0111 0111 */
1611		{illegal,0 }, /* 78: 0100 1101 0111 1000 */
1612		{illegal,0 }, /* 79: 0100 1101 0111 1001 */
1613		{illegal,0 }, /* 7a: 0100 1101 0111 1010 */
1614		{illegal,0 }, /* 7b: 0100 1101 0111 1011 */
1615		{illegal,0 }, /* 7c: 0100 1101 0111 1100 */
1616		{illegal,0 }, /* 7d: 0100 1101 0111 1101 */
1617		{illegal,0 }, /* 7e: 0100 1101 0111 1110 */
1618		{illegal,0 }, /* 7f: 0100 1101 0111 1111 */
1619
1620		{illegal,0 }, /* 80: 0100 1101 1000 0000 */
1621		{illegal,0 }, /* 81: 0100 1101 1000 0001 */
1622		{illegal,0 }, /* 82: 0100 1101 1000 0010 */
1623		{illegal,0 }, /* 83: 0100 1101 1000 0011 */
1624		{illegal,0 }, /* 84: 0100 1101 1000 0100 */
1625		{illegal,0 }, /* 85: 0100 1101 1000 0101 */
1626		{illegal,0 }, /* 86: 0100 1101 1000 0110 */
1627		{illegal,0 }, /* 87: 0100 1101 1000 0111 */
1628		{illegal,0 }, /* 88: 0100 1101 1000 1000 */
1629		{illegal,0 }, /* 89: 0100 1101 1000 1001 */
1630		{illegal,0 }, /* 8a: 0100 1101 1000 1010 */
1631		{illegal,0 }, /* 8b: 0100 1101 1000 1011 */
1632		{illegal,0 }, /* 8c: 0100 1101 1000 1100 */
1633		{illegal,0 }, /* 8d: 0100 1101 1000 1101 */
1634		{illegal,0 }, /* 8e: 0100 1101 1000 1110 */
1635		{illegal,0 }, /* 8f: 0100 1101 1000 1111 */
1636
1637		{illegal,0 }, /* 90: 0100 1101 1001 0000 */
1638		{illegal,0 }, /* 91: 0100 1101 1001 0001 */
1639		{illegal,0 }, /* 92: 0100 1101 1001 0010 */
1640		{illegal,0 }, /* 93: 0100 1101 1001 0011 */
1641		{illegal,0 }, /* 94: 0100 1101 1001 0100 */
1642		{illegal,0 }, /* 95: 0100 1101 1001 0101 */
1643		{illegal,0 }, /* 96: 0100 1101 1001 0110 */
1644		{illegal,0 }, /* 97: 0100 1101 1001 0111 */
1645		{illegal,0 }, /* 98: 0100 1101 1001 1000 */
1646		{illegal,0 }, /* 99: 0100 1101 1001 1001 */
1647		{illegal,0 }, /* 9a: 0100 1101 1001 1010 */
1648		{illegal,0 }, /* 9b: 0100 1101 1001 1011 */
1649		{illegal,0 }, /* 9c: 0100 1101 1001 1100 */
1650		{illegal,0 }, /* 9d: 0100 1101 1001 1101 */
1651		{illegal,0 }, /* 9e: 0100 1101 1001 1110 */
1652		{illegal,0 }, /* 9f: 0100 1101 1001 1111 */
1653
1654		{illegal,0 }, /* a0: 0100 1101 1010 0000 */
1655		{illegal,0 }, /* a1: 0100 1101 1010 0001 */
1656		{illegal,0 }, /* a2: 0100 1101 1010 0010 */
1657		{illegal,0 }, /* a3: 0100 1101 1010 0011 */
1658		{illegal,0 }, /* a4: 0100 1101 1010 0100 */
1659		{illegal,0 }, /* a5: 0100 1101 1010 0101 */
1660		{illegal,0 }, /* a6: 0100 1101 1010 0110 */
1661		{illegal,0 }, /* a7: 0100 1101 1010 0111 */
1662		{illegal,0 }, /* a8: 0100 1101 1010 1000 */
1663		{illegal,0 }, /* a9: 0100 1101 1010 1001 */
1664		{illegal,0 }, /* aa: 0100 1101 1010 1010 */
1665		{illegal,0 }, /* ab: 0100 1101 1010 1011 */
1666		{illegal,0 }, /* ac: 0100 1101 1010 1100 */
1667		{illegal,0 }, /* ad: 0100 1101 1010 1101 */
1668		{illegal,0 }, /* ae: 0100 1101 1010 1110 */
1669		{illegal,0 }, /* af: 0100 1101 1010 1111 */
1670
1671		{illegal,0 }, /* b0: 0100 1101 1011 0000 */
1672		{illegal,0 }, /* b1: 0100 1101 1011 0001 */
1673		{illegal,0 }, /* b2: 0100 1101 1011 0010 */
1674		{illegal,0 }, /* b3: 0100 1101 1011 0011 */
1675		{illegal,0 }, /* b4: 0100 1101 1011 0100 */
1676		{illegal,0 }, /* b5: 0100 1101 1011 0101 */
1677		{illegal,0 }, /* b6: 0100 1101 1011 0110 */
1678		{illegal,0 }, /* b7: 0100 1101 1011 0111 */
1679		{illegal,0 }, /* b8: 0100 1101 1011 1000 */
1680		{illegal,0 }, /* b9: 0100 1101 1011 1001 */
1681		{illegal,0 }, /* ba: 0100 1101 1011 1010 */
1682		{illegal,0 }, /* bb: 0100 1101 1011 1011 */
1683		{illegal,0 }, /* bc: 0100 1101 1011 1100 */
1684		{illegal,0 }, /* bd: 0100 1101 1011 1101 */
1685		{illegal,0 }, /* be: 0100 1101 1011 1110 */
1686		{illegal,0 }, /* bf: 0100 1101 1011 1111 */
1687
1688		{MOV,"PA,A" }, /* c0: 0100 1101 1100 0000 */
1689		{MOV,"PB,A" }, /* c1: 0100 1101 1100 0001 */
1690		{MOV,"PC,A" }, /* c2: 0100 1101 1100 0010 */
1691		{MOV,"PD,A" }, /* c3: 0100 1101 1100 0011 */
1692		{illegal,0 }, /* c4: 0100 1101 1100 0100 */
1693		{MOV,"PF,A" }, /* c5: 0100 1101 1100 0101 */
1694		{MOV,"MKH,A" }, /* c6: 0100 1101 1100 0110 */
1695		{MOV,"MKL,A" }, /* c7: 0100 1101 1100 0111 */
1696		{MOV,"ANM,A" }, /* c8: 0100 1101 1100 1000 / / 7810 */
1697		{MOV,"SMH,A" }, /* c9: 0100 1101 1100 1001 */
1698		{MOV,"SML,A" }, /* ca: 0100 1101 1100 1010 */
1699		{MOV,"EOM,A" }, /* cb: 0100 1101 1100 1011 */
1700		{MOV,"ETMM,A" }, /* cc: 0100 1101 1100 1100 */
1701		{MOV,"TMM,A" }, /* cd: 0100 1101 1100 1101 */
1702		{illegal,0 }, /* ce: 0100 1101 1100 1110 */
1703		{illegal,0 }, /* cf: 0100 1101 1100 1111 */
1704
1705		{MOV,"MM,A" }, /* d0: 0100 1101 1101 0000 */
1706		{MOV,"MCC,A" }, /* d1: 0100 1101 1101 0001 */
1707		{MOV,"MA,A" }, /* d2: 0100 1101 1101 0010 */
1708		{MOV,"MB,A" }, /* d3: 0100 1101 1101 0011 */
1709		{MOV,"MC,A" }, /* d4: 0100 1101 1101 0100 */
1710		{illegal,0 }, /* d5: 0100 1101 1101 0101 */
1711		{illegal,0 }, /* d6: 0100 1101 1101 0110 */
1712		{MOV,"MF,A" }, /* d7: 0100 1101 1101 0111 */
1713		{MOV,"TXB,A" }, /* d8: 0100 1101 1101 1000 */
1714		{illegal,0 }, /* d9: 0100 1101 1101 1001 */
1715		{MOV,"TM0,A" }, /* da: 0100 1101 1101 1010 */
1716		{MOV,"TM1,A" }, /* db: 0100 1101 1101 1011 */
1717		{illegal,0 }, /* dc: 0100 1101 1101 1100 */
1718		{illegal,0 }, /* dd: 0100 1101 1101 1101 */
1719		{illegal,0 }, /* de: 0100 1101 1101 1110 */
1720		{illegal,0 }, /* df: 0100 1101 1101 1111 */
1721
1722		{illegal,0 }, /* e0: 0100 1101 1110 0000 */
1723		{illegal,0 }, /* e1: 0100 1101 1110 0001 */
1724		{illegal,0 }, /* e2: 0100 1101 1110 0010 */
1725		{illegal,0 }, /* e3: 0100 1101 1110 0011 */
1726		{illegal,0 }, /* e4: 0100 1101 1110 0100 */
1727		{illegal,0 }, /* e5: 0100 1101 1110 0101 */
1728		{illegal,0 }, /* e6: 0100 1101 1110 0110 */
1729		{illegal,0 }, /* e7: 0100 1101 1110 0111 */
1730		{MOV,"ZCM,A" }, /* e8: 0100 1101 1110 1000 / / 7810 */
1731		{illegal,0 }, /* e9: 0100 1101 1110 1001 */
1732		{illegal,0 }, /* ea: 0100 1101 1110 1010 */
1733		{illegal,0 }, /* eb: 0100 1101 1110 1011 */
1734		{illegal,0 }, /* ec: 0100 1101 1110 1100 */
1735		{illegal,0 }, /* ed: 0100 1101 1110 1101 */
1736		{illegal,0 }, /* ee: 0100 1101 1110 1110 */
1737		{illegal,0 }, /* ef: 0100 1101 1110 1111 */
1738
1739		{illegal,0 }, /* f0: 0100 1101 1111 0000 */
1740		{illegal,0 }, /* f1: 0100 1101 1111 0001 */
1741		{illegal,0 }, /* f2: 0100 1101 1111 0010 */
1742		{illegal,0 }, /* f3: 0100 1101 1111 0011 */
1743		{illegal,0 }, /* f4: 0100 1101 1111 0100 */
1744		{illegal,0 }, /* f5: 0100 1101 1111 0101 */
1745		{illegal,0 }, /* f6: 0100 1101 1111 0110 */
1746		{illegal,0 }, /* f7: 0100 1101 1111 0111 */
1747		{illegal,0 }, /* f8: 0100 1101 1111 1000 */
1748		{illegal,0 }, /* f9: 0100 1101 1111 1001 */
1749		{illegal,0 }, /* fa: 0100 1101 1111 1010 */
1750		{illegal,0 }, /* fb: 0100 1101 1111 1011 */
1751		{illegal,0 }, /* fc: 0100 1101 1111 1100 */
1752		{illegal,0 }, /* fd: 0100 1101 1111 1101 */
1753		{illegal,0 }, /* fe: 0100 1101 1111 1110 */
1754		{illegal,0 } /* ff: 0100 1101 1111 1111 */
1755		};
1756
1757		static const struct dasm_s dasm4D_7807[256] =
1758		{
1759		{illegal,0 }, /* 00: 0100 1101 0000 0000 */
1760		{illegal,0 }, /* 01: 0100 1101 0000 0001 */
1761		{illegal,0 }, /* 02: 0100 1101 0000 0010 */
1762		{illegal,0 }, /* 03: 0100 1101 0000 0011 */
1763		{illegal,0 }, /* 04: 0100 1101 0000 0100 */
1764		{illegal,0 }, /* 05: 0100 1101 0000 0101 */
1765		{illegal,0 }, /* 06: 0100 1101 0000 0110 */
1766		{illegal,0 }, /* 07: 0100 1101 0000 0111 */
1767		{illegal,0 }, /* 08: 0100 1101 0000 1000 */
1768		{illegal,0 }, /* 09: 0100 1101 0000 1001 */
1769		{illegal,0 }, /* 0a: 0100 1101 0000 1010 */
1770		{illegal,0 }, /* 0b: 0100 1101 0000 1011 */
1771		{illegal,0 }, /* 0c: 0100 1101 0000 1100 */
1772		{illegal,0 }, /* 0d: 0100 1101 0000 1101 */
1773		{illegal,0 }, /* 0e: 0100 1101 0000 1110 */
1774		{illegal,0 }, /* 0f: 0100 1101 0000 1111 */
1775
1776		{illegal,0 }, /* 10: 0100 1101 0001 0000 */
1777		{illegal,0 }, /* 11: 0100 1101 0001 0001 */
1778		{illegal,0 }, /* 12: 0100 1101 0001 0010 */
1779		{illegal,0 }, /* 13: 0100 1101 0001 0011 */
1780		{illegal,0 }, /* 14: 0100 1101 0001 0100 */
1781		{illegal,0 }, /* 15: 0100 1101 0001 0101 */
1782		{illegal,0 }, /* 16: 0100 1101 0001 0110 */
1783		{illegal,0 }, /* 17: 0100 1101 0001 0111 */
1784		{illegal,0 }, /* 18: 0100 1101 0001 1000 */
1785		{illegal,0 }, /* 19: 0100 1101 0001 1001 */
1786		{illegal,0 }, /* 1a: 0100 1101 0001 1010 */
1787		{illegal,0 }, /* 1b: 0100 1101 0001 1011 */
1788		{illegal,0 }, /* 1c: 0100 1101 0001 1100 */
1789		{illegal,0 }, /* 1d: 0100 1101 0001 1101 */
1790		{illegal,0 }, /* 1e: 0100 1101 0001 1110 */
1791		{illegal,0 }, /* 1f: 0100 1101 0001 1111 */
1792
1793		{illegal,0 }, /* 20: 0100 1101 0010 0000 */
1794		{illegal,0 }, /* 21: 0100 1101 0010 0001 */
1795		{illegal,0 }, /* 22: 0100 1101 0010 0010 */
1796		{illegal,0 }, /* 23: 0100 1101 0010 0011 */
1797		{illegal,0 }, /* 24: 0100 1101 0010 0100 */
1798		{illegal,0 }, /* 25: 0100 1101 0010 0101 */
1799		{illegal,0 }, /* 26: 0100 1101 0010 0110 */
1800		{illegal,0 }, /* 27: 0100 1101 0010 0111 */
1801		{illegal,0 }, /* 28: 0100 1101 0010 1000 */
1802		{illegal,0 }, /* 29: 0100 1101 0010 1001 */
1803		{illegal,0 }, /* 2a: 0100 1101 0010 1010 */
1804		{illegal,0 }, /* 2b: 0100 1101 0010 1011 */
1805		{illegal,0 }, /* 2c: 0100 1101 0010 1100 */
1806		{illegal,0 }, /* 2d: 0100 1101 0010 1101 */
1807		{illegal,0 }, /* 2e: 0100 1101 0010 1110 */
1808		{illegal,0 }, /* 2f: 0100 1101 0010 1111 */
1809
1810		{illegal,0 }, /* 30: 0100 1101 0011 0000 */
1811		{illegal,0 }, /* 31: 0100 1101 0011 0001 */
1812		{illegal,0 }, /* 32: 0100 1101 0011 0010 */
1813		{illegal,0 }, /* 33: 0100 1101 0011 0011 */
1814		{illegal,0 }, /* 34: 0100 1101 0011 0100 */
1815		{illegal,0 }, /* 35: 0100 1101 0011 0101 */
1816		{illegal,0 }, /* 36: 0100 1101 0011 0110 */
1817		{illegal,0 }, /* 37: 0100 1101 0011 0111 */
1818		{illegal,0 }, /* 38: 0100 1101 0011 1000 */
1819		{illegal,0 }, /* 39: 0100 1101 0011 1001 */
1820		{illegal,0 }, /* 3a: 0100 1101 0011 1010 */
1821		{illegal,0 }, /* 3b: 0100 1101 0011 1011 */
1822		{illegal,0 }, /* 3c: 0100 1101 0011 1100 */
1823		{illegal,0 }, /* 3d: 0100 1101 0011 1101 */
1824		{illegal,0 }, /* 3e: 0100 1101 0011 1110 */
1825		{illegal,0 }, /* 3f: 0100 1101 0011 1111 */
1826
1827		{illegal,0 }, /* 40: 0100 1101 0100 0000 */
1828		{illegal,0 }, /* 41: 0100 1101 0100 0001 */
1829		{illegal,0 }, /* 42: 0100 1101 0100 0010 */
1830		{illegal,0 }, /* 43: 0100 1101 0100 0011 */
1831		{illegal,0 }, /* 44: 0100 1101 0100 0100 */
1832		{illegal,0 }, /* 45: 0100 1101 0100 0101 */
1833		{illegal,0 }, /* 46: 0100 1101 0100 0110 */
1834		{illegal,0 }, /* 47: 0100 1101 0100 0111 */
1835		{illegal,0 }, /* 48: 0100 1101 0100 1000 */
1836		{illegal,0 }, /* 49: 0100 1101 0100 1001 */
1837		{illegal,0 }, /* 4a: 0100 1101 0100 1010 */
1838		{illegal,0 }, /* 4b: 0100 1101 0100 1011 */
1839		{illegal,0 }, /* 4c: 0100 1101 0100 1100 */
1840		{illegal,0 }, /* 4d: 0100 1101 0100 1101 */
1841		{illegal,0 }, /* 4e: 0100 1101 0100 1110 */
1842		{illegal,0 }, /* 4f: 0100 1101 0100 1111 */
1843
1844		{illegal,0 }, /* 50: 0100 1101 0101 0000 */
1845		{illegal,0 }, /* 51: 0100 1101 0101 0001 */
1846		{illegal,0 }, /* 52: 0100 1101 0101 0010 */
1847		{illegal,0 }, /* 53: 0100 1101 0101 0011 */
1848		{illegal,0 }, /* 54: 0100 1101 0101 0100 */
1849		{illegal,0 }, /* 55: 0100 1101 0101 0101 */
1850		{illegal,0 }, /* 56: 0100 1101 0101 0110 */
1851		{illegal,0 }, /* 57: 0100 1101 0101 0111 */
1852		{illegal,0 }, /* 58: 0100 1101 0101 1000 */
1853		{illegal,0 }, /* 59: 0100 1101 0101 1001 */
1854		{illegal,0 }, /* 5a: 0100 1101 0101 1010 */
1855		{illegal,0 }, /* 5b: 0100 1101 0101 1011 */
1856		{illegal,0 }, /* 5c: 0100 1101 0101 1100 */
1857		{illegal,0 }, /* 5d: 0100 1101 0101 1101 */
1858		{illegal,0 }, /* 5e: 0100 1101 0101 1110 */
1859		{illegal,0 }, /* 5f: 0100 1101 0101 1111 */
1860
1861		{illegal,0 }, /* 60: 0100 1101 0110 0000 */
1862		{illegal,0 }, /* 61: 0100 1101 0110 0001 */
1863		{illegal,0 }, /* 62: 0100 1101 0110 0010 */
1864		{illegal,0 }, /* 63: 0100 1101 0110 0011 */
1865		{illegal,0 }, /* 64: 0100 1101 0110 0100 */
1866		{illegal,0 }, /* 65: 0100 1101 0110 0101 */
1867		{illegal,0 }, /* 66: 0100 1101 0110 0110 */
1868		{illegal,0 }, /* 67: 0100 1101 0110 0111 */
1869		{illegal,0 }, /* 68: 0100 1101 0110 1000 */
1870		{illegal,0 }, /* 69: 0100 1101 0110 1001 */
1871		{illegal,0 }, /* 6a: 0100 1101 0110 1010 */
1872		{illegal,0 }, /* 6b: 0100 1101 0110 1011 */
1873		{illegal,0 }, /* 6c: 0100 1101 0110 1100 */
1874		{illegal,0 }, /* 6d: 0100 1101 0110 1101 */
1875		{illegal,0 }, /* 6e: 0100 1101 0110 1110 */
1876		{illegal,0 }, /* 6f: 0100 1101 0110 1111 */
1877
1878		{illegal,0 }, /* 70: 0100 1101 0111 0000 */
1879		{illegal,0 }, /* 71: 0100 1101 0111 0001 */
1880		{illegal,0 }, /* 72: 0100 1101 0111 0010 */
1881		{illegal,0 }, /* 73: 0100 1101 0111 0011 */
1882		{illegal,0 }, /* 74: 0100 1101 0111 0100 */
1883		{illegal,0 }, /* 75: 0100 1101 0111 0101 */
1884		{illegal,0 }, /* 76: 0100 1101 0111 0110 */
1885		{illegal,0 }, /* 77: 0100 1101 0111 0111 */
1886		{illegal,0 }, /* 78: 0100 1101 0111 1000 */
1887		{illegal,0 }, /* 79: 0100 1101 0111 1001 */
1888		{illegal,0 }, /* 7a: 0100 1101 0111 1010 */
1889		{illegal,0 }, /* 7b: 0100 1101 0111 1011 */
1890		{illegal,0 }, /* 7c: 0100 1101 0111 1100 */
1891		{illegal,0 }, /* 7d: 0100 1101 0111 1101 */
1892		{illegal,0 }, /* 7e: 0100 1101 0111 1110 */
1893		{illegal,0 }, /* 7f: 0100 1101 0111 1111 */
1894
1895		{illegal,0 }, /* 80: 0100 1101 1000 0000 */
1896		{illegal,0 }, /* 81: 0100 1101 1000 0001 */
1897		{illegal,0 }, /* 82: 0100 1101 1000 0010 */
1898		{illegal,0 }, /* 83: 0100 1101 1000 0011 */
1899		{illegal,0 }, /* 84: 0100 1101 1000 0100 */
1900		{illegal,0 }, /* 85: 0100 1101 1000 0101 */
1901		{illegal,0 }, /* 86: 0100 1101 1000 0110 */
1902		{illegal,0 }, /* 87: 0100 1101 1000 0111 */
1903		{illegal,0 }, /* 88: 0100 1101 1000 1000 */
1904		{illegal,0 }, /* 89: 0100 1101 1000 1001 */
1905		{illegal,0 }, /* 8a: 0100 1101 1000 1010 */
1906		{illegal,0 }, /* 8b: 0100 1101 1000 1011 */
1907		{illegal,0 }, /* 8c: 0100 1101 1000 1100 */
1908		{illegal,0 }, /* 8d: 0100 1101 1000 1101 */
1909		{illegal,0 }, /* 8e: 0100 1101 1000 1110 */
1910		{illegal,0 }, /* 8f: 0100 1101 1000 1111 */
1911
1912		{illegal,0 }, /* 90: 0100 1101 1001 0000 */
1913		{illegal,0 }, /* 91: 0100 1101 1001 0001 */
1914		{illegal,0 }, /* 92: 0100 1101 1001 0010 */
1915		{illegal,0 }, /* 93: 0100 1101 1001 0011 */
1916		{illegal,0 }, /* 94: 0100 1101 1001 0100 */
1917		{illegal,0 }, /* 95: 0100 1101 1001 0101 */
1918		{illegal,0 }, /* 96: 0100 1101 1001 0110 */
1919		{illegal,0 }, /* 97: 0100 1101 1001 0111 */
1920		{illegal,0 }, /* 98: 0100 1101 1001 1000 */
1921		{illegal,0 }, /* 99: 0100 1101 1001 1001 */
1922		{illegal,0 }, /* 9a: 0100 1101 1001 1010 */
1923		{illegal,0 }, /* 9b: 0100 1101 1001 1011 */
1924		{illegal,0 }, /* 9c: 0100 1101 1001 1100 */
1925		{illegal,0 }, /* 9d: 0100 1101 1001 1101 */
1926		{illegal,0 }, /* 9e: 0100 1101 1001 1110 */
1927		{illegal,0 }, /* 9f: 0100 1101 1001 1111 */
1928
1929		{illegal,0 }, /* a0: 0100 1101 1010 0000 */
1930		{illegal,0 }, /* a1: 0100 1101 1010 0001 */
1931		{illegal,0 }, /* a2: 0100 1101 1010 0010 */
1932		{illegal,0 }, /* a3: 0100 1101 1010 0011 */
1933		{illegal,0 }, /* a4: 0100 1101 1010 0100 */
1934		{illegal,0 }, /* a5: 0100 1101 1010 0101 */
1935		{illegal,0 }, /* a6: 0100 1101 1010 0110 */
1936		{illegal,0 }, /* a7: 0100 1101 1010 0111 */
1937		{illegal,0 }, /* a8: 0100 1101 1010 1000 */
1938		{illegal,0 }, /* a9: 0100 1101 1010 1001 */
1939		{illegal,0 }, /* aa: 0100 1101 1010 1010 */
1940		{illegal,0 }, /* ab: 0100 1101 1010 1011 */
1941		{illegal,0 }, /* ac: 0100 1101 1010 1100 */
1942		{illegal,0 }, /* ad: 0100 1101 1010 1101 */
1943		{illegal,0 }, /* ae: 0100 1101 1010 1110 */
1944		{illegal,0 }, /* af: 0100 1101 1010 1111 */
1945
1946		{illegal,0 }, /* b0: 0100 1101 1011 0000 */
1947		{illegal,0 }, /* b1: 0100 1101 1011 0001 */
1948		{illegal,0 }, /* b2: 0100 1101 1011 0010 */
1949		{illegal,0 }, /* b3: 0100 1101 1011 0011 */
1950		{illegal,0 }, /* b4: 0100 1101 1011 0100 */
1951		{illegal,0 }, /* b5: 0100 1101 1011 0101 */
1952		{illegal,0 }, /* b6: 0100 1101 1011 0110 */
1953		{illegal,0 }, /* b7: 0100 1101 1011 0111 */
1954		{illegal,0 }, /* b8: 0100 1101 1011 1000 */
1955		{illegal,0 }, /* b9: 0100 1101 1011 1001 */
1956		{illegal,0 }, /* ba: 0100 1101 1011 1010 */
1957		{illegal,0 }, /* bb: 0100 1101 1011 1011 */
1958		{illegal,0 }, /* bc: 0100 1101 1011 1100 */
1959		{illegal,0 }, /* bd: 0100 1101 1011 1101 */
1960		{illegal,0 }, /* be: 0100 1101 1011 1110 */
1961		{illegal,0 }, /* bf: 0100 1101 1011 1111 */
1962
1963		{MOV,"PA,A" }, /* c0: 0100 1101 1100 0000 */
1964		{MOV,"PB,A" }, /* c1: 0100 1101 1100 0001 */
1965		{MOV,"PC,A" }, /* c2: 0100 1101 1100 0010 */
1966		{MOV,"PD,A" }, /* c3: 0100 1101 1100 0011 */
1967		{illegal,0 }, /* c4: 0100 1101 1100 0100 */
1968		{MOV,"PF,A" }, /* c5: 0100 1101 1100 0101 */
1969		{MOV,"MKH,A" }, /* c6: 0100 1101 1100 0110 */
1970		{MOV,"MKL,A" }, /* c7: 0100 1101 1100 0111 */
1971		{illegal,0 }, /* c8: 0100 1101 1100 1000 */
1972		{MOV,"SMH,A" }, /* c9: 0100 1101 1100 1001 */
1973		{MOV,"SML,A" }, /* ca: 0100 1101 1100 1010 */
1974		{MOV,"EOM,A" }, /* cb: 0100 1101 1100 1011 */
1975		{MOV,"ETMM,A" }, /* cc: 0100 1101 1100 1100 */
1976		{MOV,"TMM,A" }, /* cd: 0100 1101 1100 1101 */
1977		{illegal,0 }, /* ce: 0100 1101 1100 1110 */
1978		{illegal,0 }, /* cf: 0100 1101 1100 1111 */
1979
1980		{MOV,"MM,A" }, /* d0: 0100 1101 1101 0000 */
1981		{MOV,"MCC,A" }, /* d1: 0100 1101 1101 0001 */
1982		{MOV,"MA,A" }, /* d2: 0100 1101 1101 0010 */
1983		{MOV,"MB,A" }, /* d3: 0100 1101 1101 0011 */
1984		{MOV,"MC,A" }, /* d4: 0100 1101 1101 0100 */
1985		{illegal,0 }, /* d5: 0100 1101 1101 0101 */
1986		{illegal,0 }, /* d6: 0100 1101 1101 0110 */
1987		{MOV,"MF,A" }, /* d7: 0100 1101 1101 0111 */
1988		{MOV,"TXB,A" }, /* d8: 0100 1101 1101 1000 */
1989		{illegal,0 }, /* d9: 0100 1101 1101 1001 */
1990		{MOV,"TM0,A" }, /* da: 0100 1101 1101 1010 */
1991		{MOV,"TM1,A" }, /* db: 0100 1101 1101 1011 */
1992		{illegal,0 }, /* dc: 0100 1101 1101 1100 */
1993		{illegal,0 }, /* dd: 0100 1101 1101 1101 */
1994		{illegal,0 }, /* de: 0100 1101 1101 1110 */
1995		{illegal,0 }, /* df: 0100 1101 1101 1111 */
1996
1997		{illegal,0 }, /* e0: 0100 1101 1110 0000 */
1998		{illegal,0 }, /* e1: 0100 1101 1110 0001 */
1999		{illegal,0 }, /* e2: 0100 1101 1110 0010 */
2000		{illegal,0 }, /* e3: 0100 1101 1110 0011 */
2001		{illegal,0 }, /* e4: 0100 1101 1110 0100 */
2002		{MOV,"MT,A" }, /* e5: 0100 1101 1110 0101 / / 7807 */
2003		{illegal,0 }, /* e6: 0100 1101 1110 0110 */
2004		{illegal,0 }, /* e7: 0100 1101 1110 0111 */
2005		{illegal,0 }, /* e8: 0100 1101 1110 1000 */
2006		{illegal,0 }, /* e9: 0100 1101 1110 1001 */
2007		{illegal,0 }, /* ea: 0100 1101 1110 1010 */
2008		{illegal,0 }, /* eb: 0100 1101 1110 1011 */
2009		{illegal,0 }, /* ec: 0100 1101 1110 1100 */
2010		{illegal,0 }, /* ed: 0100 1101 1110 1101 */
2011		{illegal,0 }, /* ee: 0100 1101 1110 1110 */
2012		{illegal,0 }, /* ef: 0100 1101 1110 1111 */
2013
2014		{illegal,0 }, /* f0: 0100 1101 1111 0000 */
2015		{illegal,0 }, /* f1: 0100 1101 1111 0001 */
2016		{illegal,0 }, /* f2: 0100 1101 1111 0010 */
2017		{illegal,0 }, /* f3: 0100 1101 1111 0011 */
2018		{illegal,0 }, /* f4: 0100 1101 1111 0100 */
2019		{illegal,0 }, /* f5: 0100 1101 1111 0101 */
2020		{illegal,0 }, /* f6: 0100 1101 1111 0110 */
2021		{illegal,0 }, /* f7: 0100 1101 1111 0111 */
2022		{illegal,0 }, /* f8: 0100 1101 1111 1000 */
2023		{illegal,0 }, /* f9: 0100 1101 1111 1001 */
2024		{illegal,0 }, /* fa: 0100 1101 1111 1010 */
2025		{illegal,0 }, /* fb: 0100 1101 1111 1011 */
2026		{illegal,0 }, /* fc: 0100 1101 1111 1100 */
2027		{illegal,0 }, /* fd: 0100 1101 1111 1101 */
2028		{illegal,0 }, /* fe: 0100 1101 1111 1110 */
2029		{illegal,0 } /* ff: 0100 1101 1111 1111 */
2030		};
2031
2032		/* prefix 60 */
2033		static const struct dasm_s dasm60[256] =
2034		{
2035		{illegal,0 }, /* 00: 0110 0000 0000 0000 */
2036		{illegal,0 }, /* 01: 0110 0000 0000 0001 */
2037		{illegal,0 }, /* 02: 0110 0000 0000 0010 */
2038		{illegal,0 }, /* 03: 0110 0000 0000 0011 */
2039		{illegal,0 }, /* 04: 0110 0000 0000 0100 */
2040		{illegal,0 }, /* 05: 0110 0000 0000 0101 */
2041		{illegal,0 }, /* 06: 0110 0000 0000 0110 */
2042		{illegal,0 }, /* 07: 0110 0000 0000 0111 */
2043		{ANA,"V,A" }, /* 08: 0110 0000 0000 1000 */
2044		{ANA,"A,A" }, /* 09: 0110 0000 0000 1001 */
2045		{ANA,"B,A" }, /* 0a: 0110 0000 0000 1010 */
2046		{ANA,"C,A" }, /* 0b: 0110 0000 0000 1011 */
2047		{ANA,"D,A" }, /* 0c: 0110 0000 0000 1100 */
2048		{ANA,"E,A" }, /* 0d: 0110 0000 0000 1101 */
2049		{ANA,"H,A" }, /* 0e: 0110 0000 0000 1110 */
2050		{ANA,"L,A" }, /* 0f: 0110 0000 0000 1111 */
2051
2052		{XRA,"V,A" }, /* 10: 0110 0000 0001 0000 */
2053		{XRA,"A,A" }, /* 11: 0110 0000 0001 0001 */
2054		{XRA,"B,A" }, /* 12: 0110 0000 0001 0010 */
2055		{XRA,"C,A" }, /* 13: 0110 0000 0001 0011 */
2056		{XRA,"D,A" }, /* 14: 0110 0000 0001 0100 */
2057		{XRA,"E,A" }, /* 15: 0110 0000 0001 0101 */
2058		{XRA,"H,A" }, /* 16: 0110 0000 0001 0110 */
2059		{XRA,"L,A" }, /* 17: 0110 0000 0001 0111 */
2060		{ORA,"V,A" }, /* 18: 0110 0000 0001 1000 */
2061		{ORA,"A,A" }, /* 19: 0110 0000 0001 1001 */
2062		{ORA,"B,A" }, /* 1a: 0110 0000 0001 1010 */
2063		{ORA,"C,A" }, /* 1b: 0110 0000 0001 1011 */
2064		{ORA,"D,A" }, /* 1c: 0110 0000 0001 1100 */
2065		{ORA,"E,A" }, /* 1d: 0110 0000 0001 1101 */
2066		{ORA,"H,A" }, /* 1e: 0110 0000 0001 1110 */
2067		{ORA,"L,A" }, /* 1f: 0110 0000 0001 1111 */
2068
2069		{ADDNC,"V,A" }, /* 20: 0110 0000 0010 0000 */
2070		{ADDNC,"A,A" }, /* 21: 0110 0000 0010 0001 */
2071		{ADDNC,"B,A" }, /* 22: 0110 0000 0010 0010 */
2072		{ADDNC,"C,A" }, /* 23: 0110 0000 0010 0011 */
2073		{ADDNC,"D,A" }, /* 24: 0110 0000 0010 0100 */
2074		{ADDNC,"E,A" }, /* 25: 0110 0000 0010 0101 */
2075		{ADDNC,"H,A" }, /* 26: 0110 0000 0010 0110 */
2076		{ADDNC,"L,A" }, /* 27: 0110 0000 0010 0111 */
2077		{GTA,"V,A" }, /* 28: 0110 0000 0010 1000 */
2078		{GTA,"A,A" }, /* 29: 0110 0000 0010 1001 */
2079		{GTA,"B,A" }, /* 2a: 0110 0000 0010 1010 */
2080		{GTA,"C,A" }, /* 2b: 0110 0000 0010 1011 */
2081		{GTA,"D,A" }, /* 2c: 0110 0000 0010 1100 */
2082		{GTA,"E,A" }, /* 2d: 0110 0000 0010 1101 */
2083		{GTA,"H,A" }, /* 2e: 0110 0000 0010 1110 */
2084		{GTA,"L,A" }, /* 2f: 0110 0000 0010 1111 */
2085
2086		{SUBNB,"V,A" }, /* 30: 0110 0000 0011 0000 */
2087		{SUBNB,"A,A" }, /* 31: 0110 0000 0011 0001 */
2088		{SUBNB,"B,A" }, /* 32: 0110 0000 0011 0010 */
2089		{SUBNB,"C,A" }, /* 33: 0110 0000 0011 0011 */
2090		{SUBNB,"D,A" }, /* 34: 0110 0000 0011 0100 */
2091		{SUBNB,"E,A" }, /* 35: 0110 0000 0011 0101 */
2092		{SUBNB,"H,A" }, /* 36: 0110 0000 0011 0110 */
2093		{SUBNB,"L,A" }, /* 37: 0110 0000 0011 0111 */
2094		{LTA,"V,A" }, /* 38: 0110 0000 0011 1000 */
2095		{LTA,"A,A" }, /* 39: 0110 0000 0011 1001 */
2096		{LTA,"B,A" }, /* 3a: 0110 0000 0011 1010 */
2097		{LTA,"C,A" }, /* 3b: 0110 0000 0011 1011 */
2098		{LTA,"D,A" }, /* 3c: 0110 0000 0011 1100 */
2099		{LTA,"E,A" }, /* 3d: 0110 0000 0011 1101 */
2100		{LTA,"H,A" }, /* 3e: 0110 0000 0011 1110 */
2101		{LTA,"L,A" }, /* 3f: 0110 0000 0011 1111 */
2102
2103		{ADD,"V,A" }, /* 40: 0110 0000 0100 0000 */
2104		{ADD,"A,A" }, /* 41: 0110 0000 0100 0001 */
2105		{ADD,"B,A" }, /* 42: 0110 0000 0100 0010 */
2106		{ADD,"C,A" }, /* 43: 0110 0000 0100 0011 */
2107		{ADD,"D,A" }, /* 44: 0110 0000 0100 0100 */
2108		{ADD,"E,A" }, /* 45: 0110 0000 0100 0101 */
2109		{ADD,"H,A" }, /* 46: 0110 0000 0100 0110 */
2110		{ADD,"L,A" }, /* 47: 0110 0000 0100 0111 */
2111		{illegal,0 }, /* 48: 0110 0000 0100 1000 */
2112		{illegal,0 }, /* 49: 0110 0000 0100 1001 */
2113		{illegal,0 }, /* 4a: 0110 0000 0100 1010 */
2114		{illegal,0 }, /* 4b: 0110 0000 0100 1011 */
2115		{illegal,0 }, /* 4c: 0110 0000 0100 1100 */
2116		{illegal,0 }, /* 4d: 0110 0000 0100 1101 */
2117		{illegal,0 }, /* 4e: 0110 0000 0100 1110 */
2118		{illegal,0 }, /* 4f: 0110 0000 0100 1111 */
2119
2120		{ADC,"V,A" }, /* 50: 0110 0000 0101 0000 */
2121		{ADC,"A,A" }, /* 51: 0110 0000 0101 0001 */
2122		{ADC,"B,A" }, /* 52: 0110 0000 0101 0010 */
2123		{ADC,"C,A" }, /* 53: 0110 0000 0101 0011 */
2124		{ADC,"D,A" }, /* 54: 0110 0000 0101 0100 */
2125		{ADC,"E,A" }, /* 55: 0110 0000 0101 0101 */
2126		{ADC,"H,A" }, /* 56: 0110 0000 0101 0110 */
2127		{ADC,"L,A" }, /* 57: 0110 0000 0101 0111 */
2128		{illegal,0 }, /* 58: 0110 0000 0101 1000 */
2129		{illegal,0 }, /* 59: 0110 0000 0101 1001 */
2130		{illegal,0 }, /* 5a: 0110 0000 0101 1010 */
2131		{illegal,0 }, /* 5b: 0110 0000 0101 1011 */
2132		{illegal,0 }, /* 5c: 0110 0000 0101 1100 */
2133		{illegal,0 }, /* 5d: 0110 0000 0101 1101 */
2134		{illegal,0 }, /* 5e: 0110 0000 0101 1110 */
2135		{illegal,0 }, /* 5f: 0110 0000 0101 1111 */
2136
2137		{SUB,"V,A" }, /* 60: 0110 0000 0110 0000 */
2138		{SUB,"A,A" }, /* 61: 0110 0000 0110 0001 */
2139		{SUB,"B,A" }, /* 62: 0110 0000 0110 0010 */
2140		{SUB,"C,A" }, /* 63: 0110 0000 0110 0011 */
2141		{SUB,"D,A" }, /* 64: 0110 0000 0110 0100 */
2142		{SUB,"E,A" }, /* 65: 0110 0000 0110 0101 */
2143		{SUB,"H,A" }, /* 66: 0110 0000 0110 0110 */
2144		{SUB,"L,A" }, /* 67: 0110 0000 0110 0111 */
2145		{NEA,"V,A" }, /* 68: 0110 0000 0110 1000 */
2146		{NEA,"A,A" }, /* 69: 0110 0000 0110 1001 */
2147		{NEA,"B,A" }, /* 6a: 0110 0000 0110 1010 */
2148		{NEA,"C,A" }, /* 6b: 0110 0000 0110 1011 */
2149		{NEA,"D,A" }, /* 6c: 0110 0000 0110 1100 */
2150		{NEA,"E,A" }, /* 6d: 0110 0000 0110 1101 */
2151		{NEA,"H,A" }, /* 6e: 0110 0000 0110 1110 */
2152		{NEA,"L,A" }, /* 6f: 0110 0000 0110 1111 */
2153
2154		{SBB,"V,A" }, /* 70: 0110 0000 0111 0000 */
2155		{SBB,"A,A" }, /* 71: 0110 0000 0111 0001 */
2156		{SBB,"B,A" }, /* 72: 0110 0000 0111 0010 */
2157		{SBB,"C,A" }, /* 73: 0110 0000 0111 0011 */
2158		{SBB,"D,A" }, /* 74: 0110 0000 0111 0100 */
2159		{SBB,"E,A" }, /* 75: 0110 0000 0111 0101 */
2160		{SBB,"H,A" }, /* 76: 0110 0000 0111 0110 */
2161		{SBB,"L,A" }, /* 77: 0110 0000 0111 0111 */
2162		{EQA,"V,A" }, /* 78: 0110 0000 0111 1000 */
2163		{EQA,"A,A" }, /* 79: 0110 0000 0111 1001 */
2164		{EQA,"B,A" }, /* 7a: 0110 0000 0111 1010 */
2165		{EQA,"C,A" }, /* 7b: 0110 0000 0111 1011 */
2166		{EQA,"D,A" }, /* 7c: 0110 0000 0111 1100 */
2167		{EQA,"E,A" }, /* 7d: 0110 0000 0111 1101 */
2168		{EQA,"H,A" }, /* 7e: 0110 0000 0111 1110 */
2169		{EQA,"L,A" }, /* 7f: 0110 0000 0111 1111 */
2170
2171		{illegal,0 }, /* 80: 0110 0000 1000 0000 */
2172		{illegal,0 }, /* 81: 0110 0000 1000 0001 */
2173		{illegal,0 }, /* 82: 0110 0000 1000 0010 */
2174		{illegal,0 }, /* 83: 0110 0000 1000 0011 */
2175		{illegal,0 }, /* 84: 0110 0000 1000 0100 */
2176		{illegal,0 }, /* 85: 0110 0000 1000 0101 */
2177		{illegal,0 }, /* 86: 0110 0000 1000 0110 */
2178		{illegal,0 }, /* 87: 0110 0000 1000 0111 */
2179		{ANA,"A,V" }, /* 88: 0110 0000 1000 1000 */
2180		{ANA,"A,A" }, /* 89: 0110 0000 1000 1001 */
2181		{ANA,"A,B" }, /* 8a: 0110 0000 1000 1010 */
2182		{ANA,"A,C" }, /* 8b: 0110 0000 1000 1011 */
2183		{ANA,"A,D" }, /* 8c: 0110 0000 1000 1100 */
2184		{ANA,"A,E" }, /* 8d: 0110 0000 1000 1101 */
2185		{ANA,"A,H" }, /* 8e: 0110 0000 1000 1110 */
2186		{ANA,"A,L" }, /* 8f: 0110 0000 1000 1111 */
2187
2188		{XRA,"A,V" }, /* 90: 0110 0000 1001 0000 */
2189		{XRA,"A,A" }, /* 91: 0110 0000 1001 0001 */
2190		{XRA,"A,B" }, /* 92: 0110 0000 1001 0010 */
2191		{XRA,"A,C" }, /* 93: 0110 0000 1001 0011 */
2192		{XRA,"A,D" }, /* 94: 0110 0000 1001 0100 */
2193		{XRA,"A,E" }, /* 95: 0110 0000 1001 0101 */
2194		{XRA,"A,H" }, /* 96: 0110 0000 1001 0110 */
2195		{XRA,"A,L" }, /* 97: 0110 0000 1001 0111 */
2196		{ORA,"A,V" }, /* 98: 0110 0000 1001 1000 */
2197		{ORA,"A,A" }, /* 99: 0110 0000 1001 1001 */
2198		{ORA,"A,B" }, /* 9a: 0110 0000 1001 1010 */
2199		{ORA,"A,C" }, /* 9b: 0110 0000 1001 1011 */
2200		{ORA,"A,D" }, /* 9c: 0110 0000 1001 1100 */
2201		{ORA,"A,E" }, /* 9d: 0110 0000 1001 1101 */
2202		{ORA,"A,H" }, /* 9e: 0110 0000 1001 1110 */
2203		{ORA,"A,L" }, /* 9f: 0110 0000 1001 1111 */
2204
2205		{ADDNC,"A,V" }, /* a0: 0110 0000 1010 0000 */
2206		{ADDNC,"A,A" }, /* a1: 0110 0000 1010 0001 */
2207		{ADDNC,"A,B" }, /* a2: 0110 0000 1010 0010 */
2208		{ADDNC,"A,C" }, /* a3: 0110 0000 1010 0011 */
2209		{ADDNC,"A,D" }, /* a4: 0110 0000 1010 0100 */
2210		{ADDNC,"A,E" }, /* a5: 0110 0000 1010 0101 */
2211		{ADDNC,"A,H" }, /* a6: 0110 0000 1010 0110 */
2212		{ADDNC,"A,L" }, /* a7: 0110 0000 1010 0111 */
2213		{GTA,"A,V" }, /* a8: 0110 0000 1010 1000 */
2214		{GTA,"A,A" }, /* a9: 0110 0000 1010 1001 */
2215		{GTA,"A,B" }, /* aa: 0110 0000 1010 1010 */
2216		{GTA,"A,C" }, /* ab: 0110 0000 1010 1011 */
2217		{GTA,"A,D" }, /* ac: 0110 0000 1010 1100 */
2218		{GTA,"A,E" }, /* ad: 0110 0000 1010 1101 */
2219		{GTA,"A,H" }, /* ae: 0110 0000 1010 1110 */
2220		{GTA,"A,L" }, /* af: 0110 0000 1010 1111 */
2221
2222		{SUBNB,"A,V" }, /* b0: 0110 0000 1011 0000 */
2223		{SUBNB,"A,A" }, /* b1: 0110 0000 1011 0001 */
2224		{SUBNB,"A,B" }, /* b2: 0110 0000 1011 0010 */
2225		{SUBNB,"A,C" }, /* b3: 0110 0000 1011 0011 */
2226		{SUBNB,"A,D" }, /* b4: 0110 0000 1011 0100 */
2227		{SUBNB,"A,E" }, /* b5: 0110 0000 1011 0101 */
2228		{SUBNB,"A,H" }, /* b6: 0110 0000 1011 0110 */
2229		{SUBNB,"A,L" }, /* b7: 0110 0000 1011 0111 */
2230		{LTA,"A,V" }, /* b8: 0110 0000 1011 1000 */
2231		{LTA,"A,A" }, /* b9: 0110 0000 1011 1001 */
2232		{LTA,"A,B" }, /* ba: 0110 0000 1011 1010 */
2233		{LTA,"A,C" }, /* bb: 0110 0000 1011 1011 */
2234		{LTA,"A,D" }, /* bc: 0110 0000 1011 1100 */
2235		{LTA,"A,E" }, /* bd: 0110 0000 1011 1101 */
2236		{LTA,"A,H" }, /* be: 0110 0000 1011 1110 */
2237		{LTA,"A,L" }, /* bf: 0110 0000 1011 1111 */
2238
2239		{ADD,"A,V" }, /* c0: 0110 0000 1100 0000 */
2240		{ADD,"A,A" }, /* c1: 0110 0000 1100 0001 */
2241		{ADD,"A,B" }, /* c2: 0110 0000 1100 0010 */
2242		{ADD,"A,C" }, /* c3: 0110 0000 1100 0011 */
2243		{ADD,"A,D" }, /* c4: 0110 0000 1100 0100 */
2244		{ADD,"A,E" }, /* c5: 0110 0000 1100 0101 */
2245		{ADD,"A,H" }, /* c6: 0110 0000 1100 0110 */
2246		{ADD,"A,L" }, /* c7: 0110 0000 1100 0111 */
2247		{ONA,"A,V" }, /* c8: 0110 0000 1100 1000 */
2248		{ONA,"A,A" }, /* c9: 0110 0000 1100 1001 */
2249		{ONA,"A,B" }, /* ca: 0110 0000 1100 1010 */
2250		{ONA,"A,C" }, /* cb: 0110 0000 1100 1011 */
2251		{ONA,"A,D" }, /* cc: 0110 0000 1100 1100 */
2252		{ONA,"A,E" }, /* cd: 0110 0000 1100 1101 */
2253		{ONA,"A,H" }, /* ce: 0110 0000 1100 1110 */
2254		{ONA,"A,L" }, /* cf: 0110 0000 1100 1111 */
2255
2256		{ADC,"A,V" }, /* d0: 0110 0000 1101 0000 */
2257		{ADC,"A,A" }, /* d1: 0110 0000 1101 0001 */
2258		{ADC,"A,B" }, /* d2: 0110 0000 1101 0010 */
2259		{ADC,"A,C" }, /* d3: 0110 0000 1101 0011 */
2260		{ADC,"A,D" }, /* d4: 0110 0000 1101 0100 */
2261		{ADC,"A,E" }, /* d5: 0110 0000 1101 0101 */
2262		{ADC,"A,H" }, /* d6: 0110 0000 1101 0110 */
2263		{ADC,"A,L" }, /* d7: 0110 0000 1101 0111 */
2264		{OFFA,"A,V" }, /* d8: 0110 0000 1101 1000 */
2265		{OFFA,"A,A" }, /* d9: 0110 0000 1101 1001 */
2266		{OFFA,"A,B" }, /* da: 0110 0000 1101 1010 */
2267		{OFFA,"A,C" }, /* db: 0110 0000 1101 1011 */
2268		{OFFA,"A,D" }, /* dc: 0110 0000 1101 1100 */
2269		{OFFA,"A,E" }, /* dd: 0110 0000 1101 1101 */
2270		{OFFA,"A,H" }, /* de: 0110 0000 1101 1110 */
2271		{OFFA,"A,L" }, /* df: 0110 0000 1101 1111 */
2272
2273		{SUB,"A,V" }, /* e0: 0110 0000 1110 0000 */
2274		{SUB,"A,A" }, /* e1: 0110 0000 1110 0001 */
2275		{SUB,"A,B" }, /* e2: 0110 0000 1110 0010 */
2276		{SUB,"A,C" }, /* e3: 0110 0000 1110 0011 */
2277		{SUB,"A,D" }, /* e4: 0110 0000 1110 0100 */
2278		{SUB,"A,E" }, /* e5: 0110 0000 1110 0101 */
2279		{SUB,"A,H" }, /* e6: 0110 0000 1110 0110 */
2280		{SUB,"A,L" }, /* e7: 0110 0000 1110 0111 */
2281		{NEA,"A,V" }, /* e8: 0110 0000 1110 1000 */
2282		{NEA,"A,A" }, /* e9: 0110 0000 1110 1001 */
2283		{NEA,"A,B" }, /* ea: 0110 0000 1110 1010 */
2284		{NEA,"A,C" }, /* eb: 0110 0000 1110 1011 */
2285		{NEA,"A,D" }, /* ec: 0110 0000 1110 1100 */
2286		{NEA,"A,E" }, /* ed: 0110 0000 1110 1101 */
2287		{NEA,"A,H" }, /* ee: 0110 0000 1110 1110 */
2288		{NEA,"A,L" }, /* ef: 0110 0000 1110 1111 */
2289
2290		{SBB,"A,V" }, /* f0: 0110 0000 1111 0000 */
2291		{SBB,"A,A" }, /* f1: 0110 0000 1111 0001 */
2292		{SBB,"A,B" }, /* f2: 0110 0000 1111 0010 */
2293		{SBB,"A,C" }, /* f3: 0110 0000 1111 0011 */
2294		{SBB,"A,D" }, /* f4: 0110 0000 1111 0100 */
2295		{SBB,"A,E" }, /* f5: 0110 0000 1111 0101 */
2296		{SBB,"A,H" }, /* f6: 0110 0000 1111 0110 */
2297		{SBB,"A,L" }, /* f7: 0110 0000 1111 0111 */
2298		{EQA,"A,V" }, /* f8: 0110 0000 1111 1000 */
2299		{EQA,"A,A" }, /* f9: 0110 0000 1111 1001 */
2300		{EQA,"A,B" }, /* fa: 0110 0000 1111 1010 */
2301		{EQA,"A,C" }, /* fb: 0110 0000 1111 1011 */
2302		{EQA,"A,D" }, /* fc: 0110 0000 1111 1100 */
2303		{EQA,"A,E" }, /* fd: 0110 0000 1111 1101 */
2304		{EQA,"A,H" }, /* fe: 0110 0000 1111 1110 */
2305		{EQA,"A,L" } /* ff: 0110 0000 1111 1111 */
2306		};
2307
2308		/* prefix 64 */
2309		static const struct dasm_s dasm64_7810[256] =
2310		{
2311		{MVI,"PA,%b" }, /* 00: 0110 0100 0000 0000 xxxx xxxx */
2312		{MVI,"PB,%b" }, /* 01: 0110 0100 0000 0001 xxxx xxxx */
2313		{MVI,"PC,%b" }, /* 02: 0110 0100 0000 0010 xxxx xxxx */
2314		{MVI,"PD,%b" }, /* 03: 0110 0100 0000 0011 xxxx xxxx */
2315		{illegal,0 }, /* 04: 0110 0100 0000 0100 xxxx xxxx */
2316		{MVI,"PF,%b" }, /* 05: 0110 0100 0000 0101 xxxx xxxx */
2317		{MVI,"MKH,%b" }, /* 06: 0110 0100 0000 0110 xxxx xxxx */
2318		{MVI,"MKL,%b" }, /* 07: 0110 0100 0000 0111 xxxx xxxx */
2319		{ANI,"PA,%b" }, /* 08: 0110 0100 0000 1000 xxxx xxxx */
2320		{ANI,"PB,%b" }, /* 09: 0110 0100 0000 1001 xxxx xxxx */
2321		{ANI,"PC,%b" }, /* 0a: 0110 0100 0000 1010 xxxx xxxx */
2322		{ANI,"PD,%b" }, /* 0b: 0110 0100 0000 1011 xxxx xxxx */
2323		{illegal,0 }, /* 0c: 0110 0100 0000 1100 xxxx xxxx */
2324		{ANI,"PF,%b" }, /* 0d: 0110 0100 0000 1101 xxxx xxxx */
2325		{ANI,"MKH,%b" }, /* 0e: 0110 0100 0000 1110 xxxx xxxx */
2326		{ANI,"MKL,%b" }, /* 0f: 0110 0100 0000 1111 xxxx xxxx */
2327
2328		{XRI,"PA,%b" }, /* 10: 0110 0100 0001 0000 xxxx xxxx */
2329		{XRI,"PB,%b" }, /* 11: 0110 0100 0001 0001 xxxx xxxx */
2330		{XRI,"PC,%b" }, /* 12: 0110 0100 0001 0010 xxxx xxxx */
2331		{XRI,"PD,%b" }, /* 13: 0110 0100 0001 0011 xxxx xxxx */
2332		{illegal,0 }, /* 14: 0110 0100 0001 0100 xxxx xxxx */
2333		{XRI,"PF,%b" }, /* 15: 0110 0100 0001 0101 xxxx xxxx */
2334		{XRI,"MKH,%b" }, /* 16: 0110 0100 0001 0110 xxxx xxxx */
2335		{XRI,"MKL,%b" }, /* 17: 0110 0100 0001 0111 xxxx xxxx */
2336		{ORI,"PA,%b" }, /* 18: 0110 0100 0001 1000 xxxx xxxx */
2337		{ORI,"PB,%b" }, /* 19: 0110 0100 0001 1001 xxxx xxxx */
2338		{ORI,"PC,%b" }, /* 1a: 0110 0100 0001 1010 xxxx xxxx */
2339		{ORI,"PD,%b" }, /* 1b: 0110 0100 0001 1011 xxxx xxxx */
2340		{illegal,0 }, /* 1c: 0110 0100 0001 1100 xxxx xxxx */
2341		{ORI,"PF,%b" }, /* 1d: 0110 0100 0001 1101 xxxx xxxx */
2342		{ORI,"MKH,%b" }, /* 1e: 0110 0100 0001 1110 xxxx xxxx */
2343		{ORI,"MKL,%b" }, /* 1f: 0110 0100 0001 1111 xxxx xxxx */
2344
2345		{ADINC,"PA,%b" }, /* 20: 0110 0100 0010 0000 xxxx xxxx */
2346		{ADINC,"PB,%b" }, /* 21: 0110 0100 0010 0001 xxxx xxxx */
2347		{ADINC,"PC,%b" }, /* 22: 0110 0100 0010 0010 xxxx xxxx */
2348		{ADINC,"PD,%b" }, /* 23: 0110 0100 0010 0011 xxxx xxxx */
2349		{illegal,0 }, /* 24: 0110 0100 0010 0100 xxxx xxxx */
2350		{ADINC,"PF,%b" }, /* 25: 0110 0100 0010 0101 xxxx xxxx */
2351		{ADINC,"MKH,%b" }, /* 26: 0110 0100 0010 0110 xxxx xxxx */
2352		{ADINC,"MKL,%b" }, /* 27: 0110 0100 0010 0111 xxxx xxxx */
2353		{GTI,"PA,%b" }, /* 28: 0110 0100 0010 1000 xxxx xxxx */
2354		{GTI,"PB,%b" }, /* 29: 0110 0100 0010 1001 xxxx xxxx */
2355		{GTI,"PC,%b" }, /* 2a: 0110 0100 0010 1010 xxxx xxxx */
2356		{GTI,"PD,%b" }, /* 2b: 0110 0100 0010 1011 xxxx xxxx */
2357		{illegal,0 }, /* 2c: 0110 0100 0010 1100 xxxx xxxx */
2358		{GTI,"PF,%b" }, /* 2d: 0110 0100 0010 1101 xxxx xxxx */
2359		{GTI,"MKH,%b" }, /* 2e: 0110 0100 0010 1110 xxxx xxxx */
2360		{GTI,"MKL,%b" }, /* 2f: 0110 0100 0010 1111 xxxx xxxx */
2361
2362		{SUINB,"PA,%b" }, /* 30: 0110 0100 0011 0000 xxxx xxxx */
2363		{SUINB,"PB,%b" }, /* 31: 0110 0100 0011 0001 xxxx xxxx */
2364		{SUINB,"PC,%b" }, /* 32: 0110 0100 0011 0010 xxxx xxxx */
2365		{SUINB,"PD,%b" }, /* 33: 0110 0100 0011 0011 xxxx xxxx */
2366		{illegal,0 }, /* 34: 0110 0100 0011 0100 xxxx xxxx */
2367		{SUINB,"PF,%b" }, /* 35: 0110 0100 0011 0101 xxxx xxxx */
2368		{SUINB,"MKH,%b" }, /* 36: 0110 0100 0011 0110 xxxx xxxx */
2369		{SUINB,"MKL,%b" }, /* 37: 0110 0100 0011 0111 xxxx xxxx */
2370		{LTI,"PA,%b" }, /* 38: 0110 0100 0011 1000 xxxx xxxx */
2371		{LTI,"PB,%b" }, /* 39: 0110 0100 0011 1001 xxxx xxxx */
2372		{LTI,"PC,%b" }, /* 3a: 0110 0100 0011 1010 xxxx xxxx */
2373		{LTI,"PD,%b" }, /* 3b: 0110 0100 0011 1011 xxxx xxxx */
2374		{illegal,0 }, /* 3c: 0110 0100 0011 1100 xxxx xxxx */
2375		{LTI,"PF,%b" }, /* 3d: 0110 0100 0011 1101 xxxx xxxx */
2376		{LTI,"MKH,%b" }, /* 3e: 0110 0100 0011 1110 xxxx xxxx */
2377		{LTI,"MKL,%b" }, /* 3f: 0110 0100 0011 1111 xxxx xxxx */
2378
2379		{ADI,"PA,%b" }, /* 40: 0110 0100 0100 0000 xxxx xxxx */
2380		{ADI,"PB,%b" }, /* 41: 0110 0100 0100 0001 xxxx xxxx */
2381		{ADI,"PC,%b" }, /* 42: 0110 0100 0100 0010 xxxx xxxx */
2382		{ADI,"PD,%b" }, /* 43: 0110 0100 0100 0011 xxxx xxxx */
2383		{illegal,0 }, /* 44: 0110 0100 0100 0100 xxxx xxxx */
2384		{ADI,"PF,%b" }, /* 45: 0110 0100 0100 0101 xxxx xxxx */
2385		{ADI,"MKH,%b" }, /* 46: 0110 0100 0100 0110 xxxx xxxx */
2386		{ADI,"MKL,%b" }, /* 47: 0110 0100 0100 0111 xxxx xxxx */
2387		{ONI,"PA,%b" }, /* 48: 0110 0100 0100 1000 xxxx xxxx */
2388		{ONI,"PB,%b" }, /* 49: 0110 0100 0100 1001 xxxx xxxx */
2389		{ONI,"PC,%b" }, /* 4a: 0110 0100 0100 1010 xxxx xxxx */
2390		{ONI,"PD,%b" }, /* 4b: 0110 0100 0100 1011 xxxx xxxx */
2391		{illegal,0 }, /* 4c: 0110 0100 0100 1100 xxxx xxxx */
2392		{ONI,"PF,%b" }, /* 4d: 0110 0100 0100 1101 xxxx xxxx */
2393		{ONI,"MKH,%b" }, /* 4e: 0110 0100 0100 1110 xxxx xxxx */
2394		{ONI,"MKL,%b" }, /* 4f: 0110 0100 0100 1111 xxxx xxxx */
2395
2396		{ACI,"PA,%b" }, /* 50: 0110 0100 0101 0000 xxxx xxxx */
2397		{ACI,"PB,%b" }, /* 51: 0110 0100 0101 0001 xxxx xxxx */
2398		{ACI,"PC,%b" }, /* 52: 0110 0100 0101 0010 xxxx xxxx */
2399		{ACI,"PD,%b" }, /* 53: 0110 0100 0101 0011 xxxx xxxx */
2400		{illegal,0 }, /* 54: 0110 0100 0101 0100 xxxx xxxx */
2401		{ACI,"PF,%b" }, /* 55: 0110 0100 0101 0101 xxxx xxxx */
2402		{ACI,"MKH,%b" }, /* 56: 0110 0100 0101 0110 xxxx xxxx */
2403		{ACI,"MKL,%b" }, /* 57: 0110 0100 0101 0111 xxxx xxxx */
2404		{OFFI,"PA,%b" }, /* 58: 0110 0100 0101 1000 xxxx xxxx */
2405		{OFFI,"PB,%b" }, /* 59: 0110 0100 0101 1001 xxxx xxxx */
2406		{OFFI,"PC,%b" }, /* 5a: 0110 0100 0101 1010 xxxx xxxx */
2407		{OFFI,"PD,%b" }, /* 5b: 0110 0100 0101 1011 xxxx xxxx */
2408		{illegal,0 }, /* 5c: 0110 0100 0101 1100 xxxx xxxx */
2409		{OFFI,"PF,%b" }, /* 5d: 0110 0100 0101 1101 xxxx xxxx */
2410		{OFFI,"MKH,%b" }, /* 5e: 0110 0100 0101 1110 xxxx xxxx */
2411		{OFFI,"MKL,%b" }, /* 5f: 0110 0100 0101 1111 xxxx xxxx */
2412
2413		{SUI,"PA,%b" }, /* 60: 0110 0100 0110 0000 xxxx xxxx */
2414		{SUI,"PB,%b" }, /* 61: 0110 0100 0110 0001 xxxx xxxx */
2415		{SUI,"PC,%b" }, /* 62: 0110 0100 0110 0010 xxxx xxxx */
2416		{SUI,"PD,%b" }, /* 63: 0110 0100 0110 0011 xxxx xxxx */
2417		{illegal,0 }, /* 64: 0110 0100 0110 0100 xxxx xxxx */
2418		{SUI,"PF,%b" }, /* 65: 0110 0100 0110 0101 xxxx xxxx */
2419		{SUI,"MKH,%b" }, /* 66: 0110 0100 0110 0110 xxxx xxxx */
2420		{SUI,"MKL,%b" }, /* 67: 0110 0100 0110 0111 xxxx xxxx */
2421		{NEI,"PA,%b" }, /* 68: 0110 0100 0110 1000 xxxx xxxx */
2422		{NEI,"PB,%b" }, /* 69: 0110 0100 0110 1001 xxxx xxxx */
2423		{NEI,"PC,%b" }, /* 6a: 0110 0100 0110 1010 xxxx xxxx */
2424		{NEI,"PD,%b" }, /* 6b: 0110 0100 0110 1011 xxxx xxxx */
2425		{illegal,0 }, /* 6c: 0110 0100 0110 1100 xxxx xxxx */
2426		{NEI,"PF,%b" }, /* 6d: 0110 0100 0110 1101 xxxx xxxx */
2427		{NEI,"MKH,%b" }, /* 6e: 0110 0100 0110 1110 xxxx xxxx */
2428		{NEI,"MKL,%b" }, /* 6f: 0110 0100 0110 1111 xxxx xxxx */
2429
2430		{SBI,"PA,%b" }, /* 70: 0110 0100 0111 0000 xxxx xxxx */
2431		{SBI,"PB,%b" }, /* 71: 0110 0100 0111 0001 xxxx xxxx */
2432		{SBI,"PC,%b" }, /* 72: 0110 0100 0111 0010 xxxx xxxx */
2433		{SBI,"PD,%b" }, /* 73: 0110 0100 0111 0011 xxxx xxxx */
2434		{illegal,0 }, /* 74: 0110 0100 0111 0100 xxxx xxxx */
2435		{SBI,"PF,%b" }, /* 75: 0110 0100 0111 0101 xxxx xxxx */
2436		{SBI,"MKH,%b" }, /* 76: 0110 0100 0111 0110 xxxx xxxx */
2437		{SBI,"MKL,%b" }, /* 77: 0110 0100 0111 0111 xxxx xxxx */
2438		{EQI,"PA,%b" }, /* 78: 0110 0100 0111 1000 xxxx xxxx */
2439		{EQI,"PB,%b" }, /* 79: 0110 0100 0111 1001 xxxx xxxx */
2440		{EQI,"PC,%b" }, /* 7a: 0110 0100 0111 1010 xxxx xxxx */
2441		{EQI,"PD,%b" }, /* 7b: 0110 0100 0111 1011 xxxx xxxx */
2442		{illegal,0 }, /* 7c: 0110 0100 0111 1100 xxxx xxxx */
2443		{EQI,"PF,%b" }, /* 7d: 0110 0100 0111 1101 xxxx xxxx */
2444		{EQI,"MKH,%b" }, /* 7e: 0110 0100 0111 1110 xxxx xxxx */
2445		{EQI,"MKL,%b" }, /* 7f: 0110 0100 0111 1111 xxxx xxxx */
2446
2447		{MVI,"ANM,%b" }, /* 80: 0110 0100 1000 0000 xxxx xxxx / / 7810 */
2448		{MVI,"SMH,%b" }, /* 81: 0110 0100 1000 0001 xxxx xxxx */
2449		{illegal,0 }, /* 82: 0110 0100 1000 0010 xxxx xxxx */
2450		{MVI,"EOM,%b" }, /* 83: 0110 0100 1000 0011 xxxx xxxx */
2451		{illegal,0 }, /* 84: 0110 0100 1000 0100 xxxx xxxx */
2452		{MVI,"TMM,%b" }, /* 85: 0110 0100 1000 0101 xxxx xxxx */
2453		{illegal,0 }, /* 86: 0110 0100 1000 0110 xxxx xxxx */
2454		{illegal,0 }, /* 87: 0110 0100 1000 0111 xxxx xxxx */
2455		{ANI,"ANM,%b" }, /* 88: 0110 0100 1000 1000 xxxx xxxx / / 7810 */
2456		{ANI,"SMH,%b" }, /* 89: 0110 0100 1000 1001 xxxx xxxx */
2457		{illegal,0 }, /* 8a: 0110 0100 1000 1010 xxxx xxxx */
2458		{ANI,"EOM,%b" }, /* 8b: 0110 0100 1000 1011 xxxx xxxx */
2459		{illegal,0 }, /* 8c: 0110 0100 1000 1100 xxxx xxxx */
2460		{ANI,"TMM,%b" }, /* 8d: 0110 0100 1000 1101 xxxx xxxx */
2461		{illegal,0 }, /* 8e: 0110 0100 1000 1110 xxxx xxxx */
2462		{illegal,0 }, /* 8f: 0110 0100 1000 1111 xxxx xxxx */
2463
2464		{XRI,"ANM,%b" }, /* 90: 0110 0100 1001 0000 xxxx xxxx / / 7810 */
2465		{XRI,"SMH,%b" }, /* 91: 0110 0100 1001 0001 xxxx xxxx */
2466		{illegal,0 }, /* 92: 0110 0100 1001 0010 xxxx xxxx */
2467		{XRI,"EOM,%b" }, /* 93: 0110 0100 1001 0011 xxxx xxxx */
2468		{illegal,0 }, /* 94: 0110 0100 1001 0100 xxxx xxxx */
2469		{XRI,"TMM,%b" }, /* 95: 0110 0100 1001 0101 xxxx xxxx */
2470		{illegal,0 }, /* 96: 0110 0100 1001 0110 xxxx xxxx */
2471		{illegal,0 }, /* 97: 0110 0100 1001 0111 xxxx xxxx */
2472		{ORI,"ANM,%b" }, /* 98: 0110 0100 1001 1000 xxxx xxxx / / 7810 */
2473		{ORI,"SMH,%b" }, /* 99: 0110 0100 1001 1001 xxxx xxxx */
2474		{illegal,0 }, /* 9a: 0110 0100 1001 1010 xxxx xxxx */
2475		{ORI,"EOM,%b" }, /* 9b: 0110 0100 1001 1011 xxxx xxxx */
2476		{illegal,0 }, /* 9c: 0110 0100 1001 1100 xxxx xxxx */
2477		{ORI,"TMM,%b" }, /* 9d: 0110 0100 1001 1101 xxxx xxxx */
2478		{illegal,0 }, /* 9e: 0110 0100 1001 1110 xxxx xxxx */
2479		{illegal,0 }, /* 9f: 0110 0100 1001 1111 xxxx xxxx */
2480
2481		{ADINC,"ANM,%b" }, /* a0: 0110 0100 1010 0000 xxxx xxxx / / 7810 */
2482		{ADINC,"SMH,%b" }, /* a1: 0110 0100 1010 0001 xxxx xxxx */
2483		{illegal,0 }, /* a2: 0110 0100 1010 0010 xxxx xxxx */
2484		{ADINC,"EOM,%b" }, /* a3: 0110 0100 1010 0011 xxxx xxxx */
2485		{illegal,0 }, /* a4: 0110 0100 1010 0100 xxxx xxxx */
2486		{ADINC,"TMM,%b" }, /* a5: 0110 0100 1010 0101 xxxx xxxx */
2487		{illegal,0 }, /* a6: 0110 0100 1010 0110 xxxx xxxx */
2488		{illegal,0 }, /* a7: 0110 0100 1010 0111 xxxx xxxx */
2489		{GTI,"ANM,%b" }, /* a8: 0110 0100 1010 1000 xxxx xxxx / / 7810 */
2490		{GTI,"SMH,%b" }, /* a9: 0110 0100 1010 1001 xxxx xxxx */
2491		{illegal,0 }, /* aa: 0110 0100 1010 1010 xxxx xxxx */
2492		{GTI,"EOM,%b" }, /* ab: 0110 0100 1010 1011 xxxx xxxx */
2493		{illegal,0 }, /* ac: 0110 0100 1010 1100 xxxx xxxx */
2494		{GTI,"TMM,%b" }, /* ad: 0110 0100 1010 1101 xxxx xxxx */
2495		{illegal,0 }, /* ae: 0110 0100 1010 1110 xxxx xxxx */
2496		{illegal,0 }, /* af: 0110 0100 1010 1111 xxxx xxxx */
2497
2498		{SUINB,"ANM,%b" }, /* b0: 0110 0100 1011 0000 xxxx xxxx / / 7810 */
2499		{SUINB,"SMH,%b" }, /* b1: 0110 0100 1011 0001 xxxx xxxx */
2500		{illegal,0 }, /* b2: 0110 0100 1011 0010 xxxx xxxx */
2501		{SUINB,"EOM,%b" }, /* b3: 0110 0100 1011 0011 xxxx xxxx */
2502		{illegal,0 }, /* b4: 0110 0100 1011 0100 xxxx xxxx */
2503		{SUINB,"TMM,%b" }, /* b5: 0110 0100 1011 0101 xxxx xxxx */
2504		{illegal,0 }, /* b6: 0110 0100 1011 0110 xxxx xxxx */
2505		{illegal,0 }, /* b7: 0110 0100 1011 0111 xxxx xxxx */
2506		{LTI,"ANM,%b" }, /* b8: 0110 0100 1011 1000 xxxx xxxx / / 7810 */
2507		{LTI,"SMH,%b" }, /* b9: 0110 0100 1011 1001 xxxx xxxx */
2508		{illegal,0 }, /* ba: 0110 0100 1011 1010 xxxx xxxx */
2509		{LTI,"EOM,%b" }, /* bb: 0110 0100 1011 1011 xxxx xxxx */
2510		{illegal,0 }, /* bc: 0110 0100 1011 1100 xxxx xxxx */
2511		{LTI,"TMM,%b" }, /* bd: 0110 0100 1011 1101 xxxx xxxx */
2512		{illegal,0 }, /* be: 0110 0100 1011 1110 xxxx xxxx */
2513		{illegal,0 }, /* bf: 0110 0100 1011 1111 xxxx xxxx */
2514
2515		{ADI,"ANM,%b" }, /* c0: 0110 0100 1100 0000 xxxx xxxx / / 7810 */
2516		{ADI,"SMH,%b" }, /* c1: 0110 0100 1100 0001 xxxx xxxx */
2517		{illegal,0 }, /* c2: 0110 0100 1100 0010 xxxx xxxx */
2518		{ADI,"EOM,%b" }, /* c3: 0110 0100 1100 0011 xxxx xxxx */
2519		{illegal,0 }, /* c4: 0110 0100 1100 0100 xxxx xxxx */
2520		{ADI,"TMM,%b" }, /* c5: 0110 0100 1100 0101 xxxx xxxx */
2521		{illegal,0 }, /* c6: 0110 0100 1100 0110 xxxx xxxx */
2522		{illegal,0 }, /* c7: 0110 0100 1100 0111 xxxx xxxx */
2523		{ONI,"ANM,%b" }, /* c8: 0110 0100 1100 1000 xxxx xxxx / / 7810 */
2524		{ONI,"SMH,%b" }, /* c9: 0110 0100 1100 1001 xxxx xxxx */
2525		{illegal,0 }, /* ca: 0110 0100 1100 1010 xxxx xxxx */
2526		{ONI,"EOM,%b" }, /* cb: 0110 0100 1100 1011 xxxx xxxx */
2527		{illegal,0 }, /* cc: 0110 0100 1100 1100 xxxx xxxx */
2528		{ONI,"TMM,%b" }, /* cd: 0110 0100 1100 1101 xxxx xxxx */
2529		{illegal,0 }, /* ce: 0110 0100 1100 1110 xxxx xxxx */
2530		{illegal,0 }, /* cf: 0110 0100 1100 1111 xxxx xxxx */
2531
2532		{ACI,"ANM,%b" }, /* d0: 0110 0100 1101 0000 xxxx xxxx / / 7810 */
2533		{ACI,"SMH,%b" }, /* d1: 0110 0100 1101 0001 xxxx xxxx */
2534		{illegal,0 }, /* d2: 0110 0100 1101 0010 xxxx xxxx */
2535		{ACI,"EOM,%b" }, /* d3: 0110 0100 1101 0011 xxxx xxxx */
2536		{illegal,0 }, /* d4: 0110 0100 1101 0100 xxxx xxxx */
2537		{ACI,"TMM,%b" }, /* d5: 0110 0100 1101 0101 xxxx xxxx */
2538		{illegal,0 }, /* d6: 0110 0100 1101 0110 xxxx xxxx */
2539		{illegal,0 }, /* d7: 0110 0100 1101 0111 xxxx xxxx */
2540		{OFFI,"ANM,%b" }, /* d8: 0110 0100 1101 1000 xxxx xxxx / / 7810 */
2541		{OFFI,"SMH,%b" }, /* d9: 0110 0100 1101 1001 xxxx xxxx */
2542		{illegal,0 }, /* da: 0110 0100 1101 1010 xxxx xxxx */
2543		{OFFI,"EOM,%b" }, /* db: 0110 0100 1101 1011 xxxx xxxx */
2544		{illegal,0 }, /* dc: 0110 0100 1101 1100 xxxx xxxx */
2545		{OFFI,"TMM,%b" }, /* dd: 0110 0100 1101 1101 xxxx xxxx */
2546		{illegal,0 }, /* de: 0110 0100 1101 1110 xxxx xxxx */
2547		{illegal,0 }, /* df: 0110 0100 1101 1111 xxxx xxxx */
2548
2549		{SUI,"ANM,%b" }, /* e0: 0110 0100 1110 0000 xxxx xxxx / / 7810 */
2550		{SUI,"SMH,%b" }, /* e1: 0110 0100 1110 0001 xxxx xxxx */
2551		{illegal,0 }, /* e2: 0110 0100 1110 0010 xxxx xxxx */
2552		{SUI,"EOM,%b" }, /* e3: 0110 0100 1110 0011 xxxx xxxx */
2553		{illegal,0 }, /* e4: 0110 0100 1110 0100 xxxx xxxx */
2554		{SUI,"TMM,%b" }, /* e5: 0110 0100 1110 0101 xxxx xxxx */
2555		{illegal,0 }, /* e6: 0110 0100 1110 0110 xxxx xxxx */
2556		{illegal,0 }, /* e7: 0110 0100 1110 0111 xxxx xxxx */
2557		{NEI,"ANM,%b" }, /* e8: 0110 0100 1110 1000 xxxx xxxx / / 7810 */
2558		{NEI,"SMH,%b" }, /* e9: 0110 0100 1110 1001 xxxx xxxx */
2559		{illegal,0 }, /* ea: 0110 0100 1110 1010 xxxx xxxx */
2560		{NEI,"EOM,%b" }, /* eb: 0110 0100 1110 1011 xxxx xxxx */
2561		{illegal,0 }, /* ec: 0110 0100 1110 1100 xxxx xxxx */
2562		{NEI,"TMM,%b" }, /* ed: 0110 0100 1110 1101 xxxx xxxx */
2563		{illegal,0 }, /* ee: 0110 0100 1110 1110 xxxx xxxx */
2564		{illegal,0 }, /* ef: 0110 0100 1110 1111 xxxx xxxx */
2565
2566		{SBI,"ANM,%b" }, /* f0: 0110 0100 1111 0000 xxxx xxxx / / 7810 */
2567		{SBI,"SMH,%b" }, /* f1: 0110 0100 1111 0001 xxxx xxxx */
2568		{illegal,0 }, /* f2: 0110 0100 1111 0010 xxxx xxxx */
2569		{SBI,"EOM,%b" }, /* f3: 0110 0100 1111 0011 xxxx xxxx */
2570		{illegal,0 }, /* f4: 0110 0100 1111 0100 xxxx xxxx */
2571		{SBI,"TMM,%b" }, /* f5: 0110 0100 1111 0101 xxxx xxxx */
2572		{illegal,0 }, /* f6: 0110 0100 1111 0110 xxxx xxxx */
2573		{illegal,0 }, /* f7: 0110 0100 1111 0111 xxxx xxxx */
2574		{EQI,"ANM,%b" }, /* f8: 0110 0100 1111 1000 xxxx xxxx / / 7810 */
2575		{EQI,"SMH,%b" }, /* f9: 0110 0100 1111 1001 xxxx xxxx */
2576		{illegal,0 }, /* fa: 0110 0100 1111 1010 xxxx xxxx */
2577		{EQI,"EOM,%b" }, /* fb: 0110 0100 1111 1011 xxxx xxxx */
2578		{illegal,0 }, /* fc: 0110 0100 1111 1100 xxxx xxxx */
2579		{EQI,"TMM,%b" }, /* fd: 0110 0100 1111 1101 xxxx xxxx */
2580		{illegal,0 }, /* fe: 0110 0100 1111 1110 xxxx xxxx */
2581		{illegal,0 } /* ff: 0110 0100 1111 1111 xxxx xxxx */
2582		};
2583
2584		static const struct dasm_s dasm64_7807[256] =
2585		{
2586		{MVI,"PA,%b" }, /* 00: 0110 0100 0000 0000 xxxx xxxx */
2587		{MVI,"PB,%b" }, /* 01: 0110 0100 0000 0001 xxxx xxxx */
2588		{MVI,"PC,%b" }, /* 02: 0110 0100 0000 0010 xxxx xxxx */
2589		{MVI,"PD,%b" }, /* 03: 0110 0100 0000 0011 xxxx xxxx */
2590		{illegal,0 }, /* 04: 0110 0100 0000 0100 xxxx xxxx */
2591		{MVI,"PF,%b" }, /* 05: 0110 0100 0000 0101 xxxx xxxx */
2592		{MVI,"MKH,%b" }, /* 06: 0110 0100 0000 0110 xxxx xxxx */
2593		{MVI,"MKL,%b" }, /* 07: 0110 0100 0000 0111 xxxx xxxx */
2594		{ANI,"PA,%b" }, /* 08: 0110 0100 0000 1000 xxxx xxxx */
2595		{ANI,"PB,%b" }, /* 09: 0110 0100 0000 1001 xxxx xxxx */
2596		{ANI,"PC,%b" }, /* 0a: 0110 0100 0000 1010 xxxx xxxx */
2597		{ANI,"PD,%b" }, /* 0b: 0110 0100 0000 1011 xxxx xxxx */
2598		{illegal,0 }, /* 0c: 0110 0100 0000 1100 xxxx xxxx */
2599		{ANI,"PF,%b" }, /* 0d: 0110 0100 0000 1101 xxxx xxxx */
2600		{ANI,"MKH,%b" }, /* 0e: 0110 0100 0000 1110 xxxx xxxx */
2601		{ANI,"MKL,%b" }, /* 0f: 0110 0100 0000 1111 xxxx xxxx */
2602
2603		{XRI,"PA,%b" }, /* 10: 0110 0100 0001 0000 xxxx xxxx */
2604		{XRI,"PB,%b" }, /* 11: 0110 0100 0001 0001 xxxx xxxx */
2605		{XRI,"PC,%b" }, /* 12: 0110 0100 0001 0010 xxxx xxxx */
2606		{XRI,"PD,%b" }, /* 13: 0110 0100 0001 0011 xxxx xxxx */
2607		{illegal,0 }, /* 14: 0110 0100 0001 0100 xxxx xxxx */
2608		{XRI,"PF,%b" }, /* 15: 0110 0100 0001 0101 xxxx xxxx */
2609		{XRI,"MKH,%b" }, /* 16: 0110 0100 0001 0110 xxxx xxxx */
2610		{XRI,"MKL,%b" }, /* 17: 0110 0100 0001 0111 xxxx xxxx */
2611		{ORI,"PA,%b" }, /* 18: 0110 0100 0001 1000 xxxx xxxx */
2612		{ORI,"PB,%b" }, /* 19: 0110 0100 0001 1001 xxxx xxxx */
2613		{ORI,"PC,%b" }, /* 1a: 0110 0100 0001 1010 xxxx xxxx */
2614		{ORI,"PD,%b" }, /* 1b: 0110 0100 0001 1011 xxxx xxxx */
2615		{illegal,0 }, /* 1c: 0110 0100 0001 1100 xxxx xxxx */
2616		{ORI,"PF,%b" }, /* 1d: 0110 0100 0001 1101 xxxx xxxx */
2617		{ORI,"MKH,%b" }, /* 1e: 0110 0100 0001 1110 xxxx xxxx */
2618		{ORI,"MKL,%b" }, /* 1f: 0110 0100 0001 1111 xxxx xxxx */
2619
2620		{ADINC,"PA,%b" }, /* 20: 0110 0100 0010 0000 xxxx xxxx */
2621		{ADINC,"PB,%b" }, /* 21: 0110 0100 0010 0001 xxxx xxxx */
2622		{ADINC,"PC,%b" }, /* 22: 0110 0100 0010 0010 xxxx xxxx */
2623		{ADINC,"PD,%b" }, /* 23: 0110 0100 0010 0011 xxxx xxxx */
2624		{illegal,0 }, /* 24: 0110 0100 0010 0100 xxxx xxxx */
2625		{ADINC,"PF,%b" }, /* 25: 0110 0100 0010 0101 xxxx xxxx */
2626		{ADINC,"MKH,%b" }, /* 26: 0110 0100 0010 0110 xxxx xxxx */
2627		{ADINC,"MKL,%b" }, /* 27: 0110 0100 0010 0111 xxxx xxxx */
2628		{GTI,"PA,%b" }, /* 28: 0110 0100 0010 1000 xxxx xxxx */
2629		{GTI,"PB,%b" }, /* 29: 0110 0100 0010 1001 xxxx xxxx */
2630		{GTI,"PC,%b" }, /* 2a: 0110 0100 0010 1010 xxxx xxxx */
2631		{GTI,"PD,%b" }, /* 2b: 0110 0100 0010 1011 xxxx xxxx */
2632		{illegal,0 }, /* 2c: 0110 0100 0010 1100 xxxx xxxx */
2633		{GTI,"PF,%b" }, /* 2d: 0110 0100 0010 1101 xxxx xxxx */
2634		{GTI,"MKH,%b" }, /* 2e: 0110 0100 0010 1110 xxxx xxxx */
2635		{GTI,"MKL,%b" }, /* 2f: 0110 0100 0010 1111 xxxx xxxx */
2636
2637		{SUINB,"PA,%b" }, /* 30: 0110 0100 0011 0000 xxxx xxxx */
2638		{SUINB,"PB,%b" }, /* 31: 0110 0100 0011 0001 xxxx xxxx */
2639		{SUINB,"PC,%b" }, /* 32: 0110 0100 0011 0010 xxxx xxxx */
2640		{SUINB,"PD,%b" }, /* 33: 0110 0100 0011 0011 xxxx xxxx */
2641		{illegal,0 }, /* 34: 0110 0100 0011 0100 xxxx xxxx */
2642		{SUINB,"PF,%b" }, /* 35: 0110 0100 0011 0101 xxxx xxxx */
2643		{SUINB,"MKH,%b" }, /* 36: 0110 0100 0011 0110 xxxx xxxx */
2644		{SUINB,"MKL,%b" }, /* 37: 0110 0100 0011 0111 xxxx xxxx */
2645		{LTI,"PA,%b" }, /* 38: 0110 0100 0011 1000 xxxx xxxx */
2646		{LTI,"PB,%b" }, /* 39: 0110 0100 0011 1001 xxxx xxxx */
2647		{LTI,"PC,%b" }, /* 3a: 0110 0100 0011 1010 xxxx xxxx */
2648		{LTI,"PD,%b" }, /* 3b: 0110 0100 0011 1011 xxxx xxxx */
2649		{illegal,0 }, /* 3c: 0110 0100 0011 1100 xxxx xxxx */
2650		{LTI,"PF,%b" }, /* 3d: 0110 0100 0011 1101 xxxx xxxx */
2651		{LTI,"MKH,%b" }, /* 3e: 0110 0100 0011 1110 xxxx xxxx */
2652		{LTI,"MKL,%b" }, /* 3f: 0110 0100 0011 1111 xxxx xxxx */
2653
2654		{ADI,"PA,%b" }, /* 40: 0110 0100 0100 0000 xxxx xxxx */
2655		{ADI,"PB,%b" }, /* 41: 0110 0100 0100 0001 xxxx xxxx */
2656		{ADI,"PC,%b" }, /* 42: 0110 0100 0100 0010 xxxx xxxx */
2657		{ADI,"PD,%b" }, /* 43: 0110 0100 0100 0011 xxxx xxxx */
2658		{illegal,0 }, /* 44: 0110 0100 0100 0100 xxxx xxxx */
2659		{ADI,"PF,%b" }, /* 45: 0110 0100 0100 0101 xxxx xxxx */
2660		{ADI,"MKH,%b" }, /* 46: 0110 0100 0100 0110 xxxx xxxx */
2661		{ADI,"MKL,%b" }, /* 47: 0110 0100 0100 0111 xxxx xxxx */
2662		{ONI,"PA,%b" }, /* 48: 0110 0100 0100 1000 xxxx xxxx */
2663		{ONI,"PB,%b" }, /* 49: 0110 0100 0100 1001 xxxx xxxx */
2664		{ONI,"PC,%b" }, /* 4a: 0110 0100 0100 1010 xxxx xxxx */
2665		{ONI,"PD,%b" }, /* 4b: 0110 0100 0100 1011 xxxx xxxx */
2666		{illegal,0 }, /* 4c: 0110 0100 0100 1100 xxxx xxxx */
2667		{ONI,"PF,%b" }, /* 4d: 0110 0100 0100 1101 xxxx xxxx */
2668		{ONI,"MKH,%b" }, /* 4e: 0110 0100 0100 1110 xxxx xxxx */
2669		{ONI,"MKL,%b" }, /* 4f: 0110 0100 0100 1111 xxxx xxxx */
2670
2671		{ACI,"PA,%b" }, /* 50: 0110 0100 0101 0000 xxxx xxxx */
2672		{ACI,"PB,%b" }, /* 51: 0110 0100 0101 0001 xxxx xxxx */
2673		{ACI,"PC,%b" }, /* 52: 0110 0100 0101 0010 xxxx xxxx */
2674		{ACI,"PD,%b" }, /* 53: 0110 0100 0101 0011 xxxx xxxx */
2675		{illegal,0 }, /* 54: 0110 0100 0101 0100 xxxx xxxx */
2676		{ACI,"PF,%b" }, /* 55: 0110 0100 0101 0101 xxxx xxxx */
2677		{ACI,"MKH,%b" }, /* 56: 0110 0100 0101 0110 xxxx xxxx */
2678		{ACI,"MKL,%b" }, /* 57: 0110 0100 0101 0111 xxxx xxxx */
2679		{OFFI,"PA,%b" }, /* 58: 0110 0100 0101 1000 xxxx xxxx */
2680		{OFFI,"PB,%b" }, /* 59: 0110 0100 0101 1001 xxxx xxxx */
2681		{OFFI,"PC,%b" }, /* 5a: 0110 0100 0101 1010 xxxx xxxx */
2682		{OFFI,"PD,%b" }, /* 5b: 0110 0100 0101 1011 xxxx xxxx */
2683		{illegal,0 }, /* 5c: 0110 0100 0101 1100 xxxx xxxx */
2684		{OFFI,"PF,%b" }, /* 5d: 0110 0100 0101 1101 xxxx xxxx */
2685		{OFFI,"MKH,%b" }, /* 5e: 0110 0100 0101 1110 xxxx xxxx */
2686		{OFFI,"MKL,%b" }, /* 5f: 0110 0100 0101 1111 xxxx xxxx */
2687
2688		{SUI,"PA,%b" }, /* 60: 0110 0100 0110 0000 xxxx xxxx */
2689		{SUI,"PB,%b" }, /* 61: 0110 0100 0110 0001 xxxx xxxx */
2690		{SUI,"PC,%b" }, /* 62: 0110 0100 0110 0010 xxxx xxxx */
2691		{SUI,"PD,%b" }, /* 63: 0110 0100 0110 0011 xxxx xxxx */
2692		{illegal,0 }, /* 64: 0110 0100 0110 0100 xxxx xxxx */
2693		{SUI,"PF,%b" }, /* 65: 0110 0100 0110 0101 xxxx xxxx */
2694		{SUI,"MKH,%b" }, /* 66: 0110 0100 0110 0110 xxxx xxxx */
2695		{SUI,"MKL,%b" }, /* 67: 0110 0100 0110 0111 xxxx xxxx */
2696		{NEI,"PA,%b" }, /* 68: 0110 0100 0110 1000 xxxx xxxx */
2697		{NEI,"PB,%b" }, /* 69: 0110 0100 0110 1001 xxxx xxxx */
2698		{NEI,"PC,%b" }, /* 6a: 0110 0100 0110 1010 xxxx xxxx */
2699		{NEI,"PD,%b" }, /* 6b: 0110 0100 0110 1011 xxxx xxxx */
2700		{illegal,0 }, /* 6c: 0110 0100 0110 1100 xxxx xxxx */
2701		{NEI,"PF,%b" }, /* 6d: 0110 0100 0110 1101 xxxx xxxx */
2702		{NEI,"MKH,%b" }, /* 6e: 0110 0100 0110 1110 xxxx xxxx */
2703		{NEI,"MKL,%b" }, /* 6f: 0110 0100 0110 1111 xxxx xxxx */
2704
2705		{SBI,"PA,%b" }, /* 70: 0110 0100 0111 0000 xxxx xxxx */
2706		{SBI,"PB,%b" }, /* 71: 0110 0100 0111 0001 xxxx xxxx */
2707		{SBI,"PC,%b" }, /* 72: 0110 0100 0111 0010 xxxx xxxx */
2708		{SBI,"PD,%b" }, /* 73: 0110 0100 0111 0011 xxxx xxxx */
2709		{illegal,0 }, /* 74: 0110 0100 0111 0100 xxxx xxxx */
2710		{SBI,"PF,%b" }, /* 75: 0110 0100 0111 0101 xxxx xxxx */
2711		{SBI,"MKH,%b" }, /* 76: 0110 0100 0111 0110 xxxx xxxx */
2712		{SBI,"MKL,%b" }, /* 77: 0110 0100 0111 0111 xxxx xxxx */
2713		{EQI,"PA,%b" }, /* 78: 0110 0100 0111 1000 xxxx xxxx */
2714		{EQI,"PB,%b" }, /* 79: 0110 0100 0111 1001 xxxx xxxx */
2715		{EQI,"PC,%b" }, /* 7a: 0110 0100 0111 1010 xxxx xxxx */
2716		{EQI,"PD,%b" }, /* 7b: 0110 0100 0111 1011 xxxx xxxx */
2717		{illegal,0 }, /* 7c: 0110 0100 0111 1100 xxxx xxxx */
2718		{EQI,"PF,%b" }, /* 7d: 0110 0100 0111 1101 xxxx xxxx */
2719		{EQI,"MKH,%b" }, /* 7e: 0110 0100 0111 1110 xxxx xxxx */
2720		{EQI,"MKL,%b" }, /* 7f: 0110 0100 0111 1111 xxxx xxxx */
2721
2722		{illegal,0 }, /* 80: 0110 0100 1000 0000 xxxx xxxx */
2723		{MVI,"SMH,%b" }, /* 81: 0110 0100 1000 0001 xxxx xxxx */
2724		{illegal,0 }, /* 82: 0110 0100 1000 0010 xxxx xxxx */
2725		{MVI,"EOM,%b" }, /* 83: 0110 0100 1000 0011 xxxx xxxx */
2726		{illegal,0 }, /* 84: 0110 0100 1000 0100 xxxx xxxx */
2727		{MVI,"TMM,%b" }, /* 85: 0110 0100 1000 0101 xxxx xxxx */
2728		{illegal,0 }, /* 86: 0110 0100 1000 0110 xxxx xxxx */
2729		{illegal,0 }, /* 87: 0110 0100 1000 0111 xxxx xxxx */
2730		{illegal,0 }, /* 88: 0110 0100 1000 1000 xxxx xxxx */
2731		{ANI,"SMH,%b" }, /* 89: 0110 0100 1000 1001 xxxx xxxx */
2732		{illegal,0 }, /* 8a: 0110 0100 1000 1010 xxxx xxxx */
2733		{ANI,"EOM,%b" }, /* 8b: 0110 0100 1000 1011 xxxx xxxx */
2734		{illegal,0 }, /* 8c: 0110 0100 1000 1100 xxxx xxxx */
2735		{ANI,"TMM,%b" }, /* 8d: 0110 0100 1000 1101 xxxx xxxx */
2736		{illegal,0 }, /* 8e: 0110 0100 1000 1110 xxxx xxxx */
2737		{illegal,0 }, /* 8f: 0110 0100 1000 1111 xxxx xxxx */
2738
2739		{illegal,0 }, /* 90: 0110 0100 1001 0000 xxxx xxxx */
2740		{XRI,"SMH,%b" }, /* 91: 0110 0100 1001 0001 xxxx xxxx */
2741		{illegal,0 }, /* 92: 0110 0100 1001 0010 xxxx xxxx */
2742		{XRI,"EOM,%b" }, /* 93: 0110 0100 1001 0011 xxxx xxxx */
2743		{illegal,0 }, /* 94: 0110 0100 1001 0100 xxxx xxxx */
2744		{XRI,"TMM,%b" }, /* 95: 0110 0100 1001 0101 xxxx xxxx */
2745		{illegal,0 }, /* 96: 0110 0100 1001 0110 xxxx xxxx */
2746		{illegal,0 }, /* 97: 0110 0100 1001 0111 xxxx xxxx */
2747		{illegal,0 }, /* 98: 0110 0100 1001 1000 xxxx xxxx */
2748		{ORI,"SMH,%b" }, /* 99: 0110 0100 1001 1001 xxxx xxxx */
2749		{illegal,0 }, /* 9a: 0110 0100 1001 1010 xxxx xxxx */
2750		{ORI,"EOM,%b" }, /* 9b: 0110 0100 1001 1011 xxxx xxxx */
2751		{illegal,0 }, /* 9c: 0110 0100 1001 1100 xxxx xxxx */
2752		{ORI,"TMM,%b" }, /* 9d: 0110 0100 1001 1101 xxxx xxxx */
2753		{illegal,0 }, /* 9e: 0110 0100 1001 1110 xxxx xxxx */
2754		{illegal,0 }, /* 9f: 0110 0100 1001 1111 xxxx xxxx */
2755
2756		{illegal,0 }, /* a0: 0110 0100 1010 0000 xxxx xxxx */
2757		{ADINC,"SMH,%b" }, /* a1: 0110 0100 1010 0001 xxxx xxxx */
2758		{illegal,0 }, /* a2: 0110 0100 1010 0010 xxxx xxxx */
2759		{ADINC,"EOM,%b" }, /* a3: 0110 0100 1010 0011 xxxx xxxx */
2760		{illegal,0 }, /* a4: 0110 0100 1010 0100 xxxx xxxx */
2761		{ADINC,"TMM,%b" }, /* a5: 0110 0100 1010 0101 xxxx xxxx */
2762		{illegal,0 }, /* a6: 0110 0100 1010 0110 xxxx xxxx */
2763		{illegal,0 }, /* a7: 0110 0100 1010 0111 xxxx xxxx */
2764		{illegal,0 }, /* a8: 0110 0100 1010 1000 xxxx xxxx */
2765		{GTI,"SMH,%b" }, /* a9: 0110 0100 1010 1001 xxxx xxxx */
2766		{illegal,0 }, /* aa: 0110 0100 1010 1010 xxxx xxxx */
2767		{GTI,"EOM,%b" }, /* ab: 0110 0100 1010 1011 xxxx xxxx */
2768		{illegal,0 }, /* ac: 0110 0100 1010 1100 xxxx xxxx */
2769		{GTI,"TMM,%b" }, /* ad: 0110 0100 1010 1101 xxxx xxxx */
2770		{GTI,"PT,%b" }, /* ae: 0110 0100 1010 1110 xxxx xxxx */
2771		{illegal,0 }, /* af: 0110 0100 1010 1111 xxxx xxxx */
2772
2773		{illegal,0 }, /* b0: 0110 0100 1011 0000 xxxx xxxx */
2774		{SUINB,"SMH,%b" }, /* b1: 0110 0100 1011 0001 xxxx xxxx */
2775		{illegal,0 }, /* b2: 0110 0100 1011 0010 xxxx xxxx */
2776		{SUINB,"EOM,%b" }, /* b3: 0110 0100 1011 0011 xxxx xxxx */
2777		{illegal,0 }, /* b4: 0110 0100 1011 0100 xxxx xxxx */
2778		{SUINB,"TMM,%b" }, /* b5: 0110 0100 1011 0101 xxxx xxxx */
2779		{illegal,0 }, /* b6: 0110 0100 1011 0110 xxxx xxxx */
2780		{illegal,0 }, /* b7: 0110 0100 1011 0111 xxxx xxxx */
2781		{illegal,0 }, /* b8: 0110 0100 1011 1000 xxxx xxxx */
2782		{LTI,"SMH,%b" }, /* b9: 0110 0100 1011 1001 xxxx xxxx */
2783		{illegal,0 }, /* ba: 0110 0100 1011 1010 xxxx xxxx */
2784		{LTI,"EOM,%b" }, /* bb: 0110 0100 1011 1011 xxxx xxxx */
2785		{illegal,0 }, /* bc: 0110 0100 1011 1100 xxxx xxxx */
2786		{LTI,"TMM,%b" }, /* bd: 0110 0100 1011 1101 xxxx xxxx */
2787		{LTI,"PT,%b" }, /* be: 0110 0100 1011 1110 xxxx xxxx */
2788		{illegal,0 }, /* bf: 0110 0100 1011 1111 xxxx xxxx */
2789
2790		{illegal,0 }, /* c0: 0110 0100 1100 0000 xxxx xxxx */
2791		{ADI,"SMH,%b" }, /* c1: 0110 0100 1100 0001 xxxx xxxx */
2792		{illegal,0 }, /* c2: 0110 0100 1100 0010 xxxx xxxx */
2793		{ADI,"EOM,%b" }, /* c3: 0110 0100 1100 0011 xxxx xxxx */
2794		{illegal,0 }, /* c4: 0110 0100 1100 0100 xxxx xxxx */
2795		{ADI,"TMM,%b" }, /* c5: 0110 0100 1100 0101 xxxx xxxx */
2796		{illegal,0 }, /* c6: 0110 0100 1100 0110 xxxx xxxx */
2797		{illegal,0 }, /* c7: 0110 0100 1100 0111 xxxx xxxx */
2798		{illegal,0 }, /* c8: 0110 0100 1100 1000 xxxx xxxx */
2799		{ONI,"SMH,%b" }, /* c9: 0110 0100 1100 1001 xxxx xxxx */
2800		{illegal,0 }, /* ca: 0110 0100 1100 1010 xxxx xxxx */
2801		{ONI,"EOM,%b" }, /* cb: 0110 0100 1100 1011 xxxx xxxx */
2802		{illegal,0 }, /* cc: 0110 0100 1100 1100 xxxx xxxx */
2803		{ONI,"TMM,%b" }, /* cd: 0110 0100 1100 1101 xxxx xxxx */
2804		{ONI,"PT,%b" }, /* ce: 0110 0100 1100 1110 xxxx xxxx */
2805		{illegal,0 }, /* cf: 0110 0100 1100 1111 xxxx xxxx */
2806
2807		{illegal,0 }, /* d0: 0110 0100 1101 0000 xxxx xxxx */
2808		{ACI,"SMH,%b" }, /* d1: 0110 0100 1101 0001 xxxx xxxx */
2809		{illegal,0 }, /* d2: 0110 0100 1101 0010 xxxx xxxx */
2810		{ACI,"EOM,%b" }, /* d3: 0110 0100 1101 0011 xxxx xxxx */
2811		{illegal,0 }, /* d4: 0110 0100 1101 0100 xxxx xxxx */
2812		{ACI,"TMM,%b" }, /* d5: 0110 0100 1101 0101 xxxx xxxx */
2813		{illegal,0 }, /* d6: 0110 0100 1101 0110 xxxx xxxx */
2814		{illegal,0 }, /* d7: 0110 0100 1101 0111 xxxx xxxx */
2815		{illegal,0 }, /* d8: 0110 0100 1101 1000 xxxx xxxx */
2816		{OFFI,"SMH,%b" }, /* d9: 0110 0100 1101 1001 xxxx xxxx */
2817		{illegal,0 }, /* da: 0110 0100 1101 1010 xxxx xxxx */
2818		{OFFI,"EOM,%b" }, /* db: 0110 0100 1101 1011 xxxx xxxx */
2819		{illegal,0 }, /* dc: 0110 0100 1101 1100 xxxx xxxx */
2820		{OFFI,"TMM,%b" }, /* dd: 0110 0100 1101 1101 xxxx xxxx */
2821		{OFFI,"PT,%b" }, /* de: 0110 0100 1101 1110 xxxx xxxx */
2822		{illegal,0 }, /* df: 0110 0100 1101 1111 xxxx xxxx */
2823
2824		{illegal,0 }, /* e0: 0110 0100 1110 0000 xxxx xxxx */
2825		{SUI,"SMH,%b" }, /* e1: 0110 0100 1110 0001 xxxx xxxx */
2826		{illegal,0 }, /* e2: 0110 0100 1110 0010 xxxx xxxx */
2827		{SUI,"EOM,%b" }, /* e3: 0110 0100 1110 0011 xxxx xxxx */
2828		{illegal,0 }, /* e4: 0110 0100 1110 0100 xxxx xxxx */
2829		{SUI,"TMM,%b" }, /* e5: 0110 0100 1110 0101 xxxx xxxx */
2830		{illegal,0 }, /* e6: 0110 0100 1110 0110 xxxx xxxx */
2831		{illegal,0 }, /* e7: 0110 0100 1110 0111 xxxx xxxx */
2832		{illegal,0 }, /* e8: 0110 0100 1110 1000 xxxx xxxx */
2833		{NEI,"SMH,%b" }, /* e9: 0110 0100 1110 1001 xxxx xxxx */
2834		{illegal,0 }, /* ea: 0110 0100 1110 1010 xxxx xxxx */
2835		{NEI,"EOM,%b" }, /* eb: 0110 0100 1110 1011 xxxx xxxx */
2836		{illegal,0 }, /* ec: 0110 0100 1110 1100 xxxx xxxx */
2837		{NEI,"TMM,%b" }, /* ed: 0110 0100 1110 1101 xxxx xxxx */
2838		{NEI,"PT,%b" }, /* ee: 0110 0100 1110 1110 xxxx xxxx */
2839		{illegal,0 }, /* ef: 0110 0100 1110 1111 xxxx xxxx */
2840
2841		{illegal,0 }, /* f0: 0110 0100 1111 0000 xxxx xxxx */
2842		{SBI,"SMH,%b" }, /* f1: 0110 0100 1111 0001 xxxx xxxx */
2843		{illegal,0 }, /* f2: 0110 0100 1111 0010 xxxx xxxx */
2844		{SBI,"EOM,%b" }, /* f3: 0110 0100 1111 0011 xxxx xxxx */
2845		{illegal,0 }, /* f4: 0110 0100 1111 0100 xxxx xxxx */
2846		{SBI,"TMM,%b" }, /* f5: 0110 0100 1111 0101 xxxx xxxx */
2847		{illegal,0 }, /* f6: 0110 0100 1111 0110 xxxx xxxx */
2848		{illegal,0 }, /* f7: 0110 0100 1111 0111 xxxx xxxx */
2849		{illegal,0 }, /* f8: 0110 0100 1111 1000 xxxx xxxx */
2850		{EQI,"SMH,%b" }, /* f9: 0110 0100 1111 1001 xxxx xxxx */
2851		{illegal,0 }, /* fa: 0110 0100 1111 1010 xxxx xxxx */
2852		{EQI,"EOM,%b" }, /* fb: 0110 0100 1111 1011 xxxx xxxx */
2853		{illegal,0 }, /* fc: 0110 0100 1111 1100 xxxx xxxx */
2854		{EQI,"TMM,%b" }, /* fd: 0110 0100 1111 1101 xxxx xxxx */
2855		{EQI,"PT,%b" }, /* fe: 0110 0100 1111 1110 xxxx xxxx */
2856		{illegal,0 } /* ff: 0110 0100 1111 1111 xxxx xxxx */
2857		};
2858
2859		/* prefix 70 */
2860		static const struct dasm_s dasm70[256] =
2861		{
2862		{illegal,0 }, /* 00: 0111 0000 0000 0000 */
2863		{illegal,0 }, /* 01: 0111 0000 0000 0001 */
2864		{illegal,0 }, /* 02: 0111 0000 0000 0010 */
2865		{illegal,0 }, /* 03: 0111 0000 0000 0011 */
2866		{illegal,0 }, /* 04: 0111 0000 0000 0100 */
2867		{illegal,0 }, /* 05: 0111 0000 0000 0101 */
2868		{illegal,0 }, /* 06: 0111 0000 0000 0110 */
2869		{illegal,0 }, /* 07: 0111 0000 0000 0111 */
2870		{illegal,0 }, /* 08: 0111 0000 0000 1000 */
2871		{illegal,0 }, /* 09: 0111 0000 0000 1001 */
2872		{illegal,0 }, /* 0a: 0111 0000 0000 1010 */
2873		{illegal,0 }, /* 0b: 0111 0000 0000 1011 */
2874		{illegal,0 }, /* 0c: 0111 0000 0000 1100 */
2875		{illegal,0 }, /* 0d: 0111 0000 0000 1101 */
2876		{SSPD,"%w" }, /* 0e: 0111 0000 0000 1110 llll llll hhhh hhhh */
2877		{LSPD,"%w" }, /* 0f: 0111 0000 0000 1111 llll llll hhhh hhhh */
2878
2879		{illegal,0 }, /* 10: 0111 0000 0001 0000 */
2880		{illegal,0 }, /* 11: 0111 0000 0001 0001 */
2881		{illegal,0 }, /* 12: 0111 0000 0001 0010 */
2882		{illegal,0 }, /* 13: 0111 0000 0001 0011 */
2883		{illegal,0 }, /* 14: 0111 0000 0001 0100 */
2884		{illegal,0 }, /* 15: 0111 0000 0001 0101 */
2885		{illegal,0 }, /* 16: 0111 0000 0001 0110 */
2886		{illegal,0 }, /* 17: 0111 0000 0001 0111 */
2887		{illegal,0 }, /* 18: 0111 0000 0001 1000 */
2888		{illegal,0 }, /* 19: 0111 0000 0001 1001 */
2889		{illegal,0 }, /* 1a: 0111 0000 0001 1010 */
2890		{illegal,0 }, /* 1b: 0111 0000 0001 1011 */
2891		{illegal,0 }, /* 1c: 0111 0000 0001 1100 */
2892		{illegal,0 }, /* 1d: 0111 0000 0001 1101 */
2893		{SBCD,"%w" }, /* 1e: 0111 0000 0001 1110 llll llll hhhh hhhh */
2894		{LBCD,"%w" }, /* 1f: 0111 0000 0001 1111 llll llll hhhh hhhh */
2895
2896		{illegal,0 }, /* 20: 0111 0000 0010 0000 */
2897		{illegal,0 }, /* 21: 0111 0000 0010 0001 */
2898		{illegal,0 }, /* 22: 0111 0000 0010 0010 */
2899		{illegal,0 }, /* 23: 0111 0000 0010 0011 */
2900		{illegal,0 }, /* 24: 0111 0000 0010 0100 */
2901		{illegal,0 }, /* 25: 0111 0000 0010 0101 */
2902		{illegal,0 }, /* 26: 0111 0000 0010 0110 */
2903		{illegal,0 }, /* 27: 0111 0000 0010 0111 */
2904		{illegal,0 }, /* 28: 0111 0000 0010 1000 */
2905		{illegal,0 }, /* 29: 0111 0000 0010 1001 */
2906		{illegal,0 }, /* 2a: 0111 0000 0010 1010 */
2907		{illegal,0 }, /* 2b: 0111 0000 0010 1011 */
2908		{illegal,0 }, /* 2c: 0111 0000 0010 1100 */
2909		{illegal,0 }, /* 2d: 0111 0000 0010 1101 */
2910		{SDED,"%w" }, /* 2e: 0111 0000 0010 1110 llll llll hhhh hhhh */
2911		{LDED,"%w" }, /* 2f: 0111 0000 0010 1111 llll llll hhhh hhhh */
2912
2913		{illegal,0 }, /* 30: 0111 0000 0011 0000 */
2914		{illegal,0 }, /* 31: 0111 0000 0011 0001 */
2915		{illegal,0 }, /* 32: 0111 0000 0011 0010 */
2916		{illegal,0 }, /* 33: 0111 0000 0011 0011 */
2917		{illegal,0 }, /* 34: 0111 0000 0011 0100 */
2918		{illegal,0 }, /* 35: 0111 0000 0011 0101 */
2919		{illegal,0 }, /* 36: 0111 0000 0011 0110 */
2920		{illegal,0 }, /* 37: 0111 0000 0011 0111 */
2921		{illegal,0 }, /* 38: 0111 0000 0011 1000 */
2922		{illegal,0 }, /* 39: 0111 0000 0011 1001 */
2923		{illegal,0 }, /* 3a: 0111 0000 0011 1010 */
2924		{illegal,0 }, /* 3b: 0111 0000 0011 1011 */
2925		{illegal,0 }, /* 3c: 0111 0000 0011 1100 */
2926		{illegal,0 }, /* 3d: 0111 0000 0011 1101 */
2927		{SHLD,"%w" }, /* 3e: 0111 0000 0011 1110 llll llll hhhh hhhh */
2928		{LHLD,"%w" }, /* 3f: 0111 0000 0011 1111 llll llll hhhh hhhh */
2929
2930		{EADD,"EA,V" }, /* 40: 0111 0000 0100 0000 */
2931		{EADD,"EA,A" }, /* 41: 0111 0000 0100 0001 */
2932		{EADD,"EA,B" }, /* 42: 0111 0000 0100 0010 */
2933		{EADD,"EA,C" }, /* 43: 0111 0000 0100 0011 */
2934		{illegal,0 }, /* 44: 0111 0000 0100 0100 */
2935		{illegal,0 }, /* 45: 0111 0000 0100 0101 */
2936		{illegal,0 }, /* 46: 0111 0000 0100 0110 */
2937		{illegal,0 }, /* 47: 0111 0000 0100 0111 */
2938		{illegal,0 }, /* 48: 0111 0000 0100 1000 */
2939		{illegal,0 }, /* 49: 0111 0000 0100 1001 */
2940		{illegal,0 }, /* 4a: 0111 0000 0100 1010 */
2941		{illegal,0 }, /* 4b: 0111 0000 0100 1011 */
2942		{illegal,0 }, /* 4c: 0111 0000 0100 1100 */
2943		{illegal,0 }, /* 4d: 0111 0000 0100 1101 */
2944		{illegal,0 }, /* 4e: 0111 0000 0100 1110 */
2945		{illegal,0 }, /* 4f: 0111 0000 0100 1111 */
2946
2947		{illegal,0 }, /* 50: 0111 0000 0101 0000 */
2948		{illegal,0 }, /* 51: 0111 0000 0101 0001 */
2949		{illegal,0 }, /* 52: 0111 0000 0101 0010 */
2950		{illegal,0 }, /* 53: 0111 0000 0101 0011 */
2951		{illegal,0 }, /* 54: 0111 0000 0101 0100 */
2952		{illegal,0 }, /* 55: 0111 0000 0101 0101 */
2953		{illegal,0 }, /* 56: 0111 0000 0101 0110 */
2954		{illegal,0 }, /* 57: 0111 0000 0101 0111 */
2955		{illegal,0 }, /* 58: 0111 0000 0101 1000 */
2956		{illegal,0 }, /* 59: 0111 0000 0101 1001 */
2957		{illegal,0 }, /* 5a: 0111 0000 0101 1010 */
2958		{illegal,0 }, /* 5b: 0111 0000 0101 1011 */
2959		{illegal,0 }, /* 5c: 0111 0000 0101 1100 */
2960		{illegal,0 }, /* 5d: 0111 0000 0101 1101 */
2961		{illegal,0 }, /* 5e: 0111 0000 0101 1110 */
2962		{illegal,0 }, /* 5f: 0111 0000 0101 1111 */
2963
2964		{ESUB,"EA,V" }, /* 60: 0111 0000 0110 0000 */
2965		{ESUB,"EA,A" }, /* 61: 0111 0000 0110 0001 */
2966		{ESUB,"EA,B" }, /* 62: 0111 0000 0110 0010 */
2967		{ESUB,"EA,C" }, /* 63: 0111 0000 0110 0011 */
2968		{illegal,0 }, /* 64: 0111 0000 0110 0100 */
2969		{illegal,0 }, /* 65: 0111 0000 0110 0101 */
2970		{illegal,0 }, /* 66: 0111 0000 0110 0110 */
2971		{illegal,0 }, /* 67: 0111 0000 0110 0111 */
2972		{MOV,"V,(%w)" }, /* 68: 0111 0000 0110 1000 llll llll hhhh hhhh */
2973		{MOV,"A,(%w)" }, /* 69: 0111 0000 0110 1001 llll llll hhhh hhhh */
2974		{MOV,"B,(%w)" }, /* 6a: 0111 0000 0110 1010 llll llll hhhh hhhh */
2975		{MOV,"C,(%w)" }, /* 6b: 0111 0000 0110 1011 llll llll hhhh hhhh */
2976		{MOV,"D,(%w)" }, /* 6c: 0111 0000 0110 1100 llll llll hhhh hhhh */
2977		{MOV,"E,(%w)" }, /* 6d: 0111 0000 0110 1101 llll llll hhhh hhhh */
2978		{MOV,"H,(%w)" }, /* 6e: 0111 0000 0110 1110 llll llll hhhh hhhh */
2979		{MOV,"L,(%w)" }, /* 6f: 0111 0000 0110 1111 llll llll hhhh hhhh */
2980
2981		{illegal,0 }, /* 70: 0111 0000 0111 0000 */
2982		{illegal,0 }, /* 71: 0111 0000 0111 0001 */
2983		{illegal,0 }, /* 72: 0111 0000 0111 0010 */
2984		{illegal,0 }, /* 73: 0111 0000 0111 0011 */
2985		{illegal,0 }, /* 74: 0111 0000 0111 0100 */
2986		{illegal,0 }, /* 75: 0111 0000 0111 0101 */
2987		{illegal,0 }, /* 76: 0111 0000 0111 0110 */
2988		{illegal,0 }, /* 77: 0111 0000 0111 0111 */
2989		{MOV,"(%w),V" }, /* 78: 0111 0000 0111 1000 llll llll hhhh hhhh */
2990		{MOV,"(%w),A" }, /* 79: 0111 0000 0111 1001 llll llll hhhh hhhh */
2991		{MOV,"(%w),B" }, /* 7a: 0111 0000 0111 1010 llll llll hhhh hhhh */
2992		{MOV,"(%w),C" }, /* 7b: 0111 0000 0111 1011 llll llll hhhh hhhh */
2993		{MOV,"(%w),D" }, /* 7c: 0111 0000 0111 1100 llll llll hhhh hhhh */
2994		{MOV,"(%w),E" }, /* 7d: 0111 0000 0111 1101 llll llll hhhh hhhh */
2995		{MOV,"(%w),H" }, /* 7e: 0111 0000 0111 1110 llll llll hhhh hhhh */
2996		{MOV,"(%w),L" }, /* 7f: 0111 0000 0111 1111 llll llll hhhh hhhh */
2997
2998		{illegal,0 }, /* 80: 0111 0000 1000 0000 */
2999		{illegal,0 }, /* 81: 0111 0000 1000 0001 */
3000		{illegal,0 }, /* 82: 0111 0000 1000 0010 */
3001		{illegal,0 }, /* 83: 0111 0000 1000 0011 */
3002		{illegal,0 }, /* 84: 0111 0000 1000 0100 */
3003		{illegal,0 }, /* 85: 0111 0000 1000 0101 */
3004		{illegal,0 }, /* 86: 0111 0000 1000 0110 */
3005		{illegal,0 }, /* 87: 0111 0000 1000 0111 */
3006		{illegal,0 }, /* 88: 0111 0000 1000 1000 */
3007		{ANAX,"(BC)" }, /* 89: 0111 0000 1000 1001 */
3008		{ANAX,"(DE)" }, /* 8a: 0111 0000 1000 1010 */
3009		{ANAX,"(HL)" }, /* 8b: 0111 0000 1000 1011 */
3010		{ANAX,"(DE+)" }, /* 8c: 0111 0000 1000 1100 */
3011		{ANAX,"(HL+)" }, /* 8d: 0111 0000 1000 1101 */
3012		{ANAX,"(DE-)" }, /* 8e: 0111 0000 1000 1110 */
3013		{ANAX,"(HL-)" }, /* 8f: 0111 0000 1000 1111 */
3014
3015		{illegal,0 }, /* 90: 0111 0000 1001 0000 */
3016		{XRAX,"(BC)" }, /* 91: 0111 0000 1001 0001 */
3017		{XRAX,"(DE)" }, /* 92: 0111 0000 1001 0010 */
3018		{XRAX,"(HL)" }, /* 93: 0111 0000 1001 0011 */
3019		{XRAX,"(DE+)" }, /* 94: 0111 0000 1001 0100 */
3020		{XRAX,"(HL+)" }, /* 95: 0111 0000 1001 0101 */
3021		{XRAX,"(DE-)" }, /* 96: 0111 0000 1001 0110 */
3022		{XRAX,"(HL-)" }, /* 97: 0111 0000 1001 0111 */
3023		{illegal,0 }, /* 98: 0111 0000 1001 1000 */
3024		{ORAX,"(BC)" }, /* 99: 0111 0000 1001 1001 */
3025		{ORAX,"(DE)" }, /* 9a: 0111 0000 1001 1010 */
3026		{ORAX,"(HL)" }, /* 9b: 0111 0000 1001 1011 */
3027		{ORAX,"(DE+)" }, /* 9c: 0111 0000 1001 1100 */
3028		{ORAX,"(HL+)" }, /* 9d: 0111 0000 1001 1101 */
3029		{ORAX,"(DE-)" }, /* 9e: 0111 0000 1001 1110 */
3030		{ORAX,"(HL-)" }, /* 9f: 0111 0000 1001 1111 */
3031
3032		{illegal,0 }, /* a0: 0111 0000 1010 0000 */
3033		{ADDNCX,"(BC)" }, /* a1: 0111 0000 1010 0001 */
3034		{ADDNCX,"(DE)" }, /* a2: 0111 0000 1010 0010 */
3035		{ADDNCX,"(HL)" }, /* a3: 0111 0000 1010 0011 */
3036		{ADDNCX,"(DE+)" }, /* a4: 0111 0000 1010 0100 */
3037		{ADDNCX,"(HL+)" }, /* a5: 0111 0000 1010 0101 */
3038		{ADDNCX,"(DE-)" }, /* a6: 0111 0000 1010 0110 */
3039		{ADDNCX,"(HL-)" }, /* a7: 0111 0000 1010 0111 */
3040		{illegal,0 }, /* a8: 0111 0000 1010 1000 */
3041		{GTAX,"(BC)" }, /* a9: 0111 0000 1010 1001 */
3042		{GTAX,"(DE)" }, /* aa: 0111 0000 1010 1010 */
3043		{GTAX,"(HL)" }, /* ab: 0111 0000 1010 1011 */
3044		{GTAX,"(DE+)" }, /* ac: 0111 0000 1010 1100 */
3045		{GTAX,"(HL+)" }, /* ad: 0111 0000 1010 1101 */
3046		{GTAX,"(DE-)" }, /* ae: 0111 0000 1010 1110 */
3047		{GTAX,"(HL-)" }, /* af: 0111 0000 1010 1111 */
3048
3049		{illegal,0 }, /* b0: 0111 0000 1011 0000 */
3050		{SUBNBX,"(BC)" }, /* b1: 0111 0000 1011 0001 */
3051		{SUBNBX,"(DE)" }, /* b2: 0111 0000 1011 0010 */
3052		{SUBNBX,"(HL)" }, /* b3: 0111 0000 1011 0011 */
3053		{SUBNBX,"(DE+)" }, /* b4: 0111 0000 1011 0100 */
3054		{SUBNBX,"(HL+)" }, /* b5: 0111 0000 1011 0101 */
3055		{SUBNBX,"(DE-)" }, /* b6: 0111 0000 1011 0110 */
3056		{SUBNBX,"(HL-)" }, /* b7: 0111 0000 1011 0111 */
3057		{illegal,0 }, /* b8: 0111 0000 1011 1000 */
3058		{LTAX,"(BC)" }, /* b9: 0111 0000 1011 1001 */
3059		{LTAX,"(DE)" }, /* ba: 0111 0000 1011 1010 */
3060		{LTAX,"(HL)" }, /* bb: 0111 0000 1011 1011 */
3061		{LTAX,"(DE+)" }, /* bc: 0111 0000 1011 1100 */
3062		{LTAX,"(HL+)" }, /* bd: 0111 0000 1011 1101 */
3063		{LTAX,"(DE-)" }, /* be: 0111 0000 1011 1110 */
3064		{LTAX,"(HL-)" }, /* bf: 0111 0000 1011 1111 */
3065
3066		{illegal,0 }, /* c0: 0111 0000 1100 0000 */
3067		{ADDX,"(BC)" }, /* c1: 0111 0000 1100 0001 */
3068		{ADDX,"(DE)" }, /* c2: 0111 0000 1100 0010 */
3069		{ADDX,"(HL)" }, /* c3: 0111 0000 1100 0011 */
3070		{ADDX,"(DE+)" }, /* c4: 0111 0000 1100 0100 */
3071		{ADDX,"(HL+)" }, /* c5: 0111 0000 1100 0101 */
3072		{ADDX,"(DE-)" }, /* c6: 0111 0000 1100 0110 */
3073		{ADDX,"(HL-)" }, /* c7: 0111 0000 1100 0111 */
3074		{illegal,0 }, /* c8: 0111 0000 1100 1000 */
3075		{ONAX,"(BC)" }, /* c9: 0111 0000 1100 1001 */
3076		{ONAX,"(DE)" }, /* ca: 0111 0000 1100 1010 */
3077		{ONAX,"(HL)" }, /* cb: 0111 0000 1100 1011 */
3078		{ONAX,"(DE+)" }, /* cc: 0111 0000 1100 1100 */
3079		{ONAX,"(HL+)" }, /* cd: 0111 0000 1100 1101 */
3080		{ONAX,"(DE-)" }, /* ce: 0111 0000 1100 1110 */
3081		{ONAX,"(HL-)" }, /* cf: 0111 0000 1100 1111 */
3082
3083		{illegal,0 }, /* d0: 0111 0000 1101 0000 */
3084		{ADCX,"(BC)" }, /* d1: 0111 0000 1101 0001 */
3085		{ADCX,"(DE)" }, /* d2: 0111 0000 1101 0010 */
3086		{ADCX,"(HL)" }, /* d3: 0111 0000 1101 0011 */
3087		{ADCX,"(DE+)" }, /* d4: 0111 0000 1101 0100 */
3088		{ADCX,"(HL+)" }, /* d5: 0111 0000 1101 0101 */
3089		{ADCX,"(DE-)" }, /* d6: 0111 0000 1101 0110 */
3090		{ADCX,"(HL-)" }, /* d7: 0111 0000 1101 0111 */
3091		{illegal,0 }, /* d8: 0111 0000 1101 1000 */
3092		{OFFAX,"(BC)" }, /* d9: 0111 0000 1101 1001 */
3093		{OFFAX,"(DE)" }, /* da: 0111 0000 1101 1010 */
3094		{OFFAX,"(HL)" }, /* db: 0111 0000 1101 1011 */
3095		{OFFAX,"(DE+)" }, /* dc: 0111 0000 1101 1100 */
3096		{OFFAX,"(HL+)" }, /* dd: 0111 0000 1101 1101 */
3097		{OFFAX,"(DE-)" }, /* de: 0111 0000 1101 1110 */
3098		{OFFAX,"(HL-)" }, /* df: 0111 0000 1101 1111 */
3099
3100		{illegal,0 }, /* e0: 0111 0000 1110 0000 */
3101		{SUBX,"(BC)" }, /* e1: 0111 0000 1110 0001 */
3102		{SUBX,"(DE)" }, /* e2: 0111 0000 1110 0010 */
3103		{SUBX,"(HL)" }, /* e3: 0111 0000 1110 0011 */
3104		{SUBX,"(DE+)" }, /* e4: 0111 0000 1110 0100 */
3105		{SUBX,"(HL+)" }, /* e5: 0111 0000 1110 0101 */
3106		{SUBX,"(DE-)" }, /* e6: 0111 0000 1110 0110 */
3107		{SUBX,"(HL-)" }, /* e7: 0111 0000 1110 0111 */
3108		{illegal,0 }, /* e8: 0111 0000 1110 1000 */
3109		{NEAX,"(BC)" }, /* e9: 0111 0000 1110 1001 */
3110		{NEAX,"(DE)" }, /* ea: 0111 0000 1110 1010 */
3111		{NEAX,"(HL)" }, /* eb: 0111 0000 1110 1011 */
3112		{NEAX,"(DE+)" }, /* ec: 0111 0000 1110 1100 */
3113		{NEAX,"(HL+)" }, /* ed: 0111 0000 1110 1101 */
3114		{NEAX,"(DE-)" }, /* ee: 0111 0000 1110 1110 */
3115		{NEAX,"(HL-)" }, /* ef: 0111 0000 1110 1111 */
3116
3117		{illegal,0 }, /* f0: 0111 0000 1111 0000 */
3118		{SBBX,"(BC)" }, /* f1: 0111 0000 1111 0001 */
3119		{SBBX,"(DE)" }, /* f2: 0111 0000 1111 0010 */
3120		{SBBX,"(HL)" }, /* f3: 0111 0000 1111 0011 */
3121		{SBBX,"(DE+)" }, /* f4: 0111 0000 1111 0100 */
3122		{SBBX,"(HL+)" }, /* f5: 0111 0000 1111 0101 */
3123		{SBBX,"(DE-)" }, /* f6: 0111 0000 1111 0110 */
3124		{SBBX,"(HL-)" }, /* f7: 0111 0000 1111 0111 */
3125		{illegal,0 }, /* f8: 0111 0000 1111 1000 */
3126		{EQAX,"(BC)" }, /* f9: 0111 0000 1111 1001 */
3127		{EQAX,"(DE)" }, /* fa: 0111 0000 1111 1010 */
3128		{EQAX,"(HL)" }, /* fb: 0111 0000 1111 1011 */
3129		{EQAX,"(DE+)" }, /* fc: 0111 0000 1111 1100 */
3130		{EQAX,"(HL+)" }, /* fd: 0111 0000 1111 1101 */
3131		{EQAX,"(DE-)" }, /* fe: 0111 0000 1111 1110 */
3132		{EQAX,"(HL-)" } /* ff: 0111 0000 1111 1111 */
3133		};
3134
3135		/* prefix 74 */
3136		static const struct dasm_s dasm74[256] =
3137		{
3138		{illegal,0 }, /* 00: 0111 0100 0000 0000 */
3139		{illegal,0 }, /* 01: 0111 0100 0000 0001 */
3140		{illegal,0 }, /* 02: 0111 0100 0000 0010 */
3141		{illegal,0 }, /* 03: 0111 0100 0000 0011 */
3142		{illegal,0 }, /* 04: 0111 0100 0000 0100 */
3143		{illegal,0 }, /* 05: 0111 0100 0000 0101 */
3144		{illegal,0 }, /* 06: 0111 0100 0000 0110 */
3145		{illegal,0 }, /* 07: 0111 0100 0000 0111 */
3146		{ANI,"V,%b" }, /* 08: 0111 0100 0000 1000 xxxx xxxx */
3147		{ANI,"A,%b" }, /* 09: 0111 0100 0000 1001 xxxx xxxx */
3148		{ANI,"B,%b" }, /* 0a: 0111 0100 0000 1010 xxxx xxxx */
3149		{ANI,"C,%b" }, /* 0b: 0111 0100 0000 1011 xxxx xxxx */
3150		{ANI,"D,%b" }, /* 0c: 0111 0100 0000 1100 xxxx xxxx */
3151		{ANI,"E,%b" }, /* 0d: 0111 0100 0000 1101 xxxx xxxx */
3152		{ANI,"H,%b" }, /* 0e: 0111 0100 0000 1110 xxxx xxxx */
3153		{ANI,"L,%b" }, /* 0f: 0111 0100 0000 1111 xxxx xxxx */
3154
3155		{XRI,"V,%b" }, /* 10: 0111 0100 0001 0000 xxxx xxxx */
3156		{XRI,"A,%b" }, /* 11: 0111 0100 0001 0001 xxxx xxxx */
3157		{XRI,"B,%b" }, /* 12: 0111 0100 0001 0010 xxxx xxxx */
3158		{XRI,"C,%b" }, /* 13: 0111 0100 0001 0011 xxxx xxxx */
3159		{XRI,"D,%b" }, /* 14: 0111 0100 0001 0100 xxxx xxxx */
3160		{XRI,"E,%b" }, /* 15: 0111 0100 0001 0101 xxxx xxxx */
3161		{XRI,"H,%b" }, /* 16: 0111 0100 0001 0110 xxxx xxxx */
3162		{XRI,"L,%b" }, /* 17: 0111 0100 0001 0111 xxxx xxxx */
3163		{ORI,"V,%b" }, /* 18: 0111 0100 0001 1000 xxxx xxxx */
3164		{ORI,"A,%b" }, /* 19: 0111 0100 0001 1001 xxxx xxxx */
3165		{ORI,"B,%b" }, /* 1a: 0111 0100 0001 1010 xxxx xxxx */
3166		{ORI,"C,%b" }, /* 1b: 0111 0100 0001 1011 xxxx xxxx */
3167		{ORI,"D,%b" }, /* 1c: 0111 0100 0001 1100 xxxx xxxx */
3168		{ORI,"E,%b" }, /* 1d: 0111 0100 0001 1101 xxxx xxxx */
3169		{ORI,"H,%b" }, /* 1e: 0111 0100 0001 1110 xxxx xxxx */
3170		{ORI,"L,%b" }, /* 1f: 0111 0100 0001 1111 xxxx xxxx */
3171
3172		{ADINC,"V,%b" }, /* 20: 0111 0100 0010 0000 xxxx xxxx */
3173		{ADINC,"A,%b" }, /* 21: 0111 0100 0010 0001 xxxx xxxx */
3174		{ADINC,"B,%b" }, /* 22: 0111 0100 0010 0010 xxxx xxxx */
3175		{ADINC,"C,%b" }, /* 23: 0111 0100 0010 0011 xxxx xxxx */
3176		{ADINC,"D,%b" }, /* 24: 0111 0100 0010 0100 xxxx xxxx */
3177		{ADINC,"E,%b" }, /* 25: 0111 0100 0010 0101 xxxx xxxx */
3178		{ADINC,"H,%b" }, /* 26: 0111 0100 0010 0110 xxxx xxxx */
3179		{ADINC,"L,%b" }, /* 27: 0111 0100 0010 0111 xxxx xxxx */
3180		{GTI,"V,%b" }, /* 28: 0111 0100 0010 1000 xxxx xxxx */
3181		{GTI,"A,%b" }, /* 29: 0111 0100 0010 1001 xxxx xxxx */
3182		{GTI,"B,%b" }, /* 2a: 0111 0100 0010 1010 xxxx xxxx */
3183		{GTI,"C,%b" }, /* 2b: 0111 0100 0010 1011 xxxx xxxx */
3184		{GTI,"D,%b" }, /* 2c: 0111 0100 0010 1100 xxxx xxxx */
3185		{GTI,"E,%b" }, /* 2d: 0111 0100 0010 1101 xxxx xxxx */
3186		{GTI,"H,%b" }, /* 2e: 0111 0100 0010 1110 xxxx xxxx */
3187		{GTI,"L,%b" }, /* 2f: 0111 0100 0010 1111 xxxx xxxx */
3188
3189		{SUINB,"V,%b" }, /* 30: 0111 0100 0011 0000 xxxx xxxx */
3190		{SUINB,"A,%b" }, /* 31: 0111 0100 0011 0001 xxxx xxxx */
3191		{SUINB,"B,%b" }, /* 32: 0111 0100 0011 0010 xxxx xxxx */
3192		{SUINB,"C,%b" }, /* 33: 0111 0100 0011 0011 xxxx xxxx */
3193		{SUINB,"D,%b" }, /* 34: 0111 0100 0011 0100 xxxx xxxx */
3194		{SUINB,"E,%b" }, /* 35: 0111 0100 0011 0101 xxxx xxxx */
3195		{SUINB,"H,%b" }, /* 36: 0111 0100 0011 0110 xxxx xxxx */
3196		{SUINB,"L,%b" }, /* 37: 0111 0100 0011 0111 xxxx xxxx */
3197		{LTI,"V,%b" }, /* 38: 0111 0100 0011 1000 xxxx xxxx */
3198		{LTI,"A,%b" }, /* 39: 0111 0100 0011 1001 xxxx xxxx */
3199		{LTI,"B,%b" }, /* 3a: 0111 0100 0011 1010 xxxx xxxx */
3200		{LTI,"C,%b" }, /* 3b: 0111 0100 0011 1011 xxxx xxxx */
3201		{LTI,"D,%b" }, /* 3c: 0111 0100 0011 1100 xxxx xxxx */
3202		{LTI,"E,%b" }, /* 3d: 0111 0100 0011 1101 xxxx xxxx */
3203		{LTI,"H,%b" }, /* 3e: 0111 0100 0011 1110 xxxx xxxx */
3204		{LTI,"L,%b" }, /* 3f: 0111 0100 0011 1111 xxxx xxxx */
3205
3206		{ADI,"V,%b" }, /* 40: 0111 0100 0100 0000 xxxx xxxx */
3207		{ADI,"A,%b" }, /* 41: 0111 0100 0100 0001 xxxx xxxx */
3208		{ADI,"B,%b" }, /* 42: 0111 0100 0100 0010 xxxx xxxx */
3209		{ADI,"C,%b" }, /* 43: 0111 0100 0100 0011 xxxx xxxx */
3210		{ADI,"D,%b" }, /* 44: 0111 0100 0100 0100 xxxx xxxx */
3211		{ADI,"E,%b" }, /* 45: 0111 0100 0100 0101 xxxx xxxx */
3212		{ADI,"H,%b" }, /* 46: 0111 0100 0100 0110 xxxx xxxx */
3213		{ADI,"L,%b" }, /* 47: 0111 0100 0100 0111 xxxx xxxx */
3214		{ONI,"V,%b" }, /* 48: 0111 0100 0100 1000 xxxx xxxx */
3215		{ONI,"A,%b" }, /* 49: 0111 0100 0100 1001 xxxx xxxx */
3216		{ONI,"B,%b" }, /* 4a: 0111 0100 0100 1010 xxxx xxxx */
3217		{ONI,"C,%b" }, /* 4b: 0111 0100 0100 1011 xxxx xxxx */
3218		{ONI,"D,%b" }, /* 4c: 0111 0100 0100 1100 xxxx xxxx */
3219		{ONI,"E,%b" }, /* 4d: 0111 0100 0100 1101 xxxx xxxx */
3220		{ONI,"H,%b" }, /* 4e: 0111 0100 0100 1110 xxxx xxxx */
3221		{ONI,"L,%b" }, /* 4f: 0111 0100 0100 1111 xxxx xxxx */
3222
3223		{ACI,"V,%b" }, /* 50: 0111 0100 0101 0000 xxxx xxxx */
3224		{ACI,"A,%b" }, /* 51: 0111 0100 0101 0001 xxxx xxxx */
3225		{ACI,"B,%b" }, /* 52: 0111 0100 0101 0010 xxxx xxxx */
3226		{ACI,"C,%b" }, /* 53: 0111 0100 0101 0011 xxxx xxxx */
3227		{ACI,"D,%b" }, /* 54: 0111 0100 0101 0100 xxxx xxxx */
3228		{ACI,"E,%b" }, /* 55: 0111 0100 0101 0101 xxxx xxxx */
3229		{ACI,"H,%b" }, /* 56: 0111 0100 0101 0110 xxxx xxxx */
3230		{ACI,"L,%b" }, /* 57: 0111 0100 0101 0111 xxxx xxxx */
3231		{OFFI,"V,%b" }, /* 58: 0111 0100 0101 1000 xxxx xxxx */
3232		{OFFI,"A,%b" }, /* 59: 0111 0100 0101 1001 xxxx xxxx */
3233		{OFFI,"B,%b" }, /* 5a: 0111 0100 0101 1010 xxxx xxxx */
3234		{OFFI,"C,%b" }, /* 5b: 0111 0100 0101 1011 xxxx xxxx */
3235		{OFFI,"D,%b" }, /* 5c: 0111 0100 0101 1100 xxxx xxxx */
3236		{OFFI,"E,%b" }, /* 5d: 0111 0100 0101 1101 xxxx xxxx */
3237		{OFFI,"H,%b" }, /* 5e: 0111 0100 0101 1110 xxxx xxxx */
3238		{OFFI,"L,%b" }, /* 5f: 0111 0100 0101 1111 xxxx xxxx */
3239
3240		{SUI,"V,%b" }, /* 60: 0111 0100 0110 0000 xxxx xxxx */
3241		{SUI,"A,%b" }, /* 61: 0111 0100 0110 0001 xxxx xxxx */
3242		{SUI,"B,%b" }, /* 62: 0111 0100 0110 0010 xxxx xxxx */
3243		{SUI,"C,%b" }, /* 63: 0111 0100 0110 0011 xxxx xxxx */
3244		{SUI,"D,%b" }, /* 64: 0111 0100 0110 0100 xxxx xxxx */
3245		{SUI,"E,%b" }, /* 65: 0111 0100 0110 0101 xxxx xxxx */
3246		{SUI,"H,%b" }, /* 66: 0111 0100 0110 0110 xxxx xxxx */
3247		{SUI,"L,%b" }, /* 67: 0111 0100 0110 0111 xxxx xxxx */
3248		{NEI,"V,%b" }, /* 68: 0111 0100 0110 1000 xxxx xxxx */
3249		{NEI,"A,%b" }, /* 69: 0111 0100 0110 1001 xxxx xxxx */
3250		{NEI,"B,%b" }, /* 6a: 0111 0100 0110 1010 xxxx xxxx */
3251		{NEI,"C,%b" }, /* 6b: 0111 0100 0110 1011 xxxx xxxx */
3252		{NEI,"D,%b" }, /* 6c: 0111 0100 0110 1100 xxxx xxxx */
3253		{NEI,"E,%b" }, /* 6d: 0111 0100 0110 1101 xxxx xxxx */
3254		{NEI,"H,%b" }, /* 6e: 0111 0100 0110 1110 xxxx xxxx */
3255		{NEI,"L,%b" }, /* 6f: 0111 0100 0110 1111 xxxx xxxx */
3256
3257		{SBI,"V,%b" }, /* 70: 0111 0100 0111 0000 xxxx xxxx */
3258		{SBI,"A,%b" }, /* 71: 0111 0100 0111 0001 xxxx xxxx */
3259		{SBI,"B,%b" }, /* 72: 0111 0100 0111 0010 xxxx xxxx */
3260		{SBI,"C,%b" }, /* 73: 0111 0100 0111 0011 xxxx xxxx */
3261		{SBI,"D,%b" }, /* 74: 0111 0100 0111 0100 xxxx xxxx */
3262		{SBI,"E,%b" }, /* 75: 0111 0100 0111 0101 xxxx xxxx */
3263		{SBI,"H,%b" }, /* 76: 0111 0100 0111 0110 xxxx xxxx */
3264		{SBI,"L,%b" }, /* 77: 0111 0100 0111 0111 xxxx xxxx */
3265		{EQI,"V,%b" }, /* 78: 0111 0100 0111 1000 xxxx xxxx */
3266		{EQI,"A,%b" }, /* 79: 0111 0100 0111 1001 xxxx xxxx */
3267		{EQI,"B,%b" }, /* 7a: 0111 0100 0111 1010 xxxx xxxx */
3268		{EQI,"C,%b" }, /* 7b: 0111 0100 0111 1011 xxxx xxxx */
3269		{EQI,"D,%b" }, /* 7c: 0111 0100 0111 1100 xxxx xxxx */
3270		{EQI,"E,%b" }, /* 7d: 0111 0100 0111 1101 xxxx xxxx */
3271		{EQI,"H,%b" }, /* 7e: 0111 0100 0111 1110 xxxx xxxx */
3272		{EQI,"L,%b" }, /* 7f: 0111 0100 0111 1111 xxxx xxxx */
3273
3274		{illegal,0 }, /* 80: 0111 0100 1000 0000 */
3275		{illegal,0 }, /* 81: 0111 0100 1000 0001 */
3276		{illegal,0 }, /* 82: 0111 0100 1000 0010 */
3277		{illegal,0 }, /* 83: 0111 0100 1000 0011 */
3278		{illegal,0 }, /* 84: 0111 0100 1000 0100 */
3279		{illegal,0 }, /* 85: 0111 0100 1000 0101 */
3280		{illegal,0 }, /* 86: 0111 0100 1000 0110 */
3281		{illegal,0 }, /* 87: 0111 0100 1000 0111 */
3282		{ANAW,"%a" }, /* 88: 0111 0100 1000 1000 oooo oooo */
3283		{illegal,0 }, /* 89: 0111 0100 1000 1001 */
3284		{illegal,0 }, /* 8a: 0111 0100 1000 1010 */
3285		{illegal,0 }, /* 8b: 0111 0100 1000 1011 */
3286		{illegal,0 }, /* 8c: 0111 0100 1000 1100 */
3287		{DAN,"EA,BC" }, /* 8d: 0111 0100 1000 1101 */
3288		{DAN,"EA,DE" }, /* 8e: 0111 0100 1000 1110 */
3289		{DAN,"EA,HL" }, /* 8f: 0111 0100 1000 1111 */
3290
3291		{XRAW,"%a" }, /* 90: 0111 0100 1001 0000 oooo oooo */
3292		{illegal,0 }, /* 91: 0111 0100 1001 0001 */
3293		{illegal,0 }, /* 92: 0111 0100 1001 0010 */
3294		{illegal,0 }, /* 93: 0111 0100 1001 0011 */
3295		{illegal,0 }, /* 94: 0111 0100 1001 0100 */
3296		{DXR,"EA,BC" }, /* 95: 0111 0100 1001 0101 */
3297		{DXR,"EA,DE" }, /* 96: 0111 0100 1001 0110 */
3298		{DXR,"EA,HL" }, /* 97: 0111 0100 1001 0111 */
3299		{ORAW,"%a" }, /* 98: 0111 0100 1001 1000 oooo oooo */
3300		{illegal,0 }, /* 99: 0111 0100 1001 1001 */
3301		{illegal,0 }, /* 9a: 0111 0100 1001 1010 */
3302		{illegal,0 }, /* 9b: 0111 0100 1001 1011 */
3303		{illegal,0 }, /* 9c: 0111 0100 1001 1100 */
3304		{DOR,"EA,BC" }, /* 9d: 0111 0100 1001 1101 */
3305		{DOR,"EA,DE" }, /* 9e: 0111 0100 1001 1110 */
3306		{DOR,"EA,HL" }, /* 9f: 0111 0100 1001 1111 */
3307
3308		{ADDNCW,"%a" }, /* a0: 0111 0100 1010 0000 oooo oooo */
3309		{illegal,0 }, /* a1: 0111 0100 1010 0001 */
3310		{illegal,0 }, /* a2: 0111 0100 1010 0010 */
3311		{illegal,0 }, /* a3: 0111 0100 1010 0011 */
3312		{illegal,0 }, /* a4: 0111 0100 1010 0100 */
3313		{DADDNC,"EA,BC" }, /* a5: 0111 0100 1010 0101 */
3314		{DADDNC,"EA,DE" }, /* a6: 0111 0100 1010 0110 */
3315		{DADDNC,"EA,HL" }, /* a7: 0111 0100 1010 0111 */
3316		{GTAW,"%a" }, /* a8: 0111 0100 1010 1000 oooo oooo */
3317		{illegal,0 }, /* a9: 0111 0100 1010 1001 */
3318		{illegal,0 }, /* aa: 0111 0100 1010 1010 */
3319		{illegal,0 }, /* ab: 0111 0100 1010 1011 */
3320		{illegal,0 }, /* ac: 0111 0100 1010 1100 */
3321		{DGT,"EA,BC" }, /* ad: 0111 0100 1010 1101 */
3322		{DGT,"EA,DE" }, /* ae: 0111 0100 1010 1110 */
3323		{DGT,"EA,HL" }, /* af: 0111 0100 1010 1111 */
3324
3325		{SUBNBW,"%a" }, /* b0: 0111 0100 1011 0000 oooo oooo */
3326		{illegal,0 }, /* b1: 0111 0100 1011 0001 */
3327		{illegal,0 }, /* b2: 0111 0100 1011 0010 */
3328		{illegal,0 }, /* b3: 0111 0100 1011 0011 */
3329		{illegal,0 }, /* b4: 0111 0100 1011 0100 */
3330		{DSUBNB,"EA,BC" }, /* b5: 0111 0100 1011 0101 */
3331		{DSUBNB,"EA,DE" }, /* b6: 0111 0100 1011 0110 */
3332		{DSUBNB,"EA,HL" }, /* b7: 0111 0100 1011 0111 */
3333		{LTAW,"%a" }, /* b8: 0111 0100 1011 1000 oooo oooo */
3334		{illegal,0 }, /* b9: 0111 0100 1011 1001 */
3335		{illegal,0 }, /* ba: 0111 0100 1011 1010 */
3336		{illegal,0 }, /* bb: 0111 0100 1011 1011 */
3337		{illegal,0 }, /* bc: 0111 0100 1011 1100 */
3338		{DLT,"EA,BC" }, /* bd: 0111 0100 1011 1101 */
3339		{DLT,"EA,DE" }, /* be: 0111 0100 1011 1110 */
3340		{DLT,"EA,HL" }, /* bf: 0111 0100 1011 1111 */
3341
3342		{ADDW,"%a" }, /* c0: 0111 0100 1100 0000 oooo oooo */
3343		{illegal,0 }, /* c1: 0111 0100 1100 0001 */
3344		{illegal,0 }, /* c2: 0111 0100 1100 0010 */
3345		{illegal,0 }, /* c3: 0111 0100 1100 0011 */
3346		{illegal,0 }, /* c4: 0111 0100 1100 0100 */
3347		{DADD,"EA,BC" }, /* c5: 0111 0100 1100 0101 */
3348		{DADD,"EA,DE" }, /* c6: 0111 0100 1100 0110 */
3349		{DADD,"EA,HL" }, /* c7: 0111 0100 1100 0111 */
3350		{ONAW,"%a" }, /* c8: 0111 0100 1100 1000 oooo oooo */
3351		{illegal,0 }, /* c9: 0111 0100 1100 1001 */
3352		{illegal,0 }, /* ca: 0111 0100 1100 1010 */
3353		{illegal,0 }, /* cb: 0111 0100 1100 1011 */
3354		{illegal,0 }, /* cc: 0111 0100 1100 1100 */
3355		{DON,"EA,BC" }, /* cd: 0111 0100 1100 1101 */
3356		{DON,"EA,DE" }, /* ce: 0111 0100 1100 1110 */
3357		{DON,"EA,HL" }, /* cf: 0111 0100 1100 1111 */
3358
3359		{ADCW,"%a" }, /* d0: 0111 0100 1101 0000 oooo oooo */
3360		{illegal,0 }, /* d1: 0111 0100 1101 0001 */
3361		{illegal,0 }, /* d2: 0111 0100 1101 0010 */
3362		{illegal,0 }, /* d3: 0111 0100 1101 0011 */
3363		{illegal,0 }, /* d4: 0111 0100 1101 0100 */
3364		{DADC,"EA,BC" }, /* d5: 0111 0100 1101 0101 */
3365		{DADC,"EA,DE" }, /* d6: 0111 0100 1101 0110 */
3366		{DADC,"EA,HL" }, /* d7: 0111 0100 1101 0111 */
3367		{OFFAW,"%a" }, /* d8: 0111 0100 1101 1000 oooo oooo */
3368		{illegal,0 }, /* d9: 0111 0100 1101 1001 */
3369		{illegal,0 }, /* da: 0111 0100 1101 1010 */
3370		{illegal,0 }, /* db: 0111 0100 1101 1011 */
3371		{illegal,0 }, /* dc: 0111 0100 1101 1100 */
3372		{DOFF,"EA,BC" }, /* dd: 0111 0100 1101 1101 */
3373		{DOFF,"EA,DE" }, /* de: 0111 0100 1101 1110 */
3374		{DOFF,"EA,HL" }, /* df: 0111 0100 1101 1111 */
3375
3376		{SUBW,"%a" }, /* e0: 0111 0100 1110 0000 oooo oooo */
3377		{illegal,0 }, /* e1: 0111 0100 1110 0001 */
3378		{illegal,0 }, /* e2: 0111 0100 1110 0010 */
3379		{illegal,0 }, /* e3: 0111 0100 1110 0011 */
3380		{illegal,0 }, /* e4: 0111 0100 1110 0100 */
3381		{DSUB,"EA,BC" }, /* e5: 0111 0100 1110 0101 */
3382		{DSUB,"EA,DE" }, /* e6: 0111 0100 1110 0110 */
3383		{DSUB,"EA,HL" }, /* e7: 0111 0100 1110 0111 */
3384		{NEAW,"%a" }, /* e8: 0111 0100 1110 1000 oooo oooo */
3385		{illegal,0 }, /* e9: 0111 0100 1110 1001 */
3386		{illegal,0 }, /* ea: 0111 0100 1110 1010 */
3387		{illegal,0 }, /* eb: 0111 0100 1110 1011 */
3388		{illegal,0 }, /* ec: 0111 0100 1110 1100 */
3389		{DNE,"EA,BC" }, /* ed: 0111 0100 1110 1101 */
3390		{DNE,"EA,DE" }, /* ee: 0111 0100 1110 1110 */
3391		{DNE,"EA,HL" }, /* ef: 0111 0100 1110 1111 */
3392
3393		{SBBW,"%a" }, /* f0: 0111 0100 1111 0000 oooo oooo */
3394		{illegal,0 }, /* f1: 0111 0100 1111 0001 */
3395		{illegal,0 }, /* f2: 0111 0100 1111 0010 */
3396		{illegal,0 }, /* f3: 0111 0100 1111 0011 */
3397		{illegal,0 }, /* f4: 0111 0100 1111 0100 */
3398		{DSBB,"EA,BC" }, /* f5: 0111 0100 1111 0101 */
3399		{DSBB,"EA,DE" }, /* f6: 0111 0100 1111 0110 */
3400		{DSBB,"EA,HL" }, /* f7: 0111 0100 1111 0111 */
3401		{EQAW,"%a" }, /* f8: 0111 0100 1111 1000 oooo oooo */
3402		{illegal,0 }, /* f9: 0111 0100 1111 1001 */
3403		{illegal,0 }, /* fa: 0111 0100 1111 1010 */
3404		{illegal,0 }, /* fb: 0111 0100 1111 1011 */
3405		{illegal,0 }, /* fc: 0111 0100 1111 1100 */
3406		{DEQ,"EA,BC" }, /* fd: 0111 0100 1111 1101 */
3407		{DEQ,"EA,DE" }, /* fe: 0111 0100 1111 1110 */
3408		{DEQ,"EA,HL" } /* ff: 0111 0100 1111 1111 */
3409		};
3410
3411		/* main opcodes */
3412		static const struct dasm_s dasmXX_7810[256] =
3413		{
3414		{NOP,0 }, /* 00: 0000 0000 */
3415		{LDAW,"%a" }, /* 01: 0000 0001 oooo oooo */
3416		{INX,"SP" }, /* 02: 0000 0010 */
3417		{DCX,"SP" }, /* 03: 0000 0011 */
3418		{LXI,"SP,%w" }, /* 04: 0000 0100 llll llll hhhh hhhh */
3419		{ANIW,"%a,%b" }, /* 05: 0000 0101 oooo oooo xxxx xxxx */
3420		{illegal,0 }, /* 06: */
3421		{ANI,"A,%b" }, /* 07: 0000 0111 xxxx xxxx */
3422		{MOV,"A,EAH" }, /* 08: 0000 1000 */
3423		{MOV,"A,EAL" }, /* 09: 0000 1001 */
3424		{MOV,"A,B" }, /* 0a: 0000 1010 */
3425		{MOV,"A,C" }, /* 0b: 0000 1011 */
3426		{MOV,"A,D" }, /* 0c: 0000 1100 */
3427		{MOV,"A,E" }, /* 0d: 0000 1101 */
3428		{MOV,"A,H" }, /* 0e: 0000 1110 */
3429		{MOV,"A,L" }, /* 0f: 0000 1111 */
3430
3431		{EXA,0 }, /* 10: 0001 0000 / / 7810 */
3432		{EXX,0 }, /* 11: 0001 0001 / / 7810 */
3433		{INX,"BC" }, /* 12: 0001 0010 */
3434		{DCX,"BC" }, /* 13: 0001 0011 */
3435		{LXI,"BC,%w" }, /* 14: 0001 0100 llll llll hhhh hhhh */
3436		{ORIW,"%a,%b" }, /* 15: 0001 0101 oooo oooo xxxx xxxx */
3437		{XRI,"A,%b" }, /* 16: 0001 0110 xxxx xxxx */
3438		{ORI,"A,%b" }, /* 17: 0001 0111 xxxx xxxx */
3439		{MOV,"EAH,A" }, /* 18: 0001 1000 */
3440		{MOV,"EAL,A" }, /* 19: 0001 1001 */
3441		{MOV,"B,A" }, /* 1a: 0001 1010 */
3442		{MOV,"C,A" }, /* 1b: 0001 1011 */
3443		{MOV,"D,A" }, /* 1c: 0001 1100 */
3444		{MOV,"E,A" }, /* 1d: 0001 1101 */
3445		{MOV,"H,A" }, /* 1e: 0001 1110 */
3446		{MOV,"L,A" }, /* 1f: 0001 1111 */
3447
3448		{INRW,"%a" }, /* 20: 0010 0000 oooo oooo */
3449		{JB,0 }, /* 21: 0010 0001 */
3450		{INX,"DE" }, /* 22: 0010 0010 */
3451		{DCX,"DE" }, /* 23: 0010 0011 */
3452		{LXI,"DE,%w" }, /* 24: 0010 0100 llll llll hhhh hhhh */
3453		{GTIW,"%a,%b" }, /* 25: 0010 0101 oooo oooo xxxx xxxx */
3454		{ADINC,"A,%b" }, /* 26: 0010 0110 xxxx xxxx */
3455		{GTI,"A,%b" }, /* 27: 0010 0111 xxxx xxxx */
3456		{illegal,0 }, /* 28: 0010 1000 */
3457		{LDAX,"(BC)" }, /* 29: 0010 1001 */
3458		{LDAX,"(DE)" }, /* 2a: 0010 1010 */
3459		{LDAX,"(HL)" }, /* 2b: 0010 1011 */
3460		{LDAX,"(DE+)" }, /* 2c: 0010 1100 */
3461		{LDAX,"(HL+)" }, /* 2d: 0010 1101 */
3462		{LDAX,"(DE-)" }, /* 2e: 0010 1110 */
3463		{LDAX,"(HL-)" }, /* 2f: 0010 1111 */
3464
3465		{DCRW,"%a" }, /* 30: 0011 0000 oooo oooo */
3466		{BLOCK,0 }, /* 31: 0011 0001 / / 7810 */
3467		{INX,"HL", }, /* 32: 0011 0010 */
3468		{DCX,"HL", }, /* 33: 0011 0011 */
3469		{LXI,"HL,%w" }, /* 34: 0011 0100 llll llll hhhh hhhh */
3470		{LTIW,"%a,%b" }, /* 35: 0011 0101 oooo oooo xxxx xxxx */
3471		{SUINB,"A,%b" }, /* 36: 0011 0110 xxxx xxxx */
3472		{LTI,"A,%b" }, /* 37: 0011 0111 xxxx xxxx */
3473		{illegal,0 }, /* 38: */
3474		{STAX,"(BC)" }, /* 39: 0011 1001 */
3475		{STAX,"(DE)" }, /* 3a: 0011 1010 */
3476		{STAX,"(HL)" }, /* 3b: 0011 1011 */
3477		{STAX,"(DE+)" }, /* 3c: 0011 1100 */
3478		{STAX,"(HL+)" }, /* 3d: 0011 1101 */
3479		{STAX,"(DE-)" }, /* 3e: 0011 1110 */
3480		{STAX,"(HL-)" }, /* 3f: 0011 1111 */
3481
3482		{CALL,"%w" }, /* 40: 0100 0000 llll llll hhhh hhhh */
3483		{INR,"A" }, /* 41: 0100 0001 */
3484		{INR,"B" }, /* 42: 0100 0010 */
3485		{INR,"C" }, /* 43: 0100 0011 */
3486		{LXI,"EA,%w" }, /* 44: 0100 0100 llll llll hhhh hhhh */
3487		{ONIW,"%a,%b" }, /* 45: 0100 0101 oooo oooo xxxx xxxx */
3488		{ADI,"A,%b" }, /* 46: 0100 0110 xxxx xxxx */
3489		{ONI,"A,%b" }, /* 47: 0100 0111 xxxx xxxx */
3490		{0,dasm48_7810 }, /* 48: prefix */
3491		{MVIX,"BC,%b" }, /* 49: 0100 1001 xxxx xxxx */
3492		{MVIX,"DE,%b" }, /* 4a: 0100 1010 xxxx xxxx */
3493		{MVIX,"HL,%b" }, /* 4b: 0100 1011 xxxx xxxx */
3494		{0,dasm4C_7810 }, /* 4c: prefix */
3495		{0,dasm4D_7810 }, /* 4d: prefix */
3496		{JRE,"%d" }, /* 4e: 0100 111d dddd dddd */
3497		{JRE,"%d" }, /* 4f: 0100 111d dddd dddd */
3498
3499		{EXH,0 }, /* 50: 0101 0000 / / 7810 */
3500		{DCR,"A" }, /* 51: 0101 0001 */
3501		{DCR,"B" }, /* 52: 0101 0010 */
3502		{DCR,"C" }, /* 53: 0101 0011 */
3503		{JMP,"%w" }, /* 54: 0101 0100 llll llll hhhh hhhh */
3504		{OFFIW,"%a,%b" }, /* 55: 0101 0101 oooo oooo xxxx xxxx */
3505		{ACI,"A,%b" }, /* 56: 0101 0110 xxxx xxxx */
3506		{OFFI,"A,%b" }, /* 57: 0101 0111 xxxx xxxx */
3507		{BIT,"0,%a", }, /* 58: 0101 1000 oooo oooo / / 7810 */
3508		{BIT,"1,%a", }, /* 59: 0101 1001 oooo oooo / / 7810 */
3509		{BIT,"2,%a", }, /* 5a: 0101 1010 oooo oooo / / 7810 */
3510		{BIT,"3,%a", }, /* 5b: 0101 1011 oooo oooo / / 7810 */
3511		{BIT,"4,%a", }, /* 5c: 0101 1100 oooo oooo / / 7810 */
3512		{BIT,"5,%a", }, /* 5d: 0101 1101 oooo oooo / / 7810 */
3513		{BIT,"6,%a", }, /* 5e: 0101 1110 oooo oooo / / 7810 */
3514		{BIT,"7,%a", }, /* 5f: 0101 1111 oooo oooo / / 7810 */
3515
3516		{0,dasm60 }, /* 60: prefix */
3517		{DAA,0 }, /* 61: 0110 0001 */
3518		{RETI,0 }, /* 62: 0110 0010 */
3519		{STAW,"%a" }, /* 63: 0110 0011 oooo oooo */
3520		{0,dasm64_7810 }, /* 64: prefix */
3521		{NEIW,"%a,%b" }, /* 65: 0110 0101 oooo oooo xxxx xxxx */
3522		{SUI,"A,%b" }, /* 66: 0110 0110 xxxx xxxx */
3523		{NEI,"A,%b" }, /* 67: 0110 0111 xxxx xxxx */
3524		{MVI,"V,%b" }, /* 68: 0110 1000 xxxx xxxx */
3525		{MVI,"A,%b" }, /* 69: 0110 1001 xxxx xxxx */
3526		{MVI,"B,%b" }, /* 6a: 0110 1010 xxxx xxxx */
3527		{MVI,"C,%b" }, /* 6b: 0110 1011 xxxx xxxx */
3528		{MVI,"D,%b" }, /* 6c: 0110 1100 xxxx xxxx */
3529		{MVI,"E,%b" }, /* 6d: 0110 1101 xxxx xxxx */
3530		{MVI,"H,%b" }, /* 6e: 0110 1110 xxxx xxxx */
3531		{MVI,"L,%b" }, /* 6f: 0110 1111 xxxx xxxx */
3532
3533		{0,dasm70 }, /* 70: prefix */
3534		{MVIW,"%a,%b" }, /* 71: 0111 0001 oooo oooo xxxx xxxx */
3535		{SOFTI,0 }, /* 72: 0111 0010 */
3536		{illegal,0 }, /* 73: */
3537		{0,dasm74 }, /* 74: prefix */
3538		{EQIW,"%a,%b" }, /* 75: 0111 0101 oooo oooo xxxx xxxx */
3539		{SBI,"A,%b" }, /* 76: 0111 0110 xxxx xxxx */
3540		{EQI,"A,%b" }, /* 77: 0111 0111 xxxx xxxx */
3541		{CALF,"%f" }, /* 78: 0111 1ddd dddd dddd */
3542		{CALF,"%f" }, /* 79: 0111 1ddd dddd dddd */
3543		{CALF,"%f" }, /* 7a: 0111 1ddd dddd dddd */
3544		{CALF,"%f" }, /* 7b: 0111 1ddd dddd dddd */
3545		{CALF,"%f" }, /* 7c: 0111 1ddd dddd dddd */
3546		{CALF,"%f" }, /* 7d: 0111 1ddd dddd dddd */
3547		{CALF,"%f" }, /* 7e: 0111 1ddd dddd dddd */
3548		{CALF,"%f" }, /* 7f: 0111 1ddd dddd dddd */
3549
3550		{CALT,"%t" }, /* 80: 100t tttt */
3551		{CALT,"%t" }, /* 81: 100t tttt */
3552		{CALT,"%t" }, /* 82: 100t tttt */
3553		{CALT,"%t" }, /* 83: 100t tttt */
3554		{CALT,"%t" }, /* 84: 100t tttt */
3555		{CALT,"%t" }, /* 85: 100t tttt */
3556		{CALT,"%t" }, /* 86: 100t tttt */
3557		{CALT,"%t" }, /* 87: 100t tttt */
3558		{CALT,"%t" }, /* 88: 100t tttt */
3559		{CALT,"%t" }, /* 89: 100t tttt */
3560		{CALT,"%t" }, /* 8a: 100t tttt */
3561		{CALT,"%t" }, /* 8b: 100t tttt */
3562		{CALT,"%t" }, /* 8c: 100t tttt */
3563		{CALT,"%t" }, /* 8d: 100t tttt */
3564		{CALT,"%t" }, /* 8e: 100t tttt */
3565		{CALT,"%t" }, /* 8f: 100t tttt */
3566
3567		{CALT,"%t" }, /* 90: 100t tttt */
3568		{CALT,"%t" }, /* 91: 100t tttt */
3569		{CALT,"%t" }, /* 92: 100t tttt */
3570		{CALT,"%t" }, /* 93: 100t tttt */
3571		{CALT,"%t" }, /* 94: 100t tttt */
3572		{CALT,"%t" }, /* 95: 100t tttt */
3573		{CALT,"%t" }, /* 96: 100t tttt */
3574		{CALT,"%t" }, /* 97: 100t tttt */
3575		{CALT,"%t" }, /* 98: 100t tttt */
3576		{CALT,"%t" }, /* 99: 100t tttt */
3577		{CALT,"%t" }, /* 9a: 100t tttt */
3578		{CALT,"%t" }, /* 9b: 100t tttt */
3579		{CALT,"%t" }, /* 9c: 100t tttt */
3580		{CALT,"%t" }, /* 9d: 100t tttt */
3581		{CALT,"%t" }, /* 9e: 100t tttt */
3582		{CALT,"%t" }, /* 9f: 100t tttt */
3583
3584		{POP,"VA" }, /* a0: 1010 0000 */
3585		{POP,"BC" }, /* a1: 1010 0001 */
3586		{POP,"DE" }, /* a2: 1010 0010 */
3587		{POP,"HL", }, /* a3: 1010 0011 */
3588		{POP,"EA" }, /* a4: 1010 0100 */
3589		{DMOV,"EA,BC" }, /* a5: 1010 0101 */
3590		{DMOV,"EA,DE" }, /* a6: 1010 0110 */
3591		{DMOV,"EA,HL" }, /* a7: 1010 0111 */
3592		{INX,"EA" }, /* a8: 1010 1000 */
3593		{DCX,"EA" }, /* a9: 1010 1001 */
3594		{EI,0 }, /* aa: 1010 1010 */
3595		{LDAX,"(DE+%b)" }, /* ab: 1010 1011 dddd dddd */
3596		{LDAX,"(HL+A)" }, /* ac: 1010 1100 */
3597		{LDAX,"(HL+B)" }, /* ad: 1010 1101 */
3598		{LDAX,"(HL+EA)" }, /* ae: 1010 1110 */
3599		{LDAX,"(HL+%b)" }, /* af: 1010 1111 dddd dddd */
3600
3601		{PUSH,"VA" }, /* b0: 1011 0000 */
3602		{PUSH,"BC" }, /* b1: 1011 0001 */
3603		{PUSH,"DE" }, /* b2: 1011 0010 */
3604		{PUSH,"HL", }, /* b3: 1011 0011 */
3605		{PUSH,"EA" }, /* b4: 1011 0100 */
3606		{DMOV,"BC,EA" }, /* b5: 1011 0101 */
3607		{DMOV,"DE,EA" }, /* b6: 1011 0110 */
3608		{DMOV,"HL,EA" }, /* b7: 1011 0111 */
3609		{RET,0 }, /* b8: 1011 1000 */
3610		{RETS,0 }, /* b9: 1011 1001 */
3611		{DI,0 }, /* ba: 1011 1010 */
3612		{STAX,"(DE+%b)" }, /* bb: 1011 1011 dddd dddd */
3613		{STAX,"(HL+A)" }, /* bc: 1011 1100 */
3614		{STAX,"(HL+B)" }, /* bd: 1011 1101 */
3615		{STAX,"(HL+EA)" }, /* be: 1011 1110 */
3616		{STAX,"(HL+%b)" }, /* bf: 1011 1111 dddd dddd */
3617
3618		{JR,"%o" }, /* c0: 11oo oooo */
3619		{JR,"%o" }, /* c1: 11oo oooo */
3620		{JR,"%o" }, /* c2: 11oo oooo */
3621		{JR,"%o" }, /* c3: 11oo oooo */
3622		{JR,"%o" }, /* c4: 11oo oooo */
3623		{JR,"%o" }, /* c5: 11oo oooo */
3624		{JR,"%o" }, /* c6: 11oo oooo */
3625		{JR,"%o" }, /* c7: 11oo oooo */
3626		{JR,"%o" }, /* c8: 11oo oooo */
3627		{JR,"%o" }, /* c9: 11oo oooo */
3628		{JR,"%o" }, /* ca: 11oo oooo */
3629		{JR,"%o" }, /* cb: 11oo oooo */
3630		{JR,"%o" }, /* cc: 11oo oooo */
3631		{JR,"%o" }, /* cd: 11oo oooo */
3632		{JR,"%o" }, /* ce: 11oo oooo */
3633		{JR,"%o" }, /* cf: 11oo oooo */
3634
3635		{JR,"%o" }, /* d0: 11oo oooo */
3636		{JR,"%o" }, /* d1: 11oo oooo */
3637		{JR,"%o" }, /* d2: 11oo oooo */
3638		{JR,"%o" }, /* d3: 11oo oooo */
3639		{JR,"%o" }, /* d4: 11oo oooo */
3640		{JR,"%o" }, /* d5: 11oo oooo */
3641		{JR,"%o" }, /* d6: 11oo oooo */
3642		{JR,"%o" }, /* d7: 11oo oooo */
3643		{JR,"%o" }, /* d8: 11oo oooo */
3644		{JR,"%o" }, /* d9: 11oo oooo */
3645		{JR,"%o" }, /* da: 11oo oooo */
3646		{JR,"%o" }, /* db: 11oo oooo */
3647		{JR,"%o" }, /* dc: 11oo oooo */
3648		{JR,"%o" }, /* dd: 11oo oooo */
3649		{JR,"%o" }, /* de: 11oo oooo */
3650		{JR,"%o" }, /* df: 11oo oooo */
3651
3652		{JR,"%o" }, /* e0: 11oo oooo */
3653		{JR,"%o" }, /* e1: 11oo oooo */
3654		{JR,"%o" }, /* e2: 11oo oooo */
3655		{JR,"%o" }, /* e3: 11oo oooo */
3656		{JR,"%o" }, /* e4: 11oo oooo */
3657		{JR,"%o" }, /* e5: 11oo oooo */
3658		{JR,"%o" }, /* e6: 11oo oooo */
3659		{JR,"%o" }, /* e7: 11oo oooo */
3660		{JR,"%o" }, /* e8: 11oo oooo */
3661		{JR,"%o" }, /* e9: 11oo oooo */
3662		{JR,"%o" }, /* ea: 11oo oooo */
3663		{JR,"%o" }, /* eb: 11oo oooo */
3664		{JR,"%o" }, /* ec: 11oo oooo */
3665		{JR,"%o" }, /* ed: 11oo oooo */
3666		{JR,"%o" }, /* ee: 11oo oooo */
3667		{JR,"%o" }, /* ef: 11oo oooo */
3668
3669		{JR,"%o" }, /* f0: 11oo oooo */
3670		{JR,"%o" }, /* f1: 11oo oooo */
3671		{JR,"%o" }, /* f2: 11oo oooo */
3672		{JR,"%o" }, /* f3: 11oo oooo */
3673		{JR,"%o" }, /* f4: 11oo oooo */
3674		{JR,"%o" }, /* f5: 11oo oooo */
3675		{JR,"%o" }, /* f6: 11oo oooo */
3676		{JR,"%o" }, /* f7: 11oo oooo */
3677		{JR,"%o" }, /* f8: 11oo oooo */
3678		{JR,"%o" }, /* f9: 11oo oooo */
3679		{JR,"%o" }, /* fa: 11oo oooo */
3680		{JR,"%o" }, /* fb: 11oo oooo */
3681		{JR,"%o" }, /* fc: 11oo oooo */
3682		{JR,"%o" }, /* fd: 11oo oooo */
3683		{JR,"%o" }, /* fe: 11oo oooo */
3684		{JR,"%o" } /* ff: 11oo oooo */
3685		};
3686
3687		static const struct dasm_s dasmXX_7807[256] =
3688		{
3689		{NOP,0 }, /* 00: 0000 0000 */
3690		{LDAW,"%a" }, /* 01: 0000 0001 oooo oooo */
3691		{INX,"SP" }, /* 02: 0000 0010 */
3692		{DCX,"SP" }, /* 03: 0000 0011 */
3693		{LXI,"SP,%w" }, /* 04: 0000 0100 llll llll hhhh hhhh */
3694		{ANIW,"%a,%b" }, /* 05: 0000 0101 oooo oooo xxxx xxxx */
3695		{illegal,0 }, /* 06: */
3696		{ANI,"A,%b" }, /* 07: 0000 0111 xxxx xxxx */
3697		{MOV,"A,EAH" }, /* 08: 0000 1000 */
3698		{MOV,"A,EAL" }, /* 09: 0000 1001 */
3699		{MOV,"A,B" }, /* 0a: 0000 1010 */
3700		{MOV,"A,C" }, /* 0b: 0000 1011 */
3701		{MOV,"A,D" }, /* 0c: 0000 1100 */
3702		{MOV,"A,E" }, /* 0d: 0000 1101 */
3703		{MOV,"A,H" }, /* 0e: 0000 1110 */
3704		{MOV,"A,L" }, /* 0f: 0000 1111 */
3705
3706		{BLOCK,"D+" }, /* 10: 0001 0000 / / 7807 */
3707		{BLOCK,"D-" }, /* 11: 0001 0001 / / 7807 */
3708		{INX,"BC" }, /* 12: 0001 0010 */
3709		{DCX,"BC" }, /* 13: 0001 0011 */
3710		{LXI,"BC,%w" }, /* 14: 0001 0100 llll llll hhhh hhhh */
3711		{ORIW,"%a,%b" }, /* 15: 0001 0101 oooo oooo xxxx xxxx */
3712		{XRI,"A,%b" }, /* 16: 0001 0110 xxxx xxxx */
3713		{ORI,"A,%b" }, /* 17: 0001 0111 xxxx xxxx */
3714		{MOV,"EAH,A" }, /* 18: 0001 1000 */
3715		{MOV,"EAL,A" }, /* 19: 0001 1001 */
3716		{MOV,"B,A" }, /* 1a: 0001 1010 */
3717		{MOV,"C,A" }, /* 1b: 0001 1011 */
3718		{MOV,"D,A" }, /* 1c: 0001 1100 */
3719		{MOV,"E,A" }, /* 1d: 0001 1101 */
3720		{MOV,"H,A" }, /* 1e: 0001 1110 */
3721		{MOV,"L,A" }, /* 1f: 0001 1111 */
3722
3723		{INRW,"%a" }, /* 20: 0010 0000 oooo oooo */
3724		{JB,0 }, /* 21: 0010 0001 */
3725		{INX,"DE" }, /* 22: 0010 0010 */
3726		{DCX,"DE" }, /* 23: 0010 0011 */
3727		{LXI,"DE,%w" }, /* 24: 0010 0100 llll llll hhhh hhhh */
3728		{GTIW,"%a,%b" }, /* 25: 0010 0101 oooo oooo xxxx xxxx */
3729		{ADINC,"A,%b" }, /* 26: 0010 0110 xxxx xxxx */
3730		{GTI,"A,%b" }, /* 27: 0010 0111 xxxx xxxx */
3731		{illegal,0 }, /* 28: 0010 1000 */
3732		{LDAX,"(BC)" }, /* 29: 0010 1001 */
3733		{LDAX,"(DE)" }, /* 2a: 0010 1010 */
3734		{LDAX,"(HL)" }, /* 2b: 0010 1011 */
3735		{LDAX,"(DE+)" }, /* 2c: 0010 1100 */
3736		{LDAX,"(HL+)" }, /* 2d: 0010 1101 */
3737		{LDAX,"(DE-)" }, /* 2e: 0010 1110 */
3738		{LDAX,"(HL-)" }, /* 2f: 0010 1111 */
3739
3740		{DCRW,"%a" }, /* 30: 0011 0000 oooo oooo */
3741		{AND,"CY,%i" }, /* 31: 0011 0001 bbbb bbbb / / 7807 */
3742		{INX,"HL", }, /* 32: 0011 0010 */
3743		{DCX,"HL", }, /* 33: 0011 0011 */
3744		{LXI,"HL,%w" }, /* 34: 0011 0100 llll llll hhhh hhhh */
3745		{LTIW,"%a,%b" }, /* 35: 0011 0101 oooo oooo xxxx xxxx */
3746		{SUINB,"A,%b" }, /* 36: 0011 0110 xxxx xxxx */
3747		{LTI,"A,%b" }, /* 37: 0011 0111 xxxx xxxx */
3748		{illegal,0 }, /* 38: */
3749		{STAX,"(BC)" }, /* 39: 0011 1001 */
3750		{STAX,"(DE)" }, /* 3a: 0011 1010 */
3751		{STAX,"(HL)" }, /* 3b: 0011 1011 */
3752		{STAX,"(DE+)" }, /* 3c: 0011 1100 */
3753		{STAX,"(HL+)" }, /* 3d: 0011 1101 */
3754		{STAX,"(DE-)" }, /* 3e: 0011 1110 */
3755		{STAX,"(HL-)" }, /* 3f: 0011 1111 */
3756
3757		{CALL,"%w" }, /* 40: 0100 0000 llll llll hhhh hhhh */
3758		{INR,"A" }, /* 41: 0100 0001 */
3759		{INR,"B" }, /* 42: 0100 0010 */
3760		{INR,"C" }, /* 43: 0100 0011 */
3761		{LXI,"EA,%w" }, /* 44: 0100 0100 llll llll hhhh hhhh */
3762		{ONIW,"%a,%b" }, /* 45: 0100 0101 oooo oooo xxxx xxxx */
3763		{ADI,"A,%b" }, /* 46: 0100 0110 xxxx xxxx */
3764		{ONI,"A,%b" }, /* 47: 0100 0111 xxxx xxxx */
3765		{0,dasm48_7807 }, /* 48: prefix */
3766		{MVIX,"BC,%b" }, /* 49: 0100 1001 xxxx xxxx */
3767		{MVIX,"DE,%b" }, /* 4a: 0100 1010 xxxx xxxx */
3768		{MVIX,"HL,%b" }, /* 4b: 0100 1011 xxxx xxxx */
3769		{0,dasm4C_7807 }, /* 4c: prefix */
3770		{0,dasm4D_7807 }, /* 4d: prefix */
3771		{JRE,"%d" }, /* 4e: 0100 111d dddd dddd */
3772		{JRE,"%d" }, /* 4f: 0100 111d dddd dddd */
3773		{SKN,"%i" }, /* 50: 0101 0000 bbbb bbbb / / 7807 */
3774		{DCR,"A" }, /* 51: 0101 0001 */
3775		{DCR,"B" }, /* 52: 0101 0010 */
3776		{DCR,"C" }, /* 53: 0101 0011 */
3777		{JMP,"%w" }, /* 54: 0101 0100 llll llll hhhh hhhh */
3778		{OFFIW,"%a,%b" }, /* 55: 0101 0101 oooo oooo xxxx xxxx */
3779		{ACI,"A,%b" }, /* 56: 0101 0110 xxxx xxxx */
3780		{OFFI,"A,%b" }, /* 57: 0101 0111 xxxx xxxx */
3781		{SETB,"%i" }, /* 58: 0101 1000 bbbb bbbb / / 7807 */
3782		{NOT,"%i" }, /* 59: 0101 1001 bbbb bbbb / / 7807 */
3783		{MOV,"%i,CY" }, /* 5a: 0101 1010 bbbb bbbb / / 7807 */
3784		{CLR,"%i" }, /* 5b: 0101 1011 bbbb bbbb / / 7807 */
3785		{OR,"CY,%i" }, /* 5c: 0101 1100 bbbb bbbb / / 7807 */
3786		{SK,"%i" }, /* 5d: 0101 1101 bbbb bbbb / / 7807 */
3787		{XOR,"CY,%i" }, /* 5e: 0101 1110 bbbb bbbb / / 7807 */
3788		{MOV,"CY,%i" }, /* 5f: 0101 1111 bbbb bbbb / / 7807 */
3789
3790		{0,dasm60 }, /* 60: prefix */
3791		{DAA,0 }, /* 61: 0110 0001 */
3792		{RETI,0 }, /* 62: 0110 0010 */
3793		{STAW,"%a" }, /* 63: 0110 0011 oooo oooo */
3794		{0,dasm64_7807 }, /* 64: prefix */
3795		{NEIW,"%a,%b" }, /* 65: 0110 0101 oooo oooo xxxx xxxx */
3796		{SUI,"A,%b" }, /* 66: 0110 0110 xxxx xxxx */
3797		{NEI,"A,%b" }, /* 67: 0110 0111 xxxx xxxx */
3798		{MVI,"V,%b" }, /* 68: 0110 1000 xxxx xxxx */
3799		{MVI,"A,%b" }, /* 69: 0110 1001 xxxx xxxx */
3800		{MVI,"B,%b" }, /* 6a: 0110 1010 xxxx xxxx */
3801		{MVI,"C,%b" }, /* 6b: 0110 1011 xxxx xxxx */
3802		{MVI,"D,%b" }, /* 6c: 0110 1100 xxxx xxxx */
3803		{MVI,"E,%b" }, /* 6d: 0110 1101 xxxx xxxx */
3804		{MVI,"H,%b" }, /* 6e: 0110 1110 xxxx xxxx */
3805		{MVI,"L,%b" }, /* 6f: 0110 1111 xxxx xxxx */
3806
3807		{0,dasm70 }, /* 70: prefix */
3808		{MVIW,"%a,%b" }, /* 71: 0111 0001 oooo oooo xxxx xxxx */
3809		{SOFTI,0 }, /* 72: 0111 0010 */
3810		{illegal,0 }, /* 73: */
3811		{0,dasm74 }, /* 74: prefix */
3812		{EQIW,"%a,%b" }, /* 75: 0111 0101 oooo oooo xxxx xxxx */
3813		{SBI,"A,%b" }, /* 76: 0111 0110 xxxx xxxx */
3814		{EQI,"A,%b" }, /* 77: 0111 0111 xxxx xxxx */
3815		{CALF,"%f" }, /* 78: 0111 1ddd dddd dddd */
3816		{CALF,"%f" }, /* 79: 0111 1ddd dddd dddd */
3817		{CALF,"%f" }, /* 7a: 0111 1ddd dddd dddd */
3818		{CALF,"%f" }, /* 7b: 0111 1ddd dddd dddd */
3819		{CALF,"%f" }, /* 7c: 0111 1ddd dddd dddd */
3820		{CALF,"%f" }, /* 7d: 0111 1ddd dddd dddd */
3821		{CALF,"%f" }, /* 7e: 0111 1ddd dddd dddd */
3822		{CALF,"%f" }, /* 7f: 0111 1ddd dddd dddd */
3823
3824		{CALT,"%t" }, /* 80: 100t tttt */
3825		{CALT,"%t" }, /* 81: 100t tttt */
3826		{CALT,"%t" }, /* 82: 100t tttt */
3827		{CALT,"%t" }, /* 83: 100t tttt */
3828		{CALT,"%t" }, /* 84: 100t tttt */
3829		{CALT,"%t" }, /* 85: 100t tttt */
3830		{CALT,"%t" }, /* 86: 100t tttt */
3831		{CALT,"%t" }, /* 87: 100t tttt */
3832		{CALT,"%t" }, /* 88: 100t tttt */
3833		{CALT,"%t" }, /* 89: 100t tttt */
3834		{CALT,"%t" }, /* 8a: 100t tttt */
3835		{CALT,"%t" }, /* 8b: 100t tttt */
3836		{CALT,"%t" }, /* 8c: 100t tttt */
3837		{CALT,"%t" }, /* 8d: 100t tttt */
3838		{CALT,"%t" }, /* 8e: 100t tttt */
3839		{CALT,"%t" }, /* 8f: 100t tttt */
3840
3841		{CALT,"%t" }, /* 90: 100t tttt */
3842		{CALT,"%t" }, /* 91: 100t tttt */
3843		{CALT,"%t" }, /* 92: 100t tttt */
3844		{CALT,"%t" }, /* 93: 100t tttt */
3845		{CALT,"%t" }, /* 94: 100t tttt */
3846		{CALT,"%t" }, /* 95: 100t tttt */
3847		{CALT,"%t" }, /* 96: 100t tttt */
3848		{CALT,"%t" }, /* 97: 100t tttt */
3849		{CALT,"%t" }, /* 98: 100t tttt */
3850		{CALT,"%t" }, /* 99: 100t tttt */
3851		{CALT,"%t" }, /* 9a: 100t tttt */
3852		{CALT,"%t" }, /* 9b: 100t tttt */
3853		{CALT,"%t" }, /* 9c: 100t tttt */
3854		{CALT,"%t" }, /* 9d: 100t tttt */
3855		{CALT,"%t" }, /* 9e: 100t tttt */
3856		{CALT,"%t" }, /* 9f: 100t tttt */
3857
3858		{POP,"VA" }, /* a0: 1010 0000 */
3859		{POP,"BC" }, /* a1: 1010 0001 */
3860		{POP,"DE" }, /* a2: 1010 0010 */
3861		{POP,"HL", }, /* a3: 1010 0011 */
3862		{POP,"EA" }, /* a4: 1010 0100 */
3863		{DMOV,"EA,BC" }, /* a5: 1010 0101 */
3864		{DMOV,"EA,DE" }, /* a6: 1010 0110 */
3865		{DMOV,"EA,HL" }, /* a7: 1010 0111 */
3866		{INX,"EA" }, /* a8: 1010 1000 */
3867		{DCX,"EA" }, /* a9: 1010 1001 */
3868		{EI,0 }, /* aa: 1010 1010 */
3869		{LDAX,"(DE+%b)" }, /* ab: 1010 1011 dddd dddd */
3870		{LDAX,"(HL+A)" }, /* ac: 1010 1100 */
3871		{LDAX,"(HL+B)" }, /* ad: 1010 1101 */
3872		{LDAX,"(HL+EA)" }, /* ae: 1010 1110 */
3873		{LDAX,"(HL+%b)" }, /* af: 1010 1111 dddd dddd */
3874
3875		{PUSH,"VA" }, /* b0: 1011 0000 */
3876		{PUSH,"BC" }, /* b1: 1011 0001 */
3877		{PUSH,"DE" }, /* b2: 1011 0010 */
3878		{PUSH,"HL", }, /* b3: 1011 0011 */
3879		{PUSH,"EA" }, /* b4: 1011 0100 */
3880		{DMOV,"BC,EA" }, /* b5: 1011 0101 */
3881		{DMOV,"DE,EA" }, /* b6: 1011 0110 */
3882		{DMOV,"HL,EA" }, /* b7: 1011 0111 */
3883		{RET,0 }, /* b8: 1011 1000 */
3884		{RETS,0 }, /* b9: 1011 1001 */
3885		{DI,0 }, /* ba: 1011 1010 */
3886		{STAX,"(DE+%b)" }, /* bb: 1011 1011 dddd dddd */
3887		{STAX,"(HL+A)" }, /* bc: 1011 1100 */
3888		{STAX,"(HL+B)" }, /* bd: 1011 1101 */
3889		{STAX,"(HL+EA)" }, /* be: 1011 1110 */
3890		{STAX,"(HL+%b)" }, /* bf: 1011 1111 dddd dddd */
3891
3892		{JR,"%o" }, /* c0: 11oo oooo */
3893		{JR,"%o" }, /* c1: 11oo oooo */
3894		{JR,"%o" }, /* c2: 11oo oooo */
3895		{JR,"%o" }, /* c3: 11oo oooo */
3896		{JR,"%o" }, /* c4: 11oo oooo */
3897		{JR,"%o" }, /* c5: 11oo oooo */
3898		{JR,"%o" }, /* c6: 11oo oooo */
3899		{JR,"%o" }, /* c7: 11oo oooo */
3900		{JR,"%o" }, /* c8: 11oo oooo */
3901		{JR,"%o" }, /* c9: 11oo oooo */
3902		{JR,"%o" }, /* ca: 11oo oooo */
3903		{JR,"%o" }, /* cb: 11oo oooo */
3904		{JR,"%o" }, /* cc: 11oo oooo */
3905		{JR,"%o" }, /* cd: 11oo oooo */
3906		{JR,"%o" }, /* ce: 11oo oooo */
3907		{JR,"%o" }, /* cf: 11oo oooo */
3908
3909		{JR,"%o" }, /* d0: 11oo oooo */
3910		{JR,"%o" }, /* d1: 11oo oooo */
3911		{JR,"%o" }, /* d2: 11oo oooo */
3912		{JR,"%o" }, /* d3: 11oo oooo */
3913		{JR,"%o" }, /* d4: 11oo oooo */
3914		{JR,"%o" }, /* d5: 11oo oooo */
3915		{JR,"%o" }, /* d6: 11oo oooo */
3916		{JR,"%o" }, /* d7: 11oo oooo */
3917		{JR,"%o" }, /* d8: 11oo oooo */
3918		{JR,"%o" }, /* d9: 11oo oooo */
3919		{JR,"%o" }, /* da: 11oo oooo */
3920		{JR,"%o" }, /* db: 11oo oooo */
3921		{JR,"%o" }, /* dc: 11oo oooo */
3922		{JR,"%o" }, /* dd: 11oo oooo */
3923		{JR,"%o" }, /* de: 11oo oooo */
3924		{JR,"%o" }, /* df: 11oo oooo */
3925
3926		{JR,"%o" }, /* e0: 11oo oooo */
3927		{JR,"%o" }, /* e1: 11oo oooo */
3928		{JR,"%o" }, /* e2: 11oo oooo */
3929		{JR,"%o" }, /* e3: 11oo oooo */
3930		{JR,"%o" }, /* e4: 11oo oooo */
3931		{JR,"%o" }, /* e5: 11oo oooo */
3932		{JR,"%o" }, /* e6: 11oo oooo */
3933		{JR,"%o" }, /* e7: 11oo oooo */
3934		{JR,"%o" }, /* e8: 11oo oooo */
3935		{JR,"%o" }, /* e9: 11oo oooo */
3936		{JR,"%o" }, /* ea: 11oo oooo */
3937		{JR,"%o" }, /* eb: 11oo oooo */
3938		{JR,"%o" }, /* ec: 11oo oooo */
3939		{JR,"%o" }, /* ed: 11oo oooo */
3940		{JR,"%o" }, /* ee: 11oo oooo */
3941		{JR,"%o" }, /* ef: 11oo oooo */
3942
3943		{JR,"%o" }, /* f0: 11oo oooo */
3944		{JR,"%o" }, /* f1: 11oo oooo */
3945		{JR,"%o" }, /* f2: 11oo oooo */
3946		{JR,"%o" }, /* f3: 11oo oooo */
3947		{JR,"%o" }, /* f4: 11oo oooo */
3948		{JR,"%o" }, /* f5: 11oo oooo */
3949		{JR,"%o" }, /* f6: 11oo oooo */
3950		{JR,"%o" }, /* f7: 11oo oooo */
3951		{JR,"%o" }, /* f8: 11oo oooo */
3952		{JR,"%o" }, /* f9: 11oo oooo */
3953		{JR,"%o" }, /* fa: 11oo oooo */
3954		{JR,"%o" }, /* fb: 11oo oooo */
3955		{JR,"%o" }, /* fc: 11oo oooo */
3956		{JR,"%o" }, /* fd: 11oo oooo */
3957		{JR,"%o" }, /* fe: 11oo oooo */
3958		{JR,"%o" } /* ff: 11oo oooo */
3959		};
3960
3961		/*********************************************************
3962		*
3963		* uPD7801
3964		*
3965		*********************************************************/
3966
3967		static const struct dasm_s dasm48_7801[256] = {
3968		/* 0x00 - 0x3F */
3969		{ SKIT, "F0" }, { SKIT, "FT" }, { SKIT, "F1" }, { SKIT, "F2" },
3970		{ SKIT, "FS" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
3971		{ illegal, 0 }, { illegal, 0 }, { SK, "CY" }, { illegal, 0 },
3972		{ SK, "Z" }, { illegal, 0 }, { PUSH, "VA" }, { POP, "VA" },
3973
3974		{ SKNIT, "F0" }, { SKNIT, "FT" }, { SKNIT, "F1" }, { SKNIT, "F2" },
3975		{ SKNIT, "FS" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
3976		{ illegal, 0 }, { illegal, 0 }, { SKN, "CY" }, { illegal, 0 },
3977		{ SKN, "Z" }, { illegal, 0 }, { PUSH, "BC" }, { POP, "BC" },
3978
3979		{ EI, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
3980		{ DI, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
3981		{ illegal, 0 }, { illegal, 0 }, { CLC, 0 }, { STC, 0 },
3982		{ PER, 0 }, { PEX, 0 }, { PUSH, "DE" }, { POP, "DE" },
3983
3984		{ RLL, "A" }, { RLR, "A" }, { RLL, "C" }, { RLR, "C" },
3985		{ SLL, "A" }, { SLR, "A" }, { SLL, "C" }, { SLR, "C" },
3986		{ RLD, 0 }, { RRD, 0 }, { illegal, 0 }, { illegal, 0 },
3987		{ PER, 0 }, { illegal, 0 }, { PUSH, "HL" }, { POP, "HL" },
3988
3989		/* 0x40 - 0x7F */
3990		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
3991		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
3992		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
3993		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
3994
3995		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
3996		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
3997		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
3998		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
3999
4000		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4001		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4002		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4003		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4004
4005		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4006		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4007		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4008		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4009
4010		/* 0x80 - 0xBF */
4011		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4012		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4013		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4014		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4015
4016		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4017		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4018		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4019		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4020
4021		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4022		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4023		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4024		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4025
4026		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4027		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4028		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4029		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4030
4031		/* 0xC0 - 0xFF */
4032		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4033		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4034		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4035		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4036
4037		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4038		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4039		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4040		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4041
4042		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4043		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4044		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4045		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4046
4047		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4048		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4049		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4050		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
4051		};
4052
4053		static const struct dasm_s dasm4c_7801[256] = {
4054		/* 0x00 - 0x3F */
4055		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4056		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4057		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4058		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4059
4060		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4061		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4062		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4063		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4064
4065		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4066		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4067		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4068		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4069
4070		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4071		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4072		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4073		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4074
4075		/* 0x40 - 0x7F */
4076		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4077		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4078		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4079		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4080
4081		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4082		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4083		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4084		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4085
4086		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4087		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4088		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4089		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4090
4091		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4092		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4093		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4094		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4095
4096		/* 0x80 - 0xBF */
4097		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4098		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4099		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4100		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4101
4102		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4103		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4104		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4105		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4106
4107		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4108		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4109		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4110		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4111
4112		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4113		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4114		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4115		{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
4116
4117		/* 0xC0 - 0xFF */
4118		{ MOV, "A,PA" }, { MOV, "A,PB" }, { MOV, "A,PC" }, { MOV, "A,MK" },
4119		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4120		{ MOV, "A,S" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4121		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4122
4123		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4124		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4125		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4126		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4127
4128		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4129		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4130		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4131		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4132
4133		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4134		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4135		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4136		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
4137		};
4138
4139		static const struct dasm_s dasm4d_7801[256] = {
4140		/* 0x00 - 0x3F */
4141		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4142		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4143		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4144		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4145
4146		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4147		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4148		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4149		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4150
4151		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4152		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4153		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4154		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4155
4156		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4157		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4158		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4159		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4160
4161		/* 0x40 - 0x7F */
4162		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4163		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4164		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4165		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4166
4167		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4168		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4169		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4170		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4171
4172		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4173		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4174		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4175		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4176
4177		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4178		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4179		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4180		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4181
4182		/* 0x80 - 0xBF */
4183		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4184		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4185		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4186		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4187
4188		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4189		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4190		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4191		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4192
4193		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4194		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4195		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4196		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4197
4198		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4199		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4200		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4201		{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
4202
4203		/* 0xC0 - 0xFF */
4204		{ MOV, "PA,A" }, { MOV, "PB,A" }, { MOV, "PC,A" }, { MOV, "MK,A" },
4205		{ MOV, "MB,A" }, { MOV, "MC,A" }, { MOV, "TM0,A" }, { MOV, "TM1,A" },
4206		{ MOV, "S,A" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4207		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4208
4209		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4210		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4211		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4212		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4213
4214		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4215		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4216		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4217		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4218
4219		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4220		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4221		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4222		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
4223		};
4224
4225		static const struct dasm_s dasm60_7801[256] = {
4226		/* 0x00 - 0x3F */
4227		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4228		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4229		{ ANA, "V,A" }, { ANA, "A,A" }, { ANA, "B,A" }, { ANA, "C,A" },
4230		{ ANA, "D,A" }, { ANA, "E,A" }, { ANA, "H,A" }, { ANA, "L,A" },
4231
4232		{ XRA, "V,A" }, { XRA, "A,A" }, { XRA, "B,A" }, { XRA, "C,A" },
4233		{ XRA, "D,A" }, { XRA, "E,A" }, { XRA, "H,A" }, { XRA, "L,A" },
4234		{ ORA, "V,A" }, { ORA, "A,A" }, { ORA, "B,A" }, { ORA, "C,A" },
4235		{ ORA, "D,A" }, { ORA, "E,A" }, { ORA, "H,A" }, { ORA, "L,A" },
4236
4237		{ ADDNC, "V,A" }, { ADDNC, "A,A" }, { ADDNC, "B,A" }, { ADDNC, "C,A" },
4238		{ ADDNC, "D,A" }, { ADDNC, "E,A" }, { ADDNC, "H,A" }, { ADDNC, "L,A" },
4239		{ GTA, "V,A" }, { GTA, "A,A" }, { GTA, "B,A" }, { GTA, "C,A" },
4240		{ GTA, "D,A" }, { GTA, "E,A" }, { GTA, "H,A" }, { GTA, "L,A" },
4241
4242		{ SUBNB, "V,A" }, { SUBNB, "A,A" }, { SUBNB, "B,A" }, { SUBNB, "C,A" },
4243		{ SUBNB, "D,A" }, { SUBNB, "E,A" }, { SUBNB, "H,A" }, { SUBNB, "L,A" },
4244		{ LTA, "V,A" }, { LTA, "A,A" }, { LTA, "B,A" }, { LTA, "C,A" },
4245		{ LTA, "D,A" }, { LTA, "E,A" }, { LTA, "H,A" }, { LTA, "L,A" },
4246
4247		/* 0x40 - 0x7F */
4248		{ ADD, "V,A" }, { ADD, "A,A" }, { ADD, "B,A" }, { ADD, "C,A" },
4249		{ ADD, "D,A" }, { ADD, "E,A" }, { ADD, "H,A" }, { ADD, "L,A" },
4250		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4251		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4252
4253		{ ADC, "V,A" }, { ADC, "A,A" }, { ADC, "B,A" }, { ADC, "C,A" },
4254		{ ADC, "D,A" }, { ADC, "E,A" }, { ADC, "H,A" }, { ADC, "L,A" },
4255		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4256		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4257
4258		{ SUB, "V,A" }, { SUB, "A,A" }, { SUB, "B,A" }, { SUB, "C,A" },
4259		{ SUB, "D,A" }, { SUB, "E,A" }, { SUB, "H,A" }, { SUB, "L,A" },
4260		{ NEA, "V,A" }, { NEA, "A,A" }, { NEA, "B,A" }, { NEA, "C,A" },
4261		{ NEA, "D,A" }, { NEA, "E,A" }, { NEA, "H,A" }, { NEA, "L,A" },
4262
4263		{ SBB, "V,A" }, { SBB, "A,A" }, { SBB, "B,A" }, { SBB, "C,A" },
4264		{ SBB, "D,A" }, { SBB, "E,A" }, { SBB, "H,A" }, { SBB, "L,A" },
4265		{ EQA, "V,A" }, { EQA, "A,A" }, { EQA, "B,A" }, { EQA, "C,A" },
4266		{ EQA, "D,A" }, { EQA, "E,A" }, { EQA, "H,A" }, { EQA, "L,A" },
4267
4268		/* 0x80 - 0xBF */
4269		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4270		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4271		{ ANA, "A,V" }, { ANA, "A,A" }, { ANA, "A,B" }, { ANA, "A,C" },
4272		{ ANA, "A,D" }, { ANA, "A,E" }, { ANA, "A,H" }, { ANA, "A,L" },
4273
4274		{ XRA, "A,V" }, { XRA, "A,A" }, { XRA, "A,B" }, { XRA, "A,C" },
4275		{ XRA, "A,D" }, { XRA, "A,E" }, { XRA, "A,H" }, { XRA, "A,L" },
4276		{ ORA, "A,V" }, { ORA, "A,A" }, { ORA, "A,B" }, { ORA, "A,C" },
4277		{ ORA, "A,D" }, { ORA, "A,E" }, { ORA, "A,H" }, { ORA, "A,L" },
4278
4279		{ ADDNC, "A,V" }, { ADDNC, "A,A" }, { ADDNC, "A,B" }, { ADDNC, "A,C" },
4280		{ ADDNC, "A,D" }, { ADDNC, "A,E" }, { ADDNC, "A,H" }, { ADDNC, "A,L" },
4281		{ GTA, "A,V" }, { GTA, "A,A" }, { GTA, "A,B" }, { GTA, "A,C" },
4282		{ GTA, "A,D" }, { GTA, "A,E" }, { GTA, "A,H" }, { GTA, "A,L" },
4283
4284		{ SUBNB, "A,V" }, { SUBNB, "A,A" }, { SUBNB, "A,B" }, { SUBNB, "A,C" },
4285		{ SUBNB, "A,D" }, { SUBNB, "A,E" }, { SUBNB, "A,H" }, { SUBNB, "A,L" },
4286		{ LTA, "A,V" }, { LTA, "A,A" }, { LTA, "A,B" }, { LTA, "A,C" },
4287		{ LTA, "A,D" }, { LTA, "A,E" }, { LTA, "A,H" }, { LTA, "A,L" },
4288
4289		/* 0xC0 - 0xFF */
4290		{ ADD, "A,V" }, { ADD, "A,A" }, { ADD, "A,B" }, { ADD, "A,C" },
4291		{ ADD, "A,D" }, { ADD, "A,E" }, { ADD, "A,H" }, { ADD, "A,L" },
4292		{ ONA, "A,V" }, { ONA, "A,A" }, { ONA, "A,B" }, { ONA, "A,C" },
4293		{ ONA, "A,D" }, { ONA, "A,E" }, { ONA, "A,H" }, { ONA, "A,L" },
4294
4295		{ ADC, "A,V" }, { ADC, "A,A" }, { ADC, "A,B" }, { ADC, "A,C" },
4296		{ ADC, "A,D" }, { ADC, "A,E" }, { ADC, "A,H" }, { ADC, "A,L" },
4297		{ OFFA, "A,V" }, { OFFA, "A,A" }, { OFFA, "A,B" }, { OFFA, "A,C" },
4298		{ OFFA, "A,D" }, { OFFA, "A,E" }, { OFFA, "A,H" }, { OFFA, "A,L" },
4299
4300		{ SUB, "A,V" }, { SUB, "A,A" }, { SUB, "A,B" }, { SUB, "A,C" },
4301		{ SUB, "A,D" }, { SUB, "A,E" }, { SUB, "A,H" }, { SUB, "A,L" },
4302		{ NEA, "A,V" }, { NEA, "A,A" }, { NEA, "A,B" }, { NEA, "A,C" },
4303		{ NEA, "A,D" }, { NEA, "A,E" }, { NEA, "A,H" }, { NEA, "A,L" },
4304
4305		{ SBB, "A,V" }, { SBB, "A,A" }, { SBB, "A,B" }, { SBB, "A,C" },
4306		{ SBB, "A,D" }, { SBB, "A,E" }, { SBB, "A,H" }, { SBB, "A,L" },
4307		{ EQA, "A,V" }, { EQA, "A,A" }, { EQA, "A,B" }, { EQA, "A,C" },
4308		{ EQA, "A,D" }, { EQA, "A,E" }, { EQA, "A,H" }, { EQA, "A,L" }
4309		};
4310
4311		static const struct dasm_s dasm64_7801[256] = {
4312		/* 0x00 - 0x3F */
4313		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4314		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4315		{ ANI, "V,%b" }, { ANI, "A,%b" }, { ANI, "B,%b" }, { ANI, "C,%b" },
4316		{ ANI, "D,%b" }, { ANI, "E,%b" }, { ANI, "H,%b" }, { ANI, "L,%b" },
4317
4318		{ XRI, "V,%b" }, { XRI, "A,%b" }, { XRI, "B,%b" }, { XRI, "C,%b" },
4319		{ XRI, "D,%b" }, { XRI, "E,%b" }, { XRI, "H,%b" }, { XRI, "L,%b" },
4320		{ ORI, "V,%b" }, { ORI, "A,%b" }, { ORI, "B,%b" }, { ORI, "C,%b" },
4321		{ ORI, "D,%b" }, { ORI, "E,%b" }, { ORI, "H,%b" }, { ORI, "L,%b" },
4322
4323		{ ADINC, "V,%b" }, { ADINC, "A,%b" }, { ADINC, "B,%b" }, { ADINC, "C,%b" },
4324		{ ADINC, "D,%b" }, { ADINC, "E,%b" }, { ADINC, "H,%b" }, { ADINC, "L,%b" },
4325		{ GTI, "V,%b" }, { GTI, "A,%b" }, { GTI, "B,%b" }, { GTI, "C,%b" },
4326		{ GTI, "D,%b" }, { GTI, "E,%b" }, { GTI, "H,%b" }, { GTI, "L,%b" },
4327
4328		{ SUINB, "V,%b" }, { SUINB, "A,%b" }, { SUINB, "B,%b" }, { SUINB, "C,%b" },
4329		{ SUINB, "D,%b" }, { SUINB, "E,%b" }, { SUINB, "H,%b" }, { SUINB, "L,%b" },
4330		{ LTI, "V,%b" }, { LTI, "A,%b" }, { LTI, "B,%b" }, { LTI, "C,%b" },
4331		{ LTI, "D,%b" }, { LTI, "E,%b" }, { LTI, "H,%b" }, { LTI, "L,%b" },
4332
4333		/* 0x40 - 0x7F */
4334		{ ADI, "V,%b" }, { ADI, "A,%b" }, { ADI, "B,%b" }, { ADI, "C,%b" },
4335		{ ADI, "D,%b" }, { ADI, "E,%b" }, { ADI, "H,%b" }, { ADI, "L,%b" },
4336		{ ONI, "V,%b" }, { ONI, "A,%b" }, { ONI, "B,%b" }, { ONI, "C,%b" },
4337		{ ONI, "D,%b" }, { ONI, "E,%b" }, { ONI, "H,%b" }, { ONI, "L,%b" },
4338
4339		{ ACI, "V,%b" }, { ACI, "A,%b" }, { ACI, "B,%b" }, { ACI, "C,%b" },
4340		{ ACI, "D,%b" }, { ACI, "E,%b" }, { ACI, "H,%b" }, { ACI, "L,%b" },
4341		{ OFFI, "V,%b" }, { OFFI, "A,%b" }, { OFFI, "B,%b" }, { OFFI, "C,%b" },
4342		{ OFFI, "D,%b" }, { OFFI, "E,%b" }, { OFFI, "H,%b" }, { OFFI, "L,%b" },
4343
4344		{ SUI, "V,%b" }, { SUI, "A,%b" }, { SUI, "B,%b" }, { SUI, "C,%b" },
4345		{ SUI, "D,%b" }, { SUI, "E,%b" }, { SUI, "H,%b" }, { SUI, "L,%b" },
4346		{ NEI, "V,%b" }, { NEI, "A,%b" }, { NEI, "B,%b" }, { NEI, "C,%b" },
4347		{ NEI, "D,%b" }, { NEI, "E,%b" }, { NEI, "H,%b" }, { NEI, "L,%b" },
4348
4349		{ SBI, "V,%b" }, { SBI, "A,%b" }, { SBI, "B,%b" }, { SBI, "C,%b" },
4350		{ SBI, "D,%b" }, { SBI, "E,%b" }, { SBI, "H,%b" }, { SBI, "L,%b" },
4351		{ EQI, "V,%b" }, { EQI, "A,%b" }, { EQI, "B,%b" }, { EQI, "C,%b" },
4352		{ EQI, "D,%b" }, { EQI, "E,%b" }, { EQI, "H,%b" }, { EQI, "L,%b" },
4353
4354		/* 0x80 - 0xBF */
4355		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4356		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4357		{ ANI, "PA,%b" }, { ANI, "PB,%b" }, { ANI, "PC,%b" }, { ANI, "MK,%b" },
4358		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4359
4360		{ XRI, "PA,%b" }, { XRI, "PB,%b" }, { XRI, "PC,%b" }, { XRI, "MK,%b" },
4361		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4362		{ ORI, "PA,%b" }, { ORI, "PB,%b" }, { ORI, "PC,%b" }, { ORI, "MK,%b" },
4363		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4364
4365		{ ADINC, "PA,%b" }, { ADINC, "PB,%b" }, { ADINC, "PC,%b" }, { ADINC, "MK,%b" },
4366		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4367		{ GTI, "PA,%b" }, { GTI, "PB,%b" }, { GTI, "PC,%b" }, { GTI, "MK,%b" },
4368		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4369
4370		{ SUINB, "PA,%b" }, { SUINB, "PB,%b" }, { SUINB, "PC,%b" }, { SUINB, "MK,%b" },
4371		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4372		{ LTI, "PA,%b" }, { LTI, "PB,%b" }, { LTI, "PC,%b" }, { LTI, "MK,%b" },
4373		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4374
4375		/* 0xC0 - 0xFF */
4376		{ ADI, "PA,%b" }, { ADI, "PB,%b" }, { ADI, "PC,%b" }, { ADI, "MK,%b" },
4377		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4378		{ ONI, "PA,%b" }, { ONI, "PB,%b" }, { ONI, "PC,%b" }, { ONI, "MK,%b" },
4379		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4380
4381		{ ACI, "PA,%b" }, { ACI, "PB,%b" }, { ACI, "PC,%b" }, { ACI, "MK,%b" },
4382		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4383		{ OFFI, "PA,%b" }, { OFFI, "PB,%b" }, { OFFI, "PC,%b" }, { OFFI, "MK,%b" },
4384		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4385
4386		{ SUI, "PA,%b" }, { SUI, "PB,%b" }, { SUI, "PC,%b" }, { SUI, "MK,%b" },
4387		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4388		{ NEI, "PA,%b" }, { NEI, "PB,%b" }, { NEI, "PC,%b" }, { NEI, "MK,%b" },
4389		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4390
4391		{ SBI, "PA,%b" }, { SBI, "PB,%b" }, { SBI, "PC,%b" }, { SBI, "MK,%b" },
4392		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4393		{ EQI, "PA,%b" }, { EQI, "PB,%b" }, { EQI, "PC,%b" }, { EQI, "MK,%b" },
4394		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
4395		};
4396
4397		static const struct dasm_s dasm70_7801[256] = {
4398		/* 0x00 - 0x3F */
4399		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4400		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4401		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4402		{ illegal, 0 }, { illegal, 0 }, { SSPD, "%w" }, { LSPD, "%w" },
4403
4404		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4405		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4406		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4407		{ illegal, 0 }, { illegal, 0 }, { SBCD, "%w" }, { LBCD, "%w" },
4408
4409		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4410		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4411		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4412		{ illegal, 0 }, { illegal, 0 }, { SDED, "%w" }, { LDED, "%w" },
4413
4414		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4415		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4416		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4417		{ illegal, 0 }, { illegal, 0 }, { SHLD, "%w" }, { LHLD, "%w" },
4418
4419		/* 0x40 - 0x7F */
4420		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4421		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4422		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4423		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4424
4425		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4426		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4427		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4428		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4429
4430		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4431		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4432		{ MOV, "V,%w" }, { MOV, "A,%w" }, { MOV, "B,%w" }, { MOV, "C,%w" },
4433		{ MOV, "D,%w" }, { MOV, "E,%w" }, { MOV, "H,%w" }, { MOV, "L,%w" },
4434
4435		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4436		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4437		{ MOV, "%w,V" }, { MOV, "%w,A" }, { MOV, "%w,B" }, { MOV, "%w,C" },
4438		{ MOV, "%w,D" }, { MOV, "%w,E" }, { MOV, "%w,H" }, { MOV, "%w,L" },
4439
4440		/* 0x80 - 0xBF */
4441		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4442		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4443		{ illegal, 0 }, { ANAX, "BC" }, { ANAX, "DE" }, { ANAX, "HL" },
4444		{ ANAX, "DE+" }, { ANAX, "HL+" }, { ANAX, "DE-" }, { ANAX, "HL-" },
4445
4446		{ illegal, 0 }, { XRAX, "BC" }, { XRAX, "DE" }, { XRAX, "HL" },
4447		{ XRAX, "DE+" }, { XRAX, "HL+" }, { XRAX, "DE-" }, { XRAX, "HL-" },
4448		{ illegal, 0 }, { ORAX, "BC" }, { ORAX, "DE" }, { ORAX, "HL" },
4449		{ ORAX, "DE+" }, { ORAX, "HL+" }, { ORAX, "DE-" }, { ORAX, "HL-" },
4450
4451		{ illegal, 0 }, { ADDNCX, "BC" }, { ADDNCX, "DE" }, { ADDNCX, "HL" },
4452		{ ADDNCX, "DE+" }, { ADDNCX, "HL+" }, { ADDNCX, "DE-" }, { ADDNCX, "HL-" },
4453		{ illegal, 0 }, { GTAX, "BC" }, { GTAX, "DE" }, { GTAX, "HL" },
4454		{ GTAX, "DE+" }, { GTAX, "HL+" }, { GTAX, "DE-" }, { GTAX, "HL-" },
4455
4456		{ illegal, 0 }, { SUBNBX, "BC" }, { SUBNBX, "DE" }, { SUBNBX, "HL" },
4457		{ SUBNBX, "DE+" }, { SUBNBX, "HL+" }, { SUBNBX, }, { SUBNBX, "HL-" },
4458		{ illegal, 0 }, { LTAX, "BC" }, { LTAX, "DE" }, { LTAX, "HL" },
4459		{ LTAX, "DE+" }, { LTAX, "HL+" }, { LTAX, "DE-" }, { LTAX, "HL-" },
4460
4461		/* 0xC0 - 0xFF */
4462		{ illegal, 0 }, { ADDX, "BC" }, { ADDX, "DE" }, { ADDX, "HL" },
4463		{ ADDX, "DE+" }, { ADDX, "HL+" }, { ADDX, "DE-" }, { ADDX, "HL-" },
4464		{ illegal, 0 }, { ONAX, "BC" }, { ONAX, "DE" }, { ONAX, "HL" },
4465		{ ONAX, "DE+" }, { ONAX, "HL+" }, { ONAX, "DE-" }, { ONAX, "HL-" },
4466
4467		{ illegal, 0 }, { ADCX, "BC" }, { ADCX, "DE" }, { ADCX, "HL" },
4468		{ ADCX, "DE+" }, { ADCX, "HL+" }, { ADCX, "DE-" }, { ADCX, "HL-" },
4469		{ illegal, 0 }, { OFFAX, "BC" }, { OFFAX, "DE" }, { OFFAX, "HL" },
4470		{ OFFAX, "DE+" }, { OFFAX, "HL+" }, { OFFAX, "DE-" }, { OFFAX, "HL-" },
4471
4472		{ illegal, 0 }, { SUBX, "BC" }, { SUBX, "DE" }, { SUBX, "HL" },
4473		{ SUBX, "DE+" }, { SUBX, "HL+" }, { SUBX, "DE-" }, { SUBX, "HL-" },
4474		{ illegal, 0 }, { NEAX, "BC" }, { NEAX, "DE" }, { NEAX, "HL" },
4475		{ NEAX, "DE+" }, { NEAX, "HL+" }, { NEAX, "DE-" }, { NEAX, "HL-" },
4476
4477		{ illegal, 0 }, { SBBX, "BC" }, { SBBX, "DE" }, { SBBX, "HL" },
4478		{ SBBX, "DE+" }, { SBBX, "HL+" }, { SBBX, "DE-" }, { SBBX, "HL-" },
4479		{ illegal, 0 }, { EQAX, "BC" }, { EQAX, "DE" }, { EQAX, "HL" },
4480		{ EQAX, "DE+" }, { EQAX, "HL+" }, { EQAX, "DE-" }, { EQAX, "HL-" },
4481		};
4482
4483		static const struct dasm_s dasm74_7801[256] = {
4484		/* 0x00 - 0x3F */
4485		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4486		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4487		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4488		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4489
4490		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4491		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4492		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4493		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4494
4495		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4496		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4497		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4498		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4499
4500		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4501		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4502		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4503		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4504
4505		/* 0x40 - 0x7F */
4506		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4507		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4508		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4509		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4510
4511		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4512		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4513		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4514		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4515
4516		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4517		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4518		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4519		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4520
4521		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4522		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4523		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4524		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4525
4526		/* 0x80 - 0xBF */
4527		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4528		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4529		{ ANAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4530		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4531
4532		{ XRAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4533		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4534		{ ORAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4535		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4536
4537		{ ADDNCW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4538		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4539		{ GTAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4540		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4541
4542		{ SUBNBW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4543		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4544		{ LTAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4545		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4546
4547		/* 0xC0 - 0xFF */
4548		{ ADDW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4549		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4550		{ ONAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4551		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4552
4553		{ ADCW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4554		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4555		{ OFFAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4556		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4557
4558		{ SUBW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4559		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4560		{ NEAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4561		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4562
4563		{ SBBW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4564		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4565		{ EQAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4566		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
4567		};
4568
4569		static const struct dasm_s dasmXX_7801[256] = {
4570		/* 0x00 - 0x3F */
4571		{ NOP, 0 }, { HALT, 0 }, { INX, "SP" }, { DCX, "SP" },
4572		{ LXI, "SP,%w" }, { ANIW, "%a,%b" }, { illegal, 0 }, { ANI, "A,%b" },
4573		{ RET, 0 }, { SIO, 0 }, { MOV, "A,B" }, { MOV, "A,C" },
4574		{ MOV, "A,D" }, { MOV, "A,E" }, { MOV, "A,H" }, { MOV, "A,L" },
4575
4576		{ EX, 0 }, { EXX, 0 }, { INX, "BC" }, { DCX, "BC" },
4577		{ LXI, "BC,%w" }, { ORIW, "%a,%b" }, { XRI, "A,%b" }, { ORI, "A,%b" },
4578		{ RETS, 0 }, { STM, 0 }, { MOV, "B,A" }, { MOV, "C,A" },
4579		{ MOV, "D,A" }, { MOV, "E,A" }, { MOV, "H,A" }, { MOV, "L,A" },
4580
4581		{ INRW, "%a" }, { TABLE, 0 }, { INX, "DE" }, { DCX, "DE" },
4582		{ LXI, "DE,%w" }, { GTIW, "%a,%b" }, { ADINC, "A,%b" }, { GTI, "A,%b" },
4583		{ LDAW, "%a" }, { LDAX, "BC" }, { LDAX, "DE" }, { LDAX, "HL" },
4584		{ LDAX, "DE+" }, { LDAX, "HL+" }, { LDAX, "DE-" }, { LDAX, "HL-" },
4585
4586		{ DCRW, "%a" }, { BLOCK, 0 }, { INX, "HL" }, { DCX, "HL" },
4587		{ LXI, "HL,%w" }, { LTIW, "%a,%b" }, { SUINB, "A,%b" }, { LTI, "A,%b" },
4588		{ STAW, "%a" }, { STAX, "BC" }, { STAX, "DE" }, { STAX, "HL" },
4589		{ STAX, "DE+" }, { STAX, "HL+" }, { STAX, "DE-" }, { STAX, "HL-" },
4590
4591		/* 0x40 - 0x7F */
4592		{ illegal, 0 }, { INR, "A" }, { INR, "B" }, { INR, "C" },
4593		{ CALL, "%w" }, { ONIW, "%a,%b" }, { ADI, "A,%b" }, { ONI, "A,%b" },
4594		{ 0, dasm48_7801 }, { MVIX, "BC,%b" }, { MVIX, "DE,%b" }, { MVIX, "HL,%b" },
4595		{ 0, dasm4c_7801 }, { 0, dasm4d_7801 }, { JRE, "%d" }, { JRE, "%d" },
4596
4597		{ illegal, 0 }, { DCR, "A" }, { DCR, "B" }, { DCR, "C" },
4598		{ JMP, "%w" }, { OFFIW, "%a,%b" }, { ACI, "A,%b" }, { OFFI, "A,%b" },
4599		{ BIT, "0,%a" }, { BIT, "1,%a" }, { BIT," 2,%a" }, { BIT, "3,%a" },
4600		{ BIT, "4,%a" }, { BIT, "5,%a" }, { BIT, "6,%a" }, { BIT, "7,%a" },
4601
4602		{ 0, dasm60_7801 }, { DAA, 0 }, { RETI, 0 }, { CALB, 0 },
4603		{ 0, dasm64_7801 }, { NEIW, "%a,%b" }, { SUI, "A,%b" }, { NEI, "A,%b" },
4604		{ MVI, "V,%b" }, { MVI, "A,%b" }, { MVI, "B,%b" }, { MVI, "C,%b" },
4605		{ MVI, "D,%b" }, { MVI, "E,%b" }, { MVI, "H,%b" }, { MVI, "L,%b" },
4606
4607		{ 0, dasm70_7801 }, { MVIW, "%a,%b" }, { SOFTI, 0 }, { JB, 0 },
4608		{ 0, dasm74_7801 }, { EQIW, "%a,%b" }, { SBI, "A,%b" }, { EQI, "A,%b" },
4609		{ CALF, "%f" }, { CALF, "%f" }, { CALF, "%f" }, { CALF, "%f" },
4610		{ CALF, "%f" }, { CALF, "%f" }, { CALF, "%f" }, { CALF, "%f" },
4611
4612		/* 0x80 - 0xBF */
4613		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
4614		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
4615		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
4616		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
4617
4618		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
4619		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
4620		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
4621		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
4622
4623		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
4624		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
4625		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
4626		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
4627
4628		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
4629		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
4630		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
4631		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
4632
4633		/* 0xC0 - 0xFF */
4634		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
4635		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
4636		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
4637		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
4638
4639		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
4640		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
4641		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
4642		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
4643
4644		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
4645		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
4646		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
4647		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
4648
4649		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
4650		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
4651		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
4652		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" }
4653		};
4654
4655		/*********************************************************
4656		*
4657		* uPD7801
4658		*
4659		*********************************************************/
4660
4661		static const struct dasm_s dasm48_78c05[256] = {
4662		/* 0x00 - 0x3F */
4663		{ SKIT, "F0" }, { SKIT, "FT" }, { SKIT, "F1" }, { illegal, 0 }, /* TODO: PDF doesn't mention SKIT and SK */
4664		{ SKIT, "FS" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4665		{ illegal, 0 }, { illegal, 0 }, { SK, "CY" }, { illegal, 0 },
4666		{ SK, "Z" }, { illegal, 0 }, { PUSH, "VA" }, { POP, "VA" },
4667
4668		{ SKNIT, "F0" }, { SKNIT, "FT" }, { SKNIT, "F1" }, { illegal, 0 },
4669		{ SKNIT, "FS" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4670		{ illegal, 0 }, { illegal, 0 }, { SKN, "CY" }, { illegal, 0 },
4671		{ SKN, "Z" }, { illegal, 0 }, { PUSH, "BC" }, { POP, "BC" },
4672
4673		{ EI, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4674		{ DI, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4675		{ illegal, 0 }, { illegal, 0 }, { CLC, 0 }, { STC, 0 },
4676		{ illegal, 0 }, { PEX, 0 }, { PUSH, "DE" }, { POP, "DE" },
4677
4678		{ RLL, "A" }, { RLR, "A" }, { illegal, 0 }, { illegal, 0 },
4679		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4680		{ RLD, 0 }, { RRD, 0 }, { illegal, 0 }, { illegal, 0 },
4681		{ PER, 0 }, { illegal, 0 }, { PUSH, "HL" }, { POP, "HL" },
4682
4683		/* 0x40 - 0x7F */
4684		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4685		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4686		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4687		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4688
4689		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4690		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4691		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4692		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4693
4694		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4695		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4696		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4697		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4698
4699		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4700		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4701		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4702		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4703
4704		/* 0x80 - 0xBF */
4705		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4706		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4707		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4708		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4709
4710		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4711		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4712		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4713		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4714
4715		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4716		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4717		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4718		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4719
4720		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4721		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4722		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4723		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4724
4725		/* 0xC0 - 0xFF */
4726		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4727		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4728		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4729		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4730
4731		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4732		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4733		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4734		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4735
4736		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4737		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4738		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4739		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4740
4741		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4742		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4743		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4744		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
4745		};
4746
4747		static const struct dasm_s dasm4c_78c05[256] = {
4748		/* 0x00 - 0x3F */
4749		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4750		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4751		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4752		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4753
4754		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4755		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4756		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4757		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4758
4759		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4760		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4761		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4762		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4763
4764		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4765		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4766		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4767		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4768
4769		/* 0x40 - 0x7F */
4770		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4771		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4772		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4773		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4774
4775		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4776		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4777		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4778		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4779
4780		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4781		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4782		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4783		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4784
4785		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4786		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4787		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4788		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4789
4790		/* 0x80 - 0xBF */
4791		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4792		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4793		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4794		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4795
4796		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4797		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4798		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4799		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4800
4801		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4802		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4803		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4804		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4805
4806		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4807		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4808		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4809		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4810
4811		/* 0xC0 - 0xFF */
4812		{ MOV, "A,PA" }, { MOV, "A,PB" }, { MOV, "A,PC" }, { MOV, "A,MK" },
4813		{ MOV, "A,MB" }, { MOV, "A,MC" }, { MOV, "A,TM0" }, { MOV, "A,TM1" },
4814		{ MOV, "A,S" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }, /* TODO: Figure out what regsiter C9 indicates */
4815		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4816
4817		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4818		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4819		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4820		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4821
4822		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4823		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4824		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4825		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4826
4827		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4828		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4829		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4830		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
4831		};
4832
4833		static const struct dasm_s dasm4d_78c05[256] = {
4834		/* 0x00 - 0x3F */
4835		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4836		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4837		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4838		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4839
4840		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4841		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4842		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4843		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4844
4845		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4846		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4847		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4848		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4849
4850		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4851		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4852		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4853		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4854
4855		/* 0x40 - 0x7F */
4856		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4857		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4858		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4859		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4860
4861		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4862		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4863		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4864		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4865
4866		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4867		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4868		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4869		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4870
4871		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4872		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4873		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4874		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4875
4876		/* 0x80 - 0xBF */
4877		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4878		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4879		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4880		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4881
4882		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4883		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4884		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4885		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4886
4887		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4888		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4889		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4890		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4891
4892		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4893		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4894		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4895		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4896
4897		/* 0xC0 - 0xFF */
4898		{ MOV, "PA,A" }, { MOV, "PB,A" }, { MOV, "PC,A" }, { MOV, "MK,A" },
4899		{ MOV, "MB,A" }, { MOV, "MC,A" }, { MOV, "TM0,A" }, { MOV, "TM1,A" },
4900		{ MOV, "S,A" }, { MOV, "TMM,A" }, { illegal, 0 }, { illegal, 0 },
4901		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4902
4903		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4904		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4905		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4906		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4907
4908		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4909		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4910		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4911		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4912
4913		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4914		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4915		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4916		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
4917		};
4918
4919		static const struct dasm_s dasm60_78c05[256] = {
4920		/* 0x00 - 0x3F */
4921		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4922		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4923		{ illegal, 0 }, { ANA, "A,A" }, { illegal, 0 }, { illegal, 0 },
4924		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4925
4926		{ illegal, 0 }, { XRA, "A,A" }, { illegal, 0 }, { illegal, 0 },
4927		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4928		{ illegal, 0 }, { ORA, "A,A" }, { illegal, 0 }, { illegal, 0 },
4929		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4930
4931		{ illegal, 0 }, { ADDNC, "A,A" }, { illegal, 0 }, { illegal, 0 },
4932		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4933		{ illegal, 0 }, { GTA, "A,A" }, { illegal, 0 }, { illegal, 0 },
4934		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4935
4936		{ illegal, 0 }, { SUBNB, "A,A" }, { illegal, 0 }, { illegal, 0 },
4937		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4938		{ illegal, 0 }, { LTA, "A,A" }, { illegal, 0 }, { illegal, 0 },
4939		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4940
4941		/* 0x40 - 0x7F */
4942		{ illegal, 0 }, { ADD, "A,A" }, { illegal, 0 }, { illegal, 0 },
4943		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4944		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4945		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4946
4947		{ illegal, 0 }, { ADC, "A,A" }, { illegal, 0 }, { illegal, 0 },
4948		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4949		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4950		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4951
4952		{ illegal, 0 }, { SUB, "A,A" }, { illegal, 0 }, { illegal, 0 },
4953		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4954		{ illegal, 0 }, { NEA, "A,A" }, { illegal, 0 }, { illegal, 0 },
4955		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4956
4957		{ illegal, 0 }, { SBB, "A,A" }, { illegal, 0 }, { illegal, 0 },
4958		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4959		{ illegal, 0 }, { EQA, "A,A" }, { illegal, 0 }, { illegal, 0 },
4960		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4961
4962		/* 0x80 - 0xBF */
4963		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4964		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
4965		{ illegal, 0 }, { ANA, "A,A" }, { ANA, "A,B" }, { ANA, "A,C" },
4966		{ ANA, "A,D" }, { ANA, "A,E" }, { ANA, "A,H" }, { ANA, "A,L" },
4967
4968		{ illegal, 0 }, { XRA, "A,A" }, { XRA, "A,B" }, { XRA, "A,C" },
4969		{ XRA, "A,D" }, { XRA, "A,E" }, { XRA, "A,H" }, { XRA, "A,L" },
4970		{ illegal, 0 }, { ORA, "A,A" }, { ORA, "A,B" }, { ORA, "A,C" },
4971		{ ORA, "A,D" }, { ORA, "A,E" }, { ORA, "A,H" }, { ORA, "A,L" },
4972
4973		{ illegal, 0 }, { ADDNC, "A,A" }, { ADDNC, "A,B" }, { ADDNC, "A,C" },
4974		{ ADDNC, "A,D" }, { ADDNC, "A,E" }, { ADDNC, "A,H" }, { ADDNC, "A,L" },
4975		{ illegal, 0 }, { GTA, "A,A" }, { GTA, "A,B" }, { GTA, "A,C" },
4976		{ GTA, "A,D" }, { GTA, "A,E" }, { GTA, "A,H" }, { GTA, "A,L" },
4977
4978		{ illegal, 0 }, { SUBNB, "A,A" }, { SUBNB, "A,B" }, { SUBNB, "A,C" },
4979		{ SUBNB, "A,D" }, { SUBNB, "A,E" }, { SUBNB, "A,H" }, { SUBNB, "A,L" },
4980		{ illegal, 0 }, { LTA, "A,A" }, { LTA, "A,B" }, { LTA, "A,C" },
4981		{ LTA, "A,D" }, { LTA, "A,E" }, { LTA, "A,H" }, { LTA, "A,L" },
4982
4983		/* 0xC0 - 0xFF */
4984		{ illegal, 0 }, { ADD, "A,A" }, { ADD, "A,B" }, { ADD, "A,C" },
4985		{ ADD, "A,D" }, { ADD, "A,E" }, { ADD, "A,H" }, { ADD, "A,L" },
4986		{ illegal, 0 }, { ONA, "A,A" }, { ONA, "A,B" }, { ONA, "A,C" },
4987		{ ONA, "A,D" }, { ONA, "A,E" }, { ONA, "A,H" }, { ONA, "A,L" },
4988
4989		{ illegal, 0 }, { ADC, "A,A" }, { ADC, "A,B" }, { ADC, "A,C" },
4990		{ ADC, "A,D" }, { ADC, "A,E" }, { ADC, "A,H" }, { ADC, "A,L" },
4991		{ illegal, 0 }, { OFFA, "A,A" }, { OFFA, "A,B" }, { OFFA, "A,C" },
4992		{ OFFA, "A,D" }, { OFFA, "A,E" }, { OFFA, "A,H" }, { OFFA, "A,L" },
4993
4994		{ illegal, 0 }, { SUB, "A,A" }, { SUB, "A,B" }, { SUB, "A,C" },
4995		{ SUB, "A,D" }, { SUB, "A,E" }, { SUB, "A,H" }, { SUB, "A,L" },
4996		{ illegal, 0 }, { NEA, "A,A" }, { NEA, "A,B" }, { NEA, "A,C" },
4997		{ NEA, "A,D" }, { NEA, "A,E" }, { NEA, "A,H" }, { NEA, "A,L" },
4998
4999		{ illegal, 0 }, { SBB, "A,A" }, { SBB, "A,B" }, { SBB, "A,C" },
5000		{ SBB, "A,D" }, { SBB, "A,E" }, { SBB, "A,H" }, { SBB, "A,L" },
5001		{ illegal, 0 }, { EQA, "A,A" }, { EQA, "A,B" }, { EQA, "A,C" },
5002		{ EQA, "A,D" }, { EQA, "A,E" }, { EQA, "A,H" }, { EQA, "A,L" }
5003		};
5004
5005		static const struct dasm_s dasm64_78c05[256] = {
5006		/* 0x00 - 0x3F */
5007		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5008		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5009		{ illegal, 0 }, { ANI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
5010		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5011
5012		{ illegal, 0 }, { XRI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
5013		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5014		{ illegal, 0 }, { ORI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
5015		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5016
5017		{ illegal, 0 }, { ADINC, "A,%b" }, { illegal, 0 }, { illegal, 0 },
5018		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5019		{ illegal, 0 }, { GTI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
5020		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5021
5022		{ illegal, 0 }, { SUINB, "A,%b" }, { illegal, 0 }, { illegal, 0 },
5023		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5024		{ illegal, 0 }, { LTI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
5025		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5026
5027		/* 0x40 - 0x7F */
5028		{ illegal, 0 }, { ADI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
5029		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5030		{ illegal, 0 }, { ONI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
5031		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5032
5033		{ illegal, 0 }, { ACI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
5034		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5035		{ illegal, 0 }, { OFFI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
5036		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5037
5038		{ illegal, 0 }, { SUI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
5039		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5040		{ illegal, 0 }, { NEI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
5041		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5042
5043		{ illegal, 0 }, { SBI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
5044		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5045		{ illegal, 0 }, { EQI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
5046		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5047
5048		/* 0x80 - 0xBF */
5049		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5050		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5051		{ ANI, "PA,%b" }, { ANI, "PB,%b" }, { ANI, "PC,%b" }, { ANI, "MK,%b" },
5052		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5053
5054		{ XRI, "PA,%b" }, { XRI, "PB,%b" }, { XRI, "PC,%b" }, { XRI, "MK,%b" },
5055		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5056		{ ORI, "PA,%b" }, { ORI, "PB,%b" }, { ORI, "PC,%b" }, { ORI, "MK,%b" },
5057		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5058
5059		{ ADINC, "PA,%b" }, { ADINC, "PB,%b" }, { ADINC, "PC,%b" }, { ADINC, "MK,%b" },
5060		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5061		{ GTI, "PA,%b" }, { GTI, "PB,%b" }, { GTI, "PC,%b" }, { GTI, "MK,%b" },
5062		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5063
5064		{ SUINB, "PA,%b" }, { SUINB, "PB,%b" }, { SUINB, "PC,%b" }, { SUINB, "MK,%b" },
5065		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5066		{ LTI, "PA,%b" }, { LTI, "PB,%b" }, { LTI, "PC,%b" }, { LTI, "MK,%b" },
5067		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5068
5069		/* 0xC0 - 0xFF */
5070		{ ADI, "PA,%b" }, { ADI, "PB,%b" }, { ADI, "PC,%b" }, { ADI, "MK,%b" },
5071		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5072		{ ONI, "PA,%b" }, { ONI, "PB,%b" }, { ONI, "PC,%b" }, { ONI, "MK,%b" },
5073		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5074
5075		{ ACI, "PA,%b" }, { ACI, "PB,%b" }, { ACI, "PC,%b" }, { ACI, "MK,%b" },
5076		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5077		{ SUI, "PA,%b" }, { SUI, "PB,%b" }, { SUI, "PC,%b" }, { SUI, "MK,%b" },
5078		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5079
5080		{ NEI, "PA,%b" }, { NEI, "PB,%b" }, { NEI, "PC,%b" }, { NEI, "MK,%b" },
5081		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5082		{ SBI, "PA,%b" }, { SBI, "PB,%b" }, { SBI, "PC,%b" }, { SBI, "MK,%b" },
5083		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5084
5085		{ SBI, "PA,%b" }, { SBI, "PB,%b" }, { SBI, "PC,%b" }, { SBI, "MK,%b" },
5086		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5087		{ EQI, "PA,%b" }, { EQI, "PB,%b" }, { EQI, "PC,%b" }, { EQI, "MK,%b" },
5088		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
5089		};
5090
5091		static const struct dasm_s dasm70_78c05[256] = {
5092		/* 0x00 - 0x3F */
5093		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5094		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5095		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5096		{ illegal, 0 }, { illegal, 0 }, { SSPD, "%w" }, { LSPD, "%w" },
5097
5098		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5099		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5100		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5101		{ illegal, 0 }, { illegal, 0 }, { SBCD, "%w" }, { LBCD, "%w" },
5102
5103		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5104		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5105		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5106		{ illegal, 0 }, { illegal, 0 }, { SDED, "%w" }, { LDED, "%w" },
5107
5108		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5109		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5110		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5111		{ illegal, 0 }, { illegal, 0 }, { SHLD, "%w" }, { LHLD, "%w" },
5112
5113		/* 0x40 - 0x7F */
5114		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5115		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5116		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5117		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5118
5119		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5120		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5121		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5122		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5123
5124		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5125		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5126		{ illegal, 0 }, { MOV, "A,%w" }, { MOV, "B,%w" }, { MOV, "C,%w" },
5127		{ MOV, "D,%w" }, { MOV, "E,%w" }, { MOV, "H,%w" }, { MOV, "L,%w" },
5128
5129		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5130		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5131		{ illegal, 0 }, { MOV, "%w,A" }, { MOV, "%w,B" }, { MOV, "%w,C" },
5132		{ MOV, "%w,D" }, { MOV, "%w,E" }, { MOV, "%w,H" }, { MOV, "%w,L" },
5133
5134		/* 0x80 - 0xBF */
5135		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5136		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5137		{ illegal, 0 }, { ANAX, "BC" }, { ANAX, "DE" }, { ANAX, "HL" },
5138		{ ANAX, "DE+" }, { ANAX, "HL+" }, { ANAX, "DE-" }, { ANAX, "HL-" },
5139
5140		{ illegal, 0 }, { XRAX, "BC" }, { XRAX, "DE" }, { XRAX, "HL" },
5141		{ XRAX, "DE+" }, { XRAX, "HL+" }, { XRAX, "DE-" }, { XRAX, "HL-" },
5142		{ illegal, 0 }, { ORAX, "BC" }, { ORAX, "DE" }, { ORAX, "HL" },
5143		{ ORAX, "DE+" }, { ORAX, "HL+" }, { ORAX, "DE-" }, { ORAX, "HL-" },
5144
5145		{ illegal, 0 }, { ADDNCX, "BC" }, { ADDNCX, "DE" }, { ADDNCX, "HL" },
5146		{ ADDNCX, "DE+" }, { ADDNCX, "HL+" }, { ADDNCX, "DE-" }, { ADDNCX, "HL-" },
5147		{ illegal, 0 }, { GTAX, "BC" }, { GTAX, "DE" }, { GTAX, "HL" },
5148		{ GTAX, "DE+" }, { GTAX, "HL+" }, { GTAX, "DE-" }, { GTAX, "HL-" },
5149
5150		{ illegal, 0 }, { SUBNBX, "BC" }, { SUBNBX, "DE" }, { SUBNBX, "HL" },
5151		{ SUBNBX, "DE+" }, { SUBNBX, "HL+" }, { SUBNBX, "DE-" }, { SUBNBX, "HL-" },
5152		{ illegal, 0 }, { LTAX, "BC" }, { LTAX, "DE" }, { LTAX, "HL" },
5153		{ LTAX, "DE+" }, { LTAX, "HL+" }, { LTAX, "DE-" }, { LTAX, "HL-" },
5154
5155		/* 0xC0 - 0xFF */
5156		{ illegal, 0 }, { ADDX, "BC" }, { ADDX, "DE" }, { ADDX, "HL" },
5157		{ ADDX, "DE+" }, { ADDX, "HL+" }, { ADDX, "DE-" }, { ADDX, "HL-" },
5158		{ illegal, 0 }, { ONAX, "BC" }, { ONAX, "DE" }, { ONAX, "HL" },
5159		{ ONAX, "DE+" }, { ONAX, "HL+" }, { ONAX, "DE-" }, { ONAX, "HL-" },
5160
5161		{ illegal, 0 }, { ADCX, "BC" }, { ADCX, "DE" }, { ADCX, "HL" },
5162		{ ADCX, "DE+" }, { ADCX, "HL+" }, { ADCX, "DE-" }, { ADCX, "HL-" },
5163		{ illegal, 0 }, { OFFAX, "BC" }, { OFFAX, "DE" }, { OFFAX, "HL" },
5164		{ OFFAX, "DE+" }, { OFFAX, "HL+" }, { OFFAX, "DE-" }, { OFFAX, "HL-" },
5165
5166		{ illegal, 0 }, { SUBX, "BC" }, { SUBX, "DE" }, { SUBX, "HL" },
5167		{ SUBX, "DE+" }, { SUBX, "HL+" }, { SUBX, "DE-" }, { SUBX, "HL-" },
5168		{ illegal, 0 }, { NEAX, "BC" }, { NEAX, "DE" }, { NEAX, "HL" },
5169		{ NEAX, "DE+" }, { NEAX, "HL+" }, { NEAX, "DE-" }, { NEAX, "HL-" },
5170
5171		{ illegal, 0 }, { SBBX, "BC" }, { SBBX, "DE" }, { SBBX, "HL" },
5172		{ SBBX, "DE+" }, { SBBX, "HL+" }, { SBBX, "DE-" }, { SBBX, "HL-" },
5173		{ illegal, 0 }, { EQAX, "BC" }, { EQAX, "DE" }, { EQAX, "HL" },
5174		{ EQAX, "DE+" }, { EQAX, "HL+" }, { EQAX, "DE-" }, { EQAX, "HL-" },
5175		};
5176
5177		static const struct dasm_s dasm74_78c05[256] = {
5178		/* 0x00 - 0x3F */
5179		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5180		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5181		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5182		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5183
5184		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5185		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5186		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5187		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5188
5189		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5190		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5191		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5192		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5193
5194		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5195		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5196		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5197		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5198
5199		/* 0x40 - 0x7F */
5200		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5201		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5202		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5203		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5204
5205		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5206		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5207		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5208		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5209
5210		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5211		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5212		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5213		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5214
5215		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5216		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5217		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5218		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5219
5220		/* 0x80 - 0xBF */
5221		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5222		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5223		{ ANAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5224		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5225
5226		{ XRAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5227		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5228		{ ORAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5229		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5230
5231		{ ADDNCW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5232		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5233		{ GTAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5234		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5235
5236		{ SUBNBW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5237		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5238		{ LTAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5239		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5240
5241		/* 0xC0 - 0xFF */
5242		{ ADDW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5243		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5244		{ ONAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5245		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5246
5247		{ ADCW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5248		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5249		{ OFFAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5250		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5251
5252		{ SUBW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5253		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5254		{ NEAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5255		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5256
5257		{ SBBW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5258		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5259		{ EQAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5260		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5261		};
5262
5263		static const struct dasm_s dasmXX_78c05[256] = {
5264		/* 0x00 - 0x3F */
5265		{ NOP, 0 }, { HALT, 0 }, { INX, "SP" }, { DCX, "SP" },
5266		{ LXI, "SP,%w" }, { ANIW, "%a,%b" }, { illegal, 0 }, { ANI, "A,%b" },
5267		{ RET, 0 }, { SIO, 0 }, { MOV, "A,B" }, { MOV, "A,C" },
5268		{ MOV, "A,D" }, { MOV, "A,E" }, { MOV, "A,H" }, { MOV, "A,L" },
5269
5270		{ illegal, 0 }, { illegal, 0 }, { INX, "BC" }, { DCX, "BC" },
5271		{ LXI, "BC,%w" }, { ORIW, "%a,%b" }, { XRI, "A,%b" }, { ORI, "A,%b" },
5272		{ RETS, 0 }, { STM, 0 }, { MOV, "B,A" }, { MOV, "C,A" },
5273		{ MOV, "D,A" }, { MOV, "E,A" }, { MOV, "H,A" }, { MOV, "L,A" },
5274
5275		{ INRW, "%a" }, { illegal, 0 }, { INX, "DE" }, { DCX, "DE" },
5276		{ LXI, "DE,%w" }, { GTIW, "%a,%b" }, { ADINC, "A,%b" }, { GTI, "A,%b" },
5277		{ LDAW, "%a" }, { LDAX, "BC" }, { LDAX, "DE" }, { LDAX, "HL" },
5278		{ LDAX, "DE+" }, { LDAX, "HL+" }, { LDAX, "DE-" }, { LDAX, "HL-" },
5279
5280		{ DCRW, "%a" }, { illegal, 0 }, { INX, "HL" }, { DCX, "HL" },
5281		{ LXI, "HL,%w" }, { LTIW, "%a,%b" }, { SUINB, "A,%b" }, { LTI, "A,%b" },
5282		{ STAW, "%a" }, { STAX, "BC" }, { STAX, "DE" }, { STAX, "HL" },
5283		{ STAX, "DE+" }, { STAX, "HL+" }, { STAX, "DE-" }, { STAX, "HL-" },
5284
5285		/* 0x40 - 0x7F */
5286		{ illegal, 0 }, { INR, "A" }, { INR, "B" }, { INR, "C" },
5287		{ CALL, "%w" }, { ONIW, "%a,%b" }, { ADI, "A,%b" }, { ONI, "A,%b" },
5288		{ 0, dasm48_78c05 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5289		{ 0, dasm4c_78c05 }, { 0, dasm4d_78c05 }, { JRE, "%d" }, { JRE, "%d" },
5290
5291		{ illegal, 0 }, { DCR, "A" }, { DCR, "B" }, { DCR, "C" },
5292		{ JMP, "%w" }, { OFFIW, "%a,%b" }, { ACI, "A,%b" }, { OFFI, "A,%b" },
5293		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5294		{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
5295
5296		{ 0, dasm60_78c05 }, { DAA, 0 }, { RETI, 0 }, { CALB, 0 },
5297		{ 0, dasm64_78c05 }, { NEIW, "%a,%b" }, { SUI, "A,%b" }, { NEI, "A,%b" },
5298		{ illegal, 0 }, { MVI, "A,%b" }, { MVI, "B,%b" }, { MVI, "C,%b" },
5299		{ MVI, "D,%b" }, { MVI, "E,%b" }, { MVI, "H,%b" }, { MVI, "L,%b" },
5300
5301		{ 0, dasm70_78c05 }, { MVIW, "%a,%b" }, { SOFTI, 0 }, { JB, 0 },
5302		{ 0, dasm74_78c05 }, { EQIW, "%a,%b" }, { SBI, "A,%b" }, { EQI, "A,%b" },
5303		{ CALF, "%f" }, { CALF, "%f" }, { CALF, "%f" }, { CALF, "%f" },
5304		{ CALF, "%f" }, { CALF, "%f" }, { CALF, "%f" }, { CALF, "%f" },
5305
5306		/* 0x80 - 0xBF */
5307		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
5308		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
5309		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
5310		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
5311
5312		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
5313		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
5314		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
5315		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
5316
5317		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
5318		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
5319		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
5320		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
5321
5322		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
5323		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
5324		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
5325		{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
5326
5327		/* 0xC0 - 0xFF */
5328		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
5329		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
5330		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
5331		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
5332
5333		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
5334		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
5335		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
5336		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
5337
5338		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
5339		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
5340		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
5341		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
5342
5343		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
5344		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
5345		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
5346		{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" }
5347		};
5348
5349
5350		/* register names for bit manipulation instructions */
5351		static const char *const regname[32] =
5352		{
5353		"illegal", "illegal", "illegal", "illegal",
5354		"illegal", "illegal", "illegal", "illegal",
5355		"illegal", "illegal", "illegal", "illegal",
5356		"illegal", "illegal", "illegal", "illegal",
5357		"PA", "PB", "PC", "PD",
5358		"illegal", "PF", "MKH", "MKL",
5359		"illegal", "SMH", "illegal", "EOM",
5360		"illegal", "TMM", "PT", "illegal"
5361		};
5362
5363		static offs_t Dasm( char buffer, offs_t pc, const struct dasm_s dasmXX, const UINT8 oprom, const UINT8 opram, int is_7810 )
5364		{
5365		int idx = 0;
5366		UINT8 op = oprom[idx++], op2, t;
5367		int offset;
5368		UINT16 ea;
5369		const char *a;
5370		UINT32 flags = 0;
5371
5372		t = dasmXX[op].token;
5373		a = (const char *)dasmXX[op].args;
5374
5375		/* 0 token means prefix opcode (use table from args) */
5376		if (0 == t)
5377		{
5378		struct dasm_s p_dasm = (struct dasm_s )a;
5379
5380		op2 = oprom[idx++];
5381		t = p_dasm[op2].token;
5382		a = (const char *)p_dasm[op2].args;
5383		}
5384
5385		buffer += sprintf(buffer, "%-8.8s", token[t]);
5386
5387		if (t == CALB \|\| t == CALF \|\| t == CALL \|\| t == CALT)
5388		flags = DASMFLAG_STEP_OVER;
5389		else if (t == RET \|\| t == RETI)
5390		flags = DASMFLAG_STEP_OUT;
5391
5392		while (a && *a)
5393		{
5394		if ('%' == *a)
5395		{
5396		a++;
5397		switch (*a)
5398		{
5399		case 'a': /* address V * 256 + offset */
5400		op2 = opram[idx++];
5401		buffer += sprintf(buffer, "VV:%02X", op2);
5402		break;
5403		case 'b': /* immediate byte */
5404		buffer += sprintf(buffer, "$%02X", opram[idx++]);
5405		break;
5406		case 'w': /* immediate word */
5407		ea = opram[idx++];
5408		ea += opram[idx++] << 8;
5409		buffer += sprintf(buffer, "$%04X", ea);
5410		break;
5411		case 'd': /* JRE address */
5412		op2 = oprom[idx++];
5413		offset = (op & 1) ? -(256 - op2): + op2;
5414		buffer += sprintf(buffer, "$%04X", ( pc + idx + offset ) & 0xFFFF );
5415		break;
5416		case 't': /* CALT address */
5417		ea = 0x80 + 2 * (op & (is_7810 ? 0x1f : 0x3f));
5418		buffer += sprintf(buffer, "($%04X)", ea);
5419		break;
5420		case 'f': /* CALF address */
5421		op2 = oprom[idx++];
5422		ea = 0x800 + 0x100 * (op & 0x07) + op2;
5423		buffer += sprintf(buffer, "$%04X", ea);
5424		break;
5425		case 'o': /* JR offset */
5426		offset = ( ( op & 0x20 ) ? -0x20 : 0 ) + ( op & 0x1F );
5427		buffer += sprintf(buffer, "$%04X", ( pc + idx + offset ) & 0xFFFF );
5428		break;
5429		case 'i': /* bit manipulation */
5430		op2 = oprom[idx++];
5431		buffer += sprintf(buffer, "%s,%d", regname[op2 & 0x1f], op2 >> 5);
5432		break;
5433		default:
5434		buffer++ = a;
5435		}
5436		}
5437		else
5438		buffer++ = a;
5439		a++;
5440		}
5441		*buffer = '\0';
5442
5443		return idx \| flags \| DASMFLAG_SUPPORTED;
5444		}
5445
5446		CPU_DISASSEMBLE( upd7810 )
5447		{
5448		return Dasm( buffer, pc, dasmXX_7810, oprom, opram, 1 );
5449		}
5450
5451		CPU_DISASSEMBLE( upd7807 )
5452		{
5453		return Dasm( buffer, pc, dasmXX_7807, oprom, opram, 1 );
5454		}
5455
5456		CPU_DISASSEMBLE( upd7801 )
5457		{
5458		return Dasm( buffer, pc, dasmXX_7801, oprom, opram, 0 );
5459		}
5460
5461		CPU_DISASSEMBLE( upd78c05 )
5462		{
5463		return Dasm( buffer, pc, dasmXX_78c05, oprom, opram, 0 );
5464		}

trunk/src/emu/cpu/upd7810/7810ops.inc
r30937	r30938
1		/*****************************************************************************
2		*
3		* Portable uPD7810/11, 7810H/11H, 78C10/C11/C14 emulator V0.2
4		* Copyright Juergen Buchmueller, all rights reserved.
5		*
6		* 7810ops.inc - opcode functions
7		*
8		*****************************************************************************/
9
10		void upd7810_device::illegal()
11		{
12		logerror("uPD7810 '%s': illegal opcode %02x at PC:%04x\n", tag(), OP, PC);
13		}
14
15		void upd7810_device::illegal2()
16		{
17		logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", tag(), OP, OP2, PC);
18		}
19
20		/* prefix 48 */
21
22		/* 48 01: 0100 1000 0000 0001 */
23		void upd7810_device::SLRC_A()
24		{
25		PSW = (PSW & ~CY) \| (A & CY);
26		A >>= 1;
27		SKIP_CY;
28		}
29
30		/* 48 02: 0100 1000 0000 0010 */
31		void upd7810_device::SLRC_B()
32		{
33		PSW = (PSW & ~CY) \| (B & CY);
34		B >>= 1;
35		SKIP_CY;
36		}
37
38		/* 48 03: 0100 1000 0000 0011 */
39		void upd7810_device::SLRC_C()
40		{
41		PSW = (PSW & ~CY) \| (C & CY);
42		C >>= 1;
43		SKIP_CY;
44		}
45
46
47		/* 48 05: 0100 1000 0000 0101 */
48		void upd7810_device::SLLC_A()
49		{
50		PSW = (PSW & ~CY) \| ((A >> 7) & CY);
51		A <<= 1;
52		SKIP_CY;
53		}
54
55		/* 48 06: 0100 1000 0000 0110 */
56		void upd7810_device::SLLC_B()
57		{
58		PSW = (PSW & ~CY) \| ((B >> 7) & CY);
59		B <<= 1;
60		SKIP_CY;
61		}
62
63		/* 48 07: 0100 1000 0000 0111 */
64		void upd7810_device::SLLC_C()
65		{
66		PSW = (PSW & ~CY) \| ((C >> 7) & CY);
67		C <<= 1;
68		SKIP_CY;
69		}
70
71		/* 48 08: 0100 1000 0000 1000 */
72		void upd7810_device::SK_NV()
73		{
74		/* 48 skip never */
75		}
76
77		/* 48 0a: 0100 1000 0000 1010 */
78		void upd7810_device::SK_CY()
79		{
80		if (CY == (PSW & CY))
81		PSW \|= SK;
82		}
83
84		/* 48 0b: 0100 1000 0000 1011 */
85		void upd7810_device::SK_HC()
86		{
87		if (HC == (PSW & HC))
88		PSW \|= SK;
89		}
90
91		/* 48 0c: 0100 1000 0000 1100 */
92		void upd7810_device::SK_Z()
93		{
94		if (Z == (PSW & Z))
95		PSW \|= SK;
96		}
97
98		/* 48 18: 0100 1000 0001 1000 */
99		void upd7810_device::SKN_NV()
100		{
101		/* skip not never -> skip always ;-) */
102		PSW \|= SK;
103		}
104
105		/* 48 1a: 0100 1000 0001 1010 */
106		void upd7810_device::SKN_CY()
107		{
108		if (0 == (PSW & CY))
109		PSW \|= SK;
110		}
111
112		/* 48 1b: 0100 1000 0001 1011 */
113		void upd7810_device::SKN_HC()
114		{
115		if (0 == (PSW & HC))
116		PSW \|= SK;
117		}
118
119		/* 48 1c: 0100 1000 0001 1100 */
120		void upd7810_device::SKN_Z()
121		{
122		if (0 == (PSW & Z))
123		PSW \|= SK;
124		}
125
126		/* 48 21: 0100 1000 0010 0001 */
127		void upd7810_device::SLR_A()
128		{
129		PSW = (PSW & ~CY) \| (A & CY);
130		A >>= 1;
131		}
132
133		/* 48 22: 0100 1000 0010 0010 */
134		void upd7810_device::SLR_B()
135		{
136		PSW = (PSW & ~CY) \| (B & CY);
137		B >>= 1;
138		}
139
140		/* 48 23: 0100 1000 0010 0011 */
141		void upd7810_device::SLR_C()
142		{
143		PSW = (PSW & ~CY) \| (C & CY);
144		C >>= 1;
145		}
146
147		/* 48 25: 0100 1000 0010 0101 */
148		void upd7810_device::SLL_A()
149		{
150		PSW = (PSW & ~CY) \| ((A >> 7) & CY);
151		A <<= 1;
152		}
153
154		/* 48 26: 0100 1000 0010 0110 */
155		void upd7810_device::SLL_B()
156		{
157		PSW = (PSW & ~CY) \| ((B >> 7) & CY);
158		B <<= 1;
159		}
160
161		/* 48 27: 0100 1000 0010 0111 */
162		void upd7810_device::SLL_C()
163		{
164		PSW = (PSW & ~CY) \| ((C >> 7) & CY);
165		C <<= 1;
166		}
167
168		/* 48 28: 0100 1000 0010 1000 */
169		void upd7810_device::JEA()
170		{
171		PC = EA;
172		}
173
174		/* 48 29: 0100 1000 0010 1001 */
175		void upd7810_device::CALB()
176		{
177		SP--;
178		WM( SPD, PCH );
179		SP--;
180		WM( SPD, PCL );
181
182		PC = BC;
183		}
184
185		/* 48 2a: 0100 1000 0010 1010 */
186		void upd7810_device::CLC()
187		{
188		PSW &= ~CY;
189		}
190
191		/* 48 2b: 0100 1000 0010 1011 */
192		void upd7810_device::STC()
193		{
194		PSW \|= CY;
195		}
196
197		/* 48 2d: 0100 1000 0010 1101 */
198		void upd7810_device::MUL_A()
199		{
200		EA = A * A;
201		}
202
203		/* 48 2e: 0100 1000 0010 1110 */
204		void upd7810_device::MUL_B()
205		{
206		EA = A * B;
207		}
208
209		/* 48 2f: 0100 1000 0010 1111 */
210		void upd7810_device::MUL_C()
211		{
212		EA = A * C;
213		}
214
215		/* 48 31: 0100 1000 0011 0001 */
216		void upd7810_device::RLR_A()
217		{
218		UINT8 carry=(PSW&CY)<<7;
219		PSW = (PSW & ~CY) \| (A & CY);
220		A = (A >> 1) \| carry;
221		}
222
223		/* 48 32: 0100 1000 0011 0010 */
224		void upd7810_device::RLR_B()
225		{
226		UINT8 carry=(PSW&CY)<<7;
227		PSW = (PSW & ~CY) \| (B & CY);
228		B = (B >> 1) \| carry;
229		}
230
231		/* 48 33: 0100 1000 0011 0011 */
232		void upd7810_device::RLR_C()
233		{
234		UINT8 carry=(PSW&CY)<<7;
235		PSW = (PSW & ~CY) \| (C & CY);
236		C = (C >> 1) \| carry;
237		}
238
239		/* 48 35: 0100 1000 0011 0101 */
240		void upd7810_device::RLL_A()
241		{
242		UINT8 carry=PSW&CY;
243		PSW = (PSW & ~CY) \| ((A >> 7) & CY);
244		A = (A << 1) \| carry;
245		}
246
247		/* 48 36: 0100 1000 0011 0110 */
248		void upd7810_device::RLL_B()
249		{
250		UINT8 carry=PSW&CY;
251		PSW = (PSW & ~CY) \| ((B >> 7) & CY);
252		B = (B << 1) \| carry;
253		}
254
255		/* 48 37: 0100 1000 0011 0111 */
256		void upd7810_device::RLL_C()
257		{
258		UINT8 carry=PSW&CY;
259		PSW = (PSW & ~CY) \| ((C >> 7) & CY);
260		C = (C << 1) \| carry;
261		}
262
263		/* 48 38: 0100 1000 0011 1000 */
264		void upd7810_device::RLD()
265		{
266		UINT8 m = RM( HL ), tmp;
267		tmp = (m << 4) \| (A & 0x0f);
268		A = (A & 0xf0) \| (m >> 4);
269		WM( HL, tmp );
270		}
271
272		/* 48 39: 0100 1000 0011 1001 */
273		void upd7810_device::RRD()
274		{
275		UINT8 m = RM( HL ), tmp;
276		tmp = (A << 4) \| (m >> 4);
277		A = (A & 0xf0) \| (m & 0x0f);
278		WM( HL, tmp );
279		}
280
281		/* 48 3a: 0100 1000 0011 1010 */
282		void upd7810_device::NEGA()
283		{
284		A = ~A + 1;
285		}
286
287		/* 48 3b: 0100 1000 0011 1011 */
288		void upd7810_device::HALT()
289		{
290		int cycles = (m_icount / 4) * 4;
291		m_icount -= cycles;
292		handle_timers(cycles);
293		PC -= 1; /* continue executing HALT */
294		}
295
296		/* 48 3d: 0100 1000 0011 1101 */
297		void upd7810_device::DIV_A()
298		{
299		if (A)
300		{
301		UINT8 remainder;
302		remainder = EA % A;
303		EA /= A;
304		A = remainder;
305		}
306		else
307		EA = 0xffff; /* guess */
308		}
309
310		/* 48 3e: 0100 1000 0011 1110 */
311		void upd7810_device::DIV_B()
312		{
313		if (B)
314		{
315		UINT8 remainder;
316		remainder = EA % B;
317		EA /= B;
318		B = remainder;
319		}
320		else
321		EA = 0xffff; /* guess */
322		}
323
324		/* 48 3f: 0100 1000 0011 1111 */
325		void upd7810_device::DIV_C()
326		{
327		if (C)
328		{
329		UINT8 remainder;
330		remainder = EA % C;
331		EA /= C;
332		C = remainder;
333		}
334		else
335		EA = 0xffff; /* guess */
336		}
337
338		/* 48 40: 0100 1000 0100 0000 */
339		void upd7810_device::SKIT_NMI()
340		{
341		if (IRR & INTNMI)
342		PSW \|= SK;
343		IRR &= ~INTNMI;
344		}
345
346		/* 48 41: 0100 1000 0100 0001 */
347		void upd7810_device::SKIT_FT0()
348		{
349		if (IRR & INTFT0)
350		PSW \|= SK;
351		IRR &= ~INTFT0;
352		}
353
354		/* 48 42: 0100 1000 0100 0010 */
355		void upd7810_device::SKIT_FT1()
356		{
357		if (IRR & INTFT1)
358		PSW \|= SK;
359		IRR &= ~INTFT1;
360		}
361
362		/* 48 43: 0100 1000 0100 0011 */
363		void upd7810_device::SKIT_F1()
364		{
365		if (IRR & INTF1)
366		PSW \|= SK;
367		IRR &= ~INTF1;
368		}
369
370		/* 48 44: 0100 1000 0100 0100 */
371		void upd7810_device::SKIT_F2()
372		{
373		if (IRR & INTF2)
374		PSW \|= SK;
375		IRR &= ~INTF2;
376		}
377
378		/* 48 45: 0100 1000 0100 0101 */
379		void upd7810_device::SKIT_FE0()
380		{
381		if (IRR & INTFE0)
382		PSW \|= SK;
383		IRR &= ~INTFE0;
384		}
385
386		/* 48 46: 0100 1000 0100 0110 */
387		void upd7810_device::SKIT_FE1()
388		{
389		if (IRR & INTFE1)
390		PSW \|= SK;
391		IRR &= ~INTFE1;
392		}
393
394		/* 48 47: 0100 1000 0100 0111 */
395		void upd7810_device::SKIT_FEIN()
396		{
397		if (IRR & INTFEIN)
398		PSW \|= SK;
399		IRR &= ~INTFEIN;
400		}
401
402		/* 48 48: 0100 1000 0100 1000 */
403		void upd7810_device::SKIT_FAD()
404		{
405		if (IRR & INTFAD)
406		PSW \|= SK;
407		IRR &= ~INTFAD;
408		}
409
410		/* 48 49: 0100 1000 0100 1001 */
411		void upd7810_device::SKIT_FSR()
412		{
413		if (IRR & INTFSR)
414		PSW \|= SK;
415		IRR &= ~INTFSR;
416		}
417
418		/* 48 4a: 0100 1000 0100 1010 */
419		void upd7810_device::SKIT_FST()
420		{
421		if (IRR & INTFST)
422		PSW \|= SK;
423		IRR &= ~INTFST;
424		}
425
426		/* 48 4b: 0100 1000 0100 1011 */
427		void upd7810_device::SKIT_ER()
428		{
429		if (IRR & INTER)
430		PSW \|= SK;
431		IRR &= ~INTER;
432		}
433
434		/* 48 4c: 0100 1000 0100 1100 */
435		void upd7810_device::SKIT_OV()
436		{
437		if (IRR & INTOV)
438		PSW \|= SK;
439		IRR &= ~INTOV;
440		}
441
442		/* 48 50: 0100 1000 0101 0000 */
443		void upd7810_device::SKIT_AN4()
444		{
445		if (ITF & INTAN4)
446		PSW \|= SK;
447		ITF &= ~INTAN4;
448		}
449
450		/* 48 51: 0100 1000 0101 0001 */
451		void upd7810_device::SKIT_AN5()
452		{
453		if (ITF & INTAN5)
454		PSW \|= SK;
455		ITF &= ~INTAN5;
456		}
457
458		/* 48 52: 0100 1000 0101 0010 */
459		void upd7810_device::SKIT_AN6()
460		{
461		if (ITF & INTAN6)
462		PSW \|= SK;
463		ITF &= ~INTAN6;
464		}
465
466		/* 48 53: 0100 1000 0101 0011 */
467		void upd7810_device::SKIT_AN7()
468		{
469		if (ITF & INTAN7)
470		PSW \|= SK;
471		ITF &= ~INTAN7;
472		}
473
474		/* 48 54: 0100 1000 0101 0100 */
475		void upd7810_device::SKIT_SB()
476		{
477		if (ITF & INTSB)
478		PSW \|= SK;
479		ITF &= ~INTSB;
480		}
481
482		/* 48 60: 0100 1000 0110 0000 */
483		void upd7810_device::SKNIT_NMI()
484		{
485		if (0 == (IRR & INTNMI))
486		PSW \|= SK;
487		IRR &= ~INTNMI;
488		}
489
490		/* 48 61: 0100 1000 0110 0001 */
491		void upd7810_device::SKNIT_FT0()
492		{
493		if (0 == (IRR & INTFT0))
494		PSW \|= SK;
495		IRR &= ~INTFT0;
496		}
497
498		/* 48 62: 0100 1000 0110 0010 */
499		void upd7810_device::SKNIT_FT1()
500		{
501		if (0 == (IRR & INTFT1))
502		PSW \|= SK;
503		IRR &= ~INTFT1;
504		}
505
506		/* 48 63: 0100 1000 0110 0011 */
507		void upd7810_device::SKNIT_F1()
508		{
509		if (0 == (IRR & INTF1))
510		PSW \|= SK;
511		IRR &= ~INTF1;
512		}
513
514		/* 48 64: 0100 1000 0110 0100 */
515		void upd7810_device::SKNIT_F2()
516		{
517		if (0 == (IRR & INTF2))
518		PSW \|= SK;
519		IRR &= ~INTF2;
520		}
521
522		/* 48 65: 0100 1000 0110 0101 */
523		void upd7810_device::SKNIT_FE0()
524		{
525		if (0 == (IRR & INTFE0))
526		PSW \|= SK;
527		IRR &= ~INTFE0;
528		}
529
530		/* 48 66: 0100 1000 0110 0110 */
531		void upd7810_device::SKNIT_FE1()
532		{
533		if (0 == (IRR & INTFE1))
534		PSW \|= SK;
535		IRR &= ~INTFE1;
536		}
537
538		/* 48 67: 0100 1000 0110 0111 */
539		void upd7810_device::SKNIT_FEIN()
540		{
541		if (0 == (IRR & INTFEIN))
542		PSW \|= SK;
543		IRR &= ~INTFEIN;
544		}
545
546		/* 48 68: 0100 1000 0110 1000 */
547		void upd7810_device::SKNIT_FAD()
548		{
549		if (0 == (IRR & INTFAD))
550		PSW \|= SK;
551		IRR &= ~INTFAD;
552		}
553
554		/* 48 69: 0100 1000 0110 1001 */
555		void upd7810_device::SKNIT_FSR()
556		{
557		if (0 == (IRR & INTFSR))
558		PSW \|= SK;
559		IRR &= ~INTFSR;
560		}
561
562		/* 48 6a: 0100 1000 0110 1010 */
563		void upd7810_device::SKNIT_FST()
564		{
565		if (0 == (IRR & INTFST))
566		PSW \|= SK;
567		IRR &= ~INTFST;
568		}
569
570		/* 48 6b: 0100 1000 0110 1011 */
571		void upd7810_device::SKNIT_ER()
572		{
573		if (0 == (IRR & INTER))
574		PSW \|= SK;
575		IRR &= ~INTER;
576		}
577
578		/* 48 6c: 0100 1000 0110 1100 */
579		void upd7810_device::SKNIT_OV()
580		{
581		if (0 == (IRR & INTOV))
582		PSW \|= SK;
583		IRR &= ~INTOV;
584		}
585
586		/* 48 70: 0100 1000 0111 0000 */
587		void upd7810_device::SKNIT_AN4()
588		{
589		if (0 == (ITF & INTAN4))
590		PSW \|= SK;
591		ITF &= ~INTAN4;
592		}
593
594		/* 48 71: 0100 1000 0111 0001 */
595		void upd7810_device::SKNIT_AN5()
596		{
597		if (0 == (ITF & INTAN5))
598		PSW \|= SK;
599		ITF &= ~INTAN5;
600		}
601
602		/* 48 72: 0100 1000 0111 0010 */
603		void upd7810_device::SKNIT_AN6()
604		{
605		if (0 == (ITF & INTAN6))
606		PSW \|= SK;
607		ITF &= ~INTAN6;
608		}
609
610		/* 48 73: 0100 1000 0111 0011 */
611		void upd7810_device::SKNIT_AN7()
612		{
613		if (0 == (ITF & INTAN7))
614		PSW \|= SK;
615		ITF &= ~INTAN7;
616		}
617
618		/* 48 74: 0100 1000 0111 0100 */
619		void upd7810_device::SKNIT_SB()
620		{
621		if (0 == (ITF & INTSB))
622		PSW \|= SK;
623		ITF &= ~INTSB;
624		}
625
626		/* 48 82: 0100 1000 1000 0010 */
627		void upd7810_device::LDEAX_D()
628		{
629		EAL = RM( DE );
630		EAH = RM( DE + 1 );
631		}
632
633		/* 48 83: 0100 1000 1000 0011 */
634		void upd7810_device::LDEAX_H()
635		{
636		EAL = RM( HL );
637		EAH = RM( HL + 1 );
638		}
639
640		/* 48 84: 0100 1000 1000 0100 */
641		void upd7810_device::LDEAX_Dp()
642		{
643		EAL = RM( DE );
644		EAH = RM( DE + 1 );
645		DE += 2;
646		}
647
648		/* 48 85: 0100 1000 1000 0101 */
649		void upd7810_device::LDEAX_Hp()
650		{
651		EAL = RM( HL );
652		EAH = RM( HL + 1 );
653		HL += 2;
654		}
655
656		/* 48 8b: 0100 1000 1000 1011 xxxx xxxx */
657		void upd7810_device::LDEAX_D_xx()
658		{
659		UINT16 ea;
660		RDOPARG( ea );
661		ea += DE;
662		EAL = RM( ea );
663		EAH = RM( ea + 1 );
664		}
665
666		/* 48 8c: 0100 1000 1000 1100 */
667		void upd7810_device::LDEAX_H_A()
668		{
669		UINT16 ea = HL + A;
670		EAL = RM( ea );
671		EAH = RM( ea + 1 );
672		}
673
674		/* 48 8d: 0100 1000 1000 1101 */
675		void upd7810_device::LDEAX_H_B()
676		{
677		UINT16 ea = HL + B;
678		EAL = RM( ea );
679		EAH = RM( ea + 1 );
680		}
681
682		/* 48 8e: 0100 1000 1000 1110 */
683		void upd7810_device::LDEAX_H_EA()
684		{
685		UINT16 ea = HL + EA;
686		EAL = RM( ea );
687		EAH = RM( ea + 1 );
688		}
689
690		/* 48 8f: 0100 1000 1000 1111 xxxx xxxx */
691		void upd7810_device::LDEAX_H_xx()
692		{
693		UINT16 ea;
694		RDOPARG( ea );
695		ea += HL;
696		EAL = RM( ea );
697		EAH = RM( ea + 1 );
698		}
699
700		/* 48 92: 0100 1000 1000 0010 */
701		void upd7810_device::STEAX_D()
702		{
703		WM( DE, EAL );
704		WM( DE + 1, EAH );
705		}
706
707		/* 48 93: 0100 1000 1000 0011 */
708		void upd7810_device::STEAX_H()
709		{
710		WM( HL, EAL );
711		WM( HL + 1, EAH );
712		}
713
714		/* 48 94: 0100 1000 1000 0100 */
715		void upd7810_device::STEAX_Dp()
716		{
717		WM( DE, EAL );
718		WM( DE + 1, EAH );
719		DE += 2;
720		}
721
722		/* 48 95: 0100 1000 1000 0101 */
723		void upd7810_device::STEAX_Hp()
724		{
725		WM( HL, EAL );
726		WM( HL + 1, EAH );
727		HL += 2;
728		}
729
730		/* 48 9b: 0100 1000 1000 1011 xxxx xxxx */
731		void upd7810_device::STEAX_D_xx()
732		{
733		UINT16 ea;
734		RDOPARG( ea );
735		ea += DE;
736		WM( ea, EAL );
737		WM( ea + 1, EAH );
738		}
739
740		/* 48 9c: 0100 1000 1000 1100 */
741		void upd7810_device::STEAX_H_A()
742		{
743		UINT16 ea = HL + A;
744		WM( ea, EAL );
745		WM( ea + 1, EAH );
746		}
747
748		/* 48 9d: 0100 1000 1000 1101 */
749		void upd7810_device::STEAX_H_B()
750		{
751		UINT16 ea = HL + B;
752		WM( ea, EAL );
753		WM( ea + 1, EAH );
754		}
755
756		/* 48 9e: 0100 1000 1000 1110 */
757		void upd7810_device::STEAX_H_EA()
758		{
759		UINT16 ea = HL + EA;
760		WM( ea, EAL );
761		WM( ea + 1, EAH );
762		}
763
764		/* 48 9f: 0100 1000 1000 1111 xxxx xxxx */
765		void upd7810_device::STEAX_H_xx()
766		{
767		UINT16 ea;
768		RDOPARG( ea );
769		ea += HL;
770		WM( ea, EAL );
771		WM( ea + 1, EAH );
772		}
773
774		/* 48 a0: 0100 1000 1010 0000 */
775		void upd7810_device::DSLR_EA()
776		{
777		PSW = (PSW & ~CY) \| (EA & CY);
778		EA >>= 1;
779		}
780
781		/* 48 a4: 0100 1000 1010 0100 */
782		void upd7810_device::DSLL_EA()
783		{
784		PSW = (PSW & ~CY) \| ((EA >> 15) & CY);
785		EA <<= 1;
786		}
787
788		/* 48 a8: 0100 1000 1010 1000 */
789		void upd7810_device::TABLE()
790		{
791		UINT16 ea = PC + A + 1;
792		C = RM( ea );
793		B = RM( ea + 1 );
794		}
795
796		/* 48 b0: 0100 1000 1011 0000 */
797		void upd7810_device::DRLR_EA()
798		{
799		UINT8 carry=PSW&CY;
800		PSW = (PSW & ~CY) \| (EA & CY);
801		EA = (EA >> 1) \| (carry << 15);
802		}
803
804		/* 48 b4: 0100 1000 1011 0100 */
805		void upd7810_device::DRLL_EA()
806		{
807		UINT8 carry=PSW&CY;
808		PSW = (PSW & ~CY) \| ((EA >> 15) & CY);
809		EA = (EA << 1) \| carry;
810		}
811
812		/* 48 bb: 0100 1000 1011 1011 */
813		void upd7810_device::STOP()
814		{
815		int cycles = (m_icount / 4) * 4;
816		m_icount -= cycles;
817		handle_timers(cycles);
818		PC -= 1;
819		}
820
821		/* 48 c0: 0100 1000 1100 0000 */
822		void upd7810_device::DMOV_EA_ECNT()
823		{
824		EA = ECNT;
825		}
826
827		/* 48 c1: 0100 1000 1100 0001 */
828		void upd7810_device::DMOV_EA_ECPT()
829		{
830		EA = ECPT;
831		}
832
833		/* 48 d2: 0100 1000 1101 0010 */
834		void upd7810_device::DMOV_ETM0_EA()
835		{
836		ETM0 = EA;
837		}
838
839		/* 48 d3: 0100 1000 1101 0011 */
840		void upd7810_device::DMOV_ETM1_EA()
841		{
842		ETM1 = EA;
843		}
844
845		/* prefix 4C */
846		/* 4c c0: 0100 1100 1100 0000 */
847		void upd7810_device::MOV_A_PA()
848		{
849		A = RP( UPD7810_PORTA );
850		}
851
852		/* 4c c1: 0100 1100 1100 0001 */
853		void upd7810_device::MOV_A_PB()
854		{
855		A = RP( UPD7810_PORTB );
856		}
857
858		/* 4c c2: 0100 1100 1100 0010 */
859		void upd7810_device::MOV_A_PC()
860		{
861		A = RP( UPD7810_PORTC );
862		}
863
864		/* 4c c3: 0100 1100 1100 0011 */
865		void upd7810_device::MOV_A_PD()
866		{
867		A = RP( UPD7810_PORTD );
868		}
869
870		/* 4c c5: 0100 1100 1100 0101 */
871		void upd7810_device::MOV_A_PF()
872		{
873		A = RP( UPD7810_PORTF );
874		}
875
876		/* 4c c6: 0100 1100 1100 0110 */
877		void upd7810_device::MOV_A_MKH()
878		{
879		A = MKH;
880		}
881
882		/* 4c c7: 0100 1100 1100 0111 */
883		void upd7810_device::MOV_A_MKL()
884		{
885		A = MKL;
886		}
887
888		/* 4c c8: 0100 1100 1100 1000 */
889		void upd7810_device::MOV_A_ANM()
890		{
891		A = ANM;
892		}
893
894		/* 4c c9: 0100 1100 1100 1001 */
895		void upd7810_device::MOV_A_SMH()
896		{
897		A = SMH;
898		}
899
900		/* 4c cb: 0100 1100 1100 1011 */
901		void upd7810_device::MOV_A_EOM()
902		{
903		/* only bits #1 and #5 can be read */
904		UINT8 eom = EOM & 0x22;
905		A = eom;
906		}
907
908		/* 4c cd: 0100 1100 1100 1101 */
909		void upd7810_device::MOV_A_TMM()
910		{
911		A = TMM;
912		}
913
914		/* 4c ce: 0100 1100 1110 0000 (7807 only) */
915		void upd7810_device::MOV_A_PT()
916		{
917		A = RP( UPD7807_PORTT );
918		}
919
920		/* 4c d9: 0100 1100 1101 1001 */
921		void upd7810_device::MOV_A_RXB()
922		{
923		A = RXB;
924		}
925
926		/* 4c e0: 0100 1100 1110 0000 */
927		void upd7810_device::MOV_A_CR0()
928		{
929		A = CR0;
930		}
931
932		/* 4c e1: 0100 1100 1110 0001 */
933		void upd7810_device::MOV_A_CR1()
934		{
935		A = CR1;
936		}
937
938		/* 4c e2: 0100 1100 1110 0010 */
939		void upd7810_device::MOV_A_CR2()
940		{
941		A = CR2;
942		}
943
944		/* 4c e3: 0100 1100 1110 0011 */
945		void upd7810_device::MOV_A_CR3()
946		{
947		A = CR3;
948		}
949
950		/* prefix 4D */
951		/* 4d c0: 0100 1101 1100 0000 */
952		void upd7810_device::MOV_PA_A()
953		{
954		WP( UPD7810_PORTA, A );
955		}
956
957		/* 4d c1: 0100 1101 1100 0001 */
958		void upd7810_device::MOV_PB_A()
959		{
960		WP( UPD7810_PORTB, A );
961		}
962
963		/* 4d c2: 0100 1101 1100 0010 */
964		void upd7810_device::MOV_PC_A()
965		{
966		WP( UPD7810_PORTC, A );
967		}
968
969		/* 4d c3: 0100 1101 1100 0011 */
970		void upd7810_device::MOV_PD_A()
971		{
972		WP( UPD7810_PORTD, A );
973		}
974
975		/* 4d c5: 0100 1101 1100 0101 */
976		void upd7810_device::MOV_PF_A()
977		{
978		WP( UPD7810_PORTF, A );
979		}
980
981		/* 4d c6: 0100 1101 1100 0110 */
982		void upd7810_device::MOV_MKH_A()
983		{
984		MKH = A;
985		}
986
987		/* 4d c7: 0100 1101 1100 0111 */
988		void upd7810_device::MOV_MKL_A()
989		{
990		MKL = A;
991		}
992
993		/* 4d c8: 0100 1101 1100 1000 */
994		void upd7810_device::MOV_ANM_A()
995		{
996		ANM = A;
997		}
998
999		/* 4d c9: 0100 1101 1100 1001 */
1000		void upd7810_device::MOV_SMH_A()
1001		{
1002		SMH = A;
1003		}
1004
1005		/* 4d ca: 0100 1101 1100 1010 */
1006		void upd7810_device::MOV_SML_A()
1007		{
1008		SML = A;
1009		}
1010
1011		/* 4d cb: 0100 1101 1100 1011 */
1012		void upd7810_device::MOV_EOM_A()
1013		{
1014		EOM = A;
1015		upd7810_write_EOM();
1016		}
1017
1018		/* 4d cc: 0100 1101 1100 1100 */
1019		void upd7810_device::MOV_ETMM_A()
1020		{
1021		ETMM = A;
1022		}
1023
1024		/* 4d cd: 0100 1101 1100 1101 */
1025		void upd7810_device::MOV_TMM_A()
1026		{
1027		TMM = A;
1028		}
1029
1030		/* 4d d0: 0100 1101 1101 0000 */
1031		void upd7810_device::MOV_MM_A()
1032		{
1033		MM = A;
1034		}
1035
1036		/* 4d d1: 0100 1101 1101 0001 */
1037		void upd7810_device::MOV_MCC_A()
1038		{
1039		MCC = A;
1040		}
1041
1042		/* 4d d2: 0100 1101 1101 0010 */
1043		void upd7810_device::MOV_MA_A()
1044		{
1045		MA = A;
1046		}
1047
1048		/* 4d d3: 0100 1101 1101 0011 */
1049		void upd7810_device::MOV_MB_A()
1050		{
1051		MB = A;
1052		}
1053
1054		/* 4d d4: 0100 1101 1101 0100 */
1055		void upd7810_device::MOV_MC_A()
1056		{
1057		MC = A;
1058		}
1059
1060		/* 4d d7: 0100 1101 1101 0111 */
1061		void upd7810_device::MOV_MF_A()
1062		{
1063		MF = A;
1064		}
1065
1066		/* 4d d8: 0100 1101 1101 1000 */
1067		void upd7810_device::MOV_TXB_A()
1068		{
1069		TXB = A;
1070		upd7810_write_TXB();
1071		}
1072
1073		/* 4d da: 0100 1101 1101 1010 */
1074		void upd7810_device::MOV_TM0_A()
1075		{
1076		TM0 = A;
1077		}
1078
1079		/* 4d db: 0100 1101 1101 1011 */
1080		void upd7810_device::MOV_TM1_A()
1081		{
1082		TM1 = A;
1083		}
1084
1085		/* 4d e8: 0100 1101 1110 1000 */
1086		void upd7810_device::MOV_ZCM_A()
1087		{
1088		ZCM = A;
1089		}
1090
1091		/* prefix 60 */
1092		/* 60 08: 0110 0000 0000 1000 */
1093		void upd7810_device::ANA_V_A()
1094		{
1095		V &= A;
1096		SET_Z(V);
1097		}
1098
1099		/* 60 09: 0110 0000 0000 1001 */
1100		void upd7810_device::ANA_A_A()
1101		{
1102		A &= A;
1103		SET_Z(A);
1104		}
1105
1106		/* 60 0a: 0110 0000 0000 1010 */
1107		void upd7810_device::ANA_B_A()
1108		{
1109		B &= A;
1110		SET_Z(B);
1111		}
1112
1113		/* 60 0b: 0110 0000 0000 1011 */
1114		void upd7810_device::ANA_C_A()
1115		{
1116		C &= A;
1117		SET_Z(C);
1118		}
1119
1120		/* 60 0c: 0110 0000 0000 1100 */
1121		void upd7810_device::ANA_D_A()
1122		{
1123		D &= A;
1124		SET_Z(D);
1125		}
1126
1127		/* 60 0d: 0110 0000 0000 1101 */
1128		void upd7810_device::ANA_E_A()
1129		{
1130		E &= A;
1131		SET_Z(E);
1132		}
1133
1134		/* 60 0e: 0110 0000 0000 1110 */
1135		void upd7810_device::ANA_H_A()
1136		{
1137		H &= A;
1138		SET_Z(H);
1139		}
1140
1141		/* 60 0f: 0110 0000 0000 1111 */
1142		void upd7810_device::ANA_L_A()
1143		{
1144		L &= A;
1145		SET_Z(L);
1146		}
1147
1148		/* 60 10: 0110 0000 0001 0000 */
1149		void upd7810_device::XRA_V_A()
1150		{
1151		V ^= A;
1152		SET_Z(V);
1153		}
1154
1155		/* 60 11: 0110 0000 0001 0001 */
1156		void upd7810_device::XRA_A_A()
1157		{
1158		A ^= A;
1159		SET_Z(A);
1160		}
1161
1162		/* 60 12: 0110 0000 0001 0010 */
1163		void upd7810_device::XRA_B_A()
1164		{
1165		B ^= A;
1166		SET_Z(B);
1167		}
1168
1169		/* 60 13: 0110 0000 0001 0011 */
1170		void upd7810_device::XRA_C_A()
1171		{
1172		C ^= A;
1173		SET_Z(C);
1174		}
1175
1176		/* 60 14: 0110 0000 0001 0100 */
1177		void upd7810_device::XRA_D_A()
1178		{
1179		D ^= A;
1180		SET_Z(D);
1181		}
1182
1183		/* 60 15: 0110 0000 0001 0101 */
1184		void upd7810_device::XRA_E_A()
1185		{
1186		E ^= A;
1187		SET_Z(E);
1188		}
1189
1190		/* 60 16: 0110 0000 0001 0110 */
1191		void upd7810_device::XRA_H_A()
1192		{
1193		H ^= A;
1194		SET_Z(H);
1195		}
1196
1197		/* 60 17: 0110 0000 0001 0111 */
1198		void upd7810_device::XRA_L_A()
1199		{
1200		L ^= A;
1201		SET_Z(L);
1202		}
1203
1204		/* 60 18: 0110 0000 0001 1000 */
1205		void upd7810_device::ORA_V_A()
1206		{
1207		V \|= A;
1208		SET_Z(V);
1209		}
1210
1211		/* 60 19: 0110 0000 0001 1001 */
1212		void upd7810_device::ORA_A_A()
1213		{
1214		A \|= A;
1215		SET_Z(A);
1216		}
1217
1218		/* 60 1a: 0110 0000 0001 1010 */
1219		void upd7810_device::ORA_B_A()
1220		{
1221		B \|= A;
1222		SET_Z(B);
1223		}
1224
1225		/* 60 1b: 0110 0000 0001 1011 */
1226		void upd7810_device::ORA_C_A()
1227		{
1228		C \|= A;
1229		SET_Z(C);
1230		}
1231
1232		/* 60 1c: 0110 0000 0001 1100 */
1233		void upd7810_device::ORA_D_A()
1234		{
1235		D \|= A;
1236		SET_Z(D);
1237		}
1238
1239		/* 60 1d: 0110 0000 0001 1101 */
1240		void upd7810_device::ORA_E_A()
1241		{
1242		E \|= A;
1243		SET_Z(E);
1244		}
1245
1246		/* 60 1e: 0110 0000 0001 1110 */
1247		void upd7810_device::ORA_H_A()
1248		{
1249		H \|= A;
1250		SET_Z(H);
1251		}
1252
1253		/* 60 1f: 0110 0000 0001 1111 */
1254		void upd7810_device::ORA_L_A()
1255		{
1256		L \|= A;
1257		SET_Z(L);
1258		}
1259
1260		/* 60 20: 0110 0000 0010 0000 */
1261		void upd7810_device::ADDNC_V_A()
1262		{
1263		UINT8 tmp = V + A;
1264		ZHC_ADD( tmp, V, 0 );
1265		V = tmp;
1266		SKIP_NC;
1267		}
1268
1269		/* 60 21: 0110 0000 0010 0001 */
1270		void upd7810_device::ADDNC_A_A()
1271		{
1272		UINT8 tmp = A + A;
1273		ZHC_ADD( tmp, A, 0 );
1274		A = tmp;
1275		SKIP_NC;
1276		}
1277
1278		/* 60 22: 0110 0000 0010 0010 */
1279		void upd7810_device::ADDNC_B_A()
1280		{
1281		UINT8 tmp = B + A;
1282		ZHC_ADD( tmp, B, 0 );
1283		B = tmp;
1284		SKIP_NC;
1285		}
1286
1287		/* 60 23: 0110 0000 0010 0011 */
1288		void upd7810_device::ADDNC_C_A()
1289		{
1290		UINT8 tmp = C + A;
1291		ZHC_ADD( tmp, C, 0 );
1292		C = tmp;
1293		SKIP_NC;
1294		}
1295
1296		/* 60 24: 0110 0000 0010 0100 */
1297		void upd7810_device::ADDNC_D_A()
1298		{
1299		UINT8 tmp = D + A;
1300		ZHC_ADD( tmp, D, 0 );
1301		D = tmp;
1302		SKIP_NC;
1303		}
1304
1305		/* 60 25: 0110 0000 0010 0101 */
1306		void upd7810_device::ADDNC_E_A()
1307		{
1308		UINT8 tmp = E + A;
1309		ZHC_ADD( tmp, E, 0 );
1310		E = tmp;
1311		SKIP_NC;
1312		}
1313
1314		/* 60 26: 0110 0000 0010 0110 */
1315		void upd7810_device::ADDNC_H_A()
1316		{
1317		UINT8 tmp = H + A;
1318		ZHC_ADD( tmp, H, 0 );
1319		H = tmp;
1320		SKIP_NC;
1321		}
1322
1323		/* 60 27: 0110 0000 0010 0111 */
1324		void upd7810_device::ADDNC_L_A()
1325		{
1326		UINT8 tmp = L + A;
1327		ZHC_ADD( tmp, L, 0 );
1328		L = tmp;
1329		SKIP_NC;
1330		}
1331
1332		/* 60 28: 0110 0000 0010 1000 */
1333		void upd7810_device::GTA_V_A()
1334		{
1335		UINT16 tmp = V - A - 1;
1336		ZHC_SUB( tmp, V, 0 );
1337		SKIP_NC;
1338		}
1339
1340		/* 60 29: 0110 0000 0010 1001 */
1341		void upd7810_device::GTA_A_A()
1342		{
1343		UINT16 tmp = A - A - 1;
1344		ZHC_SUB( tmp, A, 0 );
1345		SKIP_NC;
1346		}
1347
1348		/* 60 2a: 0110 0000 0010 1010 */
1349		void upd7810_device::GTA_B_A()
1350		{
1351		UINT16 tmp = B - A - 1;
1352		ZHC_SUB( tmp, B, 0 );
1353		SKIP_NC;
1354		}
1355
1356		/* 60 2b: 0110 0000 0010 1011 */
1357		void upd7810_device::GTA_C_A()
1358		{
1359		UINT16 tmp = C - A - 1;
1360		ZHC_SUB( tmp, C, 0 );
1361		SKIP_NC;
1362		}
1363
1364		/* 60 2c: 0110 0000 0010 1100 */
1365		void upd7810_device::GTA_D_A()
1366		{
1367		UINT16 tmp = D - A - 1;
1368		ZHC_SUB( tmp, D, 0 );
1369		SKIP_NC;
1370		}
1371
1372		/* 60 2d: 0110 0000 0010 1101 */
1373		void upd7810_device::GTA_E_A()
1374		{
1375		UINT16 tmp = E - A - 1;
1376		ZHC_SUB( tmp, E, 0 );
1377		SKIP_NC;
1378		}
1379
1380		/* 60 2e: 0110 0000 0010 1110 */
1381		void upd7810_device::GTA_H_A()
1382		{
1383		UINT16 tmp = H - A - 1;
1384		ZHC_SUB( tmp, H, 0 );
1385		SKIP_NC;
1386		}
1387
1388		/* 60 2f: 0110 0000 0010 1111 */
1389		void upd7810_device::GTA_L_A()
1390		{
1391		UINT16 tmp = L - A - 1;
1392		ZHC_SUB( tmp, L, 0 );
1393		SKIP_NC;
1394		}
1395
1396		/* 60 30: 0110 0000 0011 0000 */
1397		void upd7810_device::SUBNB_V_A()
1398		{
1399		UINT8 tmp = V - A;
1400		ZHC_SUB( tmp, V, 0 );
1401		V = tmp;
1402		SKIP_NC;
1403		}
1404
1405		/* 60 31: 0110 0000 0011 0001 */
1406		void upd7810_device::SUBNB_A_A()
1407		{
1408		UINT8 tmp = A - A;
1409		ZHC_SUB( tmp, A, 0 );
1410		A = tmp;
1411		SKIP_NC;
1412		}
1413
1414		/* 60 32: 0110 0000 0011 0010 */
1415		void upd7810_device::SUBNB_B_A()
1416		{
1417		UINT8 tmp = B - A;
1418		ZHC_SUB( tmp, B, 0 );
1419		B = tmp;
1420		SKIP_NC;
1421		}
1422
1423		/* 60 33: 0110 0000 0011 0011 */
1424		void upd7810_device::SUBNB_C_A()
1425		{
1426		UINT8 tmp = C - A;
1427		ZHC_SUB( tmp, C, 0 );
1428		C = tmp;
1429		SKIP_NC;
1430		}
1431
1432		/* 60 34: 0110 0000 0011 0100 */
1433		void upd7810_device::SUBNB_D_A()
1434		{
1435		UINT8 tmp = D - A;
1436		ZHC_SUB( tmp, D, 0 );
1437		D = tmp;
1438		SKIP_NC;
1439		}
1440
1441		/* 60 35: 0110 0000 0011 0101 */
1442		void upd7810_device::SUBNB_E_A()
1443		{
1444		UINT8 tmp = E - A;
1445		ZHC_SUB( tmp, E, 0 );
1446		E = tmp;
1447		SKIP_NC;
1448		}
1449
1450		/* 60 36: 0110 0000 0011 0110 */
1451		void upd7810_device::SUBNB_H_A()
1452		{
1453		UINT8 tmp = H - A;
1454		ZHC_SUB( tmp, H, 0 );
1455		H = tmp;
1456		SKIP_NC;
1457		}
1458
1459		/* 60 37: 0110 0000 0011 0111 */
1460		void upd7810_device::SUBNB_L_A()
1461		{
1462		UINT8 tmp = L - A;
1463		ZHC_SUB( tmp, L, 0 );
1464		L = tmp;
1465		SKIP_NC;
1466		}
1467
1468		/* 60 38: 0110 0000 0011 1000 */
1469		void upd7810_device::LTA_V_A()
1470		{
1471		UINT8 tmp = V - A;
1472		ZHC_SUB( tmp, V, 0 );
1473		SKIP_CY;
1474		}
1475
1476		/* 60 39: 0110 0000 0011 1001 */
1477		void upd7810_device::LTA_A_A()
1478		{
1479		UINT8 tmp = A - A;
1480		ZHC_SUB( tmp, A, 0 );
1481		SKIP_CY;
1482		}
1483
1484		/* 60 3a: 0110 0000 0011 1010 */
1485		void upd7810_device::LTA_B_A()
1486		{
1487		UINT8 tmp = B - A;
1488		ZHC_SUB( tmp, B, 0 );
1489		SKIP_CY;
1490		}
1491
1492		/* 60 3b: 0110 0000 0011 1011 */
1493		void upd7810_device::LTA_C_A()
1494		{
1495		UINT8 tmp = C - A;
1496		ZHC_SUB( tmp, C, 0 );
1497		SKIP_CY;
1498		}
1499
1500		/* 60 3c: 0110 0000 0011 1100 */
1501		void upd7810_device::LTA_D_A()
1502		{
1503		UINT8 tmp = D - A;
1504		ZHC_SUB( tmp, D, 0 );
1505		SKIP_CY;
1506		}
1507
1508		/* 60 3d: 0110 0000 0011 1101 */
1509		void upd7810_device::LTA_E_A()
1510		{
1511		UINT8 tmp = E - A;
1512		ZHC_SUB( tmp, E, 0 );
1513		SKIP_CY;
1514		}
1515
1516		/* 60 3e: 0110 0000 0011 1110 */
1517		void upd7810_device::LTA_H_A()
1518		{
1519		UINT8 tmp = H - A;
1520		ZHC_SUB( tmp, H, 0 );
1521		SKIP_CY;
1522		}
1523
1524		/* 60 3f: 0110 0000 0011 1111 */
1525		void upd7810_device::LTA_L_A()
1526		{
1527		UINT8 tmp = L - A;
1528		ZHC_SUB( tmp, L, 0 );
1529		SKIP_CY;
1530		}
1531
1532		/* 60 40: 0110 0000 0100 0000 */
1533		void upd7810_device::ADD_V_A()
1534		{
1535		UINT8 tmp = V + A;
1536		ZHC_ADD( tmp, V, 0 );
1537		V = tmp;
1538		}
1539
1540		/* 60 41: 0110 0000 0100 0001 */
1541		void upd7810_device::ADD_A_A()
1542		{
1543		UINT8 tmp = A + A;
1544		ZHC_ADD( tmp, A, 0 );
1545		A = tmp;
1546		}
1547
1548		/* 60 42: 0110 0000 0100 0010 */
1549		void upd7810_device::ADD_B_A()
1550		{
1551		UINT8 tmp = B + A;
1552		ZHC_ADD( tmp, B, 0 );
1553		B = tmp;
1554		}
1555
1556		/* 60 43: 0110 0000 0100 0011 */
1557		void upd7810_device::ADD_C_A()
1558		{
1559		UINT8 tmp = C + A;
1560		ZHC_ADD( tmp, C, 0 );
1561		C = tmp;
1562		}
1563
1564		/* 60 44: 0110 0000 0100 0100 */
1565		void upd7810_device::ADD_D_A()
1566		{
1567		UINT8 tmp = D + A;
1568		ZHC_ADD( tmp, D, 0 );
1569		D = tmp;
1570		}
1571
1572		/* 60 45: 0110 0000 0100 0101 */
1573		void upd7810_device::ADD_E_A()
1574		{
1575		UINT8 tmp = E + A;
1576		ZHC_ADD( tmp, E, 0 );
1577		E = tmp;
1578		}
1579
1580		/* 60 46: 0110 0000 0100 0110 */
1581		void upd7810_device::ADD_H_A()
1582		{
1583		UINT8 tmp = H + A;
1584		ZHC_ADD( tmp, H, 0 );
1585		H = tmp;
1586		}
1587
1588		/* 60 47: 0110 0000 0100 0111 */
1589		void upd7810_device::ADD_L_A()
1590		{
1591		UINT8 tmp = L + A;
1592		ZHC_ADD( tmp, L, 0 );
1593		L = tmp;
1594		}
1595
1596		/* 60 50: 0110 0000 0101 0000 */
1597		void upd7810_device::ADC_V_A()
1598		{
1599		UINT8 tmp = V + A + (PSW & CY);
1600		ZHC_ADD( tmp, V, (PSW & CY) );
1601		V = tmp;
1602		}
1603
1604		/* 60 51: 0110 0000 0101 0001 */
1605		void upd7810_device::ADC_A_A()
1606		{
1607		UINT8 tmp = A + A + (PSW & CY);
1608		ZHC_ADD( tmp, A, (PSW & CY) );
1609		A = tmp;
1610		}
1611
1612		/* 60 52: 0110 0000 0101 0010 */
1613		void upd7810_device::ADC_B_A()
1614		{
1615		UINT8 tmp = B + A + (PSW & CY);
1616		ZHC_ADD( tmp, B, (PSW & CY) );
1617		B = tmp;
1618		}
1619
1620		/* 60 53: 0110 0000 0101 0011 */
1621		void upd7810_device::ADC_C_A()
1622		{
1623		UINT8 tmp = C + A + (PSW & CY);
1624		ZHC_ADD( tmp, C, (PSW & CY) );
1625		C = tmp;
1626		}
1627
1628		/* 60 54: 0110 0000 0101 0100 */
1629		void upd7810_device::ADC_D_A()
1630		{
1631		UINT8 tmp = D + A + (PSW & CY);
1632		ZHC_ADD( tmp, D, (PSW & CY) );
1633		D = tmp;
1634		}
1635
1636		/* 60 55: 0110 0000 0101 0101 */
1637		void upd7810_device::ADC_E_A()
1638		{
1639		UINT8 tmp = E + A + (PSW & CY);
1640		ZHC_ADD( tmp, E, (PSW & CY) );
1641		E = tmp;
1642		}
1643
1644		/* 60 56: 0110 0000 0101 0110 */
1645		void upd7810_device::ADC_H_A()
1646		{
1647		UINT8 tmp = H + A + (PSW & CY);
1648		ZHC_ADD( tmp, H, (PSW & CY) );
1649		H = tmp;
1650		}
1651
1652		/* 60 57: 0110 0000 0101 0111 */
1653		void upd7810_device::ADC_L_A()
1654		{
1655		UINT8 tmp = L + A + (PSW & CY);
1656		ZHC_ADD( tmp, L, (PSW & CY) );
1657		L = tmp;
1658		}
1659
1660		/* 60 60: 0110 0000 0110 0000 */
1661		void upd7810_device::SUB_V_A()
1662		{
1663		UINT8 tmp = V - A;
1664		ZHC_SUB( tmp, V, 0 );
1665		V = tmp;
1666		}
1667
1668		/* 60 61: 0110 0000 0110 0001 */
1669		void upd7810_device::SUB_A_A()
1670		{
1671		UINT8 tmp = A - A;
1672		ZHC_SUB( tmp, A, 0 );
1673		A = tmp;
1674		}
1675
1676		/* 60 62: 0110 0000 0110 0010 */
1677		void upd7810_device::SUB_B_A()
1678		{
1679		UINT8 tmp = B - A;
1680		ZHC_SUB( tmp, B, 0 );
1681		B = tmp;
1682		}
1683
1684		/* 60 63: 0110 0000 0110 0011 */
1685		void upd7810_device::SUB_C_A()
1686		{
1687		UINT8 tmp = C - A;
1688		ZHC_SUB( tmp, C, 0 );
1689		C = tmp;
1690		}
1691
1692		/* 60 64: 0110 0000 0110 0100 */
1693		void upd7810_device::SUB_D_A()
1694		{
1695		UINT8 tmp = D - A;
1696		ZHC_SUB( tmp, D, 0 );
1697		D = tmp;
1698		}
1699
1700		/* 60 65: 0110 0000 0110 0101 */
1701		void upd7810_device::SUB_E_A()
1702		{
1703		UINT8 tmp = E - A;
1704		ZHC_SUB( tmp, E, 0 );
1705		E = tmp;
1706		}
1707
1708		/* 60 66: 0110 0000 0110 0110 */
1709		void upd7810_device::SUB_H_A()
1710		{
1711		UINT8 tmp = H - A;
1712		ZHC_SUB( tmp, H, 0 );
1713		H = tmp;
1714		}
1715
1716		/* 60 67: 0110 0000 0110 0111 */
1717		void upd7810_device::SUB_L_A()
1718		{
1719		UINT8 tmp = L - A;
1720		ZHC_SUB( tmp, L, 0 );
1721		L = tmp;
1722		}
1723
1724		/* 60 68: 0110 0000 0110 1000 */
1725		void upd7810_device::NEA_V_A()
1726		{
1727		UINT8 tmp = V - A;
1728		ZHC_SUB( tmp, V, 0 );
1729		SKIP_NZ;
1730		}
1731
1732		/* 60 69: 0110 0000 0110 1001 */
1733		void upd7810_device::NEA_A_A()
1734		{
1735		UINT8 tmp = A - A;
1736		ZHC_SUB( tmp, A, 0 );
1737		SKIP_NZ;
1738		}
1739
1740		/* 60 6a: 0110 0000 0110 1010 */
1741		void upd7810_device::NEA_B_A()
1742		{
1743		UINT8 tmp = B - A;
1744		ZHC_SUB( tmp, B, 0 );
1745		SKIP_NZ;
1746		}
1747
1748		/* 60 6b: 0110 0000 0110 1011 */
1749		void upd7810_device::NEA_C_A()
1750		{
1751		UINT8 tmp = C - A;
1752		ZHC_SUB( tmp, C, 0 );
1753		SKIP_NZ;
1754		}
1755
1756		/* 60 6c: 0110 0000 0110 1100 */
1757		void upd7810_device::NEA_D_A()
1758		{
1759		UINT8 tmp = D - A;
1760		ZHC_SUB( tmp, D, 0 );
1761		SKIP_NZ;
1762		}
1763
1764		/* 60 6d: 0110 0000 0110 1101 */
1765		void upd7810_device::NEA_E_A()
1766		{
1767		UINT8 tmp = E - A;
1768		ZHC_SUB( tmp, E, 0 );
1769		SKIP_NZ;
1770		}
1771
1772		/* 60 6e: 0110 0000 0110 1110 */
1773		void upd7810_device::NEA_H_A()
1774		{
1775		UINT8 tmp = H - A;
1776		ZHC_SUB( tmp, H, 0 );
1777		SKIP_NZ;
1778		}
1779
1780		/* 60 6f: 0110 0000 0110 1111 */
1781		void upd7810_device::NEA_L_A()
1782		{
1783		UINT8 tmp = L - A;
1784		ZHC_SUB( tmp, L, 0 );
1785		SKIP_NZ;
1786		}
1787
1788		/* 60 70: 0110 0000 0111 0000 */
1789		void upd7810_device::SBB_V_A()
1790		{
1791		UINT8 tmp = V - A - (PSW & CY);
1792		ZHC_SUB( tmp, V, (PSW & CY) );
1793		V = tmp;
1794		}
1795
1796		/* 60 71: 0110 0000 0111 0001 */
1797		void upd7810_device::SBB_A_A()
1798		{
1799		UINT8 tmp = A - A - (PSW & CY);
1800		ZHC_SUB( tmp, A, (PSW & CY) );
1801		A = tmp;
1802		}
1803
1804		/* 60 72: 0110 0000 0111 0010 */
1805		void upd7810_device::SBB_B_A()
1806		{
1807		UINT8 tmp = B - A - (PSW & CY);
1808		ZHC_SUB( tmp, B, (PSW & CY) );
1809		B = tmp;
1810		}
1811
1812		/* 60 73: 0110 0000 0111 0011 */
1813		void upd7810_device::SBB_C_A()
1814		{
1815		UINT8 tmp = C - A - (PSW & CY);
1816		ZHC_SUB( tmp, C, (PSW & CY) );
1817		C = tmp;
1818		}
1819
1820		/* 60 74: 0110 0000 0111 0100 */
1821		void upd7810_device::SBB_D_A()
1822		{
1823		UINT8 tmp = D - A - (PSW & CY);
1824		ZHC_SUB( tmp, D, (PSW & CY) );
1825		D = tmp;
1826		}
1827
1828		/* 60 75: 0110 0000 0111 0101 */
1829		void upd7810_device::SBB_E_A()
1830		{
1831		UINT8 tmp = E - A - (PSW & CY);
1832		ZHC_SUB( tmp, E, (PSW & CY) );
1833		E = tmp;
1834		}
1835
1836		/* 60 76: 0110 0000 0111 0110 */
1837		void upd7810_device::SBB_H_A()
1838		{
1839		UINT8 tmp = H - A - (PSW & CY);
1840		ZHC_SUB( tmp, H, (PSW & CY) );
1841		H = tmp;
1842		}
1843
1844		/* 60 77: 0110 0000 0111 0111 */
1845		void upd7810_device::SBB_L_A()
1846		{
1847		UINT8 tmp = L - A - (PSW & CY);
1848		ZHC_SUB( tmp, L, (PSW & CY) );
1849		L = tmp;
1850		}
1851
1852		/* 60 78: 0110 0000 0111 1000 */
1853		void upd7810_device::EQA_V_A()
1854		{
1855		UINT8 tmp = V - A;
1856		ZHC_SUB( tmp, V, 0 );
1857		SKIP_Z;
1858		}
1859
1860		/* 60 79: 0110 0000 0111 1001 */
1861		void upd7810_device::EQA_A_A()
1862		{
1863		UINT8 tmp = A - A;
1864		ZHC_SUB( tmp, A, 0 );
1865		SKIP_Z;
1866		}
1867
1868		/* 60 7a: 0110 0000 0111 1010 */
1869		void upd7810_device::EQA_B_A()
1870		{
1871		UINT8 tmp = B - A;
1872		ZHC_SUB( tmp, B, 0 );
1873		SKIP_Z;
1874		}
1875
1876		/* 60 7b: 0110 0000 0111 1011 */
1877		void upd7810_device::EQA_C_A()
1878		{
1879		UINT8 tmp = C - A;
1880		ZHC_SUB( tmp, C, 0 );
1881		SKIP_Z;
1882		}
1883
1884		/* 60 7c: 0110 0000 0111 1100 */
1885		void upd7810_device::EQA_D_A()
1886		{
1887		UINT8 tmp = D - A;
1888		ZHC_SUB( tmp, D, 0 );
1889		SKIP_Z;
1890		}
1891
1892		/* 60 7d: 0110 0000 0111 1101 */
1893		void upd7810_device::EQA_E_A()
1894		{
1895		UINT8 tmp = E - A;
1896		ZHC_SUB( tmp, E, 0 );
1897		SKIP_Z;
1898		}
1899
1900		/* 60 7e: 0110 0000 0111 1110 */
1901		void upd7810_device::EQA_H_A()
1902		{
1903		UINT8 tmp = H - A;
1904		ZHC_SUB( tmp, H, 0 );
1905		SKIP_Z;
1906		}
1907
1908		/* 60 7f: 0110 0000 0111 1111 */
1909		void upd7810_device::EQA_L_A()
1910		{
1911		UINT8 tmp = L - A;
1912		ZHC_SUB( tmp, L, 0 );
1913		SKIP_Z;
1914		}
1915
1916		/* 60 88: 0110 0000 1000 1000 */
1917		void upd7810_device::ANA_A_V()
1918		{
1919		A &= V;
1920		SET_Z(A);
1921		}
1922
1923		/* 60 89: 0110 0000 1000 1001 */
1924		/* ANA_A_A already defined */
1925
1926		/* 60 8a: 0110 0000 1000 1010 */
1927		void upd7810_device::ANA_A_B()
1928		{
1929		A &= B;
1930		SET_Z(A);
1931		}
1932
1933		/* 60 8b: 0110 0000 1000 1011 */
1934		void upd7810_device::ANA_A_C()
1935		{
1936		A &= C;
1937		SET_Z(A);
1938		}
1939
1940		/* 60 8c: 0110 0000 1000 1100 */
1941		void upd7810_device::ANA_A_D()
1942		{
1943		A &= D;
1944		SET_Z(A);
1945		}
1946
1947		/* 60 8d: 0110 0000 1000 1101 */
1948		void upd7810_device::ANA_A_E()
1949		{
1950		A &= E;
1951		SET_Z(A);
1952		}
1953
1954		/* 60 8e: 0110 0000 1000 1110 */
1955		void upd7810_device::ANA_A_H()
1956		{
1957		A &= H;
1958		SET_Z(A);
1959		}
1960
1961		/* 60 8f: 0110 0000 1000 1111 */
1962		void upd7810_device::ANA_A_L()
1963		{
1964		A &= L;
1965		SET_Z(A);
1966		}
1967
1968		/* 60 90: 0110 0000 1001 0000 */
1969		void upd7810_device::XRA_A_V()
1970		{
1971		A ^= V;
1972		SET_Z(A);
1973		}
1974
1975		/* 60 91: 0110 0000 1001 0001 */
1976		/* XRA_A_A already defined */
1977
1978		/* 60 92: 0110 0000 1001 0010 */
1979		void upd7810_device::XRA_A_B()
1980		{
1981		A ^= B;
1982		SET_Z(A);
1983		}
1984
1985		/* 60 93: 0110 0000 1001 0011 */
1986		void upd7810_device::XRA_A_C()
1987		{
1988		A ^= C;
1989		SET_Z(A);
1990		}
1991
1992		/* 60 94: 0110 0000 1001 0100 */
1993		void upd7810_device::XRA_A_D()
1994		{
1995		A ^= D;
1996		SET_Z(A);
1997		}
1998
1999		/* 60 95: 0110 0000 1001 0101 */
2000		void upd7810_device::XRA_A_E()
2001		{
2002		A ^= E;
2003		SET_Z(A);
2004		}
2005
2006		/* 60 96: 0110 0000 1001 0110 */
2007		void upd7810_device::XRA_A_H()
2008		{
2009		A ^= H;
2010		SET_Z(A);
2011		}
2012
2013		/* 60 97: 0110 0000 1001 0111 */
2014		void upd7810_device::XRA_A_L()
2015		{
2016		A ^= L;
2017		SET_Z(A);
2018		}
2019
2020		/* 60 98: 0110 0000 1001 1000 */
2021		void upd7810_device::ORA_A_V()
2022		{
2023		A \|= V;
2024		SET_Z(A);
2025		}
2026
2027		/* 60 99: 0110 0000 1001 1001 */
2028		/* ORA_A_A already defined */
2029
2030		/* 60 9a: 0110 0000 1001 1010 */
2031		void upd7810_device::ORA_A_B()
2032		{
2033		A \|= B;
2034		SET_Z(A);
2035		}
2036
2037		/* 60 9b: 0110 0000 1001 1011 */
2038		void upd7810_device::ORA_A_C()
2039		{
2040		A \|= C;
2041		SET_Z(A);
2042		}
2043
2044		/* 60 9c: 0110 0000 1001 1100 */
2045		void upd7810_device::ORA_A_D()
2046		{
2047		A \|= D;
2048		SET_Z(A);
2049		}
2050
2051		/* 60 9d: 0110 0000 1001 1101 */
2052		void upd7810_device::ORA_A_E()
2053		{
2054		A \|= E;
2055		SET_Z(A);
2056		}
2057
2058		/* 60 9e: 0110 0000 1001 1110 */
2059		void upd7810_device::ORA_A_H()
2060		{
2061		A \|= H;
2062		SET_Z(A);
2063		}
2064
2065		/* 60 9f: 0110 0000 1001 1111 */
2066		void upd7810_device::ORA_A_L()
2067		{
2068		A \|= L;
2069		SET_Z(A);
2070		}
2071
2072		/* 60 a0: 0110 0000 1010 0000 */
2073		void upd7810_device::ADDNC_A_V()
2074		{
2075		UINT8 tmp = A + V;
2076		ZHC_ADD( tmp, A, 0 );
2077		A = tmp;
2078		SKIP_NC;
2079		}
2080
2081		/* 60 a1: 0110 0000 1010 0001 */
2082		/* ADDNC_A_A already defined */
2083
2084		/* 60 a2: 0110 0000 1010 0010 */
2085		void upd7810_device::ADDNC_A_B()
2086		{
2087		UINT8 tmp = A + B;
2088		ZHC_ADD( tmp, A, 0 );
2089		A = tmp;
2090		SKIP_NC;
2091		}
2092
2093		/* 60 a3: 0110 0000 1010 0011 */
2094		void upd7810_device::ADDNC_A_C()
2095		{
2096		UINT8 tmp = A + C;
2097		ZHC_ADD( tmp, A, 0 );
2098		A = tmp;
2099		SKIP_NC;
2100		}
2101
2102		/* 60 a4: 0110 0000 1010 0100 */
2103		void upd7810_device::ADDNC_A_D()
2104		{
2105		UINT8 tmp = A + D;
2106		ZHC_ADD( tmp, A, 0 );
2107		A = tmp;
2108		SKIP_NC;
2109		}
2110
2111		/* 60 a5: 0110 0000 1010 0101 */
2112		void upd7810_device::ADDNC_A_E()
2113		{
2114		UINT8 tmp = A + E;
2115		ZHC_ADD( tmp, A, 0 );
2116		A = tmp;
2117		SKIP_NC;
2118		}
2119
2120		/* 60 a6: 0110 0000 1010 0110 */
2121		void upd7810_device::ADDNC_A_H()
2122		{
2123		UINT8 tmp = A + H;
2124		ZHC_ADD( tmp, A, 0 );
2125		A = tmp;
2126		SKIP_NC;
2127		}
2128
2129		/* 60 a7: 0110 0000 1010 0111 */
2130		void upd7810_device::ADDNC_A_L()
2131		{
2132		UINT8 tmp = A + L;
2133		ZHC_ADD( tmp, A, 0 );
2134		A = tmp;
2135		SKIP_NC;
2136		}
2137
2138		/* 60 a8: 0110 0000 1010 1000 */
2139		void upd7810_device::GTA_A_V()
2140		{
2141		UINT16 tmp = A - V - 1;
2142		ZHC_SUB( tmp, A, 0 );
2143		SKIP_NC;
2144		}
2145
2146		/* 60 a9: 0110 0000 1010 1001 */
2147		/* GTA_A_A already defined */
2148
2149		/* 60 aa: 0110 0000 1010 1010 */
2150		void upd7810_device::GTA_A_B()
2151		{
2152		UINT16 tmp = A - B - 1;
2153		ZHC_SUB( tmp, A, 0 );
2154		SKIP_NC;
2155		}
2156
2157		/* 60 ab: 0110 0000 1010 1011 */
2158		void upd7810_device::GTA_A_C()
2159		{
2160		UINT16 tmp = A - C - 1;
2161		ZHC_SUB( tmp, A, 0 );
2162		SKIP_NC;
2163		}
2164
2165		/* 60 ac: 0110 0000 1010 1100 */
2166		void upd7810_device::GTA_A_D()
2167		{
2168		UINT16 tmp = A - D - 1;
2169		ZHC_SUB( tmp, A, 0 );
2170		SKIP_NC;
2171		}
2172
2173		/* 60 ad: 0110 0000 1010 1101 */
2174		void upd7810_device::GTA_A_E()
2175		{
2176		UINT16 tmp = A - E - 1;
2177		ZHC_SUB( tmp, A, 0 );
2178		SKIP_NC;
2179		}
2180
2181		/* 60 ae: 0110 0000 1010 1110 */
2182		void upd7810_device::GTA_A_H()
2183		{
2184		UINT16 tmp = A - H - 1;
2185		ZHC_SUB( tmp, A, 0 );
2186		SKIP_NC;
2187		}
2188
2189		/* 60 af: 0110 0000 1010 1111 */
2190		void upd7810_device::GTA_A_L()
2191		{
2192		UINT16 tmp = A - L - 1;
2193		ZHC_SUB( tmp, A, 0 );
2194		SKIP_NC;
2195		}
2196
2197		/* 60 b0: 0110 0000 1011 0000 */
2198		void upd7810_device::SUBNB_A_V()
2199		{
2200		UINT8 tmp = A - V;
2201		ZHC_SUB( tmp, A, 0 );
2202		A = tmp;
2203		SKIP_NC;
2204		}
2205
2206		/* 60 b1: 0110 0000 1011 0001 */
2207		/* SUBNB_A_A already defined */
2208
2209		/* 60 b2: 0110 0000 1011 0010 */
2210		void upd7810_device::SUBNB_A_B()
2211		{
2212		UINT8 tmp = A - B;
2213		ZHC_SUB( tmp, A, 0 );
2214		A = tmp;
2215		SKIP_NC;
2216		}
2217
2218		/* 60 b3: 0110 0000 1011 0011 */
2219		void upd7810_device::SUBNB_A_C()
2220		{
2221		UINT8 tmp = A - C;
2222		ZHC_SUB( tmp, A, 0 );
2223		A = tmp;
2224		SKIP_NC;
2225		}
2226
2227		/* 60 b4: 0110 0000 1011 0100 */
2228		void upd7810_device::SUBNB_A_D()
2229		{
2230		UINT8 tmp = A - D;
2231		ZHC_SUB( tmp, A, 0 );
2232		A = tmp;
2233		SKIP_NC;
2234		}
2235
2236		/* 60 b5: 0110 0000 1011 0101 */
2237		void upd7810_device::SUBNB_A_E()
2238		{
2239		UINT8 tmp = A - E;
2240		ZHC_SUB( tmp, A, 0 );
2241		A = tmp;
2242		SKIP_NC;
2243		}
2244
2245		/* 60 b6: 0110 0000 1011 0110 */
2246		void upd7810_device::SUBNB_A_H()
2247		{
2248		UINT8 tmp = A - H;
2249		ZHC_SUB( tmp, A, 0 );
2250		A = tmp;
2251		SKIP_NC;
2252		}
2253
2254		/* 60 b7: 0110 0000 1011 0111 */
2255		void upd7810_device::SUBNB_A_L()
2256		{
2257		UINT8 tmp = A - L;
2258		ZHC_SUB( tmp, A, 0 );
2259		A = tmp;
2260		SKIP_NC;
2261		}
2262
2263		/* 60 b8: 0110 0000 1011 1000 */
2264		void upd7810_device::LTA_A_V()
2265		{
2266		UINT8 tmp = A - V;
2267		ZHC_SUB( tmp, A, 0 );
2268		SKIP_CY;
2269		}
2270
2271		/* 60 b9: 0110 0000 1011 1001 */
2272		/* LTA_A_A already defined */
2273
2274		/* 60 ba: 0110 0000 1011 1010 */
2275		void upd7810_device::LTA_A_B()
2276		{
2277		UINT8 tmp = A - B;
2278		ZHC_SUB( tmp, A, 0 );
2279		SKIP_CY;
2280		}
2281
2282		/* 60 bb: 0110 0000 1011 1011 */
2283		void upd7810_device::LTA_A_C()
2284		{
2285		UINT8 tmp = A - C;
2286		ZHC_SUB( tmp, A, 0 );
2287		SKIP_CY;
2288		}
2289
2290		/* 60 bc: 0110 0000 1011 1100 */
2291		void upd7810_device::LTA_A_D()
2292		{
2293		UINT8 tmp = A - D;
2294		ZHC_SUB( tmp, A, 0 );
2295		SKIP_CY;
2296		}
2297
2298		/* 60 bd: 0110 0000 1011 1101 */
2299		void upd7810_device::LTA_A_E()
2300		{
2301		UINT8 tmp = A - E;
2302		ZHC_SUB( tmp, A, 0 );
2303		SKIP_CY;
2304		}
2305
2306		/* 60 be: 0110 0000 1011 1110 */
2307		void upd7810_device::LTA_A_H()
2308		{
2309		UINT8 tmp = A - H;
2310		ZHC_SUB( tmp, A, 0 );
2311		SKIP_CY;
2312		}
2313
2314		/* 60 bf: 0110 0000 1011 1111 */
2315		void upd7810_device::LTA_A_L()
2316		{
2317		UINT8 tmp = A - L;
2318		ZHC_SUB( tmp, A, 0 );
2319		SKIP_CY;
2320		}
2321
2322		/* 60 c0: 0110 0000 1100 0000 */
2323		void upd7810_device::ADD_A_V()
2324		{
2325		UINT8 tmp = A + V;
2326		ZHC_ADD( tmp, A, 0 );
2327		A = tmp;
2328		}
2329
2330		/* 60 c1: 0110 0000 1100 0001 */
2331		/* ADD_A_A already defined */
2332
2333		/* 60 c2: 0110 0000 1100 0010 */
2334		void upd7810_device::ADD_A_B()
2335		{
2336		UINT8 tmp = A + B;
2337		ZHC_ADD( tmp, A, 0 );
2338		A = tmp;
2339		}
2340
2341		/* 60 c3: 0110 0000 1100 0011 */
2342		void upd7810_device::ADD_A_C()
2343		{
2344		UINT8 tmp = A + C;
2345		ZHC_ADD( tmp, A, 0 );
2346		A = tmp;
2347		}
2348
2349		/* 60 c4: 0110 0000 1100 0100 */
2350		void upd7810_device::ADD_A_D()
2351		{
2352		UINT8 tmp = A + D;
2353		ZHC_ADD( tmp, A, 0 );
2354		A = tmp;
2355		}
2356
2357		/* 60 c5: 0110 0000 1100 0101 */
2358		void upd7810_device::ADD_A_E()
2359		{
2360		UINT8 tmp = A + E;
2361		ZHC_ADD( tmp, A, 0 );
2362		A = tmp;
2363		}
2364
2365		/* 60 c6: 0110 0000 1100 0110 */
2366		void upd7810_device::ADD_A_H()
2367		{
2368		UINT8 tmp = A + H;
2369		ZHC_ADD( tmp, A, 0 );
2370		A = tmp;
2371		}
2372
2373		/* 60 c7: 0110 0000 1100 0111 */
2374		void upd7810_device::ADD_A_L()
2375		{
2376		UINT8 tmp = A + L;
2377		ZHC_ADD( tmp, A, 0 );
2378		A = tmp;
2379		}
2380
2381		/* 60 c8: 0110 0000 1100 1000 */
2382		void upd7810_device::ONA_A_V()
2383		{
2384		if (A & V)
2385		PSW = (PSW & ~Z) \| SK;
2386		else
2387		PSW \|= Z;
2388		}
2389
2390		/* 60 c9: 0110 0000 1100 1001 */
2391		void upd7810_device::ONA_A_A()
2392		{
2393		if (A & A)
2394		PSW = (PSW & ~Z) \| SK;
2395		else
2396		PSW \|= Z;
2397		}
2398
2399		/* 60 ca: 0110 0000 1100 1010 */
2400		void upd7810_device::ONA_A_B()
2401		{
2402		if (A & B)
2403		PSW = (PSW & ~Z) \| SK;
2404		else
2405		PSW \|= Z;
2406		}
2407
2408		/* 60 cb: 0110 0000 1100 1011 */
2409		void upd7810_device::ONA_A_C()
2410		{
2411		if (A & C)
2412		PSW = (PSW & ~Z) \| SK;
2413		else
2414		PSW \|= Z;
2415		}
2416
2417		/* 60 cc: 0110 0000 1100 1100 */
2418		void upd7810_device::ONA_A_D()
2419		{
2420		if (A & D)
2421		PSW = (PSW & ~Z) \| SK;
2422		else
2423		PSW \|= Z;
2424		}
2425
2426		/* 60 cd: 0110 0000 1100 1101 */
2427		void upd7810_device::ONA_A_E()
2428		{
2429		if (A & E)
2430		PSW = (PSW & ~Z) \| SK;
2431		else
2432		PSW \|= Z;
2433		}
2434
2435		/* 60 ce: 0110 0000 1100 1110 */
2436		void upd7810_device::ONA_A_H()
2437		{
2438		if (A & H)
2439		PSW = (PSW & ~Z) \| SK;
2440		else
2441		PSW \|= Z;
2442		}
2443
2444		/* 60 cf: 0110 0000 1100 1111 */
2445		void upd7810_device::ONA_A_L()
2446		{
2447		if (A & L)
2448		PSW = (PSW & ~Z) \| SK;
2449		else
2450		PSW \|= Z;
2451		}
2452
2453		/* 60 d0: 0110 0000 1101 0000 */
2454		void upd7810_device::ADC_A_V()
2455		{
2456		UINT8 tmp = A + V + (PSW & CY);
2457		ZHC_ADD( tmp, A, (PSW & CY) );
2458		A = tmp;
2459		}
2460
2461		/* 60 d1: 0110 0000 1101 0001 */
2462		/* ADC_A_A already defined */
2463
2464		/* 60 d2: 0110 0000 1101 0010 */
2465		void upd7810_device::ADC_A_B()
2466		{
2467		UINT8 tmp = A + B + (PSW & CY);
2468		ZHC_ADD( tmp, A, (PSW & CY) );
2469		A = tmp;
2470		}
2471
2472		/* 60 d3: 0110 0000 1101 0011 */
2473		void upd7810_device::ADC_A_C()
2474		{
2475		UINT8 tmp = A + C + (PSW & CY);
2476		ZHC_ADD( tmp, A, (PSW & CY) );
2477		A = tmp;
2478		}
2479
2480		/* 60 d4: 0110 0000 1101 0100 */
2481		void upd7810_device::ADC_A_D()
2482		{
2483		UINT8 tmp = A + D + (PSW & CY);
2484		ZHC_ADD( tmp, A, (PSW & CY) );
2485		A = tmp;
2486		}
2487
2488		/* 60 d5: 0110 0000 1101 0101 */
2489		void upd7810_device::ADC_A_E()
2490		{
2491		UINT8 tmp = A + E + (PSW & CY);
2492		ZHC_ADD( tmp, A, (PSW & CY) );
2493		A = tmp;
2494		}
2495
2496		/* 60 d6: 0110 0000 1101 0110 */
2497		void upd7810_device::ADC_A_H()
2498		{
2499		UINT8 tmp = A + H + (PSW & CY);
2500		ZHC_ADD( tmp, A, (PSW & CY) );
2501		A = tmp;
2502		}
2503
2504		/* 60 d7: 0110 0000 1101 0111 */
2505		void upd7810_device::ADC_A_L()
2506		{
2507		UINT8 tmp = A + L + (PSW & CY);
2508		ZHC_ADD( tmp, A, (PSW & CY) );
2509		A = tmp;
2510		}
2511
2512		/* 60 d8: 0110 0000 1101 1000 */
2513		void upd7810_device::OFFA_A_V()
2514		{
2515		if ( A & V )
2516		PSW &= ~Z;
2517		else
2518		PSW = PSW \| Z \| SK;
2519		}
2520
2521		/* 60 d9: 0110 0000 1101 1001 */
2522		void upd7810_device::OFFA_A_A()
2523		{
2524		if ( A & A )
2525		PSW &= ~Z;
2526		else
2527		PSW = PSW \| Z \| SK;
2528		}
2529
2530		/* 60 da: 0110 0000 1101 1010 */
2531		void upd7810_device::OFFA_A_B()
2532		{
2533		if ( A & B )
2534		PSW &= ~Z;
2535		else
2536		PSW = PSW \| Z \| SK;
2537		}
2538
2539		/* 60 db: 0110 0000 1101 1011 */
2540		void upd7810_device::OFFA_A_C()
2541		{
2542		if ( A & C )
2543		PSW &= ~Z;
2544		else
2545		PSW = PSW \| Z \| SK;
2546		}
2547
2548		/* 60 dc: 0110 0000 1101 1100 */
2549		void upd7810_device::OFFA_A_D()
2550		{
2551		if ( A & D )
2552		PSW &= ~Z;
2553		else
2554		PSW = PSW \| Z \| SK;
2555		}
2556
2557		/* 60 dd: 0110 0000 1101 1101 */
2558		void upd7810_device::OFFA_A_E()
2559		{
2560		if ( A & E )
2561		PSW &= ~Z;
2562		else
2563		PSW = PSW \| Z \| SK;
2564		}
2565
2566		/* 60 de: 0110 0000 1101 1110 */
2567		void upd7810_device::OFFA_A_H()
2568		{
2569		if ( A & H )
2570		PSW &= ~Z;
2571		else
2572		PSW = PSW \| Z \| SK;
2573		}
2574
2575		/* 60 df: 0110 0000 1101 1111 */
2576		void upd7810_device::OFFA_A_L()
2577		{
2578		if ( A & L )
2579		PSW &= ~Z;
2580		else
2581		PSW = PSW \| Z \| SK;
2582		}
2583
2584		/* 60 e0: 0110 0000 1110 0000 */
2585		void upd7810_device::SUB_A_V()
2586		{
2587		UINT8 tmp = A - V;
2588		ZHC_SUB( tmp, A, 0 );
2589		A = tmp;
2590		}
2591
2592		/* 60 e1: 0110 0000 1110 0001 */
2593		/* SUB_A_A already defined */
2594
2595		/* 60 e2: 0110 0000 1110 0010 */
2596		void upd7810_device::SUB_A_B()
2597		{
2598		UINT8 tmp = A - B;
2599		ZHC_SUB( tmp, A, 0 );
2600		A = tmp;
2601		}
2602
2603		/* 60 e3: 0110 0000 1110 0011 */
2604		void upd7810_device::SUB_A_C()
2605		{
2606		UINT8 tmp = A - C;
2607		ZHC_SUB( tmp, A, 0 );
2608		A = tmp;
2609		}
2610
2611		/* 60 e4: 0110 0000 1110 0100 */
2612		void upd7810_device::SUB_A_D()
2613		{
2614		UINT8 tmp = A - D;
2615		ZHC_SUB( tmp, A, 0 );
2616		A = tmp;
2617		}
2618
2619		/* 60 e5: 0110 0000 1110 0101 */
2620		void upd7810_device::SUB_A_E()
2621		{
2622		UINT8 tmp = A - E;
2623		ZHC_SUB( tmp, A, 0 );
2624		A = tmp;
2625		}
2626
2627		/* 60 e6: 0110 0000 1110 0110 */
2628		void upd7810_device::SUB_A_H()
2629		{
2630		UINT8 tmp = A - H;
2631		ZHC_SUB( tmp, A, 0 );
2632		A = tmp;
2633		}
2634
2635		/* 60 e7: 0110 0000 1110 0111 */
2636		void upd7810_device::SUB_A_L()
2637		{
2638		UINT8 tmp = A - L;
2639		ZHC_SUB( tmp, A, 0 );
2640		A = tmp;
2641		}
2642
2643		/* 60 e8: 0110 0000 1110 1000 */
2644		void upd7810_device::NEA_A_V()
2645		{
2646		UINT8 tmp = A - V;
2647		ZHC_SUB( tmp, A, 0 );
2648		SKIP_NZ;
2649		}
2650
2651		/* 60 e9: 0110 0000 1110 1001 */
2652		/* NEA_A_A already defined */
2653
2654		/* 60 ea: 0110 0000 1110 1010 */
2655		void upd7810_device::NEA_A_B()
2656		{
2657		UINT8 tmp = A - B;
2658		ZHC_SUB( tmp, A, 0 );
2659		SKIP_NZ;
2660		}
2661
2662		/* 60 eb: 0110 0000 1110 1011 */
2663		void upd7810_device::NEA_A_C()
2664		{
2665		UINT8 tmp = A - C;
2666		ZHC_SUB( tmp, A, 0 );
2667		SKIP_NZ;
2668		}
2669
2670		/* 60 ec: 0110 0000 1110 1100 */
2671		void upd7810_device::NEA_A_D()
2672		{
2673		UINT8 tmp = A - D;
2674		ZHC_SUB( tmp, A, 0 );
2675		SKIP_NZ;
2676		}
2677
2678		/* 60 ed: 0110 0000 1110 1101 */
2679		void upd7810_device::NEA_A_E()
2680		{
2681		UINT8 tmp = A - E;
2682		ZHC_SUB( tmp, A, 0 );
2683		SKIP_NZ;
2684		}
2685
2686		/* 60 ee: 0110 0000 1110 1110 */
2687		void upd7810_device::NEA_A_H()
2688		{
2689		UINT8 tmp = A - H;
2690		ZHC_SUB( tmp, A, 0 );
2691		SKIP_NZ;
2692		}
2693
2694		/* 60 ef: 0110 0000 1110 1111 */
2695		void upd7810_device::NEA_A_L()
2696		{
2697		UINT8 tmp = A - L;
2698		ZHC_SUB( tmp, A, 0 );
2699		SKIP_NZ;
2700		}
2701
2702		/* 60 f0: 0110 0000 1111 0000 */
2703		void upd7810_device::SBB_A_V()
2704		{
2705		UINT8 tmp = A - V - (PSW & CY);
2706		ZHC_SUB( tmp, A, (PSW & CY) );
2707		A = tmp;
2708		}
2709
2710		/* 60 f1: 0110 0000 1111 0001 */
2711		/* SBB_A_A already defined */
2712
2713		/* 60 f2: 0110 0000 1111 0010 */
2714		void upd7810_device::SBB_A_B()
2715		{
2716		UINT8 tmp = A - B - (PSW & CY);
2717		ZHC_SUB( tmp, A, (PSW & CY) );
2718		A = tmp;
2719		}
2720
2721		/* 60 f3: 0110 0000 1111 0011 */
2722		void upd7810_device::SBB_A_C()
2723		{
2724		UINT8 tmp = A - C - (PSW & CY);
2725		ZHC_SUB( tmp, A, (PSW & CY) );
2726		A = tmp;
2727		}
2728
2729		/* 60 f4: 0110 0000 1111 0100 */
2730		void upd7810_device::SBB_A_D()
2731		{
2732		UINT8 tmp = A - D - (PSW & CY);
2733		ZHC_SUB( tmp, A, (PSW & CY) );
2734		A = tmp;
2735		}
2736
2737		/* 60 f5: 0110 0000 1111 0101 */
2738		void upd7810_device::SBB_A_E()
2739		{
2740		UINT8 tmp = A - E - (PSW & CY);
2741		ZHC_SUB( tmp, A, (PSW & CY) );
2742		A = tmp;
2743		}
2744
2745		/* 60 f6: 0110 0000 1111 0110 */
2746		void upd7810_device::SBB_A_H()
2747		{
2748		UINT8 tmp = A - H - (PSW & CY);
2749		ZHC_SUB( tmp, A, (PSW & CY) );
2750		A = tmp;
2751		}
2752
2753		/* 60 f7: 0110 0000 1111 0111 */
2754		void upd7810_device::SBB_A_L()
2755		{
2756		UINT8 tmp = A - L - (PSW & CY);
2757		ZHC_SUB( tmp, A, (PSW & CY) );
2758		A = tmp;
2759		}
2760
2761		/* 60 f8: 0110 0000 1111 1000 */
2762		void upd7810_device::EQA_A_V()
2763		{
2764		UINT8 tmp = A - V;
2765		ZHC_SUB( tmp, A, 0 );
2766		SKIP_Z;
2767		}
2768
2769		/* 60 f9: 0110 0000 1111 1001 */
2770		/* EQA_A_A already defined */
2771
2772		/* 60 fa: 0110 0000 1111 1010 */
2773		void upd7810_device::EQA_A_B()
2774		{
2775		UINT8 tmp = A - B;
2776		ZHC_SUB( tmp, A, 0 );
2777		SKIP_Z;
2778		}
2779
2780		/* 60 fb: 0110 0000 1111 1011 */
2781		void upd7810_device::EQA_A_C()
2782		{
2783		UINT8 tmp = A - C;
2784		ZHC_SUB( tmp, A, 0 );
2785		SKIP_Z;
2786		}
2787
2788		/* 60 fc: 0110 0000 1111 1100 */
2789		void upd7810_device::EQA_A_D()
2790		{
2791		UINT8 tmp = A - D;
2792		ZHC_SUB( tmp, A, 0 );
2793		SKIP_Z;
2794		}
2795
2796		/* 60 fd: 0110 0000 1111 1101 */
2797		void upd7810_device::EQA_A_E()
2798		{
2799		UINT8 tmp = A - E;
2800		ZHC_SUB( tmp, A, 0 );
2801		SKIP_Z;
2802		}
2803
2804		/* 60 fe: 0110 0000 1111 1110 */
2805		void upd7810_device::EQA_A_H()
2806		{
2807		UINT8 tmp = A - H;
2808		ZHC_SUB( tmp, A, 0 );
2809		SKIP_Z;
2810		}
2811
2812		/* 60 ff: 0110 0000 1111 1111 */
2813		void upd7810_device::EQA_A_L()
2814		{
2815		UINT8 tmp = A - L;
2816		ZHC_SUB( tmp, A, 0 );
2817		SKIP_Z;
2818		}
2819
2820		/* prefix 64 */
2821		/* 64 00: 0110 0100 0000 0000 xxxx xxxx */
2822		void upd7810_device::MVI_PA_xx()
2823		{
2824		UINT8 imm;
2825		RDOPARG( imm );
2826		WP( UPD7810_PORTA, imm );
2827		}
2828
2829		/* 64 01: 0110 0100 0000 0001 xxxx xxxx */
2830		void upd7810_device::MVI_PB_xx()
2831		{
2832		UINT8 imm;
2833		RDOPARG( imm );
2834		WP( UPD7810_PORTB, imm );
2835		}
2836
2837		/* 64 02: 0110 0100 0000 0010 xxxx xxxx */
2838		void upd7810_device::MVI_PC_xx()
2839		{
2840		UINT8 imm;
2841		RDOPARG( imm );
2842		WP( UPD7810_PORTC, imm );
2843		}
2844
2845		/* 64 03: 0110 0100 0000 0011 xxxx xxxx */
2846		void upd7810_device::MVI_PD_xx()
2847		{
2848		UINT8 imm;
2849		RDOPARG( imm );
2850		WP( UPD7810_PORTD, imm );
2851		}
2852
2853		/* 64 05: 0110 0100 0000 0101 xxxx xxxx */
2854		void upd7810_device::MVI_PF_xx()
2855		{
2856		UINT8 imm;
2857		RDOPARG( imm );
2858		WP( UPD7810_PORTF, imm );
2859		}
2860
2861		/* 64 06: 0110 0100 0000 0110 xxxx xxxx */
2862		void upd7810_device::MVI_MKH_xx()
2863		{
2864		RDOPARG( MKH );
2865		}
2866
2867		/* 64 07: 0110 0100 0000 0111 xxxx xxxx */
2868		void upd7810_device::MVI_MKL_xx()
2869		{
2870		RDOPARG( MKL );
2871		}
2872
2873		/* 64 08: 0110 0100 0000 1000 xxxx xxxx */
2874		void upd7810_device::ANI_PA_xx()
2875		{
2876		UINT8 pa = RP( UPD7810_PORTA), imm;
2877		RDOPARG( imm );
2878		pa &= imm;
2879		WP( UPD7810_PORTA, pa );
2880		SET_Z(pa);
2881		}
2882
2883		/* 64 09: 0110 0100 0000 1001 xxxx xxxx */
2884		void upd7810_device::ANI_PB_xx()
2885		{
2886		UINT8 pb = RP( UPD7810_PORTB), imm;
2887		RDOPARG( imm );
2888		pb &= imm;
2889		WP( UPD7810_PORTB, pb );
2890		SET_Z(pb);
2891		}
2892
2893		/* 64 0a: 0110 0100 0000 1010 xxxx xxxx */
2894		void upd7810_device::ANI_PC_xx()
2895		{
2896		UINT8 pc = RP( UPD7810_PORTC), imm;
2897		RDOPARG( imm );
2898		pc &= imm;
2899		WP( UPD7810_PORTC, pc );
2900		SET_Z(pc);
2901		}
2902
2903		/* 64 0b: 0110 0100 0000 1011 xxxx xxxx */
2904		void upd7810_device::ANI_PD_xx()
2905		{
2906		UINT8 pd = RP( UPD7810_PORTD ), imm;
2907		RDOPARG( imm );
2908		pd &= imm;
2909		WP( UPD7810_PORTD, pd );
2910		SET_Z(pd);
2911		}
2912
2913		/* 64 0d: 0110 0100 0000 1101 xxxx xxxx */
2914		void upd7810_device::ANI_PF_xx()
2915		{
2916		UINT8 pf = RP( UPD7810_PORTF ), imm;
2917		RDOPARG( imm );
2918		pf &= imm;
2919		WP( UPD7810_PORTF, pf );
2920		SET_Z(pf);
2921		}
2922
2923		/* 64 0e: 0110 0100 0000 1110 xxxx xxxx */
2924		void upd7810_device::ANI_MKH_xx()
2925		{
2926		UINT8 imm;
2927		RDOPARG( imm );
2928		MKH &= imm;
2929		SET_Z(MKH);
2930		}
2931
2932		/* 64 0f: 0110 0100 0000 1111 xxxx xxxx */
2933		void upd7810_device::ANI_MKL_xx()
2934		{
2935		UINT8 imm;
2936		RDOPARG( imm );
2937		MKL &= imm;
2938		SET_Z(MKL);
2939		}
2940
2941		/* 64 10: 0110 0100 0001 0000 xxxx xxxx */
2942		void upd7810_device::XRI_PA_xx()
2943		{
2944		UINT8 pa = RP( UPD7810_PORTA ), imm;
2945		RDOPARG( imm );
2946		pa ^= imm;
2947		WP( UPD7810_PORTA, pa );
2948		SET_Z(pa);
2949		}
2950
2951		/* 64 11: 0110 0100 0001 0001 xxxx xxxx */
2952		void upd7810_device::XRI_PB_xx()
2953		{
2954		UINT8 pb = RP( UPD7810_PORTB ), imm;
2955		RDOPARG( imm );
2956		pb ^= imm;
2957		WP( UPD7810_PORTB, pb );
2958		SET_Z(pb);
2959		}
2960
2961		/* 64 12: 0110 0100 0001 0010 xxxx xxxx */
2962		void upd7810_device::XRI_PC_xx()
2963		{
2964		UINT8 pc = RP( UPD7810_PORTC ), imm;
2965		RDOPARG( imm );
2966		pc ^= imm;
2967		WP( UPD7810_PORTC, pc );
2968		SET_Z(pc);
2969		}
2970
2971		/* 64 13: 0110 0100 0001 0011 xxxx xxxx */
2972		void upd7810_device::XRI_PD_xx()
2973		{
2974		UINT8 pd = RP( UPD7810_PORTD ), imm;
2975		RDOPARG( imm );
2976		pd ^= imm;
2977		WP( UPD7810_PORTD, pd );
2978		SET_Z(pd);
2979		}
2980
2981		/* 64 15: 0110 0100 0001 0101 xxxx xxxx */
2982		void upd7810_device::XRI_PF_xx()
2983		{
2984		UINT8 pf = RP( UPD7810_PORTF ), imm;
2985		RDOPARG( imm );
2986		pf ^= imm;
2987		WP( UPD7810_PORTF, pf );
2988		SET_Z(pf);
2989		}
2990
2991		/* 64 16: 0110 0100 0001 0110 xxxx xxxx */
2992		void upd7810_device::XRI_MKH_xx()
2993		{
2994		UINT8 imm;
2995		RDOPARG( imm );
2996		MKH ^= imm;
2997		SET_Z(MKH);
2998		}
2999
3000		/* 64 17: 0110 0100 0001 0111 xxxx xxxx */
3001		void upd7810_device::XRI_MKL_xx()
3002		{
3003		UINT8 imm;
3004		RDOPARG( imm );
3005		MKL ^= imm;
3006		SET_Z(MKL);
3007		}
3008
3009		/* 64 18: 0110 0100 0001 1000 xxxx xxxx */
3010		void upd7810_device::ORI_PA_xx()
3011		{
3012		UINT8 pa = RP( UPD7810_PORTA ), imm;
3013		RDOPARG( imm );
3014		pa \|= imm;
3015		WP( UPD7810_PORTA, pa );
3016		SET_Z(pa);
3017		}
3018
3019		/* 64 19: 0110 0100 0001 1001 xxxx xxxx */
3020		void upd7810_device::ORI_PB_xx()
3021		{
3022		UINT8 pb = RP( UPD7810_PORTB ), imm;
3023		RDOPARG( imm );
3024		pb \|= imm;
3025		WP( UPD7810_PORTB, pb );
3026		SET_Z(pb);
3027		}
3028
3029		/* 64 1a: 0110 0100 0001 1010 xxxx xxxx */
3030		void upd7810_device::ORI_PC_xx()
3031		{
3032		UINT8 pc = RP( UPD7810_PORTC ), imm;
3033		RDOPARG( imm );
3034		pc \|= imm;
3035		WP( UPD7810_PORTC, pc );
3036		SET_Z(pc);
3037		}
3038
3039		/* 64 1b: 0110 0100 0001 1011 xxxx xxxx */
3040		void upd7810_device::ORI_PD_xx()
3041		{
3042		UINT8 pd = RP( UPD7810_PORTD ), imm;
3043		RDOPARG( imm );
3044		pd \|= imm;
3045		WP( UPD7810_PORTD, pd );
3046		SET_Z(pd);
3047		}
3048
3049		/* 64 1d: 0110 0100 0001 1101 xxxx xxxx */
3050		void upd7810_device::ORI_PF_xx()
3051		{
3052		UINT8 pf = RP( UPD7810_PORTF ), imm;
3053		RDOPARG( imm );
3054		pf \|= imm;
3055		WP( UPD7810_PORTF, pf );
3056		SET_Z(pf);
3057		}
3058
3059		/* 64 1e: 0110 0100 0001 1110 xxxx xxxx */
3060		void upd7810_device::ORI_MKH_xx()
3061		{
3062		UINT8 imm;
3063		RDOPARG( imm );
3064		MKH \|= imm;
3065		SET_Z(MKH);
3066		}
3067
3068		/* 64 1f: 0110 0100 0001 1111 xxxx xxxx */
3069		void upd7810_device::ORI_MKL_xx()
3070		{
3071		UINT8 imm;
3072		RDOPARG( imm );
3073		MKL \|= imm;
3074		SET_Z(MKL);
3075		}
3076
3077		/* 64 20: 0110 0100 0010 0000 xxxx xxxx */
3078		void upd7810_device::ADINC_PA_xx()
3079		{
3080		UINT8 pa = RP( UPD7810_PORTA );
3081		UINT8 tmp, imm;
3082
3083		RDOPARG( imm );
3084		tmp = pa + imm;
3085
3086		ZHC_ADD( tmp, pa, 0 );
3087		WP( UPD7810_PORTA , tmp );
3088		SKIP_NC;
3089		}
3090
3091		/* 64 21: 0110 0100 0010 0001 xxxx xxxx */
3092		void upd7810_device::ADINC_PB_xx()
3093		{
3094		UINT8 pb = RP( UPD7810_PORTB );
3095		UINT8 tmp, imm;
3096
3097		RDOPARG( imm );
3098		tmp = pb + imm;
3099
3100		ZHC_ADD( tmp, pb, 0 );
3101		WP( UPD7810_PORTB, tmp );
3102		SKIP_NC;
3103		}
3104
3105		/* 64 22: 0110 0100 0010 0010 xxxx xxxx */
3106		void upd7810_device::ADINC_PC_xx()
3107		{
3108		UINT8 pc = RP( UPD7810_PORTC );
3109		UINT8 tmp, imm;
3110
3111		RDOPARG( imm );
3112		tmp = pc + imm;
3113
3114		ZHC_ADD( tmp, pc, 0 );
3115		WP( UPD7810_PORTC, tmp );
3116		SKIP_NC;
3117		}
3118
3119		/* 64 23: 0110 0100 0010 0011 xxxx xxxx */
3120		void upd7810_device::ADINC_PD_xx()
3121		{
3122		UINT8 pd = RP( UPD7810_PORTD );
3123		UINT8 tmp, imm;
3124
3125		RDOPARG( imm );
3126		tmp = pd + imm;
3127
3128		ZHC_ADD( tmp, pd, 0 );
3129		WP( UPD7810_PORTD, tmp );
3130		SKIP_NC;
3131		}
3132
3133		/* 64 25: 0110 0100 0010 0101 xxxx xxxx */
3134		void upd7810_device::ADINC_PF_xx()
3135		{
3136		UINT8 pf = RP( UPD7810_PORTF );
3137		UINT8 tmp, imm;
3138
3139		RDOPARG( imm );
3140		tmp = pf + imm;
3141
3142		ZHC_ADD( tmp, pf, 0 );
3143		WP( UPD7810_PORTF, tmp );
3144		SKIP_NC;
3145		}
3146
3147		/* 64 26: 0110 0100 0010 0110 xxxx xxxx */
3148		void upd7810_device::ADINC_MKH_xx()
3149		{
3150		UINT8 tmp, imm;
3151
3152		RDOPARG( imm );
3153		tmp = MKH + imm;
3154
3155		ZHC_ADD( tmp, MKH, 0 );
3156		MKH = tmp;
3157		SKIP_NC;
3158		}
3159
3160		/* 64 27: 0110 0100 0010 0111 xxxx xxxx */
3161		void upd7810_device::ADINC_MKL_xx()
3162		{
3163		UINT8 tmp, imm;
3164
3165		RDOPARG( imm );
3166		tmp = MKL + imm;
3167
3168		ZHC_ADD( tmp, MKL, 0 );
3169		MKL = tmp;
3170		SKIP_NC;
3171		}
3172
3173		/* 64 28: 0110 0100 0010 1000 xxxx xxxx */
3174		void upd7810_device::GTI_PA_xx()
3175		{
3176		UINT8 pa = RP( UPD7810_PORTA ), imm;
3177		UINT16 tmp;
3178
3179		RDOPARG( imm );
3180		tmp = pa - imm - 1;
3181		ZHC_SUB( tmp, pa, 0 );
3182
3183		SKIP_NC;
3184		}
3185
3186		/* 64 29: 0110 0100 0010 1001 xxxx xxxx */
3187		void upd7810_device::GTI_PB_xx()
3188		{
3189		UINT8 pb = RP( UPD7810_PORTB ), imm;
3190		UINT16 tmp;
3191
3192		RDOPARG( imm );
3193		tmp = pb - imm - 1;
3194		ZHC_SUB( tmp, pb, 0 );
3195
3196		SKIP_NC;
3197		}
3198
3199		/* 64 2a: 0110 0100 0010 1010 xxxx xxxx */
3200		void upd7810_device::GTI_PC_xx()
3201		{
3202		UINT8 pc = RP( UPD7810_PORTC ), imm;
3203		UINT16 tmp;
3204
3205		RDOPARG( imm );
3206		tmp = pc - imm - 1;
3207		ZHC_SUB( tmp, pc, 0 );
3208
3209		SKIP_NC;
3210		}
3211
3212		/* 64 2b: 0110 0100 0010 1011 xxxx xxxx */
3213		void upd7810_device::GTI_PD_xx()
3214		{
3215		UINT8 pd = RP( UPD7810_PORTD ), imm;
3216		UINT16 tmp;
3217
3218		RDOPARG( imm );
3219		tmp = pd - imm - 1;
3220		ZHC_SUB( tmp, pd, 0 );
3221
3222		SKIP_NC;
3223		}
3224
3225		/* 64 2d: 0110 0100 0010 1101 xxxx xxxx */
3226		void upd7810_device::GTI_PF_xx()
3227		{
3228		UINT8 pf = RP( UPD7810_PORTF ), imm;
3229		UINT16 tmp;
3230
3231		RDOPARG( imm );
3232		tmp = pf - imm - 1;
3233		ZHC_SUB( tmp, pf, 0 );
3234
3235		SKIP_NC;
3236		}
3237
3238		/* 64 2e: 0110 0100 0010 1110 xxxx xxxx */
3239		void upd7810_device::GTI_MKH_xx()
3240		{
3241		UINT8 imm;
3242		UINT16 tmp;
3243
3244		RDOPARG( imm );
3245		tmp = MKH - imm - 1;
3246		ZHC_SUB( tmp, MKH, 0 );
3247
3248		SKIP_NC;
3249		}
3250
3251		/* 64 2f: 0110 0100 0010 1111 xxxx xxxx */
3252		void upd7810_device::GTI_MKL_xx()
3253		{
3254		UINT8 imm;
3255		UINT16 tmp;
3256
3257		RDOPARG( imm );
3258		tmp = MKL - imm - 1;
3259		ZHC_SUB( tmp, MKL, 0 );
3260
3261		SKIP_NC;
3262		}
3263
3264		/* 64 30: 0110 0100 0011 0000 xxxx xxxx */
3265		void upd7810_device::SUINB_PA_xx()
3266		{
3267		UINT8 pa = RP( UPD7810_PORTA ), tmp, imm;
3268
3269		RDOPARG( imm );
3270		tmp = pa - imm;
3271		ZHC_SUB( tmp, pa, 0 );
3272		pa = tmp;
3273		WP( UPD7810_PORTA, pa );
3274		SKIP_NC;
3275		}
3276
3277		/* 64 31: 0110 0100 0011 0001 xxxx xxxx */
3278		void upd7810_device::SUINB_PB_xx()
3279		{
3280		UINT8 pb = RP( UPD7810_PORTB ), tmp, imm;
3281
3282		RDOPARG( imm );
3283		tmp = pb - imm;
3284		ZHC_SUB( tmp, pb, 0 );
3285		pb = tmp;
3286		WP( UPD7810_PORTB, pb );
3287		SKIP_NC;
3288		}
3289
3290		/* 64 32: 0110 0100 0011 0010 xxxx xxxx */
3291		void upd7810_device::SUINB_PC_xx()
3292		{
3293		UINT8 pc = RP( UPD7810_PORTC ), tmp, imm;
3294
3295		RDOPARG( imm );
3296		tmp = pc - imm;
3297		ZHC_SUB( tmp, pc, 0 );
3298		pc = tmp;
3299		WP( UPD7810_PORTC, pc );
3300		SKIP_NC;
3301		}
3302
3303		/* 64 33: 0110 0100 0011 0011 xxxx xxxx */
3304		void upd7810_device::SUINB_PD_xx()
3305		{
3306		UINT8 pd = RP( UPD7810_PORTD ), tmp, imm;
3307
3308		RDOPARG( imm );
3309		tmp = pd - imm;
3310		ZHC_SUB( tmp, pd, 0 );
3311		pd = tmp;
3312		WP( UPD7810_PORTD, pd );
3313		SKIP_NC;
3314		}
3315
3316		/* 64 35: 0110 0100 0011 0101 xxxx xxxx */
3317		void upd7810_device::SUINB_PF_xx()
3318		{
3319		UINT8 pf = RP( UPD7810_PORTF ), tmp, imm;
3320
3321		RDOPARG( imm );
3322		tmp = pf - imm;
3323		ZHC_SUB( tmp, pf, 0 );
3324		pf = tmp;
3325		WP( UPD7810_PORTF, pf );
3326		SKIP_NC;
3327		}
3328
3329		/* 64 36: 0110 0100 0011 0110 xxxx xxxx */
3330		void upd7810_device::SUINB_MKH_xx()
3331		{
3332		UINT8 tmp, imm;
3333
3334		RDOPARG( imm );
3335		tmp = MKH - imm;
3336		ZHC_SUB( tmp, MKH, 0 );
3337		MKH = tmp;
3338		SKIP_NC;
3339		}
3340
3341		/* 64 37: 0110 0100 0011 0111 xxxx xxxx */
3342		void upd7810_device::SUINB_MKL_xx()
3343		{
3344		UINT8 tmp, imm;
3345
3346		RDOPARG( imm );
3347		tmp = MKL - imm;
3348		ZHC_SUB( tmp, MKL, 0 );
3349		MKL = tmp;
3350		SKIP_NC;
3351		}
3352
3353		/* 64 38: 0110 0100 0011 1000 xxxx xxxx */
3354		void upd7810_device::LTI_PA_xx()
3355		{
3356		UINT8 pa = RP( UPD7810_PORTA ), tmp, imm;
3357		RDOPARG( imm );
3358		tmp = pa - imm;
3359		ZHC_SUB( tmp, pa, 0 );
3360		SKIP_CY;
3361		}
3362
3363		/* 64 39: 0110 0100 0011 1001 xxxx xxxx */
3364		void upd7810_device::LTI_PB_xx()
3365		{
3366		UINT8 pb = RP( UPD7810_PORTB ), tmp, imm;
3367		RDOPARG( imm );
3368		tmp = pb - imm;
3369		ZHC_SUB( tmp, pb, 0 );
3370		SKIP_CY;
3371		}
3372
3373		/* 64 3a: 0110 0100 0011 1010 xxxx xxxx */
3374		void upd7810_device::LTI_PC_xx()
3375		{
3376		UINT8 pc = RP( UPD7810_PORTC ), tmp, imm;
3377		RDOPARG( imm );
3378		tmp = pc - imm;
3379		ZHC_SUB( tmp, pc, 0 );
3380		SKIP_CY;
3381		}
3382
3383		/* 64 3b: 0110 0100 0011 1011 xxxx xxxx */
3384		void upd7810_device::LTI_PD_xx()
3385		{
3386		UINT8 pd = RP( UPD7810_PORTD ), tmp, imm;
3387		RDOPARG( imm );
3388		tmp = pd - imm;
3389		ZHC_SUB( tmp, pd, 0 );
3390		SKIP_CY;
3391		}
3392
3393		/* 64 3d: 0110 0100 0011 1101 xxxx xxxx */
3394		void upd7810_device::LTI_PF_xx()
3395		{
3396		UINT8 pf = RP( UPD7810_PORTF ), tmp, imm;
3397		RDOPARG( imm );
3398		tmp = pf - imm;
3399		ZHC_SUB( tmp, pf, 0 );
3400		SKIP_CY;
3401		}
3402
3403		/* 64 3e: 0110 0100 0011 1110 xxxx xxxx */
3404		void upd7810_device::LTI_MKH_xx()
3405		{
3406		UINT8 tmp, imm;
3407
3408		RDOPARG( imm );
3409		tmp = MKH - imm;
3410		ZHC_SUB( tmp, MKH, 0 );
3411		SKIP_CY;
3412		}
3413
3414		/* 64 3f: 0110 0100 0011 1111 xxxx xxxx */
3415		void upd7810_device::LTI_MKL_xx()
3416		{
3417		UINT8 tmp, imm;
3418
3419		RDOPARG( imm );
3420		tmp = MKL - imm;
3421		ZHC_SUB( tmp, MKL, 0 );
3422		SKIP_CY;
3423		}
3424
3425		/* 64 40: 0110 0100 0100 0000 xxxx xxxx */
3426		void upd7810_device::ADI_PA_xx()
3427		{
3428		UINT8 pa = RP( UPD7810_PORTA ), tmp, imm;
3429
3430		RDOPARG( imm );
3431		tmp = pa + imm;
3432		ZHC_ADD( tmp, pa, 0 );
3433		pa = tmp;
3434		WP( UPD7810_PORTA, pa );
3435		}
3436
3437		/* 64 41: 0110 0100 0100 0001 xxxx xxxx */
3438		void upd7810_device::ADI_PB_xx()
3439		{
3440		UINT8 pb = RP( UPD7810_PORTB ), tmp, imm;
3441
3442		RDOPARG( imm );
3443		tmp = pb + imm;
3444		ZHC_ADD( tmp, pb, 0 );
3445		pb = tmp;
3446		WP( UPD7810_PORTB, pb );
3447		}
3448
3449		/* 64 42: 0110 0100 0100 0010 xxxx xxxx */
3450		void upd7810_device::ADI_PC_xx()
3451		{
3452		UINT8 pc = RP( UPD7810_PORTC ), tmp, imm;
3453
3454		RDOPARG( imm );
3455		tmp = pc + imm;
3456		ZHC_ADD( tmp, pc, 0 );
3457		pc = tmp;
3458		WP( UPD7810_PORTC, pc );
3459		}
3460
3461		/* 64 43: 0110 0100 0100 0011 xxxx xxxx */
3462		void upd7810_device::ADI_PD_xx()
3463		{
3464		UINT8 pd = RP( UPD7810_PORTD ), tmp, imm;
3465
3466		RDOPARG( imm );
3467		tmp = pd + imm;
3468		ZHC_ADD( tmp, pd, 0 );
3469		pd = tmp;
3470		WP( UPD7810_PORTD, pd );
3471		}
3472
3473		/* 64 45: 0110 0100 0100 0101 xxxx xxxx */
3474		void upd7810_device::ADI_PF_xx()
3475		{
3476		UINT8 pf = RP( UPD7810_PORTF ), tmp, imm;
3477
3478		RDOPARG( imm );
3479		tmp = pf + imm;
3480		ZHC_ADD( tmp, pf, 0 );
3481		pf = tmp;
3482		WP( UPD7810_PORTF, pf );
3483		}
3484
3485		/* 64 46: 0110 0100 0100 0110 xxxx xxxx */
3486		void upd7810_device::ADI_MKH_xx()
3487		{
3488		UINT8 tmp, imm;
3489
3490		RDOPARG( imm );
3491		tmp = MKH + imm;
3492		ZHC_ADD( tmp, MKH, 0 );
3493		MKH = tmp;
3494		}
3495
3496		/* 64 47: 0110 0100 0100 0111 xxxx xxxx */
3497		void upd7810_device::ADI_MKL_xx()
3498		{
3499		UINT8 tmp, imm;
3500
3501		RDOPARG( imm );
3502		tmp = MKL + imm;
3503		ZHC_ADD( tmp, MKL, 0 );
3504		MKL = tmp;
3505		}
3506
3507		/* 64 48: 0110 0100 0100 1000 xxxx xxxx */
3508		void upd7810_device::ONI_PA_xx()
3509		{
3510		UINT8 pa = RP( UPD7810_PORTA ), imm;
3511
3512		RDOPARG( imm );
3513		if (pa & imm)
3514		PSW \|= SK;
3515		}
3516
3517		/* 64 49: 0110 0100 0100 1001 xxxx xxxx */
3518		void upd7810_device::ONI_PB_xx()
3519		{
3520		UINT8 pb = RP( UPD7810_PORTB ), imm;
3521
3522		RDOPARG( imm );
3523		if (pb & imm)
3524		PSW \|= SK;
3525		}
3526
3527		/* 64 4a: 0110 0100 0100 1010 xxxx xxxx */
3528		void upd7810_device::ONI_PC_xx()
3529		{
3530		UINT8 pc = RP( UPD7810_PORTC ), imm;
3531
3532		RDOPARG( imm );
3533		if (pc & imm)
3534		PSW \|= SK;
3535		}
3536
3537		/* 64 4b: 0110 0100 0100 1011 xxxx xxxx */
3538		void upd7810_device::ONI_PD_xx()
3539		{
3540		UINT8 pd = RP( UPD7810_PORTD ), imm;
3541
3542		RDOPARG( imm );
3543		if (pd & imm)
3544		PSW \|= SK;
3545		}
3546
3547		/* 64 4d: 0110 0100 0100 1101 xxxx xxxx */
3548		void upd7810_device::ONI_PF_xx()
3549		{
3550		UINT8 pf = RP( UPD7810_PORTF ), imm;
3551
3552		RDOPARG( imm );
3553		if (pf & imm)
3554		PSW \|= SK;
3555		}
3556
3557		/* 64 4e: 0110 0100 0100 1110 xxxx xxxx */
3558		void upd7810_device::ONI_MKH_xx()
3559		{
3560		UINT8 imm;
3561
3562		RDOPARG( imm );
3563		if (MKH & imm)
3564		PSW \|= SK;
3565		}
3566
3567		/* 64 4f: 0110 0100 0100 1111 xxxx xxxx */
3568		void upd7810_device::ONI_MKL_xx()
3569		{
3570		UINT8 imm;
3571
3572		RDOPARG( imm );
3573		if (MKL & imm)
3574		PSW \|= SK;
3575		}
3576
3577		/* 64 50: 0110 0100 0101 0000 xxxx xxxx */
3578		void upd7810_device::ACI_PA_xx()
3579		{
3580		UINT8 pa = RP( UPD7810_PORTA ), tmp, imm;
3581
3582		RDOPARG( imm );
3583		tmp = pa + imm + (PSW & CY);
3584		ZHC_ADD( tmp, pa, (PSW & CY) );
3585		pa = tmp;
3586		WP( UPD7810_PORTA, pa );
3587		}
3588
3589		/* 64 51: 0110 0100 0101 0001 xxxx xxxx */
3590		void upd7810_device::ACI_PB_xx()
3591		{
3592		UINT8 pb = RP( UPD7810_PORTB ), tmp, imm;
3593
3594		RDOPARG( imm );
3595		tmp = pb + imm + (PSW & CY);
3596		ZHC_ADD( tmp, pb, (PSW & CY) );
3597		pb = tmp;
3598		WP( UPD7810_PORTB, pb );
3599		}
3600
3601		/* 64 52: 0110 0100 0101 0010 xxxx xxxx */
3602		void upd7810_device::ACI_PC_xx()
3603		{
3604		UINT8 pc = RP( UPD7810_PORTC ), tmp, imm;
3605
3606		RDOPARG( imm );
3607		tmp = pc + imm + (PSW & CY);
3608		ZHC_ADD( tmp, pc, (PSW & CY) );
3609		pc = tmp;
3610		WP( UPD7810_PORTC, pc );
3611		}
3612
3613		/* 64 53: 0110 0100 0101 0011 xxxx xxxx */
3614		void upd7810_device::ACI_PD_xx()
3615		{
3616		UINT8 pd = RP( UPD7810_PORTD ), tmp, imm;
3617
3618		RDOPARG( imm );
3619		tmp = pd + imm + (PSW & CY);
3620		ZHC_ADD( tmp, pd, (PSW & CY) );
3621		pd = tmp;
3622		WP( UPD7810_PORTD, pd );
3623		}
3624
3625		/* 64 55: 0110 0100 0101 0101 xxxx xxxx */
3626		void upd7810_device::ACI_PF_xx()
3627		{
3628		UINT8 pf = RP( UPD7810_PORTF ), tmp, imm;
3629
3630		RDOPARG( imm );
3631		tmp = pf + imm + (PSW & CY);
3632		ZHC_ADD( tmp, pf, (PSW & CY) );
3633		pf = tmp;
3634		WP( UPD7810_PORTF, pf );
3635		}
3636
3637		/* 64 56: 0110 0100 0101 0110 xxxx xxxx */
3638		void upd7810_device::ACI_MKH_xx()
3639		{
3640		UINT8 imm, tmp;
3641
3642		RDOPARG( imm );
3643		tmp = MKH + imm + (PSW & CY);
3644		ZHC_ADD( tmp, MKH, (PSW & CY) );
3645		MKH = tmp;
3646		}
3647
3648		/* 64 57: 0110 0100 0101 0111 xxxx xxxx */
3649		void upd7810_device::ACI_MKL_xx()
3650		{
3651		UINT8 imm, tmp;
3652
3653		RDOPARG( imm );
3654		tmp = MKL + imm + (PSW & CY);
3655		ZHC_ADD( tmp, MKL, (PSW & CY) );
3656		MKL = tmp;
3657		}
3658
3659		/* 64 58: 0110 0100 0101 1000 xxxx xxxx */
3660		void upd7810_device::OFFI_PA_xx()
3661		{
3662		UINT8 pa = RP( UPD7810_PORTA ), imm;
3663
3664		RDOPARG( imm );
3665		if (0 == (pa & imm))
3666		PSW \|= SK;
3667		}
3668
3669		/* 64 59: 0110 0100 0101 1001 xxxx xxxx */
3670		void upd7810_device::OFFI_PB_xx()
3671		{
3672		UINT8 pb = RP( UPD7810_PORTB ), imm;
3673
3674		RDOPARG( imm );
3675		if (0 == (pb & imm))
3676		PSW \|= SK;
3677		}
3678
3679		/* 64 5a: 0110 0100 0101 1010 xxxx xxxx */
3680		void upd7810_device::OFFI_PC_xx()
3681		{
3682		UINT8 pc = RP( UPD7810_PORTC ), imm;
3683
3684		RDOPARG( imm );
3685		if (0 == (pc & imm))
3686		PSW \|= SK;
3687		}
3688
3689		/* 64 5b: 0110 0100 0101 1011 xxxx xxxx */
3690		void upd7810_device::OFFI_PD_xx()
3691		{
3692		UINT8 pd = RP( UPD7810_PORTD ), imm;
3693
3694		RDOPARG( imm );
3695		if (0 == (pd & imm))
3696		PSW \|= SK;
3697		}
3698
3699		/* 64 5d: 0110 0100 0101 1101 xxxx xxxx */
3700		void upd7810_device::OFFI_PF_xx()
3701		{
3702		UINT8 pf = RP( UPD7810_PORTF ), imm;
3703
3704		RDOPARG( imm );
3705		if (0 == (pf & imm))
3706		PSW \|= SK;
3707		}
3708
3709		/* 64 5e: 0110 0100 0101 1110 xxxx xxxx */
3710		void upd7810_device::OFFI_MKH_xx()
3711		{
3712		UINT8 imm;
3713
3714		RDOPARG( imm );
3715		if (0 == (MKH & imm))
3716		PSW \|= SK;
3717		}
3718
3719		/* 64 5f: 0110 0100 0101 1111 xxxx xxxx */
3720		void upd7810_device::OFFI_MKL_xx()
3721		{
3722		UINT8 imm;
3723
3724		RDOPARG( imm );
3725		if (0 == (MKL & imm))
3726		PSW \|= SK;
3727		}
3728
3729		/* 64 60: 0110 0100 0110 0000 xxxx xxxx */
3730		void upd7810_device::SUI_PA_xx()
3731		{
3732		UINT8 pa = RP( UPD7810_PORTA ), tmp, imm;
3733
3734		RDOPARG( imm );
3735		tmp = pa - imm;
3736		ZHC_SUB( tmp, pa, 0 );
3737		pa = tmp;
3738		WP( UPD7810_PORTA, pa );
3739		}
3740
3741		/* 64 61: 0110 0100 0110 0001 xxxx xxxx */
3742		void upd7810_device::SUI_PB_xx()
3743		{
3744		UINT8 pb = RP( UPD7810_PORTB ), tmp, imm;
3745
3746		RDOPARG( imm );
3747		tmp = pb - imm;
3748		ZHC_SUB( tmp, pb, 0 );
3749		pb = tmp;
3750		WP( UPD7810_PORTB, pb );
3751		}
3752
3753		/* 64 62: 0110 0100 0110 0010 xxxx xxxx */
3754		void upd7810_device::SUI_PC_xx()
3755		{
3756		UINT8 pc = RP( UPD7810_PORTC ), tmp, imm;
3757
3758		RDOPARG( imm );
3759		tmp = pc - imm;
3760		ZHC_SUB( tmp, pc, 0 );
3761		pc = tmp;
3762		WP( UPD7810_PORTC, pc );
3763		}
3764
3765		/* 64 63: 0110 0100 0110 0011 xxxx xxxx */
3766		void upd7810_device::SUI_PD_xx()
3767		{
3768		UINT8 pd = RP( UPD7810_PORTD ), tmp, imm;
3769
3770		RDOPARG( imm );
3771		tmp = pd - imm;
3772		ZHC_SUB( tmp, pd, 0 );
3773		pd = tmp;
3774		WP( UPD7810_PORTD, pd );
3775		}
3776
3777		/* 64 65: 0110 0100 0110 0101 xxxx xxxx */
3778		void upd7810_device::SUI_PF_xx()
3779		{
3780		UINT8 pf = RP( UPD7810_PORTF ), tmp, imm;
3781
3782		RDOPARG( imm );
3783		tmp = pf - imm;
3784		ZHC_SUB( tmp, pf, 0 );
3785		pf = tmp;
3786		WP( UPD7810_PORTF, pf );
3787		}
3788
3789		/* 64 66: 0110 0100 0110 0110 xxxx xxxx */
3790		void upd7810_device::SUI_MKH_xx()
3791		{
3792		UINT8 tmp, imm;
3793
3794		RDOPARG( imm );
3795		tmp = MKH - imm;
3796		ZHC_SUB( tmp, MKH, 0 );
3797		MKH = tmp;
3798		}
3799
3800		/* 64 67: 0110 0100 0110 0111 xxxx xxxx */
3801		void upd7810_device::SUI_MKL_xx()
3802		{
3803		UINT8 tmp, imm;
3804
3805		RDOPARG( imm );
3806		tmp = MKL - imm;
3807		ZHC_SUB( tmp, MKL, 0 );
3808		MKL = tmp;
3809		}
3810
3811		/* 64 68: 0110 0100 0110 1000 xxxx xxxx */
3812		void upd7810_device::NEI_PA_xx()
3813		{
3814		UINT8 pa = RP( UPD7810_PORTA ), tmp, imm;
3815
3816		RDOPARG( imm );
3817		tmp = pa - imm;
3818		ZHC_SUB( tmp, pa, 0 );
3819		SKIP_NZ;
3820		}
3821
3822		/* 64 69: 0110 0100 0110 1001 xxxx xxxx */
3823		void upd7810_device::NEI_PB_xx()
3824		{
3825		UINT8 pb = RP( UPD7810_PORTB ), tmp, imm;
3826
3827		RDOPARG( imm );
3828		tmp = pb - imm;
3829		ZHC_SUB( tmp, pb, 0 );
3830		SKIP_NZ;
3831		}
3832
3833		/* 64 6a: 0110 0100 0110 1010 xxxx xxxx */
3834		void upd7810_device::NEI_PC_xx()
3835		{
3836		UINT8 pc = RP( UPD7810_PORTC ), tmp, imm;
3837
3838		RDOPARG( imm );
3839		tmp = pc - imm;
3840		ZHC_SUB( tmp, pc, 0 );
3841		SKIP_NZ;
3842		}
3843
3844		/* 64 6b: 0110 0100 0110 1011 xxxx xxxx */
3845		void upd7810_device::NEI_PD_xx()
3846		{
3847		UINT8 pd = RP( UPD7810_PORTD ), tmp, imm;
3848
3849		RDOPARG( imm );
3850		tmp = pd - imm;
3851		ZHC_SUB( tmp, pd, 0 );
3852		SKIP_NZ;
3853		}
3854
3855		/* 64 6d: 0110 0100 0110 1101 xxxx xxxx */
3856		void upd7810_device::NEI_PF_xx()
3857		{
3858		UINT8 pf = RP( UPD7810_PORTF ), tmp, imm;
3859
3860		RDOPARG( imm );
3861		tmp = pf - imm;
3862		ZHC_SUB( tmp, pf, 0 );
3863		SKIP_NZ;
3864		}
3865
3866		/* 64 6e: 0110 0100 0110 1110 xxxx xxxx */
3867		void upd7810_device::NEI_MKH_xx()
3868		{
3869		UINT8 tmp, imm;
3870
3871		RDOPARG( imm );
3872		tmp = MKH - imm;
3873		ZHC_SUB( tmp, MKH, 0 );
3874		SKIP_NZ;
3875		}
3876
3877		/* 64 6f: 0110 0100 0110 1111 xxxx xxxx */
3878		void upd7810_device::NEI_MKL_xx()
3879		{
3880		UINT8 tmp, imm;
3881
3882		RDOPARG( imm );
3883		tmp = MKL - imm;
3884		ZHC_SUB( tmp, MKL, 0 );
3885		SKIP_NZ;
3886		}
3887
3888		/* 64 70: 0110 0100 0111 0000 xxxx xxxx */
3889		void upd7810_device::SBI_PA_xx()
3890		{
3891		UINT8 pa = RP( UPD7810_PORTA ), tmp, imm;
3892
3893		RDOPARG( imm );
3894		tmp = pa - imm - (PSW & CY);
3895		ZHC_SUB( tmp, pa, (PSW & CY) );
3896		pa = tmp;
3897		WP( UPD7810_PORTA, pa );
3898		}
3899
3900		/* 64 71: 0110 0100 0111 0001 xxxx xxxx */
3901		void upd7810_device::SBI_PB_xx()
3902		{
3903		UINT8 pb = RP( UPD7810_PORTB ), tmp, imm;
3904
3905		RDOPARG( imm );
3906		tmp = pb - imm - (PSW & CY);
3907		ZHC_SUB( tmp, pb, (PSW & CY) );
3908		pb = tmp;
3909		WP( UPD7810_PORTB, pb );
3910		}
3911
3912		/* 64 72: 0110 0100 0111 0010 xxxx xxxx */
3913		void upd7810_device::SBI_PC_xx()
3914		{
3915		UINT8 pc = RP( UPD7810_PORTC ), tmp, imm;
3916
3917		RDOPARG( imm );
3918		tmp = pc - imm - (PSW & CY);
3919		ZHC_SUB( tmp, pc, (PSW & CY) );
3920		pc = tmp;
3921		WP( UPD7810_PORTC, pc );
3922		}
3923
3924		/* 64 73: 0110 0100 0111 0011 xxxx xxxx */
3925		void upd7810_device::SBI_PD_xx()
3926		{
3927		UINT8 pd = RP( UPD7810_PORTD ), tmp, imm;
3928
3929		RDOPARG( imm );
3930		tmp = pd - imm - (PSW & CY);
3931		ZHC_SUB( tmp, pd, (PSW & CY) );
3932		pd = tmp;
3933		WP( UPD7810_PORTD, pd );
3934		}
3935
3936		/* 64 75: 0110 0100 0111 0101 xxxx xxxx */
3937		void upd7810_device::SBI_PF_xx()
3938		{
3939		UINT8 pf = RP( UPD7810_PORTF ), tmp, imm;
3940
3941		RDOPARG( imm );
3942		tmp = pf - imm - (PSW & CY);
3943		ZHC_SUB( tmp, pf, (PSW & CY) );
3944		pf = tmp;
3945		WP( UPD7810_PORTF, pf );
3946		}
3947
3948		/* 64 76: 0110 0100 0111 0110 xxxx xxxx */
3949		void upd7810_device::SBI_MKH_xx()
3950		{
3951		UINT8 tmp, imm;
3952
3953		RDOPARG( imm );
3954		tmp = MKH - imm - (PSW & CY);
3955		ZHC_SUB( tmp, MKH, (PSW & CY) );
3956		MKH = tmp;
3957		}
3958
3959		/* 64 77: 0110 0100 0111 0111 xxxx xxxx */
3960		void upd7810_device::SBI_MKL_xx()
3961		{
3962		UINT8 tmp, imm;
3963
3964		RDOPARG( imm );
3965		tmp = MKL - imm - (PSW & CY);
3966		ZHC_SUB( tmp, MKL, (PSW & CY) );
3967		MKL = tmp;
3968		}
3969
3970		/* 64 78: 0110 0100 0111 1000 xxxx xxxx */
3971		void upd7810_device::EQI_PA_xx()
3972		{
3973		UINT8 pa = RP( UPD7810_PORTA ), tmp, imm;
3974
3975		RDOPARG( imm );
3976		tmp = pa - imm;
3977		ZHC_SUB( tmp, pa, 0 );
3978		SKIP_Z;
3979		}
3980
3981		/* 64 79: 0110 0100 0111 1001 xxxx xxxx */
3982		void upd7810_device::EQI_PB_xx()
3983		{
3984		UINT8 pb = RP( UPD7810_PORTB ), tmp, imm;
3985
3986		RDOPARG( imm );
3987		tmp = pb - imm;
3988		ZHC_SUB( tmp, pb, 0 );
3989		SKIP_Z;
3990		}
3991
3992		/* 64 7a: 0110 0100 0111 1010 xxxx xxxx */
3993		void upd7810_device::EQI_PC_xx()
3994		{
3995		UINT8 pc = RP( UPD7810_PORTC ), tmp, imm;
3996
3997		RDOPARG( imm );
3998		tmp = pc - imm;
3999		ZHC_SUB( tmp, pc, 0 );
4000		SKIP_Z;
4001		}
4002
4003		/* 64 7b: 0110 0100 0111 1011 xxxx xxxx */
4004		void upd7810_device::EQI_PD_xx()
4005		{
4006		UINT8 pd = RP( UPD7810_PORTD ), tmp, imm;
4007
4008		RDOPARG( imm );
4009		tmp = pd - imm;
4010		ZHC_SUB( tmp, pd, 0 );
4011		SKIP_Z;
4012		}
4013
4014		/* 64 7d: 0110 0100 0111 1101 xxxx xxxx */
4015		void upd7810_device::EQI_PF_xx()
4016		{
4017		UINT8 pf = RP( UPD7810_PORTF ), tmp, imm;
4018
4019		RDOPARG( imm );
4020		tmp = pf - imm;
4021		ZHC_SUB( tmp, pf, 0 );
4022		SKIP_Z;
4023		}
4024
4025		/* 64 7e: 0110 0100 0111 1110 xxxx xxxx */
4026		void upd7810_device::EQI_MKH_xx()
4027		{
4028		UINT8 tmp, imm;
4029
4030		RDOPARG( imm );
4031		tmp = MKH - imm;
4032		ZHC_SUB( tmp, MKH, 0 );
4033		SKIP_Z;
4034		}
4035
4036		/* 64 7f: 0110 0100 0111 1111 xxxx xxxx */
4037		void upd7810_device::EQI_MKL_xx()
4038		{
4039		UINT8 tmp, imm;
4040
4041		RDOPARG( imm );
4042		tmp = MKL - imm;
4043		ZHC_SUB( tmp, MKL, 0 );
4044		SKIP_Z;
4045		}
4046
4047		/* 64 80: 0110 0100 1000 0000 xxxx xxxx */
4048		void upd7810_device::MVI_ANM_xx()
4049		{
4050		RDOPARG( ANM );
4051		}
4052
4053		/* 64 81: 0110 0100 1000 0001 xxxx xxxx */
4054		void upd7810_device::MVI_SMH_xx()
4055		{
4056		RDOPARG( SMH );
4057		}
4058
4059		/* 64 83: 0110 0100 1000 0011 xxxx xxxx */
4060		void upd7810_device::MVI_EOM_xx()
4061		{
4062		RDOPARG( EOM );
4063		upd7810_write_EOM();
4064		}
4065
4066		/* 64 85: 0110 0100 1000 0101 xxxx xxxx */
4067		void upd7810_device::MVI_TMM_xx()
4068		{
4069		RDOPARG( TMM );
4070		}
4071
4072		/* 64 88: 0110 0100 1000 1000 xxxx xxxx */
4073		void upd7810_device::ANI_ANM_xx()
4074		{
4075		UINT8 imm;
4076
4077		RDOPARG( imm );
4078		ANM &= imm;
4079		SET_Z(ANM);
4080		}
4081
4082		/* 64 89: 0110 0100 1000 1001 xxxx xxxx */
4083		void upd7810_device::ANI_SMH_xx()
4084		{
4085		UINT8 imm;
4086
4087		RDOPARG( imm );
4088		SMH &= imm;
4089		SET_Z(SMH);
4090		}
4091
4092		/* 64 8b: 0110 0100 1000 1011 xxxx xxxx */
4093		void upd7810_device::ANI_EOM_xx()
4094		{
4095		/* only bits #1 and #5 can be read */
4096		UINT8 eom = EOM & 0x22;
4097		UINT8 imm;
4098
4099		RDOPARG( imm );
4100		/* only bits #1 and #5 can be read */
4101		EOM = eom & imm;
4102		SET_Z(EOM);
4103		upd7810_write_EOM();
4104		}
4105
4106		/* 64 8d: 0110 0100 1000 1101 xxxx xxxx */
4107		void upd7810_device::ANI_TMM_xx()
4108		{
4109		UINT8 imm;
4110
4111		RDOPARG( imm );
4112		TMM &= imm;
4113		SET_Z(TMM);
4114		}
4115
4116		/* 64 90: 0110 0100 1001 0000 xxxx xxxx */
4117		void upd7810_device::XRI_ANM_xx()
4118		{
4119		UINT8 imm;
4120
4121		RDOPARG( imm );
4122		ANM ^= imm;
4123		SET_Z(ANM);
4124		}
4125
4126		/* 64 91: 0110 0100 1001 0001 xxxx xxxx */
4127		void upd7810_device::XRI_SMH_xx()
4128		{
4129		UINT8 imm;
4130
4131		RDOPARG( imm );
4132		SMH ^= imm;
4133		SET_Z(SMH);
4134		}
4135
4136		/* 64 93: 0110 0100 1001 0011 xxxx xxxx */
4137		void upd7810_device::XRI_EOM_xx()
4138		{
4139		/* only bits #1 and #5 can be read */
4140		UINT8 eom = EOM & 0x22;
4141		UINT8 imm;
4142
4143		RDOPARG( imm );
4144		/* only bits #1 and #5 can be read */
4145		EOM = eom ^ imm;
4146		SET_Z(EOM);
4147		upd7810_write_EOM();
4148		}
4149
4150		/* 64 95: 0110 0100 1001 0101 xxxx xxxx */
4151		void upd7810_device::XRI_TMM_xx()
4152		{
4153		UINT8 imm;
4154
4155		RDOPARG( imm );
4156		TMM ^= imm;
4157		SET_Z(TMM);
4158		}
4159
4160		/* 64 98: 0110 0100 1001 1000 xxxx xxxx */
4161		void upd7810_device::ORI_ANM_xx()
4162		{
4163		UINT8 imm;
4164
4165		RDOPARG( imm );
4166		ANM \|= imm;
4167		SET_Z(ANM);
4168		}
4169
4170		/* 64 99: 0110 0100 1001 1001 xxxx xxxx */
4171		void upd7810_device::ORI_SMH_xx()
4172		{
4173		UINT8 imm;
4174
4175		RDOPARG( imm );
4176		SMH \|= imm;
4177		SET_Z(SMH);
4178		}
4179
4180		/* 64 9b: 0110 0100 1001 1011 xxxx xxxx */
4181		void upd7810_device::ORI_EOM_xx()
4182		{
4183		/* only bits #1 and #5 can be read */
4184		UINT8 eom = EOM & 0x22;
4185		UINT8 imm;
4186
4187		RDOPARG( imm );
4188		/* only bits #1 and #5 can be read */
4189		EOM = eom \| imm;
4190		SET_Z(EOM);
4191		upd7810_write_EOM();
4192		}
4193
4194		/* 64 9d: 0110 0100 1001 1101 xxxx xxxx */
4195		void upd7810_device::ORI_TMM_xx()
4196		{
4197		UINT8 imm;
4198
4199		RDOPARG( imm );
4200		TMM \|= imm;
4201		SET_Z(TMM);
4202		}
4203
4204		/* 64 a0: 0110 0100 1010 0000 xxxx xxxx */
4205		void upd7810_device::ADINC_ANM_xx()
4206		{
4207		UINT8 tmp, imm;
4208
4209		RDOPARG( imm );
4210		tmp = ANM + imm;
4211
4212		ZHC_ADD( tmp, ANM, 0 );
4213		ANM = tmp;
4214		SKIP_NC;
4215		}
4216
4217		/* 64 a1: 0110 0100 1010 0001 xxxx xxxx */
4218		void upd7810_device::ADINC_SMH_xx()
4219		{
4220		UINT8 tmp, imm;
4221
4222		RDOPARG( imm );
4223		tmp = SMH + imm;
4224
4225		ZHC_ADD( tmp, SMH, 0 );
4226		SMH = tmp;
4227		SKIP_NC;
4228		}
4229
4230		/* 64 a3: 0110 0100 1010 0011 xxxx xxxx */
4231		void upd7810_device::ADINC_EOM_xx()
4232		{
4233		/* only bits #1 and #5 can be read */
4234		UINT8 eom = EOM & 0x22;
4235		UINT8 tmp, imm;
4236
4237		RDOPARG( imm );
4238		/* only bits #1 and #5 can be read */
4239		tmp = eom + imm;
4240
4241		ZHC_ADD( tmp, eom, 0 );
4242		EOM = tmp;
4243		SKIP_NC;
4244		upd7810_write_EOM();
4245		}
4246
4247		/* 64 a5: 0110 0100 1010 0101 xxxx xxxx */
4248		void upd7810_device::ADINC_TMM_xx()
4249		{
4250		UINT8 tmp, imm;
4251
4252		RDOPARG( imm );
4253		tmp = TMM + imm;
4254
4255		ZHC_ADD( tmp, TMM, 0 );
4256		TMM = tmp;
4257		SKIP_NC;
4258		}
4259
4260		/* 64 a8: 0110 0100 1010 1000 xxxx xxxx */
4261		void upd7810_device::GTI_ANM_xx()
4262		{
4263		UINT8 imm;
4264		UINT16 tmp;
4265
4266		RDOPARG( imm );
4267		tmp = ANM - imm - 1;
4268		ZHC_SUB( tmp, ANM, 0 );
4269
4270		SKIP_NC;
4271		}
4272
4273		/* 64 a9: 0110 0100 1010 1001 xxxx xxxx */
4274		void upd7810_device::GTI_SMH_xx()
4275		{
4276		UINT8 imm;
4277		UINT16 tmp;
4278
4279		RDOPARG( imm );
4280		tmp = SMH - imm - 1;
4281		ZHC_SUB( tmp, SMH, 0 );
4282
4283		SKIP_NC;
4284		}
4285
4286		/* 64 ab: 0110 0100 1010 1011 xxxx xxxx */
4287		void upd7810_device::GTI_EOM_xx()
4288		{
4289		/* only bits #1 and #5 can be read */
4290		UINT8 eom = EOM & 0x22;
4291		UINT8 imm;
4292		UINT16 tmp;
4293
4294		RDOPARG( imm );
4295		tmp = eom - imm - 1;
4296		ZHC_SUB( tmp, eom, 0 );
4297
4298		SKIP_NC;
4299		}
4300
4301		/* 64 ad: 0110 0100 1010 1101 xxxx xxxx */
4302		void upd7810_device::GTI_TMM_xx()
4303		{
4304		UINT8 imm;
4305		UINT16 tmp;
4306
4307		RDOPARG( imm );
4308		tmp = TMM - imm - 1;
4309		ZHC_SUB( tmp, TMM, 0 );
4310
4311		SKIP_NC;
4312		}
4313
4314		/* 64 b0: 0110 0100 1011 0000 xxxx xxxx */
4315		void upd7810_device::SUINB_ANM_xx()
4316		{
4317		UINT8 tmp, imm;
4318
4319		RDOPARG( imm );
4320		tmp = ANM - imm;
4321		ZHC_SUB( tmp, ANM, 0 );
4322		ANM = tmp;
4323		SKIP_NC;
4324		}
4325
4326		/* 64 b1: 0110 0100 1011 0001 xxxx xxxx */
4327		void upd7810_device::SUINB_SMH_xx()
4328		{
4329		UINT8 tmp, imm;
4330
4331		RDOPARG( imm );
4332		tmp = SMH - imm;
4333		ZHC_SUB( tmp, SMH, 0 );
4334		SMH = tmp;
4335		SKIP_NC;
4336		}
4337
4338		/* 64 b3: 0110 0100 1011 0011 xxxx xxxx */
4339		void upd7810_device::SUINB_EOM_xx()
4340		{
4341		/* only bits #1 and #5 can be read */
4342		UINT8 eom = EOM & 0x22;
4343		UINT8 tmp, imm;
4344
4345		RDOPARG( imm );
4346		tmp = eom - imm;
4347		ZHC_SUB( tmp, eom, 0 );
4348		EOM = tmp;
4349		SKIP_NC;
4350		upd7810_write_EOM();
4351		}
4352
4353		/* 64 b5: 0110 0100 1011 0101 xxxx xxxx */
4354		void upd7810_device::SUINB_TMM_xx()
4355		{
4356		UINT8 tmp, imm;
4357
4358		RDOPARG( imm );
4359		tmp = TMM - imm;
4360		ZHC_SUB( tmp, TMM, 0 );
4361		TMM = tmp;
4362		SKIP_NC;
4363		}
4364
4365		/* 64 b8: 0110 0100 1011 1000 xxxx xxxx */
4366		void upd7810_device::LTI_ANM_xx()
4367		{
4368		UINT8 tmp, imm;
4369
4370		RDOPARG( imm );
4371		tmp = ANM - imm;
4372		ZHC_SUB( tmp, ANM, 0 );
4373		SKIP_CY;
4374		}
4375
4376		/* 64 b9: 0110 0100 1011 1001 xxxx xxxx */
4377		void upd7810_device::LTI_SMH_xx()
4378		{
4379		UINT8 tmp, imm;
4380
4381		RDOPARG( imm );
4382		tmp = SMH - imm;
4383		ZHC_SUB( tmp, SMH, 0 );
4384		SKIP_CY;
4385		}
4386
4387		/* 64 bb: 0110 0100 1011 1011 xxxx xxxx */
4388		void upd7810_device::LTI_EOM_xx()
4389		{
4390		/* only bits #1 and #5 can be read */
4391		UINT8 eom = EOM & 0x22;
4392		UINT8 tmp, imm;
4393
4394		RDOPARG( imm );
4395		tmp = eom - imm;
4396		ZHC_SUB( tmp, eom, 0 );
4397		SKIP_CY;
4398		}
4399
4400		/* 64 bd: 0110 0100 1011 1101 xxxx xxxx */
4401		void upd7810_device::LTI_TMM_xx()
4402		{
4403		UINT8 tmp, imm;
4404
4405		RDOPARG( imm );
4406		tmp = TMM - imm;
4407		ZHC_SUB( tmp, TMM, 0 );
4408		SKIP_CY;
4409		}
4410
4411		/* 64 c0: 0110 0100 1100 0000 xxxx xxxx */
4412		void upd7810_device::ADI_ANM_xx()
4413		{
4414		UINT8 tmp, imm;
4415
4416		RDOPARG( imm );
4417		tmp = ANM + imm;
4418
4419		ZHC_ADD( tmp, ANM, 0 );
4420		ANM = tmp;
4421		}
4422
4423		/* 64 c1: 0110 0100 1100 0001 xxxx xxxx */
4424		void upd7810_device::ADI_SMH_xx()
4425		{
4426		UINT8 tmp, imm;
4427
4428		RDOPARG( imm );
4429		tmp = SMH + imm;
4430
4431		ZHC_ADD( tmp, SMH, 0 );
4432		SMH = tmp;
4433		}
4434
4435		/* 64 c3: 0110 0100 1100 0011 xxxx xxxx */
4436		void upd7810_device::ADI_EOM_xx()
4437		{
4438		/* only bits #1 and #5 can be read */
4439		UINT8 eom = EOM & 0x22;
4440		UINT8 tmp, imm;
4441
4442		RDOPARG( imm );
4443		tmp = eom + imm;
4444
4445		ZHC_ADD( tmp, eom, 0 );
4446		EOM = tmp;
4447		upd7810_write_EOM();
4448		}
4449
4450		/* 64 c5: 0110 0100 1100 0101 xxxx xxxx */
4451		void upd7810_device::ADI_TMM_xx()
4452		{
4453		UINT8 tmp, imm;
4454
4455		RDOPARG( imm );
4456		tmp = TMM + imm;
4457
4458		ZHC_ADD( tmp, TMM, 0 );
4459		TMM = tmp;
4460		}
4461
4462		/* 64 c8: 0110 0100 1100 1000 xxxx xxxx */
4463		void upd7810_device::ONI_ANM_xx()
4464		{
4465		UINT8 imm;
4466
4467		RDOPARG( imm );
4468		if (ANM & imm)
4469		PSW \|= SK;
4470		}
4471
4472		/* 64 c9: 0110 0100 1100 1001 xxxx xxxx */
4473		void upd7810_device::ONI_SMH_xx()
4474		{
4475		UINT8 imm;
4476
4477		RDOPARG( imm );
4478		if (SMH & imm)
4479		PSW \|= SK;
4480		}
4481
4482		/* 64 cb: 0110 0100 1100 1011 xxxx xxxx */
4483		void upd7810_device::ONI_EOM_xx()
4484		{
4485		/* only bits #1 and #5 can be read */
4486		UINT8 eom = EOM & 0x22;
4487		UINT8 imm;
4488
4489		RDOPARG( imm );
4490		if (eom & imm)
4491		PSW \|= SK;
4492		}
4493
4494		/* 64 cd: 0110 0100 1100 1101 xxxx xxxx */
4495		void upd7810_device::ONI_TMM_xx()
4496		{
4497		UINT8 imm;
4498
4499		RDOPARG( imm );
4500		if (TMM & imm)
4501		PSW \|= SK;
4502		}
4503
4504		/* 64 d0: 0110 0100 1101 0000 xxxx xxxx */
4505		void upd7810_device::ACI_ANM_xx()
4506		{
4507		UINT8 tmp, imm;
4508
4509		RDOPARG( imm );
4510		tmp = ANM + imm + (PSW & CY);
4511
4512		ZHC_ADD( tmp, ANM, (PSW & CY) );
4513		ANM = tmp;
4514		}
4515
4516		/* 64 d1: 0110 0100 1101 0001 xxxx xxxx */
4517		void upd7810_device::ACI_SMH_xx()
4518		{
4519		UINT8 tmp, imm;
4520
4521		RDOPARG( imm );
4522		tmp = SMH + imm + (PSW & CY);
4523
4524		ZHC_ADD( tmp, SMH, (PSW & CY) );
4525		SMH = tmp;
4526		}
4527
4528		/* 64 d3: 0110 0100 1101 0011 xxxx xxxx */
4529		void upd7810_device::ACI_EOM_xx()
4530		{
4531		/* only bits #1 and #5 can be read */
4532		UINT8 eom = EOM & 0x22;
4533		UINT8 tmp, imm;
4534
4535		RDOPARG( imm );
4536		tmp = eom + imm + (PSW & CY);
4537
4538		ZHC_ADD( tmp, eom, (PSW & CY) );
4539		EOM = tmp;
4540		upd7810_write_EOM();
4541		}
4542
4543		/* 64 d5: 0110 0100 1101 0101 xxxx xxxx */
4544		void upd7810_device::ACI_TMM_xx()
4545		{
4546		UINT8 tmp, imm;
4547
4548		RDOPARG( imm );
4549		tmp = TMM + imm + (PSW & CY);
4550
4551		ZHC_ADD( tmp, TMM, (PSW & CY) );
4552		TMM = tmp;
4553		}
4554
4555		/* 64 d8: 0110 0100 1101 1000 xxxx xxxx */
4556		void upd7810_device::OFFI_ANM_xx()
4557		{
4558		UINT8 imm;
4559
4560		RDOPARG( imm );
4561		if (0 == (ANM & imm))
4562		PSW \|= SK;
4563		}
4564
4565		/* 64 d9: 0110 0100 1101 1001 xxxx xxxx */
4566		void upd7810_device::OFFI_SMH_xx()
4567		{
4568		UINT8 imm;
4569
4570		RDOPARG( imm );
4571		if (0 == (SMH & imm))
4572		PSW \|= SK;
4573		}
4574
4575		/* 64 db: 0110 0100 1101 1011 xxxx xxxx */
4576		void upd7810_device::OFFI_EOM_xx()
4577		{
4578		/* only bits #1 and #5 can be read */
4579		UINT8 eom = EOM & 0x22;
4580		UINT8 imm;
4581
4582		RDOPARG( imm );
4583		if (0 == (eom & imm))
4584		PSW \|= SK;
4585		}
4586
4587		/* 64 dd: 0110 0100 1101 1101 xxxx xxxx */
4588		void upd7810_device::OFFI_TMM_xx()
4589		{
4590		UINT8 imm;
4591
4592		RDOPARG( imm );
4593		if (0 == (TMM & imm))
4594		PSW \|= SK;
4595		}
4596
4597		/* 64 e0: 0110 0100 1110 0000 xxxx xxxx */
4598		void upd7810_device::SUI_ANM_xx()
4599		{
4600		UINT8 tmp, imm;
4601
4602		RDOPARG( imm );
4603		tmp = ANM - imm;
4604		ZHC_SUB( tmp, ANM, 0 );
4605		ANM = tmp;
4606		}
4607
4608		/* 64 e1: 0110 0100 1110 0001 xxxx xxxx */
4609		void upd7810_device::SUI_SMH_xx()
4610		{
4611		UINT8 tmp, imm;
4612
4613		RDOPARG( imm );
4614		tmp = SMH - imm;
4615		ZHC_SUB( tmp, SMH, 0 );
4616		SMH = tmp;
4617		}
4618
4619		/* 64 e3: 0110 0100 1110 0011 xxxx xxxx */
4620		void upd7810_device::SUI_EOM_xx()
4621		{
4622		/* only bits #1 and #5 can be read */
4623		UINT8 eom = EOM & 0x22;
4624		UINT8 tmp, imm;
4625
4626		RDOPARG( imm );
4627		tmp = eom - imm;
4628		ZHC_SUB( tmp, eom, 0 );
4629		EOM = tmp;
4630		upd7810_write_EOM();
4631		}
4632
4633		/* 64 e5: 0110 0100 1110 0101 xxxx xxxx */
4634		void upd7810_device::SUI_TMM_xx()
4635		{
4636		UINT8 tmp, imm;
4637
4638		RDOPARG( imm );
4639		tmp = TMM - imm;
4640		ZHC_SUB( tmp, TMM, 0 );
4641		TMM = tmp;
4642		}
4643
4644		/* 64 e8: 0110 0100 1110 1000 xxxx xxxx */
4645		void upd7810_device::NEI_ANM_xx()
4646		{
4647		UINT8 tmp, imm;
4648
4649		RDOPARG( imm );
4650		tmp = ANM - imm;
4651		ZHC_SUB( tmp, ANM, 0 );
4652		SKIP_NZ;
4653		}
4654
4655		/* 64 e9: 0110 0100 1110 1001 xxxx xxxx */
4656		void upd7810_device::NEI_SMH_xx()
4657		{
4658		UINT8 tmp, imm;
4659
4660		RDOPARG( imm );
4661		tmp = SMH - imm;
4662		ZHC_SUB( tmp, SMH, 0 );
4663		SKIP_NZ;
4664		}
4665
4666		/* 64 eb: 0110 0100 1110 1011 xxxx xxxx */
4667		void upd7810_device::NEI_EOM_xx()
4668		{
4669		/* only bits #1 and #5 can be read */
4670		UINT8 eom = EOM & 0x22;
4671		UINT8 tmp, imm;
4672
4673		RDOPARG( imm );
4674		tmp = eom - imm;
4675		ZHC_SUB( tmp, eom, 0 );
4676		SKIP_NZ;
4677		}
4678
4679		/* 64 ed: 0110 0100 1110 1101 xxxx xxxx */
4680		void upd7810_device::NEI_TMM_xx()
4681		{
4682		UINT8 tmp, imm;
4683
4684		RDOPARG( imm );
4685		tmp = TMM - imm;
4686		ZHC_SUB( tmp, TMM, 0 );
4687		SKIP_NZ;
4688		}
4689
4690		/* 64 f0: 0110 0100 1111 0000 xxxx xxxx */
4691		void upd7810_device::SBI_ANM_xx()
4692		{
4693		UINT8 tmp, imm;
4694
4695		RDOPARG( imm );
4696		tmp = ANM - imm - (PSW & CY);
4697		ZHC_SUB( tmp, ANM, (PSW & CY) );
4698		ANM = tmp;
4699		}
4700
4701		/* 64 f1: 0110 0100 1111 0001 xxxx xxxx */
4702		void upd7810_device::SBI_SMH_xx()
4703		{
4704		UINT8 tmp, imm;
4705
4706		RDOPARG( imm );
4707		tmp = SMH - imm - (PSW & CY);
4708		ZHC_SUB( tmp, SMH, (PSW & CY) );
4709		SMH = tmp;
4710		}
4711
4712		/* 64 f3: 0110 0100 1111 0011 xxxx xxxx */
4713		void upd7810_device::SBI_EOM_xx()
4714		{
4715		/* only bits #1 and #5 can be read */
4716		UINT8 eom = EOM & 0x22;
4717		UINT8 tmp, imm;
4718
4719		RDOPARG( imm );
4720		tmp = eom - imm - (PSW & CY);
4721		ZHC_SUB( tmp, eom, (PSW & CY) );
4722		EOM = tmp;
4723		upd7810_write_EOM();
4724		}
4725
4726		/* 64 f5: 0110 0100 1111 0101 xxxx xxxx */
4727		void upd7810_device::SBI_TMM_xx()
4728		{
4729		UINT8 tmp, imm;
4730
4731		RDOPARG( imm );
4732		tmp = TMM - imm - (PSW & CY);
4733		ZHC_SUB( tmp, TMM, (PSW & CY) );
4734		TMM = tmp;
4735		}
4736
4737		/* 64 f8: 0110 0100 1111 1000 xxxx xxxx */
4738		void upd7810_device::EQI_ANM_xx()
4739		{
4740		UINT8 tmp, imm;
4741
4742		RDOPARG( imm );
4743		tmp = ANM - imm;
4744		ZHC_SUB( tmp, ANM, 0 );
4745		SKIP_Z;
4746		}
4747
4748		/* 64 f9: 0110 0100 1111 1001 xxxx xxxx */
4749		void upd7810_device::EQI_SMH_xx()
4750		{
4751		UINT8 tmp, imm;
4752
4753		RDOPARG( imm );
4754		tmp = SMH - imm;
4755		ZHC_SUB( tmp, SMH, 0 );
4756		SKIP_Z;
4757		}
4758
4759		/* 64 fb: 0110 0100 1111 1011 xxxx xxxx */
4760		void upd7810_device::EQI_EOM_xx()
4761		{
4762		/* only bits #1 and #5 can be read */
4763		UINT8 eom = EOM & 0x22;
4764		UINT8 tmp, imm;
4765
4766		RDOPARG( imm );
4767		tmp = eom - imm;
4768		ZHC_SUB( tmp, eom, 0 );
4769		SKIP_Z;
4770		}
4771
4772		/* 64 fd: 0110 0100 1111 1101 xxxx xxxx */
4773		void upd7810_device::EQI_TMM_xx()
4774		{
4775		UINT8 tmp, imm;
4776
4777		RDOPARG( imm );
4778		tmp = TMM - imm;
4779		ZHC_SUB( tmp, TMM, 0 );
4780		SKIP_Z;
4781		}
4782
4783		/* prefix 70 */
4784		/* 70 0e: 0111 0000 0000 1110 llll llll hhhh hhhh */
4785		void upd7810_device::SSPD_w()
4786		{
4787		PAIR ea;
4788		ea.d = 0;
4789
4790		RDOPARG( ea.b.l );
4791		RDOPARG( ea.b.h );
4792		WM( ea.d, SPL );
4793		WM( ea.d + 1, SPH );
4794		}
4795
4796		/* 70 0f: 0111 0000 0000 1111 llll llll hhhh hhhh */
4797		void upd7810_device::LSPD_w()
4798		{
4799		PAIR ea;
4800		ea.d = 0;
4801
4802		RDOPARG( ea.b.l );
4803		RDOPARG( ea.b.h );
4804		SPL = RM( ea.d );
4805		SPH = RM( ea.d + 1 );
4806		}
4807
4808		/* 70 1e: 0111 0000 0001 1110 llll llll hhhh hhhh */
4809		void upd7810_device::SBCD_w()
4810		{
4811		PAIR ea;
4812		ea.d = 0;
4813
4814		RDOPARG( ea.b.l );
4815		RDOPARG( ea.b.h );
4816		WM( ea.d, C );
4817		WM( ea.d + 1, B );
4818		}
4819
4820		/* 70 1f: 0111 0000 0001 1111 llll llll hhhh hhhh */
4821		void upd7810_device::LBCD_w()
4822		{
4823		PAIR ea;
4824		ea.d = 0;
4825
4826		RDOPARG( ea.b.l );
4827		RDOPARG( ea.b.h );
4828		C = RM( ea.d );
4829		B = RM( ea.d + 1 );
4830		}
4831
4832		/* 70 2e: 0111 0000 0010 1110 llll llll hhhh hhhh */
4833		void upd7810_device::SDED_w()
4834		{
4835		PAIR ea;
4836		ea.d = 0;
4837
4838		RDOPARG( ea.b.l );
4839		RDOPARG( ea.b.h );
4840		WM( ea.d, E );
4841		WM( ea.d + 1, D );
4842		}
4843
4844		/* 70 2f: 0111 0000 0010 1111 llll llll hhhh hhhh */
4845		void upd7810_device::LDED_w()
4846		{
4847		PAIR ea;
4848		ea.d = 0;
4849
4850		RDOPARG( ea.b.l );
4851		RDOPARG( ea.b.h );
4852		E = RM( ea.d );
4853		D = RM( ea.d + 1 );
4854		}
4855
4856		/* 70 3e: 0111 0000 0011 1110 llll llll hhhh hhhh */
4857		void upd7810_device::SHLD_w()
4858		{
4859		PAIR ea;
4860		ea.d = 0;
4861
4862		RDOPARG( ea.b.l );
4863		RDOPARG( ea.b.h );
4864		WM( ea.d, L );
4865		WM( ea.d + 1, H );
4866		}
4867
4868		/* 70 3f: 0111 0000 0011 1111 llll llll hhhh hhhh */
4869		void upd7810_device::LHLD_w()
4870		{
4871		PAIR ea;
4872		ea.d = 0;
4873
4874		RDOPARG( ea.b.l );
4875		RDOPARG( ea.b.h );
4876		L = RM( ea.d );
4877		H = RM( ea.d + 1 );
4878		}
4879
4880		/* 70 41: 0111 0000 0100 0001 */
4881		void upd7810_device::EADD_EA_A()
4882		{
4883		UINT16 tmp;
4884		tmp = EA + A;
4885		ZHC_ADD( tmp, EA, 0 );
4886		EA = tmp;
4887		}
4888
4889		/* 70 42: 0111 0000 0100 0010 */
4890		void upd7810_device::EADD_EA_B()
4891		{
4892		UINT16 tmp;
4893		tmp = EA + B;
4894		ZHC_ADD( tmp, EA, 0 );
4895		EA = tmp;
4896		}
4897
4898		/* 70 43: 0111 0000 0100 0011 */
4899		void upd7810_device::EADD_EA_C()
4900		{
4901		UINT16 tmp;
4902		tmp = EA + C;
4903		ZHC_ADD( tmp, EA, 0 );
4904		EA = tmp;
4905		}
4906
4907		/* 70 61: 0111 0000 0110 0001 */
4908		void upd7810_device::ESUB_EA_A()
4909		{
4910		UINT16 tmp;
4911		tmp = EA - A;
4912		ZHC_SUB( tmp, EA, 0 );
4913		EA = tmp;
4914		}
4915
4916		/* 70 62: 0111 0000 0110 0010 */
4917		void upd7810_device::ESUB_EA_B()
4918		{
4919		UINT16 tmp;
4920		tmp = EA - B;
4921		ZHC_SUB( tmp, EA, 0 );
4922		EA = tmp;
4923		}
4924
4925		/* 70 63: 0111 0000 0110 0011 */
4926		void upd7810_device::ESUB_EA_C()
4927		{
4928		UINT16 tmp;
4929		tmp = EA - C;
4930		ZHC_SUB( tmp, EA, 0 );
4931		EA = tmp;
4932		}
4933
4934		/* 70 68: 0111 0000 0110 1000 llll llll hhhh hhhh */
4935		void upd7810_device::MOV_V_w()
4936		{
4937		PAIR ea;
4938		ea.d = 0;
4939
4940		RDOPARG( ea.b.l );
4941		RDOPARG( ea.b.h );
4942		V = RM( ea.d );
4943		}
4944
4945		/* 70 69: 0111 0000 0110 1001 llll llll hhhh hhhh */
4946		void upd7810_device::MOV_A_w()
4947		{
4948		PAIR ea;
4949		ea.d = 0;
4950
4951		RDOPARG( ea.b.l );
4952		RDOPARG( ea.b.h );
4953		A = RM( ea.d );
4954		}
4955
4956		/* 70 6a: 0111 0000 0110 1010 llll llll hhhh hhhh */
4957		void upd7810_device::MOV_B_w()
4958		{
4959		PAIR ea;
4960		ea.d = 0;
4961
4962		RDOPARG( ea.b.l );
4963		RDOPARG( ea.b.h );
4964		B = RM( ea.d );
4965		}
4966
4967		/* 70 6b: 0111 0000 0110 1011 llll llll hhhh hhhh */
4968		void upd7810_device::MOV_C_w()
4969		{
4970		PAIR ea;
4971		ea.d = 0;
4972
4973		RDOPARG( ea.b.l );
4974		RDOPARG( ea.b.h );
4975		C = RM( ea.d );
4976		}
4977
4978		/* 70 6c: 0111 0000 0110 1100 llll llll hhhh hhhh */
4979		void upd7810_device::MOV_D_w()
4980		{
4981		PAIR ea;
4982		ea.d = 0;
4983
4984		RDOPARG( ea.b.l );
4985		RDOPARG( ea.b.h );
4986		D = RM( ea.d );
4987		}
4988
4989		/* 70 6d: 0111 0000 0110 1101 llll llll hhhh hhhh */
4990		void upd7810_device::MOV_E_w()
4991		{
4992		PAIR ea;
4993		ea.d = 0;
4994
4995		RDOPARG( ea.b.l );
4996		RDOPARG( ea.b.h );
4997		E = RM( ea.d );
4998		}
4999
5000		/* 70 6e: 0111 0000 0110 1110 llll llll hhhh hhhh */
5001		void upd7810_device::MOV_H_w()
5002		{
5003		PAIR ea;
5004		ea.d = 0;
5005
5006		RDOPARG( ea.b.l );
5007		RDOPARG( ea.b.h );
5008		H = RM( ea.d );
5009		}
5010
5011		/* 70 6f: 0111 0000 0110 1111 llll llll hhhh hhhh */
5012		void upd7810_device::MOV_L_w()
5013		{
5014		PAIR ea;
5015		ea.d = 0;
5016
5017		RDOPARG( ea.b.l );
5018		RDOPARG( ea.b.h );
5019		L = RM( ea.d );
5020		}
5021
5022		/* 70 78: 0111 0000 0111 1000 llll llll hhhh hhhh */
5023		void upd7810_device::MOV_w_V()
5024		{
5025		PAIR ea;
5026		ea.d = 0;
5027
5028		RDOPARG( ea.b.l );
5029		RDOPARG( ea.b.h );
5030		WM( ea.d, V );
5031		}
5032
5033		/* 70 79: 0111 0000 0111 1001 llll llll hhhh hhhh */
5034		void upd7810_device::MOV_w_A()
5035		{
5036		PAIR ea;
5037		ea.d = 0;
5038
5039		RDOPARG( ea.b.l );
5040		RDOPARG( ea.b.h );
5041		WM( ea.d, A );
5042		}
5043
5044		/* 70 7a: 0111 0000 0111 1010 llll llll hhhh hhhh */
5045		void upd7810_device::MOV_w_B()
5046		{
5047		PAIR ea;
5048		ea.d = 0;
5049
5050		RDOPARG( ea.b.l );
5051		RDOPARG( ea.b.h );
5052		WM( ea.d, B );
5053		}
5054
5055		/* 70 7b: 0111 0000 0111 1011 llll llll hhhh hhhh */
5056		void upd7810_device::MOV_w_C()
5057		{
5058		PAIR ea;
5059		ea.d = 0;
5060
5061		RDOPARG( ea.b.l );
5062		RDOPARG( ea.b.h );
5063		WM( ea.d, C );
5064		}
5065
5066		/* 70 7c: 0111 0000 0111 1100 llll llll hhhh hhhh */
5067		void upd7810_device::MOV_w_D()
5068		{
5069		PAIR ea;
5070		ea.d = 0;
5071
5072		RDOPARG( ea.b.l );
5073		RDOPARG( ea.b.h );
5074		WM( ea.d, D );
5075		}
5076
5077		/* 70 7d: 0111 0000 0111 1101 llll llll hhhh hhhh */
5078		void upd7810_device::MOV_w_E()
5079		{
5080		PAIR ea;
5081		ea.d = 0;
5082
5083		RDOPARG( ea.b.l );
5084		RDOPARG( ea.b.h );
5085		WM( ea.d, E );
5086		}
5087
5088		/* 70 7e: 0111 0000 0111 1110 llll llll hhhh hhhh */
5089		void upd7810_device::MOV_w_H()
5090		{
5091		PAIR ea;
5092		ea.d = 0;
5093
5094		RDOPARG( ea.b.l );
5095		RDOPARG( ea.b.h );
5096		WM( ea.d, H );
5097		}
5098
5099		/* 70 7f: 0111 0000 0111 1111 llll llll hhhh hhhh */
5100		void upd7810_device::MOV_w_L()
5101		{
5102		PAIR ea;
5103		ea.d = 0;
5104
5105		RDOPARG( ea.b.l );
5106		RDOPARG( ea.b.h );
5107		WM( ea.d, L );
5108		}
5109
5110		/* 70 89: 0111 0000 1000 1001 */
5111		void upd7810_device::ANAX_B()
5112		{
5113		A &= RM( BC );
5114		SET_Z(A);
5115		}
5116
5117		/* 70 8a: 0111 0000 1000 1010 */
5118		void upd7810_device::ANAX_D()
5119		{
5120		A &= RM( DE );
5121		SET_Z(A);
5122		}
5123
5124		/* 70 8b: 0111 0000 1000 1011 */
5125		void upd7810_device::ANAX_H()
5126		{
5127		A &= RM( HL );
5128		SET_Z(A);
5129		}
5130
5131		/* 70 8c: 0111 0000 1000 1100 */
5132		void upd7810_device::ANAX_Dp()
5133		{
5134		A &= RM( DE );
5135		DE++;
5136		SET_Z(A);
5137		}
5138
5139		/* 70 8d: 0111 0000 1000 1101 */
5140		void upd7810_device::ANAX_Hp()
5141		{
5142		A &= RM( HL );
5143		HL++;
5144		SET_Z(A);
5145		}
5146
5147		/* 70 8e: 0111 0000 1000 1110 */
5148		void upd7810_device::ANAX_Dm()
5149		{
5150		A &= RM( DE );
5151		DE--;
5152		SET_Z(A);
5153		}
5154
5155		/* 70 8f: 0111 0000 1000 1111 */
5156		void upd7810_device::ANAX_Hm()
5157		{
5158		A &= RM( HL );
5159		HL--;
5160		SET_Z(A);
5161		}
5162
5163		/* 70 91: 0111 0000 1001 0001 */
5164		void upd7810_device::XRAX_B()
5165		{
5166		A ^= RM( BC );
5167		SET_Z(A);
5168		}
5169
5170		/* 70 92: 0111 0000 1001 0010 */
5171		void upd7810_device::XRAX_D()
5172		{
5173		A ^= RM( DE );
5174		SET_Z(A);
5175		}
5176
5177		/* 70 93: 0111 0000 1001 0011 */
5178		void upd7810_device::XRAX_H()
5179		{
5180		A ^= RM( HL );
5181		SET_Z(A);
5182		}
5183
5184		/* 70 94: 0111 0000 1001 0100 */
5185		void upd7810_device::XRAX_Dp()
5186		{
5187		A ^= RM( DE );
5188		DE++;
5189		SET_Z(A);
5190		}
5191
5192		/* 70 95: 0111 0000 1001 0101 */
5193		void upd7810_device::XRAX_Hp()
5194		{
5195		A ^= RM( HL );
5196		HL++;
5197		SET_Z(A);
5198		}
5199
5200		/* 70 96: 0111 0000 1001 0110 */
5201		void upd7810_device::XRAX_Dm()
5202		{
5203		A ^= RM( DE );
5204		DE--;
5205		SET_Z(A);
5206		}
5207
5208		/* 70 97: 0111 0000 1001 0111 */
5209		void upd7810_device::XRAX_Hm()
5210		{
5211		A ^= RM( HL );
5212		HL--;
5213		SET_Z(A);
5214		}
5215
5216		/* 70 99: 0111 0000 1001 1001 */
5217		void upd7810_device::ORAX_B()
5218		{
5219		A \|= RM( BC );
5220		SET_Z(A);
5221		}
5222
5223		/* 70 9a: 0111 0000 1001 1010 */
5224		void upd7810_device::ORAX_D()
5225		{
5226		A \|= RM( DE );
5227		SET_Z(A);
5228		}
5229
5230		/* 70 9b: 0111 0000 1001 1011 */
5231		void upd7810_device::ORAX_H()
5232		{
5233		A \|= RM( HL );
5234		SET_Z(A);
5235		}
5236
5237		/* 70 9c: 0111 0000 1001 0100 */
5238		void upd7810_device::ORAX_Dp()
5239		{
5240		A \|= RM( DE );
5241		DE++;
5242		SET_Z(A);
5243		}
5244
5245		/* 70 9d: 0111 0000 1001 1101 */
5246		void upd7810_device::ORAX_Hp()
5247		{
5248		A \|= RM( HL );
5249		HL++;
5250		SET_Z(A);
5251		}
5252
5253		/* 70 9e: 0111 0000 1001 1110 */
5254		void upd7810_device::ORAX_Dm()
5255		{
5256		A \|= RM( DE );
5257		DE--;
5258		SET_Z(A);
5259		}
5260
5261		/* 70 9f: 0111 0000 1001 1111 */
5262		void upd7810_device::ORAX_Hm()
5263		{
5264		A \|= RM( HL );
5265		HL--;
5266		SET_Z(A);
5267		}
5268
5269		/* 70 a1: 0111 0000 1010 0001 */
5270		void upd7810_device::ADDNCX_B()
5271		{
5272		UINT8 tmp = A + RM( BC );
5273		ZHC_ADD( tmp, A, 0 );
5274		A = tmp;
5275		SKIP_NC;
5276		}
5277
5278		/* 70 a2: 0111 0000 1010 0010 */
5279		void upd7810_device::ADDNCX_D()
5280		{
5281		UINT8 tmp = A + RM( DE );
5282		ZHC_ADD( tmp, A, 0 );
5283		A = tmp;
5284		SKIP_NC;
5285		}
5286
5287		/* 70 a3: 0111 0000 1010 0011 */
5288		void upd7810_device::ADDNCX_H()
5289		{
5290		UINT8 tmp = A + RM( HL );
5291		ZHC_ADD( tmp, A, 0 );
5292		A = tmp;
5293		SKIP_NC;
5294		}
5295
5296		/* 70 a4: 0111 0000 1010 0100 */
5297		void upd7810_device::ADDNCX_Dp()
5298		{
5299		UINT8 tmp = A + RM( DE );
5300		DE++;
5301		ZHC_ADD( tmp, A, 0 );
5302		A = tmp;
5303		SKIP_NC;
5304		}
5305
5306		/* 70 a5: 0111 0000 1010 0101 */
5307		void upd7810_device::ADDNCX_Hp()
5308		{
5309		UINT8 tmp = A + RM( HL );
5310		HL++;
5311		ZHC_ADD( tmp, A, 0 );
5312		A = tmp;
5313		SKIP_NC;
5314		}
5315
5316		/* 70 a6: 0111 0000 1010 0110 */
5317		void upd7810_device::ADDNCX_Dm()
5318		{
5319		UINT8 tmp = A + RM( DE );
5320		DE--;
5321		ZHC_ADD( tmp, A, 0 );
5322		A = tmp;
5323		SKIP_NC;
5324		}
5325
5326		/* 70 a7: 0111 0000 1010 0111 */
5327		void upd7810_device::ADDNCX_Hm()
5328		{
5329		UINT8 tmp = A + RM( HL );
5330		HL--;
5331		ZHC_ADD( tmp, A, 0 );
5332		A = tmp;
5333		SKIP_NC;
5334		}
5335
5336		/* 70 a9: 0111 0000 1010 1001 */
5337		void upd7810_device::GTAX_B()
5338		{
5339		UINT16 tmp = A - RM( BC ) - 1;
5340		ZHC_SUB( tmp, A, 0 );
5341		SKIP_NC;
5342		}
5343
5344		/* 70 aa: 0111 0000 1010 1010 */
5345		void upd7810_device::GTAX_D()
5346		{
5347		UINT16 tmp = A - RM( DE ) - 1;
5348		ZHC_SUB( tmp, A, 0 );
5349		SKIP_NC;
5350		}
5351
5352		/* 70 ab: 0111 0000 1010 1011 */
5353		void upd7810_device::GTAX_H()
5354		{
5355		UINT16 tmp = A - RM( HL ) - 1;
5356		ZHC_SUB( tmp, A, 0 );
5357		SKIP_NC;
5358		}
5359
5360		/* 70 ac: 0111 0000 1010 1100 */
5361		void upd7810_device::GTAX_Dp()
5362		{
5363		UINT16 tmp = A - RM( DE ) - 1;
5364		DE++;
5365		ZHC_SUB( tmp, A, 0 );
5366		SKIP_NC;
5367		}
5368
5369		/* 70 ad: 0111 0000 1010 1101 */
5370		void upd7810_device::GTAX_Hp()
5371		{
5372		UINT16 tmp = A - RM( HL ) - 1;
5373		HL++;
5374		ZHC_SUB( tmp, A, 0 );
5375		SKIP_NC;
5376		}
5377
5378		/* 70 ae: 0111 0000 1010 1110 */
5379		void upd7810_device::GTAX_Dm()
5380		{
5381		UINT16 tmp = A - RM( DE ) - 1;
5382		DE--;
5383		ZHC_SUB( tmp, A, 0 );
5384		SKIP_NC;
5385		}
5386
5387		/* 70 af: 0111 0000 1010 1111 */
5388		void upd7810_device::GTAX_Hm()
5389		{
5390		UINT16 tmp = A - RM( HL ) - 1;
5391		HL--;
5392		ZHC_SUB( tmp, A, 0 );
5393		SKIP_NC;
5394		}
5395
5396		/* 70 b1: 0111 0000 1011 0001 */
5397		void upd7810_device::SUBNBX_B()
5398		{
5399		UINT8 tmp = A - RM( BC );
5400		ZHC_SUB( tmp, A, 0 );
5401		A = tmp;
5402		SKIP_NC;
5403		}
5404
5405		/* 70 b2: 0111 0000 1011 0010 */
5406		void upd7810_device::SUBNBX_D()
5407		{
5408		UINT8 tmp = A - RM( DE );
5409		ZHC_SUB( tmp, A, 0 );
5410		A = tmp;
5411		SKIP_NC;
5412		}
5413
5414		/* 70 b3: 0111 0000 1011 0011 */
5415		void upd7810_device::SUBNBX_H()
5416		{
5417		UINT8 tmp = A - RM( HL );
5418		ZHC_SUB( tmp, A, 0 );
5419		A = tmp;
5420		SKIP_NC;
5421		}
5422
5423		/* 70 b4: 0111 0000 1011 0100 */
5424		void upd7810_device::SUBNBX_Dp()
5425		{
5426		UINT8 tmp = A - RM( DE );
5427		DE++;
5428		ZHC_SUB( tmp, A, 0 );
5429		A = tmp;
5430		SKIP_NC;
5431		}
5432
5433		/* 70 b5: 0111 0000 1011 0101 */
5434		void upd7810_device::SUBNBX_Hp()
5435		{
5436		UINT8 tmp = A - RM( HL );
5437		HL++;
5438		ZHC_SUB( tmp, A, 0 );
5439		A = tmp;
5440		SKIP_NC;
5441		}
5442
5443		/* 70 b6: 0111 0000 1011 0110 */
5444		void upd7810_device::SUBNBX_Dm()
5445		{
5446		UINT8 tmp = A - RM( DE );
5447		DE--;
5448		ZHC_SUB( tmp, A, 0 );
5449		A = tmp;
5450		SKIP_NC;
5451		}
5452
5453		/* 70 b7: 0111 0000 1011 0111 */
5454		void upd7810_device::SUBNBX_Hm()
5455		{
5456		UINT8 tmp = A - RM( HL );
5457		HL--;
5458		ZHC_SUB( tmp, A, 0 );
5459		A = tmp;
5460		SKIP_NC;
5461		}
5462
5463		/* 70 b9: 0111 0000 1011 1001 */
5464		void upd7810_device::LTAX_B()
5465		{
5466		UINT8 tmp = A - RM( BC );
5467		ZHC_SUB( tmp, A, 0 );
5468		SKIP_CY;
5469		}
5470
5471		/* 70 ba: 0111 0000 1011 1010 */
5472		void upd7810_device::LTAX_D()
5473		{
5474		UINT8 tmp = A - RM( DE );
5475		ZHC_SUB( tmp, A, 0 );
5476		SKIP_CY;
5477		}
5478
5479		/* 70 bb: 0111 0000 1011 1011 */
5480		void upd7810_device::LTAX_H()
5481		{
5482		UINT8 tmp = A - RM( HL );
5483		ZHC_SUB( tmp, A, 0 );
5484		SKIP_CY;
5485		}
5486
5487		/* 70 bc: 0111 0000 1011 1100 */
5488		void upd7810_device::LTAX_Dp()
5489		{
5490		UINT8 tmp = A - RM( DE );
5491		DE++;
5492		ZHC_SUB( tmp, A, 0 );
5493		SKIP_CY;
5494		}
5495
5496		/* 70 bd: 0111 0000 1011 1101 */
5497		void upd7810_device::LTAX_Hp()
5498		{
5499		UINT8 tmp = A - RM( HL );
5500		HL++;
5501		ZHC_SUB( tmp, A, 0 );
5502		SKIP_CY;
5503		}
5504
5505		/* 70 be: 0111 0000 1011 1110 */
5506		void upd7810_device::LTAX_Dm()
5507		{
5508		UINT8 tmp = A - RM( DE );
5509		DE--;
5510		ZHC_SUB( tmp, A, 0 );
5511		SKIP_CY;
5512		}
5513
5514		/* 70 bf: 0111 0000 1011 1111 */
5515		void upd7810_device::LTAX_Hm()
5516		{
5517		UINT8 tmp = A - RM( HL );
5518		HL--;
5519		ZHC_SUB( tmp, A, 0 );
5520		SKIP_CY;
5521		}
5522
5523		/* 70 c1: 0111 0000 1100 0001 */
5524		void upd7810_device::ADDX_B()
5525		{
5526		UINT8 tmp = A + RM( BC );
5527		ZHC_ADD( tmp, A, 0 );
5528		A = tmp;
5529		}
5530
5531		/* 70 c2: 0111 0000 1100 0010 */
5532		void upd7810_device::ADDX_D()
5533		{
5534		UINT8 tmp = A + RM( DE );
5535		ZHC_ADD( tmp, A, 0 );
5536		A = tmp;
5537		}
5538
5539		/* 70 c3: 0111 0000 1100 0011 */
5540		void upd7810_device::ADDX_H()
5541		{
5542		UINT8 tmp = A + RM( HL );
5543		ZHC_ADD( tmp, A, 0 );
5544		A = tmp;
5545		}
5546
5547		/* 70 c4: 0111 0000 1100 0100 */
5548		void upd7810_device::ADDX_Dp()
5549		{
5550		UINT8 tmp = A + RM( DE );
5551		DE++;
5552		ZHC_ADD( tmp, A, 0 );
5553		A = tmp;
5554		}
5555
5556		/* 70 c5: 0111 0000 1100 0101 */
5557		void upd7810_device::ADDX_Hp()
5558		{
5559		UINT8 tmp = A + RM( HL );
5560		HL++;
5561		ZHC_ADD( tmp, A, 0 );
5562		A = tmp;
5563		}
5564
5565		/* 70 c6: 0111 0000 1100 0110 */
5566		void upd7810_device::ADDX_Dm()
5567		{
5568		UINT8 tmp = A + RM( DE );
5569		DE--;
5570		ZHC_ADD( tmp, A, 0 );
5571		A = tmp;
5572		}
5573
5574		/* 70 c7: 0111 0000 1100 0111 */
5575		void upd7810_device::ADDX_Hm()
5576		{
5577		UINT8 tmp = A + RM( HL );
5578		HL--;
5579		ZHC_ADD( tmp, A, 0 );
5580		A = tmp;
5581		}
5582
5583		/* 70 c9: 0111 0000 1100 1001 */
5584		void upd7810_device::ONAX_B()
5585		{
5586		if (A & RM( BC ))
5587		PSW = (PSW & ~Z) \| SK;
5588		else
5589		PSW \|= Z;
5590		}
5591
5592		/* 70 ca: 0111 0000 1100 1010 */
5593		void upd7810_device::ONAX_D()
5594		{
5595		if (A & RM( DE ))
5596		PSW = (PSW & ~Z) \| SK;
5597		else
5598		PSW \|= Z;
5599		}
5600
5601		/* 70 cb: 0111 0000 1100 1011 */
5602		void upd7810_device::ONAX_H()
5603		{
5604		if (A & RM( HL ))
5605		PSW = (PSW & ~Z) \| SK;
5606		else
5607		PSW \|= Z;
5608		}
5609
5610		/* 70 cc: 0111 0000 1100 1100 */
5611		void upd7810_device::ONAX_Dp()
5612		{
5613		if (A & RM( DE ))
5614		PSW = (PSW & ~Z) \| SK;
5615		else
5616		PSW \|= Z;
5617		DE++;
5618		}
5619
5620		/* 70 cd: 0111 0000 1100 1101 */
5621		void upd7810_device::ONAX_Hp()
5622		{
5623		if (A & RM( HL ))
5624		PSW = (PSW & ~Z) \| SK;
5625		else
5626		PSW \|= Z;
5627		HL++;
5628		}
5629
5630		/* 70 ce: 0111 0000 1100 1110 */
5631		void upd7810_device::ONAX_Dm()
5632		{
5633		if (A & RM( DE ))
5634		PSW = (PSW & ~Z) \| SK;
5635		else
5636		PSW \|= Z;
5637		DE--;
5638		}
5639
5640		/* 70 cf: 0111 0000 1100 1111 */
5641		void upd7810_device::ONAX_Hm()
5642		{
5643		if (A & RM( HL ))
5644		PSW = (PSW & ~Z) \| SK;
5645		else
5646		PSW \|= Z;
5647		HL--;
5648		}
5649
5650		/* 70 d1: 0111 0000 1101 0001 */
5651		void upd7810_device::ADCX_B()
5652		{
5653		UINT8 tmp = A + RM( BC ) + (PSW & CY);
5654		ZHC_ADD( tmp, A, 0 );
5655		A = tmp;
5656		}
5657
5658		/* 70 d2: 0111 0000 1101 0010 */
5659		void upd7810_device::ADCX_D()
5660		{
5661		UINT8 tmp = A + RM( DE ) + (PSW & CY);
5662		ZHC_ADD( tmp, A, 0 );
5663		A = tmp;
5664		}
5665
5666		/* 70 d3: 0111 0000 1101 0011 */
5667		void upd7810_device::ADCX_H()
5668		{
5669		UINT8 tmp = A + RM( HL ) + (PSW & CY);
5670		ZHC_ADD( tmp, A, 0 );
5671		A = tmp;
5672		}
5673
5674		/* 70 d4: 0111 0000 1101 0100 */
5675		void upd7810_device::ADCX_Dp()
5676		{
5677		UINT8 tmp = A + RM( DE ) + (PSW & CY);
5678		DE++;
5679		ZHC_ADD( tmp, A, 0 );
5680		A = tmp;
5681		}
5682
5683		/* 70 d5: 0111 0000 1101 0101 */
5684		void upd7810_device::ADCX_Hp()
5685		{
5686		UINT8 tmp = A + RM( HL ) + (PSW & CY);
5687		HL++;
5688		ZHC_ADD( tmp, A, 0 );
5689		A = tmp;
5690		}
5691
5692		/* 70 d6: 0111 0000 1101 0110 */
5693		void upd7810_device::ADCX_Dm()
5694		{
5695		UINT8 tmp = A + RM( DE ) + (PSW & CY);
5696		DE--;
5697		ZHC_ADD( tmp, A, 0 );
5698		A = tmp;
5699		}
5700
5701		/* 70 d7: 0111 0000 1101 0111 */
5702		void upd7810_device::ADCX_Hm()
5703		{
5704		UINT8 tmp = A + RM( HL ) + (PSW & CY);
5705		HL--;
5706		ZHC_ADD( tmp, A, 0 );
5707		A = tmp;
5708		}
5709
5710		/* 70 d9: 0111 0000 1101 1001 */
5711		void upd7810_device::OFFAX_B()
5712		{
5713		if ( A & RM( BC ) )
5714		PSW &= ~Z;
5715		else
5716		PSW = PSW \| Z \| SK;
5717		}
5718
5719		/* 70 da: 0111 0000 1101 1010 */
5720		void upd7810_device::OFFAX_D()
5721		{
5722		if ( A & RM( DE ) )
5723		PSW &= ~Z;
5724		else
5725		PSW = PSW \| Z \| SK;
5726		}
5727
5728		/* 70 db: 0111 0000 1101 1011 */
5729		void upd7810_device::OFFAX_H()
5730		{
5731		if ( A & RM( HL ) )
5732		PSW &= ~Z;
5733		else
5734		PSW = PSW \| Z \| SK;
5735		}
5736
5737		/* 70 dc: 0111 0000 1101 1100 */
5738		void upd7810_device::OFFAX_Dp()
5739		{
5740		if ( A & RM( DE ) )
5741		PSW &= ~Z;
5742		else
5743		PSW = PSW \| Z \| SK;
5744		DE++;
5745		}
5746
5747		/* 70 dd: 0111 0000 1101 1101 */
5748		void upd7810_device::OFFAX_Hp()
5749		{
5750		if ( A & RM( HL ) )
5751		PSW &= ~Z;
5752		else
5753		PSW = PSW \| Z \| SK;
5754		HL++;
5755		}
5756
5757		/* 70 de: 0111 0000 1101 1110 */
5758		void upd7810_device::OFFAX_Dm()
5759		{
5760		if ( A & RM( DE ) )
5761		PSW &= ~Z;
5762		else
5763		PSW = PSW \| Z \| SK;
5764		DE--;
5765		}
5766
5767		/* 70 df: 0111 0000 1101 1111 */
5768		void upd7810_device::OFFAX_Hm()
5769		{
5770		if ( A & RM( HL ) )
5771		PSW &= ~Z;
5772		else
5773		PSW = PSW \| Z \| SK;
5774		HL--;
5775		}
5776
5777		/* 70 e1: 0111 0000 1110 0001 */
5778		void upd7810_device::SUBX_B()
5779		{
5780		UINT8 tmp = A - RM( BC );
5781		ZHC_SUB( tmp, A, 0 );
5782		A = tmp;
5783		}
5784
5785		/* 70 e2: 0111 0000 1110 0010 */
5786		void upd7810_device::SUBX_D()
5787		{
5788		UINT8 tmp = A - RM( DE );
5789		ZHC_SUB( tmp, A, 0 );
5790		A = tmp;
5791		}
5792
5793		/* 70 e3: 0111 0000 1110 0011 */
5794		void upd7810_device::SUBX_H()
5795		{
5796		UINT8 tmp = A - RM( HL );
5797		ZHC_SUB( tmp, A, 0 );
5798		A = tmp;
5799		}
5800
5801		/* 70 e4: 0111 0000 1110 0100 */
5802		void upd7810_device::SUBX_Dp()
5803		{
5804		UINT8 tmp = A - RM( DE );
5805		ZHC_SUB( tmp, A, 0 );
5806		A = tmp;
5807		DE++;
5808		}
5809
5810		/* 70 e5: 0111 0000 1110 0101 */
5811		void upd7810_device::SUBX_Hp()
5812		{
5813		UINT8 tmp = A - RM( HL );
5814		ZHC_SUB( tmp, A, 0 );
5815		A = tmp;
5816		HL++;
5817		}
5818
5819		/* 70 e6: 0111 0000 1110 0110 */
5820		void upd7810_device::SUBX_Dm()
5821		{
5822		UINT8 tmp = A - RM( DE );
5823		ZHC_SUB( tmp, A, 0 );
5824		A = tmp;
5825		DE--;
5826		}
5827
5828		/* 70 e7: 0111 0000 1110 0111 */
5829		void upd7810_device::SUBX_Hm()
5830		{
5831		UINT8 tmp = A - RM( HL );
5832		ZHC_SUB( tmp, A, 0 );
5833		A = tmp;
5834		HL--;
5835		}
5836
5837		/* 70 e9: 0111 0000 1110 1001 */
5838		void upd7810_device::NEAX_B()
5839		{
5840		UINT8 tmp = A - RM( BC );
5841		ZHC_SUB( tmp, A, 0 );
5842		SKIP_NZ;
5843		}
5844
5845		/* 70 ea: 0111 0000 1110 1010 */
5846		void upd7810_device::NEAX_D()
5847		{
5848		UINT8 tmp = A - RM( DE );
5849		ZHC_SUB( tmp, A, 0 );
5850		SKIP_NZ;
5851		}
5852
5853		/* 70 eb: 0111 0000 1110 1011 */
5854		void upd7810_device::NEAX_H()
5855		{
5856		UINT8 tmp = A - RM( HL );
5857		ZHC_SUB( tmp, A, 0 );
5858		SKIP_NZ;
5859		}
5860
5861		/* 70 ec: 0111 0000 1110 1100 */
5862		void upd7810_device::NEAX_Dp()
5863		{
5864		UINT8 tmp = A - RM( DE );
5865		DE++;
5866		ZHC_SUB( tmp, A, 0 );
5867		SKIP_NZ;
5868		}
5869
5870		/* 70 ed: 0111 0000 1110 1101 */
5871		void upd7810_device::NEAX_Hp()
5872		{
5873		UINT8 tmp = A - RM( HL );
5874		HL++;
5875		ZHC_SUB( tmp, A, 0 );
5876		SKIP_NZ;
5877		}
5878
5879		/* 70 ee: 0111 0000 1110 1110 */
5880		void upd7810_device::NEAX_Dm()
5881		{
5882		UINT8 tmp = A - RM( DE );
5883		DE--;
5884		ZHC_SUB( tmp, A, 0 );
5885		SKIP_NZ;
5886		}
5887
5888		/* 70 ef: 0111 0000 1110 1111 */
5889		void upd7810_device::NEAX_Hm()
5890		{
5891		UINT8 tmp = A - RM( HL );
5892		HL--;
5893		ZHC_SUB( tmp, A, 0 );
5894		SKIP_NZ;
5895		}
5896
5897		/* 70 f1: 0111 0000 1111 0001 */
5898		void upd7810_device::SBBX_B()
5899		{
5900		UINT8 tmp = A - RM( BC ) - (PSW & CY);
5901		ZHC_SUB( tmp, A, (PSW & CY) );
5902		A = tmp;
5903		}
5904
5905		/* 70 f2: 0111 0000 1111 0010 */
5906		void upd7810_device::SBBX_D()
5907		{
5908		UINT8 tmp = A - RM( DE ) - (PSW & CY);
5909		ZHC_SUB( tmp, A, (PSW & CY) );
5910		A = tmp;
5911		}
5912
5913		/* 70 f3: 0111 0000 1111 0011 */
5914		void upd7810_device::SBBX_H()
5915		{
5916		UINT8 tmp = A - RM( HL ) - (PSW & CY);
5917		ZHC_SUB( tmp, A, (PSW & CY) );
5918		A = tmp;
5919		}
5920
5921		/* 70 f4: 0111 0000 1111 0100 */
5922		void upd7810_device::SBBX_Dp()
5923		{
5924		UINT8 tmp = A - RM( DE ) - (PSW & CY);
5925		DE++;
5926		ZHC_SUB( tmp, A, (PSW & CY) );
5927		A = tmp;
5928		}
5929
5930		/* 70 f5: 0111 0000 1111 0101 */
5931		void upd7810_device::SBBX_Hp()
5932		{
5933		UINT8 tmp = A - RM( HL ) - (PSW & CY);
5934		HL++;
5935		ZHC_SUB( tmp, A, (PSW & CY) );
5936		A = tmp;
5937		}
5938
5939		/* 70 f6: 0111 0000 1111 0110 */
5940		void upd7810_device::SBBX_Dm()
5941		{
5942		UINT8 tmp = A - RM( DE ) - (PSW & CY);
5943		DE--;
5944		ZHC_SUB( tmp, A, (PSW & CY) );
5945		A = tmp;
5946		}
5947
5948		/* 70 f7: 0111 0000 1111 0111 */
5949		void upd7810_device::SBBX_Hm()
5950		{
5951		UINT8 tmp = A - RM( HL ) - (PSW & CY);
5952		HL--;
5953		ZHC_SUB( tmp, A, (PSW & CY) );
5954		A = tmp;
5955		}
5956
5957		/* 70 f9: 0111 0000 1111 1001 */
5958		void upd7810_device::EQAX_B()
5959		{
5960		UINT8 tmp = A - RM( BC );
5961		ZHC_SUB( tmp, A, 0 );
5962		SKIP_Z;
5963		}
5964
5965		/* 70 fa: 0111 0000 1111 1010 */
5966		void upd7810_device::EQAX_D()
5967		{
5968		UINT8 tmp = A - RM( DE );
5969		ZHC_SUB( tmp, A, 0 );
5970		SKIP_Z;
5971		}
5972
5973		/* 70 fb: 0111 0000 1111 1011 */
5974		void upd7810_device::EQAX_H()
5975		{
5976		UINT8 tmp = A - RM( HL );
5977		ZHC_SUB( tmp, A, 0 );
5978		SKIP_Z;
5979		}
5980
5981		/* 70 fc: 0111 0000 1111 1100 */
5982		void upd7810_device::EQAX_Dp()
5983		{
5984		UINT8 tmp = A - RM( DE );
5985		DE++;
5986		ZHC_SUB( tmp, A, 0 );
5987		SKIP_Z;
5988		}
5989
5990		/* 70 fd: 0111 0000 1111 1101 */
5991		void upd7810_device::EQAX_Hp()
5992		{
5993		UINT8 tmp = A - RM( HL );
5994		HL++;
5995		ZHC_SUB( tmp, A, 0 );
5996		SKIP_Z;
5997		}
5998
5999		/* 70 fe: 0111 0000 1111 1110 */
6000		void upd7810_device::EQAX_Dm()
6001		{
6002		UINT8 tmp = A - RM( DE );
6003		DE--;
6004		ZHC_SUB( tmp, A, 0 );
6005		SKIP_Z;
6006		}
6007
6008		/* 70 ff: 0111 0000 1111 1111 */
6009		void upd7810_device::EQAX_Hm()
6010		{
6011		UINT8 tmp = A - RM( HL );
6012		HL--;
6013		ZHC_SUB( tmp, A, 0 );
6014		SKIP_Z;
6015		}
6016
6017		/* prefix 74 */
6018		/* 74 08: 0111 0100 0000 1000 xxxx xxxx */
6019		void upd7810_device::ANI_V_xx()
6020		{
6021		UINT8 imm;
6022		RDOPARG( imm );
6023		V &= imm;
6024		SET_Z(V);
6025		}
6026
6027		/* 74 09: 0111 0100 0000 1001 xxxx xxxx */
6028		void upd7810_device::ANI_A_xx()
6029		{
6030		UINT8 imm;
6031		RDOPARG( imm );
6032		A &= imm;
6033		SET_Z(A);
6034		}
6035
6036		/* 74 0a: 0111 0100 0000 1010 xxxx xxxx */
6037		void upd7810_device::ANI_B_xx()
6038		{
6039		UINT8 imm;
6040		RDOPARG( imm );
6041		B &= imm;
6042		SET_Z(B);
6043		}
6044
6045		/* 74 0b: 0111 0100 0000 1011 xxxx xxxx */
6046		void upd7810_device::ANI_C_xx()
6047		{
6048		UINT8 imm;
6049		RDOPARG( imm );
6050		C &= imm;
6051		SET_Z(C);
6052		}
6053
6054		/* 74 0c: 0111 0100 0000 1100 xxxx xxxx */
6055		void upd7810_device::ANI_D_xx()
6056		{
6057		UINT8 imm;
6058		RDOPARG( imm );
6059		D &= imm;
6060		SET_Z(D);
6061		}
6062
6063		/* 74 0d: 0111 0100 0000 1101 xxxx xxxx */
6064		void upd7810_device::ANI_E_xx()
6065		{
6066		UINT8 imm;
6067		RDOPARG( imm );
6068		E &= imm;
6069		SET_Z(E);
6070		}
6071
6072		/* 74 0e: 0111 0100 0000 1110 xxxx xxxx */
6073		void upd7810_device::ANI_H_xx()
6074		{
6075		UINT8 imm;
6076		RDOPARG( imm );
6077		H &= imm;
6078		SET_Z(H);
6079		}
6080
6081		/* 74 0f: 0111 0100 0000 1111 xxxx xxxx */
6082		void upd7810_device::ANI_L_xx()
6083		{
6084		UINT8 imm;
6085		RDOPARG( imm );
6086		L &= imm;
6087		SET_Z(L);
6088		}
6089
6090		/* 74 10: 0111 0100 0001 0000 xxxx xxxx */
6091		void upd7810_device::XRI_V_xx()
6092		{
6093		UINT8 imm;
6094		RDOPARG( imm );
6095		V ^= imm;
6096		SET_Z(V);
6097		}
6098
6099		/* 74 11: 0111 0100 0001 0001 xxxx xxxx */
6100		void upd7810_device::XRI_A_xx()
6101		{
6102		UINT8 imm;
6103		RDOPARG( imm );
6104		A ^= imm;
6105		SET_Z(A);
6106		}
6107
6108		/* 74 12: 0111 0100 0001 0010 xxxx xxxx */
6109		void upd7810_device::XRI_B_xx()
6110		{
6111		UINT8 imm;
6112		RDOPARG( imm );
6113		B ^= imm;
6114		SET_Z(B);
6115		}
6116
6117		/* 74 13: 0111 0100 0001 0011 xxxx xxxx */
6118		void upd7810_device::XRI_C_xx()
6119		{
6120		UINT8 imm;
6121		RDOPARG( imm );
6122		C ^= imm;
6123		SET_Z(C);
6124		}
6125
6126		/* 74 14: 0111 0100 0001 0100 xxxx xxxx */
6127		void upd7810_device::XRI_D_xx()
6128		{
6129		UINT8 imm;
6130		RDOPARG( imm );
6131		D ^= imm;
6132		SET_Z(D);
6133		}
6134
6135		/* 74 15: 0111 0100 0001 0101 xxxx xxxx */
6136		void upd7810_device::XRI_E_xx()
6137		{
6138		UINT8 imm;
6139		RDOPARG( imm );
6140		E ^= imm;
6141		SET_Z(E);
6142		}
6143
6144		/* 74 16: 0111 0100 0001 0110 xxxx xxxx */
6145		void upd7810_device::XRI_H_xx()
6146		{
6147		UINT8 imm;
6148		RDOPARG( imm );
6149		H ^= imm;
6150		SET_Z(H);
6151		}
6152
6153		/* 74 17: 0111 0100 0001 0111 xxxx xxxx */
6154		void upd7810_device::XRI_L_xx()
6155		{
6156		UINT8 imm;
6157		RDOPARG( imm );
6158		L ^= imm;
6159		SET_Z(L);
6160		}
6161
6162		/* 74 18: 0111 0100 0001 1000 xxxx xxxx */
6163		void upd7810_device::ORI_V_xx()
6164		{
6165		UINT8 imm;
6166		RDOPARG( imm );
6167		V \|= imm;
6168		SET_Z(V);
6169		}
6170
6171		/* 74 19: 0111 0100 0001 1001 xxxx xxxx */
6172		void upd7810_device::ORI_A_xx()
6173		{
6174		UINT8 imm;
6175		RDOPARG( imm );
6176		A \|= imm;
6177		SET_Z(A);
6178		}
6179
6180		/* 74 1a: 0111 0100 0001 1010 xxxx xxxx */
6181		void upd7810_device::ORI_B_xx()
6182		{
6183		UINT8 imm;
6184		RDOPARG( imm );
6185		B \|= imm;
6186		SET_Z(B);
6187		}
6188
6189		/* 74 1b: 0111 0100 0001 1011 xxxx xxxx */
6190		void upd7810_device::ORI_C_xx()
6191		{
6192		UINT8 imm;
6193		RDOPARG( imm );
6194		C \|= imm;
6195		SET_Z(C);
6196		}
6197
6198		/* 74 1c: 0111 0100 0001 1100 xxxx xxxx */
6199		void upd7810_device::ORI_D_xx()
6200		{
6201		UINT8 imm;
6202		RDOPARG( imm );
6203		D \|= imm;
6204		SET_Z(D);
6205		}
6206
6207		/* 74 1d: 0111 0100 0001 1101 xxxx xxxx */
6208		void upd7810_device::ORI_E_xx()
6209		{
6210		UINT8 imm;
6211		RDOPARG( imm );
6212		E \|= imm;
6213		SET_Z(E);
6214		}
6215
6216		/* 74 1e: 0111 0100 0001 1110 xxxx xxxx */
6217		void upd7810_device::ORI_H_xx()
6218		{
6219		UINT8 imm;
6220		RDOPARG( imm );
6221		H \|= imm;
6222		SET_Z(H);
6223		}
6224
6225		/* 74 1f: 0111 0100 0001 1111 xxxx xxxx */
6226		void upd7810_device::ORI_L_xx()
6227		{
6228		UINT8 imm;
6229		RDOPARG( imm );
6230		L \|= imm;
6231		SET_Z(L);
6232		}
6233
6234		/* 74 20: 0111 0100 0010 0000 xxxx xxxx */
6235		void upd7810_device::ADINC_V_xx()
6236		{
6237		UINT8 tmp, imm;
6238
6239		RDOPARG( imm );
6240		tmp = V + imm;
6241
6242		ZHC_ADD( tmp, V, 0 );
6243		V = tmp;
6244		SKIP_NC;
6245		}
6246
6247		/* 74 21: 0111 0100 0010 0001 xxxx xxxx */
6248		void upd7810_device::ADINC_A_xx()
6249		{
6250		UINT8 tmp, imm;
6251
6252		RDOPARG( imm );
6253		tmp = A + imm;
6254
6255		ZHC_ADD( tmp, A, 0 );
6256		A = tmp;
6257		SKIP_NC;
6258		}
6259
6260		/* 74 22: 0111 0100 0010 0010 xxxx xxxx */
6261		void upd7810_device::ADINC_B_xx()
6262		{
6263		UINT8 tmp, imm;
6264
6265		RDOPARG( imm );
6266		tmp = B + imm;
6267
6268		ZHC_ADD( tmp, B, 0 );
6269		B = tmp;
6270		SKIP_NC;
6271		}
6272
6273		/* 74 23: 0111 0100 0010 0011 xxxx xxxx */
6274		void upd7810_device::ADINC_C_xx()
6275		{
6276		UINT8 tmp, imm;
6277
6278		RDOPARG( imm );
6279		tmp = C + imm;
6280
6281		ZHC_ADD( tmp, C, 0 );
6282		C = tmp;
6283		SKIP_NC;
6284		}
6285
6286		/* 74 24: 0111 0100 0010 0100 xxxx xxxx */
6287		void upd7810_device::ADINC_D_xx()
6288		{
6289		UINT8 tmp, imm;
6290
6291		RDOPARG( imm );
6292		tmp = D + imm;
6293
6294		ZHC_ADD( tmp, D, 0 );
6295		D = tmp;
6296		SKIP_NC;
6297		}
6298
6299		/* 74 25: 0111 0100 0010 0101 xxxx xxxx */
6300		void upd7810_device::ADINC_E_xx()
6301		{
6302		UINT8 tmp, imm;
6303
6304		RDOPARG( imm );
6305		tmp = E + imm;
6306
6307		ZHC_ADD( tmp, E, 0 );
6308		E = tmp;
6309		SKIP_NC;
6310		}
6311
6312		/* 74 26: 0111 0100 0010 0110 xxxx xxxx */
6313		void upd7810_device::ADINC_H_xx()
6314		{
6315		UINT8 tmp, imm;
6316
6317		RDOPARG( imm );
6318		tmp = H + imm;
6319
6320		ZHC_ADD( tmp, H, 0 );
6321		H = tmp;
6322		SKIP_NC;
6323		}
6324
6325		/* 74 27: 0111 0100 0010 0111 xxxx xxxx */
6326		void upd7810_device::ADINC_L_xx()
6327		{
6328		UINT8 tmp, imm;
6329
6330		RDOPARG( imm );
6331		tmp = L + imm;
6332
6333		ZHC_ADD( tmp, L, 0 );
6334		L = tmp;
6335		SKIP_NC;
6336		}
6337
6338		/* 74 28: 0111 0100 0010 1000 xxxx xxxx */
6339		void upd7810_device::GTI_V_xx()
6340		{
6341		UINT8 imm;
6342		UINT16 tmp;
6343
6344		RDOPARG( imm );
6345		tmp = V - imm - 1;
6346		ZHC_SUB( tmp, V, 0 );
6347
6348		SKIP_NC;
6349		}
6350
6351		/* 74 29: 0111 0100 0010 1001 xxxx xxxx */
6352		void upd7810_device::GTI_A_xx()
6353		{
6354		UINT8 imm;
6355		UINT16 tmp;
6356
6357		RDOPARG( imm );
6358		tmp = A - imm - 1;
6359		ZHC_SUB( tmp, A, 0 );
6360
6361		SKIP_NC;
6362		}
6363
6364		/* 74 2a: 0111 0100 0010 1010 xxxx xxxx */
6365		void upd7810_device::GTI_B_xx()
6366		{
6367		UINT8 imm;
6368		UINT16 tmp;
6369
6370		RDOPARG( imm );
6371		tmp = B - imm - 1;
6372		ZHC_SUB( tmp, B, 0 );
6373
6374		SKIP_NC;
6375		}
6376
6377		/* 74 2b: 0111 0100 0010 1011 xxxx xxxx */
6378		void upd7810_device::GTI_C_xx()
6379		{
6380		UINT8 imm;
6381		UINT16 tmp;
6382
6383		RDOPARG( imm );
6384		tmp = C - imm - 1;
6385		ZHC_SUB( tmp, C, 0 );
6386
6387		SKIP_NC;
6388		}
6389
6390		/* 74 2c: 0111 0100 0010 1100 xxxx xxxx */
6391		void upd7810_device::GTI_D_xx()
6392		{
6393		UINT8 imm;
6394		UINT16 tmp;
6395
6396		RDOPARG( imm );
6397		tmp = D - imm - 1;
6398		ZHC_SUB( tmp, D, 0 );
6399
6400		SKIP_NC;
6401		}
6402
6403		/* 74 2d: 0111 0100 0010 1101 xxxx xxxx */
6404		void upd7810_device::GTI_E_xx()
6405		{
6406		UINT8 imm;
6407		UINT16 tmp;
6408
6409		RDOPARG( imm );
6410		tmp = E - imm - 1;
6411		ZHC_SUB( tmp, E, 0 );
6412
6413		SKIP_NC;
6414		}
6415
6416		/* 74 2e: 0111 0100 0010 1110 xxxx xxxx */
6417		void upd7810_device::GTI_H_xx()
6418		{
6419		UINT8 imm;
6420		UINT16 tmp;
6421
6422		RDOPARG( imm );
6423		tmp = H - imm - 1;
6424		ZHC_SUB( tmp, H, 0 );
6425
6426		SKIP_NC;
6427		}
6428
6429		/* 74 2f: 0111 0100 0010 1111 xxxx xxxx */
6430		void upd7810_device::GTI_L_xx()
6431		{
6432		UINT8 imm;
6433		UINT16 tmp;
6434
6435		RDOPARG( imm );
6436		tmp = L - imm - 1;
6437		ZHC_SUB( tmp, L, 0 );
6438
6439		SKIP_NC;
6440		}
6441
6442		/* 74 30: 0111 0100 0011 0000 xxxx xxxx */
6443		void upd7810_device::SUINB_V_xx()
6444		{
6445		UINT8 tmp, imm;
6446
6447		RDOPARG( imm );
6448		tmp = V - imm;
6449		ZHC_SUB( tmp, V, 0 );
6450		V = tmp;
6451		SKIP_NC;
6452		}
6453
6454		/* 74 31: 0111 0100 0011 0001 xxxx xxxx */
6455		void upd7810_device::SUINB_A_xx()
6456		{
6457		UINT8 tmp, imm;
6458
6459		RDOPARG( imm );
6460		tmp = A - imm;
6461		ZHC_SUB( tmp, A, 0 );
6462		A = tmp;
6463		SKIP_NC;
6464		}
6465
6466		/* 74 32: 0111 0100 0011 0010 xxxx xxxx */
6467		void upd7810_device::SUINB_B_xx()
6468		{
6469		UINT8 tmp, imm;
6470
6471		RDOPARG( imm );
6472		tmp = B - imm;
6473		ZHC_SUB( tmp, B, 0 );
6474		B = tmp;
6475		SKIP_NC;
6476		}
6477
6478		/* 74 33: 0111 0100 0011 0011 xxxx xxxx */
6479		void upd7810_device::SUINB_C_xx()
6480		{
6481		UINT8 tmp, imm;
6482
6483		RDOPARG( imm );
6484		tmp = C - imm;
6485		ZHC_SUB( tmp, C, 0 );
6486		C = tmp;
6487		SKIP_NC;
6488		}
6489
6490		/* 74 34: 0111 0100 0011 0100 xxxx xxxx */
6491		void upd7810_device::SUINB_D_xx()
6492		{
6493		UINT8 tmp, imm;
6494
6495		RDOPARG( imm );
6496		tmp = D - imm;
6497		ZHC_SUB( tmp, D, 0 );
6498		D = tmp;
6499		SKIP_NC;
6500		}
6501
6502		/* 74 35: 0111 0100 0011 0101 xxxx xxxx */
6503		void upd7810_device::SUINB_E_xx()
6504		{
6505		UINT8 tmp, imm;
6506
6507		RDOPARG( imm );
6508		tmp = E - imm;
6509		ZHC_SUB( tmp, E, 0 );
6510		E = tmp;
6511		SKIP_NC;
6512		}
6513
6514		/* 74 36: 0111 0100 0011 0110 xxxx xxxx */
6515		void upd7810_device::SUINB_H_xx()
6516		{
6517		UINT8 tmp, imm;
6518
6519		RDOPARG( imm );
6520		tmp = H - imm;
6521		ZHC_SUB( tmp, H, 0 );
6522		H = tmp;
6523		SKIP_NC;
6524		}
6525
6526		/* 74 37: 0111 0100 0011 0111 xxxx xxxx */
6527		void upd7810_device::SUINB_L_xx()
6528		{
6529		UINT8 tmp, imm;
6530
6531		RDOPARG( imm );
6532		tmp = L - imm;
6533		ZHC_SUB( tmp, L, 0 );
6534		L = tmp;
6535		SKIP_NC;
6536		}
6537
6538		/* 74 38: 0111 0100 0011 1000 xxxx xxxx */
6539		void upd7810_device::LTI_V_xx()
6540		{
6541		UINT8 tmp, imm;
6542
6543		RDOPARG( imm );
6544		tmp = V - imm;
6545		ZHC_SUB( tmp, V, 0 );
6546		SKIP_CY;
6547		}
6548
6549		/* 74 39: 0111 0100 0011 1001 xxxx xxxx */
6550		void upd7810_device::LTI_A_xx()
6551		{
6552		UINT8 tmp, imm;
6553
6554		RDOPARG( imm );
6555		tmp = A - imm;
6556		ZHC_SUB( tmp, A, 0 );
6557		SKIP_CY;
6558		}
6559
6560		/* 74 3a: 0111 0100 0011 1010 xxxx xxxx */
6561		void upd7810_device::LTI_B_xx()
6562		{
6563		UINT8 tmp, imm;
6564
6565		RDOPARG( imm );
6566		tmp = B - imm;
6567		ZHC_SUB( tmp, B, 0 );
6568		SKIP_CY;
6569		}
6570
6571		/* 74 3b: 0111 0100 0011 1011 xxxx xxxx */
6572		void upd7810_device::LTI_C_xx()
6573		{
6574		UINT8 tmp, imm;
6575
6576		RDOPARG( imm );
6577		tmp = C - imm;
6578		ZHC_SUB( tmp, C, 0 );
6579		SKIP_CY;
6580		}
6581
6582		/* 74 3c: 0111 0100 0011 1100 xxxx xxxx */
6583		void upd7810_device::LTI_D_xx()
6584		{
6585		UINT8 tmp, imm;
6586
6587		RDOPARG( imm );
6588		tmp = D - imm;
6589		ZHC_SUB( tmp, D, 0 );
6590		SKIP_CY;
6591		}
6592
6593		/* 74 3d: 0111 0100 0011 1101 xxxx xxxx */
6594		void upd7810_device::LTI_E_xx()
6595		{
6596		UINT8 tmp, imm;
6597
6598		RDOPARG( imm );
6599		tmp = E - imm;
6600		ZHC_SUB( tmp, E, 0 );
6601		SKIP_CY;
6602		}
6603
6604		/* 74 3e: 0111 0100 0011 1110 xxxx xxxx */
6605		void upd7810_device::LTI_H_xx()
6606		{
6607		UINT8 tmp, imm;
6608
6609		RDOPARG( imm );
6610		tmp = H - imm;
6611		ZHC_SUB( tmp, H, 0 );
6612		SKIP_CY;
6613		}
6614
6615		/* 74 3f: 0111 0100 0011 1111 xxxx xxxx */
6616		void upd7810_device::LTI_L_xx()
6617		{
6618		UINT8 tmp, imm;
6619
6620		RDOPARG( imm );
6621		tmp = L - imm;
6622		ZHC_SUB( tmp, L, 0 );
6623		SKIP_CY;
6624		}
6625
6626		/* 74 40: 0111 0100 0100 0000 xxxx xxxx */
6627		void upd7810_device::ADI_V_xx()
6628		{
6629		UINT8 tmp, imm;
6630
6631		RDOPARG( imm );
6632		tmp = V + imm;
6633
6634		ZHC_ADD( tmp, V, 0 );
6635		V = tmp;
6636		}
6637
6638		/* 74 41: 0111 0100 0100 0001 xxxx xxxx */
6639		void upd7810_device::ADI_A_xx()
6640		{
6641		UINT8 tmp, imm;
6642
6643		RDOPARG( imm );
6644		tmp = A + imm;
6645
6646		ZHC_ADD( tmp, A, 0 );
6647		A = tmp;
6648		}
6649
6650		/* 74 42: 0111 0100 0100 0010 xxxx xxxx */
6651		void upd7810_device::ADI_B_xx()
6652		{
6653		UINT8 tmp, imm;
6654
6655		RDOPARG( imm );
6656		tmp = B + imm;
6657
6658		ZHC_ADD( tmp, B, 0 );
6659		B = tmp;
6660		}
6661
6662		/* 74 43: 0111 0100 0100 0011 xxxx xxxx */
6663		void upd7810_device::ADI_C_xx()
6664		{
6665		UINT8 tmp, imm;
6666
6667		RDOPARG( imm );
6668		tmp = C + imm;
6669
6670		ZHC_ADD( tmp, C, 0 );
6671		C = tmp;
6672		}
6673
6674		/* 74 44: 0111 0100 0100 0100 xxxx xxxx */
6675		void upd7810_device::ADI_D_xx()
6676		{
6677		UINT8 tmp, imm;
6678
6679		RDOPARG( imm );
6680		tmp = D + imm;
6681
6682		ZHC_ADD( tmp, D, 0 );
6683		D = tmp;
6684		}
6685
6686		/* 74 45: 0111 0100 0100 0101 xxxx xxxx */
6687		void upd7810_device::ADI_E_xx()
6688		{
6689		UINT8 tmp, imm;
6690
6691		RDOPARG( imm );
6692		tmp = E + imm;
6693
6694		ZHC_ADD( tmp, E, 0 );
6695		E = tmp;
6696		}
6697
6698		/* 74 46: 0111 0100 0100 0110 xxxx xxxx */
6699		void upd7810_device::ADI_H_xx()
6700		{
6701		UINT8 tmp, imm;
6702
6703		RDOPARG( imm );
6704		tmp = H + imm;
6705
6706		ZHC_ADD( tmp, H, 0 );
6707		H = tmp;
6708		}
6709
6710		/* 74 47: 0111 0100 0100 0111 xxxx xxxx */
6711		void upd7810_device::ADI_L_xx()
6712		{
6713		UINT8 tmp, imm;
6714
6715		RDOPARG( imm );
6716		tmp = L + imm;
6717
6718		ZHC_ADD( tmp, L, 0 );
6719		L = tmp;
6720		}
6721
6722		/* 74 48: 0111 0100 0100 1000 xxxx xxxx */
6723		void upd7810_device::ONI_V_xx()
6724		{
6725		UINT8 imm;
6726
6727		RDOPARG( imm );
6728		if (V & imm)
6729		PSW \|= SK;
6730		}
6731
6732		/* 74 49: 0111 0100 0100 1001 xxxx xxxx */
6733		void upd7810_device::ONI_A_xx()
6734		{
6735		UINT8 imm;
6736
6737		RDOPARG( imm );
6738		if (A & imm)
6739		PSW \|= SK;
6740		}
6741
6742		/* 74 4a: 0111 0100 0100 1010 xxxx xxxx */
6743		void upd7810_device::ONI_B_xx()
6744		{
6745		UINT8 imm;
6746
6747		RDOPARG( imm );
6748		if (B & imm)
6749		PSW \|= SK;
6750		}
6751
6752		/* 74 4b: 0111 0100 0100 1011 xxxx xxxx */
6753		void upd7810_device::ONI_C_xx()
6754		{
6755		UINT8 imm;
6756
6757		RDOPARG( imm );
6758		if (C & imm)
6759		PSW \|= SK;
6760		}
6761
6762		/* 74 4c: 0111 0100 0100 1100 xxxx xxxx */
6763		void upd7810_device::ONI_D_xx()
6764		{
6765		UINT8 imm;
6766
6767		RDOPARG( imm );
6768		if (D & imm)
6769		PSW \|= SK;
6770		}
6771
6772		/* 74 4d: 0111 0100 0100 1101 xxxx xxxx */
6773		void upd7810_device::ONI_E_xx()
6774		{
6775		UINT8 imm;
6776
6777		RDOPARG( imm );
6778		if (E & imm)
6779		PSW \|= SK;
6780		}
6781
6782		/* 74 4e: 0111 0100 0100 1110 xxxx xxxx */
6783		void upd7810_device::ONI_H_xx()
6784		{
6785		UINT8 imm;
6786
6787		RDOPARG( imm );
6788		if (H & imm)
6789		PSW \|= SK;
6790		}
6791
6792		/* 74 4f: 0111 0100 0100 1111 xxxx xxxx */
6793		void upd7810_device::ONI_L_xx()
6794		{
6795		UINT8 imm;
6796
6797		RDOPARG( imm );
6798		if (L & imm)
6799		PSW \|= SK;
6800		}
6801
6802		/* 74 50: 0111 0100 0101 0000 xxxx xxxx */
6803		void upd7810_device::ACI_V_xx()
6804		{
6805		UINT8 tmp, imm;
6806
6807		RDOPARG( imm );
6808		tmp = V + imm + (PSW & CY);
6809		ZHC_ADD( tmp, V, (PSW & CY) );
6810		V = tmp;
6811		}
6812
6813		/* 74 51: 0111 0100 0101 0001 xxxx xxxx */
6814		void upd7810_device::ACI_A_xx()
6815		{
6816		UINT8 tmp, imm;
6817
6818		RDOPARG( imm );
6819		tmp = A + imm + (PSW & CY);
6820		ZHC_ADD( tmp, A, (PSW & CY) );
6821		A = tmp;
6822		}
6823
6824		/* 74 52: 0111 0100 0101 0010 xxxx xxxx */
6825		void upd7810_device::ACI_B_xx()
6826		{
6827		UINT8 tmp, imm;
6828
6829		RDOPARG( imm );
6830		tmp = B + imm + (PSW & CY);
6831		ZHC_ADD( tmp, B, (PSW & CY) );
6832		B = tmp;
6833		}
6834
6835		/* 74 53: 0111 0100 0101 0011 xxxx xxxx */
6836		void upd7810_device::ACI_C_xx()
6837		{
6838		UINT8 tmp, imm;
6839
6840		RDOPARG( imm );
6841		tmp = C + imm + (PSW & CY);
6842		ZHC_ADD( tmp, C, (PSW & CY) );
6843		C = tmp;
6844		}
6845
6846		/* 74 54: 0111 0100 0101 0100 xxxx xxxx */
6847		void upd7810_device::ACI_D_xx()
6848		{
6849		UINT8 tmp, imm;
6850
6851		RDOPARG( imm );
6852		tmp = D + imm + (PSW & CY);
6853		ZHC_ADD( tmp, D, (PSW & CY) );
6854		D = tmp;
6855		}
6856
6857		/* 74 55: 0111 0100 0101 0101 xxxx xxxx */
6858		void upd7810_device::ACI_E_xx()
6859		{
6860		UINT8 tmp, imm;
6861
6862		RDOPARG( imm );
6863		tmp = E + imm + (PSW & CY);
6864		ZHC_ADD( tmp, E, (PSW & CY) );
6865		E = tmp;
6866		}
6867
6868		/* 74 56: 0111 0100 0101 0110 xxxx xxxx */
6869		void upd7810_device::ACI_H_xx()
6870		{
6871		UINT8 tmp, imm;
6872
6873		RDOPARG( imm );
6874		tmp = H + imm + (PSW & CY);
6875		ZHC_ADD( tmp, H, (PSW & CY) );
6876		H = tmp;
6877		}
6878
6879		/* 74 57: 0111 0100 0101 0111 xxxx xxxx */
6880		void upd7810_device::ACI_L_xx()
6881		{
6882		UINT8 tmp, imm;
6883
6884		RDOPARG( imm );
6885		tmp = L + imm + (PSW & CY);
6886		ZHC_ADD( tmp, L, (PSW & CY) );
6887		L = tmp;
6888		}
6889
6890		/* 74 58: 0111 0100 0101 1000 xxxx xxxx */
6891		void upd7810_device::OFFI_V_xx()
6892		{
6893		UINT8 imm;
6894
6895		RDOPARG( imm );
6896		if (0 == (V & imm))
6897		PSW \|= SK;
6898		}
6899
6900		/* 74 59: 0111 0100 0101 1001 xxxx xxxx */
6901		void upd7810_device::OFFI_A_xx()
6902		{
6903		UINT8 imm;
6904
6905		RDOPARG( imm );
6906		if (0 == (A & imm))
6907		PSW \|= SK;
6908		}
6909
6910		/* 74 5a: 0111 0100 0101 1010 xxxx xxxx */
6911		void upd7810_device::OFFI_B_xx()
6912		{
6913		UINT8 imm;
6914
6915		RDOPARG( imm );
6916		if (0 == (B & imm))
6917		PSW \|= SK;
6918		}
6919
6920		/* 74 5b: 0111 0100 0101 1011 xxxx xxxx */
6921		void upd7810_device::OFFI_C_xx()
6922		{
6923		UINT8 imm;
6924
6925		RDOPARG( imm );
6926		if (0 == (C & imm))
6927		PSW \|= SK;
6928		}
6929
6930		/* 74 5c: 0111 0100 0101 1100 xxxx xxxx */
6931		void upd7810_device::OFFI_D_xx()
6932		{
6933		UINT8 imm;
6934
6935		RDOPARG( imm );
6936		if (0 == (D & imm))
6937		PSW \|= SK;
6938		}
6939
6940		/* 74 5d: 0111 0100 0101 1101 xxxx xxxx */
6941		void upd7810_device::OFFI_E_xx()
6942		{
6943		UINT8 imm;
6944
6945		RDOPARG( imm );
6946		if (0 == (E & imm))
6947		PSW \|= SK;
6948		}
6949
6950		/* 74 5e: 0111 0100 0101 1110 xxxx xxxx */
6951		void upd7810_device::OFFI_H_xx()
6952		{
6953		UINT8 imm;
6954
6955		RDOPARG( imm );
6956		if (0 == (H & imm))
6957		PSW \|= SK;
6958		}
6959
6960		/* 74 5f: 0111 0100 0101 1111 xxxx xxxx */
6961		void upd7810_device::OFFI_L_xx()
6962		{
6963		UINT8 imm;
6964
6965		RDOPARG( imm );
6966		if (0 == (L & imm))
6967		PSW \|= SK;
6968		}
6969
6970		/* 74 60: 0111 0100 0110 0000 xxxx xxxx */
6971		void upd7810_device::SUI_V_xx()
6972		{
6973		UINT8 tmp, imm;
6974
6975		RDOPARG( imm );
6976		tmp = V - imm;
6977		ZHC_SUB( tmp, V, 0 );
6978		V = tmp;
6979		}
6980
6981		/* 74 61: 0111 0100 0110 0001 xxxx xxxx */
6982		void upd7810_device::SUI_A_xx()
6983		{
6984		UINT8 tmp, imm;
6985
6986		RDOPARG( imm );
6987		tmp = A - imm;
6988		ZHC_SUB( tmp, A, 0 );
6989		A = tmp;
6990		}
6991
6992		/* 74 62: 0111 0100 0110 0010 xxxx xxxx */
6993		void upd7810_device::SUI_B_xx()
6994		{
6995		UINT8 tmp, imm;
6996
6997		RDOPARG( imm );
6998		tmp = B - imm;
6999		ZHC_SUB( tmp, B, 0 );
7000		B = tmp;
7001		}
7002
7003		/* 74 63: 0111 0100 0110 0011 xxxx xxxx */
7004		void upd7810_device::SUI_C_xx()
7005		{
7006		UINT8 tmp, imm;
7007
7008		RDOPARG( imm );
7009		tmp = C - imm;
7010		ZHC_SUB( tmp, C, 0 );
7011		C = tmp;
7012		}
7013
7014		/* 74 64: 0111 0100 0110 0100 xxxx xxxx */
7015		void upd7810_device::SUI_D_xx()
7016		{
7017		UINT8 tmp, imm;
7018
7019		RDOPARG( imm );
7020		tmp = D - imm;
7021		ZHC_SUB( tmp, D, 0 );
7022		D = tmp;
7023		}
7024
7025		/* 74 65: 0111 0100 0110 0101 xxxx xxxx */
7026		void upd7810_device::SUI_E_xx()
7027		{
7028		UINT8 tmp, imm;
7029
7030		RDOPARG( imm );
7031		tmp = E - imm;
7032		ZHC_SUB( tmp, E, 0 );
7033		E = tmp;
7034		}
7035
7036		/* 74 66: 0111 0100 0110 0110 xxxx xxxx */
7037		void upd7810_device::SUI_H_xx()
7038		{
7039		UINT8 tmp, imm;
7040
7041		RDOPARG( imm );
7042		tmp = H - imm;
7043		ZHC_SUB( tmp, H, 0 );
7044		H = tmp;
7045		}
7046
7047		/* 74 67: 0111 0100 0110 0111 xxxx xxxx */
7048		void upd7810_device::SUI_L_xx()
7049		{
7050		UINT8 tmp, imm;
7051
7052		RDOPARG( imm );
7053		tmp = L - imm;
7054		ZHC_SUB( tmp, L, 0 );
7055		L = tmp;
7056		}
7057
7058		/* 74 68: 0111 0100 0110 1000 xxxx xxxx */
7059		void upd7810_device::NEI_V_xx()
7060		{
7061		UINT8 tmp, imm;
7062
7063		RDOPARG( imm );
7064		tmp = V - imm;
7065		ZHC_SUB( tmp, V, 0 );
7066		SKIP_NZ;
7067		}
7068
7069		/* 74 69: 0111 0100 0110 1001 xxxx xxxx */
7070		void upd7810_device::NEI_A_xx()
7071		{
7072		UINT8 tmp, imm;
7073
7074		RDOPARG( imm );
7075		tmp = A - imm;
7076		ZHC_SUB( tmp, A, 0 );
7077		SKIP_NZ;
7078		}
7079
7080		/* 74 6a: 0111 0100 0110 1010 xxxx xxxx */
7081		void upd7810_device::NEI_B_xx()
7082		{
7083		UINT8 tmp, imm;
7084
7085		RDOPARG( imm );
7086		tmp = B - imm;
7087		ZHC_SUB( tmp, B, 0 );
7088		SKIP_NZ;
7089		}
7090
7091		/* 74 6b: 0111 0100 0110 1011 xxxx xxxx */
7092		void upd7810_device::NEI_C_xx()
7093		{
7094		UINT8 tmp, imm;
7095
7096		RDOPARG( imm );
7097		tmp = C - imm;
7098		ZHC_SUB( tmp, C, 0 );
7099		SKIP_NZ;
7100		}
7101
7102		/* 74 6c: 0111 0100 0110 1100 xxxx xxxx */
7103		void upd7810_device::NEI_D_xx()
7104		{
7105		UINT8 tmp, imm;
7106
7107		RDOPARG( imm );
7108		tmp = D - imm;
7109		ZHC_SUB( tmp, D, 0 );
7110		SKIP_NZ;
7111		}
7112
7113		/* 74 6d: 0111 0100 0110 1101 xxxx xxxx */
7114		void upd7810_device::NEI_E_xx()
7115		{
7116		UINT8 tmp, imm;
7117
7118		RDOPARG( imm );
7119		tmp = E - imm;
7120		ZHC_SUB( tmp, E, 0 );
7121		SKIP_NZ;
7122		}
7123
7124		/* 74 6e: 0111 0100 0110 1110 xxxx xxxx */
7125		void upd7810_device::NEI_H_xx()
7126		{
7127		UINT8 tmp, imm;
7128
7129		RDOPARG( imm );
7130		tmp = H - imm;
7131		ZHC_SUB( tmp, H, 0 );
7132		SKIP_NZ;
7133		}
7134
7135		/* 74 6f: 0111 0100 0110 1111 xxxx xxxx */
7136		void upd7810_device::NEI_L_xx()
7137		{
7138		UINT8 tmp, imm;
7139
7140		RDOPARG( imm );
7141		tmp = L - imm;
7142		ZHC_SUB( tmp, L, 0 );
7143		SKIP_NZ;
7144		}
7145
7146		/* 74 70: 0111 0100 0111 0000 xxxx xxxx */
7147		void upd7810_device::SBI_V_xx()
7148		{
7149		UINT8 tmp, imm;
7150
7151		RDOPARG( imm );
7152		tmp = V - imm - (PSW & CY);
7153		ZHC_SUB( tmp, V, (PSW & CY) );
7154		V = tmp;
7155		}
7156
7157		/* 74 71: 0111 0100 0111 0001 xxxx xxxx */
7158		void upd7810_device::SBI_A_xx()
7159		{
7160		UINT8 tmp, imm;
7161
7162		RDOPARG( imm );
7163		tmp = A - imm - (PSW & CY);
7164		ZHC_SUB( tmp, A, (PSW & CY) );
7165		A = tmp;
7166		}
7167
7168		/* 74 72: 0111 0100 0111 0010 xxxx xxxx */
7169		void upd7810_device::SBI_B_xx()
7170		{
7171		UINT8 tmp, imm;
7172
7173		RDOPARG( imm );
7174		tmp = B - imm - (PSW & CY);
7175		ZHC_SUB( tmp, B, (PSW & CY) );
7176		B = tmp;
7177		}
7178
7179		/* 74 73: 0111 0100 0111 0011 xxxx xxxx */
7180		void upd7810_device::SBI_C_xx()
7181		{
7182		UINT8 tmp, imm;
7183
7184		RDOPARG( imm );
7185		tmp = C - imm - (PSW & CY);
7186		ZHC_SUB( tmp, C, (PSW & CY) );
7187		C = tmp;
7188		}
7189
7190		/* 74 74: 0111 0100 0111 0100 xxxx xxxx */
7191		void upd7810_device::SBI_D_xx()
7192		{
7193		UINT8 tmp, imm;
7194
7195		RDOPARG( imm );
7196		tmp = D - imm - (PSW & CY);
7197		ZHC_SUB( tmp, D, (PSW & CY) );
7198		D = tmp;
7199		}
7200
7201		/* 74 75: 0111 0100 0111 0101 xxxx xxxx */
7202		void upd7810_device::SBI_E_xx()
7203		{
7204		UINT8 tmp, imm;
7205
7206		RDOPARG( imm );
7207		tmp = E - imm - (PSW & CY);
7208		ZHC_SUB( tmp, E, (PSW & CY) );
7209		E = tmp;
7210		}
7211
7212		/* 74 76: 0111 0100 0111 0110 xxxx xxxx */
7213		void upd7810_device::SBI_H_xx()
7214		{
7215		UINT8 tmp, imm;
7216
7217		RDOPARG( imm );
7218		tmp = H - imm - (PSW & CY);
7219		ZHC_SUB( tmp, H, (PSW & CY) );
7220		H = tmp;
7221		}
7222
7223		/* 74 77: 0111 0100 0111 0111 xxxx xxxx */
7224		void upd7810_device::SBI_L_xx()
7225		{
7226		UINT8 tmp, imm;
7227
7228		RDOPARG( imm );
7229		tmp = L - imm - (PSW & CY);
7230		ZHC_SUB( tmp, L, (PSW & CY) );
7231		L = tmp;
7232		}
7233
7234		/* 74 78: 0111 0100 0111 1000 xxxx xxxx */
7235		void upd7810_device::EQI_V_xx()
7236		{
7237		UINT8 tmp, imm;
7238
7239		RDOPARG( imm );
7240		tmp = V - imm;
7241		ZHC_SUB( tmp, V, 0 );
7242		SKIP_Z;
7243		}
7244
7245		/* 74 79: 0111 0100 0111 1001 xxxx xxxx */
7246		void upd7810_device::EQI_A_xx()
7247		{
7248		UINT8 tmp, imm;
7249
7250		RDOPARG( imm );
7251		tmp = A - imm;
7252		ZHC_SUB( tmp, A, 0 );
7253		SKIP_Z;
7254		}
7255
7256		/* 74 7a: 0111 0100 0111 1010 xxxx xxxx */
7257		void upd7810_device::EQI_B_xx()
7258		{
7259		UINT8 tmp, imm;
7260
7261		RDOPARG( imm );
7262		tmp = B - imm;
7263		ZHC_SUB( tmp, B, 0 );
7264		SKIP_Z;
7265		}
7266
7267		/* 74 7b: 0111 0100 0111 1011 xxxx xxxx */
7268		void upd7810_device::EQI_C_xx()
7269		{
7270		UINT8 tmp, imm;
7271
7272		RDOPARG( imm );
7273		tmp = C - imm;
7274		ZHC_SUB( tmp, C, 0 );
7275		SKIP_Z;
7276		}
7277
7278		/* 74 7c: 0111 0100 0111 1100 xxxx xxxx */
7279		void upd7810_device::EQI_D_xx()
7280		{
7281		UINT8 tmp, imm;
7282
7283		RDOPARG( imm );
7284		tmp = D - imm;
7285		ZHC_SUB( tmp, D, 0 );
7286		SKIP_Z;
7287		}
7288
7289		/* 74 7d: 0111 0100 0111 1101 xxxx xxxx */
7290		void upd7810_device::EQI_E_xx()
7291		{
7292		UINT8 tmp, imm;
7293
7294		RDOPARG( imm );
7295		tmp = E - imm;
7296		ZHC_SUB( tmp, E, 0 );
7297		SKIP_Z;
7298		}
7299
7300		/* 74 7e: 0111 0100 0111 1110 xxxx xxxx */
7301		void upd7810_device::EQI_H_xx()
7302		{
7303		UINT8 tmp, imm;
7304
7305		RDOPARG( imm );
7306		tmp = H - imm;
7307		ZHC_SUB( tmp, H, 0 );
7308		SKIP_Z;
7309		}
7310
7311		/* 74 7f: 0111 0100 0111 1111 xxxx xxxx */
7312		void upd7810_device::EQI_L_xx()
7313		{
7314		UINT8 tmp, imm;
7315
7316		RDOPARG( imm );
7317		tmp = L - imm;
7318		ZHC_SUB( tmp, L, 0 );
7319		SKIP_Z;
7320		}
7321
7322		/* 74 88: 0111 0100 1000 1000 oooo oooo */
7323		void upd7810_device::ANAW_wa()
7324		{
7325		PAIR ea = m_va;
7326		RDOPARG( ea.b.l );
7327
7328		A &= RM( ea.d );
7329		SET_Z(A);
7330		}
7331
7332		/* 74 8d: 0111 0100 1000 1101 */
7333		void upd7810_device::DAN_EA_BC()
7334		{
7335		EA &= BC;
7336		SET_Z(EA);
7337		}
7338
7339		/* 74 8e: 0111 0100 1000 1110 */
7340		void upd7810_device::DAN_EA_DE()
7341		{
7342		EA &= DE;
7343		SET_Z(EA);
7344		}
7345
7346		/* 74 8f: 0111 0100 1000 1111 */
7347		void upd7810_device::DAN_EA_HL()
7348		{
7349		EA &= HL;
7350		SET_Z(EA);
7351		}
7352
7353		/* 74 90: 0111 0100 1001 0000 oooo oooo */
7354		void upd7810_device::XRAW_wa()
7355		{
7356		PAIR ea = m_va;
7357		RDOPARG( ea.b.l );
7358
7359		A ^= RM( ea.d );
7360		SET_Z(A);
7361		}
7362
7363		/* 74 95: 0111 0100 1001 0101 */
7364		void upd7810_device::DXR_EA_BC()
7365		{
7366		EA ^= BC;
7367		SET_Z(EA);
7368		}
7369
7370		/* 74 96: 0111 0100 1001 0110 */
7371		void upd7810_device::DXR_EA_DE()
7372		{
7373		EA ^= DE;
7374		SET_Z(EA);
7375		}
7376
7377		/* 74 97: 0111 0100 1001 0111 */
7378		void upd7810_device::DXR_EA_HL()
7379		{
7380		EA ^= HL;
7381		SET_Z(EA);
7382		}
7383
7384		/* 74 98: 0111 0100 1001 1000 oooo oooo */
7385		void upd7810_device::ORAW_wa()
7386		{
7387		PAIR ea = m_va;
7388		RDOPARG( ea.b.l );
7389
7390		A \|= RM( ea.d );
7391		SET_Z(A);
7392		}
7393
7394		/* 74 9d: 0111 0100 1001 1101 */
7395		void upd7810_device::DOR_EA_BC()
7396		{
7397		EA \|= BC;
7398		SET_Z(EA);
7399		}
7400
7401		/* 74 9e: 0111 0100 1001 1110 */
7402		void upd7810_device::DOR_EA_DE()
7403		{
7404		EA \|= DE;
7405		SET_Z(EA);
7406		}
7407
7408		/* 74 9f: 0111 0100 1001 1111 */
7409		void upd7810_device::DOR_EA_HL()
7410		{
7411		EA \|= HL;
7412		SET_Z(EA);
7413		}
7414
7415		/* 74 a0: 0111 0100 1010 0000 oooo oooo */
7416		void upd7810_device::ADDNCW_wa()
7417		{
7418		PAIR ea = m_va;
7419		UINT8 tmp;
7420
7421		RDOPARG( ea.b.l );
7422
7423		tmp = A + RM( ea.d );
7424		ZHC_ADD( tmp, A, 0 );
7425		A = tmp;
7426		SKIP_NC;
7427		}
7428
7429		/* 74 a5: 0111 0100 1010 0101 */
7430		void upd7810_device::DADDNC_EA_BC()
7431		{
7432		UINT16 tmp = EA + BC;
7433
7434		ZHC_ADD( tmp, EA, 0 );
7435		EA = tmp;
7436		SKIP_NC;
7437		}
7438
7439		/* 74 a6: 0111 0100 1010 0110 */
7440		void upd7810_device::DADDNC_EA_DE()
7441		{
7442		UINT16 tmp = EA + DE;
7443
7444		ZHC_ADD( tmp, EA, 0 );
7445		EA = tmp;
7446		SKIP_NC;
7447		}
7448
7449		/* 74 a7: 0111 0100 1010 0111 */
7450		void upd7810_device::DADDNC_EA_HL()
7451		{
7452		UINT16 tmp = EA + HL;
7453
7454		ZHC_ADD( tmp, EA, 0 );
7455		EA = tmp;
7456		SKIP_NC;
7457		}
7458
7459		/* 74 a8: 0111 0100 1010 1000 oooo oooo */
7460		void upd7810_device::GTAW_wa()
7461		{
7462		PAIR ea = m_va;
7463		UINT16 tmp;
7464
7465		RDOPARG( ea.b.l );
7466		tmp = A - RM( ea.d ) - 1;
7467		ZHC_SUB( tmp, A, 0 );
7468		SKIP_NC;
7469		}
7470
7471		/* 74 ad: 0111 0100 1010 1101 */
7472		void upd7810_device::DGT_EA_BC()
7473		{
7474		UINT32 tmp = EA - BC - 1;
7475		ZHC_SUB( tmp, EA, 0 );
7476		SKIP_NC;
7477		}
7478
7479		/* 74 ae: 0111 0100 1010 1110 */
7480		void upd7810_device::DGT_EA_DE()
7481		{
7482		UINT32 tmp = EA - DE - 1;
7483		ZHC_SUB( tmp, EA, 0 );
7484		SKIP_NC;
7485		}
7486
7487		/* 74 af: 0111 0100 1010 1111 */
7488		void upd7810_device::DGT_EA_HL()
7489		{
7490		UINT32 tmp = EA - HL - 1;
7491		ZHC_SUB( tmp, EA, 0 );
7492		SKIP_NC;
7493		}
7494
7495		/* 74 b0: 0111 0100 1011 0000 oooo oooo */
7496		void upd7810_device::SUBNBW_wa()
7497		{
7498		PAIR ea = m_va;
7499		UINT8 tmp;
7500
7501		RDOPARG( ea.b.l );
7502		tmp = A - RM( ea.d );
7503		ZHC_SUB( tmp, A, 0 );
7504		A = tmp;
7505		SKIP_NC;
7506		}
7507
7508		/* 74 b5: 0111 0100 1011 0101 */
7509		void upd7810_device::DSUBNB_EA_BC()
7510		{
7511		UINT16 tmp = EA - BC;
7512		ZHC_SUB( tmp, EA, 0 );
7513		EA = tmp;
7514		SKIP_NC;
7515		}
7516
7517		/* 74 b6: 0111 0100 1011 0110 */
7518		void upd7810_device::DSUBNB_EA_DE()
7519		{
7520		UINT16 tmp = EA - DE;
7521		ZHC_SUB( tmp, EA, 0 );
7522		EA = tmp;
7523		SKIP_NC;
7524		}
7525
7526		/* 74 b7: 0111 0100 1011 0111 */
7527		void upd7810_device::DSUBNB_EA_HL()
7528		{
7529		UINT16 tmp;
7530
7531		tmp = EA - HL;
7532		ZHC_SUB( tmp, EA, 0 );
7533		EA = tmp;
7534		SKIP_NC;
7535		}
7536
7537		/* 74 b8: 0111 0100 1011 1000 oooo oooo */
7538		void upd7810_device::LTAW_wa()
7539		{
7540		PAIR ea = m_va;
7541		UINT8 tmp;
7542
7543		RDOPARG( ea.b.l );
7544		tmp = A - RM( ea.d );
7545		ZHC_SUB( tmp, A, 0 );
7546		SKIP_CY;
7547		}
7548
7549		/* 74 bd: 0111 0100 1011 1101 */
7550		void upd7810_device::DLT_EA_BC()
7551		{
7552		UINT16 tmp = EA - BC;
7553		ZHC_SUB( tmp, EA, 0 );
7554		SKIP_CY;
7555		}
7556
7557		/* 74 be: 0111 0100 1011 1110 */
7558		void upd7810_device::DLT_EA_DE()
7559		{
7560		UINT16 tmp = EA - DE;
7561		ZHC_SUB( tmp, EA, 0 );
7562		SKIP_CY;
7563		}
7564
7565		/* 74 bf: 0111 0100 1011 1111 */
7566		void upd7810_device::DLT_EA_HL()
7567		{
7568		UINT16 tmp = EA - HL;
7569		ZHC_SUB( tmp, EA, 0 );
7570		SKIP_CY;
7571		}
7572
7573		/* 74 c0: 0111 0100 1100 0000 oooo oooo */
7574		void upd7810_device::ADDW_wa()
7575		{
7576		PAIR ea = m_va;
7577		UINT8 tmp;
7578		RDOPARG( ea.b.l );
7579		tmp = A + RM( ea.d );
7580		ZHC_ADD( tmp, A, 0 );
7581		A = tmp;
7582		}
7583
7584		/* 74 c5: 0111 0100 1100 0101 */
7585		void upd7810_device::DADD_EA_BC()
7586		{
7587		UINT16 tmp = EA + BC;
7588		ZHC_ADD( tmp, EA, 0 );
7589		EA = tmp;
7590		}
7591
7592		/* 74 c6: 0111 0100 1100 0110 */
7593		void upd7810_device::DADD_EA_DE()
7594		{
7595		UINT16 tmp = EA + DE;
7596		ZHC_ADD( tmp, EA, 0 );
7597		EA = tmp;
7598		}
7599
7600		/* 74 c7: 0111 0100 1100 0111 */
7601		void upd7810_device::DADD_EA_HL()
7602		{
7603		UINT16 tmp = EA + HL;
7604		ZHC_ADD( tmp, EA, 0 );
7605		EA = tmp;
7606		}
7607
7608		/* 74 c8: 0111 0100 1100 1000 oooo oooo */
7609		void upd7810_device::ONAW_wa()
7610		{
7611		PAIR ea = m_va;
7612		RDOPARG( ea.b.l );
7613
7614		if (A & RM( ea.d ))
7615		PSW = (PSW & ~Z) \| SK;
7616		else
7617		PSW \|= Z;
7618		}
7619
7620		/* 74 cd: 0111 0100 1100 1101 */
7621		void upd7810_device::DON_EA_BC()
7622		{
7623		if (EA & BC)
7624		PSW = (PSW & ~Z) \| SK;
7625		else
7626		PSW \|= Z;
7627		}
7628
7629		/* 74 ce: 0111 0100 1100 1110 */
7630		void upd7810_device::DON_EA_DE()
7631		{
7632		if (EA & DE)
7633		PSW = (PSW & ~Z) \| SK;
7634		else
7635		PSW \|= Z;
7636		}
7637
7638		/* 74 cf: 0111 0100 1100 1111 */
7639		void upd7810_device::DON_EA_HL()
7640		{
7641		if (EA & HL)
7642		PSW = (PSW & ~Z) \| SK;
7643		else
7644		PSW \|= Z;
7645		}
7646
7647		/* 74 d0: 0111 0100 1101 0000 oooo oooo */
7648		void upd7810_device::ADCW_wa()
7649		{
7650		PAIR ea = m_va;
7651		UINT8 tmp;
7652
7653		RDOPARG( ea.b.l );
7654		tmp = A + RM( ea.d ) + (PSW & CY);
7655		ZHC_ADD( tmp, A, (PSW & CY) );
7656		A = tmp;
7657		}
7658
7659		/* 74 d5: 0111 0100 1101 0101 */
7660		void upd7810_device::DADC_EA_BC()
7661		{
7662		UINT16 tmp = EA + BC + (PSW & CY);
7663		ZHC_ADD( tmp, EA, (PSW & CY) );
7664		EA = tmp;
7665		}
7666
7667		/* 74 d6: 0111 0100 1101 0110 */
7668		void upd7810_device::DADC_EA_DE()
7669		{
7670		UINT16 tmp = EA + DE + (PSW & CY);
7671		ZHC_ADD( tmp, EA, (PSW & CY) );
7672		EA = tmp;
7673		}
7674
7675		/* 74 d7: 0111 0100 1101 0111 */
7676		void upd7810_device::DADC_EA_HL()
7677		{
7678		UINT16 tmp = EA + HL + (PSW & CY);
7679		ZHC_ADD( tmp, EA, (PSW & CY) );
7680		EA = tmp;
7681		}
7682
7683		/* 74 d8: 0111 0100 1101 1000 oooo oooo */
7684		void upd7810_device::OFFAW_wa()
7685		{
7686		PAIR ea = m_va;
7687		RDOPARG( ea.b.l );
7688
7689		if ( A & RM( ea.d ) )
7690		PSW &= ~Z;
7691		else
7692		PSW = PSW \| Z \| SK;
7693		}
7694
7695		/* 74 dd: 0111 0100 1101 1101 */
7696		void upd7810_device::DOFF_EA_BC()
7697		{
7698		if ( EA & BC )
7699		PSW &= ~Z;
7700		else
7701		PSW = PSW \| Z \| SK;
7702		}
7703
7704		/* 74 de: 0111 0100 1101 1110 */
7705		void upd7810_device::DOFF_EA_DE()
7706		{
7707		if ( EA & DE )
7708		PSW &= ~Z;
7709		else
7710		PSW = PSW \| Z \| SK;
7711		}
7712
7713		/* 74 df: 0111 0100 1101 1111 */
7714		void upd7810_device::DOFF_EA_HL()
7715		{
7716		if ( EA & HL )
7717		PSW &= ~Z;
7718		else
7719		PSW = PSW \| Z \| SK;
7720		}
7721
7722		/* 74 e0: 0111 0100 1110 0000 oooo oooo */
7723		void upd7810_device::SUBW_wa()
7724		{
7725		PAIR ea = m_va;
7726		UINT8 tmp;
7727
7728		RDOPARG( ea.b.l );
7729		tmp = A - RM( ea.d );
7730		ZHC_SUB( tmp, A, 0 );
7731		A = tmp;
7732		}
7733
7734		/* 74 e5: 0111 0100 1110 0101 */
7735		void upd7810_device::DSUB_EA_BC()
7736		{
7737		UINT16 tmp = EA - BC;
7738		ZHC_SUB( tmp, EA, 0 );
7739		EA = tmp;
7740		}
7741
7742		/* 74 e6: 0111 0100 1110 0110 */
7743		void upd7810_device::DSUB_EA_DE()
7744		{
7745		UINT16 tmp = EA - DE;
7746		ZHC_SUB( tmp, EA, 0 );
7747		EA = tmp;
7748		}
7749
7750		/* 74 e7: 0111 0100 1110 0111 */
7751		void upd7810_device::DSUB_EA_HL()
7752		{
7753		UINT16 tmp = EA - HL;
7754		ZHC_SUB( tmp, EA, 0 );
7755		EA = tmp;
7756		}
7757
7758		/* 74 e8: 0111 0100 1110 1000 oooo oooo */
7759		void upd7810_device::NEAW_wa()
7760		{
7761		PAIR ea = m_va;
7762		UINT8 tmp;
7763
7764		RDOPARG( ea.b.l );
7765		tmp = A - RM( ea.d );
7766		ZHC_SUB( tmp, A, 0 );
7767		SKIP_NZ;
7768		}
7769
7770		/* 74 ed: 0111 0100 1110 1101 */
7771		void upd7810_device::DNE_EA_BC()
7772		{
7773		UINT16 tmp;
7774
7775		tmp = EA - BC;
7776		ZHC_SUB( tmp, EA, 0 );
7777		SKIP_NZ;
7778		}
7779
7780		/* 74 ee: 0111 0100 1110 1110 */
7781		void upd7810_device::DNE_EA_DE()
7782		{
7783		UINT16 tmp;
7784
7785		tmp = EA - DE;
7786		ZHC_SUB( tmp, EA, 0 );
7787		SKIP_NZ;
7788		}
7789
7790		/* 74 ef: 0111 0100 1110 1111 */
7791		void upd7810_device::DNE_EA_HL()
7792		{
7793		UINT16 tmp;
7794
7795		tmp = EA - HL;
7796		ZHC_SUB( tmp, EA, 0 );
7797		SKIP_NZ;
7798		}
7799
7800		/* 74 f0: 0111 0100 1111 0000 oooo oooo */
7801		void upd7810_device::SBBW_wa()
7802		{
7803		PAIR ea = m_va;
7804		UINT8 tmp;
7805
7806		RDOPARG( ea.b.l );
7807		tmp = A - RM( ea.d ) - (PSW & CY);
7808		ZHC_SUB( tmp, A, (PSW & CY) );
7809		A = tmp;
7810		}
7811
7812		/* 74 f5: 0111 0100 1111 0101 */
7813		void upd7810_device::DSBB_EA_BC()
7814		{
7815		UINT16 tmp = EA - BC - (PSW & CY);
7816		ZHC_SUB( tmp, EA, (PSW & CY) );
7817		EA = tmp;
7818		}
7819
7820		/* 74 f6: 0111 0100 1111 0110 */
7821		void upd7810_device::DSBB_EA_DE()
7822		{
7823		UINT16 tmp = EA - DE - (PSW & CY);
7824		ZHC_SUB( tmp, EA, (PSW & CY) );
7825		EA = tmp;
7826		}
7827
7828		/* 74 f7: 0111 0100 1111 0111 */
7829		void upd7810_device::DSBB_EA_HL()
7830		{
7831		UINT16 tmp = EA - HL - (PSW & CY);
7832		ZHC_SUB( tmp, EA, (PSW & CY) );
7833		EA = tmp;
7834		}
7835
7836		/* 74 f8: 0111 0100 1111 1000 oooo oooo */
7837		void upd7810_device::EQAW_wa()
7838		{
7839		PAIR ea = m_va;
7840		UINT8 tmp;
7841
7842		RDOPARG( ea.b.l );
7843		tmp = A - RM( ea.d );
7844		ZHC_SUB( tmp, A, 0 );
7845		SKIP_Z;
7846		}
7847
7848		/* 74 fd: 0111 0100 1111 1101 */
7849		void upd7810_device::DEQ_EA_BC()
7850		{
7851		UINT16 tmp;
7852
7853		tmp = EA - BC;
7854		ZHC_SUB( tmp, EA, 0 );
7855		SKIP_Z;
7856		}
7857
7858		/* 74 fe: 0111 0100 1111 1110 */
7859		void upd7810_device::DEQ_EA_DE()
7860		{
7861		UINT16 tmp;
7862
7863		tmp = EA - DE;
7864		ZHC_SUB( tmp, EA, 0 );
7865		SKIP_Z;
7866		}
7867
7868		/* 74 ff: 0111 0100 1111 1111 */
7869		void upd7810_device::DEQ_EA_HL()
7870		{
7871		UINT16 tmp;
7872
7873		tmp = EA - HL;
7874		ZHC_SUB( tmp, EA, 0 );
7875		SKIP_Z;
7876		}
7877
7878		/************************************************
7879		* main opcodes
7880		************************************************/
7881
7882		/* 00: 0000 0000 */
7883		void upd7810_device::NOP()
7884		{
7885		}
7886
7887		/* 01: 0000 0001 oooo oooo */
7888		void upd7810_device::LDAW_wa()
7889		{
7890		PAIR ea = m_va;
7891
7892		RDOPARG( ea.b.l );
7893
7894		A = RM( ea.d );
7895		}
7896
7897		/* 02: 0000 0010 */
7898		void upd7810_device::INX_SP()
7899		{
7900		SP++;
7901		}
7902
7903		/* 03: 0000 0011 */
7904		void upd7810_device::DCX_SP()
7905		{
7906		SP--;
7907		}
7908
7909		/* 04: 0000 0100 llll llll hhhh hhhh */
7910		void upd7810_device::LXI_S_w()
7911		{
7912		RDOPARG( SPL );
7913		RDOPARG( SPH );
7914		}
7915
7916		/* 05: 0000 0101 oooo oooo xxxx xxxx */
7917		void upd7810_device::ANIW_wa_xx()
7918		{
7919		PAIR ea = m_va;
7920		UINT8 m, imm;
7921
7922		RDOPARG( ea.b.l );
7923		RDOPARG( imm );
7924		m = RM( ea.d );
7925		m &= imm;
7926		WM( ea.d, m );
7927		SET_Z(m);
7928		}
7929
7930		/* 07: 0000 0111 xxxx xxxx */
7931		/* ANI_A_xx already defined (long form) */
7932
7933		/* 08: 0000 1000 */
7934		void upd7810_device::MOV_A_EAH()
7935		{
7936		A = EAH;
7937		}
7938
7939		/* 09: 0000 1001 */
7940		void upd7810_device::MOV_A_EAL()
7941		{
7942		A = EAL;
7943		}
7944
7945		/* 0a: 0000 1010 */
7946		void upd7810_device::MOV_A_B()
7947		{
7948		A = B;
7949		}
7950
7951		/* 0b: 0000 1011 */
7952		void upd7810_device::MOV_A_C()
7953		{
7954		A = C;
7955		}
7956
7957		/* 0c: 0000 1100 */
7958		void upd7810_device::MOV_A_D()
7959		{
7960		A = D;
7961		}
7962
7963		/* 0d: 0000 1101 */
7964		void upd7810_device::MOV_A_E()
7965		{
7966		A = E;
7967		}
7968
7969		/* 0e: 0000 1110 */
7970		void upd7810_device::MOV_A_H()
7971		{
7972		A = H;
7973		}
7974
7975		/* 0f: 0000 1111 */
7976		void upd7810_device::MOV_A_L()
7977		{
7978		A = L;
7979		}
7980
7981		/* 10: 0001 0000 */
7982		void upd7810_device::EXA()
7983		{
7984		UINT16 tmp;
7985		tmp = EA; EA = EA2; EA2 = tmp;
7986		tmp = VA; VA = VA2; VA2 = tmp;
7987		}
7988
7989		/* 11: 0001 0001 */
7990		void upd7810_device::EXX()
7991		{
7992		UINT16 tmp;
7993		tmp = BC; BC = BC2; BC2 = tmp;
7994		tmp = DE; DE = DE2; DE2 = tmp;
7995		tmp = HL; HL = HL2; HL2 = tmp;
7996		}
7997
7998		/* 48 AD (7807 only) */
7999		void upd7810_device::EXR()
8000		{
8001		UINT16 tmp;
8002		tmp = BC; BC = BC2; BC2 = tmp;
8003		tmp = DE; DE = DE2; DE2 = tmp;
8004		tmp = HL; HL = HL2; HL2 = tmp;
8005		tmp = EA; EA = EA2; EA2 = tmp;
8006		tmp = VA; VA = VA2; VA2 = tmp;
8007		}
8008
8009		/* 12: 0001 0010 */
8010		void upd7810_device::INX_BC()
8011		{
8012		BC++;
8013		}
8014
8015		/* 13: 0001 0011 */
8016		void upd7810_device::DCX_BC()
8017		{
8018		BC--;
8019		}
8020
8021		/* 14: 0001 0100 llll llll hhhh hhhh */
8022		void upd7810_device::LXI_B_w()
8023		{
8024		RDOPARG( C );
8025		RDOPARG( B );
8026		}
8027
8028		/* 15: 0001 0101 oooo oooo xxxx xxxx */
8029		void upd7810_device::ORIW_wa_xx()
8030		{
8031		PAIR ea = m_va;
8032		UINT8 m, imm;
8033
8034		RDOPARG( ea.b.l );
8035		RDOPARG( imm );
8036		m = RM( ea.d );
8037		m \|= imm;
8038		WM( ea.d, m );
8039		SET_Z(m);
8040		}
8041
8042		/* 16: 0001 0110 xxxx xxxx */
8043		/* XRI_A_xx already defined (long form) */
8044
8045		/* 17: 0001 0111 xxxx xxxx */
8046		/* ORI_A_xx already defined (long form) */
8047
8048		/* 18: 0001 1000 */
8049		void upd7810_device::MOV_EAH_A()
8050		{
8051		EAH = A;
8052		}
8053
8054		/* 19: 0001 1001 */
8055		void upd7810_device::MOV_EAL_A()
8056		{
8057		EAL = A;
8058		}
8059
8060		/* 1a: 0001 1010 */
8061		void upd7810_device::MOV_B_A()
8062		{
8063		B = A;
8064		}
8065
8066		/* 1b: 0001 1011 */
8067		void upd7810_device::MOV_C_A()
8068		{
8069		C = A;
8070		}
8071
8072		/* 1c: 0001 1100 */
8073		void upd7810_device::MOV_D_A()
8074		{
8075		D = A;
8076		}
8077
8078		/* 1d: 0001 1101 */
8079		void upd7810_device::MOV_E_A()
8080		{
8081		E = A;
8082		}
8083
8084		/* 1e: 0001 1110 */
8085		void upd7810_device::MOV_H_A()
8086		{
8087		H = A;
8088		}
8089
8090		/* 1f: 0001 1111 */
8091		void upd7810_device::MOV_L_A()
8092		{
8093		L = A;
8094		}
8095
8096		/* 20: 0010 0000 oooo oooo */
8097		void upd7810_device::INRW_wa()
8098		{
8099		PAIR ea = m_va;
8100		UINT8 tmp, m;
8101
8102		RDOPARG( ea.b.l );
8103		m = RM( ea.d );
8104		tmp = m + 1;
8105		ZHC_ADD( tmp, m, 0 );
8106		WM( ea.d, tmp );
8107		SKIP_CY;
8108		}
8109
8110		/* 21: 0010 0001 */
8111		void upd7810_device::JB()
8112		{
8113		PC = BC;
8114		}
8115
8116		/* 22: 0010 0010 */
8117		void upd7810_device::INX_DE()
8118		{
8119		DE++;
8120		}
8121
8122		/* 23: 0010 0011 */
8123		void upd7810_device::DCX_DE()
8124		{
8125		DE--;
8126		}
8127
8128		/* 24: 0010 0100 llll llll hhhh hhhh */
8129		void upd7810_device::LXI_D_w()
8130		{
8131		RDOPARG( E );
8132		RDOPARG( D );
8133		}
8134
8135		/* 25: 0010 0101 oooo oooo xxxx xxxx */
8136		void upd7810_device::GTIW_wa_xx()
8137		{
8138		PAIR ea = m_va;
8139		UINT8 m, imm;
8140		UINT16 tmp;
8141
8142		RDOPARG( ea.b.l );
8143		RDOPARG( imm );
8144		m = RM( ea.d );
8145		tmp = m - imm - 1;
8146		ZHC_SUB( tmp, m, 0 );
8147		SKIP_NC;
8148		}
8149
8150		/* 26: 0010 0110 xxxx xxxx */
8151		/* ADINC_A_xx already defined (long form) */
8152
8153		/* 27: 0010 0111 xxxx xxxx */
8154		/* GTI_A_xx already defined (long form) */
8155
8156		/* 29: 0010 1001 */
8157		void upd7810_device::LDAX_B()
8158		{
8159		A = RM( BC );
8160		}
8161
8162		/* 2a: 0010 1010 */
8163		void upd7810_device::LDAX_D()
8164		{
8165		A = RM( DE );
8166		}
8167
8168		/* 2b: 0010 1011 */
8169		void upd7810_device::LDAX_H()
8170		{
8171		A = RM( HL );
8172		}
8173
8174		/* 2c: 0010 1100 */
8175		void upd7810_device::LDAX_Dp()
8176		{
8177		A = RM( DE );
8178		DE++;
8179		}
8180
8181		/* 2d: 0010 1101 dddd dddd */
8182		void upd7810_device::LDAX_Hp()
8183		{
8184		A = RM( HL );
8185		HL++;
8186		}
8187
8188		/* 2e: 0010 1110 dddd dddd */
8189		void upd7810_device::LDAX_Dm()
8190		{
8191		A = RM( DE );
8192		DE--;
8193		}
8194
8195		/* 2f: 0010 1111 dddd dddd */
8196		void upd7810_device::LDAX_Hm()
8197		{
8198		A = RM( HL );
8199		HL--;
8200		}
8201
8202		/* 30: 0011 0000 oooo oooo */
8203		void upd7810_device::DCRW_wa()
8204		{
8205		PAIR ea = m_va;
8206		UINT8 tmp, m;
8207
8208		RDOPARG( ea.b.l );
8209		m = RM( ea.d );
8210		tmp = m - 1;
8211		ZHC_SUB( tmp, m, 0 );
8212		WM( ea.d, tmp );
8213		SKIP_CY;
8214		}
8215
8216		/* 31: 0011 0001 */
8217		void upd7810_device::BLOCK()
8218		{
8219		WM( DE, RM( HL ) );
8220		DE++;
8221		HL++;
8222		C--;
8223		if (C == 0xff)
8224		PSW \|= CY;
8225		else
8226		{
8227		PSW &= ~CY;
8228		PC--;
8229		}
8230		}
8231
8232		/* 32: 0011 0010 */
8233		void upd7810_device::INX_HL()
8234		{
8235		HL++;
8236		}
8237
8238		/* 33: 0011 0011 */
8239		void upd7810_device::DCX_HL()
8240		{
8241		HL--;
8242		}
8243
8244		/* 34: 0011 0100 llll llll hhhh hhhh */
8245		void upd7810_device::LXI_H_w()
8246		{
8247		if (PSW & L0) { /* overlay active? */
8248		PC+=2;
8249		return;
8250		}
8251		RDOPARG( L );
8252		RDOPARG( H );
8253		PSW \|= L0;
8254		}
8255
8256		/* 35: 0011 0101 oooo oooo xxxx xxxx */
8257		void upd7810_device::LTIW_wa_xx()
8258		{
8259		PAIR ea = m_va;
8260		UINT8 tmp, m, imm;
8261
8262		RDOPARG( ea.b.l );
8263		RDOPARG( imm );
8264		m = RM( ea.d );
8265		tmp = m - imm;
8266		ZHC_SUB( tmp, m, 0 );
8267		SKIP_CY;
8268		}
8269
8270		/* 36: 0011 0110 xxxx xxxx */
8271		/* SUINB_A_xx already defined (long form) */
8272
8273		/* 37: 0011 0111 xxxx xxxx */
8274		/* LTI_A_xx already defined (long form) */
8275
8276		/* 39: 0011 1001 */
8277		void upd7810_device::STAX_B()
8278		{
8279		WM( BC, A );
8280		}
8281
8282		/* 3a: 0011 1010 */
8283		void upd7810_device::STAX_D()
8284		{
8285		WM( DE, A );
8286		}
8287
8288		/* 3b: 0011 1011 */
8289		void upd7810_device::STAX_H()
8290		{
8291		WM( HL, A );
8292		}
8293
8294		/* 3c: 0011 1100 */
8295		void upd7810_device::STAX_Dp()
8296		{
8297		WM( DE, A );
8298		DE++;
8299		}
8300
8301		/* 3d: 0011 1101 */
8302		void upd7810_device::STAX_Hp()
8303		{
8304		WM( HL, A );
8305		HL++;
8306		}
8307
8308		/* 3e: 0011 1110 */
8309		void upd7810_device::STAX_Dm()
8310		{
8311		WM( DE, A );
8312		DE--;
8313		}
8314
8315		/* 3f: 0011 1111 */
8316		void upd7810_device::STAX_Hm()
8317		{
8318		WM( HL, A );
8319		HL--;
8320		}
8321
8322		/* 40: 0100 0000 llll llll hhhh hhhh */
8323		void upd7810_device::CALL_w()
8324		{
8325		PAIR w;
8326		w.d = 0;
8327
8328		RDOPARG( w.b.l );
8329		RDOPARG( w.b.h );
8330
8331		SP--;
8332		WM( SPD, PCH );
8333		SP--;
8334		WM( SPD, PCL );
8335
8336		PC = w.w.l;
8337		}
8338
8339		/* 41: 0100 0001 */
8340		void upd7810_device::INR_A()
8341		{
8342		UINT8 tmp = A + 1;
8343		ZHC_ADD( tmp, A, 0 );
8344		A = tmp;
8345		SKIP_CY;
8346		}
8347
8348		/* 42: 0100 0010 */
8349		void upd7810_device::INR_B()
8350		{
8351		UINT8 tmp = B + 1;
8352		ZHC_ADD( tmp, B, 0 );
8353		B = tmp;
8354		SKIP_CY;
8355		}
8356
8357		/* 43: 0100 0011 */
8358		void upd7810_device::INR_C()
8359		{
8360		UINT8 tmp = C + 1;
8361		ZHC_ADD( tmp, C, 0 );
8362		C = tmp;
8363		SKIP_CY;
8364		}
8365
8366		/* 44: 0100 0100 llll llll hhhh hhhh */
8367		void upd7810_device::LXI_EA_s()
8368		{
8369		RDOPARG( EAL );
8370		RDOPARG( EAH );
8371		}
8372
8373		/* 45: 0100 0101 oooo oooo xxxx xxxx */
8374		void upd7810_device::ONIW_wa_xx()
8375		{
8376		PAIR ea = m_va;
8377		UINT8 imm;
8378
8379		RDOPARG( ea.b.l );
8380		RDOPARG( imm );
8381
8382		if (RM( ea.d ) & imm)
8383		PSW \|= SK;
8384		}
8385
8386		/* 46: 0100 0110 xxxx xxxx */
8387		/* ADI_A_xx already defined (long form) */
8388
8389		/* 47: 0100 0111 xxxx xxxx */
8390		/* ONI_A_xx already defined (long form) */
8391
8392		/* 48: prefix */
8393		void upd7810_device::PRE_48()
8394		{
8395		RDOP(OP2);
8396		m_icount -= m_op48[OP2].cycles;
8397		handle_timers(m_op48[OP2].cycles);
8398		(this->*m_op48[OP2].opfunc)();
8399		}
8400
8401		/* 49: 0100 1001 xxxx xxxx */
8402		void upd7810_device::MVIX_BC_xx()
8403		{
8404		UINT8 imm;
8405		RDOPARG( imm );
8406		WM( BC, imm );
8407		}
8408
8409		/* 4a: 0100 1010 xxxx xxxx */
8410		void upd7810_device::MVIX_DE_xx()
8411		{
8412		UINT8 imm;
8413		RDOPARG( imm );
8414		WM( DE, imm );
8415		}
8416
8417		/* 4b: 0100 1011 xxxx xxxx */
8418		void upd7810_device::MVIX_HL_xx()
8419		{
8420		UINT8 imm;
8421		RDOPARG( imm );
8422		WM( HL, imm );
8423		}
8424
8425		/* 4c: prefix */
8426		void upd7810_device::PRE_4C()
8427		{
8428		RDOP(OP2);
8429		m_icount -= m_op4C[OP2].cycles;
8430		handle_timers(m_op4C[OP2].cycles);
8431		(this->*m_op4C[OP2].opfunc)();
8432		}
8433
8434		/* 4d: prefix */
8435		void upd7810_device::PRE_4D()
8436		{
8437		RDOP(OP2);
8438		m_icount -= m_op4D[OP2].cycles;
8439		handle_timers(m_op4D[OP2].cycles);
8440		(this->*m_op4D[OP2].opfunc)();
8441		}
8442
8443		/* 4e: 0100 111d dddd dddd */
8444		void upd7810_device::JRE()
8445		{
8446		UINT8 offs;
8447		RDOPARG( offs );
8448		if (OP & 0x01)
8449		PC -= 256 - offs;
8450		else
8451		PC += offs;
8452		}
8453
8454		/* 50: 0101 0000 */
8455		void upd7810_device::EXH()
8456		{
8457		UINT16 tmp;
8458		tmp = HL; HL = HL2; HL2 = tmp;
8459		}
8460
8461		/* 51: 0101 0001 */
8462		void upd7810_device::DCR_A()
8463		{
8464		UINT8 tmp = A - 1;
8465		ZHC_SUB( tmp, A, 0 );
8466		A = tmp;
8467		SKIP_CY;
8468		}
8469
8470		/* 52: 0101 0010 */
8471		void upd7810_device::DCR_B()
8472		{
8473		UINT8 tmp = B - 1;
8474		ZHC_SUB( tmp, B, 0 );
8475		B = tmp;
8476		SKIP_CY;
8477		}
8478
8479		/* 53: 0101 0011 */
8480		void upd7810_device::DCR_C()
8481		{
8482		UINT8 tmp = C - 1;
8483		ZHC_SUB( tmp, C, 0 );
8484		C = tmp;
8485		SKIP_CY;
8486		}
8487
8488		/* 54: 0101 0100 llll llll hhhh hhhh */
8489		void upd7810_device::JMP_w()
8490		{
8491		PAIR w;
8492		w.d = 0;
8493
8494		RDOPARG( w.b.l );
8495		RDOPARG( w.b.h );
8496
8497		PCD = w.d;
8498		}
8499
8500		/* 55: 0101 0101 oooo oooo xxxx xxxx */
8501		void upd7810_device::OFFIW_wa_xx()
8502		{
8503		PAIR ea = m_va;
8504		UINT8 imm;
8505
8506		RDOPARG( ea.b.l );
8507		RDOPARG( imm );
8508
8509		if (0 == (RM( ea.d ) & imm))
8510		PSW \|= SK;
8511		}
8512
8513		/* 56: 0101 0110 xxxx xxxx */
8514		/* ACI_A_xx already defined (long form) */
8515
8516		/* 57: 0101 0111 xxxx xxxx */
8517		/* OFFI_A_xx already defined (long form) */
8518
8519		/* 58: 0101 1000 oooo oooo (7810 only) */
8520		void upd7810_device::BIT_0_wa()
8521		{
8522		PAIR ea = m_va;
8523
8524		RDOPARG( ea.b.l );
8525
8526		if (RM( ea.d ) & 0x01)
8527		PSW \|= SK;
8528		}
8529
8530		/* 59: 0101 1001 oooo oooo (7810 only) */
8531		void upd7810_device::BIT_1_wa()
8532		{
8533		PAIR ea = m_va;
8534
8535		RDOPARG( ea.b.l );
8536
8537		if (RM( ea.d ) & 0x02)
8538		PSW \|= SK;
8539		}
8540
8541		/* 5a: 0101 1010 oooo oooo (7810 only) */
8542		void upd7810_device::BIT_2_wa()
8543		{
8544		PAIR ea = m_va;
8545
8546		RDOPARG( ea.b.l );
8547
8548		if (RM( ea.d ) & 0x04)
8549		PSW \|= SK;
8550		}
8551
8552		/* 5b: 0101 1011 oooo oooo (7810 only) */
8553		void upd7810_device::BIT_3_wa()
8554		{
8555		PAIR ea = m_va;
8556
8557		RDOPARG( ea.b.l );
8558
8559		if (RM( ea.d ) & 0x08)
8560		PSW \|= SK;
8561		}
8562
8563		/* 5c: 0101 1100 oooo oooo (7810 only) */
8564		void upd7810_device::BIT_4_wa()
8565		{
8566		PAIR ea = m_va;
8567
8568		RDOPARG( ea.b.l );
8569
8570		if (RM( ea.d ) & 0x10)
8571		PSW \|= SK;
8572		}
8573
8574		/* 5d: 0101 1101 oooo oooo (7810 only) */
8575		void upd7810_device::BIT_5_wa()
8576		{
8577		PAIR ea = m_va;
8578
8579		RDOPARG( ea.b.l );
8580
8581		if (RM( ea.d ) & 0x20)
8582		PSW \|= SK;
8583		}
8584
8585		/* 5e: 0101 1110 oooo oooo (7810 only) */
8586		void upd7810_device::BIT_6_wa()
8587		{
8588		PAIR ea = m_va;
8589
8590		RDOPARG( ea.b.l );
8591
8592		if (RM( ea.d ) & 0x40)
8593		PSW \|= SK;
8594		}
8595
8596		/* 5f: 0101 1111 oooo oooo (7810 only) */
8597		void upd7810_device::BIT_7_wa()
8598		{
8599		PAIR ea = m_va;
8600
8601		RDOPARG( ea.b.l );
8602
8603		if (RM( ea.d ) & 0x80)
8604		PSW \|= SK;
8605		}
8606
8607		/* 5d: 0101 1111 bbbb bbbb (7807 only) */
8608		void upd7810_device::SKN_bit()
8609		{
8610		UINT8 imm;
8611		int val;
8612
8613		RDOPARG( imm );
8614
8615		switch( imm & 0x1f )
8616		{
8617		case 0x10: /* PA */
8618		val = RP( UPD7810_PORTA );
8619		break;
8620		case 0x11: /* PB */
8621		val = RP( UPD7810_PORTB );
8622		break;
8623		case 0x12: /* PC */
8624		val = RP( UPD7810_PORTC );
8625		break;
8626		case 0x13: /* PD */
8627		val = RP( UPD7810_PORTD );
8628		break;
8629		case 0x15: /* PF */
8630		val = RP( UPD7810_PORTF );
8631		break;
8632		case 0x16: /* MKH */
8633		val = MKH;
8634		break;
8635		case 0x17: /* MKL */
8636		val = MKL;
8637		break;
8638		case 0x19: /* SMH */
8639		val = SMH;
8640		break;
8641		case 0x1b: /* EOM */
8642		val = EOM;
8643		break;
8644		case 0x1d: /* TMM */
8645		val = TMM;
8646		break;
8647		case 0x1e: /* PT */
8648		val = RP( UPD7807_PORTT );
8649		break;
8650		default:
8651		logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", tag(), OP, imm, PC);
8652		val = 0;
8653		break;
8654		}
8655
8656		if (~val & (1 << (imm >> 5)))
8657		PSW \|= SK;
8658		}
8659
8660		/* 58: 0101 1000 bbbb bbbb (7807 only) */
8661		void upd7810_device::SETB()
8662		{
8663		UINT8 imm;
8664		int bit;
8665
8666		RDOPARG( imm );
8667		bit = imm >> 5;
8668
8669		switch( imm & 0x1f )
8670		{
8671		case 0x10: /* PA */
8672		WP( UPD7810_PORTA, RP( UPD7810_PORTA ) \| (1 << bit));
8673		break;
8674		case 0x11: /* PB */
8675		WP( UPD7810_PORTB, RP( UPD7810_PORTB ) \| (1 << bit));
8676		break;
8677		case 0x12: /* PC */
8678		WP( UPD7810_PORTC, RP( UPD7810_PORTC ) \| (1 << bit));
8679		break;
8680		case 0x13: /* PD */
8681		WP( UPD7810_PORTD, RP( UPD7810_PORTD ) \| (1 << bit));
8682		break;
8683		case 0x15: /* PF */
8684		WP( UPD7810_PORTF, RP( UPD7810_PORTF ) \| (1 << bit));
8685		break;
8686		case 0x16: /* MKH */
8687		MKH \|= (1 << bit);
8688		break;
8689		case 0x17: /* MKL */
8690		MKL \|= (1 << bit);
8691		break;
8692		case 0x19: /* SMH */
8693		SMH \|= (1 << bit);
8694		break;
8695		case 0x1b: /* EOM */
8696		EOM \|= (1 << bit);
8697		break;
8698		case 0x1d: /* TMM */
8699		TMM \|= (1 << bit);
8700		break;
8701		// case 0x1e: /* PT */
8702		// PT is input only
8703		// break;
8704		default:
8705		logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", tag(), OP, imm, PC);
8706		break;
8707		}
8708		}
8709
8710		/* 5b: 0101 1011 bbbb bbbb (7807 only) */
8711		void upd7810_device::CLR()
8712		{
8713		UINT8 imm;
8714		int bit;
8715
8716		RDOPARG( imm );
8717		bit = imm >> 5;
8718
8719		switch( imm & 0x1f )
8720		{
8721		case 0x10: /* PA */
8722		WP( UPD7810_PORTA, RP( UPD7810_PORTA ) & ~(1 << bit));
8723		break;
8724		case 0x11: /* PB */
8725		WP( UPD7810_PORTB, RP( UPD7810_PORTB ) & ~(1 << bit));
8726		break;
8727		case 0x12: /* PC */
8728		WP( UPD7810_PORTC, RP( UPD7810_PORTC ) & ~(1 << bit));
8729		break;
8730		case 0x13: /* PD */
8731		WP( UPD7810_PORTD, RP( UPD7810_PORTD ) & ~(1 << bit));
8732		break;
8733		case 0x15: /* PF */
8734		WP( UPD7810_PORTF, RP( UPD7810_PORTF ) & ~(1 << bit));
8735		break;
8736		case 0x16: /* MKH */
8737		MKH &= ~(1 << bit);
8738		break;
8739		case 0x17: /* MKL */
8740		MKL &= ~(1 << bit);
8741		break;
8742		case 0x19: /* SMH */
8743		SMH &= ~(1 << bit);
8744		break;
8745		case 0x1b: /* EOM */
8746		EOM &= ~(1 << bit);
8747		break;
8748		case 0x1d: /* TMM */
8749		TMM &= ~(1 << bit);
8750		break;
8751		// case 0x1e: /* PT */
8752		// PT is input only
8753		// break;
8754		default:
8755		logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", tag(), OP, imm, PC);
8756		break;
8757		}
8758		}
8759
8760		/* 5d: 0101 1111 bbbb bbbb (7807 only) */
8761		void upd7810_device::SK_bit()
8762		{
8763		UINT8 imm;
8764		int val;
8765
8766		RDOPARG( imm );
8767
8768		switch( imm & 0x1f )
8769		{
8770		case 0x10: /* PA */
8771		val = RP( UPD7810_PORTA );
8772		break;
8773		case 0x11: /* PB */
8774		val = RP( UPD7810_PORTB );
8775		break;
8776		case 0x12: /* PC */
8777		val = RP( UPD7810_PORTC );
8778		break;
8779		case 0x13: /* PD */
8780		val = RP( UPD7810_PORTD );
8781		break;
8782		case 0x15: /* PF */
8783		val = RP( UPD7810_PORTF );
8784		break;
8785		case 0x16: /* MKH */
8786		val = MKH;
8787		break;
8788		case 0x17: /* MKL */
8789		val = MKL;
8790		break;
8791		case 0x19: /* SMH */
8792		val = SMH;
8793		break;
8794		case 0x1b: /* EOM */
8795		val = EOM;
8796		break;
8797		case 0x1d: /* TMM */
8798		val = TMM;
8799		break;
8800		case 0x1e: /* PT */
8801		val = RP( UPD7807_PORTT );
8802		break;
8803		default:
8804		logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", tag(), OP, imm, PC);
8805		val = 0;
8806		break;
8807		}
8808
8809		if (val & (1 << (imm >> 5)))
8810		PSW \|= SK;
8811		}
8812
8813		/* 60:*/
8814		void upd7810_device::PRE_60()
8815		{
8816		RDOP(OP2);
8817		m_icount -= m_op60[OP2].cycles;
8818		handle_timers(m_op60[OP2].cycles);
8819		(this->*m_op60[OP2].opfunc)();
8820		}
8821
8822		/* 61: 0110 0001 */
8823		void upd7810_device::DAA()
8824		{
8825		UINT8 l = A & 0x0f, h = A >> 4, tmp, adj = 0x00, old_cy = PSW & CY;
8826
8827		if (0 == (PSW & HC))
8828		{
8829		if (l < 10)
8830		{
8831		if (!(h < 10 && 0 == (PSW & CY)))
8832		adj = 0x60;
8833		}
8834		else
8835		{
8836		if (h < 9 && 0 == (PSW & CY))
8837		adj = 0x06;
8838		else
8839		adj = 0x66;
8840		}
8841		}
8842		else
8843		if (l < 3)
8844		{
8845		if (h < 10 && 0 == (PSW & CY))
8846		adj = 0x06;
8847		else
8848		adj = 0x66;
8849		}
8850		tmp = A + adj;
8851		ZHC_ADD( tmp, A, PSW & CY );
8852		PSW \|= old_cy;
8853		A = tmp;
8854		}
8855
8856		/* 62: 0110 0010 */
8857		void upd7810_device::RETI()
8858		{
8859		PCL = RM( SPD );
8860		SP++;
8861		PCH = RM( SPD );
8862		SP++;
8863		PSW = RM( SPD );
8864		SP++;
8865		}
8866
8867		/* 63: 0110 0011 oooo oooo */
8868		void upd7810_device::STAW_wa()
8869		{
8870		PAIR ea = m_va;
8871
8872		RDOPARG( ea.b.l );
8873
8874		WM( ea.d, A );
8875		}
8876
8877		/* 64: prefix */
8878		void upd7810_device::PRE_64()
8879		{
8880		RDOP(OP2);
8881		m_icount -= m_op64[OP2].cycles;
8882		handle_timers(m_op64[OP2].cycles);
8883		(this->*m_op64[OP2].opfunc)();
8884		}
8885
8886		/* 65: 0110 0101 oooo oooo xxxx xxxx */
8887		void upd7810_device::NEIW_wa_xx()
8888		{
8889		PAIR ea = m_va;
8890		UINT8 tmp, m, imm;
8891
8892		RDOPARG( ea.b.l );
8893		RDOPARG( imm );
8894		m = RM( ea.d );
8895		tmp = m - imm;
8896		ZHC_SUB( tmp, m, 0 );
8897		SKIP_NZ;
8898		}
8899
8900		/* 66: 0110 0110 xxxx xxxx */
8901		/* SUI_A_xx already defined (long form) */
8902
8903		/* 67: 0110 0111 xxxx xxxx */
8904		/* NEI_A_xx already defined (long form) */
8905
8906		/* 68: 0110 1000 xxxx xxxx */
8907		void upd7810_device::MVI_V_xx()
8908		{
8909		RDOPARG( V );
8910		}
8911
8912		/* 69: 0110 1001 xxxx xxxx */
8913		void upd7810_device::MVI_A_xx()
8914		{
8915		if (PSW & L1) { /* overlay active? */
8916		PC++;
8917		return; /* NOP */
8918		}
8919		RDOPARG( A );
8920		PSW \|= L1;
8921		}
8922
8923		/* 6a: 0110 1010 xxxx xxxx */
8924		void upd7810_device::MVI_B_xx()
8925		{
8926		RDOPARG( B );
8927		}
8928
8929		/* 6b: 0110 1011 xxxx xxxx */
8930		void upd7810_device::MVI_C_xx()
8931		{
8932		RDOPARG( C );
8933		}
8934
8935		/* 6c: 0110 1100 xxxx xxxx */
8936		void upd7810_device::MVI_D_xx()
8937		{
8938		RDOPARG( D );
8939		}
8940
8941		/* 6d: 0110 1101 xxxx xxxx */
8942		void upd7810_device::MVI_E_xx()
8943		{
8944		RDOPARG( E );
8945		}
8946
8947		/* 6e: 0110 1110 xxxx xxxx */
8948		void upd7810_device::MVI_H_xx()
8949		{
8950		RDOPARG( H );
8951		}
8952
8953		/* 6f: 0110 1111 xxxx xxxx */
8954		void upd7810_device::MVI_L_xx()
8955		{
8956		if (PSW & L0) { /* overlay active? */
8957		PC++;
8958		return; /* NOP */
8959		}
8960		RDOPARG( L );
8961		PSW \|= L0;
8962		}
8963
8964		/* 70: prefix */
8965		void upd7810_device::PRE_70()
8966		{
8967		RDOP(OP2);
8968		m_icount -= m_op70[OP2].cycles;
8969		handle_timers(m_op70[OP2].cycles);
8970		(this->*m_op70[OP2].opfunc)();
8971		}
8972
8973		/* 71: 0111 0001 oooo oooo xxxx xxxx */
8974		void upd7810_device::MVIW_wa_xx()
8975		{
8976		PAIR ea = m_va;
8977		UINT8 imm;
8978
8979		RDOPARG( ea.b.l );
8980		RDOPARG( imm );
8981
8982		WM( ea.d, imm );
8983		}
8984
8985		/* 72: 0111 0010 */
8986		void upd7810_device::SOFTI()
8987		{
8988		SP--;
8989		WM( SPD, PSW );
8990		SP--;
8991		WM( SPD, PCH );
8992		SP--;
8993		WM( SPD, PCL );
8994
8995		PC = 0x0060;
8996		}
8997
8998		/* 74: prefix */
8999		void upd7810_device::PRE_74()
9000		{
9001		RDOP(OP2);
9002		m_icount -= m_op74[OP2].cycles;
9003		handle_timers(m_op74[OP2].cycles);
9004		(this->*m_op74[OP2].opfunc)();
9005		}
9006
9007		/* 75: 0111 0101 oooo oooo xxxx xxxx */
9008		void upd7810_device::EQIW_wa_xx()
9009		{
9010		PAIR ea = m_va;
9011		UINT8 tmp, m, imm;
9012
9013		RDOPARG( ea.b.l );
9014		RDOPARG( imm );
9015		m = RM( ea.d );
9016		tmp = m - imm;
9017		ZHC_SUB( tmp, m, 0 );
9018		SKIP_Z;
9019		}
9020
9021		/* 76: 0111 0110 xxxx xxxx */
9022		/* SBI_A_xx already defined (long form) */
9023
9024		/* 77: 0111 0111 xxxx xxxx */
9025		/* EQI_A_xx already defined (long form) */
9026
9027		/* 78: 0111 1ddd dddd dddd */
9028		void upd7810_device::CALF()
9029		{
9030		PAIR w;
9031		w.d = 0;
9032
9033		RDOPARG( w.b.l );
9034		w.b.h = 0x08 + (OP & 0x07);
9035
9036		SP--;
9037		WM( SPD, PCH );
9038		SP--;
9039		WM( SPD, PCL );
9040
9041		PCD = w.d;
9042		}
9043
9044		/* 80: 100t tttt */
9045		void upd7810_device::CALT()
9046		{
9047		PAIR w;
9048		w.d = 0;
9049
9050		w.w.l = 0x80 + 2 * (OP & 0x1f);
9051
9052		SP--;
9053		WM( SPD, PCH );
9054		SP--;
9055		WM( SPD, PCL );
9056
9057		PCL=RM(w.w.l);
9058		PCH=RM(w.w.l+1);
9059		}
9060
9061		/* a0: 1010 0000 */
9062		void upd7810_device::POP_VA()
9063		{
9064		A = RM( SPD );
9065		SP++;
9066		V = RM( SPD );
9067		SP++;
9068		}
9069
9070		/* a1: 1010 0001 */
9071		void upd7810_device::POP_BC()
9072		{
9073		C = RM( SPD );
9074		SP++;
9075		B = RM( SPD );
9076		SP++;
9077		}
9078
9079		/* a2: 1010 0010 */
9080		void upd7810_device::POP_DE()
9081		{
9082		E = RM( SPD );
9083		SP++;
9084		D = RM( SPD );
9085		SP++;
9086		}
9087
9088		/* a3: 1010 0011 */
9089		void upd7810_device::POP_HL()
9090		{
9091		L = RM( SPD );
9092		SP++;
9093		H = RM( SPD );
9094		SP++;
9095		}
9096
9097		/* a4: 1010 0100 */
9098		void upd7810_device::POP_EA()
9099		{
9100		EAL = RM( SPD );
9101		SP++;
9102		EAH = RM( SPD );
9103		SP++;
9104		}
9105
9106		/* a5: 1010 0101 */
9107		void upd7810_device::DMOV_EA_BC()
9108		{
9109		EA = BC;
9110		}
9111
9112		/* a6: 1010 0110 */
9113		void upd7810_device::DMOV_EA_DE()
9114		{
9115		EA = DE;
9116		}
9117
9118		/* a7: 1010 0111 */
9119		void upd7810_device::DMOV_EA_HL()
9120		{
9121		EA = HL;
9122		}
9123
9124		/* a8: 1010 1000 */
9125		void upd7810_device::INX_EA()
9126		{
9127		EA++;
9128		}
9129
9130		/* a9: 1010 1001 */
9131		void upd7810_device::DCX_EA()
9132		{
9133		EA--;
9134		}
9135
9136		/* aa: 1010 1010 */
9137		void upd7810_device::EI()
9138		{
9139		IFF = 1;
9140		}
9141
9142		/* ab: 1010 1011 dddd dddd */
9143		void upd7810_device::LDAX_D_xx()
9144		{
9145		UINT16 ea;
9146		RDOPARG( ea );
9147		ea += DE;
9148		A = RM( ea );
9149		}
9150
9151		/* ac: 1010 1100 */
9152		void upd7810_device::LDAX_H_A()
9153		{
9154		UINT16 ea;
9155		ea = HL + A;
9156		A = RM( ea );
9157		}
9158
9159		/* ad: 1010 1101 */
9160		void upd7810_device::LDAX_H_B()
9161		{
9162		UINT16 ea;
9163		ea = HL + B;
9164		A = RM( ea );
9165		}
9166
9167		/* ae: 1010 1110 */
9168		void upd7810_device::LDAX_H_EA()
9169		{
9170		UINT16 ea;
9171		ea = HL + EA;
9172		A = RM( ea );
9173		}
9174
9175		/* af: 1010 1111 dddd dddd */
9176		void upd7810_device::LDAX_H_xx()
9177		{
9178		UINT16 ea;
9179		RDOPARG( ea );
9180		ea += HL;
9181		A = RM( ea );
9182		}
9183
9184		/* b0: 1011 0000 */
9185		void upd7810_device::PUSH_VA()
9186		{
9187		SP--;
9188		WM( SPD, V );
9189		SP--;
9190		WM( SPD, A );
9191		}
9192
9193		/* b1: 1011 0001 */
9194		void upd7810_device::PUSH_BC()
9195		{
9196		SP--;
9197		WM( SPD, B );
9198		SP--;
9199		WM( SPD, C );
9200		}
9201
9202		/* b2: 1011 0010 */
9203		void upd7810_device::PUSH_DE()
9204		{
9205		SP--;
9206		WM( SPD, D );
9207		SP--;
9208		WM( SPD, E );
9209		}
9210
9211		/* b3: 1011 0011 */
9212		void upd7810_device::PUSH_HL()
9213		{
9214		SP--;
9215		WM( SPD, H );
9216		SP--;
9217		WM( SPD, L );
9218		}
9219
9220		/* b4: 1011 0100 */
9221		void upd7810_device::PUSH_EA()
9222		{
9223		SP--;
9224		WM( SPD, EAH );
9225		SP--;
9226		WM( SPD, EAL );
9227		}
9228
9229		/* b5: 1011 0101 */
9230		void upd7810_device::DMOV_BC_EA()
9231		{
9232		BC = EA;
9233		}
9234
9235		/* b6: 1011 0110 */
9236		void upd7810_device::DMOV_DE_EA()
9237		{
9238		DE = EA;
9239		}
9240
9241		/* b7: 1011 0111 */
9242		void upd7810_device::DMOV_HL_EA()
9243		{
9244		HL = EA;
9245		}
9246
9247		/* b8: 1011 1000 */
9248		void upd7810_device::RET()
9249		{
9250		PCL = RM( SPD );
9251		SP++;
9252		PCH = RM( SPD );
9253		SP++;
9254		}
9255
9256		/* b9: 1011 1001 */
9257		void upd7810_device::RETS()
9258		{
9259		PCL = RM( SPD );
9260		SP++;
9261		PCH = RM( SPD );
9262		SP++;
9263		PSW\|=SK; /* skip one instruction */
9264		}
9265
9266		/* ba: 1011 1010 */
9267		void upd7810_device::DI()
9268		{
9269		IFF = 0;
9270		}
9271
9272		/* bb: 1011 1011 dddd dddd */
9273		void upd7810_device::STAX_D_xx()
9274		{
9275		UINT16 ea;
9276		RDOPARG(ea);
9277		ea += DE;
9278		WM( ea, A );
9279		}
9280
9281		/* bc: 1011 1100 */
9282		void upd7810_device::STAX_H_A()
9283		{
9284		UINT16 ea = A;
9285		ea += HL;
9286		WM( ea, A );
9287		}
9288
9289		/* bd: 1011 1101 */
9290		void upd7810_device::STAX_H_B()
9291		{
9292		UINT16 ea = B;
9293		ea += HL;
9294		WM( ea, A );
9295		}
9296
9297		/* be: 1011 1110 */
9298		void upd7810_device::STAX_H_EA()
9299		{
9300		UINT16 ea = EA;
9301		ea += HL;
9302		WM( ea, A );
9303		}
9304
9305		/* bf: 1011 1111 dddd dddd */
9306		void upd7810_device::STAX_H_xx()
9307		{
9308		UINT16 ea;
9309		RDOPARG( ea );
9310		ea += HL;
9311		WM( ea, A );
9312		}
9313
9314		/* c0: 11dd dddd */
9315		void upd7810_device::JR()
9316		{
9317		INT8 offs = (INT8)(OP << 2) >> 2;
9318		PC += offs;
9319		}
9320
9321		/*********************/
9322		/* */
9323		/* 7801 instructions */
9324		/* */
9325		/*********************/
9326
9327		void upd7810_device::CALT_7801()
9328		{
9329		PAIR w;
9330		w.d = 0;
9331
9332		w.w.l = 0x80 + 2 * (OP & 0x3f);
9333
9334		SP--;
9335		WM( SPD, PCH );
9336		SP--;
9337		WM( SPD, PCL );
9338
9339		PCL=RM(w.w.l);
9340		PCH=RM(w.w.l+1);
9341		}
9342
9343		/* DCR(W) and INR(W) instructions do not modify the CY register on at least 78c05 and 78c06 */
9344		void upd7810_device::DCR_A_7801()
9345		{
9346		UINT32 old_CY = PSW & CY;
9347		DCR_A();
9348		PSW = ( PSW & ~CY ) \| old_CY;
9349		}
9350
9351		void upd7810_device::DCR_B_7801()
9352		{
9353		UINT32 old_CY = PSW & CY;
9354		DCR_B();
9355		PSW = ( PSW & ~CY ) \| old_CY;
9356		}
9357
9358		void upd7810_device::DCR_C_7801()
9359		{
9360		UINT32 old_CY = PSW & CY;
9361		DCR_C();
9362		PSW = ( PSW & ~CY ) \| old_CY;
9363		}
9364
9365		void upd7810_device::DCRW_wa_7801()
9366		{
9367		UINT32 old_CY = PSW & CY;
9368		DCRW_wa();
9369		PSW = ( PSW & ~CY ) \| old_CY;
9370		}
9371
9372		void upd7810_device::INR_A_7801()
9373		{
9374		UINT32 old_CY = PSW & CY;
9375		INR_A();
9376		PSW = ( PSW & ~CY ) \| old_CY;
9377		}
9378
9379		void upd7810_device::INR_B_7801()
9380		{
9381		UINT32 old_CY = PSW & CY;
9382		INR_B();
9383		PSW = ( PSW & ~CY ) \| old_CY;
9384		}
9385
9386		void upd7810_device::INR_C_7801()
9387		{
9388		UINT32 old_CY = PSW & CY;
9389		INR_C();
9390		PSW = ( PSW & ~CY ) \| old_CY;
9391		}
9392
9393		void upd7810_device::INRW_wa_7801()
9394		{
9395		UINT32 old_CY = PSW & CY;
9396		INRW_wa();
9397		PSW = ( PSW & ~CY ) \| old_CY;
9398		}
9399
9400		void upd7810_device::IN()
9401		{
9402		logerror("unimplemented instruction: IN\n");
9403		}
9404
9405		void upd7810_device::OUT()
9406		{
9407		logerror("unimplemented instruction: OUT\n");
9408		}
9409
9410		void upd7810_device::MOV_A_S()
9411		{
9412		logerror("unimplemented instruction: MOV_A_S\n");
9413		}
9414
9415		void upd7810_device::MOV_S_A()
9416		{
9417		logerror("unimplemented instruction: MOV_A_S\n");
9418		}
9419
9420		void upd7810_device::PEN()
9421		{
9422		logerror("unimplemented instruction: PEN\n");
9423		}
9424
9425		void upd7810_device::PER()
9426		{
9427		logerror("unimplemented instruction: PER\n");
9428		}
9429
9430		void upd7810_device::PEX()
9431		{
9432		logerror("unimplemented instruction: PEX\n");
9433		}
9434
9435		void upd7810_device::SIO()
9436		{
9437		logerror("unimplemented instruction: SIO\n");
9438		}
9439
9440		void upd7810_device::SKIT_F0()
9441		{
9442		if (IRR & INTF0)
9443		PSW \|= SK;
9444		IRR &= ~INTF0;
9445		}
9446
9447		void upd7810_device::SKNIT_F0()
9448		{
9449		logerror("unimplemented instruction: SKNIT_F0\n");
9450		}
9451
9452		void upd7810_device::STM()
9453		{
9454		m_ovc0 = ( ( TMM & 0x04 ) ? 16 * 8 : 8 ) * TM0;
9455		}
9456
9457		void upd7810_device::STM_7801()
9458		{
9459		/* Set the timer flip/fliop */
9460		TO = 1;
9461		m_to_func(TO);
9462
9463		/* Reload the timer */
9464		m_ovc0 = 16 * ( TM0 + ( ( TM1 & 0x0f ) << 8 ) );
9465		}
9466
9467		void upd7810_device::MOV_MC_A_7801()
9468		{
9469		/* On the 7801 the mode C bits function as follows: */
9470		/* Cn=1 Cn=0 */
9471		/* PC0 Input Output */
9472		/* PC1 Input Output */
9473		/* PC2 Input -SCS Input */
9474		/* PC3 Output SAK Output */
9475		/* PC4 Output To Output */
9476		/* PC5 Output IO/-M Output */
9477		/* PC6 Output HLDA Output */
9478		/* PC7 Input HOLD Input */
9479		MC = 0x84 \| ( ( A & 0x02 ) ? 0x02 : 0x00 ) \| ( ( A & 0x01 ) ? 0x01 : 0x00 );
9480		}

trunk/src/emu/cpu/upd7810/7810tbl.inc
r30937	r30938
1		/*****************************************************************************
2		*
3		* Portable uPD7810/11, 7810H/11H, 78C10/C11/C14 emulator V0.2
4		* Copyright Juergen Buchmueller, all rights reserved.
5		*
6		* 7810tbl.inc - function pointer tables
7		*
8		*****************************************************************************/
9
10
11		const struct upd7810_device::opcode_s upd7810_device::s_op48[256] =
12		{
13		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 00: 0100 1000 0000 0000 */
14		{&upd7810_device::SLRC_A, 2, 8, 8,L0\|L1}, /* 01: 0100 1000 0000 0001 */
15		{&upd7810_device::SLRC_B, 2, 8, 8,L0\|L1}, /* 02: 0100 1000 0000 0010 */
16		{&upd7810_device::SLRC_C, 2, 8, 8,L0\|L1}, /* 03: 0100 1000 0000 0011 */
17		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 04: 0100 1000 0000 0100 */
18		{&upd7810_device::SLLC_A, 2, 8, 8,L0\|L1}, /* 05: 0100 1000 0000 0101 */
19		{&upd7810_device::SLLC_B, 2, 8, 8,L0\|L1}, /* 06: 0100 1000 0000 0110 */
20		{&upd7810_device::SLLC_C, 2, 8, 8,L0\|L1}, /* 07: 0100 1000 0000 0111 */
21		{&upd7810_device::SK_NV, 2, 8, 8,L0\|L1}, /* 08: 0100 1000 0000 1000 */
22		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 09: 0100 1000 0000 1001 */
23		{&upd7810_device::SK_CY, 2, 8, 8,L0\|L1}, /* 0a: 0100 1000 0000 1010 */
24		{&upd7810_device::SK_HC, 2, 8, 8,L0\|L1}, /* 0b: 0100 1000 0000 1011 */
25		{&upd7810_device::SK_Z, 2, 8, 8,L0\|L1}, /* 0c: 0100 1000 0000 1100 */
26		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 0d: 0100 1000 0000 1101 */
27		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 0e: 0100 1000 0000 1110 */
28		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 0f: 0100 1000 0000 1111 */
29
30		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 10: 0100 1000 0001 0000 */
31		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 11: 0100 1000 0001 0001 */
32		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 12: 0100 1000 0001 0010 */
33		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 13: 0100 1000 0001 0011 */
34		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 14: 0100 1000 0001 0100 */
35		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 15: 0100 1000 0001 0101 */
36		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 16: 0100 1000 0001 0110 */
37		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 17: 0100 1000 0001 0111 */
38		{&upd7810_device::SKN_NV, 2, 8, 8,L0\|L1}, /* 18: 0100 1000 0001 1000 */
39		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 19: 0100 1000 0001 1001 */
40		{&upd7810_device::SKN_CY, 2, 8, 8,L0\|L1}, /* 1a: 0100 1000 0001 1010 */
41		{&upd7810_device::SKN_HC, 2, 8, 8,L0\|L1}, /* 1b: 0100 1000 0001 1011 */
42		{&upd7810_device::SKN_Z, 2, 8, 8,L0\|L1}, /* 1c: 0100 1000 0001 1100 */
43		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 1d: 0100 1000 0001 1101 */
44		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 1e: 0100 1000 0001 1110 */
45		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 1f: 0100 1000 0001 1111 */
46
47		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 20: 0100 1000 0010 0000 */
48		{&upd7810_device::SLR_A, 2, 8, 8,L0\|L1}, /* 21: 0100 1000 0010 0001 */
49		{&upd7810_device::SLR_B, 2, 8, 8,L0\|L1}, /* 22: 0100 1000 0010 0010 */
50		{&upd7810_device::SLR_C, 2, 8, 8,L0\|L1}, /* 23: 0100 1000 0010 0011 */
51		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 24: 0100 1000 0010 0100 */
52		{&upd7810_device::SLL_A, 2, 8, 8,L0\|L1}, /* 25: 0100 1000 0010 0101 */
53		{&upd7810_device::SLL_B, 2, 8, 8,L0\|L1}, /* 26: 0100 1000 0010 0110 */
54		{&upd7810_device::SLL_C, 2, 8, 8,L0\|L1}, /* 27: 0100 1000 0010 0111 */
55		{&upd7810_device::JEA, 2, 8, 8,L0\|L1}, /* 28: 0100 1000 0010 1000 */
56		{&upd7810_device::CALB, 2,17,17,L0\|L1}, /* 29: 0100 1000 0010 1001 */
57		{&upd7810_device::CLC, 2, 8, 8,L0\|L1}, /* 2a: 0100 1000 0010 1010 */
58		{&upd7810_device::STC, 2, 8, 8,L0\|L1}, /* 2b: 0100 1000 0010 1011 */
59		{&upd7810_device::illegal, 2,32,32,L0\|L1}, /* 2c: 0100 1000 0010 1100 */
60		{&upd7810_device::MUL_A, 2,32,32,L0\|L1}, /* 2d: 0100 1000 0010 1101 */
61		{&upd7810_device::MUL_B, 2,32,32,L0\|L1}, /* 2e: 0100 1000 0010 1110 */
62		{&upd7810_device::MUL_C, 2,32,32,L0\|L1}, /* 2f: 0100 1000 0010 1111 */
63
64		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 30: 0100 1000 0011 0000 */
65		{&upd7810_device::RLR_A, 2, 8, 8,L0\|L1}, /* 31: 0100 1000 0011 0001 */
66		{&upd7810_device::RLR_B, 2, 8, 8,L0\|L1}, /* 32: 0100 1000 0011 0010 */
67		{&upd7810_device::RLR_C, 2, 8, 8,L0\|L1}, /* 33: 0100 1000 0011 0011 */
68		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 34: 0100 1000 0011 0100 */
69		{&upd7810_device::RLL_A, 2, 8, 8,L0\|L1}, /* 35: 0100 1000 0011 0101 */
70		{&upd7810_device::RLL_B, 2, 8, 8,L0\|L1}, /* 36: 0100 1000 0011 0110 */
71		{&upd7810_device::RLL_C, 2, 8, 8,L0\|L1}, /* 37: 0100 1000 0011 0111 */
72		{&upd7810_device::RLD, 2,17,17,L0\|L1}, /* 38: 0100 1000 0011 1000 */
73		{&upd7810_device::RRD, 2,17,17,L0\|L1}, /* 39: 0100 1000 0011 1001 */
74		{&upd7810_device::NEGA, 2, 8, 8,L0\|L1}, /* 3a: 0100 1000 0011 1010 */
75		{&upd7810_device::HALT, 2,12,12,L0\|L1}, /* 3b: 0100 1000 0011 1011 */
76		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 3c: 0100 1000 0011 1100 */
77		{&upd7810_device::DIV_A, 2,59,59,L0\|L1}, /* 3d: 0100 1000 0011 1101 */
78		{&upd7810_device::DIV_B, 2,59,59,L0\|L1}, /* 3e: 0100 1000 0011 1110 */
79		{&upd7810_device::DIV_C, 2,59,59,L0\|L1}, /* 3f: 0100 1000 0011 1111 */
80
81		{&upd7810_device::SKIT_NMI, 2, 8, 8,L0\|L1}, /* 40: 0100 1000 0100 0000 */
82		{&upd7810_device::SKIT_FT0, 2, 8, 8,L0\|L1}, /* 41: 0100 1000 0100 0001 */
83		{&upd7810_device::SKIT_FT1, 2, 8, 8,L0\|L1}, /* 42: 0100 1000 0100 0010 */
84		{&upd7810_device::SKIT_F1, 2, 8, 8,L0\|L1}, /* 43: 0100 1000 0100 0011 */
85		{&upd7810_device::SKIT_F2, 2, 8, 8,L0\|L1}, /* 44: 0100 1000 0100 0100 */
86		{&upd7810_device::SKIT_FE0, 2, 8, 8,L0\|L1}, /* 45: 0100 1000 0100 0101 */
87		{&upd7810_device::SKIT_FE1, 2, 8, 8,L0\|L1}, /* 46: 0100 1000 0100 0110 */
88		{&upd7810_device::SKIT_FEIN, 2, 8, 8,L0\|L1}, /* 47: 0100 1000 0100 0111 */
89		{&upd7810_device::SKIT_FAD, 2, 8, 8,L0\|L1}, /* 48: 0100 1000 0100 1000 */
90		{&upd7810_device::SKIT_FSR, 2, 8, 8,L0\|L1}, /* 49: 0100 1000 0100 1001 */
91		{&upd7810_device::SKIT_FST, 2, 8, 8,L0\|L1}, /* 4a: 0100 1000 0100 1010 */
92		{&upd7810_device::SKIT_ER, 2, 8, 8,L0\|L1}, /* 4b: 0100 1000 0100 1011 */
93		{&upd7810_device::SKIT_OV, 2, 8, 8,L0\|L1}, /* 4c: 0100 1000 0100 1100 */
94		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4d: 0100 1000 0100 1101 */
95		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4e: 0100 1000 0100 1110 */
96		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4f: 0100 1000 0100 1111 */
97
98		{&upd7810_device::SKIT_AN4, 2, 8, 8,L0\|L1}, /* 50: 0100 1000 0101 0000 */
99		{&upd7810_device::SKIT_AN5, 2, 8, 8,L0\|L1}, /* 51: 0100 1000 0101 0001 */
100		{&upd7810_device::SKIT_AN6, 2, 8, 8,L0\|L1}, /* 52: 0100 1000 0101 0010 */
101		{&upd7810_device::SKIT_AN7, 2, 8, 8,L0\|L1}, /* 53: 0100 1000 0101 0011 */
102		{&upd7810_device::SKIT_SB, 2, 8, 8,L0\|L1}, /* 54: 0100 1000 0101 0100 */
103		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 55: 0100 1000 0101 0101 */
104		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 56: 0100 1000 0101 0110 */
105		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 57: 0100 1000 0101 0111 */
106		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 58: 0100 1000 0101 1000 */
107		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 59: 0100 1000 0101 1001 */
108		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5a: 0100 1000 0101 1010 */
109		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5b: 0100 1000 0101 1011 */
110		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5c: 0100 1000 0101 1100 */
111		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5d: 0100 1000 0101 1101 */
112		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5e: 0100 1000 0101 1110 */
113		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5f: 0100 1000 0101 1111 */
114
115		{&upd7810_device::SKNIT_NMI, 2, 8, 8,L0\|L1}, /* 60: 0100 1000 0110 0000 */
116		{&upd7810_device::SKNIT_FT0, 2, 8, 8,L0\|L1}, /* 61: 0100 1000 0110 0001 */
117		{&upd7810_device::SKNIT_FT1, 2, 8, 8,L0\|L1}, /* 62: 0100 1000 0110 0010 */
118		{&upd7810_device::SKNIT_F1, 2, 8, 8,L0\|L1}, /* 63: 0100 1000 0110 0011 */
119		{&upd7810_device::SKNIT_F2, 2, 8, 8,L0\|L1}, /* 64: 0100 1000 0110 0100 */
120		{&upd7810_device::SKNIT_FE0, 2, 8, 8,L0\|L1}, /* 65: 0100 1000 0110 0101 */
121		{&upd7810_device::SKNIT_FE1, 2, 8, 8,L0\|L1}, /* 66: 0100 1000 0110 0110 */
122		{&upd7810_device::SKNIT_FEIN, 2, 8, 8,L0\|L1}, /* 67: 0100 1000 0110 0111 */
123		{&upd7810_device::SKNIT_FAD, 2, 8, 8,L0\|L1}, /* 68: 0100 1000 0110 1000 */
124		{&upd7810_device::SKNIT_FSR, 2, 8, 8,L0\|L1}, /* 69: 0100 1000 0110 1001 */
125		{&upd7810_device::SKNIT_FST, 2, 8, 8,L0\|L1}, /* 6a: 0100 1000 0110 1010 */
126		{&upd7810_device::SKNIT_ER, 2, 8, 8,L0\|L1}, /* 6b: 0100 1000 0110 1011 */
127		{&upd7810_device::SKNIT_OV, 2, 8, 8,L0\|L1}, /* 6c: 0100 1000 0110 1100 */
128		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6d: 0100 1000 0110 1101 */
129		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6e: 0100 1000 0110 1110 */
130		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6f: 0100 1000 0110 1111 */
131
132		{&upd7810_device::SKNIT_AN4, 2, 8, 8,L0\|L1}, /* 70: 0100 1000 0111 0000 */
133		{&upd7810_device::SKNIT_AN5, 2, 8, 8,L0\|L1}, /* 71: 0100 1000 0111 0001 */
134		{&upd7810_device::SKNIT_AN6, 2, 8, 8,L0\|L1}, /* 72: 0100 1000 0111 0010 */
135		{&upd7810_device::SKNIT_AN7, 2, 8, 8,L0\|L1}, /* 73: 0100 1000 0111 0011 */
136		{&upd7810_device::SKNIT_SB, 2, 8, 8,L0\|L1}, /* 74: 0100 1000 0111 0100 */
137		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 75: 0100 1000 0111 0101 */
138		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 76: 0100 1000 0111 0110 */
139		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 77: 0100 1000 0111 0111 */
140		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 78: 0100 1000 0111 1000 */
141		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 79: 0100 1000 0111 1001 */
142		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7a: 0100 1000 0111 1010 */
143		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7b: 0100 1000 0111 1011 */
144		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7c: 0100 1000 0111 1100 */
145		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7d: 0100 1000 0111 1101 */
146		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7e: 0100 1000 0111 1110 */
147		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7f: 0100 1000 0111 1111 */
148
149		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 80: 0100 1000 1000 0000 */
150		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 81: 0100 1000 1000 0001 */
151		{&upd7810_device::LDEAX_D, 2,14,11,L0\|L1}, /* 82: 0100 1000 1000 0010 */
152		{&upd7810_device::LDEAX_H, 2,14,11,L0\|L1}, /* 83: 0100 1000 1000 0011 */
153		{&upd7810_device::LDEAX_Dp, 2,14,11,L0\|L1}, /* 84: 0100 1000 1000 0100 */
154		{&upd7810_device::LDEAX_Hp, 2,14,11,L0\|L1}, /* 85: 0100 1000 1000 0101 */
155		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 86: 0100 1000 1000 0110 */
156		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 87: 0100 1000 1000 0111 */
157		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 88: 0100 1000 1000 1000 */
158		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 89: 0100 1000 1000 1001 */
159		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8a: 0100 1000 1000 1010 */
160		{&upd7810_device::LDEAX_D_xx, 3,20,20,L0\|L1}, /* 8b: 0100 1000 1000 1011 xxxx xxxx */
161		{&upd7810_device::LDEAX_H_A, 2,20,20,L0\|L1}, /* 8c: 0100 1000 1000 1100 */
162		{&upd7810_device::LDEAX_H_B, 2,20,20,L0\|L1}, /* 8d: 0100 1000 1000 1101 */
163		{&upd7810_device::LDEAX_H_EA, 2,20,20,L0\|L1}, /* 8e: 0100 1000 1000 1110 */
164		{&upd7810_device::LDEAX_H_xx, 3,20,20,L0\|L1}, /* 8f: 0100 1000 1000 1111 xxxx xxxx */
165
166		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 90: 0100 1000 1000 0000 */
167		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 91: 0100 1000 1000 0001 */
168		{&upd7810_device::STEAX_D, 2,14,11,L0\|L1}, /* 92: 0100 1000 1000 0010 */
169		{&upd7810_device::STEAX_H, 2,14,11,L0\|L1}, /* 93: 0100 1000 1000 0011 */
170		{&upd7810_device::STEAX_Dp, 2,14,11,L0\|L1}, /* 94: 0100 1000 1000 0100 */
171		{&upd7810_device::STEAX_Hp, 2,14,11,L0\|L1}, /* 95: 0100 1000 1000 0101 */
172		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 96: 0100 1000 1000 0110 */
173		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 97: 0100 1000 1000 0111 */
174		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 98: 0100 1000 1000 1000 */
175		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 99: 0100 1000 1000 1001 */
176		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9a: 0100 1000 1000 1010 */
177		{&upd7810_device::STEAX_D_xx, 3,20,20,L0\|L1}, /* 9b: 0100 1000 1000 1011 xxxx xxxx */
178		{&upd7810_device::STEAX_H_A, 2,20,20,L0\|L1}, /* 9c: 0100 1000 1000 1100 */
179		{&upd7810_device::STEAX_H_B, 2,20,20,L0\|L1}, /* 9d: 0100 1000 1000 1101 */
180		{&upd7810_device::STEAX_H_EA, 2,20,20,L0\|L1}, /* 9e: 0100 1000 1000 1110 */
181		{&upd7810_device::STEAX_H_xx, 3,20,20,L0\|L1}, /* 9f: 0100 1000 1000 1111 xxxx xxxx */
182
183		{&upd7810_device::DSLR_EA, 2, 8, 8,L0\|L1}, /* a0: 0100 1000 1010 0000 */
184		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a1: 0100 1000 1010 0001 */
185		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a2: 0100 1000 1010 0010 */
186		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a3: 0100 1000 1010 0011 */
187		{&upd7810_device::DSLL_EA, 2, 8, 8,L0\|L1}, /* a4: 0100 1000 1010 0100 */
188		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a5: 0100 1000 1010 0101 */
189		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a6: 0100 1000 1010 0110 */
190		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a7: 0100 1000 1010 0111 */
191		{&upd7810_device::TABLE, 2,17,17,L0\|L1}, /* a8: 0100 1000 1010 1000 */
192		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a9: 0100 1000 1010 1001 */
193		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* aa: 0100 1000 1010 1010 */
194		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ab: 0100 1000 1010 1011 */
195		// {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ac: 0100 1000 1010 1100 */
196		// {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ad: 0100 1000 1010 1101 */
197		// {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ae: 0100 1000 1010 1110 */
198		// {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* af: 0100 1000 1010 1111 */
199		{&upd7810_device::EXA, 2, 8, 8,L0\|L1}, /* ac: 0100 1000 1010 1100 / / 7807 */
200		{&upd7810_device::EXR, 2, 8, 8,L0\|L1}, /* ad: 0100 1000 1010 1101 / / 7807 */
201		{&upd7810_device::EXH, 2, 8, 8,L0\|L1}, /* ae: 0100 1000 1010 1110 / / 7807 */
202		{&upd7810_device::EXX, 2, 8, 8,L0\|L1}, /* af: 0100 1000 1010 1111 / / 7807 */
203		{&upd7810_device::DRLR_EA, 2, 8, 8,L0\|L1}, /* b0: 0100 1000 1011 0000 */
204		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b1: 0100 1000 1011 0001 */
205		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b2: 0100 1000 1011 0010 */
206		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b3: 0100 1000 1011 0011 */
207		{&upd7810_device::DRLL_EA, 2, 8, 8,L0\|L1}, /* b4: 0100 1000 1011 0100 */
208		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b5: 0100 1000 1011 0101 */
209		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b6: 0100 1000 1011 0110 */
210		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b7: 0100 1000 1011 0111 */
211		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b8: 0100 1000 1011 1000 */
212		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b9: 0100 1000 1011 1001 */
213		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ba: 0100 1000 1011 1010 */
214		{&upd7810_device::STOP, 2,12,12,L0\|L1}, /* bb: 0100 1000 1011 1011 */
215		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bc: 0100 1000 1011 1100 */
216		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bd: 0100 1000 1011 1101 */
217		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* be: 0100 1000 1011 1110 */
218		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bf: 0100 1000 1011 1111 */
219
220		{&upd7810_device::DMOV_EA_ECNT, 2,14,11,L0\|L1}, /* c0: 0100 1000 1100 0000 */
221		{&upd7810_device::DMOV_EA_ECPT, 2,14,11,L0\|L1}, /* c1: 0100 1000 1100 0001 */
222		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c2: 0100 1000 1100 0010 */
223		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c3: 0100 1000 1100 0011 */
224		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c4: 0100 1000 1100 0100 */
225		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c5: 0100 1000 1100 0101 */
226		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c6: 0100 1000 1100 0110 */
227		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c7: 0100 1000 1100 0111 */
228		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c8: 0100 1000 1100 1000 */
229		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c9: 0100 1000 1100 1001 */
230		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ca: 0100 1000 1100 1010 */
231		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* cb: 0100 1000 1100 1011 */
232		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* cc: 0100 1000 1100 1100 */
233		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* cd: 0100 1000 1100 1101 */
234		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ce: 0100 1000 1100 1110 */
235		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* cf: 0100 1000 1100 1111 */
236
237		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d0: 0100 1000 1101 0000 */
238		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d1: 0100 1000 1101 0001 */
239		{&upd7810_device::DMOV_ETM0_EA, 2,14,11,L0\|L1}, /* d2: 0100 1000 1101 0010 */
240		{&upd7810_device::DMOV_ETM1_EA, 2,14,11,L0\|L1}, /* d3: 0100 1000 1101 0011 */
241		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d4: 0100 1000 1101 0100 */
242		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d5: 0100 1000 1101 0101 */
243		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d6: 0100 1000 1101 0110 */
244		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d7: 0100 1000 1101 0111 */
245		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d8: 0100 1000 1101 1000 */
246		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d9: 0100 1000 1101 1001 */
247		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* da: 0100 1000 1101 1010 */
248		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* db: 0100 1000 1101 1011 */
249		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* dc: 0100 1000 1101 1100 */
250		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* dd: 0100 1000 1101 1101 */
251		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* de: 0100 1000 1101 1110 */
252		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* df: 0100 1000 1101 1111 */
253
254		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e0: 0100 1000 1110 0000 */
255		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e1: 0100 1000 1110 0001 */
256		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e2: 0100 1000 1110 0010 */
257		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e3: 0100 1000 1110 0011 */
258		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e4: 0100 1000 1110 0100 */
259		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e5: 0100 1000 1110 0101 */
260		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e6: 0100 1000 1110 0110 */
261		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e7: 0100 1000 1110 0111 */
262		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e8: 0100 1000 1110 1000 */
263		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e9: 0100 1000 1110 1001 */
264		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ea: 0100 1000 1110 1010 */
265		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* eb: 0100 1000 1110 1011 */
266		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ec: 0100 1000 1110 1100 */
267		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ed: 0100 1000 1110 1101 */
268		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ee: 0100 1000 1110 1110 */
269		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ef: 0100 1000 1110 1111 */
270
271		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f0: 0100 1000 1111 0000 */
272		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f1: 0100 1000 1111 0001 */
273		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f2: 0100 1000 1111 0010 */
274		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f3: 0100 1000 1111 0011 */
275		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f4: 0100 1000 1111 0100 */
276		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f5: 0100 1000 1111 0101 */
277		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f6: 0100 1000 1111 0110 */
278		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f7: 0100 1000 1111 0111 */
279		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f8: 0100 1000 1111 1000 */
280		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f9: 0100 1000 1111 1001 */
281		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* fa: 0100 1000 1111 1010 */
282		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* fb: 0100 1000 1111 1011 */
283		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* fc: 0100 1000 1111 1100 */
284		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* fd: 0100 1000 1111 1101 */
285		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* fe: 0100 1000 1111 1110 */
286		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1} /* ff: 0100 1000 1111 1111 */
287		};
288
289		/* prefix 4C */
290		const struct upd7810_device::opcode_s upd7810_device::s_op4C[256] =
291		{
292		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 00: 0100 1100 0000 0000 */
293		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 01: 0100 1100 0000 0001 */
294		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 02: 0100 1100 0000 0010 */
295		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 03: 0100 1100 0000 0011 */
296		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 04: 0100 1100 0000 0100 */
297		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 05: 0100 1100 0000 0101 */
298		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 06: 0100 1100 0000 0110 */
299		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 07: 0100 1100 0000 0111 */
300		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 08: 0100 1100 0000 1000 */
301		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 09: 0100 1100 0000 1001 */
302		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0a: 0100 1100 0000 1010 */
303		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0b: 0100 1100 0000 1011 */
304		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0c: 0100 1100 0000 1100 */
305		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0d: 0100 1100 0000 1101 */
306		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0e: 0100 1100 0000 1110 */
307		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0f: 0100 1100 0000 1111 */
308
309		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 10: 0100 1100 0001 0000 */
310		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 11: 0100 1100 0001 0001 */
311		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 12: 0100 1100 0001 0010 */
312		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 13: 0100 1100 0001 0011 */
313		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 14: 0100 1100 0001 0100 */
314		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 15: 0100 1100 0001 0101 */
315		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 16: 0100 1100 0001 0110 */
316		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 17: 0100 1100 0001 0111 */
317		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 18: 0100 1100 0001 1000 */
318		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 19: 0100 1100 0001 1001 */
319		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1a: 0100 1100 0001 1010 */
320		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1b: 0100 1100 0001 1011 */
321		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1c: 0100 1100 0001 1100 */
322		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1d: 0100 1100 0001 1101 */
323		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1e: 0100 1100 0001 1110 */
324		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1f: 0100 1100 0001 1111 */
325
326		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 20: 0100 1100 0010 0000 */
327		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 21: 0100 1100 0010 0001 */
328		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 22: 0100 1100 0010 0010 */
329		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 23: 0100 1100 0010 0011 */
330		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 24: 0100 1100 0010 0100 */
331		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 25: 0100 1100 0010 0101 */
332		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 26: 0100 1100 0010 0110 */
333		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 27: 0100 1100 0010 0111 */
334		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 28: 0100 1100 0010 1000 */
335		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 29: 0100 1100 0010 1001 */
336		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2a: 0100 1100 0010 1010 */
337		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2b: 0100 1100 0010 1011 */
338		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2c: 0100 1100 0010 1100 */
339		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2d: 0100 1100 0010 1101 */
340		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2e: 0100 1100 0010 1110 */
341		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2f: 0100 1100 0010 1111 */
342
343		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 30: 0100 1100 0011 0000 */
344		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 31: 0100 1100 0011 0001 */
345		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 32: 0100 1100 0011 0010 */
346		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 33: 0100 1100 0011 0011 */
347		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 34: 0100 1100 0011 0100 */
348		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 35: 0100 1100 0011 0101 */
349		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 36: 0100 1100 0011 0110 */
350		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 37: 0100 1100 0011 0111 */
351		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 38: 0100 1100 0011 1000 */
352		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 39: 0100 1100 0011 1001 */
353		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3a: 0100 1100 0011 1010 */
354		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3b: 0100 1100 0011 1011 */
355		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3c: 0100 1100 0011 1100 */
356		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3d: 0100 1100 0011 1101 */
357		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3e: 0100 1100 0011 1110 */
358		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3f: 0100 1100 0011 1111 */
359
360		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 40: 0100 1100 0100 0000 */
361		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 41: 0100 1100 0100 0001 */
362		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 42: 0100 1100 0100 0010 */
363		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 43: 0100 1100 0100 0011 */
364		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 44: 0100 1100 0100 0100 */
365		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 45: 0100 1100 0100 0101 */
366		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 46: 0100 1100 0100 0110 */
367		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 47: 0100 1100 0100 0111 */
368		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 48: 0100 1100 0100 1000 */
369		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 49: 0100 1100 0100 1001 */
370		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4a: 0100 1100 0100 1010 */
371		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4b: 0100 1100 0100 1011 */
372		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4c: 0100 1100 0100 1100 */
373		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4d: 0100 1100 0100 1101 */
374		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4e: 0100 1100 0100 1110 */
375		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4f: 0100 1100 0100 1111 */
376
377		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 50: 0100 1100 0101 0000 */
378		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 51: 0100 1100 0101 0001 */
379		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 52: 0100 1100 0101 0010 */
380		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 53: 0100 1100 0101 0011 */
381		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 54: 0100 1100 0101 0100 */
382		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 55: 0100 1100 0101 0101 */
383		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 56: 0100 1100 0101 0110 */
384		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 57: 0100 1100 0101 0111 */
385		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 58: 0100 1100 0101 1000 */
386		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 59: 0100 1100 0101 1001 */
387		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5a: 0100 1100 0101 1010 */
388		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5b: 0100 1100 0101 1011 */
389		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5c: 0100 1100 0101 1100 */
390		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5d: 0100 1100 0101 1101 */
391		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5e: 0100 1100 0101 1110 */
392		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5f: 0100 1100 0101 1111 */
393
394		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 60: 0100 1100 0110 0000 */
395		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 61: 0100 1100 0110 0001 */
396		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 62: 0100 1100 0110 0010 */
397		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 63: 0100 1100 0110 0011 */
398		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 64: 0100 1100 0110 0100 */
399		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 65: 0100 1100 0110 0101 */
400		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 66: 0100 1100 0110 0110 */
401		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 67: 0100 1100 0110 0111 */
402		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 68: 0100 1100 0110 1000 */
403		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 69: 0100 1100 0110 1001 */
404		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6a: 0100 1100 0110 1010 */
405		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6b: 0100 1100 0110 1011 */
406		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6c: 0100 1100 0110 1100 */
407		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6d: 0100 1100 0110 1101 */
408		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6e: 0100 1100 0110 1110 */
409		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6f: 0100 1100 0110 1111 */
410
411		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 70: 0100 1100 0111 0000 */
412		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 71: 0100 1100 0111 0001 */
413		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 72: 0100 1100 0111 0010 */
414		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 73: 0100 1100 0111 0011 */
415		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 74: 0100 1100 0111 0100 */
416		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 75: 0100 1100 0111 0101 */
417		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 76: 0100 1100 0111 0110 */
418		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 77: 0100 1100 0111 0111 */
419		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 78: 0100 1100 0111 1000 */
420		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 79: 0100 1100 0111 1001 */
421		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7a: 0100 1100 0111 1010 */
422		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7b: 0100 1100 0111 1011 */
423		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7c: 0100 1100 0111 1100 */
424		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7d: 0100 1100 0111 1101 */
425		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7e: 0100 1100 0111 1110 */
426		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7f: 0100 1100 0111 1111 */
427
428		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 80: 0100 1100 1000 0000 */
429		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 81: 0100 1100 1000 0001 */
430		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 82: 0100 1100 1000 0010 */
431		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 83: 0100 1100 1000 0011 */
432		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 84: 0100 1100 1000 0100 */
433		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 85: 0100 1100 1000 0101 */
434		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 86: 0100 1100 1000 0110 */
435		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 87: 0100 1100 1000 0111 */
436		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 88: 0100 1100 1000 1000 */
437		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 89: 0100 1100 1000 1001 */
438		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8a: 0100 1100 1000 1010 */
439		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8b: 0100 1100 1000 1011 */
440		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8c: 0100 1100 1000 1100 */
441		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8d: 0100 1100 1000 1101 */
442		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8e: 0100 1100 1000 1110 */
443		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8f: 0100 1100 1000 1111 */
444
445		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 90: 0100 1100 1001 0000 */
446		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 91: 0100 1100 1001 0001 */
447		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 92: 0100 1100 1001 0010 */
448		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 93: 0100 1100 1001 0011 */
449		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 94: 0100 1100 1001 0100 */
450		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 95: 0100 1100 1001 0101 */
451		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 96: 0100 1100 1001 0110 */
452		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 97: 0100 1100 1001 0111 */
453		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 98: 0100 1100 1001 1000 */
454		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 99: 0100 1100 1001 1001 */
455		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9a: 0100 1100 1001 1010 */
456		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9b: 0100 1100 1001 1011 */
457		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9c: 0100 1100 1001 1100 */
458		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9d: 0100 1100 1001 1101 */
459		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9e: 0100 1100 1001 1110 */
460		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9f: 0100 1100 1001 1111 */
461
462		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a0: 0100 1100 1010 0000 */
463		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a1: 0100 1100 1010 0001 */
464		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a2: 0100 1100 1010 0010 */
465		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a3: 0100 1100 1010 0011 */
466		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a4: 0100 1100 1010 0100 */
467		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a5: 0100 1100 1010 0101 */
468		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a6: 0100 1100 1010 0110 */
469		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a7: 0100 1100 1010 0111 */
470		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a8: 0100 1100 1010 1000 */
471		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a9: 0100 1100 1010 1001 */
472		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* aa: 0100 1100 1010 1010 */
473		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ab: 0100 1100 1010 1011 */
474		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ac: 0100 1100 1010 1100 */
475		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ad: 0100 1100 1010 1101 */
476		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ae: 0100 1100 1010 1110 */
477		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* af: 0100 1100 1010 1111 */
478
479		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b0: 0100 1100 1011 0000 */
480		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b1: 0100 1100 1011 0001 */
481		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b2: 0100 1100 1011 0010 */
482		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b3: 0100 1100 1011 0011 */
483		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b4: 0100 1100 1011 0100 */
484		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b5: 0100 1100 1011 0101 */
485		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b6: 0100 1100 1011 0110 */
486		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b7: 0100 1100 1011 0111 */
487		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b8: 0100 1100 1011 1000 */
488		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b9: 0100 1100 1011 1001 */
489		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ba: 0100 1100 1011 1010 */
490		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bb: 0100 1100 1011 1011 */
491		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bc: 0100 1100 1011 1100 */
492		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bd: 0100 1100 1011 1101 */
493		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* be: 0100 1100 1011 1110 */
494		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bf: 0100 1100 1011 1111 */
495
496		{&upd7810_device::MOV_A_PA, 2,10,10,L0\|L1}, /* c0: 0100 1100 1100 0000 */
497		{&upd7810_device::MOV_A_PB, 2,10,10,L0\|L1}, /* c1: 0100 1100 1100 0001 */
498		{&upd7810_device::MOV_A_PC, 2,10,10,L0\|L1}, /* c2: 0100 1100 1100 0010 */
499		{&upd7810_device::MOV_A_PD, 2,10,10,L0\|L1}, /* c3: 0100 1100 1100 0011 */
500		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* c4: 0100 1100 1100 0100 */
501		{&upd7810_device::MOV_A_PF, 2,10,10,L0\|L1}, /* c5: 0100 1100 1100 0101 */
502		{&upd7810_device::MOV_A_MKH, 2,10,10,L0\|L1}, /* c6: 0100 1100 1100 0110 */
503		{&upd7810_device::MOV_A_MKL, 2,10,10,L0\|L1}, /* c7: 0100 1100 1100 0111 */
504		{&upd7810_device::MOV_A_ANM, 2,10,10,L0\|L1}, /* c8: 0100 1100 1100 1000 */
505		{&upd7810_device::MOV_A_SMH, 2,10,10,L0\|L1}, /* c9: 0100 1100 1100 1001 */
506		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ca: 0100 1100 1100 1010 */
507		{&upd7810_device::MOV_A_EOM, 2,10,10,L0\|L1}, /* cb: 0100 1100 1100 1011 */
508		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* cc: 0100 1100 1100 1100 */
509		{&upd7810_device::MOV_A_TMM, 2,10,10,L0\|L1}, /* cd: 0100 1100 1100 1101 */
510		// {&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ce: 0100 1100 1100 1110 */
511		{&upd7810_device::MOV_A_PT, 2,10,10,L0\|L1}, /* ce: 0100 1100 1100 1110 / / 7807 */
512		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* cf: 0100 1100 1100 1111 */
513
514		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d0: 0100 1100 1101 0000 */
515		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d1: 0100 1100 1101 0001 */
516		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d2: 0100 1100 1101 0010 */
517		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d3: 0100 1100 1101 0011 */
518		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d4: 0100 1100 1101 0100 */
519		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d5: 0100 1100 1101 0101 */
520		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d6: 0100 1100 1101 0110 */
521		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d7: 0100 1100 1101 0111 */
522		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d8: 0100 1100 1101 1000 */
523		{&upd7810_device::MOV_A_RXB, 2,10,10,L0\|L1}, /* d9: 0100 1100 1101 1001 */
524		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* da: 0100 1100 1101 1010 */
525		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* db: 0100 1100 1101 1011 */
526		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* dc: 0100 1100 1101 1100 */
527		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* dd: 0100 1100 1101 1101 */
528		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* de: 0100 1100 1101 1110 */
529		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* df: 0100 1100 1101 1111 */
530
531		{&upd7810_device::MOV_A_CR0, 2,10,10,L0\|L1}, /* e0: 0100 1100 1110 0000 */
532		{&upd7810_device::MOV_A_CR1, 2,10,10,L0\|L1}, /* e1: 0100 1100 1110 0001 */
533		{&upd7810_device::MOV_A_CR2, 2,10,10,L0\|L1}, /* e2: 0100 1100 1110 0010 */
534		{&upd7810_device::MOV_A_CR3, 2,10,10,L0\|L1}, /* e3: 0100 1100 1110 0011 */
535		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e4: 0100 1100 1110 0100 */
536		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e5: 0100 1100 1110 0101 */
537		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e6: 0100 1100 1110 0110 */
538		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e7: 0100 1100 1110 0111 */
539		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e8: 0100 1100 1110 1000 */
540		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e9: 0100 1100 1110 1001 */
541		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ea: 0100 1100 1110 1010 */
542		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* eb: 0100 1100 1110 1011 */
543		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ec: 0100 1100 1110 1100 */
544		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ed: 0100 1100 1110 1101 */
545		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ee: 0100 1100 1110 1110 */
546		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ef: 0100 1100 1110 1111 */
547
548		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f0: 0100 1100 1111 0000 */
549		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f1: 0100 1100 1111 0001 */
550		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f2: 0100 1100 1111 0010 */
551		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f3: 0100 1100 1111 0011 */
552		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f4: 0100 1100 1111 0100 */
553		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f5: 0100 1100 1111 0101 */
554		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f6: 0100 1100 1111 0110 */
555		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f7: 0100 1100 1111 0111 */
556		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f8: 0100 1100 1111 1000 */
557		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f9: 0100 1100 1111 1001 */
558		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fa: 0100 1100 1111 1010 */
559		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fb: 0100 1100 1111 1011 */
560		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fc: 0100 1100 1111 1100 */
561		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fd: 0100 1100 1111 1101 */
562		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fe: 0100 1100 1111 1110 */
563		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ff: 0100 1100 1111 1111 */
564		};
565
566		/* prefix 4D */
567		const struct upd7810_device::opcode_s upd7810_device::s_op4D[256] =
568		{
569		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 00: 0100 1101 0000 0000 */
570		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 01: 0100 1101 0000 0001 */
571		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 02: 0100 1101 0000 0010 */
572		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 03: 0100 1101 0000 0011 */
573		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 04: 0100 1101 0000 0100 */
574		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 05: 0100 1101 0000 0101 */
575		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 06: 0100 1101 0000 0110 */
576		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 07: 0100 1101 0000 0111 */
577		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 08: 0100 1101 0000 1000 */
578		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 09: 0100 1101 0000 1001 */
579		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0a: 0100 1101 0000 1010 */
580		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0b: 0100 1101 0000 1011 */
581		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0c: 0100 1101 0000 1100 */
582		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0d: 0100 1101 0000 1101 */
583		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0e: 0100 1101 0000 1110 */
584		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0f: 0100 1101 0000 1111 */
585
586		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 10: 0100 1101 0001 0000 */
587		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 11: 0100 1101 0001 0001 */
588		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 12: 0100 1101 0001 0010 */
589		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 13: 0100 1101 0001 0011 */
590		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 14: 0100 1101 0001 0100 */
591		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 15: 0100 1101 0001 0101 */
592		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 16: 0100 1101 0001 0110 */
593		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 17: 0100 1101 0001 0111 */
594		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 18: 0100 1101 0001 1000 */
595		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 19: 0100 1101 0001 1001 */
596		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1a: 0100 1101 0001 1010 */
597		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1b: 0100 1101 0001 1011 */
598		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1c: 0100 1101 0001 1100 */
599		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1d: 0100 1101 0001 1101 */
600		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1e: 0100 1101 0001 1110 */
601		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1f: 0100 1101 0001 1111 */
602
603		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 20: 0100 1101 0010 0000 */
604		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 21: 0100 1101 0010 0001 */
605		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 22: 0100 1101 0010 0010 */
606		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 23: 0100 1101 0010 0011 */
607		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 24: 0100 1101 0010 0100 */
608		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 25: 0100 1101 0010 0101 */
609		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 26: 0100 1101 0010 0110 */
610		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 27: 0100 1101 0010 0111 */
611		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 28: 0100 1101 0010 1000 */
612		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 29: 0100 1101 0010 1001 */
613		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2a: 0100 1101 0010 1010 */
614		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2b: 0100 1101 0010 1011 */
615		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2c: 0100 1101 0010 1100 */
616		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2d: 0100 1101 0010 1101 */
617		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2e: 0100 1101 0010 1110 */
618		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2f: 0100 1101 0010 1111 */
619
620		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 30: 0100 1101 0011 0000 */
621		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 31: 0100 1101 0011 0001 */
622		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 32: 0100 1101 0011 0010 */
623		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 33: 0100 1101 0011 0011 */
624		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 34: 0100 1101 0011 0100 */
625		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 35: 0100 1101 0011 0101 */
626		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 36: 0100 1101 0011 0110 */
627		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 37: 0100 1101 0011 0111 */
628		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 38: 0100 1101 0011 1000 */
629		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 39: 0100 1101 0011 1001 */
630		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3a: 0100 1101 0011 1010 */
631		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3b: 0100 1101 0011 1011 */
632		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3c: 0100 1101 0011 1100 */
633		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3d: 0100 1101 0011 1101 */
634		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3e: 0100 1101 0011 1110 */
635		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3f: 0100 1101 0011 1111 */
636
637		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 40: 0100 1101 0100 0000 */
638		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 41: 0100 1101 0100 0001 */
639		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 42: 0100 1101 0100 0010 */
640		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 43: 0100 1101 0100 0011 */
641		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 44: 0100 1101 0100 0100 */
642		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 45: 0100 1101 0100 0101 */
643		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 46: 0100 1101 0100 0110 */
644		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 47: 0100 1101 0100 0111 */
645		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 48: 0100 1101 0100 1000 */
646		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 49: 0100 1101 0100 1001 */
647		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4a: 0100 1101 0100 1010 */
648		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4b: 0100 1101 0100 1011 */
649		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4c: 0100 1101 0100 1100 */
650		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4d: 0100 1101 0100 1101 */
651		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4e: 0100 1101 0100 1110 */
652		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4f: 0100 1101 0100 1111 */
653
654		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 50: 0100 1101 0101 0000 */
655		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 51: 0100 1101 0101 0001 */
656		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 52: 0100 1101 0101 0010 */
657		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 53: 0100 1101 0101 0011 */
658		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 54: 0100 1101 0101 0100 */
659		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 55: 0100 1101 0101 0101 */
660		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 56: 0100 1101 0101 0110 */
661		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 57: 0100 1101 0101 0111 */
662		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 58: 0100 1101 0101 1000 */
663		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 59: 0100 1101 0101 1001 */
664		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5a: 0100 1101 0101 1010 */
665		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5b: 0100 1101 0101 1011 */
666		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5c: 0100 1101 0101 1100 */
667		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5d: 0100 1101 0101 1101 */
668		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5e: 0100 1101 0101 1110 */
669		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5f: 0100 1101 0101 1111 */
670
671		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 60: 0100 1101 0110 0000 */
672		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 61: 0100 1101 0110 0001 */
673		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 62: 0100 1101 0110 0010 */
674		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 63: 0100 1101 0110 0011 */
675		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 64: 0100 1101 0110 0100 */
676		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 65: 0100 1101 0110 0101 */
677		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 66: 0100 1101 0110 0110 */
678		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 67: 0100 1101 0110 0111 */
679		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 68: 0100 1101 0110 1000 */
680		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 69: 0100 1101 0110 1001 */
681		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6a: 0100 1101 0110 1010 */
682		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6b: 0100 1101 0110 1011 */
683		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6c: 0100 1101 0110 1100 */
684		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6d: 0100 1101 0110 1101 */
685		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6e: 0100 1101 0110 1110 */
686		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6f: 0100 1101 0110 1111 */
687
688		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 70: 0100 1101 0111 0000 */
689		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 71: 0100 1101 0111 0001 */
690		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 72: 0100 1101 0111 0010 */
691		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 73: 0100 1101 0111 0011 */
692		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 74: 0100 1101 0111 0100 */
693		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 75: 0100 1101 0111 0101 */
694		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 76: 0100 1101 0111 0110 */
695		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 77: 0100 1101 0111 0111 */
696		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 78: 0100 1101 0111 1000 */
697		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 79: 0100 1101 0111 1001 */
698		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7a: 0100 1101 0111 1010 */
699		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7b: 0100 1101 0111 1011 */
700		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7c: 0100 1101 0111 1100 */
701		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7d: 0100 1101 0111 1101 */
702		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7e: 0100 1101 0111 1110 */
703		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7f: 0100 1101 0111 1111 */
704
705		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 80: 0100 1101 1000 0000 */
706		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 81: 0100 1101 1000 0001 */
707		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 82: 0100 1101 1000 0010 */
708		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 83: 0100 1101 1000 0011 */
709		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 84: 0100 1101 1000 0100 */
710		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 85: 0100 1101 1000 0101 */
711		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 86: 0100 1101 1000 0110 */
712		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 87: 0100 1101 1000 0111 */
713		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 88: 0100 1101 1000 1000 */
714		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 89: 0100 1101 1000 1001 */
715		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8a: 0100 1101 1000 1010 */
716		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8b: 0100 1101 1000 1011 */
717		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8c: 0100 1101 1000 1100 */
718		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8d: 0100 1101 1000 1101 */
719		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8e: 0100 1101 1000 1110 */
720		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8f: 0100 1101 1000 1111 */
721
722		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 90: 0100 1101 1001 0000 */
723		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 91: 0100 1101 1001 0001 */
724		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 92: 0100 1101 1001 0010 */
725		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 93: 0100 1101 1001 0011 */
726		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 94: 0100 1101 1001 0100 */
727		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 95: 0100 1101 1001 0101 */
728		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 96: 0100 1101 1001 0110 */
729		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 97: 0100 1101 1001 0111 */
730		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 98: 0100 1101 1001 1000 */
731		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 99: 0100 1101 1001 1001 */
732		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9a: 0100 1101 1001 1010 */
733		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9b: 0100 1101 1001 1011 */
734		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9c: 0100 1101 1001 1100 */
735		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9d: 0100 1101 1001 1101 */
736		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9e: 0100 1101 1001 1110 */
737		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9f: 0100 1101 1001 1111 */
738
739		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a0: 0100 1101 1010 0000 */
740		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a1: 0100 1101 1010 0001 */
741		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a2: 0100 1101 1010 0010 */
742		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a3: 0100 1101 1010 0011 */
743		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a4: 0100 1101 1010 0100 */
744		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a5: 0100 1101 1010 0101 */
745		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a6: 0100 1101 1010 0110 */
746		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a7: 0100 1101 1010 0111 */
747		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a8: 0100 1101 1010 1000 */
748		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a9: 0100 1101 1010 1001 */
749		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* aa: 0100 1101 1010 1010 */
750		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ab: 0100 1101 1010 1011 */
751		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ac: 0100 1101 1010 1100 */
752		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ad: 0100 1101 1010 1101 */
753		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ae: 0100 1101 1010 1110 */
754		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* af: 0100 1101 1010 1111 */
755
756		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b0: 0100 1101 1011 0000 */
757		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b1: 0100 1101 1011 0001 */
758		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b2: 0100 1101 1011 0010 */
759		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b3: 0100 1101 1011 0011 */
760		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b4: 0100 1101 1011 0100 */
761		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b5: 0100 1101 1011 0101 */
762		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b6: 0100 1101 1011 0110 */
763		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b7: 0100 1101 1011 0111 */
764		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b8: 0100 1101 1011 1000 */
765		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b9: 0100 1101 1011 1001 */
766		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ba: 0100 1101 1011 1010 */
767		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bb: 0100 1101 1011 1011 */
768		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bc: 0100 1101 1011 1100 */
769		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bd: 0100 1101 1011 1101 */
770		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* be: 0100 1101 1011 1110 */
771		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bf: 0100 1101 1011 1111 */
772
773		{&upd7810_device::MOV_PA_A, 2,10,10,L0\|L1}, /* c0: 0100 1101 1100 0000 */
774		{&upd7810_device::MOV_PB_A, 2,10,10,L0\|L1}, /* c1: 0100 1101 1100 0001 */
775		{&upd7810_device::MOV_PC_A, 2,10,10,L0\|L1}, /* c2: 0100 1101 1100 0010 */
776		{&upd7810_device::MOV_PD_A, 2,10,10,L0\|L1}, /* c3: 0100 1101 1100 0011 */
777		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* c4: 0100 1101 1100 0100 */
778		{&upd7810_device::MOV_PF_A, 2,10,10,L0\|L1}, /* c5: 0100 1101 1100 0101 */
779		{&upd7810_device::MOV_MKH_A, 2,10,10,L0\|L1}, /* c6: 0100 1101 1100 0110 */
780		{&upd7810_device::MOV_MKL_A, 2,10,10,L0\|L1}, /* c7: 0100 1101 1100 0111 */
781		{&upd7810_device::MOV_ANM_A, 2,10,10,L0\|L1}, /* c8: 0100 1101 1100 1000 */
782		{&upd7810_device::MOV_SMH_A, 2,10,10,L0\|L1}, /* c9: 0100 1101 1100 1001 */
783		{&upd7810_device::MOV_SML_A, 2,10,10,L0\|L1}, /* ca: 0100 1101 1100 1010 */
784		{&upd7810_device::MOV_EOM_A, 2,10,10,L0\|L1}, /* cb: 0100 1101 1100 1011 */
785		{&upd7810_device::MOV_ETMM_A, 2,10,10,L0\|L1}, /* cc: 0100 1101 1100 1100 */
786		{&upd7810_device::MOV_TMM_A, 2,10,10,L0\|L1}, /* cd: 0100 1101 1100 1101 */
787		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ce: 0100 1101 1100 1110 */
788		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* cf: 0100 1101 1100 1111 */
789
790		{&upd7810_device::MOV_MM_A, 2,10,10,L0\|L1}, /* d0: 0100 1101 1101 0000 */
791		{&upd7810_device::MOV_MCC_A, 2,10,10,L0\|L1}, /* d1: 0100 1101 1101 0001 */
792		{&upd7810_device::MOV_MA_A, 2,10,10,L0\|L1}, /* d2: 0100 1101 1101 0010 */
793		{&upd7810_device::MOV_MB_A, 2,10,10,L0\|L1}, /* d3: 0100 1101 1101 0011 */
794		{&upd7810_device::MOV_MC_A, 2,10,10,L0\|L1}, /* d4: 0100 1101 1101 0100 */
795		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d5: 0100 1101 1101 0101 */
796		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d6: 0100 1101 1101 0110 */
797		{&upd7810_device::MOV_MF_A, 2,10,10,L0\|L1}, /* d7: 0100 1101 1101 0111 */
798		{&upd7810_device::MOV_TXB_A, 2,10,10,L0\|L1}, /* d8: 0100 1101 1101 1000 */
799		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d9: 0100 1101 1101 1001 */
800		{&upd7810_device::MOV_TM0_A, 2,10,10,L0\|L1}, /* da: 0100 1101 1101 1010 */
801		{&upd7810_device::MOV_TM1_A, 2,10,10,L0\|L1}, /* db: 0100 1101 1101 1011 */
802		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* dc: 0100 1101 1101 1100 */
803		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* dd: 0100 1101 1101 1101 */
804		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* de: 0100 1101 1101 1110 */
805		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* df: 0100 1101 1101 1111 */
806
807		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e0: 0100 1101 1110 0000 */
808		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e1: 0100 1101 1110 0001 */
809		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e2: 0100 1101 1110 0010 */
810		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e3: 0100 1101 1110 0011 */
811		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e4: 0100 1101 1110 0100 */
812		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e5: 0100 1101 1110 0101 */
813		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e6: 0100 1101 1110 0110 */
814		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e7: 0100 1101 1110 0111 */
815		{&upd7810_device::MOV_ZCM_A, 2,10,10,L0\|L1}, /* e8: 0100 1101 1110 1000 */
816		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e9: 0100 1101 1110 1001 */
817		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ea: 0100 1101 1110 1010 */
818		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* eb: 0100 1101 1110 1011 */
819		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ec: 0100 1101 1110 1100 */
820		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ed: 0100 1101 1110 1101 */
821		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ee: 0100 1101 1110 1110 */
822		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ef: 0100 1101 1110 1111 */
823
824		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f0: 0100 1101 1111 0000 */
825		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f1: 0100 1101 1111 0001 */
826		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f2: 0100 1101 1111 0010 */
827		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f3: 0100 1101 1111 0011 */
828		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f4: 0100 1101 1111 0100 */
829		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f5: 0100 1101 1111 0101 */
830		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f6: 0100 1101 1111 0110 */
831		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f7: 0100 1101 1111 0111 */
832		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f8: 0100 1101 1111 1000 */
833		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f9: 0100 1101 1111 1001 */
834		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fa: 0100 1101 1111 1010 */
835		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fb: 0100 1101 1111 1011 */
836		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fc: 0100 1101 1111 1100 */
837		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fd: 0100 1101 1111 1101 */
838		{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fe: 0100 1101 1111 1110 */
839		{&upd7810_device::illegal2, 2,10,10,L0\|L1} /* ff: 0100 1101 1111 1111 */
840		};
841
842		/* prefix 60 */
843		const struct upd7810_device::opcode_s upd7810_device::s_op60[256] =
844		{
845		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 00: 0110 0000 0000 0000 */
846		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 01: 0110 0000 0000 0001 */
847		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 02: 0110 0000 0000 0010 */
848		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 03: 0110 0000 0000 0011 */
849		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 04: 0110 0000 0000 0100 */
850		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 05: 0110 0000 0000 0101 */
851		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 06: 0110 0000 0000 0110 */
852		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 07: 0110 0000 0000 0111 */
853		{&upd7810_device::ANA_V_A, 2, 8, 8,L0\|L1}, /* 08: 0110 0000 0000 1000 */
854		{&upd7810_device::ANA_A_A, 2, 8, 8,L0\|L1}, /* 09: 0110 0000 0000 1001 */
855		{&upd7810_device::ANA_B_A, 2, 8, 8,L0\|L1}, /* 0a: 0110 0000 0000 1010 */
856		{&upd7810_device::ANA_C_A, 2, 8, 8,L0\|L1}, /* 0b: 0110 0000 0000 1011 */
857		{&upd7810_device::ANA_D_A, 2, 8, 8,L0\|L1}, /* 0c: 0110 0000 0000 1100 */
858		{&upd7810_device::ANA_E_A, 2, 8, 8,L0\|L1}, /* 0d: 0110 0000 0000 1101 */
859		{&upd7810_device::ANA_H_A, 2, 8, 8,L0\|L1}, /* 0e: 0110 0000 0000 1110 */
860		{&upd7810_device::ANA_L_A, 2, 8, 8,L0\|L1}, /* 0f: 0110 0000 0000 1111 */
861
862		{&upd7810_device::XRA_V_A, 2, 8, 8,L0\|L1}, /* 10: 0110 0000 0001 0000 */
863		{&upd7810_device::XRA_A_A, 2, 8, 8,L0\|L1}, /* 11: 0110 0000 0001 0001 */
864		{&upd7810_device::XRA_B_A, 2, 8, 8,L0\|L1}, /* 12: 0110 0000 0001 0010 */
865		{&upd7810_device::XRA_C_A, 2, 8, 8,L0\|L1}, /* 13: 0110 0000 0001 0011 */
866		{&upd7810_device::XRA_D_A, 2, 8, 8,L0\|L1}, /* 14: 0110 0000 0001 0100 */
867		{&upd7810_device::XRA_E_A, 2, 8, 8,L0\|L1}, /* 15: 0110 0000 0001 0101 */
868		{&upd7810_device::XRA_H_A, 2, 8, 8,L0\|L1}, /* 16: 0110 0000 0001 0110 */
869		{&upd7810_device::XRA_L_A, 2, 8, 8,L0\|L1}, /* 17: 0110 0000 0001 0111 */
870		{&upd7810_device::ORA_V_A, 2, 8, 8,L0\|L1}, /* 18: 0110 0000 0001 1000 */
871		{&upd7810_device::ORA_A_A, 2, 8, 8,L0\|L1}, /* 19: 0110 0000 0001 1001 */
872		{&upd7810_device::ORA_B_A, 2, 8, 8,L0\|L1}, /* 1a: 0110 0000 0001 1010 */
873		{&upd7810_device::ORA_C_A, 2, 8, 8,L0\|L1}, /* 1b: 0110 0000 0001 1011 */
874		{&upd7810_device::ORA_D_A, 2, 8, 8,L0\|L1}, /* 1c: 0110 0000 0001 1100 */
875		{&upd7810_device::ORA_E_A, 2, 8, 8,L0\|L1}, /* 1d: 0110 0000 0001 1101 */
876		{&upd7810_device::ORA_H_A, 2, 8, 8,L0\|L1}, /* 1e: 0110 0000 0001 1110 */
877		{&upd7810_device::ORA_L_A, 2, 8, 8,L0\|L1}, /* 1f: 0110 0000 0001 1111 */
878
879		{&upd7810_device::ADDNC_V_A, 2, 8, 8,L0\|L1}, /* 20: 0110 0000 0010 0000 */
880		{&upd7810_device::ADDNC_A_A, 2, 8, 8,L0\|L1}, /* 21: 0110 0000 0010 0001 */
881		{&upd7810_device::ADDNC_B_A, 2, 8, 8,L0\|L1}, /* 22: 0110 0000 0010 0010 */
882		{&upd7810_device::ADDNC_C_A, 2, 8, 8,L0\|L1}, /* 23: 0110 0000 0010 0011 */
883		{&upd7810_device::ADDNC_D_A, 2, 8, 8,L0\|L1}, /* 24: 0110 0000 0010 0100 */
884		{&upd7810_device::ADDNC_E_A, 2, 8, 8,L0\|L1}, /* 25: 0110 0000 0010 0101 */
885		{&upd7810_device::ADDNC_H_A, 2, 8, 8,L0\|L1}, /* 26: 0110 0000 0010 0110 */
886		{&upd7810_device::ADDNC_L_A, 2, 8, 8,L0\|L1}, /* 27: 0110 0000 0010 0111 */
887		{&upd7810_device::GTA_V_A, 2, 8, 8,L0\|L1}, /* 28: 0110 0000 0010 1000 */
888		{&upd7810_device::GTA_A_A, 2, 8, 8,L0\|L1}, /* 29: 0110 0000 0010 1001 */
889		{&upd7810_device::GTA_B_A, 2, 8, 8,L0\|L1}, /* 2a: 0110 0000 0010 1010 */
890		{&upd7810_device::GTA_C_A, 2, 8, 8,L0\|L1}, /* 2b: 0110 0000 0010 1011 */
891		{&upd7810_device::GTA_D_A, 2, 8, 8,L0\|L1}, /* 2c: 0110 0000 0010 1100 */
892		{&upd7810_device::GTA_E_A, 2, 8, 8,L0\|L1}, /* 2d: 0110 0000 0010 1101 */
893		{&upd7810_device::GTA_H_A, 2, 8, 8,L0\|L1}, /* 2e: 0110 0000 0010 1110 */
894		{&upd7810_device::GTA_L_A, 2, 8, 8,L0\|L1}, /* 2f: 0110 0000 0010 1111 */
895
896		{&upd7810_device::SUBNB_V_A, 2, 8, 8,L0\|L1}, /* 30: 0110 0000 0011 0000 */
897		{&upd7810_device::SUBNB_A_A, 2, 8, 8,L0\|L1}, /* 31: 0110 0000 0011 0001 */
898		{&upd7810_device::SUBNB_B_A, 2, 8, 8,L0\|L1}, /* 32: 0110 0000 0011 0010 */
899		{&upd7810_device::SUBNB_C_A, 2, 8, 8,L0\|L1}, /* 33: 0110 0000 0011 0011 */
900		{&upd7810_device::SUBNB_D_A, 2, 8, 8,L0\|L1}, /* 34: 0110 0000 0011 0100 */
901		{&upd7810_device::SUBNB_E_A, 2, 8, 8,L0\|L1}, /* 35: 0110 0000 0011 0101 */
902		{&upd7810_device::SUBNB_H_A, 2, 8, 8,L0\|L1}, /* 36: 0110 0000 0011 0110 */
903		{&upd7810_device::SUBNB_L_A, 2, 8, 8,L0\|L1}, /* 37: 0110 0000 0011 0111 */
904		{&upd7810_device::LTA_V_A, 2, 8, 8,L0\|L1}, /* 38: 0110 0000 0011 1000 */
905		{&upd7810_device::LTA_A_A, 2, 8, 8,L0\|L1}, /* 39: 0110 0000 0011 1001 */
906		{&upd7810_device::LTA_B_A, 2, 8, 8,L0\|L1}, /* 3a: 0110 0000 0011 1010 */
907		{&upd7810_device::LTA_C_A, 2, 8, 8,L0\|L1}, /* 3b: 0110 0000 0011 1011 */
908		{&upd7810_device::LTA_D_A, 2, 8, 8,L0\|L1}, /* 3c: 0110 0000 0011 1100 */
909		{&upd7810_device::LTA_E_A, 2, 8, 8,L0\|L1}, /* 3d: 0110 0000 0011 1101 */
910		{&upd7810_device::LTA_H_A, 2, 8, 8,L0\|L1}, /* 3e: 0110 0000 0011 1110 */
911		{&upd7810_device::LTA_L_A, 2, 8, 8,L0\|L1}, /* 3f: 0110 0000 0011 1111 */
912
913		{&upd7810_device::ADD_V_A, 2, 8, 8,L0\|L1}, /* 40: 0110 0000 0100 0000 */
914		{&upd7810_device::ADD_A_A, 2, 8, 8,L0\|L1}, /* 41: 0110 0000 0100 0001 */
915		{&upd7810_device::ADD_B_A, 2, 8, 8,L0\|L1}, /* 42: 0110 0000 0100 0010 */
916		{&upd7810_device::ADD_C_A, 2, 8, 8,L0\|L1}, /* 43: 0110 0000 0100 0011 */
917		{&upd7810_device::ADD_D_A, 2, 8, 8,L0\|L1}, /* 44: 0110 0000 0100 0100 */
918		{&upd7810_device::ADD_E_A, 2, 8, 8,L0\|L1}, /* 45: 0110 0000 0100 0101 */
919		{&upd7810_device::ADD_H_A, 2, 8, 8,L0\|L1}, /* 46: 0110 0000 0100 0110 */
920		{&upd7810_device::ADD_L_A, 2, 8, 8,L0\|L1}, /* 47: 0110 0000 0100 0111 */
921		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 48: 0110 0000 0100 1000 */
922		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 49: 0110 0000 0100 1001 */
923		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4a: 0110 0000 0100 1010 */
924		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4b: 0110 0000 0100 1011 */
925		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4c: 0110 0000 0100 1100 */
926		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4d: 0110 0000 0100 1101 */
927		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4e: 0110 0000 0100 1110 */
928		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4f: 0110 0000 0100 1111 */
929
930		{&upd7810_device::ADC_V_A, 2, 8, 8,L0\|L1}, /* 50: 0110 0000 0101 0000 */
931		{&upd7810_device::ADC_A_A, 2, 8, 8,L0\|L1}, /* 51: 0110 0000 0101 0001 */
932		{&upd7810_device::ADC_B_A, 2, 8, 8,L0\|L1}, /* 52: 0110 0000 0101 0010 */
933		{&upd7810_device::ADC_C_A, 2, 8, 8,L0\|L1}, /* 53: 0110 0000 0101 0011 */
934		{&upd7810_device::ADC_D_A, 2, 8, 8,L0\|L1}, /* 54: 0110 0000 0101 0100 */
935		{&upd7810_device::ADC_E_A, 2, 8, 8,L0\|L1}, /* 55: 0110 0000 0101 0101 */
936		{&upd7810_device::ADC_H_A, 2, 8, 8,L0\|L1}, /* 56: 0110 0000 0101 0110 */
937		{&upd7810_device::ADC_L_A, 2, 8, 8,L0\|L1}, /* 57: 0110 0000 0101 0111 */
938		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 58: 0110 0000 0101 1000 */
939		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 59: 0110 0000 0101 1001 */
940		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5a: 0110 0000 0101 1010 */
941		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5b: 0110 0000 0101 1011 */
942		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5c: 0110 0000 0101 1100 */
943		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5d: 0110 0000 0101 1101 */
944		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5e: 0110 0000 0101 1110 */
945		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5f: 0110 0000 0101 1111 */
946
947		{&upd7810_device::SUB_V_A, 2, 8, 8,L0\|L1}, /* 60: 0110 0000 0110 0000 */
948		{&upd7810_device::SUB_A_A, 2, 8, 8,L0\|L1}, /* 61: 0110 0000 0110 0001 */
949		{&upd7810_device::SUB_B_A, 2, 8, 8,L0\|L1}, /* 62: 0110 0000 0110 0010 */
950		{&upd7810_device::SUB_C_A, 2, 8, 8,L0\|L1}, /* 63: 0110 0000 0110 0011 */
951		{&upd7810_device::SUB_D_A, 2, 8, 8,L0\|L1}, /* 64: 0110 0000 0110 0100 */
952		{&upd7810_device::SUB_E_A, 2, 8, 8,L0\|L1}, /* 65: 0110 0000 0110 0101 */
953		{&upd7810_device::SUB_H_A, 2, 8, 8,L0\|L1}, /* 66: 0110 0000 0110 0110 */
954		{&upd7810_device::SUB_L_A, 2, 8, 8,L0\|L1}, /* 67: 0110 0000 0110 0111 */
955		{&upd7810_device::NEA_V_A, 2, 8, 8,L0\|L1}, /* 68: 0110 0000 0110 1000 */
956		{&upd7810_device::NEA_A_A, 2, 8, 8,L0\|L1}, /* 69: 0110 0000 0110 1001 */
957		{&upd7810_device::NEA_B_A, 2, 8, 8,L0\|L1}, /* 6a: 0110 0000 0110 1010 */
958		{&upd7810_device::NEA_C_A, 2, 8, 8,L0\|L1}, /* 6b: 0110 0000 0110 1011 */
959		{&upd7810_device::NEA_D_A, 2, 8, 8,L0\|L1}, /* 6c: 0110 0000 0110 1100 */
960		{&upd7810_device::NEA_E_A, 2, 8, 8,L0\|L1}, /* 6d: 0110 0000 0110 1101 */
961		{&upd7810_device::NEA_H_A, 2, 8, 8,L0\|L1}, /* 6e: 0110 0000 0110 1110 */
962		{&upd7810_device::NEA_L_A, 2, 8, 8,L0\|L1}, /* 6f: 0110 0000 0110 1111 */
963
964		{&upd7810_device::SBB_V_A, 2, 8, 8,L0\|L1}, /* 70: 0110 0000 0111 0000 */
965		{&upd7810_device::SBB_A_A, 2, 8, 8,L0\|L1}, /* 71: 0110 0000 0111 0001 */
966		{&upd7810_device::SBB_B_A, 2, 8, 8,L0\|L1}, /* 72: 0110 0000 0111 0010 */
967		{&upd7810_device::SBB_C_A, 2, 8, 8,L0\|L1}, /* 73: 0110 0000 0111 0011 */
968		{&upd7810_device::SBB_D_A, 2, 8, 8,L0\|L1}, /* 74: 0110 0000 0111 0100 */
969		{&upd7810_device::SBB_E_A, 2, 8, 8,L0\|L1}, /* 75: 0110 0000 0111 0101 */
970		{&upd7810_device::SBB_H_A, 2, 8, 8,L0\|L1}, /* 76: 0110 0000 0111 0110 */
971		{&upd7810_device::SBB_L_A, 2, 8, 8,L0\|L1}, /* 77: 0110 0000 0111 0111 */
972		{&upd7810_device::EQA_V_A, 2, 8, 8,L0\|L1}, /* 78: 0110 0000 0111 1000 */
973		{&upd7810_device::EQA_A_A, 2, 8, 8,L0\|L1}, /* 79: 0110 0000 0111 1001 */
974		{&upd7810_device::EQA_B_A, 2, 8, 8,L0\|L1}, /* 7a: 0110 0000 0111 1010 */
975		{&upd7810_device::EQA_C_A, 2, 8, 8,L0\|L1}, /* 7b: 0110 0000 0111 1011 */
976		{&upd7810_device::EQA_D_A, 2, 8, 8,L0\|L1}, /* 7c: 0110 0000 0111 1100 */
977		{&upd7810_device::EQA_E_A, 2, 8, 8,L0\|L1}, /* 7d: 0110 0000 0111 1101 */
978		{&upd7810_device::EQA_H_A, 2, 8, 8,L0\|L1}, /* 7e: 0110 0000 0111 1110 */
979		{&upd7810_device::EQA_L_A, 2, 8, 8,L0\|L1}, /* 7f: 0110 0000 0111 1111 */
980
981		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 80: 0110 0000 1000 0000 */
982		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 81: 0110 0000 1000 0001 */
983		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 82: 0110 0000 1000 0010 */
984		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 83: 0110 0000 1000 0011 */
985		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 84: 0110 0000 1000 0100 */
986		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 85: 0110 0000 1000 0101 */
987		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 86: 0110 0000 1000 0110 */
988		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 87: 0110 0000 1000 0111 */
989		{&upd7810_device::ANA_A_V, 2, 8, 8,L0\|L1}, /* 88: 0110 0000 1000 1000 */
990		{&upd7810_device::ANA_A_A, 2, 8, 8,L0\|L1}, /* 89: 0110 0000 1000 1001 */
991		{&upd7810_device::ANA_A_B, 2, 8, 8,L0\|L1}, /* 8a: 0110 0000 1000 1010 */
992		{&upd7810_device::ANA_A_C, 2, 8, 8,L0\|L1}, /* 8b: 0110 0000 1000 1011 */
993		{&upd7810_device::ANA_A_D, 2, 8, 8,L0\|L1}, /* 8c: 0110 0000 1000 1100 */
994		{&upd7810_device::ANA_A_E, 2, 8, 8,L0\|L1}, /* 8d: 0110 0000 1000 1101 */
995		{&upd7810_device::ANA_A_H, 2, 8, 8,L0\|L1}, /* 8e: 0110 0000 1000 1110 */
996		{&upd7810_device::ANA_A_L, 2, 8, 8,L0\|L1}, /* 8f: 0110 0000 1000 1111 */
997
998		{&upd7810_device::XRA_A_V, 2, 8, 8,L0\|L1}, /* 90: 0110 0000 1001 0000 */
999		{&upd7810_device::XRA_A_A, 2, 8, 8,L0\|L1}, /* 91: 0110 0000 1001 0001 */
1000		{&upd7810_device::XRA_A_B, 2, 8, 8,L0\|L1}, /* 92: 0110 0000 1001 0010 */
1001		{&upd7810_device::XRA_A_C, 2, 8, 8,L0\|L1}, /* 93: 0110 0000 1001 0011 */
1002		{&upd7810_device::XRA_A_D, 2, 8, 8,L0\|L1}, /* 94: 0110 0000 1001 0100 */
1003		{&upd7810_device::XRA_A_E, 2, 8, 8,L0\|L1}, /* 95: 0110 0000 1001 0101 */
1004		{&upd7810_device::XRA_A_H, 2, 8, 8,L0\|L1}, /* 96: 0110 0000 1001 0110 */
1005		{&upd7810_device::XRA_A_L, 2, 8, 8,L0\|L1}, /* 97: 0110 0000 1001 0111 */
1006		{&upd7810_device::ORA_A_V, 2, 8, 8,L0\|L1}, /* 98: 0110 0000 1001 1000 */
1007		{&upd7810_device::ORA_A_A, 2, 8, 8,L0\|L1}, /* 99: 0110 0000 1001 1001 */
1008		{&upd7810_device::ORA_A_B, 2, 8, 8,L0\|L1}, /* 9a: 0110 0000 1001 1010 */
1009		{&upd7810_device::ORA_A_C, 2, 8, 8,L0\|L1}, /* 9b: 0110 0000 1001 1011 */
1010		{&upd7810_device::ORA_A_D, 2, 8, 8,L0\|L1}, /* 9c: 0110 0000 1001 1100 */
1011		{&upd7810_device::ORA_A_E, 2, 8, 8,L0\|L1}, /* 9d: 0110 0000 1001 1101 */
1012		{&upd7810_device::ORA_A_H, 2, 8, 8,L0\|L1}, /* 9e: 0110 0000 1001 1110 */
1013		{&upd7810_device::ORA_A_L, 2, 8, 8,L0\|L1}, /* 9f: 0110 0000 1001 1111 */
1014
1015		{&upd7810_device::ADDNC_A_V, 2, 8, 8,L0\|L1}, /* a0: 0110 0000 1010 0000 */
1016		{&upd7810_device::ADDNC_A_A, 2, 8, 8,L0\|L1}, /* a1: 0110 0000 1010 0001 */
1017		{&upd7810_device::ADDNC_A_B, 2, 8, 8,L0\|L1}, /* a2: 0110 0000 1010 0010 */
1018		{&upd7810_device::ADDNC_A_C, 2, 8, 8,L0\|L1}, /* a3: 0110 0000 1010 0011 */
1019		{&upd7810_device::ADDNC_A_D, 2, 8, 8,L0\|L1}, /* a4: 0110 0000 1010 0100 */
1020		{&upd7810_device::ADDNC_A_E, 2, 8, 8,L0\|L1}, /* a5: 0110 0000 1010 0101 */
1021		{&upd7810_device::ADDNC_A_H, 2, 8, 8,L0\|L1}, /* a6: 0110 0000 1010 0110 */
1022		{&upd7810_device::ADDNC_A_L, 2, 8, 8,L0\|L1}, /* a7: 0110 0000 1010 0111 */
1023		{&upd7810_device::GTA_A_V, 2, 8, 8,L0\|L1}, /* a8: 0110 0000 1010 1000 */
1024		{&upd7810_device::GTA_A_A, 2, 8, 8,L0\|L1}, /* a9: 0110 0000 1010 1001 */
1025		{&upd7810_device::GTA_A_B, 2, 8, 8,L0\|L1}, /* aa: 0110 0000 1010 1010 */
1026		{&upd7810_device::GTA_A_C, 2, 8, 8,L0\|L1}, /* ab: 0110 0000 1010 1011 */
1027		{&upd7810_device::GTA_A_D, 2, 8, 8,L0\|L1}, /* ac: 0110 0000 1010 1100 */
1028		{&upd7810_device::GTA_A_E, 2, 8, 8,L0\|L1}, /* ad: 0110 0000 1010 1101 */
1029		{&upd7810_device::GTA_A_H, 2, 8, 8,L0\|L1}, /* ae: 0110 0000 1010 1110 */
1030		{&upd7810_device::GTA_A_L, 2, 8, 8,L0\|L1}, /* af: 0110 0000 1010 1111 */
1031
1032		{&upd7810_device::SUBNB_A_V, 2, 8, 8,L0\|L1}, /* b0: 0110 0000 1011 0000 */
1033		{&upd7810_device::SUBNB_A_A, 2, 8, 8,L0\|L1}, /* b1: 0110 0000 1011 0001 */
1034		{&upd7810_device::SUBNB_A_B, 2, 8, 8,L0\|L1}, /* b2: 0110 0000 1011 0010 */
1035		{&upd7810_device::SUBNB_A_C, 2, 8, 8,L0\|L1}, /* b3: 0110 0000 1011 0011 */
1036		{&upd7810_device::SUBNB_A_D, 2, 8, 8,L0\|L1}, /* b4: 0110 0000 1011 0100 */
1037		{&upd7810_device::SUBNB_A_E, 2, 8, 8,L0\|L1}, /* b5: 0110 0000 1011 0101 */
1038		{&upd7810_device::SUBNB_A_H, 2, 8, 8,L0\|L1}, /* b6: 0110 0000 1011 0110 */
1039		{&upd7810_device::SUBNB_A_L, 2, 8, 8,L0\|L1}, /* b7: 0110 0000 1011 0111 */
1040		{&upd7810_device::LTA_A_V, 2, 8, 8,L0\|L1}, /* b8: 0110 0000 1011 1000 */
1041		{&upd7810_device::LTA_A_A, 2, 8, 8,L0\|L1}, /* b9: 0110 0000 1011 1001 */
1042		{&upd7810_device::LTA_A_B, 2, 8, 8,L0\|L1}, /* ba: 0110 0000 1011 1010 */
1043		{&upd7810_device::LTA_A_C, 2, 8, 8,L0\|L1}, /* bb: 0110 0000 1011 1011 */
1044		{&upd7810_device::LTA_A_D, 2, 8, 8,L0\|L1}, /* bc: 0110 0000 1011 1100 */
1045		{&upd7810_device::LTA_A_E, 2, 8, 8,L0\|L1}, /* bd: 0110 0000 1011 1101 */
1046		{&upd7810_device::LTA_A_H, 2, 8, 8,L0\|L1}, /* be: 0110 0000 1011 1110 */
1047		{&upd7810_device::LTA_A_L, 2, 8, 8,L0\|L1}, /* bf: 0110 0000 1011 1111 */
1048
1049		{&upd7810_device::ADD_A_V, 2, 8, 8,L0\|L1}, /* c0: 0110 0000 1100 0000 */
1050		{&upd7810_device::ADD_A_A, 2, 8, 8,L0\|L1}, /* c1: 0110 0000 1100 0001 */
1051		{&upd7810_device::ADD_A_B, 2, 8, 8,L0\|L1}, /* c2: 0110 0000 1100 0010 */
1052		{&upd7810_device::ADD_A_C, 2, 8, 8,L0\|L1}, /* c3: 0110 0000 1100 0011 */
1053		{&upd7810_device::ADD_A_D, 2, 8, 8,L0\|L1}, /* c4: 0110 0000 1100 0100 */
1054		{&upd7810_device::ADD_A_E, 2, 8, 8,L0\|L1}, /* c5: 0110 0000 1100 0101 */
1055		{&upd7810_device::ADD_A_H, 2, 8, 8,L0\|L1}, /* c6: 0110 0000 1100 0110 */
1056		{&upd7810_device::ADD_A_L, 2, 8, 8,L0\|L1}, /* c7: 0110 0000 1100 0111 */
1057		{&upd7810_device::ONA_A_V, 2, 8, 8,L0\|L1}, /* c8: 0110 0000 1100 1000 */
1058		{&upd7810_device::ONA_A_A, 2, 8, 8,L0\|L1}, /* c9: 0110 0000 1100 1001 */
1059		{&upd7810_device::ONA_A_B, 2, 8, 8,L0\|L1}, /* ca: 0110 0000 1100 1010 */
1060		{&upd7810_device::ONA_A_C, 2, 8, 8,L0\|L1}, /* cb: 0110 0000 1100 1011 */
1061		{&upd7810_device::ONA_A_D, 2, 8, 8,L0\|L1}, /* cc: 0110 0000 1100 1100 */
1062		{&upd7810_device::ONA_A_E, 2, 8, 8,L0\|L1}, /* cd: 0110 0000 1100 1101 */
1063		{&upd7810_device::ONA_A_H, 2, 8, 8,L0\|L1}, /* ce: 0110 0000 1100 1110 */
1064		{&upd7810_device::ONA_A_L, 2, 8, 8,L0\|L1}, /* cf: 0110 0000 1100 1111 */
1065
1066		{&upd7810_device::ADC_A_V, 2, 8, 8,L0\|L1}, /* d0: 0110 0000 1101 0000 */
1067		{&upd7810_device::ADC_A_A, 2, 8, 8,L0\|L1}, /* d1: 0110 0000 1101 0001 */
1068		{&upd7810_device::ADC_A_B, 2, 8, 8,L0\|L1}, /* d2: 0110 0000 1101 0010 */
1069		{&upd7810_device::ADC_A_C, 2, 8, 8,L0\|L1}, /* d3: 0110 0000 1101 0011 */
1070		{&upd7810_device::ADC_A_D, 2, 8, 8,L0\|L1}, /* d4: 0110 0000 1101 0100 */
1071		{&upd7810_device::ADC_A_E, 2, 8, 8,L0\|L1}, /* d5: 0110 0000 1101 0101 */
1072		{&upd7810_device::ADC_A_H, 2, 8, 8,L0\|L1}, /* d6: 0110 0000 1101 0110 */
1073		{&upd7810_device::ADC_A_L, 2, 8, 8,L0\|L1}, /* d7: 0110 0000 1101 0111 */
1074		{&upd7810_device::OFFA_A_V, 2, 8, 8,L0\|L1}, /* d8: 0110 0000 1101 1000 */
1075		{&upd7810_device::OFFA_A_A, 2, 8, 8,L0\|L1}, /* d9: 0110 0000 1101 1001 */
1076		{&upd7810_device::OFFA_A_B, 2, 8, 8,L0\|L1}, /* da: 0110 0000 1101 1010 */
1077		{&upd7810_device::OFFA_A_C, 2, 8, 8,L0\|L1}, /* db: 0110 0000 1101 1011 */
1078		{&upd7810_device::OFFA_A_D, 2, 8, 8,L0\|L1}, /* dc: 0110 0000 1101 1100 */
1079		{&upd7810_device::OFFA_A_E, 2, 8, 8,L0\|L1}, /* dd: 0110 0000 1101 1101 */
1080		{&upd7810_device::OFFA_A_H, 2, 8, 8,L0\|L1}, /* de: 0110 0000 1101 1110 */
1081		{&upd7810_device::OFFA_A_L, 2, 8, 8,L0\|L1}, /* df: 0110 0000 1101 1111 */
1082
1083		{&upd7810_device::SUB_A_V, 2, 8, 8,L0\|L1}, /* e0: 0110 0000 1110 0000 */
1084		{&upd7810_device::SUB_A_A, 2, 8, 8,L0\|L1}, /* e1: 0110 0000 1110 0001 */
1085		{&upd7810_device::SUB_A_B, 2, 8, 8,L0\|L1}, /* e2: 0110 0000 1110 0010 */
1086		{&upd7810_device::SUB_A_C, 2, 8, 8,L0\|L1}, /* e3: 0110 0000 1110 0011 */
1087		{&upd7810_device::SUB_A_D, 2, 8, 8,L0\|L1}, /* e4: 0110 0000 1110 0100 */
1088		{&upd7810_device::SUB_A_E, 2, 8, 8,L0\|L1}, /* e5: 0110 0000 1110 0101 */
1089		{&upd7810_device::SUB_A_H, 2, 8, 8,L0\|L1}, /* e6: 0110 0000 1110 0110 */
1090		{&upd7810_device::SUB_A_L, 2, 8, 8,L0\|L1}, /* e7: 0110 0000 1110 0111 */
1091		{&upd7810_device::NEA_A_V, 2, 8, 8,L0\|L1}, /* e8: 0110 0000 1110 1000 */
1092		{&upd7810_device::NEA_A_A, 2, 8, 8,L0\|L1}, /* e9: 0110 0000 1110 1001 */
1093		{&upd7810_device::NEA_A_B, 2, 8, 8,L0\|L1}, /* ea: 0110 0000 1110 1010 */
1094		{&upd7810_device::NEA_A_C, 2, 8, 8,L0\|L1}, /* eb: 0110 0000 1110 1011 */
1095		{&upd7810_device::NEA_A_D, 2, 8, 8,L0\|L1}, /* ec: 0110 0000 1110 1100 */
1096		{&upd7810_device::NEA_A_E, 2, 8, 8,L0\|L1}, /* ed: 0110 0000 1110 1101 */
1097		{&upd7810_device::NEA_A_H, 2, 8, 8,L0\|L1}, /* ee: 0110 0000 1110 1110 */
1098		{&upd7810_device::NEA_A_L, 2, 8, 8,L0\|L1}, /* ef: 0110 0000 1110 1111 */
1099
1100		{&upd7810_device::SBB_A_V, 2, 8, 8,L0\|L1}, /* f0: 0110 0000 1111 0000 */
1101		{&upd7810_device::SBB_A_A, 2, 8, 8,L0\|L1}, /* f1: 0110 0000 1111 0001 */
1102		{&upd7810_device::SBB_A_B, 2, 8, 8,L0\|L1}, /* f2: 0110 0000 1111 0010 */
1103		{&upd7810_device::SBB_A_C, 2, 8, 8,L0\|L1}, /* f3: 0110 0000 1111 0011 */
1104		{&upd7810_device::SBB_A_D, 2, 8, 8,L0\|L1}, /* f4: 0110 0000 1111 0100 */
1105		{&upd7810_device::SBB_A_E, 2, 8, 8,L0\|L1}, /* f5: 0110 0000 1111 0101 */
1106		{&upd7810_device::SBB_A_H, 2, 8, 8,L0\|L1}, /* f6: 0110 0000 1111 0110 */
1107		{&upd7810_device::SBB_A_L, 2, 8, 8,L0\|L1}, /* f7: 0110 0000 1111 0111 */
1108		{&upd7810_device::EQA_A_V, 2, 8, 8,L0\|L1}, /* f8: 0110 0000 1111 1000 */
1109		{&upd7810_device::EQA_A_A, 2, 8, 8,L0\|L1}, /* f9: 0110 0000 1111 1001 */
1110		{&upd7810_device::EQA_A_B, 2, 8, 8,L0\|L1}, /* fa: 0110 0000 1111 1010 */
1111		{&upd7810_device::EQA_A_C, 2, 8, 8,L0\|L1}, /* fb: 0110 0000 1111 1011 */
1112		{&upd7810_device::EQA_A_D, 2, 8, 8,L0\|L1}, /* fc: 0110 0000 1111 1100 */
1113		{&upd7810_device::EQA_A_E, 2, 8, 8,L0\|L1}, /* fd: 0110 0000 1111 1101 */
1114		{&upd7810_device::EQA_A_H, 2, 8, 8,L0\|L1}, /* fe: 0110 0000 1111 1110 */
1115		{&upd7810_device::EQA_A_L, 2, 8, 8,L0\|L1} /* ff: 0110 0000 1111 1111 */
1116		};
1117
1118		/* prefix 64 */
1119		const struct upd7810_device::opcode_s upd7810_device::s_op64[256] =
1120		{
1121		{&upd7810_device::MVI_PA_xx, 3,14,11,L0\|L1}, /* 00: 0110 0100 0000 0000 xxxx xxxx */
1122		{&upd7810_device::MVI_PB_xx, 3,14,11,L0\|L1}, /* 01: 0110 0100 0000 0001 xxxx xxxx */
1123		{&upd7810_device::MVI_PC_xx, 3,14,11,L0\|L1}, /* 02: 0110 0100 0000 0010 xxxx xxxx */
1124		{&upd7810_device::MVI_PD_xx, 3,14,11,L0\|L1}, /* 03: 0110 0100 0000 0011 xxxx xxxx */
1125		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 04: 0110 0100 0000 0100 xxxx xxxx */
1126		{&upd7810_device::MVI_PF_xx, 3,14,11,L0\|L1}, /* 05: 0110 0100 0000 0101 xxxx xxxx */
1127		{&upd7810_device::MVI_MKH_xx, 3,14,11,L0\|L1}, /* 06: 0110 0100 0000 0110 xxxx xxxx */
1128		{&upd7810_device::MVI_MKL_xx, 3,14,11,L0\|L1}, /* 07: 0110 0100 0000 0111 xxxx xxxx */
1129		{&upd7810_device::ANI_PA_xx, 3,20,11,L0\|L1}, /* 08: 0110 0100 0000 1000 xxxx xxxx */
1130		{&upd7810_device::ANI_PB_xx, 3,20,11,L0\|L1}, /* 09: 0110 0100 0000 1001 xxxx xxxx */
1131		{&upd7810_device::ANI_PC_xx, 3,20,11,L0\|L1}, /* 0a: 0110 0100 0000 1010 xxxx xxxx */
1132		{&upd7810_device::ANI_PD_xx, 3,20,11,L0\|L1}, /* 0b: 0110 0100 0000 1011 xxxx xxxx */
1133		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 0c: 0110 0100 0000 1100 xxxx xxxx */
1134		{&upd7810_device::ANI_PF_xx, 3,20,11,L0\|L1}, /* 0d: 0110 0100 0000 1101 xxxx xxxx */
1135		{&upd7810_device::ANI_MKH_xx, 3,20,11,L0\|L1}, /* 0e: 0110 0100 0000 1110 xxxx xxxx */
1136		{&upd7810_device::ANI_MKL_xx, 3,20,11,L0\|L1}, /* 0f: 0110 0100 0000 1111 xxxx xxxx */
1137
1138		{&upd7810_device::XRI_PA_xx, 3,20,11,L0\|L1}, /* 10: 0110 0100 0001 0000 xxxx xxxx */
1139		{&upd7810_device::XRI_PB_xx, 3,20,11,L0\|L1}, /* 11: 0110 0100 0001 0001 xxxx xxxx */
1140		{&upd7810_device::XRI_PC_xx, 3,20,11,L0\|L1}, /* 12: 0110 0100 0001 0010 xxxx xxxx */
1141		{&upd7810_device::XRI_PD_xx, 3,20,11,L0\|L1}, /* 13: 0110 0100 0001 0011 xxxx xxxx */
1142		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 14: 0110 0100 0001 0100 xxxx xxxx */
1143		{&upd7810_device::XRI_PF_xx, 3,20,11,L0\|L1}, /* 15: 0110 0100 0001 0101 xxxx xxxx */
1144		{&upd7810_device::XRI_MKH_xx, 3,20,11,L0\|L1}, /* 16: 0110 0100 0001 0110 xxxx xxxx */
1145		{&upd7810_device::XRI_MKL_xx, 3,20,11,L0\|L1}, /* 17: 0110 0100 0001 0111 xxxx xxxx */
1146		{&upd7810_device::ORI_PA_xx, 3,20,11,L0\|L1}, /* 18: 0110 0100 0001 1000 xxxx xxxx */
1147		{&upd7810_device::ORI_PB_xx, 3,20,11,L0\|L1}, /* 19: 0110 0100 0001 1001 xxxx xxxx */
1148		{&upd7810_device::ORI_PC_xx, 3,20,11,L0\|L1}, /* 1a: 0110 0100 0001 1010 xxxx xxxx */
1149		{&upd7810_device::ORI_PD_xx, 3,20,11,L0\|L1}, /* 1b: 0110 0100 0001 1011 xxxx xxxx */
1150		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 1c: 0110 0100 0001 1100 xxxx xxxx */
1151		{&upd7810_device::ORI_PF_xx, 3,20,11,L0\|L1}, /* 1d: 0110 0100 0001 1101 xxxx xxxx */
1152		{&upd7810_device::ORI_MKH_xx, 3,20,11,L0\|L1}, /* 1e: 0110 0100 0001 1110 xxxx xxxx */
1153		{&upd7810_device::ORI_MKL_xx, 3,20,11,L0\|L1}, /* 1f: 0110 0100 0001 1111 xxxx xxxx */
1154
1155		{&upd7810_device::ADINC_PA_xx, 3,20,11,L0\|L1}, /* 20: 0110 0100 0010 0000 xxxx xxxx */
1156		{&upd7810_device::ADINC_PB_xx, 3,20,11,L0\|L1}, /* 21: 0110 0100 0010 0001 xxxx xxxx */
1157		{&upd7810_device::ADINC_PC_xx, 3,20,11,L0\|L1}, /* 22: 0110 0100 0010 0010 xxxx xxxx */
1158		{&upd7810_device::ADINC_PD_xx, 3,20,11,L0\|L1}, /* 23: 0110 0100 0010 0011 xxxx xxxx */
1159		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 24: 0110 0100 0010 0100 xxxx xxxx */
1160		{&upd7810_device::ADINC_PF_xx, 3,20,11,L0\|L1}, /* 25: 0110 0100 0010 0101 xxxx xxxx */
1161		{&upd7810_device::ADINC_MKH_xx, 3,20,11,L0\|L1}, /* 26: 0110 0100 0010 0110 xxxx xxxx */
1162		{&upd7810_device::ADINC_MKL_xx, 3,20,11,L0\|L1}, /* 27: 0110 0100 0010 0111 xxxx xxxx */
1163		{&upd7810_device::GTI_PA_xx, 3,20,11,L0\|L1}, /* 28: 0110 0100 0010 1000 xxxx xxxx */
1164		{&upd7810_device::GTI_PB_xx, 3,20,11,L0\|L1}, /* 29: 0110 0100 0010 1001 xxxx xxxx */
1165		{&upd7810_device::GTI_PC_xx, 3,20,11,L0\|L1}, /* 2a: 0110 0100 0010 1010 xxxx xxxx */
1166		{&upd7810_device::GTI_PD_xx, 3,20,11,L0\|L1}, /* 2b: 0110 0100 0010 1011 xxxx xxxx */
1167		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 2c: 0110 0100 0010 1100 xxxx xxxx */
1168		{&upd7810_device::GTI_PF_xx, 3,20,11,L0\|L1}, /* 2d: 0110 0100 0010 1101 xxxx xxxx */
1169		{&upd7810_device::GTI_MKH_xx, 3,20,11,L0\|L1}, /* 2e: 0110 0100 0010 1110 xxxx xxxx */
1170		{&upd7810_device::GTI_MKL_xx, 3,20,11,L0\|L1}, /* 2f: 0110 0100 0010 1111 xxxx xxxx */
1171
1172		{&upd7810_device::SUINB_PA_xx, 3,20,11,L0\|L1}, /* 30: 0110 0100 0011 0000 xxxx xxxx */
1173		{&upd7810_device::SUINB_PB_xx, 3,20,11,L0\|L1}, /* 31: 0110 0100 0011 0001 xxxx xxxx */
1174		{&upd7810_device::SUINB_PC_xx, 3,20,11,L0\|L1}, /* 32: 0110 0100 0011 0010 xxxx xxxx */
1175		{&upd7810_device::SUINB_PD_xx, 3,20,11,L0\|L1}, /* 33: 0110 0100 0011 0011 xxxx xxxx */
1176		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 34: 0110 0100 0011 0100 xxxx xxxx */
1177		{&upd7810_device::SUINB_PF_xx, 3,20,11,L0\|L1}, /* 35: 0110 0100 0011 0101 xxxx xxxx */
1178		{&upd7810_device::SUINB_MKH_xx, 3,20,11,L0\|L1}, /* 36: 0110 0100 0011 0110 xxxx xxxx */
1179		{&upd7810_device::SUINB_MKL_xx, 3,20,11,L0\|L1}, /* 37: 0110 0100 0011 0111 xxxx xxxx */
1180		{&upd7810_device::LTI_PA_xx, 3,20,11,L0\|L1}, /* 38: 0110 0100 0011 1000 xxxx xxxx */
1181		{&upd7810_device::LTI_PB_xx, 3,20,11,L0\|L1}, /* 39: 0110 0100 0011 1001 xxxx xxxx */
1182		{&upd7810_device::LTI_PC_xx, 3,20,11,L0\|L1}, /* 3a: 0110 0100 0011 1010 xxxx xxxx */
1183		{&upd7810_device::LTI_PD_xx, 3,20,11,L0\|L1}, /* 3b: 0110 0100 0011 1011 xxxx xxxx */
1184		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 3c: 0110 0100 0011 1100 xxxx xxxx */
1185		{&upd7810_device::LTI_PF_xx, 3,20,11,L0\|L1}, /* 3d: 0110 0100 0011 1101 xxxx xxxx */
1186		{&upd7810_device::LTI_MKH_xx, 3,20,11,L0\|L1}, /* 3e: 0110 0100 0011 1110 xxxx xxxx */
1187		{&upd7810_device::LTI_MKL_xx, 3,20,11,L0\|L1}, /* 3f: 0110 0100 0011 1111 xxxx xxxx */
1188
1189		{&upd7810_device::ADI_PA_xx, 3,20,11,L0\|L1}, /* 40: 0110 0100 0100 0000 xxxx xxxx */
1190		{&upd7810_device::ADI_PB_xx, 3,20,11,L0\|L1}, /* 41: 0110 0100 0100 0001 xxxx xxxx */
1191		{&upd7810_device::ADI_PC_xx, 3,20,11,L0\|L1}, /* 42: 0110 0100 0100 0010 xxxx xxxx */
1192		{&upd7810_device::ADI_PD_xx, 3,20,11,L0\|L1}, /* 43: 0110 0100 0100 0011 xxxx xxxx */
1193		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 44: 0110 0100 0100 0100 xxxx xxxx */
1194		{&upd7810_device::ADI_PF_xx, 3,20,11,L0\|L1}, /* 45: 0110 0100 0100 0101 xxxx xxxx */
1195		{&upd7810_device::ADI_MKH_xx, 3,20,11,L0\|L1}, /* 46: 0110 0100 0100 0110 xxxx xxxx */
1196		{&upd7810_device::ADI_MKL_xx, 3,20,11,L0\|L1}, /* 47: 0110 0100 0100 0111 xxxx xxxx */
1197		{&upd7810_device::ONI_PA_xx, 3,20,11,L0\|L1}, /* 48: 0110 0100 0100 1000 xxxx xxxx */
1198		{&upd7810_device::ONI_PB_xx, 3,20,11,L0\|L1}, /* 49: 0110 0100 0100 1001 xxxx xxxx */
1199		{&upd7810_device::ONI_PC_xx, 3,20,11,L0\|L1}, /* 4a: 0110 0100 0100 1010 xxxx xxxx */
1200		{&upd7810_device::ONI_PD_xx, 3,20,11,L0\|L1}, /* 4b: 0110 0100 0100 1011 xxxx xxxx */
1201		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 4c: 0110 0100 0100 1100 xxxx xxxx */
1202		{&upd7810_device::ONI_PF_xx, 3,20,11,L0\|L1}, /* 4d: 0110 0100 0100 1101 xxxx xxxx */
1203		{&upd7810_device::ONI_MKH_xx, 3,20,11,L0\|L1}, /* 4e: 0110 0100 0100 1110 xxxx xxxx */
1204		{&upd7810_device::ONI_MKL_xx, 3,20,11,L0\|L1}, /* 4f: 0110 0100 0100 1111 xxxx xxxx */
1205
1206		{&upd7810_device::ACI_PA_xx, 3,20,11,L0\|L1}, /* 50: 0110 0100 0101 0000 xxxx xxxx */
1207		{&upd7810_device::ACI_PB_xx, 3,20,11,L0\|L1}, /* 51: 0110 0100 0101 0001 xxxx xxxx */
1208		{&upd7810_device::ACI_PC_xx, 3,20,11,L0\|L1}, /* 52: 0110 0100 0101 0010 xxxx xxxx */
1209		{&upd7810_device::ACI_PD_xx, 3,20,11,L0\|L1}, /* 53: 0110 0100 0101 0011 xxxx xxxx */
1210		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 54: 0110 0100 0101 0100 xxxx xxxx */
1211		{&upd7810_device::ACI_PF_xx, 3,20,11,L0\|L1}, /* 55: 0110 0100 0101 0101 xxxx xxxx */
1212		{&upd7810_device::ACI_MKH_xx, 3,20,11,L0\|L1}, /* 56: 0110 0100 0101 0110 xxxx xxxx */
1213		{&upd7810_device::ACI_MKL_xx, 3,20,11,L0\|L1}, /* 57: 0110 0100 0101 0111 xxxx xxxx */
1214		{&upd7810_device::OFFI_PA_xx, 3,20,11,L0\|L1}, /* 58: 0110 0100 0101 1000 xxxx xxxx */
1215		{&upd7810_device::OFFI_PB_xx, 3,20,11,L0\|L1}, /* 59: 0110 0100 0101 1001 xxxx xxxx */
1216		{&upd7810_device::OFFI_PC_xx, 3,20,11,L0\|L1}, /* 5a: 0110 0100 0101 1010 xxxx xxxx */
1217		{&upd7810_device::OFFI_PD_xx, 3,20,11,L0\|L1}, /* 5b: 0110 0100 0101 1011 xxxx xxxx */
1218		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 5c: 0110 0100 0101 1100 xxxx xxxx */
1219		{&upd7810_device::OFFI_PF_xx, 3,20,11,L0\|L1}, /* 5d: 0110 0100 0101 1101 xxxx xxxx */
1220		{&upd7810_device::OFFI_MKH_xx, 3,20,11,L0\|L1}, /* 5e: 0110 0100 0101 1110 xxxx xxxx */
1221		{&upd7810_device::OFFI_MKL_xx, 3,20,11,L0\|L1}, /* 5f: 0110 0100 0101 1111 xxxx xxxx */
1222
1223		{&upd7810_device::SUI_PA_xx, 3,20,11,L0\|L1}, /* 60: 0110 0100 0110 0000 xxxx xxxx */
1224		{&upd7810_device::SUI_PB_xx, 3,20,11,L0\|L1}, /* 61: 0110 0100 0110 0001 xxxx xxxx */
1225		{&upd7810_device::SUI_PC_xx, 3,20,11,L0\|L1}, /* 62: 0110 0100 0110 0010 xxxx xxxx */
1226		{&upd7810_device::SUI_PD_xx, 3,20,11,L0\|L1}, /* 63: 0110 0100 0110 0011 xxxx xxxx */
1227		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 64: 0110 0100 0110 0100 xxxx xxxx */
1228		{&upd7810_device::SUI_PF_xx, 3,20,11,L0\|L1}, /* 65: 0110 0100 0110 0101 xxxx xxxx */
1229		{&upd7810_device::SUI_MKH_xx, 3,20,11,L0\|L1}, /* 66: 0110 0100 0110 0110 xxxx xxxx */
1230		{&upd7810_device::SUI_MKL_xx, 3,20,11,L0\|L1}, /* 67: 0110 0100 0110 0111 xxxx xxxx */
1231		{&upd7810_device::NEI_PA_xx, 3,20,11,L0\|L1}, /* 68: 0110 0100 0110 1000 xxxx xxxx */
1232		{&upd7810_device::NEI_PB_xx, 3,20,11,L0\|L1}, /* 69: 0110 0100 0110 1001 xxxx xxxx */
1233		{&upd7810_device::NEI_PC_xx, 3,20,11,L0\|L1}, /* 6a: 0110 0100 0110 1010 xxxx xxxx */
1234		{&upd7810_device::NEI_PD_xx, 3,20,11,L0\|L1}, /* 6b: 0110 0100 0110 1011 xxxx xxxx */
1235		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 6c: 0110 0100 0110 1100 xxxx xxxx */
1236		{&upd7810_device::NEI_PF_xx, 3,20,11,L0\|L1}, /* 6d: 0110 0100 0110 1101 xxxx xxxx */
1237		{&upd7810_device::NEI_MKH_xx, 3,20,11,L0\|L1}, /* 6e: 0110 0100 0110 1110 xxxx xxxx */
1238		{&upd7810_device::NEI_MKL_xx, 3,20,11,L0\|L1}, /* 6f: 0110 0100 0110 1111 xxxx xxxx */
1239
1240		{&upd7810_device::SBI_PA_xx, 3,20,11,L0\|L1}, /* 70: 0110 0100 0111 0000 xxxx xxxx */
1241		{&upd7810_device::SBI_PB_xx, 3,20,11,L0\|L1}, /* 71: 0110 0100 0111 0001 xxxx xxxx */
1242		{&upd7810_device::SBI_PC_xx, 3,20,11,L0\|L1}, /* 72: 0110 0100 0111 0010 xxxx xxxx */
1243		{&upd7810_device::SBI_PD_xx, 3,20,11,L0\|L1}, /* 73: 0110 0100 0111 0011 xxxx xxxx */
1244		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 74: 0110 0100 0111 0100 xxxx xxxx */
1245		{&upd7810_device::SBI_PF_xx, 3,20,11,L0\|L1}, /* 75: 0110 0100 0111 0101 xxxx xxxx */
1246		{&upd7810_device::SBI_MKH_xx, 3,20,11,L0\|L1}, /* 76: 0110 0100 0111 0110 xxxx xxxx */
1247		{&upd7810_device::SBI_MKL_xx, 3,20,11,L0\|L1}, /* 77: 0110 0100 0111 0111 xxxx xxxx */
1248		{&upd7810_device::EQI_PA_xx, 3,20,11,L0\|L1}, /* 78: 0110 0100 0111 1000 xxxx xxxx */
1249		{&upd7810_device::EQI_PB_xx, 3,20,11,L0\|L1}, /* 79: 0110 0100 0111 1001 xxxx xxxx */
1250		{&upd7810_device::EQI_PC_xx, 3,20,11,L0\|L1}, /* 7a: 0110 0100 0111 1010 xxxx xxxx */
1251		{&upd7810_device::EQI_PD_xx, 3,20,11,L0\|L1}, /* 7b: 0110 0100 0111 1011 xxxx xxxx */
1252		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 7c: 0110 0100 0111 1100 xxxx xxxx */
1253		{&upd7810_device::EQI_PF_xx, 3,20,11,L0\|L1}, /* 7d: 0110 0100 0111 1101 xxxx xxxx */
1254		{&upd7810_device::EQI_MKH_xx, 3,20,11,L0\|L1}, /* 7e: 0110 0100 0111 1110 xxxx xxxx */
1255		{&upd7810_device::EQI_MKL_xx, 3,20,11,L0\|L1}, /* 7f: 0110 0100 0111 1111 xxxx xxxx */
1256
1257		{&upd7810_device::MVI_ANM_xx, 3,14,11,L0\|L1}, /* 80: 0110 0100 1000 0000 xxxx xxxx */
1258		{&upd7810_device::MVI_SMH_xx, 3,14,11,L0\|L1}, /* 81: 0110 0100 1000 0001 xxxx xxxx */
1259		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 82: 0110 0100 1000 0010 xxxx xxxx */
1260		{&upd7810_device::MVI_EOM_xx, 3,14,11,L0\|L1}, /* 83: 0110 0100 1000 0011 xxxx xxxx */
1261		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 84: 0110 0100 1000 0100 xxxx xxxx */
1262		{&upd7810_device::MVI_TMM_xx, 3,14,11,L0\|L1}, /* 85: 0110 0100 1000 0101 xxxx xxxx */
1263		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 86: 0110 0100 1000 0110 xxxx xxxx */
1264		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 87: 0110 0100 1000 0111 xxxx xxxx */
1265		{&upd7810_device::ANI_ANM_xx, 3,20,11,L0\|L1}, /* 88: 0110 0100 1000 1000 xxxx xxxx */
1266		{&upd7810_device::ANI_SMH_xx, 3,20,11,L0\|L1}, /* 89: 0110 0100 1000 1001 xxxx xxxx */
1267		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 8a: 0110 0100 1000 1010 xxxx xxxx */
1268		{&upd7810_device::ANI_EOM_xx, 3,20,11,L0\|L1}, /* 8b: 0110 0100 1000 1011 xxxx xxxx */
1269		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 8c: 0110 0100 1000 1100 xxxx xxxx */
1270		{&upd7810_device::ANI_TMM_xx, 3,20,11,L0\|L1}, /* 8d: 0110 0100 1000 1101 xxxx xxxx */
1271		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 8e: 0110 0100 1000 1110 xxxx xxxx */
1272		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 8f: 0110 0100 1000 1111 xxxx xxxx */
1273
1274		{&upd7810_device::XRI_ANM_xx, 3,20,11,L0\|L1}, /* 90: 0110 0100 1001 0000 xxxx xxxx */
1275		{&upd7810_device::XRI_SMH_xx, 3,20,11,L0\|L1}, /* 91: 0110 0100 1001 0001 xxxx xxxx */
1276		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 92: 0110 0100 1001 0010 xxxx xxxx */
1277		{&upd7810_device::XRI_EOM_xx, 3,20,11,L0\|L1}, /* 93: 0110 0100 1001 0011 xxxx xxxx */
1278		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 94: 0110 0100 1001 0100 xxxx xxxx */
1279		{&upd7810_device::XRI_TMM_xx, 3,20,11,L0\|L1}, /* 95: 0110 0100 1001 0101 xxxx xxxx */
1280		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 96: 0110 0100 1001 0110 xxxx xxxx */
1281		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 97: 0110 0100 1001 0111 xxxx xxxx */
1282		{&upd7810_device::ORI_ANM_xx, 3,20,11,L0\|L1}, /* 98: 0110 0100 1001 1000 xxxx xxxx */
1283		{&upd7810_device::ORI_SMH_xx, 3,20,11,L0\|L1}, /* 99: 0110 0100 1001 1001 xxxx xxxx */
1284		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 9a: 0110 0100 1001 1010 xxxx xxxx */
1285		{&upd7810_device::ORI_EOM_xx, 3,20,11,L0\|L1}, /* 9b: 0110 0100 1001 1011 xxxx xxxx */
1286		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 9c: 0110 0100 1001 1100 xxxx xxxx */
1287		{&upd7810_device::ORI_TMM_xx, 3,20,11,L0\|L1}, /* 9d: 0110 0100 1001 1101 xxxx xxxx */
1288		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 9e: 0110 0100 1001 1110 xxxx xxxx */
1289		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 9f: 0110 0100 1001 1111 xxxx xxxx */
1290
1291		{&upd7810_device::ADINC_ANM_xx, 3,20,11,L0\|L1}, /* a0: 0110 0100 1010 0000 xxxx xxxx */
1292		{&upd7810_device::ADINC_SMH_xx, 3,20,11,L0\|L1}, /* a1: 0110 0100 1010 0001 xxxx xxxx */
1293		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* a2: 0110 0100 1010 0010 xxxx xxxx */
1294		{&upd7810_device::ADINC_EOM_xx, 3,20,11,L0\|L1}, /* a3: 0110 0100 1010 0011 xxxx xxxx */
1295		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* a4: 0110 0100 1010 0100 xxxx xxxx */
1296		{&upd7810_device::ADINC_TMM_xx, 3,20,11,L0\|L1}, /* a5: 0110 0100 1010 0101 xxxx xxxx */
1297		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* a6: 0110 0100 1010 0110 xxxx xxxx */
1298		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* a7: 0110 0100 1010 0111 xxxx xxxx */
1299		{&upd7810_device::GTI_ANM_xx, 3,20,11,L0\|L1}, /* a8: 0110 0100 1010 1000 xxxx xxxx */
1300		{&upd7810_device::GTI_SMH_xx, 3,20,11,L0\|L1}, /* a9: 0110 0100 1010 1001 xxxx xxxx */
1301		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* aa: 0110 0100 1010 1010 xxxx xxxx */
1302		{&upd7810_device::GTI_EOM_xx, 3,20,11,L0\|L1}, /* ab: 0110 0100 1010 1011 xxxx xxxx */
1303		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ac: 0110 0100 1010 1100 xxxx xxxx */
1304		{&upd7810_device::GTI_TMM_xx, 3,20,11,L0\|L1}, /* ad: 0110 0100 1010 1101 xxxx xxxx */
1305		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ae: 0110 0100 1010 1110 xxxx xxxx */
1306		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* af: 0110 0100 1010 1111 xxxx xxxx */
1307
1308		{&upd7810_device::SUINB_ANM_xx, 3,20,11,L0\|L1}, /* b0: 0110 0100 1011 0000 xxxx xxxx */
1309		{&upd7810_device::SUINB_SMH_xx, 3,20,11,L0\|L1}, /* b1: 0110 0100 1011 0001 xxxx xxxx */
1310		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* b2: 0110 0100 1011 0010 xxxx xxxx */
1311		{&upd7810_device::SUINB_EOM_xx, 3,20,11,L0\|L1}, /* b3: 0110 0100 1011 0011 xxxx xxxx */
1312		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* b4: 0110 0100 1011 0100 xxxx xxxx */
1313		{&upd7810_device::SUINB_TMM_xx, 3,20,11,L0\|L1}, /* b5: 0110 0100 1011 0101 xxxx xxxx */
1314		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* b6: 0110 0100 1011 0110 xxxx xxxx */
1315		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* b7: 0110 0100 1011 0111 xxxx xxxx */
1316		{&upd7810_device::LTI_ANM_xx, 3,20,11,L0\|L1}, /* b8: 0110 0100 1011 1000 xxxx xxxx */
1317		{&upd7810_device::LTI_SMH_xx, 3,20,11,L0\|L1}, /* b9: 0110 0100 1011 1001 xxxx xxxx */
1318		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ba: 0110 0100 1011 1010 xxxx xxxx */
1319		{&upd7810_device::LTI_EOM_xx, 3,20,11,L0\|L1}, /* bb: 0110 0100 1011 1011 xxxx xxxx */
1320		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* bc: 0110 0100 1011 1100 xxxx xxxx */
1321		{&upd7810_device::LTI_TMM_xx, 3,20,11,L0\|L1}, /* bd: 0110 0100 1011 1101 xxxx xxxx */
1322		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* be: 0110 0100 1011 1110 xxxx xxxx */
1323		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* bf: 0110 0100 1011 1111 xxxx xxxx */
1324
1325		{&upd7810_device::ADI_ANM_xx, 3,20,11,L0\|L1}, /* c0: 0110 0100 1100 0000 xxxx xxxx */
1326		{&upd7810_device::ADI_SMH_xx, 3,20,11,L0\|L1}, /* c1: 0110 0100 1100 0001 xxxx xxxx */
1327		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* c2: 0110 0100 1100 0010 xxxx xxxx */
1328		{&upd7810_device::ADI_EOM_xx, 3,20,11,L0\|L1}, /* c3: 0110 0100 1100 0011 xxxx xxxx */
1329		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* c4: 0110 0100 1100 0100 xxxx xxxx */
1330		{&upd7810_device::ADI_TMM_xx, 3,20,11,L0\|L1}, /* c5: 0110 0100 1100 0101 xxxx xxxx */
1331		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* c6: 0110 0100 1100 0110 xxxx xxxx */
1332		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* c7: 0110 0100 1100 0111 xxxx xxxx */
1333		{&upd7810_device::ONI_ANM_xx, 3,20,11,L0\|L1}, /* c8: 0110 0100 1100 1000 xxxx xxxx */
1334		{&upd7810_device::ONI_SMH_xx, 3,20,11,L0\|L1}, /* c9: 0110 0100 1100 1001 xxxx xxxx */
1335		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ca: 0110 0100 1100 1010 xxxx xxxx */
1336		{&upd7810_device::ONI_EOM_xx, 3,20,11,L0\|L1}, /* cb: 0110 0100 1100 1011 xxxx xxxx */
1337		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* cc: 0110 0100 1100 1100 xxxx xxxx */
1338		{&upd7810_device::ONI_TMM_xx, 3,20,11,L0\|L1}, /* cd: 0110 0100 1100 1101 xxxx xxxx */
1339		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ce: 0110 0100 1100 1110 xxxx xxxx */
1340		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* cf: 0110 0100 1100 1111 xxxx xxxx */
1341
1342		{&upd7810_device::ACI_ANM_xx, 3,20,11,L0\|L1}, /* d0: 0110 0100 1101 0000 xxxx xxxx */
1343		{&upd7810_device::ACI_SMH_xx, 3,20,11,L0\|L1}, /* d1: 0110 0100 1101 0001 xxxx xxxx */
1344		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* d2: 0110 0100 1101 0010 xxxx xxxx */
1345		{&upd7810_device::ACI_EOM_xx, 3,20,11,L0\|L1}, /* d3: 0110 0100 1101 0011 xxxx xxxx */
1346		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* d4: 0110 0100 1101 0100 xxxx xxxx */
1347		{&upd7810_device::ACI_TMM_xx, 3,20,11,L0\|L1}, /* d5: 0110 0100 1101 0101 xxxx xxxx */
1348		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* d6: 0110 0100 1101 0110 xxxx xxxx */
1349		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* d7: 0110 0100 1101 0111 xxxx xxxx */
1350		{&upd7810_device::OFFI_ANM_xx, 3,20,11,L0\|L1}, /* d8: 0110 0100 1101 1000 xxxx xxxx */
1351		{&upd7810_device::OFFI_SMH_xx, 3,20,11,L0\|L1}, /* d9: 0110 0100 1101 1001 xxxx xxxx */
1352		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* da: 0110 0100 1101 1010 xxxx xxxx */
1353		{&upd7810_device::OFFI_EOM_xx, 3,20,11,L0\|L1}, /* db: 0110 0100 1101 1011 xxxx xxxx */
1354		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* dc: 0110 0100 1101 1100 xxxx xxxx */
1355		{&upd7810_device::OFFI_TMM_xx, 3,20,11,L0\|L1}, /* dd: 0110 0100 1101 1101 xxxx xxxx */
1356		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* de: 0110 0100 1101 1110 xxxx xxxx */
1357		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* df: 0110 0100 1101 1111 xxxx xxxx */
1358
1359		{&upd7810_device::SUI_ANM_xx, 3,20,11,L0\|L1}, /* e0: 0110 0100 1110 0000 xxxx xxxx */
1360		{&upd7810_device::SUI_SMH_xx, 3,20,11,L0\|L1}, /* e1: 0110 0100 1110 0001 xxxx xxxx */
1361		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* e2: 0110 0100 1110 0010 xxxx xxxx */
1362		{&upd7810_device::SUI_EOM_xx, 3,20,11,L0\|L1}, /* e3: 0110 0100 1110 0011 xxxx xxxx */
1363		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* e4: 0110 0100 1110 0100 xxxx xxxx */
1364		{&upd7810_device::SUI_TMM_xx, 3,20,11,L0\|L1}, /* e5: 0110 0100 1110 0101 xxxx xxxx */
1365		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* e6: 0110 0100 1110 0110 xxxx xxxx */
1366		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* e7: 0110 0100 1110 0111 xxxx xxxx */
1367		{&upd7810_device::NEI_ANM_xx, 3,20,11,L0\|L1}, /* e8: 0110 0100 1110 1000 xxxx xxxx */
1368		{&upd7810_device::NEI_SMH_xx, 3,20,11,L0\|L1}, /* e9: 0110 0100 1110 1001 xxxx xxxx */
1369		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ea: 0110 0100 1110 1010 xxxx xxxx */
1370		{&upd7810_device::NEI_EOM_xx, 3,20,11,L0\|L1}, /* eb: 0110 0100 1110 1011 xxxx xxxx */
1371		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ec: 0110 0100 1110 1100 xxxx xxxx */
1372		{&upd7810_device::NEI_TMM_xx, 3,20,11,L0\|L1}, /* ed: 0110 0100 1110 1101 xxxx xxxx */
1373		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ee: 0110 0100 1110 1110 xxxx xxxx */
1374		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ef: 0110 0100 1110 1111 xxxx xxxx */
1375
1376		{&upd7810_device::SBI_ANM_xx, 3,20,11,L0\|L1}, /* f0: 0110 0100 1111 0000 xxxx xxxx */
1377		{&upd7810_device::SBI_SMH_xx, 3,20,11,L0\|L1}, /* f1: 0110 0100 1111 0001 xxxx xxxx */
1378		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* f2: 0110 0100 1111 0010 xxxx xxxx */
1379		{&upd7810_device::SBI_EOM_xx, 3,20,11,L0\|L1}, /* f3: 0110 0100 1111 0011 xxxx xxxx */
1380		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* f4: 0110 0100 1111 0100 xxxx xxxx */
1381		{&upd7810_device::SBI_TMM_xx, 3,20,11,L0\|L1}, /* f5: 0110 0100 1111 0101 xxxx xxxx */
1382		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* f6: 0110 0100 1111 0110 xxxx xxxx */
1383		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* f7: 0110 0100 1111 0111 xxxx xxxx */
1384		{&upd7810_device::EQI_ANM_xx, 3,20,11,L0\|L1}, /* f8: 0110 0100 1111 1000 xxxx xxxx */
1385		{&upd7810_device::EQI_SMH_xx, 3,20,11,L0\|L1}, /* f9: 0110 0100 1111 1001 xxxx xxxx */
1386		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* fa: 0110 0100 1111 1010 xxxx xxxx */
1387		{&upd7810_device::EQI_EOM_xx, 3,20,11,L0\|L1}, /* fb: 0110 0100 1111 1011 xxxx xxxx */
1388		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* fc: 0110 0100 1111 1100 xxxx xxxx */
1389		{&upd7810_device::EQI_TMM_xx, 3,20,11,L0\|L1}, /* fd: 0110 0100 1111 1101 xxxx xxxx */
1390		{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* fe: 0110 0100 1111 1110 xxxx xxxx */
1391		{&upd7810_device::illegal2, 3,11,11,L0\|L1} /* ff: 0110 0100 1111 1111 xxxx xxxx */
1392		};
1393
1394		/* prefix 70 */
1395		const struct upd7810_device::opcode_s upd7810_device::s_op70[256] =
1396		{
1397		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 00: 0111 0000 0000 0000 */
1398		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 01: 0111 0000 0000 0001 */
1399		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 02: 0111 0000 0000 0010 */
1400		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 03: 0111 0000 0000 0011 */
1401		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 04: 0111 0000 0000 0100 */
1402		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 05: 0111 0000 0000 0101 */
1403		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 06: 0111 0000 0000 0110 */
1404		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 07: 0111 0000 0000 0111 */
1405		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 08: 0111 0000 0000 1000 */
1406		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 09: 0111 0000 0000 1001 */
1407		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0a: 0111 0000 0000 1010 */
1408		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0b: 0111 0000 0000 1011 */
1409		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0c: 0111 0000 0000 1100 */
1410		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0d: 0111 0000 0000 1101 */
1411		{&upd7810_device::SSPD_w, 4,20,20,L0\|L1}, /* 0e: 0111 0000 0000 1110 llll llll hhhh hhhh */
1412		{&upd7810_device::LSPD_w, 4,20,20,L0\|L1}, /* 0f: 0111 0000 0000 1111 llll llll hhhh hhhh */
1413
1414		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 10: 0111 0000 0001 0000 */
1415		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 11: 0111 0000 0001 0001 */
1416		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 12: 0111 0000 0001 0010 */
1417		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 13: 0111 0000 0001 0011 */
1418		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 14: 0111 0000 0001 0100 */
1419		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 15: 0111 0000 0001 0101 */
1420		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 16: 0111 0000 0001 0110 */
1421		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 17: 0111 0000 0001 0111 */
1422		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 18: 0111 0000 0001 1000 */
1423		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 19: 0111 0000 0001 1001 */
1424		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1a: 0111 0000 0001 1010 */
1425		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1b: 0111 0000 0001 1011 */
1426		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1c: 0111 0000 0001 1100 */
1427		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1d: 0111 0000 0001 1101 */
1428		{&upd7810_device::SBCD_w, 4,20,20,L0\|L1}, /* 1e: 0111 0000 0001 1110 llll llll hhhh hhhh */
1429		{&upd7810_device::LBCD_w, 4,20,20,L0\|L1}, /* 1f: 0111 0000 0001 1111 llll llll hhhh hhhh */
1430
1431		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 20: 0111 0000 0010 0000 */
1432		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 21: 0111 0000 0010 0001 */
1433		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 22: 0111 0000 0010 0010 */
1434		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 23: 0111 0000 0010 0011 */
1435		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 24: 0111 0000 0010 0100 */
1436		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 25: 0111 0000 0010 0101 */
1437		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 26: 0111 0000 0010 0110 */
1438		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 27: 0111 0000 0010 0111 */
1439		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 28: 0111 0000 0010 1000 */
1440		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 29: 0111 0000 0010 1001 */
1441		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2a: 0111 0000 0010 1010 */
1442		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2b: 0111 0000 0010 1011 */
1443		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2c: 0111 0000 0010 1100 */
1444		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2d: 0111 0000 0010 1101 */
1445		{&upd7810_device::SDED_w, 4,20,20,L0\|L1}, /* 2e: 0111 0000 0010 1110 llll llll hhhh hhhh */
1446		{&upd7810_device::LDED_w, 4,20,20,L0\|L1}, /* 2f: 0111 0000 0010 1111 llll llll hhhh hhhh */
1447
1448		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 30: 0111 0000 0011 0000 */
1449		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 31: 0111 0000 0011 0001 */
1450		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 32: 0111 0000 0011 0010 */
1451		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 33: 0111 0000 0011 0011 */
1452		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 34: 0111 0000 0011 0100 */
1453		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 35: 0111 0000 0011 0101 */
1454		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 36: 0111 0000 0011 0110 */
1455		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 37: 0111 0000 0011 0111 */
1456		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 38: 0111 0000 0011 1000 */
1457		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 39: 0111 0000 0011 1001 */
1458		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3a: 0111 0000 0011 1010 */
1459		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3b: 0111 0000 0011 1011 */
1460		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3c: 0111 0000 0011 1100 */
1461		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3d: 0111 0000 0011 1101 */
1462		{&upd7810_device::SHLD_w, 4,20,20,L0\|L1}, /* 3e: 0111 0000 0011 1110 llll llll hhhh hhhh */
1463		{&upd7810_device::LHLD_w, 4,20,20,L0\|L1}, /* 3f: 0111 0000 0011 1111 llll llll hhhh hhhh */
1464
1465		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 40: 0111 0000 0100 0000 */
1466		{&upd7810_device::EADD_EA_A, 2,11,11,L0\|L1}, /* 41: 0111 0000 0100 0001 */
1467		{&upd7810_device::EADD_EA_B, 2,11,11,L0\|L1}, /* 42: 0111 0000 0100 0010 */
1468		{&upd7810_device::EADD_EA_C, 2,11,11,L0\|L1}, /* 43: 0111 0000 0100 0011 */
1469		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 44: 0111 0000 0100 0100 */
1470		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 45: 0111 0000 0100 0101 */
1471		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 46: 0111 0000 0100 0110 */
1472		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 47: 0111 0000 0100 0111 */
1473		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 48: 0111 0000 0100 1000 */
1474		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 49: 0111 0000 0100 1001 */
1475		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4a: 0111 0000 0100 1010 */
1476		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4b: 0111 0000 0100 1011 */
1477		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4c: 0111 0000 0100 1100 */
1478		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4d: 0111 0000 0100 1101 */
1479		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4e: 0111 0000 0100 1110 */
1480		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4f: 0111 0000 0100 1111 */
1481
1482		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 50: 0111 0000 0101 0000 */
1483		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 51: 0111 0000 0101 0001 */
1484		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 52: 0111 0000 0101 0010 */
1485		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 53: 0111 0000 0101 0011 */
1486		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 54: 0111 0000 0101 0100 */
1487		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 55: 0111 0000 0101 0101 */
1488		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 56: 0111 0000 0101 0110 */
1489		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 57: 0111 0000 0101 0111 */
1490		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 58: 0111 0000 0101 1000 */
1491		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 59: 0111 0000 0101 1001 */
1492		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5a: 0111 0000 0101 1010 */
1493		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5b: 0111 0000 0101 1011 */
1494		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5c: 0111 0000 0101 1100 */
1495		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5d: 0111 0000 0101 1101 */
1496		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5e: 0111 0000 0101 1110 */
1497		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5f: 0111 0000 0101 1111 */
1498
1499		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 60: 0111 0000 0110 0000 */
1500		{&upd7810_device::ESUB_EA_A, 2,11,11,L0\|L1}, /* 61: 0111 0000 0110 0001 */
1501		{&upd7810_device::ESUB_EA_B, 2,11,11,L0\|L1}, /* 62: 0111 0000 0110 0010 */
1502		{&upd7810_device::ESUB_EA_C, 2,11,11,L0\|L1}, /* 63: 0111 0000 0110 0011 */
1503		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 64: 0111 0000 0110 0100 */
1504		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 65: 0111 0000 0110 0101 */
1505		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 66: 0111 0000 0110 0110 */
1506		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 67: 0111 0000 0110 0111 */
1507		{&upd7810_device::MOV_V_w, 4,17,17,L0\|L1}, /* 68: 0111 0000 0110 1000 llll llll hhhh hhhh */
1508		{&upd7810_device::MOV_A_w, 4,17,17,L0\|L1}, /* 69: 0111 0000 0110 1001 llll llll hhhh hhhh */
1509		{&upd7810_device::MOV_B_w, 4,17,17,L0\|L1}, /* 6a: 0111 0000 0110 1010 llll llll hhhh hhhh */
1510		{&upd7810_device::MOV_C_w, 4,17,17,L0\|L1}, /* 6b: 0111 0000 0110 1011 llll llll hhhh hhhh */
1511		{&upd7810_device::MOV_D_w, 4,17,17,L0\|L1}, /* 6c: 0111 0000 0110 1100 llll llll hhhh hhhh */
1512		{&upd7810_device::MOV_E_w, 4,17,17,L0\|L1}, /* 6d: 0111 0000 0110 1101 llll llll hhhh hhhh */
1513		{&upd7810_device::MOV_H_w, 4,17,17,L0\|L1}, /* 6e: 0111 0000 0110 1110 llll llll hhhh hhhh */
1514		{&upd7810_device::MOV_L_w, 4,17,17,L0\|L1}, /* 6f: 0111 0000 0110 1111 llll llll hhhh hhhh */
1515
1516		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 70: 0111 0000 0111 0000 */
1517		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 71: 0111 0000 0111 0001 */
1518		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 72: 0111 0000 0111 0010 */
1519		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 73: 0111 0000 0111 0011 */
1520		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 74: 0111 0000 0111 0100 */
1521		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 75: 0111 0000 0111 0101 */
1522		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 76: 0111 0000 0111 0110 */
1523		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 77: 0111 0000 0111 0111 */
1524		{&upd7810_device::MOV_w_V, 4,17,17,L0\|L1}, /* 78: 0111 0000 0111 1000 llll llll hhhh hhhh */
1525		{&upd7810_device::MOV_w_A, 4,17,17,L0\|L1}, /* 79: 0111 0000 0111 1001 llll llll hhhh hhhh */
1526		{&upd7810_device::MOV_w_B, 4,17,17,L0\|L1}, /* 7a: 0111 0000 0111 1010 llll llll hhhh hhhh */
1527		{&upd7810_device::MOV_w_C, 4,17,17,L0\|L1}, /* 7b: 0111 0000 0111 1011 llll llll hhhh hhhh */
1528		{&upd7810_device::MOV_w_D, 4,17,17,L0\|L1}, /* 7c: 0111 0000 0111 1100 llll llll hhhh hhhh */
1529		{&upd7810_device::MOV_w_E, 4,17,17,L0\|L1}, /* 7d: 0111 0000 0111 1101 llll llll hhhh hhhh */
1530		{&upd7810_device::MOV_w_H, 4,17,17,L0\|L1}, /* 7e: 0111 0000 0111 1110 llll llll hhhh hhhh */
1531		{&upd7810_device::MOV_w_L, 4,17,17,L0\|L1}, /* 7f: 0111 0000 0111 1111 llll llll hhhh hhhh */
1532
1533		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 80: 0111 0000 1000 0000 */
1534		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 81: 0111 0000 1000 0001 */
1535		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 82: 0111 0000 1000 0010 */
1536		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 83: 0111 0000 1000 0011 */
1537		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 84: 0111 0000 1000 0100 */
1538		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 85: 0111 0000 1000 0101 */
1539		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 86: 0111 0000 1000 0110 */
1540		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 87: 0111 0000 1000 0111 */
1541		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 88: 0111 0000 1000 1000 */
1542		{&upd7810_device::ANAX_B, 2,11,11,L0\|L1}, /* 89: 0111 0000 1000 1001 */
1543		{&upd7810_device::ANAX_D, 2,11,11,L0\|L1}, /* 8a: 0111 0000 1000 1010 */
1544		{&upd7810_device::ANAX_H, 2,11,11,L0\|L1}, /* 8b: 0111 0000 1000 1011 */
1545		{&upd7810_device::ANAX_Dp, 2,11,11,L0\|L1}, /* 8c: 0111 0000 1000 1100 */
1546		{&upd7810_device::ANAX_Hp, 2,11,11,L0\|L1}, /* 8d: 0111 0000 1000 1101 */
1547		{&upd7810_device::ANAX_Dm, 2,11,11,L0\|L1}, /* 8e: 0111 0000 1000 1110 */
1548		{&upd7810_device::ANAX_Hm, 2,11,11,L0\|L1}, /* 8f: 0111 0000 1000 1111 */
1549
1550		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 90: 0111 0000 1001 0000 */
1551		{&upd7810_device::XRAX_B, 2,11,11,L0\|L1}, /* 91: 0111 0000 1001 0001 */
1552		{&upd7810_device::XRAX_D, 2,11,11,L0\|L1}, /* 92: 0111 0000 1001 0010 */
1553		{&upd7810_device::XRAX_H, 2,11,11,L0\|L1}, /* 93: 0111 0000 1001 0011 */
1554		{&upd7810_device::XRAX_Dp, 2,11,11,L0\|L1}, /* 94: 0111 0000 1001 0100 */
1555		{&upd7810_device::XRAX_Hp, 2,11,11,L0\|L1}, /* 95: 0111 0000 1001 0101 */
1556		{&upd7810_device::XRAX_Dm, 2,11,11,L0\|L1}, /* 96: 0111 0000 1001 0110 */
1557		{&upd7810_device::XRAX_Hm, 2,11,11,L0\|L1}, /* 97: 0111 0000 1001 0111 */
1558		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 98: 0111 0000 1001 1000 */
1559		// orax added, timings not verified
1560		{&upd7810_device::ORAX_B, 2,11, 8,L0\|L1}, /* 99: 0111 0000 1001 1001 */
1561		{&upd7810_device::ORAX_D, 2,11, 8,L0\|L1}, /* 9a: 0111 0000 1001 1010 */
1562		{&upd7810_device::ORAX_H, 2,11, 8,L0\|L1}, /* 9b: 0111 0000 1001 1011 */
1563		{&upd7810_device::ORAX_Dp, 2,11, 8,L0\|L1}, /* 9c: 0111 0000 1001 1100 */
1564		{&upd7810_device::ORAX_Hp, 2,11, 8,L0\|L1}, /* 9d: 0111 0000 1001 1101 */
1565		{&upd7810_device::ORAX_Dm, 2,11, 8,L0\|L1}, /* 9e: 0111 0000 1001 1110 */
1566		{&upd7810_device::ORAX_Hm, 2,11, 8,L0\|L1}, /* 9f: 0111 0000 1001 1111 */
1567
1568		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a0: 0111 0000 1010 0000 */
1569		{&upd7810_device::ADDNCX_B, 2,11, 8,L0\|L1}, /* a1: 0111 0000 1010 0001 */
1570		{&upd7810_device::ADDNCX_D, 2,11, 8,L0\|L1}, /* a2: 0111 0000 1010 0010 */
1571		{&upd7810_device::ADDNCX_H, 2,11, 8,L0\|L1}, /* a3: 0111 0000 1010 0011 */
1572		{&upd7810_device::ADDNCX_Dp, 2,11, 8,L0\|L1}, /* a4: 0111 0000 1010 0100 */
1573		{&upd7810_device::ADDNCX_Hp, 2,11, 8,L0\|L1}, /* a5: 0111 0000 1010 0101 */
1574		{&upd7810_device::ADDNCX_Dm, 2,11, 8,L0\|L1}, /* a6: 0111 0000 1010 0110 */
1575		{&upd7810_device::ADDNCX_Hm, 2,11, 8,L0\|L1}, /* a7: 0111 0000 1010 0111 */
1576		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a8: 0111 0000 1010 1000 */
1577		{&upd7810_device::GTAX_B, 2,11,11,L0\|L1}, /* a9: 0111 0000 1010 1001 */
1578		{&upd7810_device::GTAX_D, 2,11,11,L0\|L1}, /* aa: 0111 0000 1010 1010 */
1579		{&upd7810_device::GTAX_H, 2,11,11,L0\|L1}, /* ab: 0111 0000 1010 1011 */
1580		{&upd7810_device::GTAX_Dp, 2,11,11,L0\|L1}, /* ac: 0111 0000 1010 1100 */
1581		{&upd7810_device::GTAX_Hp, 2,11,11,L0\|L1}, /* ad: 0111 0000 1010 1101 */
1582		{&upd7810_device::GTAX_Dm, 2,11,11,L0\|L1}, /* ae: 0111 0000 1010 1110 */
1583		{&upd7810_device::GTAX_Hm, 2,11,11,L0\|L1}, /* af: 0111 0000 1010 1111 */
1584
1585		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b0: 0111 0000 1011 0000 */
1586		{&upd7810_device::SUBNBX_B, 2,11,11,L0\|L1}, /* b1: 0111 0000 1011 0001 */
1587		{&upd7810_device::SUBNBX_D, 2,11,11,L0\|L1}, /* b2: 0111 0000 1011 0010 */
1588		{&upd7810_device::SUBNBX_H, 2,11,11,L0\|L1}, /* b3: 0111 0000 1011 0011 */
1589		{&upd7810_device::SUBNBX_Dp, 2,11,11,L0\|L1}, /* b4: 0111 0000 1011 0100 */
1590		{&upd7810_device::SUBNBX_Hp, 2,11,11,L0\|L1}, /* b5: 0111 0000 1011 0101 */
1591		{&upd7810_device::SUBNBX_Dm, 2,11,11,L0\|L1}, /* b6: 0111 0000 1011 0110 */
1592		{&upd7810_device::SUBNBX_Hm, 2,11,11,L0\|L1}, /* b7: 0111 0000 1011 0111 */
1593		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b8: 0111 0000 1011 1000 */
1594		{&upd7810_device::LTAX_B, 2,11,11,L0\|L1}, /* b9: 0111 0000 1011 1001 */
1595		{&upd7810_device::LTAX_D, 2,11,11,L0\|L1}, /* ba: 0111 0000 1011 1010 */
1596		{&upd7810_device::LTAX_H, 2,11,11,L0\|L1}, /* bb: 0111 0000 1011 1011 */
1597		{&upd7810_device::LTAX_Dp, 2,11,11,L0\|L1}, /* bc: 0111 0000 1011 1100 */
1598		{&upd7810_device::LTAX_Hp, 2,11,11,L0\|L1}, /* bd: 0111 0000 1011 1101 */
1599		{&upd7810_device::LTAX_Dm, 2,11,11,L0\|L1}, /* be: 0111 0000 1011 1110 */
1600		{&upd7810_device::LTAX_Hm, 2,11,11,L0\|L1}, /* bf: 0111 0000 1011 1111 */
1601
1602		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c0: 0111 0000 1100 0000 */
1603		{&upd7810_device::ADDX_B, 2,11, 8,L0\|L1}, /* c1: 0111 0000 1100 0001 */
1604		{&upd7810_device::ADDX_D, 2,11, 8,L0\|L1}, /* c2: 0111 0000 1100 0010 */
1605		{&upd7810_device::ADDX_H, 2,11, 8,L0\|L1}, /* c3: 0111 0000 1100 0011 */
1606		{&upd7810_device::ADDX_Dp, 2,11, 8,L0\|L1}, /* c4: 0111 0000 1100 0100 */
1607		{&upd7810_device::ADDX_Hp, 2,11, 8,L0\|L1}, /* c5: 0111 0000 1100 0101 */
1608		{&upd7810_device::ADDX_Dm, 2,11, 8,L0\|L1}, /* c6: 0111 0000 1100 0110 */
1609		{&upd7810_device::ADDX_Hm, 2,11, 8,L0\|L1}, /* c7: 0111 0000 1100 0111 */
1610		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c8: 0111 0000 1100 1000 */
1611		{&upd7810_device::ONAX_B, 2,11, 8,L0\|L1}, /* c9: 0111 0000 1100 1001 */
1612		{&upd7810_device::ONAX_D, 2,11, 8,L0\|L1}, /* ca: 0111 0000 1100 1010 */
1613		{&upd7810_device::ONAX_H, 2,11, 8,L0\|L1}, /* cb: 0111 0000 1100 1011 */
1614		{&upd7810_device::ONAX_Dp, 2,11, 8,L0\|L1}, /* cc: 0111 0000 1100 1100 */
1615		{&upd7810_device::ONAX_Hp, 2,11, 8,L0\|L1}, /* cd: 0111 0000 1100 1101 */
1616		{&upd7810_device::ONAX_Dm, 2,11, 8,L0\|L1}, /* ce: 0111 0000 1100 1110 */
1617		{&upd7810_device::ONAX_Hm, 2,11, 8,L0\|L1}, /* cf: 0111 0000 1100 1111 */
1618
1619		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d0: 0111 0000 1101 0000 */
1620		{&upd7810_device::ADCX_B, 2,11, 8,L0\|L1}, /* d1: 0111 0000 1101 0001 */
1621		{&upd7810_device::ADCX_D, 2,11, 8,L0\|L1}, /* d2: 0111 0000 1101 0010 */
1622		{&upd7810_device::ADCX_H, 2,11, 8,L0\|L1}, /* d3: 0111 0000 1101 0011 */
1623		{&upd7810_device::ADCX_Dp, 2,11, 8,L0\|L1}, /* d4: 0111 0000 1101 0100 */
1624		{&upd7810_device::ADCX_Hp, 2,11, 8,L0\|L1}, /* d5: 0111 0000 1101 0101 */
1625		{&upd7810_device::ADCX_Dm, 2,11, 8,L0\|L1}, /* d6: 0111 0000 1101 0110 */
1626		{&upd7810_device::ADCX_Hm, 2,11, 8,L0\|L1}, /* d7: 0111 0000 1101 0111 */
1627		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d8: 0111 0000 1101 1000 */
1628		{&upd7810_device::OFFAX_B, 2,11, 8,L0\|L1}, /* d9: 0111 0000 1101 1001 */
1629		{&upd7810_device::OFFAX_D, 2,11, 8,L0\|L1}, /* da: 0111 0000 1101 1010 */
1630		{&upd7810_device::OFFAX_H, 2,11, 8,L0\|L1}, /* db: 0111 0000 1101 1011 */
1631		{&upd7810_device::OFFAX_Dp, 2,11, 8,L0\|L1}, /* dc: 0111 0000 1101 1100 */
1632		{&upd7810_device::OFFAX_Hp, 2,11, 8,L0\|L1}, /* dd: 0111 0000 1101 1101 */
1633		{&upd7810_device::OFFAX_Dm, 2,11, 8,L0\|L1}, /* de: 0111 0000 1101 1110 */
1634		{&upd7810_device::OFFAX_Hm, 2,11, 8,L0\|L1}, /* df: 0111 0000 1101 1111 */
1635
1636		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e0: 0111 0000 1110 0000 */
1637		{&upd7810_device::SUBX_B, 2,11,11,L0\|L1}, /* e1: 0111 0000 1110 0001 */
1638		{&upd7810_device::SUBX_D, 2,11,11,L0\|L1}, /* e2: 0111 0000 1110 0010 */
1639		{&upd7810_device::SUBX_H, 2,11,11,L0\|L1}, /* e3: 0111 0000 1110 0011 */
1640		{&upd7810_device::SUBX_Dp, 2,11,11,L0\|L1}, /* e4: 0111 0000 1110 0100 */
1641		{&upd7810_device::SUBX_Hp, 2,11,11,L0\|L1}, /* e5: 0111 0000 1110 0101 */
1642		{&upd7810_device::SUBX_Dm, 2,11,11,L0\|L1}, /* e6: 0111 0000 1110 0110 */
1643		{&upd7810_device::SUBX_Hm, 2,11,11,L0\|L1}, /* e7: 0111 0000 1110 0111 */
1644		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e8: 0111 0000 1110 1000 */
1645		{&upd7810_device::NEAX_B, 2,11,11,L0\|L1}, /* e9: 0111 0000 1110 1001 */
1646		{&upd7810_device::NEAX_D, 2,11,11,L0\|L1}, /* ea: 0111 0000 1110 1010 */
1647		{&upd7810_device::NEAX_H, 2,11,11,L0\|L1}, /* eb: 0111 0000 1110 1011 */
1648		{&upd7810_device::NEAX_Dp, 2,11,11,L0\|L1}, /* ec: 0111 0000 1110 1100 */
1649		{&upd7810_device::NEAX_Hp, 2,11,11,L0\|L1}, /* ed: 0111 0000 1110 1101 */
1650		{&upd7810_device::NEAX_Dm, 2,11,11,L0\|L1}, /* ee: 0111 0000 1110 1110 */
1651		{&upd7810_device::NEAX_Hm, 2,11,11,L0\|L1}, /* ef: 0111 0000 1110 1111 */
1652
1653		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f0: 0111 0000 1111 0000 */
1654		{&upd7810_device::SBBX_B, 2,11,11,L0\|L1}, /* f1: 0111 0000 1111 0001 */
1655		{&upd7810_device::SBBX_D, 2,11,11,L0\|L1}, /* f2: 0111 0000 1111 0010 */
1656		{&upd7810_device::SBBX_H, 2,11,11,L0\|L1}, /* f3: 0111 0000 1111 0011 */
1657		{&upd7810_device::SBBX_Dp, 2,11,11,L0\|L1}, /* f4: 0111 0000 1111 0100 */
1658		{&upd7810_device::SBBX_Hp, 2,11,11,L0\|L1}, /* f5: 0111 0000 1111 0101 */
1659		{&upd7810_device::SBBX_Dm, 2,11,11,L0\|L1}, /* f6: 0111 0000 1111 0110 */
1660		{&upd7810_device::SBBX_Hm, 2,11,11,L0\|L1}, /* f7: 0111 0000 1111 0111 */
1661		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f8: 0111 0000 1111 1000 */
1662		{&upd7810_device::EQAX_B, 2,11,11,L0\|L1}, /* f9: 0111 0000 1111 1001 */
1663		{&upd7810_device::EQAX_D, 2,11,11,L0\|L1}, /* fa: 0111 0000 1111 1010 */
1664		{&upd7810_device::EQAX_H, 2,11,11,L0\|L1}, /* fb: 0111 0000 1111 1011 */
1665		{&upd7810_device::EQAX_Dp, 2,11,11,L0\|L1}, /* fc: 0111 0000 1111 1100 */
1666		{&upd7810_device::EQAX_Hp, 2,11,11,L0\|L1}, /* fd: 0111 0000 1111 1101 */
1667		{&upd7810_device::EQAX_Dm, 2,11,11,L0\|L1}, /* fe: 0111 0000 1111 1110 */
1668		{&upd7810_device::EQAX_Hm, 2,11,11,L0\|L1} /* ff: 0111 0000 1111 1111 */
1669		};
1670
1671		/* prefix 74 */
1672		const struct upd7810_device::opcode_s upd7810_device::s_op74[256] =
1673		{
1674		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 00: 0111 0100 0000 0000 */
1675		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 01: 0111 0100 0000 0001 */
1676		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 02: 0111 0100 0000 0010 */
1677		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 03: 0111 0100 0000 0011 */
1678		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 04: 0111 0100 0000 0100 */
1679		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 05: 0111 0100 0000 0101 */
1680		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 06: 0111 0100 0000 0110 */
1681		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 07: 0111 0100 0000 0111 */
1682		{&upd7810_device::ANI_V_xx, 3,11,11,L0\|L1}, /* 08: 0111 0100 0000 1000 xxxx xxxx */
1683		{&upd7810_device::ANI_A_xx, 3,11,11,L0\|L1}, /* 09: 0111 0100 0000 1001 xxxx xxxx */
1684		{&upd7810_device::ANI_B_xx, 3,11,11,L0\|L1}, /* 0a: 0111 0100 0000 1010 xxxx xxxx */
1685		{&upd7810_device::ANI_C_xx, 3,11,11,L0\|L1}, /* 0b: 0111 0100 0000 1011 xxxx xxxx */
1686		{&upd7810_device::ANI_D_xx, 3,11,11,L0\|L1}, /* 0c: 0111 0100 0000 1100 xxxx xxxx */
1687		{&upd7810_device::ANI_E_xx, 3,11,11,L0\|L1}, /* 0d: 0111 0100 0000 1101 xxxx xxxx */
1688		{&upd7810_device::ANI_H_xx, 3,11,11,L0\|L1}, /* 0e: 0111 0100 0000 1110 xxxx xxxx */
1689		{&upd7810_device::ANI_L_xx, 3,11,11,L0\|L1}, /* 0f: 0111 0100 0000 1111 xxxx xxxx */
1690
1691		{&upd7810_device::XRI_V_xx, 3,11,11,L0\|L1}, /* 10: 0111 0100 0001 0000 xxxx xxxx */
1692		{&upd7810_device::XRI_A_xx, 3,11,11,L0\|L1}, /* 11: 0111 0100 0001 0001 xxxx xxxx */
1693		{&upd7810_device::XRI_B_xx, 3,11,11,L0\|L1}, /* 12: 0111 0100 0001 0010 xxxx xxxx */
1694		{&upd7810_device::XRI_C_xx, 3,11,11,L0\|L1}, /* 13: 0111 0100 0001 0011 xxxx xxxx */
1695		{&upd7810_device::XRI_D_xx, 3,11,11,L0\|L1}, /* 14: 0111 0100 0001 0100 xxxx xxxx */
1696		{&upd7810_device::XRI_E_xx, 3,11,11,L0\|L1}, /* 15: 0111 0100 0001 0101 xxxx xxxx */
1697		{&upd7810_device::XRI_H_xx, 3,11,11,L0\|L1}, /* 16: 0111 0100 0001 0110 xxxx xxxx */
1698		{&upd7810_device::XRI_L_xx, 3,11,11,L0\|L1}, /* 17: 0111 0100 0001 0111 xxxx xxxx */
1699		{&upd7810_device::ORI_V_xx, 3,11,11,L0\|L1}, /* 18: 0111 0100 0001 1000 xxxx xxxx */
1700		{&upd7810_device::ORI_A_xx, 3,11,11,L0\|L1}, /* 19: 0111 0100 0001 1001 xxxx xxxx */
1701		{&upd7810_device::ORI_B_xx, 3,11,11,L0\|L1}, /* 1a: 0111 0100 0001 1010 xxxx xxxx */
1702		{&upd7810_device::ORI_C_xx, 3,11,11,L0\|L1}, /* 1b: 0111 0100 0001 1011 xxxx xxxx */
1703		{&upd7810_device::ORI_D_xx, 3,11,11,L0\|L1}, /* 1c: 0111 0100 0001 1100 xxxx xxxx */
1704		{&upd7810_device::ORI_E_xx, 3,11,11,L0\|L1}, /* 1d: 0111 0100 0001 1101 xxxx xxxx */
1705		{&upd7810_device::ORI_H_xx, 3,11,11,L0\|L1}, /* 1e: 0111 0100 0001 1110 xxxx xxxx */
1706		{&upd7810_device::ORI_L_xx, 3,11,11,L0\|L1}, /* 1f: 0111 0100 0001 1111 xxxx xxxx */
1707
1708		{&upd7810_device::ADINC_V_xx, 3,11,11,L0\|L1}, /* 20: 0111 0100 0010 0000 xxxx xxxx */
1709		{&upd7810_device::ADINC_A_xx, 3,11,11,L0\|L1}, /* 21: 0111 0100 0010 0001 xxxx xxxx */
1710		{&upd7810_device::ADINC_B_xx, 3,11,11,L0\|L1}, /* 22: 0111 0100 0010 0010 xxxx xxxx */
1711		{&upd7810_device::ADINC_C_xx, 3,11,11,L0\|L1}, /* 23: 0111 0100 0010 0011 xxxx xxxx */
1712		{&upd7810_device::ADINC_D_xx, 3,11,11,L0\|L1}, /* 24: 0111 0100 0010 0100 xxxx xxxx */
1713		{&upd7810_device::ADINC_E_xx, 3,11,11,L0\|L1}, /* 25: 0111 0100 0010 0101 xxxx xxxx */
1714		{&upd7810_device::ADINC_H_xx, 3,11,11,L0\|L1}, /* 26: 0111 0100 0010 0110 xxxx xxxx */
1715		{&upd7810_device::ADINC_L_xx, 3,11,11,L0\|L1}, /* 27: 0111 0100 0010 0111 xxxx xxxx */
1716		{&upd7810_device::GTI_V_xx, 3,11,11,L0\|L1}, /* 28: 0111 0100 0010 1000 xxxx xxxx */
1717		{&upd7810_device::GTI_A_xx, 3,11,11,L0\|L1}, /* 29: 0111 0100 0010 1001 xxxx xxxx */
1718		{&upd7810_device::GTI_B_xx, 3,11,11,L0\|L1}, /* 2a: 0111 0100 0010 1010 xxxx xxxx */
1719		{&upd7810_device::GTI_C_xx, 3,11,11,L0\|L1}, /* 2b: 0111 0100 0010 1011 xxxx xxxx */
1720		{&upd7810_device::GTI_D_xx, 3,11,11,L0\|L1}, /* 2c: 0111 0100 0010 1100 xxxx xxxx */
1721		{&upd7810_device::GTI_E_xx, 3,11,11,L0\|L1}, /* 2d: 0111 0100 0010 1101 xxxx xxxx */
1722		{&upd7810_device::GTI_H_xx, 3,11,11,L0\|L1}, /* 2e: 0111 0100 0010 1110 xxxx xxxx */
1723		{&upd7810_device::GTI_L_xx, 3,11,11,L0\|L1}, /* 2f: 0111 0100 0010 1111 xxxx xxxx */
1724
1725		{&upd7810_device::SUINB_V_xx, 3,11,11,L0\|L1}, /* 30: 0111 0100 0011 0000 xxxx xxxx */
1726		{&upd7810_device::SUINB_A_xx, 3,11,11,L0\|L1}, /* 31: 0111 0100 0011 0001 xxxx xxxx */
1727		{&upd7810_device::SUINB_B_xx, 3,11,11,L0\|L1}, /* 32: 0111 0100 0011 0010 xxxx xxxx */
1728		{&upd7810_device::SUINB_C_xx, 3,11,11,L0\|L1}, /* 33: 0111 0100 0011 0011 xxxx xxxx */
1729		{&upd7810_device::SUINB_D_xx, 3,11,11,L0\|L1}, /* 34: 0111 0100 0011 0100 xxxx xxxx */
1730		{&upd7810_device::SUINB_E_xx, 3,11,11,L0\|L1}, /* 35: 0111 0100 0011 0101 xxxx xxxx */
1731		{&upd7810_device::SUINB_H_xx, 3,11,11,L0\|L1}, /* 36: 0111 0100 0011 0110 xxxx xxxx */
1732		{&upd7810_device::SUINB_L_xx, 3,11,11,L0\|L1}, /* 37: 0111 0100 0011 0111 xxxx xxxx */
1733		{&upd7810_device::LTI_V_xx, 3,11,11,L0\|L1}, /* 38: 0111 0100 0011 1000 xxxx xxxx */
1734		{&upd7810_device::LTI_A_xx, 3,11,11,L0\|L1}, /* 39: 0111 0100 0011 1001 xxxx xxxx */
1735		{&upd7810_device::LTI_B_xx, 3,11,11,L0\|L1}, /* 3a: 0111 0100 0011 1010 xxxx xxxx */
1736		{&upd7810_device::LTI_C_xx, 3,11,11,L0\|L1}, /* 3b: 0111 0100 0011 1011 xxxx xxxx */
1737		{&upd7810_device::LTI_D_xx, 3,11,11,L0\|L1}, /* 3c: 0111 0100 0011 1100 xxxx xxxx */
1738		{&upd7810_device::LTI_E_xx, 3,11,11,L0\|L1}, /* 3d: 0111 0100 0011 1101 xxxx xxxx */
1739		{&upd7810_device::LTI_H_xx, 3,11,11,L0\|L1}, /* 3e: 0111 0100 0011 1110 xxxx xxxx */
1740		{&upd7810_device::LTI_L_xx, 3,11,11,L0\|L1}, /* 3f: 0111 0100 0011 1111 xxxx xxxx */
1741
1742		{&upd7810_device::ADI_V_xx, 3,11,11,L0\|L1}, /* 40: 0111 0100 0100 0000 xxxx xxxx */
1743		{&upd7810_device::ADI_A_xx, 3,11,11,L0\|L1}, /* 41: 0111 0100 0100 0001 xxxx xxxx */
1744		{&upd7810_device::ADI_B_xx, 3,11,11,L0\|L1}, /* 42: 0111 0100 0100 0010 xxxx xxxx */
1745		{&upd7810_device::ADI_C_xx, 3,11,11,L0\|L1}, /* 43: 0111 0100 0100 0011 xxxx xxxx */
1746		{&upd7810_device::ADI_D_xx, 3,11,11,L0\|L1}, /* 44: 0111 0100 0100 0100 xxxx xxxx */
1747		{&upd7810_device::ADI_E_xx, 3,11,11,L0\|L1}, /* 45: 0111 0100 0100 0101 xxxx xxxx */
1748		{&upd7810_device::ADI_H_xx, 3,11,11,L0\|L1}, /* 46: 0111 0100 0100 0110 xxxx xxxx */
1749		{&upd7810_device::ADI_L_xx, 3,11,11,L0\|L1}, /* 47: 0111 0100 0100 0111 xxxx xxxx */
1750		{&upd7810_device::ONI_V_xx, 3,11,11,L0\|L1}, /* 48: 0111 0100 0100 1000 xxxx xxxx */
1751		{&upd7810_device::ONI_A_xx, 3,11,11,L0\|L1}, /* 49: 0111 0100 0100 1001 xxxx xxxx */
1752		{&upd7810_device::ONI_B_xx, 3,11,11,L0\|L1}, /* 4a: 0111 0100 0100 1010 xxxx xxxx */
1753		{&upd7810_device::ONI_C_xx, 3,11,11,L0\|L1}, /* 4b: 0111 0100 0100 1011 xxxx xxxx */
1754		{&upd7810_device::ONI_D_xx, 3,11,11,L0\|L1}, /* 4c: 0111 0100 0100 1100 xxxx xxxx */
1755		{&upd7810_device::ONI_E_xx, 3,11,11,L0\|L1}, /* 4d: 0111 0100 0100 1101 xxxx xxxx */
1756		{&upd7810_device::ONI_H_xx, 3,11,11,L0\|L1}, /* 4e: 0111 0100 0100 1110 xxxx xxxx */
1757		{&upd7810_device::ONI_L_xx, 3,11,11,L0\|L1}, /* 4f: 0111 0100 0100 1111 xxxx xxxx */
1758
1759		{&upd7810_device::ACI_V_xx, 3,11,11,L0\|L1}, /* 50: 0111 0100 0101 0000 xxxx xxxx */
1760		{&upd7810_device::ACI_A_xx, 3,11,11,L0\|L1}, /* 51: 0111 0100 0101 0001 xxxx xxxx */
1761		{&upd7810_device::ACI_B_xx, 3,11,11,L0\|L1}, /* 52: 0111 0100 0101 0010 xxxx xxxx */
1762		{&upd7810_device::ACI_C_xx, 3,11,11,L0\|L1}, /* 53: 0111 0100 0101 0011 xxxx xxxx */
1763		{&upd7810_device::ACI_D_xx, 3,11,11,L0\|L1}, /* 54: 0111 0100 0101 0100 xxxx xxxx */
1764		{&upd7810_device::ACI_E_xx, 3,11,11,L0\|L1}, /* 55: 0111 0100 0101 0101 xxxx xxxx */
1765		{&upd7810_device::ACI_H_xx, 3,11,11,L0\|L1}, /* 56: 0111 0100 0101 0110 xxxx xxxx */
1766		{&upd7810_device::ACI_L_xx, 3,11,11,L0\|L1}, /* 57: 0111 0100 0101 0111 xxxx xxxx */
1767		{&upd7810_device::OFFI_V_xx, 3,11,11,L0\|L1}, /* 58: 0111 0100 0101 1000 xxxx xxxx */
1768		{&upd7810_device::OFFI_A_xx, 3,11,11,L0\|L1}, /* 59: 0111 0100 0101 1001 xxxx xxxx */
1769		{&upd7810_device::OFFI_B_xx, 3,11,11,L0\|L1}, /* 5a: 0111 0100 0101 1010 xxxx xxxx */
1770		{&upd7810_device::OFFI_C_xx, 3,11,11,L0\|L1}, /* 5b: 0111 0100 0101 1011 xxxx xxxx */
1771		{&upd7810_device::OFFI_D_xx, 3,11,11,L0\|L1}, /* 5c: 0111 0100 0101 1100 xxxx xxxx */
1772		{&upd7810_device::OFFI_E_xx, 3,11,11,L0\|L1}, /* 5d: 0111 0100 0101 1101 xxxx xxxx */
1773		{&upd7810_device::OFFI_H_xx, 3,11,11,L0\|L1}, /* 5e: 0111 0100 0101 1110 xxxx xxxx */
1774		{&upd7810_device::OFFI_L_xx, 3,11,11,L0\|L1}, /* 5f: 0111 0100 0101 1111 xxxx xxxx */
1775
1776		{&upd7810_device::SUI_V_xx, 3,11,11,L0\|L1}, /* 60: 0111 0100 0110 0000 xxxx xxxx */
1777		{&upd7810_device::SUI_A_xx, 3,11,11,L0\|L1}, /* 61: 0111 0100 0110 0001 xxxx xxxx */
1778		{&upd7810_device::SUI_B_xx, 3,11,11,L0\|L1}, /* 62: 0111 0100 0110 0010 xxxx xxxx */
1779		{&upd7810_device::SUI_C_xx, 3,11,11,L0\|L1}, /* 63: 0111 0100 0110 0011 xxxx xxxx */
1780		{&upd7810_device::SUI_D_xx, 3,11,11,L0\|L1}, /* 64: 0111 0100 0110 0100 xxxx xxxx */
1781		{&upd7810_device::SUI_E_xx, 3,11,11,L0\|L1}, /* 65: 0111 0100 0110 0101 xxxx xxxx */
1782		{&upd7810_device::SUI_H_xx, 3,11,11,L0\|L1}, /* 66: 0111 0100 0110 0110 xxxx xxxx */
1783		{&upd7810_device::SUI_L_xx, 3,11,11,L0\|L1}, /* 67: 0111 0100 0110 0111 xxxx xxxx */
1784		{&upd7810_device::NEI_V_xx, 3,11,11,L0\|L1}, /* 68: 0111 0100 0110 1000 xxxx xxxx */
1785		{&upd7810_device::NEI_A_xx, 3,11,11,L0\|L1}, /* 69: 0111 0100 0110 1001 xxxx xxxx */
1786		{&upd7810_device::NEI_B_xx, 3,11,11,L0\|L1}, /* 6a: 0111 0100 0110 1010 xxxx xxxx */
1787		{&upd7810_device::NEI_C_xx, 3,11,11,L0\|L1}, /* 6b: 0111 0100 0110 1011 xxxx xxxx */
1788		{&upd7810_device::NEI_D_xx, 3,11,11,L0\|L1}, /* 6c: 0111 0100 0110 1100 xxxx xxxx */
1789		{&upd7810_device::NEI_E_xx, 3,11,11,L0\|L1}, /* 6d: 0111 0100 0110 1101 xxxx xxxx */
1790		{&upd7810_device::NEI_H_xx, 3,11,11,L0\|L1}, /* 6e: 0111 0100 0110 1110 xxxx xxxx */
1791		{&upd7810_device::NEI_L_xx, 3,11,11,L0\|L1}, /* 6f: 0111 0100 0110 1111 xxxx xxxx */
1792
1793		{&upd7810_device::SBI_V_xx, 3,11,11,L0\|L1}, /* 70: 0111 0100 0111 0000 xxxx xxxx */
1794		{&upd7810_device::SBI_A_xx, 3,11,11,L0\|L1}, /* 71: 0111 0100 0111 0001 xxxx xxxx */
1795		{&upd7810_device::SBI_B_xx, 3,11,11,L0\|L1}, /* 72: 0111 0100 0111 0010 xxxx xxxx */
1796		{&upd7810_device::SBI_C_xx, 3,11,11,L0\|L1}, /* 73: 0111 0100 0111 0011 xxxx xxxx */
1797		{&upd7810_device::SBI_D_xx, 3,11,11,L0\|L1}, /* 74: 0111 0100 0111 0100 xxxx xxxx */
1798		{&upd7810_device::SBI_E_xx, 3,11,11,L0\|L1}, /* 75: 0111 0100 0111 0101 xxxx xxxx */
1799		{&upd7810_device::SBI_H_xx, 3,11,11,L0\|L1}, /* 76: 0111 0100 0111 0110 xxxx xxxx */
1800		{&upd7810_device::SBI_L_xx, 3,11,11,L0\|L1}, /* 77: 0111 0100 0111 0111 xxxx xxxx */
1801		{&upd7810_device::EQI_V_xx, 3,11,11,L0\|L1}, /* 78: 0111 0100 0111 1000 xxxx xxxx */
1802		{&upd7810_device::EQI_A_xx, 3,11,11,L0\|L1}, /* 79: 0111 0100 0111 1001 xxxx xxxx */
1803		{&upd7810_device::EQI_B_xx, 3,11,11,L0\|L1}, /* 7a: 0111 0100 0111 1010 xxxx xxxx */
1804		{&upd7810_device::EQI_C_xx, 3,11,11,L0\|L1}, /* 7b: 0111 0100 0111 1011 xxxx xxxx */
1805		{&upd7810_device::EQI_D_xx, 3,11,11,L0\|L1}, /* 7c: 0111 0100 0111 1100 xxxx xxxx */
1806		{&upd7810_device::EQI_E_xx, 3,11,11,L0\|L1}, /* 7d: 0111 0100 0111 1101 xxxx xxxx */
1807		{&upd7810_device::EQI_H_xx, 3,11,11,L0\|L1}, /* 7e: 0111 0100 0111 1110 xxxx xxxx */
1808		{&upd7810_device::EQI_L_xx, 3,11,11,L0\|L1}, /* 7f: 0111 0100 0111 1111 xxxx xxxx */
1809
1810		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 80: 0111 0100 1000 0000 */
1811		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 81: 0111 0100 1000 0001 */
1812		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 82: 0111 0100 1000 0010 */
1813		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 83: 0111 0100 1000 0011 */
1814		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 84: 0111 0100 1000 0100 */
1815		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 85: 0111 0100 1000 0101 */
1816		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 86: 0111 0100 1000 0110 */
1817		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 87: 0111 0100 1000 0111 */
1818		{&upd7810_device::ANAW_wa, 3,14,11,L0\|L1}, /* 88: 0111 0100 1000 1000 oooo oooo */
1819		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 89: 0111 0100 1000 1001 */
1820		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8a: 0111 0100 1000 1010 */
1821		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8b: 0111 0100 1000 1011 */
1822		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8c: 0111 0100 1000 1100 */
1823		{&upd7810_device::DAN_EA_BC, 2,11,11,L0\|L1}, /* 8d: 0111 0100 1000 1101 */
1824		{&upd7810_device::DAN_EA_DE, 2,11,11,L0\|L1}, /* 8e: 0111 0100 1000 1110 */
1825		{&upd7810_device::DAN_EA_HL, 2,11,11,L0\|L1}, /* 8f: 0111 0100 1000 1111 */
1826
1827		{&upd7810_device::XRAW_wa, 3,14,11,L0\|L1}, /* 90: 0111 0100 1001 0000 oooo oooo */
1828		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 91: 0111 0100 1001 0001 */
1829		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 92: 0111 0100 1001 0010 */
1830		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 93: 0111 0100 1001 0011 */
1831		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 94: 0111 0100 1001 0100 */
1832		{&upd7810_device::DXR_EA_BC, 2,11,11,L0\|L1}, /* 95: 0111 0100 1001 0101 */
1833		{&upd7810_device::DXR_EA_DE, 2,11,11,L0\|L1}, /* 96: 0111 0100 1001 0110 */
1834		{&upd7810_device::DXR_EA_HL, 2,11,11,L0\|L1}, /* 97: 0111 0100 1001 0111 */
1835		{&upd7810_device::ORAW_wa, 3,14,11,L0\|L1}, /* 98: 0111 0100 1001 1000 oooo oooo */
1836		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 99: 0111 0100 1001 1001 */
1837		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9a: 0111 0100 1001 1010 */
1838		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9b: 0111 0100 1001 1011 */
1839		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9c: 0111 0100 1001 1100 */
1840		{&upd7810_device::DOR_EA_BC, 2,11,11,L0\|L1}, /* 9d: 0111 0100 1001 1101 */
1841		{&upd7810_device::DOR_EA_DE, 2,11,11,L0\|L1}, /* 9e: 0111 0100 1001 1110 */
1842		{&upd7810_device::DOR_EA_HL, 2,11,11,L0\|L1}, /* 9f: 0111 0100 1001 1111 */
1843
1844		{&upd7810_device::ADDNCW_wa, 3,14,11,L0\|L1}, /* a0: 0111 0100 1010 0000 oooo oooo */
1845		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a1: 0111 0100 1010 0001 */
1846		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a2: 0111 0100 1010 0010 */
1847		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a3: 0111 0100 1010 0011 */
1848		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a4: 0111 0100 1010 0100 */
1849		{&upd7810_device::DADDNC_EA_BC, 2,11,11,L0\|L1}, /* a5: 0111 0100 1010 0101 */
1850		{&upd7810_device::DADDNC_EA_DE, 2,11,11,L0\|L1}, /* a6: 0111 0100 1010 0110 */
1851		{&upd7810_device::DADDNC_EA_HL, 2,11,11,L0\|L1}, /* a7: 0111 0100 1010 0111 */
1852		{&upd7810_device::GTAW_wa, 3,14,11,L0\|L1}, /* a8: 0111 0100 1010 1000 oooo oooo */
1853		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a9: 0111 0100 1010 1001 */
1854		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* aa: 0111 0100 1010 1010 */
1855		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ab: 0111 0100 1010 1011 */
1856		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ac: 0111 0100 1010 1100 */
1857		{&upd7810_device::DGT_EA_BC, 2,11,11,L0\|L1}, /* ad: 0111 0100 1010 1101 */
1858		{&upd7810_device::DGT_EA_DE, 2,11,11,L0\|L1}, /* ae: 0111 0100 1010 1110 */
1859		{&upd7810_device::DGT_EA_HL, 2,11,11,L0\|L1}, /* af: 0111 0100 1010 1111 */
1860
1861		{&upd7810_device::SUBNBW_wa, 3,14,11,L0\|L1}, /* b0: 0111 0100 1011 0000 oooo oooo */
1862		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b1: 0111 0100 1011 0001 */
1863		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b2: 0111 0100 1011 0010 */
1864		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b3: 0111 0100 1011 0011 */
1865		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b4: 0111 0100 1011 0100 */
1866		{&upd7810_device::DSUBNB_EA_BC, 2,11,11,L0\|L1}, /* b5: 0111 0100 1011 0101 */
1867		{&upd7810_device::DSUBNB_EA_DE, 2,11,11,L0\|L1}, /* b6: 0111 0100 1011 0110 */
1868		{&upd7810_device::DSUBNB_EA_HL, 2,11,11,L0\|L1}, /* b7: 0111 0100 1011 0111 */
1869		{&upd7810_device::LTAW_wa, 3,14,11,L0\|L1}, /* b8: 0111 0100 1011 1000 oooo oooo */
1870		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b9: 0111 0100 1011 1001 */
1871		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ba: 0111 0100 1011 1010 */
1872		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bb: 0111 0100 1011 1011 */
1873		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bc: 0111 0100 1011 1100 */
1874		{&upd7810_device::DLT_EA_BC, 2,11,11,L0\|L1}, /* bd: 0111 0100 1011 1101 */
1875		{&upd7810_device::DLT_EA_DE, 2,11,11,L0\|L1}, /* be: 0111 0100 1011 1110 */
1876		{&upd7810_device::DLT_EA_HL, 2,11,11,L0\|L1}, /* bf: 0111 0100 1011 1111 */
1877
1878		{&upd7810_device::ADDW_wa, 3,14,11,L0\|L1}, /* c0: 0111 0100 1100 0000 oooo oooo */
1879		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c1: 0111 0100 1100 0001 */
1880		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c2: 0111 0100 1100 0010 */
1881		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c3: 0111 0100 1100 0011 */
1882		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c4: 0111 0100 1100 0100 */
1883		{&upd7810_device::DADD_EA_BC, 2,11,11,L0\|L1}, /* c5: 0111 0100 1100 0101 */
1884		{&upd7810_device::DADD_EA_DE, 2,11,11,L0\|L1}, /* c6: 0111 0100 1100 0110 */
1885		{&upd7810_device::DADD_EA_HL, 2,11,11,L0\|L1}, /* c7: 0111 0100 1100 0111 */
1886		{&upd7810_device::ONAW_wa, 3,14,11,L0\|L1}, /* c8: 0111 0100 1100 1000 oooo oooo */
1887		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c9: 0111 0100 1100 1001 */
1888		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ca: 0111 0100 1100 1010 */
1889		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* cb: 0111 0100 1100 1011 */
1890		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* cc: 0111 0100 1100 1100 */
1891		{&upd7810_device::DON_EA_BC, 2,11,11,L0\|L1}, /* cd: 0111 0100 1100 1101 */
1892		{&upd7810_device::DON_EA_DE, 2,11,11,L0\|L1}, /* ce: 0111 0100 1100 1110 */
1893		{&upd7810_device::DON_EA_HL, 2,11,11,L0\|L1}, /* cf: 0111 0100 1100 1111 */
1894
1895		{&upd7810_device::ADCW_wa, 3,14,11,L0\|L1}, /* d0: 0111 0100 1101 0000 oooo oooo */
1896		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d1: 0111 0100 1101 0001 */
1897		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d2: 0111 0100 1101 0010 */
1898		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d3: 0111 0100 1101 0011 */
1899		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d4: 0111 0100 1101 0100 */
1900		{&upd7810_device::DADC_EA_BC, 2,11,11,L0\|L1}, /* d5: 0111 0100 1101 0101 */
1901		{&upd7810_device::DADC_EA_DE, 2,11,11,L0\|L1}, /* d6: 0111 0100 1101 0110 */
1902		{&upd7810_device::DADC_EA_HL, 2,11,11,L0\|L1}, /* d7: 0111 0100 1101 0111 */
1903		{&upd7810_device::OFFAW_wa, 3,14,11,L0\|L1}, /* d8: 0111 0100 1101 1000 oooo oooo */
1904		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d9: 0111 0100 1101 1001 */
1905		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* da: 0111 0100 1101 1010 */
1906		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* db: 0111 0100 1101 1011 */
1907		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* dc: 0111 0100 1101 1100 */
1908		{&upd7810_device::DOFF_EA_BC, 2,11,11,L0\|L1}, /* dd: 0111 0100 1101 1101 */
1909		{&upd7810_device::DOFF_EA_DE, 2,11,11,L0\|L1}, /* de: 0111 0100 1101 1110 */
1910		{&upd7810_device::DOFF_EA_HL, 2,11,11,L0\|L1}, /* df: 0111 0100 1101 1111 */
1911
1912		{&upd7810_device::SUBW_wa, 3,14,11,L0\|L1}, /* e0: 0111 0100 1110 0000 oooo oooo */
1913		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e1: 0111 0100 1110 0001 */
1914		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e2: 0111 0100 1110 0010 */
1915		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e3: 0111 0100 1110 0011 */
1916		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e4: 0111 0100 1110 0100 */
1917		{&upd7810_device::DSUB_EA_BC, 2,11,11,L0\|L1}, /* e5: 0111 0100 1110 0101 */
1918		{&upd7810_device::DSUB_EA_DE, 2,11,11,L0\|L1}, /* e6: 0111 0100 1110 0110 */
1919		{&upd7810_device::DSUB_EA_HL, 2,11,11,L0\|L1}, /* e7: 0111 0100 1110 0111 */
1920		{&upd7810_device::NEAW_wa, 3,14,11,L0\|L1}, /* e8: 0111 0100 1110 1000 oooo oooo */
1921		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e9: 0111 0100 1110 1001 */
1922		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ea: 0111 0100 1110 1010 */
1923		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* eb: 0111 0100 1110 1011 */
1924		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ec: 0111 0100 1110 1100 */
1925		{&upd7810_device::DNE_EA_BC, 2,11,11,L0\|L1}, /* ed: 0111 0100 1110 1101 */
1926		{&upd7810_device::DNE_EA_DE, 2,11,11,L0\|L1}, /* ee: 0111 0100 1110 1110 */
1927		{&upd7810_device::DNE_EA_HL, 2,11,11,L0\|L1}, /* ef: 0111 0100 1110 1111 */
1928
1929		{&upd7810_device::SBBW_wa, 3,14,11,L0\|L1}, /* f0: 0111 0100 1111 0000 oooo oooo */
1930		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f1: 0111 0100 1111 0001 */
1931		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f2: 0111 0100 1111 0010 */
1932		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f3: 0111 0100 1111 0011 */
1933		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f4: 0111 0100 1111 0100 */
1934		{&upd7810_device::DSBB_EA_BC, 2,11,11,L0\|L1}, /* f5: 0111 0100 1111 0101 */
1935		{&upd7810_device::DSBB_EA_DE, 2,11,11,L0\|L1}, /* f6: 0111 0100 1111 0110 */
1936		{&upd7810_device::DSBB_EA_HL, 2,11,11,L0\|L1}, /* f7: 0111 0100 1111 0111 */
1937		{&upd7810_device::EQAW_wa, 3,14,11,L0\|L1}, /* f8: 0111 0100 1111 1000 oooo oooo */
1938		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f9: 0111 0100 1111 1001 */
1939		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* fa: 0111 0100 1111 1010 */
1940		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* fb: 0111 0100 1111 1011 */
1941		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* fc: 0111 0100 1111 1100 */
1942		{&upd7810_device::DEQ_EA_BC, 2,11,11,L0\|L1}, /* fd: 0111 0100 1111 1101 */
1943		{&upd7810_device::DEQ_EA_DE, 2,11,11,L0\|L1}, /* fe: 0111 0100 1111 1110 */
1944		{&upd7810_device::DEQ_EA_HL, 2,11,11,L0\|L1} /* ff: 0111 0100 1111 1111 */
1945		};
1946
1947		/* main opcodes */
1948		const struct upd7810_device::opcode_s upd7810_device::s_opXX_7810[256] =
1949		{
1950		{&upd7810_device::NOP, 1, 4, 4,L0\|L1}, /* 00: 0000 0000 */
1951		{&upd7810_device::LDAW_wa, 2,10,10,L0\|L1}, /* 01: 0000 0001 oooo oooo */
1952		{&upd7810_device::INX_SP, 1, 7, 7,L0\|L1}, /* 02: 0000 0010 */
1953		{&upd7810_device::DCX_SP, 1, 7, 7,L0\|L1}, /* 03: 0000 0011 */
1954		{&upd7810_device::LXI_S_w, 3,10,10,L0\|L1}, /* 04: 0000 0100 llll llll hhhh hhhh */
1955		{&upd7810_device::ANIW_wa_xx, 3,19,19,L0\|L1}, /* 05: 0000 0101 oooo oooo xxxx xxxx */
1956		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, /* 06: */
1957		{&upd7810_device::ANI_A_xx, 2, 7, 7,L0\|L1}, /* 07: 0000 0111 xxxx xxxx */
1958		{&upd7810_device::MOV_A_EAH, 1, 4, 4,L0\|L1}, /* 08: 0000 1000 */
1959		{&upd7810_device::MOV_A_EAL, 1, 4, 4,L0\|L1}, /* 09: 0000 1001 */
1960		{&upd7810_device::MOV_A_B, 1, 4, 4,L0\|L1}, /* 0a: 0000 1010 */
1961		{&upd7810_device::MOV_A_C, 1, 4, 4,L0\|L1}, /* 0b: 0000 1011 */
1962		{&upd7810_device::MOV_A_D, 1, 4, 4,L0\|L1}, /* 0c: 0000 1100 */
1963		{&upd7810_device::MOV_A_E, 1, 4, 4,L0\|L1}, /* 0d: 0000 1101 */
1964		{&upd7810_device::MOV_A_H, 1, 4, 4,L0\|L1}, /* 0e: 0000 1110 */
1965		{&upd7810_device::MOV_A_L, 1, 4, 4,L0\|L1}, /* 0f: 0000 1111 */
1966
1967		{&upd7810_device::EXA, 1, 4, 4,L0\|L1}, /* 10: 0001 0000 */
1968		{&upd7810_device::EXX, 1, 4, 4,L0\|L1}, /* 11: 0001 0001 */
1969		{&upd7810_device::INX_BC, 1, 7, 7,L0\|L1}, /* 12: 0001 0010 */
1970		{&upd7810_device::DCX_BC, 1, 7, 7,L0\|L1}, /* 13: 0001 0011 */
1971		{&upd7810_device::LXI_B_w, 3,10,10,L0\|L1}, /* 14: 0001 0100 llll llll hhhh hhhh */
1972		{&upd7810_device::ORIW_wa_xx, 3,19,19,L0\|L1}, /* 15: 0001 0101 oooo oooo xxxx xxxx */
1973		{&upd7810_device::XRI_A_xx, 2, 7, 7,L0\|L1}, /* 16: 0001 0110 xxxx xxxx */
1974		{&upd7810_device::ORI_A_xx, 2, 7, 7,L0\|L1}, /* 17: 0001 0111 xxxx xxxx */
1975		{&upd7810_device::MOV_EAH_A, 1, 4, 4,L0\|L1}, /* 18: 0001 1000 */
1976		{&upd7810_device::MOV_EAL_A, 1, 4, 4,L0\|L1}, /* 19: 0001 1001 */
1977		{&upd7810_device::MOV_B_A, 1, 4, 4,L0\|L1}, /* 1a: 0001 1010 */
1978		{&upd7810_device::MOV_C_A, 1, 4, 4,L0\|L1}, /* 1b: 0001 1011 */
1979		{&upd7810_device::MOV_D_A, 1, 4, 4,L0\|L1}, /* 1c: 0001 1100 */
1980		{&upd7810_device::MOV_E_A, 1, 4, 4,L0\|L1}, /* 1d: 0001 1101 */
1981		{&upd7810_device::MOV_H_A, 1, 4, 4,L0\|L1}, /* 1e: 0001 1110 */
1982		{&upd7810_device::MOV_L_A, 1, 4, 4,L0\|L1}, /* 1f: 0001 1111 */
1983
1984		{&upd7810_device::INRW_wa, 2,16,16,L0\|L1}, /* 20: 0010 0000 oooo oooo */
1985		{&upd7810_device::JB, 1, 4, 4,L0\|L1}, /* 21: 0010 0001 */
1986		{&upd7810_device::INX_DE, 1, 7, 7,L0\|L1}, /* 22: 0010 0010 */
1987		{&upd7810_device::DCX_DE, 1, 7, 7,L0\|L1}, /* 23: 0010 0011 */
1988		{&upd7810_device::LXI_D_w, 3,10,10,L0\|L1}, /* 24: 0010 0100 llll llll hhhh hhhh */
1989		{&upd7810_device::GTIW_wa_xx, 3,19,19,L0\|L1}, /* 25: 0010 0101 oooo oooo xxxx xxxx */
1990		{&upd7810_device::ADINC_A_xx, 2, 7, 7,L0\|L1}, /* 26: 0010 0110 xxxx xxxx */
1991		{&upd7810_device::GTI_A_xx, 2, 7, 7,L0\|L1}, /* 27: 0010 0111 xxxx xxxx */
1992		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, /* 28: */
1993		{&upd7810_device::LDAX_B, 2, 7, 7,L0\|L1}, /* 29: 0010 1001 dddd dddd */
1994		{&upd7810_device::LDAX_D, 2, 7, 7,L0\|L1}, /* 2a: 0010 1010 dddd dddd */
1995		{&upd7810_device::LDAX_H, 2, 7, 7,L0\|L1}, /* 2b: 0010 1011 dddd dddd */
1996		{&upd7810_device::LDAX_Dp, 2, 7, 7,L0\|L1}, /* 2c: 0010 1100 dddd dddd */
1997		{&upd7810_device::LDAX_Hp, 2, 7, 7,L0\|L1}, /* 2d: 0010 1101 dddd dddd */
1998		{&upd7810_device::LDAX_Dm, 2, 7, 7,L0\|L1}, /* 2e: 0010 1110 dddd dddd */
1999		{&upd7810_device::LDAX_Hm, 2, 7, 7,L0\|L1}, /* 2f: 0010 1111 dddd dddd */
2000
2001		{&upd7810_device::DCRW_wa, 2,16,16,L0\|L1}, /* 30: 0011 0000 oooo oooo */
2002		{&upd7810_device::BLOCK, 1,13,13,L0\|L1}, /* 31: 0011 0001 / / 7810 */
2003		{&upd7810_device::INX_HL, 1, 7, 7,L0\|L1}, /* 32: 0011 0010 */
2004		{&upd7810_device::DCX_HL, 1, 7, 7,L0\|L1}, /* 33: 0011 0011 */
2005		{&upd7810_device::LXI_H_w, 3,10,10, L1}, /* 34: 0011 0100 llll llll hhhh hhhh */
2006		{&upd7810_device::LTIW_wa_xx, 3,19,19,L0\|L1}, /* 35: 0011 0101 oooo oooo xxxx xxxx */
2007		{&upd7810_device::SUINB_A_xx, 2, 7, 7,L0\|L1}, /* 36: 0011 0110 xxxx xxxx */
2008		{&upd7810_device::LTI_A_xx, 2, 7, 7,L0\|L1}, /* 37: 0011 0111 xxxx xxxx */
2009		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, /* 38: */
2010		{&upd7810_device::STAX_B, 2, 7, 7,L0\|L1}, /* 39: 0011 1001 dddd dddd */
2011		{&upd7810_device::STAX_D, 2, 7, 7,L0\|L1}, /* 3a: 0011 1010 dddd dddd */
2012		{&upd7810_device::STAX_H, 2, 7, 7,L0\|L1}, /* 3b: 0011 1011 dddd dddd */
2013		{&upd7810_device::STAX_Dp, 2, 7, 7,L0\|L1}, /* 3c: 0011 1100 dddd dddd */
2014		{&upd7810_device::STAX_Hp, 2, 7, 7,L0\|L1}, /* 3d: 0011 1101 dddd dddd */
2015		{&upd7810_device::STAX_Dm, 2, 7, 7,L0\|L1}, /* 3e: 0011 1110 dddd dddd */
2016		{&upd7810_device::STAX_Hm, 2, 7, 7,L0\|L1}, /* 3f: 0011 1111 dddd dddd */
2017
2018		{&upd7810_device::CALL_w, 3,16,16,L0\|L1}, /* 40: 0100 0000 llll llll hhhh hhhh */
2019		{&upd7810_device::INR_A, 1, 4, 4,L0\|L1}, /* 41: 0100 0001 */
2020		{&upd7810_device::INR_B, 1, 4, 4,L0\|L1}, /* 42: 0100 0010 */
2021		{&upd7810_device::INR_C, 1, 4, 4,L0\|L1}, /* 43: 0100 0011 */
2022		{&upd7810_device::LXI_EA_s, 3,10,10,L0\|L1}, /* 44: 0100 0100 llll llll hhhh hhhh */
2023		{&upd7810_device::ONIW_wa_xx, 3,19,19,L0\|L1}, /* 45: 0100 0101 oooo oooo xxxx xxxx */
2024		{&upd7810_device::ADI_A_xx, 2, 7, 7,L0\|L1}, /* 46: 0100 0110 xxxx xxxx */
2025		{&upd7810_device::ONI_A_xx, 2, 7, 7,L0\|L1}, /* 47: 0100 0111 xxxx xxxx */
2026		{&upd7810_device::PRE_48, 1, 0, 0,L0\|L1}, /* 48: prefix */
2027		{&upd7810_device::MVIX_BC_xx, 2,10,10,L0\|L1}, /* 49: 0100 1001 xxxx xxxx */
2028		{&upd7810_device::MVIX_DE_xx, 2,10,10,L0\|L1}, /* 4a: 0100 1010 xxxx xxxx */
2029		{&upd7810_device::MVIX_HL_xx, 2,10,10,L0\|L1}, /* 4b: 0100 1011 xxxx xxxx */
2030		{&upd7810_device::PRE_4C, 1, 0, 0,L0\|L1}, /* 4c: prefix */
2031		{&upd7810_device::PRE_4D, 1, 4, 4,L0\|L1}, /* 4d: prefix */
2032		{&upd7810_device::JRE, 2,10,10,L0\|L1}, /* 4e: 0100 111d dddd dddd */
2033		{&upd7810_device::JRE, 2,10,10,L0\|L1}, /* 4f: 0100 111d dddd dddd */
2034
2035		{&upd7810_device::EXH, 1, 4, 4,L0\|L1}, /* 50: 0101 0000 / / 7810 */
2036		{&upd7810_device::DCR_A, 1, 4, 4,L0\|L1}, /* 51: 0101 0001 */
2037		{&upd7810_device::DCR_B, 1, 4, 4,L0\|L1}, /* 52: 0101 0010 */
2038		{&upd7810_device::DCR_C, 1, 4, 4,L0\|L1}, /* 53: 0101 0011 */
2039		{&upd7810_device::JMP_w, 3,10,10,L0\|L1}, /* 54: 0101 0100 llll llll hhhh hhhh */
2040		{&upd7810_device::OFFIW_wa_xx, 3,19,19,L0\|L1}, /* 55: 0101 0101 oooo oooo xxxx xxxx */
2041		{&upd7810_device::ACI_A_xx, 2, 7, 7,L0\|L1}, /* 56: 0101 0110 xxxx xxxx */
2042		{&upd7810_device::OFFI_A_xx, 2, 7, 7,L0\|L1}, /* 57: 0101 0111 xxxx xxxx */
2043		{&upd7810_device::BIT_0_wa, 2,10,10,L0\|L1}, /* 58: 0101 1000 oooo oooo / / 7810 */
2044		{&upd7810_device::BIT_1_wa, 2,10,10,L0\|L1}, /* 59: 0101 1001 oooo oooo / / 7810 */
2045		{&upd7810_device::BIT_2_wa, 2,10,10,L0\|L1}, /* 5a: 0101 1010 oooo oooo / / 7810 */
2046		{&upd7810_device::BIT_3_wa, 2,10,10,L0\|L1}, /* 5b: 0101 1011 oooo oooo / / 7810 */
2047		{&upd7810_device::BIT_4_wa, 2,10,10,L0\|L1}, /* 5c: 0101 1100 oooo oooo / / 7810 */
2048		{&upd7810_device::BIT_5_wa, 2,10,10,L0\|L1}, /* 5d: 0101 1101 oooo oooo / / 7810 */
2049		{&upd7810_device::BIT_6_wa, 2,10,10,L0\|L1}, /* 5e: 0101 1110 oooo oooo / / 7810 */
2050		{&upd7810_device::BIT_7_wa, 2,10,10,L0\|L1}, /* 5f: 0101 1111 oooo oooo / / 7810 */
2051
2052		{&upd7810_device::PRE_60, 1, 0, 0,L0\|L1}, /* 60: */
2053		{&upd7810_device::DAA, 1, 4, 4,L0\|L1}, /* 61: 0110 0001 */
2054		{&upd7810_device::RETI, 1,13,13,L0\|L1}, /* 62: 0110 0010 */
2055		{&upd7810_device::STAW_wa, 2,10,10,L0\|L1}, /* 63: 0110 0011 oooo oooo */
2056		{&upd7810_device::PRE_64, 1, 0, 0,L0\|L1}, /* 64: */
2057		{&upd7810_device::NEIW_wa_xx, 3,19,19,L0\|L1}, /* 65: 0110 0101 oooo oooo xxxx xxxx */
2058		{&upd7810_device::SUI_A_xx, 2, 7, 7,L0\|L1}, /* 66: 0110 0110 xxxx xxxx */
2059		{&upd7810_device::NEI_A_xx, 2, 7, 7,L0\|L1}, /* 67: 0110 0111 xxxx xxxx */
2060		{&upd7810_device::MVI_V_xx, 2, 7, 7,L0\|L1}, /* 68: 0110 1000 xxxx xxxx */
2061		{&upd7810_device::MVI_A_xx, 2, 7, 7,L0 }, /* 69: 0110 1001 xxxx xxxx */
2062		{&upd7810_device::MVI_B_xx, 2, 7, 7,L0\|L1}, /* 6a: 0110 1010 xxxx xxxx */
2063		{&upd7810_device::MVI_C_xx, 2, 7, 7,L0\|L1}, /* 6b: 0110 1011 xxxx xxxx */
2064		{&upd7810_device::MVI_D_xx, 2, 7, 7,L0\|L1}, /* 6c: 0110 1100 xxxx xxxx */
2065		{&upd7810_device::MVI_E_xx, 2, 7, 7,L0\|L1}, /* 6d: 0110 1101 xxxx xxxx */
2066		{&upd7810_device::MVI_H_xx, 2, 7, 7,L0\|L1}, /* 6e: 0110 1110 xxxx xxxx */
2067		{&upd7810_device::MVI_L_xx, 2, 7, 7, L1}, /* 6f: 0110 1111 xxxx xxxx */
2068
2069		{&upd7810_device::PRE_70, 1, 0, 0,L0\|L1}, /* 70: */
2070		{&upd7810_device::MVIW_wa_xx, 3,13,13,L0\|L1}, /* 71: 0111 0001 oooo oooo xxxx xxxx */
2071		{&upd7810_device::SOFTI, 1,16,16,L0\|L1}, /* 72: 0111 0010 */
2072		{&upd7810_device::illegal, 1, 0, 0,L0\|L1}, /* 73: */
2073		{&upd7810_device::PRE_74, 1, 0, 0,L0\|L1}, /* 74: prefix */
2074		{&upd7810_device::EQIW_wa_xx, 3,19,19,L0\|L1}, /* 75: 0111 0101 oooo oooo xxxx xxxx */
2075		{&upd7810_device::SBI_A_xx, 2, 7, 7,L0\|L1}, /* 76: 0111 0110 xxxx xxxx */
2076		{&upd7810_device::EQI_A_xx, 2, 7, 7,L0\|L1}, /* 77: 0111 0111 xxxx xxxx */
2077		{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 78: 0111 1xxx xxxx xxxx */
2078		{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 79: 0111 1xxx xxxx xxxx */
2079		{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7a: 0111 1xxx xxxx xxxx */
2080		{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7b: 0111 1xxx xxxx xxxx */
2081		{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7c: 0111 1xxx xxxx xxxx */
2082		{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7d: 0111 1xxx xxxx xxxx */
2083		{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7e: 0111 1xxx xxxx xxxx */
2084		{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7f: 0111 1xxx xxxx xxxx */
2085
2086		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 80: 100x xxxx */
2087		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 81: 100x xxxx */
2088		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 82: 100x xxxx */
2089		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 83: 100x xxxx */
2090		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 84: 100x xxxx */
2091		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 85: 100x xxxx */
2092		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 86: 100x xxxx */
2093		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 87: 100x xxxx */
2094		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 88: 100x xxxx */
2095		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 89: 100x xxxx */
2096		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8a: 100x xxxx */
2097		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8b: 100x xxxx */
2098		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8c: 100x xxxx */
2099		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8d: 100x xxxx */
2100		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8e: 100x xxxx */
2101		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8f: 100x xxxx */
2102
2103		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 90: 100x xxxx */
2104		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 91: 100x xxxx */
2105		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 92: 100x xxxx */
2106		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 93: 100x xxxx */
2107		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 94: 100x xxxx */
2108		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 95: 100x xxxx */
2109		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 96: 100x xxxx */
2110		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 97: 100x xxxx */
2111		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 98: 100x xxxx */
2112		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 99: 100x xxxx */
2113		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9a: 100x xxxx */
2114		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9b: 100x xxxx */
2115		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9c: 100x xxxx */
2116		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9d: 100x xxxx */
2117		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9e: 100x xxxx */
2118		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9f: 100x xxxx */
2119
2120		{&upd7810_device::POP_VA, 1,10,10,L0\|L1}, /* a0: 1010 0000 */
2121		{&upd7810_device::POP_BC, 1,10,10,L0\|L1}, /* a1: 1010 0001 */
2122		{&upd7810_device::POP_DE, 1,10,10,L0\|L1}, /* a2: 1010 0010 */
2123		{&upd7810_device::POP_HL, 1,10,10,L0\|L1}, /* a3: 1010 0011 */
2124		{&upd7810_device::POP_EA, 1,10,10,L0\|L1}, /* a4: 1010 0100 */
2125		{&upd7810_device::DMOV_EA_BC, 1, 4, 4,L0\|L1}, /* a5: 1010 0101 */
2126		{&upd7810_device::DMOV_EA_DE, 1, 4, 4,L0\|L1}, /* a6: 1010 0110 */
2127		{&upd7810_device::DMOV_EA_HL, 1, 4, 4,L0\|L1}, /* a7: 1010 0111 */
2128		{&upd7810_device::INX_EA, 1, 7, 7,L0\|L1}, /* a8: 1010 1000 */
2129		{&upd7810_device::DCX_EA, 1, 7, 7,L0\|L1}, /* a9: 1010 1001 */
2130		{&upd7810_device::EI, 1, 4, 4,L0\|L1}, /* aa: 1010 1010 */
2131		{&upd7810_device::LDAX_D_xx, 2, 7, 7,L0\|L1}, /* ab: 1010 1011 dddd dddd */
2132		{&upd7810_device::LDAX_H_A, 1, 7, 7,L0\|L1}, /* ac: 1010 1100 */
2133		{&upd7810_device::LDAX_H_B, 1, 7, 7,L0\|L1}, /* ad: 1010 1101 */
2134		{&upd7810_device::LDAX_H_EA, 1, 7, 7,L0\|L1}, /* ae: 1010 1110 */
2135		{&upd7810_device::LDAX_H_xx, 2, 7, 7,L0\|L1}, /* af: 1010 1111 dddd dddd */
2136
2137		{&upd7810_device::PUSH_VA, 1,13,13,L0\|L1}, /* b0: 1011 0000 */
2138		{&upd7810_device::PUSH_BC, 1,13,13,L0\|L1}, /* b1: 1011 0001 */
2139		{&upd7810_device::PUSH_DE, 1,13,13,L0\|L1}, /* b2: 1011 0010 */
2140		{&upd7810_device::PUSH_HL, 1,13,13,L0\|L1}, /* b3: 1011 0011 */
2141		{&upd7810_device::PUSH_EA, 1,13,13,L0\|L1}, /* b4: 1011 0100 */
2142		{&upd7810_device::DMOV_BC_EA, 1, 4, 4,L0\|L1}, /* b5: 1011 0101 */
2143		{&upd7810_device::DMOV_DE_EA, 1, 4, 4,L0\|L1}, /* b6: 1011 0110 */
2144		{&upd7810_device::DMOV_HL_EA, 1, 4, 4,L0\|L1}, /* b7: 1011 0111 */
2145		{&upd7810_device::RET, 1,10,10,L0\|L1}, /* b8: 1011 1000 */
2146		{&upd7810_device::RETS, 1,10,10,L0\|L1}, /* b9: 1011 1001 */
2147		{&upd7810_device::DI, 1, 4, 4,L0\|L1}, /* ba: 1011 1010 */
2148		{&upd7810_device::STAX_D_xx, 2, 7, 7,L0\|L1}, /* bb: 1011 1011 dddd dddd */
2149		{&upd7810_device::STAX_H_A, 1, 7, 7,L0\|L1}, /* bc: 1011 1100 */
2150		{&upd7810_device::STAX_H_B, 1, 7, 7,L0\|L1}, /* bd: 1011 1101 */
2151		{&upd7810_device::STAX_H_EA, 1, 7, 7,L0\|L1}, /* be: 1011 1110 */
2152		{&upd7810_device::STAX_H_xx, 2, 7, 7,L0\|L1}, /* bf: 1011 1111 dddd dddd */
2153
2154		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c0: 1100 0000 */
2155		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c1: 1100 0001 */
2156		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c2: 1100 0010 */
2157		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c3: 1100 0011 */
2158		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c4: 1100 0100 */
2159		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c5: 1100 0101 */
2160		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c6: 1100 0110 */
2161		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c7: 1100 0111 */
2162		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c8: 1100 1000 */
2163		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c9: 1100 1001 */
2164		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ca: 1100 1010 */
2165		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* cb: 1100 1011 */
2166		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* cc: 1100 1100 */
2167		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* cd: 1100 1101 */
2168		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ce: 1100 1110 */
2169		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* cf: 1100 1111 */
2170
2171		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d0: 1101 0000 */
2172		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d1: 1101 0001 */
2173		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d2: 1101 0010 */
2174		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d3: 1101 0011 */
2175		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d4: 1101 0100 */
2176		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d5: 1101 0101 */
2177		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d6: 1101 0110 */
2178		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d7: 1101 0111 */
2179		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d8: 1101 1000 */
2180		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d9: 1101 1001 */
2181		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* da: 1101 1010 */
2182		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* db: 1101 1011 */
2183		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* dc: 1101 1100 */
2184		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* dd: 1101 1101 */
2185		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* de: 1101 1110 */
2186		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* df: 1101 1111 */
2187
2188		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e0: 1110 0000 */
2189		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e1: 1110 0001 */
2190		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e2: 1110 0010 */
2191		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e3: 1110 0011 */
2192		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e4: 1110 0100 */
2193		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e5: 1110 0101 */
2194		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e6: 1110 0110 */
2195		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e7: 1110 0111 */
2196		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e8: 1110 1000 */
2197		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e9: 1110 1001 */
2198		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ea: 1110 1010 */
2199		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* eb: 1110 1011 */
2200		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ec: 1110 1100 */
2201		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ed: 1110 1101 */
2202		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ee: 1110 1110 */
2203		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ef: 1110 1111 */
2204
2205		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f0: 1111 0000 */
2206		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f1: 1111 0001 */
2207		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f2: 1111 0010 */
2208		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f3: 1111 0011 */
2209		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f4: 1111 0100 */
2210		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f5: 1111 0101 */
2211		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f6: 1111 0110 */
2212		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f7: 1111 0111 */
2213		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f8: 1111 1000 */
2214		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f9: 1111 1001 */
2215		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fa: 1111 1010 */
2216		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fb: 1111 1011 */
2217		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fc: 1111 1100 */
2218		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fd: 1111 1101 */
2219		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fe: 1111 1110 */
2220		{&upd7810_device::JR, 1,10,10,L0\|L1} /* ff: 1111 1111 */
2221		};
2222
2223		const struct upd7810_device::opcode_s upd7810_device::s_opXX_7807[256] =
2224		{
2225		{&upd7810_device::NOP, 1, 4, 4,L0\|L1}, /* 00: 0000 0000 */
2226		{&upd7810_device::LDAW_wa, 2,10,10,L0\|L1}, /* 01: 0000 0001 oooo oooo */
2227		{&upd7810_device::INX_SP, 1, 7, 7,L0\|L1}, /* 02: 0000 0010 */
2228		{&upd7810_device::DCX_SP, 1, 7, 7,L0\|L1}, /* 03: 0000 0011 */
2229		{&upd7810_device::LXI_S_w, 3,10,10,L0\|L1}, /* 04: 0000 0100 llll llll hhhh hhhh */
2230		{&upd7810_device::ANIW_wa_xx, 3,19,19,L0\|L1}, /* 05: 0000 0101 oooo oooo xxxx xxxx */
2231		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, /* 06: */
2232		{&upd7810_device::ANI_A_xx, 2, 7, 7,L0\|L1}, /* 07: 0000 0111 xxxx xxxx */
2233		{&upd7810_device::MOV_A_EAH, 1, 4, 4,L0\|L1}, /* 08: 0000 1000 */
2234		{&upd7810_device::MOV_A_EAL, 1, 4, 4,L0\|L1}, /* 09: 0000 1001 */
2235		{&upd7810_device::MOV_A_B, 1, 4, 4,L0\|L1}, /* 0a: 0000 1010 */
2236		{&upd7810_device::MOV_A_C, 1, 4, 4,L0\|L1}, /* 0b: 0000 1011 */
2237		{&upd7810_device::MOV_A_D, 1, 4, 4,L0\|L1}, /* 0c: 0000 1100 */
2238		{&upd7810_device::MOV_A_E, 1, 4, 4,L0\|L1}, /* 0d: 0000 1101 */
2239		{&upd7810_device::MOV_A_H, 1, 4, 4,L0\|L1}, /* 0e: 0000 1110 */
2240		{&upd7810_device::MOV_A_L, 1, 4, 4,L0\|L1}, /* 0f: 0000 1111 */
2241
2242		{&upd7810_device::illegal, 1,13, 4,L0\|L1}, /* 10: 0001 0000 / / 7807 */
2243		{&upd7810_device::illegal, 1,13, 4,L0\|L1}, /* 11: 0001 0001 / / 7807 */
2244		{&upd7810_device::INX_BC, 1, 7, 7,L0\|L1}, /* 12: 0001 0010 */
2245		{&upd7810_device::DCX_BC, 1, 7, 7,L0\|L1}, /* 13: 0001 0011 */
2246		{&upd7810_device::LXI_B_w, 3,10,10,L0\|L1}, /* 14: 0001 0100 llll llll hhhh hhhh */
2247		{&upd7810_device::ORIW_wa_xx, 3,19,19,L0\|L1}, /* 15: 0001 0101 oooo oooo xxxx xxxx */
2248		{&upd7810_device::XRI_A_xx, 2, 7, 7,L0\|L1}, /* 16: 0001 0110 xxxx xxxx */
2249		{&upd7810_device::ORI_A_xx, 2, 7, 7,L0\|L1}, /* 17: 0001 0111 xxxx xxxx */
2250		{&upd7810_device::MOV_EAH_A, 1, 4, 4,L0\|L1}, /* 18: 0001 1000 */
2251		{&upd7810_device::MOV_EAL_A, 1, 4, 4,L0\|L1}, /* 19: 0001 1001 */
2252		{&upd7810_device::MOV_B_A, 1, 4, 4,L0\|L1}, /* 1a: 0001 1010 */
2253		{&upd7810_device::MOV_C_A, 1, 4, 4,L0\|L1}, /* 1b: 0001 1011 */
2254		{&upd7810_device::MOV_D_A, 1, 4, 4,L0\|L1}, /* 1c: 0001 1100 */
2255		{&upd7810_device::MOV_E_A, 1, 4, 4,L0\|L1}, /* 1d: 0001 1101 */
2256		{&upd7810_device::MOV_H_A, 1, 4, 4,L0\|L1}, /* 1e: 0001 1110 */
2257		{&upd7810_device::MOV_L_A, 1, 4, 4,L0\|L1}, /* 1f: 0001 1111 */
2258
2259		{&upd7810_device::INRW_wa, 2,16,16,L0\|L1}, /* 20: 0010 0000 oooo oooo */
2260		{&upd7810_device::JB, 1, 4, 4,L0\|L1}, /* 21: 0010 0001 */
2261		{&upd7810_device::INX_DE, 1, 7, 7,L0\|L1}, /* 22: 0010 0010 */
2262		{&upd7810_device::DCX_DE, 1, 7, 7,L0\|L1}, /* 23: 0010 0011 */
2263		{&upd7810_device::LXI_D_w, 3,10,10,L0\|L1}, /* 24: 0010 0100 llll llll hhhh hhhh */
2264		{&upd7810_device::GTIW_wa_xx, 3,19,19,L0\|L1}, /* 25: 0010 0101 oooo oooo xxxx xxxx */
2265		{&upd7810_device::ADINC_A_xx, 2, 7, 7,L0\|L1}, /* 26: 0010 0110 xxxx xxxx */
2266		{&upd7810_device::GTI_A_xx, 2, 7, 7,L0\|L1}, /* 27: 0010 0111 xxxx xxxx */
2267		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, /* 28: */
2268		{&upd7810_device::LDAX_B, 2, 7, 7,L0\|L1}, /* 29: 0010 1001 dddd dddd */
2269		{&upd7810_device::LDAX_D, 2, 7, 7,L0\|L1}, /* 2a: 0010 1010 dddd dddd */
2270		{&upd7810_device::LDAX_H, 2, 7, 7,L0\|L1}, /* 2b: 0010 1011 dddd dddd */
2271		{&upd7810_device::LDAX_Dp, 2, 7, 7,L0\|L1}, /* 2c: 0010 1100 dddd dddd */
2272		{&upd7810_device::LDAX_Hp, 2, 7, 7,L0\|L1}, /* 2d: 0010 1101 dddd dddd */
2273		{&upd7810_device::LDAX_Dm, 2, 7, 7,L0\|L1}, /* 2e: 0010 1110 dddd dddd */
2274		{&upd7810_device::LDAX_Hm, 2, 7, 7,L0\|L1}, /* 2f: 0010 1111 dddd dddd */
2275
2276		{&upd7810_device::DCRW_wa, 2,16,16,L0\|L1}, /* 30: 0011 0000 oooo oooo */
2277		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 31: 0011 0001 bbbb bbbb / / 7807 */
2278		{&upd7810_device::INX_HL, 1, 7, 7,L0\|L1}, /* 32: 0011 0010 */
2279		{&upd7810_device::DCX_HL, 1, 7, 7,L0\|L1}, /* 33: 0011 0011 */
2280		{&upd7810_device::LXI_H_w, 3,10,10, L1}, /* 34: 0011 0100 llll llll hhhh hhhh */
2281		{&upd7810_device::LTIW_wa_xx, 3,19,19,L0\|L1}, /* 35: 0011 0101 oooo oooo xxxx xxxx */
2282		{&upd7810_device::SUINB_A_xx, 2, 7, 7,L0\|L1}, /* 36: 0011 0110 xxxx xxxx */
2283		{&upd7810_device::LTI_A_xx, 2, 7, 7,L0\|L1}, /* 37: 0011 0111 xxxx xxxx */
2284		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, /* 38: */
2285		{&upd7810_device::STAX_B, 2, 7, 7,L0\|L1}, /* 39: 0011 1001 dddd dddd */
2286		{&upd7810_device::STAX_D, 2, 7, 7,L0\|L1}, /* 3a: 0011 1010 dddd dddd */
2287		{&upd7810_device::STAX_H, 2, 7, 7,L0\|L1}, /* 3b: 0011 1011 dddd dddd */
2288		{&upd7810_device::STAX_Dp, 2, 7, 7,L0\|L1}, /* 3c: 0011 1100 dddd dddd */
2289		{&upd7810_device::STAX_Hp, 2, 7, 7,L0\|L1}, /* 3d: 0011 1101 dddd dddd */
2290		{&upd7810_device::STAX_Dm, 2, 7, 7,L0\|L1}, /* 3e: 0011 1110 dddd dddd */
2291		{&upd7810_device::STAX_Hm, 2, 7, 7,L0\|L1}, /* 3f: 0011 1111 dddd dddd */
2292
2293		{&upd7810_device::CALL_w, 3,16,16,L0\|L1}, /* 40: 0100 0000 llll llll hhhh hhhh */
2294		{&upd7810_device::INR_A, 1, 4, 4,L0\|L1}, /* 41: 0100 0001 */
2295		{&upd7810_device::INR_B, 1, 4, 4,L0\|L1}, /* 42: 0100 0010 */
2296		{&upd7810_device::INR_C, 1, 4, 4,L0\|L1}, /* 43: 0100 0011 */
2297		{&upd7810_device::LXI_EA_s, 3,10,10,L0\|L1}, /* 44: 0100 0100 llll llll hhhh hhhh */
2298		{&upd7810_device::ONIW_wa_xx, 3,19,19,L0\|L1}, /* 45: 0100 0101 oooo oooo xxxx xxxx */
2299		{&upd7810_device::ADI_A_xx, 2, 7, 7,L0\|L1}, /* 46: 0100 0110 xxxx xxxx */
2300		{&upd7810_device::ONI_A_xx, 2, 7, 7,L0\|L1}, /* 47: 0100 0111 xxxx xxxx */
2301		{&upd7810_device::PRE_48, 1, 0, 0,L0\|L1}, /* 48: prefix */
2302		{&upd7810_device::MVIX_BC_xx, 2,10,10,L0\|L1}, /* 49: 0100 1001 xxxx xxxx */
2303		{&upd7810_device::MVIX_DE_xx, 2,10,10,L0\|L1}, /* 4a: 0100 1010 xxxx xxxx */
2304		{&upd7810_device::MVIX_HL_xx, 2,10,10,L0\|L1}, /* 4b: 0100 1011 xxxx xxxx */
2305		{&upd7810_device::PRE_4C, 1, 0, 0,L0\|L1}, /* 4c: prefix */
2306		{&upd7810_device::PRE_4D, 1, 4, 4,L0\|L1}, /* 4d: prefix */
2307		{&upd7810_device::JRE, 2,10,10,L0\|L1}, /* 4e: 0100 111d dddd dddd */
2308		{&upd7810_device::JRE, 2,10,10,L0\|L1}, /* 4f: 0100 111d dddd dddd */
2309
2310		{&upd7810_device::SKN_bit, 2,13,13,L0\|L1}, /* 50: 0101 0000 bbbb bbbb / / 7807 */
2311		{&upd7810_device::DCR_A, 1, 4, 4,L0\|L1}, /* 51: 0101 0001 */
2312		{&upd7810_device::DCR_B, 1, 4, 4,L0\|L1}, /* 52: 0101 0010 */
2313		{&upd7810_device::DCR_C, 1, 4, 4,L0\|L1}, /* 53: 0101 0011 */
2314		{&upd7810_device::JMP_w, 3,10,10,L0\|L1}, /* 54: 0101 0100 llll llll hhhh hhhh */
2315		{&upd7810_device::OFFIW_wa_xx, 3,19,19,L0\|L1}, /* 55: 0101 0101 oooo oooo xxxx xxxx */
2316		{&upd7810_device::ACI_A_xx, 2, 7, 7,L0\|L1}, /* 56: 0101 0110 xxxx xxxx */
2317		{&upd7810_device::OFFI_A_xx, 2, 7, 7,L0\|L1}, /* 57: 0101 0111 xxxx xxxx */
2318		{&upd7810_device::SETB, 2,13,13,L0\|L1}, /* 58: 0101 1000 bbbb bbbb / / 7807 */
2319		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 59: 0101 1001 bbbb bbbb / / 7807 */
2320		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 5a: 0101 1010 bbbb bbbb / / 7807 */
2321		{&upd7810_device::CLR, 2,13,13,L0\|L1}, /* 5b: 0101 1011 bbbb bbbb / / 7807 */
2322		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 5c: 0101 1100 bbbb bbbb / / 7807 */
2323		{&upd7810_device::SK_bit, 2,10,10,L0\|L1}, /* 5d: 0101 1101 bbbb bbbb / / 7807 */
2324		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 5e: 0101 1110 bbbb bbbb / / 7807 */
2325		{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 5f: 0101 1111 bbbb bbbb / / 7807 */
2326
2327		{&upd7810_device::PRE_60, 1, 0, 0,L0\|L1}, /* 60: */
2328		{&upd7810_device::DAA, 1, 4, 4,L0\|L1}, /* 61: 0110 0001 */
2329		{&upd7810_device::RETI, 1,13,13,L0\|L1}, /* 62: 0110 0010 */
2330		{&upd7810_device::STAW_wa, 2,10,10,L0\|L1}, /* 63: 0110 0011 oooo oooo */
2331		{&upd7810_device::PRE_64, 1, 0, 0,L0\|L1}, /* 64: */
2332		{&upd7810_device::NEIW_wa_xx, 3,19,19,L0\|L1}, /* 65: 0110 0101 oooo oooo xxxx xxxx */
2333		{&upd7810_device::SUI_A_xx, 2, 7, 7,L0\|L1}, /* 66: 0110 0110 xxxx xxxx */
2334		{&upd7810_device::NEI_A_xx, 2, 7, 7,L0\|L1}, /* 67: 0110 0111 xxxx xxxx */
2335		{&upd7810_device::MVI_V_xx, 2, 7, 7,L0\|L1}, /* 68: 0110 1000 xxxx xxxx */
2336		{&upd7810_device::MVI_A_xx, 2, 7, 7,L0 }, /* 69: 0110 1001 xxxx xxxx */
2337		{&upd7810_device::MVI_B_xx, 2, 7, 7,L0\|L1}, /* 6a: 0110 1010 xxxx xxxx */
2338		{&upd7810_device::MVI_C_xx, 2, 7, 7,L0\|L1}, /* 6b: 0110 1011 xxxx xxxx */
2339		{&upd7810_device::MVI_D_xx, 2, 7, 7,L0\|L1}, /* 6c: 0110 1100 xxxx xxxx */
2340		{&upd7810_device::MVI_E_xx, 2, 7, 7,L0\|L1}, /* 6d: 0110 1101 xxxx xxxx */
2341		{&upd7810_device::MVI_H_xx, 2, 7, 7,L0\|L1}, /* 6e: 0110 1110 xxxx xxxx */
2342		{&upd7810_device::MVI_L_xx, 2, 7, 7, L1}, /* 6f: 0110 1111 xxxx xxxx */
2343
2344		{&upd7810_device::PRE_70, 1, 0, 0,L0\|L1}, /* 70: */
2345		{&upd7810_device::MVIW_wa_xx, 3,13,13,L0\|L1}, /* 71: 0111 0001 oooo oooo xxxx xxxx */
2346		{&upd7810_device::SOFTI, 1,16,16,L0\|L1}, /* 72: 0111 0010 */
2347		{&upd7810_device::illegal, 1, 0, 0,L0\|L1}, /* 73: */
2348		{&upd7810_device::PRE_74, 1, 0, 0,L0\|L1}, /* 74: prefix */
2349		{&upd7810_device::EQIW_wa_xx, 3,19,19,L0\|L1}, /* 75: 0111 0101 oooo oooo xxxx xxxx */
2350		{&upd7810_device::SBI_A_xx, 2, 7, 7,L0\|L1}, /* 76: 0111 0110 xxxx xxxx */
2351		{&upd7810_device::EQI_A_xx, 2, 7, 7,L0\|L1}, /* 77: 0111 0111 xxxx xxxx */
2352		{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 78: 0111 1xxx xxxx xxxx */
2353		{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 79: 0111 1xxx xxxx xxxx */
2354		{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7a: 0111 1xxx xxxx xxxx */
2355		{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7b: 0111 1xxx xxxx xxxx */
2356		{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7c: 0111 1xxx xxxx xxxx */
2357		{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7d: 0111 1xxx xxxx xxxx */
2358		{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7e: 0111 1xxx xxxx xxxx */
2359		{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7f: 0111 1xxx xxxx xxxx */
2360
2361		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 80: 100x xxxx */
2362		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 81: 100x xxxx */
2363		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 82: 100x xxxx */
2364		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 83: 100x xxxx */
2365		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 84: 100x xxxx */
2366		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 85: 100x xxxx */
2367		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 86: 100x xxxx */
2368		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 87: 100x xxxx */
2369		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 88: 100x xxxx */
2370		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 89: 100x xxxx */
2371		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8a: 100x xxxx */
2372		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8b: 100x xxxx */
2373		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8c: 100x xxxx */
2374		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8d: 100x xxxx */
2375		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8e: 100x xxxx */
2376		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8f: 100x xxxx */
2377
2378		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 90: 100x xxxx */
2379		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 91: 100x xxxx */
2380		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 92: 100x xxxx */
2381		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 93: 100x xxxx */
2382		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 94: 100x xxxx */
2383		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 95: 100x xxxx */
2384		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 96: 100x xxxx */
2385		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 97: 100x xxxx */
2386		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 98: 100x xxxx */
2387		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 99: 100x xxxx */
2388		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9a: 100x xxxx */
2389		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9b: 100x xxxx */
2390		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9c: 100x xxxx */
2391		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9d: 100x xxxx */
2392		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9e: 100x xxxx */
2393		{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9f: 100x xxxx */
2394
2395		{&upd7810_device::POP_VA, 1,10,10,L0\|L1}, /* a0: 1010 0000 */
2396		{&upd7810_device::POP_BC, 1,10,10,L0\|L1}, /* a1: 1010 0001 */
2397		{&upd7810_device::POP_DE, 1,10,10,L0\|L1}, /* a2: 1010 0010 */
2398		{&upd7810_device::POP_HL, 1,10,10,L0\|L1}, /* a3: 1010 0011 */
2399		{&upd7810_device::POP_EA, 1,10,10,L0\|L1}, /* a4: 1010 0100 */
2400		{&upd7810_device::DMOV_EA_BC, 1, 4, 4,L0\|L1}, /* a5: 1010 0101 */
2401		{&upd7810_device::DMOV_EA_DE, 1, 4, 4,L0\|L1}, /* a6: 1010 0110 */
2402		{&upd7810_device::DMOV_EA_HL, 1, 4, 4,L0\|L1}, /* a7: 1010 0111 */
2403		{&upd7810_device::INX_EA, 1, 7, 7,L0\|L1}, /* a8: 1010 1000 */
2404		{&upd7810_device::DCX_EA, 1, 7, 7,L0\|L1}, /* a9: 1010 1001 */
2405		{&upd7810_device::EI, 1, 4, 4,L0\|L1}, /* aa: 1010 1010 */
2406		{&upd7810_device::LDAX_D_xx, 2, 7, 7,L0\|L1}, /* ab: 1010 1011 dddd dddd */
2407		{&upd7810_device::LDAX_H_A, 1, 7, 7,L0\|L1}, /* ac: 1010 1100 */
2408		{&upd7810_device::LDAX_H_B, 1, 7, 7,L0\|L1}, /* ad: 1010 1101 */
2409		{&upd7810_device::LDAX_H_EA, 1, 7, 7,L0\|L1}, /* ae: 1010 1110 */
2410		{&upd7810_device::LDAX_H_xx, 2, 7, 7,L0\|L1}, /* af: 1010 1111 dddd dddd */
2411
2412		{&upd7810_device::PUSH_VA, 1,13,13,L0\|L1}, /* b0: 1011 0000 */
2413		{&upd7810_device::PUSH_BC, 1,13,13,L0\|L1}, /* b1: 1011 0001 */
2414		{&upd7810_device::PUSH_DE, 1,13,13,L0\|L1}, /* b2: 1011 0010 */
2415		{&upd7810_device::PUSH_HL, 1,13,13,L0\|L1}, /* b3: 1011 0011 */
2416		{&upd7810_device::PUSH_EA, 1,13,13,L0\|L1}, /* b4: 1011 0100 */
2417		{&upd7810_device::DMOV_BC_EA, 1, 4, 4,L0\|L1}, /* b5: 1011 0101 */
2418		{&upd7810_device::DMOV_DE_EA, 1, 4, 4,L0\|L1}, /* b6: 1011 0110 */
2419		{&upd7810_device::DMOV_HL_EA, 1, 4, 4,L0\|L1}, /* b7: 1011 0111 */
2420		{&upd7810_device::RET, 1,10,10,L0\|L1}, /* b8: 1011 1000 */
2421		{&upd7810_device::RETS, 1,10,10,L0\|L1}, /* b9: 1011 1001 */
2422		{&upd7810_device::DI, 1, 4, 4,L0\|L1}, /* ba: 1011 1010 */
2423		{&upd7810_device::STAX_D_xx, 2, 7, 7,L0\|L1}, /* bb: 1011 1011 dddd dddd */
2424		{&upd7810_device::STAX_H_A, 1, 7, 7,L0\|L1}, /* bc: 1011 1100 */
2425		{&upd7810_device::STAX_H_B, 1, 7, 7,L0\|L1}, /* bd: 1011 1101 */
2426		{&upd7810_device::STAX_H_EA, 1, 7, 7,L0\|L1}, /* be: 1011 1110 */
2427		{&upd7810_device::STAX_H_xx, 2, 7, 7,L0\|L1}, /* bf: 1011 1111 dddd dddd */
2428
2429		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c0: 1100 0000 */
2430		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c1: 1100 0001 */
2431		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c2: 1100 0010 */
2432		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c3: 1100 0011 */
2433		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c4: 1100 0100 */
2434		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c5: 1100 0101 */
2435		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c6: 1100 0110 */
2436		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c7: 1100 0111 */
2437		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c8: 1100 1000 */
2438		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c9: 1100 1001 */
2439		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ca: 1100 1010 */
2440		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* cb: 1100 1011 */
2441		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* cc: 1100 1100 */
2442		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* cd: 1100 1101 */
2443		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ce: 1100 1110 */
2444		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* cf: 1100 1111 */
2445
2446		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d0: 1101 0000 */
2447		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d1: 1101 0001 */
2448		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d2: 1101 0010 */
2449		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d3: 1101 0011 */
2450		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d4: 1101 0100 */
2451		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d5: 1101 0101 */
2452		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d6: 1101 0110 */
2453		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d7: 1101 0111 */
2454		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d8: 1101 1000 */
2455		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d9: 1101 1001 */
2456		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* da: 1101 1010 */
2457		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* db: 1101 1011 */
2458		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* dc: 1101 1100 */
2459		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* dd: 1101 1101 */
2460		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* de: 1101 1110 */
2461		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* df: 1101 1111 */
2462
2463		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e0: 1110 0000 */
2464		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e1: 1110 0001 */
2465		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e2: 1110 0010 */
2466		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e3: 1110 0011 */
2467		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e4: 1110 0100 */
2468		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e5: 1110 0101 */
2469		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e6: 1110 0110 */
2470		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e7: 1110 0111 */
2471		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e8: 1110 1000 */
2472		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e9: 1110 1001 */
2473		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ea: 1110 1010 */
2474		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* eb: 1110 1011 */
2475		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ec: 1110 1100 */
2476		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ed: 1110 1101 */
2477		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ee: 1110 1110 */
2478		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ef: 1110 1111 */
2479
2480		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f0: 1111 0000 */
2481		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f1: 1111 0001 */
2482		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f2: 1111 0010 */
2483		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f3: 1111 0011 */
2484		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f4: 1111 0100 */
2485		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f5: 1111 0101 */
2486		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f6: 1111 0110 */
2487		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f7: 1111 0111 */
2488		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f8: 1111 1000 */
2489		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f9: 1111 1001 */
2490		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fa: 1111 1010 */
2491		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fb: 1111 1011 */
2492		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fc: 1111 1100 */
2493		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fd: 1111 1101 */
2494		{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fe: 1111 1110 */
2495		{&upd7810_device::JR, 1,10,10,L0\|L1} /* ff: 1111 1111 */
2496		};
2497
2498
2499		/***********************************************************************
2500		*
2501		* uPD7801
2502		*
2503		**********************************************************************/
2504
2505		const struct upd7810_device::opcode_s upd7810_device::s_op48_7801[256] =
2506		{
2507		/* 0x00 - 0x1F */
2508		{&upd7810_device::SKIT_F0, 2, 8, 8,L0\|L1}, {&upd7810_device::SKIT_FT0, 2, 8, 8,L0\|L1},
2509		{&upd7810_device::SKIT_F1, 2, 8, 8,L0\|L1}, {&upd7810_device::SKIT_F2, 2, 8, 8,L0\|L1},
2510		{&upd7810_device::SKIT_FST, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2511		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2512		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2513		{&upd7810_device::SK_CY, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2514		{&upd7810_device::SK_Z, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2515		{&upd7810_device::PUSH_VA, 2,17,17,L0\|L1}, {&upd7810_device::POP_VA, 2,15,15,L0\|L1},
2516
2517		{&upd7810_device::SKNIT_F0, 2, 8, 8,L0\|L1}, {&upd7810_device::SKNIT_FT0, 2, 8, 8,L0\|L1},
2518		{&upd7810_device::SKNIT_F1, 2, 8, 8,L0\|L1}, {&upd7810_device::SKNIT_F2, 2, 8, 8,L0\|L1},
2519		{&upd7810_device::SKNIT_FST, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2520		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2521		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal, 2, 8, 8,L0\|L1},
2522		{&upd7810_device::SKN_CY, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2523		{&upd7810_device::SKN_Z, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2524		{&upd7810_device::PUSH_BC, 2,17,17,L0\|L1}, {&upd7810_device::POP_BC, 2,15,15,L0\|L1},
2525
2526		/* 0x20 - 0x3F */
2527		{&upd7810_device::EI, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2528		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2529		{&upd7810_device::DI, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2530		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2531		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2532		{&upd7810_device::CLC, 2, 8, 8,L0\|L1}, {&upd7810_device::STC, 2, 8, 8,L0\|L1},
2533		{&upd7810_device::PEN, 2,11,11,L0\|L1}, {&upd7810_device::PEX, 2,11,11,L0\|L1},
2534		{&upd7810_device::PUSH_DE, 2,17,17,L0\|L1}, {&upd7810_device::POP_DE, 2,15,15,L0\|L1},
2535
2536		{&upd7810_device::RLL_A, 2, 8, 8,L0\|L1}, {&upd7810_device::RLR_A, 2, 8, 8,L0\|L1},
2537		{&upd7810_device::RLL_C, 2, 8, 8,L0\|L1}, {&upd7810_device::RLR_C, 2, 8, 8,L0\|L1},
2538		{&upd7810_device::SLL_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SLR_A, 2, 8, 8,L0\|L1},
2539		{&upd7810_device::SLL_C, 2, 8, 8,L0\|L1}, {&upd7810_device::SLR_C, 2, 8, 8,L0\|L1},
2540		{&upd7810_device::RLD, 2,17,17,L0\|L1}, {&upd7810_device::RRD, 2,17,17,L0\|L1},
2541		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2542		{&upd7810_device::PER, 2,11,11,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2543		{&upd7810_device::PUSH_HL, 2,17,17,L0\|L1}, {&upd7810_device::POP_HL, 2,15,15,L0\|L1},
2544
2545		/* 0x40 - 0x5F */
2546		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2547		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2548		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2549		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2550		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2551		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2552		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2553		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2554
2555		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2556		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2557		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2558		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2559		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2560		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2561		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2562		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2563
2564		/* 0x60 - 0x7F */
2565		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2566		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2567		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2568		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2569		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2570		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2571		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2572		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2573
2574		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2575		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2576		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2577		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2578		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2579		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2580		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2581		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2582
2583		/* 0x80 - 0x9F */
2584		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2585		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2586		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2587		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2588		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2589		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2590		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2591		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2592
2593		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2594		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2595		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2596		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2597		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2598		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2599		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2600		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2601
2602		/* 0xA0 - 0xBF */
2603		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2604		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2605		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2606		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2607		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2608		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2609		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2610		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2611
2612		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2613		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2614		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2615		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2616		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2617		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2618		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2619		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2620
2621		/* 0xC0 - 0xDF */
2622		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2623		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2624		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2625		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2626		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2627		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2628		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2629		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2630
2631		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2632		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2633		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2634		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2635		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2636		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2637		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2638		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2639
2640		/* 0xE0 - 0xFF */
2641		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2642		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2643		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2644		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2645		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2646		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2647		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2648		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2649
2650		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2651		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2652		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2653		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2654		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2655		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2656		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2657		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
2658		};
2659
2660		const struct upd7810_device::opcode_s upd7810_device::s_op4C_7801[256] =
2661		{
2662		/* 0x00 - 0x1F */
2663		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2664		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2665		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2666		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2667		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2668		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2669		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2670		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2671
2672		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2673		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2674		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2675		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2676		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2677		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2678		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2679		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2680
2681		/* 0x20 - 0x3F */
2682		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2683		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2684		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2685		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2686		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2687		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2688		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2689		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2690
2691		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2692		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2693		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2694		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2695		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2696		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2697		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2698		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2699
2700		/* 0x40 - 0x5F */
2701		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2702		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2703		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2704		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2705		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2706		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2707		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2708		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2709
2710		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2711		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2712		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2713		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2714		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2715		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2716		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2717		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2718
2719		/* 0x60 - 0x7F */
2720		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2721		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2722		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2723		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2724		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2725		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2726		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2727		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2728
2729		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2730		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2731		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2732		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2733		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2734		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2735		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2736		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2737
2738		/* 0x80 - 0x9F */
2739		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2740		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2741		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2742		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2743		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2744		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2745		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2746		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2747
2748		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2749		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2750		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2751		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2752		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2753		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2754		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2755		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2756
2757		/* 0xA0 - 0xBF */
2758		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2759		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2760		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2761		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2762		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2763		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2764		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2765		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2766
2767		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2768		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2769		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2770		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2771		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2772		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2773		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2774		{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
2775
2776		/* 0xC0 - 0xDF */
2777		{&upd7810_device::MOV_A_PA, 2,10,10,L0\|L1}, {&upd7810_device::MOV_A_PB, 2,10,10,L0\|L1},
2778		{&upd7810_device::MOV_A_PC, 2,10,10,L0\|L1}, {&upd7810_device::MOV_A_MKL, 2,10,10,L0\|L1},
2779		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2780		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2781		{&upd7810_device::MOV_A_S, 2,10,10,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2782		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2783		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2784		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2785
2786		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2787		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2788		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2789		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2790		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2791		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2792		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2793		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2794
2795		/* 0xE0 - 0xFF */
2796		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2797		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2798		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2799		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2800		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2801		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2802		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2803		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2804
2805		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2806		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2807		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2808		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2809		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2810		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2811		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2812		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
2813		};
2814
2815		/* prefix 4D */
2816		const struct upd7810_device::opcode_s upd7810_device::s_op4D_7801[256] =
2817		{
2818		/* 0x00 - 0x1F */
2819		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2820		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2821		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2822		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2823		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2824		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2825		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2826		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2827
2828		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2829		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2830		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2831		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2832		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2833		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2834		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2835		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2836
2837		/* 0x20 - 0x3F */
2838		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2839		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2840		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2841		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2842		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2843		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2844		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2845		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2846
2847		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2848		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2849		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2850		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2851		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2852		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2853		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2854		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2855
2856		/* 0x40 - 0x5F */
2857		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2858		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2859		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2860		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2861		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2862		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2863		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2864		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2865
2866		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2867		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2868		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2869		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2870		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2871		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2872		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2873		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2874
2875		/* 0x60 - 0x7F */
2876		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2877		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2878		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2879		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2880		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2881		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2882		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2883		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2884
2885		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2886		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2887		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2888		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2889		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2890		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2891		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2892		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2893
2894		/* 0x80 - 0x9F */
2895		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2896		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2897		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2898		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2899		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2900		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2901		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2902		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2903
2904		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2905		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2906		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2907		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2908		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2909		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2910		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2911		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2912
2913		/* 0xA0 - 0xBF */
2914		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2915		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2916		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2917		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2918		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2919		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2920		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2921		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2922
2923		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2924		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2925		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2926		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2927		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2928		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2929		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2930		{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
2931
2932		/* 0xC0 - 0xDF */
2933		{&upd7810_device::MOV_PA_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_PB_A, 2,10,10,L0\|L1},
2934		{&upd7810_device::MOV_PC_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_MKL_A, 2,10,10,L0\|L1},
2935		{&upd7810_device::MOV_MB_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_MC_A_7801, 2,10,10,L0\|L1},
2936		{&upd7810_device::MOV_TM0_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_TM1_A, 2,10,10,L0\|L1},
2937		{&upd7810_device::MOV_S_A, 2,10,10,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2938		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2939		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2940		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2941
2942		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2943		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2944		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2945		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2946		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2947		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2948		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2949		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2950
2951		/* 0xE0 - 0xFF */
2952		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2953		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2954		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2955		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2956		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2957		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2958		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2959		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2960
2961		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2962		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2963		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2964		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2965		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2966		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2967		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2968		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
2969		};
2970
2971		/* prefix 60 */
2972		const struct upd7810_device::opcode_s upd7810_device::s_op60_7801[256] =
2973		{
2974		/* 0x00 - 0x1F */
2975		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2976		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2977		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2978		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
2979		{&upd7810_device::ANA_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_A, 2, 8, 8,L0\|L1},
2980		{&upd7810_device::ANA_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_C_A, 2, 8, 8,L0\|L1},
2981		{&upd7810_device::ANA_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_E_A, 2, 8, 8,L0\|L1},
2982		{&upd7810_device::ANA_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_L_A, 2, 8, 8,L0\|L1},
2983
2984		{&upd7810_device::XRA_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_A, 2, 8, 8,L0\|L1},
2985		{&upd7810_device::XRA_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_C_A, 2, 8, 8,L0\|L1},
2986		{&upd7810_device::XRA_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_E_A, 2, 8, 8,L0\|L1},
2987		{&upd7810_device::XRA_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_L_A, 2, 8, 8,L0\|L1},
2988		{&upd7810_device::ORA_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_A, 2, 8, 8,L0\|L1},
2989		{&upd7810_device::ORA_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_C_A, 2, 8, 8,L0\|L1},
2990		{&upd7810_device::ORA_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_E_A, 2, 8, 8,L0\|L1},
2991		{&upd7810_device::ORA_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_L_A, 2, 8, 8,L0\|L1},
2992
2993		/* 0x20 - 0x3F */
2994		{&upd7810_device::ADDNC_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_A, 2, 8, 8,L0\|L1},
2995		{&upd7810_device::ADDNC_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_C_A, 2, 8, 8,L0\|L1},
2996		{&upd7810_device::ADDNC_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_E_A, 2, 8, 8,L0\|L1},
2997		{&upd7810_device::ADDNC_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_L_A, 2, 8, 8,L0\|L1},
2998		{&upd7810_device::GTA_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_A, 2, 8, 8,L0\|L1},
2999		{&upd7810_device::GTA_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_C_A, 2, 8, 8,L0\|L1},
3000		{&upd7810_device::GTA_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_E_A, 2, 8, 8,L0\|L1},
3001		{&upd7810_device::GTA_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_L_A, 2, 8, 8,L0\|L1},
3002
3003		{&upd7810_device::SUBNB_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_A, 2, 8, 8,L0\|L1},
3004		{&upd7810_device::SUBNB_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_C_A, 2, 8, 8,L0\|L1},
3005		{&upd7810_device::SUBNB_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_E_A, 2, 8, 8,L0\|L1},
3006		{&upd7810_device::SUBNB_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_L_A, 2, 8, 8,L0\|L1},
3007		{&upd7810_device::LTA_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_A, 2, 8, 8,L0\|L1},
3008		{&upd7810_device::LTA_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_C_A, 2, 8, 8,L0\|L1},
3009		{&upd7810_device::LTA_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_E_A, 2, 8, 8,L0\|L1},
3010		{&upd7810_device::LTA_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_L_A, 2, 8, 8,L0\|L1},
3011
3012		/* 0x40 - 0x5F */
3013		{&upd7810_device::ADD_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_A, 2, 8, 8,L0\|L1},
3014		{&upd7810_device::ADD_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_C_A, 2, 8, 8,L0\|L1},
3015		{&upd7810_device::ADD_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_E_A, 2, 8, 8,L0\|L1},
3016		{&upd7810_device::ADD_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_L_A, 2, 8, 8,L0\|L1},
3017		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3018		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3019		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3020		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3021
3022		{&upd7810_device::ADC_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_A, 2, 8, 8,L0\|L1},
3023		{&upd7810_device::ADC_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_C_A, 2, 8, 8,L0\|L1},
3024		{&upd7810_device::ADC_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_E_A, 2, 8, 8,L0\|L1},
3025		{&upd7810_device::ADC_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_L_A, 2, 8, 8,L0\|L1},
3026		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3027		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3028		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3029		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3030
3031		/* 0x60 - 0x7F */
3032		{&upd7810_device::SUB_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_A, 2, 8, 8,L0\|L1},
3033		{&upd7810_device::SUB_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_C_A, 2, 8, 8,L0\|L1},
3034		{&upd7810_device::SUB_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_E_A, 2, 8, 8,L0\|L1},
3035		{&upd7810_device::SUB_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_L_A, 2, 8, 8,L0\|L1},
3036		{&upd7810_device::NEA_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_A, 2, 8, 8,L0\|L1},
3037		{&upd7810_device::NEA_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_C_A, 2, 8, 8,L0\|L1},
3038		{&upd7810_device::NEA_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_E_A, 2, 8, 8,L0\|L1},
3039		{&upd7810_device::NEA_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_L_A, 2, 8, 8,L0\|L1},
3040
3041		{&upd7810_device::SBB_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_A, 2, 8, 8,L0\|L1},
3042		{&upd7810_device::SBB_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_C_A, 2, 8, 8,L0\|L1},
3043		{&upd7810_device::SBB_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_E_A, 2, 8, 8,L0\|L1},
3044		{&upd7810_device::SBB_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_L_A, 2, 8, 8,L0\|L1},
3045		{&upd7810_device::EQA_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_A, 2, 8, 8,L0\|L1},
3046		{&upd7810_device::EQA_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_C_A, 2, 8, 8,L0\|L1},
3047		{&upd7810_device::EQA_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_E_A, 2, 8, 8,L0\|L1},
3048		{&upd7810_device::EQA_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_L_A, 2, 8, 8,L0\|L1},
3049
3050		/* 0x80 - 0x9F */
3051		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3052		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3053		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3054		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3055		{&upd7810_device::ANA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_A, 2, 8, 8,L0\|L1},
3056		{&upd7810_device::ANA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_C, 2, 8, 8,L0\|L1},
3057		{&upd7810_device::ANA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_E, 2, 8, 8,L0\|L1},
3058		{&upd7810_device::ANA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_L, 2, 8, 8,L0\|L1},
3059
3060		{&upd7810_device::XRA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_A, 2, 8, 8,L0\|L1},
3061		{&upd7810_device::XRA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_C, 2, 8, 8,L0\|L1},
3062		{&upd7810_device::XRA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_E, 2, 8, 8,L0\|L1},
3063		{&upd7810_device::XRA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_L, 2, 8, 8,L0\|L1},
3064		{&upd7810_device::ORA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_A, 2, 8, 8,L0\|L1},
3065		{&upd7810_device::ORA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_C, 2, 8, 8,L0\|L1},
3066		{&upd7810_device::ORA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_E, 2, 8, 8,L0\|L1},
3067		{&upd7810_device::ORA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_L, 2, 8, 8,L0\|L1},
3068
3069		/* 0xA0 - 0xBF */
3070		{&upd7810_device::ADDNC_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_A, 2, 8, 8,L0\|L1},
3071		{&upd7810_device::ADDNC_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_C, 2, 8, 8,L0\|L1},
3072		{&upd7810_device::ADDNC_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_E, 2, 8, 8,L0\|L1},
3073		{&upd7810_device::ADDNC_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_L, 2, 8, 8,L0\|L1},
3074		{&upd7810_device::GTA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_A, 2, 8, 8,L0\|L1},
3075		{&upd7810_device::GTA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_C, 2, 8, 8,L0\|L1},
3076		{&upd7810_device::GTA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_E, 2, 8, 8,L0\|L1},
3077		{&upd7810_device::GTA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_L, 2, 8, 8,L0\|L1},
3078
3079		{&upd7810_device::SUBNB_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_A, 2, 8, 8,L0\|L1},
3080		{&upd7810_device::SUBNB_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_C, 2, 8, 8,L0\|L1},
3081		{&upd7810_device::SUBNB_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_E, 2, 8, 8,L0\|L1},
3082		{&upd7810_device::SUBNB_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_L, 2, 8, 8,L0\|L1},
3083		{&upd7810_device::LTA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_A, 2, 8, 8,L0\|L1},
3084		{&upd7810_device::LTA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_C, 2, 8, 8,L0\|L1},
3085		{&upd7810_device::LTA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_E, 2, 8, 8,L0\|L1},
3086		{&upd7810_device::LTA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_L, 2, 8, 8,L0\|L1},
3087
3088		/* 0xC0 - 0xDF */
3089		{&upd7810_device::ADD_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_A, 2, 8, 8,L0\|L1},
3090		{&upd7810_device::ADD_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_C, 2, 8, 8,L0\|L1},
3091		{&upd7810_device::ADD_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_E, 2, 8, 8,L0\|L1},
3092		{&upd7810_device::ADD_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_L, 2, 8, 8,L0\|L1},
3093		{&upd7810_device::ONA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::ONA_A_A, 2, 8, 8,L0\|L1},
3094		{&upd7810_device::ONA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ONA_A_C, 2, 8, 8,L0\|L1},
3095		{&upd7810_device::ONA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ONA_A_E, 2, 8, 8,L0\|L1},
3096		{&upd7810_device::ONA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ONA_A_L, 2, 8, 8,L0\|L1},
3097
3098		{&upd7810_device::ADC_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_A, 2, 8, 8,L0\|L1},
3099		{&upd7810_device::ADC_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_C, 2, 8, 8,L0\|L1},
3100		{&upd7810_device::ADC_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_E, 2, 8, 8,L0\|L1},
3101		{&upd7810_device::ADC_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_L, 2, 8, 8,L0\|L1},
3102		{&upd7810_device::OFFA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFA_A_A, 2, 8, 8,L0\|L1},
3103		{&upd7810_device::OFFA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFA_A_C, 2, 8, 8,L0\|L1},
3104		{&upd7810_device::OFFA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFA_A_E, 2, 8, 8,L0\|L1},
3105		{&upd7810_device::OFFA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFA_A_L, 2, 8, 8,L0\|L1},
3106
3107		/* 0xE0 - 0xFF */
3108		{&upd7810_device::SUB_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_A, 2, 8, 8,L0\|L1},
3109		{&upd7810_device::SUB_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_C, 2, 8, 8,L0\|L1},
3110		{&upd7810_device::SUB_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_E, 2, 8, 8,L0\|L1},
3111		{&upd7810_device::SUB_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_L, 2, 8, 8,L0\|L1},
3112		{&upd7810_device::NEA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_A, 2, 8, 8,L0\|L1},
3113		{&upd7810_device::NEA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_C, 2, 8, 8,L0\|L1},
3114		{&upd7810_device::NEA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_E, 2, 8, 8,L0\|L1},
3115		{&upd7810_device::NEA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_L, 2, 8, 8,L0\|L1},
3116
3117		{&upd7810_device::SBB_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_A, 2, 8, 8,L0\|L1},
3118		{&upd7810_device::SBB_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_C, 2, 8, 8,L0\|L1},
3119		{&upd7810_device::SBB_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_E, 2, 8, 8,L0\|L1},
3120		{&upd7810_device::SBB_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_L, 2, 8, 8,L0\|L1},
3121		{&upd7810_device::EQA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_A, 2, 8, 8,L0\|L1},
3122		{&upd7810_device::EQA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_C, 2, 8, 8,L0\|L1},
3123		{&upd7810_device::EQA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_E, 2, 8, 8,L0\|L1},
3124		{&upd7810_device::EQA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_L, 2, 8, 8,L0\|L1}
3125		};
3126
3127		/* prefix 64 */
3128		const struct upd7810_device::opcode_s upd7810_device::s_op64_7801[256] =
3129		{
3130		/* 0x00 - 0x1F */
3131		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3132		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3133		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3134		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3135		{&upd7810_device::ANI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::ANI_A_xx, 3,11,11,L0\|L1},
3136		{&upd7810_device::ANI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::ANI_C_xx, 3,11,11,L0\|L1},
3137		{&upd7810_device::ANI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::ANI_E_xx, 3,11,11,L0\|L1},
3138		{&upd7810_device::ANI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::ANI_L_xx, 3,11,11,L0\|L1},
3139
3140		{&upd7810_device::XRI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::XRI_A_xx, 3,11,11,L0\|L1},
3141		{&upd7810_device::XRI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::XRI_C_xx, 3,11,11,L0\|L1},
3142		{&upd7810_device::XRI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::XRI_E_xx, 3,11,11,L0\|L1},
3143		{&upd7810_device::XRI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::XRI_L_xx, 3,11,11,L0\|L1},
3144		{&upd7810_device::ORI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::ORI_A_xx, 3,11,11,L0\|L1},
3145		{&upd7810_device::ORI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::ORI_C_xx, 3,11,11,L0\|L1},
3146		{&upd7810_device::ORI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::ORI_E_xx, 3,11,11,L0\|L1},
3147		{&upd7810_device::ORI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::ORI_L_xx, 3,11,11,L0\|L1},
3148
3149		/* 0x20 - 0x3F */
3150		{&upd7810_device::ADINC_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::ADINC_A_xx, 3,11,11,L0\|L1},
3151		{&upd7810_device::ADINC_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::ADINC_C_xx, 3,11,11,L0\|L1},
3152		{&upd7810_device::ADINC_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::ADINC_E_xx, 3,11,11,L0\|L1},
3153		{&upd7810_device::ADINC_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::ADINC_L_xx, 3,11,11,L0\|L1},
3154		{&upd7810_device::GTI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::GTI_A_xx, 3,11,11,L0\|L1},
3155		{&upd7810_device::GTI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::GTI_C_xx, 3,11,11,L0\|L1},
3156		{&upd7810_device::GTI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::GTI_E_xx, 3,11,11,L0\|L1},
3157		{&upd7810_device::GTI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::GTI_L_xx, 3,11,11,L0\|L1},
3158
3159		{&upd7810_device::SUINB_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::SUINB_A_xx, 3,11,11,L0\|L1},
3160		{&upd7810_device::SUINB_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::SUINB_C_xx, 3,11,11,L0\|L1},
3161		{&upd7810_device::SUINB_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::SUINB_E_xx, 3,11,11,L0\|L1},
3162		{&upd7810_device::SUINB_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::SUINB_L_xx, 3,11,11,L0\|L1},
3163		{&upd7810_device::LTI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::LTI_A_xx, 3,11,11,L0\|L1},
3164		{&upd7810_device::LTI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::LTI_C_xx, 3,11,11,L0\|L1},
3165		{&upd7810_device::LTI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::LTI_E_xx, 3,11,11,L0\|L1},
3166		{&upd7810_device::LTI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::LTI_L_xx, 3,11,11,L0\|L1},
3167
3168		/* 0x40 - 0x5F */
3169		{&upd7810_device::ADI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::ADI_A_xx, 3,11,11,L0\|L1},
3170		{&upd7810_device::ADI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::ADI_C_xx, 3,11,11,L0\|L1},
3171		{&upd7810_device::ADI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::ADI_E_xx, 3,11,11,L0\|L1},
3172		{&upd7810_device::ADI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::ADI_L_xx, 3,11,11,L0\|L1},
3173		{&upd7810_device::ONI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::ONI_A_xx, 3,11,11,L0\|L1},
3174		{&upd7810_device::ONI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::ONI_C_xx, 3,11,11,L0\|L1},
3175		{&upd7810_device::ONI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::ONI_E_xx, 3,11,11,L0\|L1},
3176		{&upd7810_device::ONI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::ONI_L_xx, 3,11,11,L0\|L1},
3177
3178		{&upd7810_device::ACI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::ACI_A_xx, 3,11,11,L0\|L1},
3179		{&upd7810_device::ACI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::ACI_C_xx, 3,11,11,L0\|L1},
3180		{&upd7810_device::ACI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::ACI_E_xx, 3,11,11,L0\|L1},
3181		{&upd7810_device::ACI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::ACI_L_xx, 3,11,11,L0\|L1},
3182		{&upd7810_device::OFFI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::OFFI_A_xx, 3,11,11,L0\|L1},
3183		{&upd7810_device::OFFI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::OFFI_C_xx, 3,11,11,L0\|L1},
3184		{&upd7810_device::OFFI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::OFFI_E_xx, 3,11,11,L0\|L1},
3185		{&upd7810_device::OFFI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::OFFI_L_xx, 3,11,11,L0\|L1},
3186
3187		/* 0x60 - 0x7F */
3188		{&upd7810_device::SUI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::SUI_A_xx, 3,11,11,L0\|L1},
3189		{&upd7810_device::SUI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::SUI_C_xx, 3,11,11,L0\|L1},
3190		{&upd7810_device::SUI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::SUI_E_xx, 3,11,11,L0\|L1},
3191		{&upd7810_device::SUI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::SUI_L_xx, 3,11,11,L0\|L1},
3192		{&upd7810_device::NEI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::NEI_A_xx, 3,11,11,L0\|L1},
3193		{&upd7810_device::NEI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::NEI_C_xx, 3,11,11,L0\|L1},
3194		{&upd7810_device::NEI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::NEI_E_xx, 3,11,11,L0\|L1},
3195		{&upd7810_device::NEI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::NEI_L_xx, 3,11,11,L0\|L1},
3196
3197		{&upd7810_device::SBI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::SBI_A_xx, 3,11,11,L0\|L1},
3198		{&upd7810_device::SBI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::SBI_C_xx, 3,11,11,L0\|L1},
3199		{&upd7810_device::SBI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::SBI_E_xx, 3,11,11,L0\|L1},
3200		{&upd7810_device::SBI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::SBI_L_xx, 3,11,11,L0\|L1},
3201		{&upd7810_device::EQI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::EQI_A_xx, 3,11,11,L0\|L1},
3202		{&upd7810_device::EQI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::EQI_C_xx, 3,11,11,L0\|L1},
3203		{&upd7810_device::EQI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::EQI_E_xx, 3,11,11,L0\|L1},
3204		{&upd7810_device::EQI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::EQI_L_xx, 3,11,11,L0\|L1},
3205
3206		/* 0x80 - 0x9F */
3207		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3208		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3209		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3210		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3211		{&upd7810_device::ANI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ANI_PB_xx, 3,17,17,L0\|L1},
3212		{&upd7810_device::ANI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ANI_MKL_xx, 3,17,17,L0\|L1},
3213		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3214		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3215
3216		{&upd7810_device::XRI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::XRI_PB_xx, 3,17,17,L0\|L1},
3217		{&upd7810_device::XRI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::XRI_MKL_xx, 3,17,17,L0\|L1},
3218		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3219		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3220		{&upd7810_device::ORI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ORI_PB_xx, 3,17,17,L0\|L1},
3221		{&upd7810_device::ORI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ORI_MKL_xx, 3,17,17,L0\|L1},
3222		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3223		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3224
3225		/* 0xA0 - 0xBF */
3226		{&upd7810_device::ADINC_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ADINC_PB_xx, 3,17,17,L0\|L1},
3227		{&upd7810_device::ADINC_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ADINC_MKL_xx, 3,17,17,L0\|L1},
3228		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3229		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3230		{&upd7810_device::GTI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::GTI_PB_xx, 3,14,14,L0\|L1},
3231		{&upd7810_device::GTI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::GTI_MKL_xx, 3,14,14,L0\|L1},
3232		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3233		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3234
3235		{&upd7810_device::SUINB_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::SUINB_PB_xx, 3,17,17,L0\|L1},
3236		{&upd7810_device::SUINB_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::SUINB_MKL_xx, 3,17,17,L0\|L1},
3237		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3238		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3239		{&upd7810_device::LTI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::LTI_PB_xx, 3,14,14,L0\|L1},
3240		{&upd7810_device::LTI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::LTI_MKL_xx, 3,14,14,L0\|L1},
3241		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3242		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3243
3244		/* 0xC0 - 0xDF */
3245		{&upd7810_device::ADI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ADI_PB_xx, 3,17,17,L0\|L1},
3246		{&upd7810_device::ADI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ADI_MKL_xx, 3,17,17,L0\|L1},
3247		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3248		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3249		{&upd7810_device::ONI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::ONI_PB_xx, 3,14,14,L0\|L1},
3250		{&upd7810_device::ONI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::ONI_MKL_xx, 3,14,14,L0\|L1},
3251		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3252		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3253
3254		{&upd7810_device::ACI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ACI_PB_xx, 3,17,17,L0\|L1},
3255		{&upd7810_device::ACI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ACI_MKL_xx, 3,17,17,L0\|L1},
3256		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3257		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3258		{&upd7810_device::OFFI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::OFFI_PB_xx, 3,14,14,L0\|L1},
3259		{&upd7810_device::OFFI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::OFFI_MKL_xx, 3,14,14,L0\|L1},
3260		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3261		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3262
3263		/* 0xE0 - 0xFF */
3264		{&upd7810_device::SUI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::SUI_PB_xx, 3,17,17,L0\|L1},
3265		{&upd7810_device::SUI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::SUI_MKL_xx, 3,17,17,L0\|L1},
3266		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3267		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3268		{&upd7810_device::NEI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::NEI_PB_xx, 3,14,14,L0\|L1},
3269		{&upd7810_device::NEI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::NEI_MKL_xx, 3,14,14,L0\|L1},
3270		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3271		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3272
3273		{&upd7810_device::SBI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::SBI_PB_xx, 3,17,17,L0\|L1},
3274		{&upd7810_device::SBI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::SBI_MKL_xx, 3,17,17,L0\|L1},
3275		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3276		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3277		{&upd7810_device::EQI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::EQI_PB_xx, 3,14,14,L0\|L1},
3278		{&upd7810_device::EQI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::EQI_MKL_xx, 3,14,14,L0\|L1},
3279		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3280		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
3281		};
3282
3283		/* prefix 70 */
3284		const struct upd7810_device::opcode_s upd7810_device::s_op70_7801[256] =
3285		{
3286		/* 0x00 - 0x1F */
3287		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3288		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3289		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3290		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3291		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3292		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3293		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3294		{&upd7810_device::SSPD_w, 4,20,20,L0\|L1}, {&upd7810_device::LSPD_w, 4,20,20,L0\|L1},
3295
3296		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3297		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3298		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3299		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3300		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3301		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3302		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3303		{&upd7810_device::SBCD_w, 4,20,20,L0\|L1}, {&upd7810_device::LBCD_w, 4,20,20,L0\|L1},
3304
3305		/* 0x20 - 0x3F */
3306		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3307		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3308		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3309		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3310		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3311		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3312		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3313		{&upd7810_device::SDED_w, 4,20,20,L0\|L1}, {&upd7810_device::LDED_w, 4,20,20,L0\|L1},
3314
3315		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3316		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3317		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3318		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3319		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3320		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3321		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3322		{&upd7810_device::SHLD_w, 4,20,20,L0\|L1}, {&upd7810_device::LHLD_w, 4,20,20,L0\|L1},
3323
3324		/* 0x40 - 0x5F */
3325		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3326		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3327		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3328		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3329		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3330		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3331		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3332		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3333
3334		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3335		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3336		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3337		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3338		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3339		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3340		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3341		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3342
3343		/* 0x60 - 0x7F */
3344		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3345		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3346		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3347		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3348		{&upd7810_device::MOV_V_w, 4,17,17,L0\|L1}, {&upd7810_device::MOV_A_w, 4,17,17,L0\|L1},
3349		{&upd7810_device::MOV_B_w, 4,17,17,L0\|L1}, {&upd7810_device::MOV_C_w, 4,17,17,L0\|L1},
3350		{&upd7810_device::MOV_D_w, 4,17,17,L0\|L1}, {&upd7810_device::MOV_E_w, 4,17,17,L0\|L1},
3351		{&upd7810_device::MOV_H_w, 4,17,17,L0\|L1}, {&upd7810_device::MOV_L_w, 4,17,17,L0\|L1},
3352
3353		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3354		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3355		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3356		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3357		{&upd7810_device::MOV_w_V, 4,17,17,L0\|L1}, {&upd7810_device::MOV_w_A, 4,17,17,L0\|L1},
3358		{&upd7810_device::MOV_w_B, 4,17,17,L0\|L1}, {&upd7810_device::MOV_w_C, 4,17,17,L0\|L1},
3359		{&upd7810_device::MOV_w_D, 4,17,17,L0\|L1}, {&upd7810_device::MOV_w_E, 4,17,17,L0\|L1},
3360		{&upd7810_device::MOV_w_H, 4,17,17,L0\|L1}, {&upd7810_device::MOV_w_L, 4,17,17,L0\|L1},
3361
3362		/* 0x80 - 0x9F */
3363		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3364		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3365		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3366		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3367		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ANAX_B, 2,11,11,L0\|L1},
3368		{&upd7810_device::ANAX_D, 2,11,11,L0\|L1}, {&upd7810_device::ANAX_H, 2,11,11,L0\|L1},
3369		{&upd7810_device::ANAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ANAX_Hp, 2,11,11,L0\|L1},
3370		{&upd7810_device::ANAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ANAX_Hm, 2,11,11,L0\|L1},
3371
3372		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::XRAX_B, 2,11,11,L0\|L1},
3373		{&upd7810_device::XRAX_D, 2,11,11,L0\|L1}, {&upd7810_device::XRAX_H, 2,11,11,L0\|L1},
3374		{&upd7810_device::XRAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::XRAX_Hp, 2,11,11,L0\|L1},
3375		{&upd7810_device::XRAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::XRAX_Hm, 2,11,11,L0\|L1},
3376		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ORAX_B, 2,11,11,L0\|L1},
3377		{&upd7810_device::ORAX_D, 2,11,11,L0\|L1}, {&upd7810_device::ORAX_H, 2,11,11,L0\|L1},
3378		{&upd7810_device::ORAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ORAX_Hp, 2,11,11,L0\|L1},
3379		{&upd7810_device::ORAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ORAX_Hm, 2,11,11,L0\|L1},
3380
3381		/* 0xA0 - 0xBF */
3382		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNCX_B, 2,11,11,L0\|L1},
3383		{&upd7810_device::ADDNCX_D, 2,11,11,L0\|L1}, {&upd7810_device::ADDNCX_H, 2,11,11,L0\|L1},
3384		{&upd7810_device::ADDNCX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ADDNCX_Hp, 2,11,11,L0\|L1},
3385		{&upd7810_device::ADDNCX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ADDNCX_Hm, 2,11,11,L0\|L1},
3386		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::GTAX_B, 2,11,11,L0\|L1},
3387		{&upd7810_device::GTAX_D, 2,11,11,L0\|L1}, {&upd7810_device::GTAX_H, 2,11,11,L0\|L1},
3388		{&upd7810_device::GTAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::GTAX_Hp, 2,11,11,L0\|L1},
3389		{&upd7810_device::GTAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::GTAX_Hm, 2,11,11,L0\|L1},
3390
3391		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNBX_B, 2,11,11,L0\|L1},
3392		{&upd7810_device::SUBNBX_D, 2,11,11,L0\|L1}, {&upd7810_device::SUBNBX_H, 2,11,11,L0\|L1},
3393		{&upd7810_device::SUBNBX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::SUBNBX_Hp, 2,11,11,L0\|L1},
3394		{&upd7810_device::SUBNBX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::SUBNBX_Hm, 2,11,11,L0\|L1},
3395		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::LTAX_B, 2,11,11,L0\|L1},
3396		{&upd7810_device::LTAX_D, 2,11,11,L0\|L1}, {&upd7810_device::LTAX_H, 2,11,11,L0\|L1},
3397		{&upd7810_device::LTAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::LTAX_Hp, 2,11,11,L0\|L1},
3398		{&upd7810_device::LTAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::LTAX_Hm, 2,11,11,L0\|L1},
3399
3400		/* 0xC0 - 0xDF */
3401		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDX_B, 2,11,11,L0\|L1},
3402		{&upd7810_device::ADDX_D, 2,11,11,L0\|L1}, {&upd7810_device::ADDX_H, 2,11,11,L0\|L1},
3403		{&upd7810_device::ADDX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ADDX_Hp, 2,11,11,L0\|L1},
3404		{&upd7810_device::ADDX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ADDX_Hm, 2,11,11,L0\|L1},
3405		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ONAX_B, 2,11,11,L0\|L1},
3406		{&upd7810_device::ONAX_D, 2,11,11,L0\|L1}, {&upd7810_device::ONAX_H, 2,11,11,L0\|L1},
3407		{&upd7810_device::ONAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ONAX_Hp, 2,11,11,L0\|L1},
3408		{&upd7810_device::ONAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ONAX_Hm, 2,11,11,L0\|L1},
3409
3410		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADCX_B, 2,11,11,L0\|L1},
3411		{&upd7810_device::ADCX_D, 2,11,11,L0\|L1}, {&upd7810_device::ADCX_H, 2,11,11,L0\|L1},
3412		{&upd7810_device::ADCX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ADCX_Hp, 2,11,11,L0\|L1},
3413		{&upd7810_device::ADCX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ADCX_Hm, 2,11,11,L0\|L1},
3414		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFAX_B, 2,11,11,L0\|L1},
3415		{&upd7810_device::OFFAX_D, 2,11,11,L0\|L1}, {&upd7810_device::OFFAX_H, 2,11,11,L0\|L1},
3416		{&upd7810_device::OFFAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::OFFAX_Hp, 2,11,11,L0\|L1},
3417		{&upd7810_device::OFFAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::OFFAX_Hm, 2,11,11,L0\|L1},
3418
3419		/* 0xE0 - 0xFF */
3420		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBX_B, 2,11,11,L0\|L1},
3421		{&upd7810_device::SUBX_D, 2,11,11,L0\|L1}, {&upd7810_device::SUBX_H, 2,11,11,L0\|L1},
3422		{&upd7810_device::SUBX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::SUBX_Hp, 2,11,11,L0\|L1},
3423		{&upd7810_device::SUBX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::SUBX_Hm, 2,11,11,L0\|L1},
3424		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::NEAX_B, 2,11,11,L0\|L1},
3425		{&upd7810_device::NEAX_D, 2,11,11,L0\|L1}, {&upd7810_device::NEAX_H, 2,11,11,L0\|L1},
3426		{&upd7810_device::NEAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::NEAX_Hp, 2,11,11,L0\|L1},
3427		{&upd7810_device::NEAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::NEAX_Hm, 2,11,11,L0\|L1},
3428
3429		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SBBX_B, 2,11,11,L0\|L1},
3430		{&upd7810_device::SBBX_D, 2,11,11,L0\|L1}, {&upd7810_device::SBBX_H, 2,11,11,L0\|L1},
3431		{&upd7810_device::SBBX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::SBBX_Hp, 2,11,11,L0\|L1},
3432		{&upd7810_device::SBBX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::SBBX_Hm, 2,11,11,L0\|L1},
3433		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::EQAX_B, 2,11,11,L0\|L1},
3434		{&upd7810_device::EQAX_D, 2,11,11,L0\|L1}, {&upd7810_device::EQAX_H, 2,11,11,L0\|L1},
3435		{&upd7810_device::EQAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::EQAX_Hp, 2,11,11,L0\|L1},
3436		{&upd7810_device::EQAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::EQAX_Hm, 2,11,11,L0\|L1}
3437		};
3438
3439		/* prefix 74 */
3440		const struct upd7810_device::opcode_s upd7810_device::s_op74_7801[256] =
3441		{
3442		/* 0x00 - 0x1F */
3443		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3444		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3445		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3446		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3447		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3448		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3449		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3450		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3451
3452		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3453		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3454		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3455		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3456		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3457		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3458		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3459		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3460
3461		/* 0x20 - 0x3F */
3462		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3463		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3464		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3465		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3466		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3467		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3468		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3469		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3470
3471		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3472		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3473		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3474		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3475		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3476		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3477		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3478		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3479
3480		/* 0x40 - 0x5F */
3481		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3482		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3483		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3484		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3485		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3486		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3487		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3488		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3489
3490		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3491		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3492		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3493		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3494		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3495		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3496		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3497		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3498
3499		/* 0x60 - 0x7F */
3500		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3501		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3502		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3503		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3504		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3505		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3506		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3507		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3508
3509		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3510		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3511		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3512		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3513		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3514		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3515		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3516		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3517
3518		/* 0x80 - 0x9F */
3519		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3520		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3521		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3522		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3523		{&upd7810_device::ANAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3524		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3525		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3526		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3527
3528		{&upd7810_device::XRAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3529		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3530		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3531		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3532		{&upd7810_device::ORAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3533		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3534		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3535		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3536
3537		/* 0xA0 - 0xBF */
3538		{&upd7810_device::ADDNCW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3539		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3540		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3541		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3542		{&upd7810_device::GTAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3543		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3544		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3545		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3546
3547		{&upd7810_device::SUBNBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3548		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3549		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3550		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3551		{&upd7810_device::LTAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3552		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3553		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3554		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3555
3556		/* 0xC0 - 0xDF */
3557		{&upd7810_device::ADDW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3558		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3559		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3560		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3561		{&upd7810_device::ONAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3562		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3563		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3564		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3565
3566		{&upd7810_device::ADCW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3567		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3568		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3569		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3570		{&upd7810_device::OFFAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3571		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3572		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3573		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3574
3575		/* 0xE0 - 0xFF */
3576		{&upd7810_device::SUBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3577		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3578		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3579		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3580		{&upd7810_device::NEAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3581		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3582		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3583		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3584
3585		{&upd7810_device::SBBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3586		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3587		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3588		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3589		{&upd7810_device::EQAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3590		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3591		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3592		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
3593		};
3594
3595		const struct upd7810_device::opcode_s upd7810_device::s_opXX_7801[256] =
3596		{
3597		/* 0x00 - 0x1F */
3598		{&upd7810_device::NOP, 1, 4, 4,L0\|L1}, {&upd7810_device::HALT, 1, 6, 6,L0\|L1},
3599		{&upd7810_device::INX_SP, 1, 7, 7,L0\|L1}, {&upd7810_device::DCX_SP, 1, 7, 7,L0\|L1},
3600		{&upd7810_device::LXI_S_w, 3,10,10,L0\|L1}, {&upd7810_device::ANIW_wa_xx, 3,16,16,L0\|L1},
3601		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::ANI_A_xx, 2, 7, 7,L0\|L1},
3602		{&upd7810_device::RET, 1,11,11,L0\|L1}, {&upd7810_device::SIO, 1, 4, 4,L0\|L1},
3603		{&upd7810_device::MOV_A_B, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_A_C, 1, 4, 4,L0\|L1},
3604		{&upd7810_device::MOV_A_D, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_A_E, 1, 4, 4,L0\|L1},
3605		{&upd7810_device::MOV_A_H, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_A_L, 1, 4, 4,L0\|L1},
3606
3607		{&upd7810_device::EXA, 1, 4, 4,L0\|L1}, {&upd7810_device::EXX, 1, 4, 4,L0\|L1},
3608		{&upd7810_device::INX_BC, 1, 7, 7,L0\|L1}, {&upd7810_device::DCX_BC, 1, 7, 7,L0\|L1},
3609		{&upd7810_device::LXI_B_w, 3,10,10,L0\|L1}, {&upd7810_device::ORIW_wa_xx, 3,16,16,L0\|L1},
3610		{&upd7810_device::XRI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::ORI_A_xx, 2, 7, 7,L0\|L1},
3611		{&upd7810_device::RETS, 1,11,11,L0\|L1}, {&upd7810_device::STM_7801, 1, 4, 4,L0\|L1},
3612		{&upd7810_device::MOV_B_A, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_C_A, 1, 4, 4,L0\|L1},
3613		{&upd7810_device::MOV_D_A, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_E_A, 1, 4, 4,L0\|L1},
3614		{&upd7810_device::MOV_H_A, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_L_A, 1, 4, 4,L0\|L1},
3615
3616		/* 0x20 - 0x3F */
3617		{&upd7810_device::INRW_wa_7801, 2,13,13,L0\|L1}, {&upd7810_device::TABLE, 1,19,19,L0\|L1},
3618		{&upd7810_device::INX_DE, 1, 7, 7,L0\|L1}, {&upd7810_device::DCX_DE, 1, 7, 7,L0\|L1},
3619		{&upd7810_device::LXI_D_w, 3,10,10,L0\|L1}, {&upd7810_device::GTIW_wa_xx, 3,13,13,L0\|L1},
3620		{&upd7810_device::ADINC_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::GTI_A_xx, 2, 7, 7,L0\|L1},
3621		{&upd7810_device::LDAW_wa, 2,10,10,L0\|L1}, {&upd7810_device::LDAX_B, 1, 7, 7,L0\|L1},
3622		{&upd7810_device::LDAX_D, 1, 7, 7,L0\|L1}, {&upd7810_device::LDAX_H, 1, 7, 7,L0\|L1},
3623		{&upd7810_device::LDAX_Dp, 1, 7, 7,L0\|L1}, {&upd7810_device::LDAX_Hp, 1, 7, 7,L0\|L1},
3624		{&upd7810_device::LDAX_Dm, 1, 7, 7,L0\|L1}, {&upd7810_device::LDAX_Hm, 1, 7, 7,L0\|L1},
3625
3626		{&upd7810_device::DCRW_wa_7801, 2,13,13,L0\|L1}, {&upd7810_device::BLOCK, 1,13,13,L0\|L1},
3627		{&upd7810_device::INX_HL, 1, 7, 7,L0\|L1}, {&upd7810_device::DCX_HL, 1, 7, 7,L0\|L1},
3628		{&upd7810_device::LXI_H_w, 3,10,10, L1}, {&upd7810_device::LTIW_wa_xx, 3,13,13,L0\|L1},
3629		{&upd7810_device::SUINB_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::LTI_A_xx, 2, 7, 7,L0\|L1},
3630		{&upd7810_device::STAW_wa, 2,10,10,L0\|L1}, {&upd7810_device::STAX_B, 1, 7, 7,L0\|L1},
3631		{&upd7810_device::STAX_D, 1, 7, 7,L0\|L1}, {&upd7810_device::STAX_H, 1, 7, 7,L0\|L1},
3632		{&upd7810_device::STAX_Dp, 1, 7, 7,L0\|L1}, {&upd7810_device::STAX_Hp, 1, 7, 7,L0\|L1},
3633		{&upd7810_device::STAX_Dm, 1, 7, 7,L0\|L1}, {&upd7810_device::STAX_Hm, 1, 7, 7,L0\|L1},
3634
3635		/* 0x40 - 0x5F */
3636		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::INR_A_7801, 1, 4, 4,L0\|L1},
3637		{&upd7810_device::INR_B_7801, 1, 4, 4,L0\|L1}, {&upd7810_device::INR_C_7801, 1, 4, 4,L0\|L1},
3638		{&upd7810_device::CALL_w, 3,16,16,L0\|L1}, {&upd7810_device::ONIW_wa_xx, 3,13,13,L0\|L1},
3639		{&upd7810_device::ADI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::ONI_A_xx, 2, 7, 7,L0\|L1},
3640		{&upd7810_device::PRE_48, 1, 0, 0,L0\|L1}, {&upd7810_device::MVIX_BC_xx, 2,10,10,L0\|L1},
3641		{&upd7810_device::MVIX_DE_xx, 2,10,10,L0\|L1}, {&upd7810_device::MVIX_HL_xx, 2,10,10,L0\|L1},
3642		{&upd7810_device::PRE_4C, 1, 0, 0,L0\|L1}, {&upd7810_device::PRE_4D, 1, 0, 0,L0\|L1},
3643		{&upd7810_device::JRE, 2,17,17,L0\|L1}, {&upd7810_device::JRE, 2,17,17,L0\|L1},
3644
3645		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::DCR_A_7801, 1, 4, 4,L0\|L1},
3646		{&upd7810_device::DCR_B_7801, 1, 4, 4,L0\|L1}, {&upd7810_device::DCR_C_7801, 1, 4, 4,L0\|L1},
3647		{&upd7810_device::JMP_w, 3,10,10,L0\|L1}, {&upd7810_device::OFFIW_wa_xx, 3,13,13,L0\|L1},
3648		{&upd7810_device::ACI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::OFFI_A_xx, 2, 7, 7,L0\|L1},
3649		{&upd7810_device::BIT_0_wa, 2,10,10,L0\|L1}, {&upd7810_device::BIT_1_wa, 2,10,10,L0\|L1},
3650		{&upd7810_device::BIT_2_wa, 2,10,10,L0\|L1}, {&upd7810_device::BIT_3_wa, 2,10,10,L0\|L1},
3651		{&upd7810_device::BIT_4_wa, 2,10,10,L0\|L1}, {&upd7810_device::BIT_5_wa, 2,10,10,L0\|L1},
3652		{&upd7810_device::BIT_6_wa, 2,10,10,L0\|L1}, {&upd7810_device::BIT_7_wa, 2,10,10,L0\|L1},
3653
3654		/* 0x60 - 0x7F */
3655		{&upd7810_device::PRE_60, 1, 0, 0,L0\|L1}, {&upd7810_device::DAA, 1, 4, 4,L0\|L1},
3656		{&upd7810_device::RETI, 1,15,15,L0\|L1}, {&upd7810_device::CALB, 2,13,13,L0\|L1},
3657		{&upd7810_device::PRE_64, 1, 0, 0,L0\|L1}, {&upd7810_device::NEIW_wa_xx, 3,13,13,L0\|L1},
3658		{&upd7810_device::SUI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::NEI_A_xx, 2, 7, 7,L0\|L1},
3659		{&upd7810_device::MVI_V_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::MVI_A_xx, 2, 7, 7,L0 },
3660		{&upd7810_device::MVI_B_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::MVI_C_xx, 2, 7, 7,L0\|L1},
3661		{&upd7810_device::MVI_D_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::MVI_E_xx, 2, 7, 7,L0\|L1},
3662		{&upd7810_device::MVI_H_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::MVI_L_xx, 2, 7, 7, L1},
3663
3664		{&upd7810_device::PRE_70, 1, 0, 0,L0\|L1}, {&upd7810_device::MVIW_wa_xx, 3,13,13,L0\|L1},
3665		{&upd7810_device::SOFTI, 1,19,19,L0\|L1}, {&upd7810_device::JB, 1, 4, 4,L0\|L1},
3666		{&upd7810_device::PRE_74, 1, 0, 0,L0\|L1}, {&upd7810_device::EQIW_wa_xx, 3,13,13,L0\|L1},
3667		{&upd7810_device::SBI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::EQI_A_xx, 2, 7, 7,L0\|L1},
3668		{&upd7810_device::CALF, 2,16,16,L0\|L1}, {&upd7810_device::CALF, 2,16,16,L0\|L1},
3669		{&upd7810_device::CALF, 2,16,16,L0\|L1}, {&upd7810_device::CALF, 2,16,16,L0\|L1},
3670		{&upd7810_device::CALF, 2,16,16,L0\|L1}, {&upd7810_device::CALF, 2,16,16,L0\|L1},
3671		{&upd7810_device::CALF, 2,16,16,L0\|L1}, {&upd7810_device::CALF, 2,16,16,L0\|L1},
3672
3673		/* 0x80 - 0x9F */
3674		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3675		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3676		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3677		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3678		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3679		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3680		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3681		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3682
3683		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3684		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3685		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3686		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3687		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3688		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3689		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3690		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3691
3692		/* 0xA0 - 0xBF */
3693		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3694		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3695		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3696		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3697		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3698		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3699		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3700		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3701
3702		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3703		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3704		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3705		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3706		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3707		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3708		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3709		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
3710
3711		/* 0xC0 - 0xDF */
3712		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3713		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3714		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3715		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3716		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3717		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3718		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3719		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3720
3721		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3722		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3723		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3724		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3725		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3726		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3727		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3728		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3729
3730		/* 0xE0 - 0xFF */
3731		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3732		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3733		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3734		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3735		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3736		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3737		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3738		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3739
3740		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3741		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3742		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3743		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3744		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3745		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3746		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
3747		{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1}
3748		};
3749
3750		/***********************************************************************
3751		*
3752		* uPD78C05(A)
3753		*
3754		**********************************************************************/
3755
3756		const struct upd7810_device::opcode_s upd7810_device::s_op48_78c05[256] =
3757		{
3758		/* 0x00 - 0x1F */
3759		{&upd7810_device::SKIT_F0, 2, 8, 8,L0\|L1}, {&upd7810_device::SKIT_FT0, 2, 8, 8,L0\|L1},
3760		{&upd7810_device::SKIT_F1, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3761		{&upd7810_device::SKIT_FST, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3762		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3763		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3764		{&upd7810_device::SK_CY, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3765		{&upd7810_device::SK_Z, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3766		{&upd7810_device::PUSH_VA, 2,17,17,L0\|L1}, {&upd7810_device::POP_VA, 2,14,14,L0\|L1},
3767
3768		{&upd7810_device::SKNIT_F0, 2, 8, 8,L0\|L1}, {&upd7810_device::SKNIT_FT0, 2, 8, 8,L0\|L1},
3769		{&upd7810_device::SKNIT_F1, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3770		{&upd7810_device::SKNIT_FST, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3771		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3772		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3773		{&upd7810_device::SKN_CY, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3774		{&upd7810_device::SKN_Z, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3775		{&upd7810_device::PUSH_BC, 2,17,17,L0\|L1}, {&upd7810_device::POP_BC, 2,14,14,L0\|L1},
3776
3777		/* 0x20 - 0x3F */
3778		{&upd7810_device::EI, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3779		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3780		{&upd7810_device::DI, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3781		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3782		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3783		{&upd7810_device::CLC, 2, 8, 8,L0\|L1}, {&upd7810_device::STC, 2, 8, 8,L0\|L1},
3784		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::PEX, 2,11,11,L0\|L1},
3785		{&upd7810_device::PUSH_DE, 2,17,17,L0\|L1}, {&upd7810_device::POP_DE, 2,14,14,L0\|L1},
3786
3787		{&upd7810_device::RLL_A, 2, 8, 8,L0\|L1}, {&upd7810_device::RLR_A, 2, 8, 8,L0\|L1},
3788		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3789		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3790		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3791		{&upd7810_device::RLD, 2,17,17,L0\|L1}, {&upd7810_device::RRD, 2,17,17,L0\|L1},
3792		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3793		{&upd7810_device::PER, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3794		{&upd7810_device::PUSH_HL, 2,17,17,L0\|L1}, {&upd7810_device::POP_HL, 2,14,14,L0\|L1},
3795
3796		/* 0x40 - 0x5F */
3797		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3798		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3799		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3800		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3801		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3802		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3803		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3804		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3805
3806		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3807		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3808		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3809		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3810		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3811		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3812		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3813		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3814
3815		/* 0x60 - 0x7F */
3816		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3817		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3818		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3819		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3820		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3821		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3822		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3823		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3824
3825		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3826		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3827		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3828		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3829		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3830		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3831		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3832		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3833
3834		/* 0x80 - 0x9F */
3835		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3836		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3837		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3838		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3839		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3840		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3841		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3842		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3843
3844		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3845		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3846		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3847		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3848		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3849		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3850		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3851		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3852
3853		/* 0xA0 - 0xBF */
3854		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3855		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3856		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3857		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3858		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3859		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3860		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3861		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3862
3863		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3864		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3865		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3866		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3867		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3868		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3869		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3870		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3871
3872		/* 0xC0 - 0xDF */
3873		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3874		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3875		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3876		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3877		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3878		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3879		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3880		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3881
3882		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3883		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3884		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3885		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3886		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3887		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3888		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3889		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3890
3891		/* 0xE0 - 0xFF */
3892		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3893		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3894		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3895		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3896		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3897		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3898		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3899		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3900
3901		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3902		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3903		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3904		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3905		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3906		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3907		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3908		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
3909		};
3910
3911		const struct upd7810_device::opcode_s upd7810_device::s_op4C_78c05[256] =
3912		{
3913		/* 0x00 - 0x1F */
3914		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3915		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3916		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3917		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3918		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3919		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3920		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3921		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3922
3923		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3924		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3925		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3926		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3927		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3928		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3929		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3930		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3931
3932		/* 0x20 - 0x3F */
3933		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3934		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3935		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3936		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3937		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3938		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3939		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3940		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3941
3942		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3943		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3944		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3945		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3946		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3947		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3948		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3949		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3950
3951		/* 0x40 - 0x5F */
3952		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3953		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3954		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3955		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3956		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3957		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3958		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3959		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3960
3961		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3962		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3963		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3964		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3965		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3966		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3967		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3968		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3969
3970		/* 0x60 - 0x7F */
3971		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3972		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3973		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3974		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3975		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3976		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3977		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3978		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3979
3980		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3981		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3982		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3983		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3984		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3985		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3986		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3987		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3988
3989		/* 0x80 - 0x9F */
3990		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3991		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3992		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3993		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3994		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3995		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3996		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3997		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
3998
3999		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4000		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4001		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4002		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4003		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4004		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4005		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4006		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4007
4008		/* 0xA0 - 0xBF */
4009		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4010		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4011		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4012		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4013		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4014		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4015		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4016		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4017
4018		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4019		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4020		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4021		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4022		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4023		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4024		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4025		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4026
4027		/* 0xC0 - 0xDF */
4028		{&upd7810_device::MOV_A_PA, 2,10,10,L0\|L1}, {&upd7810_device::MOV_A_PB, 2,10,10,L0\|L1},
4029		{&upd7810_device::MOV_A_PC, 2,10,10,L0\|L1}, {&upd7810_device::MOV_A_MKL, 2,10,10,L0\|L1},
4030		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4031		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4032		{&upd7810_device::MOV_A_S, 2,10,10,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4033		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4034		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4035		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4036
4037		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4038		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4039		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4040		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4041		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4042		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4043		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4044		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4045
4046		/* 0xE0 - 0xFF */
4047		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4048		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4049		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4050		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4051		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4052		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4053		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4054		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4055
4056		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4057		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4058		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4059		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4060		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4061		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4062		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4063		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
4064		};
4065
4066		/* prefix 4D */
4067		const struct upd7810_device::opcode_s upd7810_device::s_op4D_78c05[256] =
4068		{
4069		/* 0x00 - 0x1F */
4070		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4071		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4072		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4073		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4074		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4075		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4076		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4077		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4078
4079		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4080		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4081		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4082		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4083		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4084		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4085		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4086		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4087
4088		/* 0x20 - 0x3F */
4089		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4090		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4091		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4092		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4093		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4094		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4095		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4096		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4097
4098		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4099		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4100		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4101		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4102		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4103		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4104		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4105		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4106
4107		/* 0x40 - 0x5F */
4108		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4109		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4110		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4111		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4112		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4113		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4114		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4115		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4116
4117		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4118		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4119		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4120		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4121		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4122		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4123		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4124		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4125
4126		/* 0x60 - 0x7F */
4127		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4128		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4129		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4130		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4131		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4132		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4133		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4134		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4135
4136		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4137		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4138		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4139		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4140		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4141		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4142		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4143		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4144
4145		/* 0x80 - 0x9F */
4146		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4147		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4148		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4149		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4150		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4151		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4152		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4153		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4154
4155		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4156		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4157		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4158		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4159		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4160		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4161		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4162		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4163
4164		/* 0xA0 - 0xBF */
4165		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4166		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4167		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4168		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4169		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4170		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4171		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4172		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4173
4174		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4175		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4176		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4177		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4178		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4179		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4180		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4181		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4182
4183		/* 0xC0 - 0xDF */
4184		{&upd7810_device::MOV_PA_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_PB_A, 2,10,10,L0\|L1},
4185		{&upd7810_device::MOV_PC_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_MKL_A, 2,10,10,L0\|L1},
4186		{&upd7810_device::MOV_MB_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_MC_A, 2,10,10,L0\|L1},
4187		{&upd7810_device::MOV_TM0_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_TM1_A, 2,10,10,L0\|L1},
4188		{&upd7810_device::MOV_S_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_TMM_A, 2,10,10,L0\|L1},
4189		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4190		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4191		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4192
4193		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4194		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4195		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4196		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4197		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4198		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4199		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4200		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4201
4202		/* 0xE0 - 0xFF */
4203		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4204		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4205		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4206		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4207		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4208		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4209		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4210		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4211
4212		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4213		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4214		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4215		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4216		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4217		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4218		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4219		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
4220		};
4221
4222		/* prefix 60 */
4223		const struct upd7810_device::opcode_s upd7810_device::s_op60_78c05[256] =
4224		{
4225		/* 0x00 - 0x1F */
4226		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4227		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4228		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4229		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4230		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_A, 2, 8, 8,L0\|L1},
4231		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4232		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4233		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4234
4235		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_A, 2, 8, 8,L0\|L1},
4236		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4237		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4238		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4239		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_A, 2, 8, 8,L0\|L1},
4240		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4241		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4242		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4243
4244		/* 0x20 - 0x3F */
4245		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_A, 2, 8, 8,L0\|L1},
4246		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4247		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4248		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4249		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_A, 2, 8, 8,L0\|L1},
4250		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4251		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4252		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4253
4254		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_A, 2, 8, 8,L0\|L1},
4255		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4256		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4257		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4258		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_A, 2, 8, 8,L0\|L1},
4259		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4260		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4261		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4262
4263		/* 0x40 - 0x5F */
4264		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_A, 2, 8, 8,L0\|L1},
4265		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4266		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4267		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4268		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4269		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4270		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4271		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4272
4273		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_A, 2, 8, 8,L0\|L1},
4274		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4275		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4276		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4277		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4278		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4279		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4280		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4281		/* 0x60 - 0x7F */
4282		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_A, 2, 8, 8,L0\|L1},
4283		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4284		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4285		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4286		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_A, 2, 8, 8,L0\|L1},
4287		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4288		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4289		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4290
4291		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_A, 2, 8, 8,L0\|L1},
4292		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4293		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4294		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4295		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_A, 2, 8, 8,L0\|L1},
4296		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4297		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4298		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4299
4300		/* 0x80 - 0x9F */
4301		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4302		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4303		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4304		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4305		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_A, 2, 8, 8,L0\|L1},
4306		{&upd7810_device::ANA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_C, 2, 8, 8,L0\|L1},
4307		{&upd7810_device::ANA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_E, 2, 8, 8,L0\|L1},
4308		{&upd7810_device::ANA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_L, 2, 8, 8,L0\|L1},
4309
4310		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_A, 2, 8, 8,L0\|L1},
4311		{&upd7810_device::XRA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_C, 2, 8, 8,L0\|L1},
4312		{&upd7810_device::XRA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_E, 2, 8, 8,L0\|L1},
4313		{&upd7810_device::XRA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_L, 2, 8, 8,L0\|L1},
4314		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_A, 2, 8, 8,L0\|L1},
4315		{&upd7810_device::ORA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_C, 2, 8, 8,L0\|L1},
4316		{&upd7810_device::ORA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_E, 2, 8, 8,L0\|L1},
4317		{&upd7810_device::ORA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_L, 2, 8, 8,L0\|L1},
4318
4319		/* 0xA0 - 0xBF */
4320		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_A, 2, 8, 8,L0\|L1},
4321		{&upd7810_device::ADDNC_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_C, 2, 8, 8,L0\|L1},
4322		{&upd7810_device::ADDNC_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_E, 2, 8, 8,L0\|L1},
4323		{&upd7810_device::ADDNC_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_L, 2, 8, 8,L0\|L1},
4324		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_A, 2, 8, 8,L0\|L1},
4325		{&upd7810_device::GTA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_C, 2, 8, 8,L0\|L1},
4326		{&upd7810_device::GTA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_E, 2, 8, 8,L0\|L1},
4327		{&upd7810_device::GTA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_L, 2, 8, 8,L0\|L1},
4328
4329		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_A, 2, 8, 8,L0\|L1},
4330		{&upd7810_device::SUBNB_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_C, 2, 8, 8,L0\|L1},
4331		{&upd7810_device::SUBNB_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_E, 2, 8, 8,L0\|L1},
4332		{&upd7810_device::SUBNB_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_L, 2, 8, 8,L0\|L1},
4333		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_A, 2, 8, 8,L0\|L1},
4334		{&upd7810_device::LTA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_C, 2, 8, 8,L0\|L1},
4335		{&upd7810_device::LTA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_E, 2, 8, 8,L0\|L1},
4336		{&upd7810_device::LTA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_L, 2, 8, 8,L0\|L1},
4337
4338		/* 0xC0 - 0xDF */
4339		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_A, 2, 8, 8,L0\|L1},
4340		{&upd7810_device::ADD_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_C, 2, 8, 8,L0\|L1},
4341		{&upd7810_device::ADD_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_E, 2, 8, 8,L0\|L1},
4342		{&upd7810_device::ADD_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_L, 2, 8, 8,L0\|L1},
4343		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ONA_A_A, 2, 8, 8,L0\|L1},
4344		{&upd7810_device::ONA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ONA_A_C, 2, 8, 8,L0\|L1},
4345		{&upd7810_device::ONA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ONA_A_E, 2, 8, 8,L0\|L1},
4346		{&upd7810_device::ONA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ONA_A_L, 2, 8, 8,L0\|L1},
4347
4348		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_A, 2, 8, 8,L0\|L1},
4349		{&upd7810_device::ADC_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_C, 2, 8, 8,L0\|L1},
4350		{&upd7810_device::ADC_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_E, 2, 8, 8,L0\|L1},
4351		{&upd7810_device::ADC_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_L, 2, 8, 8,L0\|L1},
4352		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFA_A_A, 2, 8, 8,L0\|L1},
4353		{&upd7810_device::OFFA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFA_A_C, 2, 8, 8,L0\|L1},
4354		{&upd7810_device::OFFA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFA_A_E, 2, 8, 8,L0\|L1},
4355		{&upd7810_device::OFFA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFA_A_L, 2, 8, 8,L0\|L1},
4356
4357		/* 0xE0 - 0xFF */
4358		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_A, 2, 8, 8,L0\|L1},
4359		{&upd7810_device::SUB_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_C, 2, 8, 8,L0\|L1},
4360		{&upd7810_device::SUB_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_E, 2, 8, 8,L0\|L1},
4361		{&upd7810_device::SUB_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_L, 2, 8, 8,L0\|L1},
4362		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_A, 2, 8, 8,L0\|L1},
4363		{&upd7810_device::NEA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_C, 2, 8, 8,L0\|L1},
4364		{&upd7810_device::NEA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_E, 2, 8, 8,L0\|L1},
4365		{&upd7810_device::NEA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_L, 2, 8, 8,L0\|L1},
4366
4367		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_A, 2, 8, 8,L0\|L1},
4368		{&upd7810_device::SBB_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_C, 2, 8, 8,L0\|L1},
4369		{&upd7810_device::SBB_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_E, 2, 8, 8,L0\|L1},
4370		{&upd7810_device::SBB_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_L, 2, 8, 8,L0\|L1},
4371		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_A, 2, 8, 8,L0\|L1},
4372		{&upd7810_device::EQA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_C, 2, 8, 8,L0\|L1},
4373		{&upd7810_device::EQA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_E, 2, 8, 8,L0\|L1},
4374		{&upd7810_device::EQA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_L, 2, 8, 8,L0\|L1}
4375		};
4376
4377		/* prefix 64 */
4378		const struct upd7810_device::opcode_s upd7810_device::s_op64_78c05[256] =
4379		{
4380		/* 0x00 - 0x1F */
4381		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4382		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4383		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4384		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4385		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ANI_A_xx, 3,11,11,L0\|L1},
4386		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4387		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4388		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4389
4390		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::XRI_A_xx, 3,11,11,L0\|L1},
4391		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4392		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4393		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4394		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ORI_A_xx, 3,11,11,L0\|L1},
4395		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4396		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4397		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4398
4399		/* 0x20 - 0x3F */
4400		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADINC_A_xx, 3,11,11,L0\|L1},
4401		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4402		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4403		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4404		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::GTI_A_xx, 3,11,11,L0\|L1},
4405		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4406		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4407		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4408
4409		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUINB_A_xx, 3,11,11,L0\|L1},
4410		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4411		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4412		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4413		{&upd7810_device::illegal2, 3, 8, 8,L0\|L1}, {&upd7810_device::LTI_A_xx, 3,11,11,L0\|L1},
4414		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4415		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4416		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4417
4418		/* 0x40 - 0x5F */
4419		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADI_A_xx, 3,11,11,L0\|L1},
4420		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4421		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4422		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4423		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ONI_A_xx, 3,11,11,L0\|L1},
4424		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4425		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4426		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4427
4428		{&upd7810_device::illegal2, 3, 8, 8,L0\|L1}, {&upd7810_device::ACI_A_xx, 3,11,11,L0\|L1},
4429		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4430		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4431		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4432		{&upd7810_device::illegal2, 3, 8, 8,L0\|L1}, {&upd7810_device::OFFI_A_xx, 3,11,11,L0\|L1},
4433		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4434		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4435		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4436
4437		/* 0x60 - 0x7F */
4438		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUI_A_xx, 3,11,11,L0\|L1},
4439		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4440		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4441		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4442		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::NEI_A_xx, 3,11,11,L0\|L1},
4443		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4444		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4445		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4446
4447		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SBI_A_xx, 3,11,11,L0\|L1},
4448		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4449		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4450		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4451		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::EQI_A_xx, 3,11,11,L0\|L1},
4452		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4453		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4454		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4455
4456		/* 0x80 - 0x9F */
4457		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4458		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4459		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4460		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4461		{&upd7810_device::ANI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ANI_PB_xx, 3,17,17,L0\|L1},
4462		{&upd7810_device::ANI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ANI_MKL_xx, 3,17,17,L0\|L1},
4463		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4464		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4465
4466		{&upd7810_device::XRI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::XRI_PB_xx, 3,17,17,L0\|L1},
4467		{&upd7810_device::XRI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::XRI_MKL_xx, 3,17,17,L0\|L1},
4468		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4469		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4470		{&upd7810_device::ORI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ORI_PB_xx, 3,17,17,L0\|L1},
4471		{&upd7810_device::ORI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ORI_MKL_xx, 3,17,17,L0\|L1},
4472		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4473		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4474
4475		/* 0xA0 - 0xBF */
4476		{&upd7810_device::ADINC_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ADINC_PB_xx, 3,17,17,L0\|L1},
4477		{&upd7810_device::ADINC_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ADINC_MKL_xx, 3,17,17,L0\|L1},
4478		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4479		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4480		{&upd7810_device::GTI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::GTI_PB_xx, 3,14,14,L0\|L1},
4481		{&upd7810_device::GTI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::GTI_MKL_xx, 3,14,14,L0\|L1},
4482		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4483		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4484
4485		{&upd7810_device::SUINB_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::SUINB_PB_xx, 3,17,17,L0\|L1},
4486		{&upd7810_device::SUINB_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::SUINB_MKL_xx, 3,17,17,L0\|L1},
4487		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4488		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4489		{&upd7810_device::LTI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::LTI_PB_xx, 3,14,14,L0\|L1},
4490		{&upd7810_device::LTI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::LTI_MKL_xx, 3,14,14,L0\|L1},
4491		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4492		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4493
4494		/* 0xC0 - 0xDF */
4495		{&upd7810_device::ADI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ADI_PB_xx, 3,17,17,L0\|L1},
4496		{&upd7810_device::ADI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ADI_MKL_xx, 3,17,17,L0\|L1},
4497		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4498		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4499		{&upd7810_device::ONI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::ONI_PB_xx, 3,14,14,L0\|L1},
4500		{&upd7810_device::ONI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::ONI_MKL_xx, 3,14,14,L0\|L1},
4501		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4502		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4503
4504		{&upd7810_device::ACI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ACI_PB_xx, 3,17,17,L0\|L1},
4505		{&upd7810_device::ACI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ACI_MKL_xx, 3,17,17,L0\|L1},
4506		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4507		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4508		{&upd7810_device::OFFI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::OFFI_PB_xx, 3,14,14,L0\|L1},
4509		{&upd7810_device::OFFI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::OFFI_MKL_xx, 3,14,14,L0\|L1},
4510		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4511		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4512
4513		/* 0xE0 - 0xFF */
4514		{&upd7810_device::SUI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::SUI_PB_xx, 3,17,17,L0\|L1},
4515		{&upd7810_device::SUI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::SUI_MKL_xx, 3,17,17,L0\|L1},
4516		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4517		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4518		{&upd7810_device::NEI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::NEI_PB_xx, 3,14,14,L0\|L1},
4519		{&upd7810_device::NEI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::NEI_MKL_xx, 3,14,14,L0\|L1},
4520		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4521		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4522
4523		{&upd7810_device::SBI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::SBI_PB_xx, 3,17,17,L0\|L1},
4524		{&upd7810_device::SBI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::SBI_MKL_xx, 3,17,17,L0\|L1},
4525		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4526		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4527		{&upd7810_device::EQI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::EQI_PB_xx, 3,14,14,L0\|L1},
4528		{&upd7810_device::EQI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::EQI_MKL_xx, 3,14,14,L0\|L1},
4529		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4530		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
4531		};
4532
4533		/* prefix 70 */
4534		const struct upd7810_device::opcode_s upd7810_device::s_op70_78c05[256] =
4535		{
4536		/* 0x00 - 0x1F */
4537		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4538		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4539		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4540		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4541		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4542		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4543		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4544		{&upd7810_device::SSPD_w, 4,20,20,L0\|L1}, {&upd7810_device::LSPD_w, 4,20,20,L0\|L1},
4545
4546		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4547		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4548		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4549		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4550		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4551		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4552		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4553		{&upd7810_device::SBCD_w, 4,20,20,L0\|L1}, {&upd7810_device::LBCD_w, 4,20,20,L0\|L1},
4554
4555		/* 0x20 - 0x3F */
4556		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4557		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4558		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4559		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4560		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4561		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4562		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4563		{&upd7810_device::SDED_w, 4,20,20,L0\|L1}, {&upd7810_device::LDED_w, 4,20,20,L0\|L1},
4564
4565		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4566		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4567		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4568		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4569		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4570		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4571		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4572		{&upd7810_device::SHLD_w, 4,20,20,L0\|L1}, {&upd7810_device::LHLD_w, 4,20,20,L0\|L1},
4573
4574		/* 0x40 - 0x5F */
4575		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4576		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4577		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4578		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4579		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4580		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4581		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4582		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4583
4584		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4585		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4586		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4587		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4588		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4589		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4590		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4591		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4592
4593		/* 0x60 - 0x7F */
4594		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4595		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4596		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4597		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4598		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::MOV_A_w, 4,17,17,L0\|L1},
4599		{&upd7810_device::MOV_B_w, 4,17,17,L0\|L1}, {&upd7810_device::MOV_C_w, 4,17,17,L0\|L1},
4600		{&upd7810_device::MOV_D_w, 4,17,17,L0\|L1}, {&upd7810_device::MOV_E_w, 4,17,17,L0\|L1},
4601		{&upd7810_device::MOV_H_w, 4,17,17,L0\|L1}, {&upd7810_device::MOV_L_w, 4,17,17,L0\|L1},
4602
4603		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4604		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4605		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4606		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4607		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::MOV_w_A, 4,17,17,L0\|L1},
4608		{&upd7810_device::MOV_w_B, 4,17,17,L0\|L1}, {&upd7810_device::MOV_w_C, 4,17,17,L0\|L1},
4609		{&upd7810_device::MOV_w_D, 4,17,17,L0\|L1}, {&upd7810_device::MOV_w_E, 4,17,17,L0\|L1},
4610		{&upd7810_device::MOV_w_H, 4,17,17,L0\|L1}, {&upd7810_device::MOV_w_L, 4,17,17,L0\|L1},
4611
4612		/* 0x80 - 0x9F */
4613		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4614		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4615		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4616		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4617		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ANAX_B, 2,11,11,L0\|L1},
4618		{&upd7810_device::ANAX_D, 2,11,11,L0\|L1}, {&upd7810_device::ANAX_H, 2,11,11,L0\|L1},
4619		{&upd7810_device::ANAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ANAX_Hp, 2,11,11,L0\|L1},
4620		{&upd7810_device::ANAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ANAX_Hm, 2,11,11,L0\|L1},
4621
4622		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::XRAX_B, 2,11,11,L0\|L1},
4623		{&upd7810_device::XRAX_D, 2,11,11,L0\|L1}, {&upd7810_device::XRAX_H, 2,11,11,L0\|L1},
4624		{&upd7810_device::XRAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::XRAX_Hp, 2,11,11,L0\|L1},
4625		{&upd7810_device::XRAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::XRAX_Hm, 2,11,11,L0\|L1},
4626		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ORAX_B, 2,11,11,L0\|L1},
4627		{&upd7810_device::ORAX_D, 2,11,11,L0\|L1}, {&upd7810_device::ORAX_H, 2,11,11,L0\|L1},
4628		{&upd7810_device::ORAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ORAX_Hp, 2,11,11,L0\|L1},
4629		{&upd7810_device::ORAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ORAX_Hm, 2,11,11,L0\|L1},
4630
4631		/* 0xA0 - 0xBF */
4632		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNCX_B, 2,11,11,L0\|L1},
4633		{&upd7810_device::ADDNCX_D, 2,11,11,L0\|L1}, {&upd7810_device::ADDNCX_H, 2,11,11,L0\|L1},
4634		{&upd7810_device::ADDNCX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ADDNCX_Hp, 2,11,11,L0\|L1},
4635		{&upd7810_device::ADDNCX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ADDNCX_Hm, 2,11,11,L0\|L1},
4636		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::GTAX_B, 2,11,11,L0\|L1},
4637		{&upd7810_device::GTAX_D, 2,11,11,L0\|L1}, {&upd7810_device::GTAX_H, 2,11,11,L0\|L1},
4638		{&upd7810_device::GTAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::GTAX_Hp, 2,11,11,L0\|L1},
4639		{&upd7810_device::GTAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::GTAX_Hm, 2,11,11,L0\|L1},
4640
4641		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNBX_B, 2,11,11,L0\|L1},
4642		{&upd7810_device::SUBNBX_D, 2,11,11,L0\|L1}, {&upd7810_device::SUBNBX_H, 2,11,11,L0\|L1},
4643		{&upd7810_device::SUBNBX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::SUBNBX_Hp, 2,11,11,L0\|L1},
4644		{&upd7810_device::SUBNBX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::SUBNBX_Hm, 2,11,11,L0\|L1},
4645		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::LTAX_B, 2,11,11,L0\|L1},
4646		{&upd7810_device::LTAX_D, 2,11,11,L0\|L1}, {&upd7810_device::LTAX_H, 2,11,11,L0\|L1},
4647		{&upd7810_device::LTAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::LTAX_Hp, 2,11,11,L0\|L1},
4648		{&upd7810_device::LTAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::LTAX_Hm, 2,11,11,L0\|L1},
4649
4650		/* 0xC0 - 0xDF */
4651		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDX_B, 2,11,11,L0\|L1},
4652		{&upd7810_device::ADDX_D, 2,11,11,L0\|L1}, {&upd7810_device::ADDX_H, 2,11,11,L0\|L1},
4653		{&upd7810_device::ADDX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ADDX_Hp, 2,11,11,L0\|L1},
4654		{&upd7810_device::ADDX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ADDX_Hm, 2,11,11,L0\|L1},
4655		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ONAX_B, 2,11,11,L0\|L1},
4656		{&upd7810_device::ONAX_D, 2,11,11,L0\|L1}, {&upd7810_device::ONAX_H, 2,11,11,L0\|L1},
4657		{&upd7810_device::ONAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ONAX_Hp, 2,11,11,L0\|L1},
4658		{&upd7810_device::ONAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ONAX_Hm, 2,11,11,L0\|L1},
4659
4660		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADCX_B, 2,11,11,L0\|L1},
4661		{&upd7810_device::ADCX_D, 2,11,11,L0\|L1}, {&upd7810_device::ADCX_H, 2,11,11,L0\|L1},
4662		{&upd7810_device::ADCX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ADCX_Hp, 2,11,11,L0\|L1},
4663		{&upd7810_device::ADCX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ADCX_Hm, 2,11,11,L0\|L1},
4664		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFAX_B, 2,11,11,L0\|L1},
4665		{&upd7810_device::OFFAX_D, 2,11,11,L0\|L1}, {&upd7810_device::OFFAX_H, 2,11,11,L0\|L1},
4666		{&upd7810_device::OFFAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::OFFAX_Hp, 2,11,11,L0\|L1},
4667		{&upd7810_device::OFFAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::OFFAX_Hm, 2,11,11,L0\|L1},
4668
4669		/* 0xE0 - 0xFF */
4670		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBX_B, 2,11,11,L0\|L1},
4671		{&upd7810_device::SUBX_D, 2,11,11,L0\|L1}, {&upd7810_device::SUBX_H, 2,11,11,L0\|L1},
4672		{&upd7810_device::SUBX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::SUBX_Hp, 2,11,11,L0\|L1},
4673		{&upd7810_device::SUBX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::SUBX_Hm, 2,11,11,L0\|L1},
4674		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::NEAX_B, 2,11,11,L0\|L1},
4675		{&upd7810_device::NEAX_D, 2,11,11,L0\|L1}, {&upd7810_device::NEAX_H, 2,11,11,L0\|L1},
4676		{&upd7810_device::NEAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::NEAX_Hp, 2,11,11,L0\|L1},
4677		{&upd7810_device::NEAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::NEAX_Hm, 2,11,11,L0\|L1},
4678
4679		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SBBX_B, 2,11,11,L0\|L1},
4680		{&upd7810_device::SBBX_D, 2,11,11,L0\|L1}, {&upd7810_device::SBBX_H, 2,11,11,L0\|L1},
4681		{&upd7810_device::SBBX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::SBBX_Hp, 2,11,11,L0\|L1},
4682		{&upd7810_device::SBBX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::SBBX_Hm, 2,11,11,L0\|L1},
4683		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::EQAX_B, 2,11,11,L0\|L1},
4684		{&upd7810_device::EQAX_D, 2,11,11,L0\|L1}, {&upd7810_device::EQAX_H, 2,11,11,L0\|L1},
4685		{&upd7810_device::EQAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::EQAX_Hp, 2,11,11,L0\|L1},
4686		{&upd7810_device::EQAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::EQAX_Hm, 2,11,11,L0\|L1}
4687		};
4688
4689		/* prefix 74 */
4690		const struct upd7810_device::opcode_s upd7810_device::s_op74_78c05[256] =
4691		{
4692		/* 0x00 - 0x1F */
4693		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4694		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4695		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4696		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4697		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4698		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4699		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4700		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4701
4702		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4703		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4704		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4705		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4706		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4707		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4708		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4709		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4710
4711		/* 0x20 - 0x3F */
4712		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4713		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4714		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4715		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4716		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4717		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4718		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4719		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4720
4721		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4722		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4723		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4724		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4725		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4726		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4727		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4728		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4729
4730		/* 0x40 - 0x5F */
4731		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4732		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4733		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4734		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4735		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4736		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4737		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4738		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4739
4740		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4741		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4742		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4743		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4744		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4745		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4746		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4747		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4748
4749		/* 0x60 - 0x7F */
4750		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4751		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4752		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4753		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4754		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4755		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4756		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4757		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4758
4759		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4760		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4761		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4762		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4763		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4764		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4765		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4766		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4767
4768		/* 0x80 - 0x9F */
4769		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4770		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4771		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4772		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4773		{&upd7810_device::ANAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4774		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4775		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4776		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4777
4778		{&upd7810_device::XRAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4779		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4780		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4781		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4782		{&upd7810_device::ORAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4783		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4784		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4785		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4786
4787		/* 0xA0 - 0xBF */
4788		{&upd7810_device::ADDNCW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4789		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4790		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4791		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4792		{&upd7810_device::GTAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4793		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4794		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4795		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4796
4797		{&upd7810_device::SUBNBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4798		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4799		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4800		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4801		{&upd7810_device::LTAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4802		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4803		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4804		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4805
4806		/* 0xC0 - 0xDF */
4807		{&upd7810_device::ADDW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4808		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4809		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4810		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4811		{&upd7810_device::ONAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4812		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4813		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4814		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4815
4816		{&upd7810_device::ADCW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4817		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4818		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4819		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4820		{&upd7810_device::OFFAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4821		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4822		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4823		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4824
4825		/* 0xE0 - 0xFF */
4826		{&upd7810_device::SUBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4827		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4828		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4829		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4830		{&upd7810_device::NEAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4831		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4832		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4833		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4834
4835		{&upd7810_device::SBBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4836		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4837		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4838		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4839		{&upd7810_device::EQAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4840		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4841		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
4842		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
4843		};
4844
4845		const struct upd7810_device::opcode_s upd7810_device::s_opXX_78c05[256] =
4846		{
4847		/* 0x00 - 0x1F */
4848		{&upd7810_device::NOP, 1, 4, 4,L0\|L1}, {&upd7810_device::HALT, 1, 6, 6,L0\|L1},
4849		{&upd7810_device::INX_SP, 1, 7, 7,L0\|L1}, {&upd7810_device::DCX_SP, 1, 7, 7,L0\|L1},
4850		{&upd7810_device::LXI_S_w, 3,10,10,L0\|L1}, {&upd7810_device::ANIW_wa_xx, 3,16,16,L0\|L1},
4851		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::ANI_A_xx, 2, 7, 7,L0\|L1},
4852		{&upd7810_device::RET, 1,10,10,L0\|L1}, {&upd7810_device::SIO, 1, 4, 4,L0\|L1},
4853		{&upd7810_device::MOV_A_B, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_A_C, 1, 4, 4,L0\|L1},
4854		{&upd7810_device::MOV_A_D, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_A_E, 1, 4, 4,L0\|L1},
4855		{&upd7810_device::MOV_A_H, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_A_L, 1, 4, 4,L0\|L1},
4856
4857		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
4858		{&upd7810_device::INX_BC, 1, 7, 7,L0\|L1}, {&upd7810_device::DCX_BC, 1, 7, 7,L0\|L1},
4859		{&upd7810_device::LXI_B_w, 3,10,10,L0\|L1}, {&upd7810_device::ORIW_wa_xx, 3,16,16,L0\|L1},
4860		{&upd7810_device::XRI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::ORI_A_xx, 2, 7, 7,L0\|L1},
4861		{&upd7810_device::RETS, 1,10,10,L0\|L1}, {&upd7810_device::STM, 1, 4, 4,L0\|L1},
4862		{&upd7810_device::MOV_B_A, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_C_A, 1, 4, 4,L0\|L1},
4863		{&upd7810_device::MOV_D_A, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_E_A, 1, 4, 4,L0\|L1},
4864		{&upd7810_device::MOV_H_A, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_L_A, 1, 4, 4,L0\|L1},
4865
4866		/* 0x20 - 0x3F */
4867		{&upd7810_device::INRW_wa_7801, 2,13,13,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
4868		{&upd7810_device::INX_DE, 1, 7, 7,L0\|L1}, {&upd7810_device::DCX_DE, 1, 7, 7,L0\|L1},
4869		{&upd7810_device::LXI_D_w, 3,10,10,L0\|L1}, {&upd7810_device::GTIW_wa_xx, 3,13,13,L0\|L1},
4870		{&upd7810_device::ADINC_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::GTI_A_xx, 2, 7, 7,L0\|L1},
4871		{&upd7810_device::LDAW_wa, 2,10,10,L0\|L1}, {&upd7810_device::LDAX_B, 1, 7, 7,L0\|L1},
4872		{&upd7810_device::LDAX_D, 1, 7, 7,L0\|L1}, {&upd7810_device::LDAX_H, 1, 7, 7,L0\|L1},
4873		{&upd7810_device::LDAX_Dp, 1, 7, 7,L0\|L1}, {&upd7810_device::LDAX_Hp, 1, 7, 7,L0\|L1},
4874		{&upd7810_device::LDAX_Dm, 1, 7, 7,L0\|L1}, {&upd7810_device::LDAX_Hm, 1, 7, 7,L0\|L1},
4875
4876		{&upd7810_device::DCRW_wa_7801, 2,13,13,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
4877		{&upd7810_device::INX_HL, 1, 7, 7,L0\|L1}, {&upd7810_device::DCX_HL, 1, 7, 7,L0\|L1},
4878		{&upd7810_device::LXI_H_w, 3,10,10, L1}, {&upd7810_device::LTIW_wa_xx, 3,13,13,L0\|L1},
4879		{&upd7810_device::SUINB_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::LTI_A_xx, 2, 7, 7,L0\|L1},
4880		{&upd7810_device::STAW_wa, 2,10,10,L0\|L1}, {&upd7810_device::STAX_B, 1, 7, 7,L0\|L1},
4881		{&upd7810_device::STAX_D, 1, 7, 7,L0\|L1}, {&upd7810_device::STAX_H, 1, 7, 7,L0\|L1},
4882		{&upd7810_device::STAX_Dp, 1, 7, 7,L0\|L1}, {&upd7810_device::STAX_Hp, 1, 7, 7,L0\|L1},
4883		{&upd7810_device::STAX_Dm, 1, 7, 7,L0\|L1}, {&upd7810_device::STAX_Hm, 1, 7, 7,L0\|L1},
4884
4885		/* 0x40 - 0x5F */
4886		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::INR_A_7801, 1, 4, 4,L0\|L1},
4887		{&upd7810_device::INR_B_7801, 1, 4, 4,L0\|L1}, {&upd7810_device::INR_C_7801, 1, 4, 4,L0\|L1},
4888		{&upd7810_device::CALL_w, 3,16,16,L0\|L1}, {&upd7810_device::ONIW_wa_xx, 3,13,13,L0\|L1},
4889		{&upd7810_device::ADI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::ONI_A_xx, 2, 7, 7,L0\|L1},
4890		{&upd7810_device::PRE_48, 1, 0, 0,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
4891		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
4892		{&upd7810_device::PRE_4C, 1, 0, 0,L0\|L1}, {&upd7810_device::PRE_4D, 1, 0, 0,L0\|L1},
4893		{&upd7810_device::JRE, 2,13,13,L0\|L1}, {&upd7810_device::JRE, 2,13,13,L0\|L1},
4894
4895		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::DCR_A_7801, 1, 4, 4,L0\|L1},
4896		{&upd7810_device::DCR_B_7801, 1, 4, 4,L0\|L1}, {&upd7810_device::DCR_C_7801, 1, 4, 4,L0\|L1},
4897		{&upd7810_device::JMP_w, 3,10,10,L0\|L1}, {&upd7810_device::OFFIW_wa_xx, 3,13,13,L0\|L1},
4898		{&upd7810_device::ACI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::OFFI_A_xx, 2, 7, 7,L0\|L1},
4899		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
4900		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
4901		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
4902		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
4903
4904		/* 0x60 - 0x7F */
4905		{&upd7810_device::PRE_60, 1, 0, 0,L0\|L1}, {&upd7810_device::DAA, 1, 4, 4,L0\|L1},
4906		{&upd7810_device::RETI, 1,13,13,L0\|L1}, {&upd7810_device::CALB, 2,13,13,L0\|L1},
4907		{&upd7810_device::PRE_64, 1, 0, 0,L0\|L1}, {&upd7810_device::NEIW_wa_xx, 3,13,13,L0\|L1},
4908		{&upd7810_device::SUI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::NEI_A_xx, 2, 7, 7,L0\|L1},
4909		{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::MVI_A_xx, 2, 7, 7,L0 },
4910		{&upd7810_device::MVI_B_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::MVI_C_xx, 2, 7, 7,L0\|L1},
4911		{&upd7810_device::MVI_D_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::MVI_E_xx, 2, 7, 7,L0\|L1},
4912		{&upd7810_device::MVI_H_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::MVI_L_xx, 2, 7, 7, L1},
4913
4914		{&upd7810_device::PRE_70, 1, 0, 0,L0\|L1}, {&upd7810_device::MVIW_wa_xx, 3,13,13,L0\|L1},
4915		{&upd7810_device::SOFTI, 1,19,19,L0\|L1}, {&upd7810_device::JB, 1, 4, 4,L0\|L1},
4916		{&upd7810_device::PRE_74, 1, 0, 0,L0\|L1}, {&upd7810_device::EQIW_wa_xx, 3,13,13,L0\|L1},
4917		{&upd7810_device::SBI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::EQI_A_xx, 2, 7, 7,L0\|L1},
4918		{&upd7810_device::CALF, 2,13,13,L0\|L1}, {&upd7810_device::CALF, 2,13,13,L0\|L1},
4919		{&upd7810_device::CALF, 2,13,13,L0\|L1}, {&upd7810_device::CALF, 2,13,13,L0\|L1},
4920		{&upd7810_device::CALF, 2,13,13,L0\|L1}, {&upd7810_device::CALF, 2,13,13,L0\|L1},
4921		{&upd7810_device::CALF, 2,13,13,L0\|L1}, {&upd7810_device::CALF, 2,13,13,L0\|L1},
4922
4923		/* 0x80 - 0x9F */
4924		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4925		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4926		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4927		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4928		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4929		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4930		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4931		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4932
4933		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4934		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4935		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4936		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4937		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4938		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4939		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4940		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4941
4942		/* 0xA0 - 0xBF */
4943		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4944		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4945		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4946		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4947		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4948		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4949		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4950		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4951
4952		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4953		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4954		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4955		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4956		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4957		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4958		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4959		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
4960
4961		/* 0xC0 - 0xDF */
4962		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4963		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4964		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4965		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4966		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4967		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4968		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4969		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4970
4971		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4972		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4973		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4974		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4975		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4976		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4977		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4978		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4979
4980		/* 0xE0 - 0xFF */
4981		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4982		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4983		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4984		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4985		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4986		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4987		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4988		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4989
4990		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4991		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4992		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4993		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4994		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4995		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4996		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
4997		{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1}
4998		};
4999
5000		/***********************************************************************
5001		*
5002		* uPD78C06(A) - Same as uPD78C05 but with different instruction timing
5003		*
5004		**********************************************************************/
5005
5006		const struct upd7810_device::opcode_s upd7810_device::s_op48_78c06[256] =
5007		{
5008		/* 0x00 - 0x1F */
5009		{&upd7810_device::SKIT_F0, 2,12,12,L0\|L1}, {&upd7810_device::SKIT_FT0, 2,12,12,L0\|L1},
5010		{&upd7810_device::SKIT_F1, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5011		{&upd7810_device::SKIT_FST, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5012		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5013		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5014		{&upd7810_device::SK_CY, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5015		{&upd7810_device::SK_Z, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5016		{&upd7810_device::PUSH_VA, 2,21,21,L0\|L1}, {&upd7810_device::POP_VA, 2,18,18,L0\|L1},
5017
5018		{&upd7810_device::SKNIT_F0, 2,12,12,L0\|L1}, {&upd7810_device::SKNIT_FT0, 2,12,12,L0\|L1},
5019		{&upd7810_device::SKNIT_F1, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5020		{&upd7810_device::SKNIT_FST, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5021		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5022		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5023		{&upd7810_device::SKN_CY, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5024		{&upd7810_device::SKN_Z, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5025		{&upd7810_device::PUSH_BC, 2,21,21,L0\|L1}, {&upd7810_device::POP_BC, 2,18,18,L0\|L1},
5026
5027		/* 0x20 - 0x3F */
5028		{&upd7810_device::EI, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5029		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5030		{&upd7810_device::DI, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5031		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5032		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5033		{&upd7810_device::CLC, 2,12,12,L0\|L1}, {&upd7810_device::STC, 2,12,12,L0\|L1},
5034		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::PEX, 2,15,15,L0\|L1},
5035		{&upd7810_device::PUSH_DE, 2,21,21,L0\|L1}, {&upd7810_device::POP_DE, 2,18,18,L0\|L1},
5036
5037		{&upd7810_device::RLL_A, 2,12,12,L0\|L1}, {&upd7810_device::RLR_A, 2,12,12,L0\|L1},
5038		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5039		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5040		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5041		{&upd7810_device::RLD, 2,21,21,L0\|L1}, {&upd7810_device::RRD, 2,21,21,L0\|L1},
5042		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5043		{&upd7810_device::PER, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5044		{&upd7810_device::PUSH_HL, 2,21,21,L0\|L1}, {&upd7810_device::POP_HL, 2,18,18,L0\|L1},
5045
5046		/* 0x40 - 0x5F */
5047		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5048		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5049		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5050		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5051		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5052		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5053		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5054		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5055
5056		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5057		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5058		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5059		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5060		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5061		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5062		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5063		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5064
5065		/* 0x60 - 0x7F */
5066		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5067		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5068		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5069		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5070		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5071		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5072		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5073		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5074
5075		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5076		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5077		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5078		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5079		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5080		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5081		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5082		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5083
5084		/* 0x80 - 0x9F */
5085		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5086		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5087		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5088		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5089		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5090		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5091		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5092		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5093
5094		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5095		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5096		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5097		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5098		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5099		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5100		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5101		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5102
5103		/* 0xA0 - 0xBF */
5104		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5105		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5106		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5107		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5108		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5109		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5110		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5111		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5112
5113		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5114		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5115		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5116		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5117		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5118		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5119		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5120		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5121
5122		/* 0xC0 - 0xDF */
5123		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5124		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5125		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5126		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5127		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5128		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5129		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5130		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5131
5132		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5133		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5134		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5135		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5136		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5137		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5138		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5139		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5140
5141		/* 0xE0 - 0xFF */
5142		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5143		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5144		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5145		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5146		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5147		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5148		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5149		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5150
5151		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5152		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5153		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5154		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5155		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5156		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5157		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5158		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1}
5159		};
5160
5161		const struct upd7810_device::opcode_s upd7810_device::s_op4C_78c06[256] =
5162		{
5163		/* 0x00 - 0x1F */
5164		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5165		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5166		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5167		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5168		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5169		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5170		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5171		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5172
5173		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5174		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5175		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5176		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5177		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5178		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5179		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5180		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5181
5182		/* 0x20 - 0x3F */
5183		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5184		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5185		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5186		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5187		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5188		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5189		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5190		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5191
5192		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5193		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5194		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5195		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5196		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5197		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5198		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5199		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5200
5201		/* 0x40 - 0x5F */
5202		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5203		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5204		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5205		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5206		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5207		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5208		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5209		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5210
5211		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5212		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5213		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5214		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5215		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5216		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5217		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5218		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5219
5220		/* 0x60 - 0x7F */
5221		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5222		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5223		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5224		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5225		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5226		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5227		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5228		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5229
5230		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5231		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5232		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5233		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5234		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5235		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5236		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5237		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5238
5239		/* 0x80 - 0x9F */
5240		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5241		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5242		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5243		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5244		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5245		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5246		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5247		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5248
5249		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5250		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5251		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5252		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5253		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5254		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5255		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5256		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5257
5258		/* 0xA0 - 0xBF */
5259		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5260		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5261		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5262		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5263		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5264		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5265		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5266		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5267
5268		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5269		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5270		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5271		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5272		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5273		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5274		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5275		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5276
5277		/* 0xC0 - 0xDF */
5278		{&upd7810_device::MOV_A_PA, 2,14,14,L0\|L1}, {&upd7810_device::MOV_A_PB, 2,14,14,L0\|L1},
5279		{&upd7810_device::MOV_A_PC, 2,14,14,L0\|L1}, {&upd7810_device::MOV_A_MKL, 2,14,14,L0\|L1},
5280		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5281		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5282		{&upd7810_device::MOV_A_S, 2,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5283		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5284		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5285		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5286
5287		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5288		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5289		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5290		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5291		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5292		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5293		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5294		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5295
5296		/* 0xE0 - 0xFF */
5297		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5298		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5299		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5300		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5301		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5302		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5303		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5304		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5305
5306		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5307		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5308		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5309		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5310		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5311		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5312		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5313		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1}
5314		};
5315
5316		/* prefix 4D */
5317		const struct upd7810_device::opcode_s upd7810_device::s_op4D_78c06[256] =
5318		{
5319		/* 0x00 - 0x1F */
5320		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5321		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5322		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5323		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5324		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5325		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5326		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5327		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5328
5329		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5330		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5331		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5332		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5333		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5334		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5335		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5336		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5337
5338		/* 0x20 - 0x3F */
5339		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5340		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5341		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5342		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5343		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5344		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5345		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5346		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5347
5348		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5349		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5350		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5351		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5352		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5353		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5354		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5355		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5356
5357		/* 0x40 - 0x5F */
5358		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5359		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5360		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5361		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5362		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5363		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5364		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5365		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5366
5367		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5368		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5369		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5370		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5371		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5372		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5373		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5374		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5375
5376		/* 0x60 - 0x7F */
5377		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5378		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5379		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5380		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5381		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5382		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5383		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5384		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5385
5386		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5387		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5388		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5389		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5390		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5391		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5392		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5393		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5394
5395		/* 0x80 - 0x9F */
5396		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5397		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5398		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5399		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5400		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5401		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5402		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5403		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5404
5405		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5406		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5407		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5408		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5409		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5410		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5411		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5412		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5413
5414		/* 0xA0 - 0xBF */
5415		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5416		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5417		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5418		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5419		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5420		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5421		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5422		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5423
5424		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5425		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5426		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5427		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5428		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5429		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5430		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5431		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5432
5433		/* 0xC0 - 0xDF */
5434		{&upd7810_device::MOV_PA_A, 2,14,14,L0\|L1}, {&upd7810_device::MOV_PB_A, 2,14,14,L0\|L1},
5435		{&upd7810_device::MOV_PC_A, 2,14,14,L0\|L1}, {&upd7810_device::MOV_MKL_A, 2,14,14,L0\|L1},
5436		{&upd7810_device::MOV_MB_A, 2,14,14,L0\|L1}, {&upd7810_device::MOV_MC_A, 2,14,14,L0\|L1},
5437		{&upd7810_device::MOV_TM0_A, 2,14,14,L0\|L1}, {&upd7810_device::MOV_TM1_A, 2,14,14,L0\|L1},
5438		{&upd7810_device::MOV_S_A, 2,14,14,L0\|L1}, {&upd7810_device::MOV_TMM_A, 2,14,14,L0\|L1},
5439		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5440		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5441		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5442
5443		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5444		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5445		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5446		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5447		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5448		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5449		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5450		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5451
5452		/* 0xE0 - 0xFF */
5453		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5454		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5455		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5456		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5457		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5458		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5459		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5460		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5461
5462		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5463		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5464		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5465		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5466		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5467		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5468		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5469		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1}
5470		};
5471
5472		/* prefix 60 */
5473		const struct upd7810_device::opcode_s upd7810_device::s_op60_78c06[256] =
5474		{
5475		/* 0x00 - 0x1F */
5476		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5477		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5478		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5479		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5480		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ANA_A_A, 2,12,12,L0\|L1},
5481		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5482		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5483		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5484
5485		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::XRA_A_A, 2,12,12,L0\|L1},
5486		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5487		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5488		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5489		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ORA_A_A, 2,12,12,L0\|L1},
5490		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5491		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5492		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5493
5494		/* 0x20 - 0x3F */
5495		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADDNC_A_A, 2,12,12,L0\|L1},
5496		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5497		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5498		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5499		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::GTA_A_A, 2,12,12,L0\|L1},
5500		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5501		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5502		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5503
5504		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SUBNB_A_A, 2,12,12,L0\|L1},
5505		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5506		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5507		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5508		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::LTA_A_A, 2,12,12,L0\|L1},
5509		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5510		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5511		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5512
5513		/* 0x40 - 0x5F */
5514		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADD_A_A, 2,12,12,L0\|L1},
5515		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5516		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5517		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5518		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5519		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5520		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5521		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5522
5523		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADC_A_A, 2,12,12,L0\|L1},
5524		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5525		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5526		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5527		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5528		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5529		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5530		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5531
5532		/* 0x60 - 0x7F */
5533		{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_A, 2,12,12,L0\|L1},
5534		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5535		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5536		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5537		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::NEA_A_A, 2,12,12,L0\|L1},
5538		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5539		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5540		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5541
5542		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SBB_A_A, 2,12,12,L0\|L1},
5543		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5544		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5545		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5546		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::EQA_A_A, 2,12,12,L0\|L1},
5547		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5548		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5549		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5550
5551		/* 0x80 - 0x9F */
5552		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5553		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5554		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5555		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5556		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ANA_A_A, 2,12,12,L0\|L1},
5557		{&upd7810_device::ANA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::ANA_A_C, 2,12,12,L0\|L1},
5558		{&upd7810_device::ANA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::ANA_A_E, 2,12,12,L0\|L1},
5559		{&upd7810_device::ANA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::ANA_A_L, 2,12,12,L0\|L1},
5560
5561		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::XRA_A_A, 2,12,12,L0\|L1},
5562		{&upd7810_device::XRA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::XRA_A_C, 2,12,12,L0\|L1},
5563		{&upd7810_device::XRA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::XRA_A_E, 2,12,12,L0\|L1},
5564		{&upd7810_device::XRA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::XRA_A_L, 2,12,12,L0\|L1},
5565		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ORA_A_A, 2,12,12,L0\|L1},
5566		{&upd7810_device::ORA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::ORA_A_C, 2,12,12,L0\|L1},
5567		{&upd7810_device::ORA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::ORA_A_E, 2,12,12,L0\|L1},
5568		{&upd7810_device::ORA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::ORA_A_L, 2,12,12,L0\|L1},
5569
5570		/* 0xA0 - 0xBF */
5571		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADDNC_A_A, 2,12,12,L0\|L1},
5572		{&upd7810_device::ADDNC_A_B, 2,12,12,L0\|L1}, {&upd7810_device::ADDNC_A_C, 2,12,12,L0\|L1},
5573		{&upd7810_device::ADDNC_A_D, 2,12,12,L0\|L1}, {&upd7810_device::ADDNC_A_E, 2,12,12,L0\|L1},
5574		{&upd7810_device::ADDNC_A_H, 2,12,12,L0\|L1}, {&upd7810_device::ADDNC_A_L, 2,12,12,L0\|L1},
5575		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::GTA_A_A, 2,12,12,L0\|L1},
5576		{&upd7810_device::GTA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::GTA_A_C, 2,12,12,L0\|L1},
5577		{&upd7810_device::GTA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::GTA_A_E, 2,12,12,L0\|L1},
5578		{&upd7810_device::GTA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::GTA_A_L, 2,12,12,L0\|L1},
5579
5580		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SUBNB_A_A, 2,12,12,L0\|L1},
5581		{&upd7810_device::SUBNB_A_B, 2,12,12,L0\|L1}, {&upd7810_device::SUBNB_A_C, 2,12,12,L0\|L1},
5582		{&upd7810_device::SUBNB_A_D, 2,12,12,L0\|L1}, {&upd7810_device::SUBNB_A_E, 2,12,12,L0\|L1},
5583		{&upd7810_device::SUBNB_A_H, 2,12,12,L0\|L1}, {&upd7810_device::SUBNB_A_L, 2,12,12,L0\|L1},
5584		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::LTA_A_A, 2,12,12,L0\|L1},
5585		{&upd7810_device::LTA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::LTA_A_C, 2,12,12,L0\|L1},
5586		{&upd7810_device::LTA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::LTA_A_E, 2,12,12,L0\|L1},
5587		{&upd7810_device::LTA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::LTA_A_L, 2,12,12,L0\|L1},
5588
5589		/* 0xC0 - 0xDF */
5590		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADD_A_A, 2,12,12,L0\|L1},
5591		{&upd7810_device::ADD_A_B, 2,12,12,L0\|L1}, {&upd7810_device::ADD_A_C, 2,12,12,L0\|L1},
5592		{&upd7810_device::ADD_A_D, 2,12,12,L0\|L1}, {&upd7810_device::ADD_A_E, 2,12,12,L0\|L1},
5593		{&upd7810_device::ADD_A_H, 2,12,12,L0\|L1}, {&upd7810_device::ADD_A_L, 2,12,12,L0\|L1},
5594		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ONA_A_A, 2,12,12,L0\|L1},
5595		{&upd7810_device::ONA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::ONA_A_C, 2,12,12,L0\|L1},
5596		{&upd7810_device::ONA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::ONA_A_E, 2,12,12,L0\|L1},
5597		{&upd7810_device::ONA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::ONA_A_L, 2,12,12,L0\|L1},
5598
5599		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADC_A_A, 2,12,12,L0\|L1},
5600		{&upd7810_device::ADC_A_B, 2,12,12,L0\|L1}, {&upd7810_device::ADC_A_C, 2,12,12,L0\|L1},
5601		{&upd7810_device::ADC_A_D, 2,12,12,L0\|L1}, {&upd7810_device::ADC_A_E, 2,12,12,L0\|L1},
5602		{&upd7810_device::ADC_A_H, 2,12,12,L0\|L1}, {&upd7810_device::ADC_A_L, 2,12,12,L0\|L1},
5603		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::OFFA_A_A, 2,12,12,L0\|L1},
5604		{&upd7810_device::OFFA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::OFFA_A_C, 2,12,12,L0\|L1},
5605		{&upd7810_device::OFFA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::OFFA_A_E, 2,12,12,L0\|L1},
5606		{&upd7810_device::OFFA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::OFFA_A_L, 2,12,12,L0\|L1},
5607
5608		/* 0xE0 - 0xFF */
5609		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SUB_A_A, 2,12,12,L0\|L1},
5610		{&upd7810_device::SUB_A_B, 2,12,12,L0\|L1}, {&upd7810_device::SUB_A_C, 2,12,12,L0\|L1},
5611		{&upd7810_device::SUB_A_D, 2,12,12,L0\|L1}, {&upd7810_device::SUB_A_E, 2,12,12,L0\|L1},
5612		{&upd7810_device::SUB_A_H, 2,12,12,L0\|L1}, {&upd7810_device::SUB_A_L, 2,12,12,L0\|L1},
5613		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::NEA_A_A, 2,12,12,L0\|L1},
5614		{&upd7810_device::NEA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::NEA_A_C, 2,12,12,L0\|L1},
5615		{&upd7810_device::NEA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::NEA_A_E, 2,12,12,L0\|L1},
5616		{&upd7810_device::NEA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::NEA_A_L, 2,12,12,L0\|L1},
5617
5618		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SBB_A_A, 2,12,12,L0\|L1},
5619		{&upd7810_device::SBB_A_B, 2,12,12,L0\|L1}, {&upd7810_device::SBB_A_C, 2,12,12,L0\|L1},
5620		{&upd7810_device::SBB_A_D, 2,12,12,L0\|L1}, {&upd7810_device::SBB_A_E, 2,12,12,L0\|L1},
5621		{&upd7810_device::SBB_A_H, 2,12,12,L0\|L1}, {&upd7810_device::SBB_A_L, 2,12,12,L0\|L1},
5622		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::EQA_A_A, 2,12,12,L0\|L1},
5623		{&upd7810_device::EQA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::EQA_A_C, 2,12,12,L0\|L1},
5624		{&upd7810_device::EQA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::EQA_A_E, 2,12,12,L0\|L1},
5625		{&upd7810_device::EQA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::EQA_A_L, 2,12,12,L0\|L1}
5626		};
5627
5628		/* prefix 64 */
5629		const struct upd7810_device::opcode_s upd7810_device::s_op64_78c06[256] =
5630		{
5631		/* 0x00 - 0x1F */
5632		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5633		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5634		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5635		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5636		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ANI_A_xx, 3,17,17,L0\|L1},
5637		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5638		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5639		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5640
5641		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::XRI_A_xx, 3,17,17,L0\|L1},
5642		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5643		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5644		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5645		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ORI_A_xx, 3,17,17,L0\|L1},
5646		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5647		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5648		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5649
5650		/* 0x20 - 0x3F */
5651		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADINC_A_xx, 3,17,17,L0\|L1},
5652		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5653		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5654		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5655		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::GTI_A_xx, 3,17,17,L0\|L1},
5656		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5657		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5658		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5659
5660		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SUINB_A_xx, 3,17,17,L0\|L1},
5661		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5662		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5663		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5664		{&upd7810_device::illegal2, 3,12,12,L0\|L1}, {&upd7810_device::LTI_A_xx, 3,17,17,L0\|L1},
5665		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5666		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5667		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5668
5669		/* 0x40 - 0x5F */
5670		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADI_A_xx, 3,17,17,L0\|L1},
5671		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5672		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5673		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5674		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ONI_A_xx, 3,17,17,L0\|L1},
5675		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5676		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5677		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5678
5679		{&upd7810_device::illegal2, 3,12,12,L0\|L1}, {&upd7810_device::ACI_A_xx, 3,17,17,L0\|L1},
5680		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5681		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5682		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5683		{&upd7810_device::illegal2, 3,12,12,L0\|L1}, {&upd7810_device::OFFI_A_xx, 3,17,17,L0\|L1},
5684		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5685		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5686		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5687
5688		/* 0x60 - 0x7F */
5689		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SUI_A_xx, 3,17,17,L0\|L1},
5690		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5691		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5692		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5693		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::NEI_A_xx, 3,17,17,L0\|L1},
5694		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5695		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5696		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5697
5698		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SBI_A_xx, 3,17,17,L0\|L1},
5699		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5700		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5701		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5702		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::EQI_A_xx, 3,17,17,L0\|L1},
5703		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5704		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5705		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5706
5707		/* 0x80 - 0x9F */
5708		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5709		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5710		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5711		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5712		{&upd7810_device::ANI_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::ANI_PB_xx, 3,23,23,L0\|L1},
5713		{&upd7810_device::ANI_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::ANI_MKL_xx, 3,23,23,L0\|L1},
5714		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5715		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5716
5717		{&upd7810_device::XRI_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::XRI_PB_xx, 3,23,23,L0\|L1},
5718		{&upd7810_device::XRI_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::XRI_MKL_xx, 3,23,23,L0\|L1},
5719		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5720		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5721		{&upd7810_device::ORI_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::ORI_PB_xx, 3,23,23,L0\|L1},
5722		{&upd7810_device::ORI_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::ORI_MKL_xx, 3,23,23,L0\|L1},
5723		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5724		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5725
5726		/* 0xA0 - 0xBF */
5727		{&upd7810_device::ADINC_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::ADINC_PB_xx, 3,23,23,L0\|L1},
5728		{&upd7810_device::ADINC_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::ADINC_MKL_xx, 3,23,23,L0\|L1},
5729		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5730		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5731		{&upd7810_device::GTI_PA_xx, 3,20,20,L0\|L1}, {&upd7810_device::GTI_PB_xx, 3,20,20,L0\|L1},
5732		{&upd7810_device::GTI_PC_xx, 3,20,20,L0\|L1}, {&upd7810_device::GTI_MKL_xx, 3,20,20,L0\|L1},
5733		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5734		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5735
5736		{&upd7810_device::SUINB_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::SUINB_PB_xx, 3,23,23,L0\|L1},
5737		{&upd7810_device::SUINB_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::SUINB_MKL_xx, 3,23,23,L0\|L1},
5738		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5739		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5740		{&upd7810_device::LTI_PA_xx, 3,20,20,L0\|L1}, {&upd7810_device::LTI_PB_xx, 3,20,20,L0\|L1},
5741		{&upd7810_device::LTI_PC_xx, 3,20,20,L0\|L1}, {&upd7810_device::LTI_MKL_xx, 3,20,20,L0\|L1},
5742		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5743		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5744
5745		/* 0xC0 - 0xDF */
5746		{&upd7810_device::ADI_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::ADI_PB_xx, 3,23,23,L0\|L1},
5747		{&upd7810_device::ADI_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::ADI_MKL_xx, 3,23,23,L0\|L1},
5748		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5749		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5750		{&upd7810_device::ONI_PA_xx, 3,20,20,L0\|L1}, {&upd7810_device::ONI_PB_xx, 3,20,20,L0\|L1},
5751		{&upd7810_device::ONI_PC_xx, 3,20,20,L0\|L1}, {&upd7810_device::ONI_MKL_xx, 3,20,20,L0\|L1},
5752		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5753		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5754
5755		{&upd7810_device::ACI_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::ACI_PB_xx, 3,23,23,L0\|L1},
5756		{&upd7810_device::ACI_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::ACI_MKL_xx, 3,23,23,L0\|L1},
5757		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5758		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5759		{&upd7810_device::OFFI_PA_xx, 3,20,20,L0\|L1}, {&upd7810_device::OFFI_PB_xx, 3,20,20,L0\|L1},
5760		{&upd7810_device::OFFI_PC_xx, 3,20,20,L0\|L1}, {&upd7810_device::OFFI_MKL_xx, 3,20,20,L0\|L1},
5761		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5762		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5763
5764		/* 0xE0 - 0xFF */
5765		{&upd7810_device::SUI_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::SUI_PB_xx, 3,23,23,L0\|L1},
5766		{&upd7810_device::SUI_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::SUI_MKL_xx, 3,23,23,L0\|L1},
5767		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5768		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5769		{&upd7810_device::NEI_PA_xx, 3,20,20,L0\|L1}, {&upd7810_device::NEI_PB_xx, 3,20,20,L0\|L1},
5770		{&upd7810_device::NEI_PC_xx, 3,20,20,L0\|L1}, {&upd7810_device::NEI_MKL_xx, 3,20,20,L0\|L1},
5771		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5772		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5773
5774		{&upd7810_device::SBI_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::SBI_PB_xx, 3,23,23,L0\|L1},
5775		{&upd7810_device::SBI_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::SBI_MKL_xx, 3,23,23,L0\|L1},
5776		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5777		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5778		{&upd7810_device::EQI_PA_xx, 3,20,20,L0\|L1}, {&upd7810_device::EQI_PB_xx, 3,20,20,L0\|L1},
5779		{&upd7810_device::EQI_PC_xx, 3,20,20,L0\|L1}, {&upd7810_device::EQI_MKL_xx, 3,20,20,L0\|L1},
5780		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5781		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1}
5782		};
5783
5784		/* prefix 70 */
5785		const struct upd7810_device::opcode_s upd7810_device::s_op70_78c06[256] =
5786		{
5787		/* 0x00 - 0x1F */
5788		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5789		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5790		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5791		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5792		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5793		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5794		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5795		{&upd7810_device::SSPD_w, 4,28,28,L0\|L1}, {&upd7810_device::LSPD_w, 4,28,28,L0\|L1},
5796
5797		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5798		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5799		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5800		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5801		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5802		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5803		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5804		{&upd7810_device::SBCD_w, 4,28,28,L0\|L1}, {&upd7810_device::LBCD_w, 4,28,28,L0\|L1},
5805
5806		/* 0x20 - 0x3F */
5807		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5808		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5809		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5810		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5811		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5812		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5813		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5814		{&upd7810_device::SDED_w, 4,28,28,L0\|L1}, {&upd7810_device::LDED_w, 4,28,28,L0\|L1},
5815
5816		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5817		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5818		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5819		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5820		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5821		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5822		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5823		{&upd7810_device::SHLD_w, 4,28,28,L0\|L1}, {&upd7810_device::LHLD_w, 4,28,28,L0\|L1},
5824
5825		/* 0x40 - 0x5F */
5826		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5827		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5828		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5829		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5830		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5831		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5832		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5833		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5834
5835		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5836		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5837		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5838		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5839		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5840		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5841		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5842		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5843
5844		/* 0x60 - 0x7F */
5845		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5846		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5847		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5848		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5849		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::MOV_A_w, 4,25,25,L0\|L1},
5850		{&upd7810_device::MOV_B_w, 4,25,25,L0\|L1}, {&upd7810_device::MOV_C_w, 4,25,25,L0\|L1},
5851		{&upd7810_device::MOV_D_w, 4,25,25,L0\|L1}, {&upd7810_device::MOV_E_w, 4,25,25,L0\|L1},
5852		{&upd7810_device::MOV_H_w, 4,25,25,L0\|L1}, {&upd7810_device::MOV_L_w, 4,25,25,L0\|L1},
5853
5854		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5855		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5856		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5857		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5858		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::MOV_w_A, 4,25,25,L0\|L1},
5859		{&upd7810_device::MOV_w_B, 4,25,25,L0\|L1}, {&upd7810_device::MOV_w_C, 4,25,25,L0\|L1},
5860		{&upd7810_device::MOV_w_D, 4,25,25,L0\|L1}, {&upd7810_device::MOV_w_E, 4,25,25,L0\|L1},
5861		{&upd7810_device::MOV_w_H, 4,25,25,L0\|L1}, {&upd7810_device::MOV_w_L, 4,25,25,L0\|L1},
5862
5863		/* 0x80 - 0x9F */
5864		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5865		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5866		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5867		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5868		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ANAX_B, 2,15,15,L0\|L1},
5869		{&upd7810_device::ANAX_D, 2,15,15,L0\|L1}, {&upd7810_device::ANAX_H, 2,15,15,L0\|L1},
5870		{&upd7810_device::ANAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::ANAX_Hp, 2,15,15,L0\|L1},
5871		{&upd7810_device::ANAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::ANAX_Hm, 2,15,15,L0\|L1},
5872
5873		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::XRAX_B, 2,15,15,L0\|L1},
5874		{&upd7810_device::XRAX_D, 2,15,15,L0\|L1}, {&upd7810_device::XRAX_H, 2,15,15,L0\|L1},
5875		{&upd7810_device::XRAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::XRAX_Hp, 2,15,15,L0\|L1},
5876		{&upd7810_device::XRAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::XRAX_Hm, 2,15,15,L0\|L1},
5877		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ORAX_B, 2,15,15,L0\|L1},
5878		{&upd7810_device::ORAX_D, 2,15,15,L0\|L1}, {&upd7810_device::ORAX_H, 2,15,15,L0\|L1},
5879		{&upd7810_device::ORAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::ORAX_Hp, 2,15,15,L0\|L1},
5880		{&upd7810_device::ORAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::ORAX_Hm, 2,15,15,L0\|L1},
5881
5882		/* 0xA0 - 0xBF */
5883		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADDNCX_B, 2,15,15,L0\|L1},
5884		{&upd7810_device::ADDNCX_D, 2,15,15,L0\|L1}, {&upd7810_device::ADDNCX_H, 2,15,15,L0\|L1},
5885		{&upd7810_device::ADDNCX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::ADDNCX_Hp, 2,15,15,L0\|L1},
5886		{&upd7810_device::ADDNCX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::ADDNCX_Hm, 2,15,15,L0\|L1},
5887		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::GTAX_B, 2,15,15,L0\|L1},
5888		{&upd7810_device::GTAX_D, 2,15,15,L0\|L1}, {&upd7810_device::GTAX_H, 2,15,15,L0\|L1},
5889		{&upd7810_device::GTAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::GTAX_Hp, 2,15,15,L0\|L1},
5890		{&upd7810_device::GTAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::GTAX_Hm, 2,15,15,L0\|L1},
5891
5892		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SUBNBX_B, 2,15,15,L0\|L1},
5893		{&upd7810_device::SUBNBX_D, 2,15,15,L0\|L1}, {&upd7810_device::SUBNBX_H, 2,15,15,L0\|L1},
5894		{&upd7810_device::SUBNBX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::SUBNBX_Hp, 2,15,15,L0\|L1},
5895		{&upd7810_device::SUBNBX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::SUBNBX_Hm, 2,15,15,L0\|L1},
5896		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::LTAX_B, 2,15,15,L0\|L1},
5897		{&upd7810_device::LTAX_D, 2,15,15,L0\|L1}, {&upd7810_device::LTAX_H, 2,15,15,L0\|L1},
5898		{&upd7810_device::LTAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::LTAX_Hp, 2,15,15,L0\|L1},
5899		{&upd7810_device::LTAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::LTAX_Hm, 2,15,15,L0\|L1},
5900
5901		/* 0xC0 - 0xDF */
5902		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADDX_B, 2,15,15,L0\|L1},
5903		{&upd7810_device::ADDX_D, 2,15,15,L0\|L1}, {&upd7810_device::ADDX_H, 2,15,15,L0\|L1},
5904		{&upd7810_device::ADDX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::ADDX_Hp, 2,15,15,L0\|L1},
5905		{&upd7810_device::ADDX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::ADDX_Hm, 2,15,15,L0\|L1},
5906		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ONAX_B, 2,15,15,L0\|L1},
5907		{&upd7810_device::ONAX_D, 2,15,15,L0\|L1}, {&upd7810_device::ONAX_H, 2,15,15,L0\|L1},
5908		{&upd7810_device::ONAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::ONAX_Hp, 2,15,15,L0\|L1},
5909		{&upd7810_device::ONAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::ONAX_Hm, 2,15,15,L0\|L1},
5910
5911		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADCX_B, 2,15,15,L0\|L1},
5912		{&upd7810_device::ADCX_D, 2,15,15,L0\|L1}, {&upd7810_device::ADCX_H, 2,15,15,L0\|L1},
5913		{&upd7810_device::ADCX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::ADCX_Hp, 2,15,15,L0\|L1},
5914		{&upd7810_device::ADCX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::ADCX_Hm, 2,15,15,L0\|L1},
5915		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::OFFAX_B, 2,15,15,L0\|L1},
5916		{&upd7810_device::OFFAX_D, 2,15,15,L0\|L1}, {&upd7810_device::OFFAX_H, 2,15,15,L0\|L1},
5917		{&upd7810_device::OFFAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::OFFAX_Hp, 2,15,15,L0\|L1},
5918		{&upd7810_device::OFFAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::OFFAX_Hm, 2,15,15,L0\|L1},
5919
5920		/* 0xE0 - 0xFF */
5921		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SUBX_B, 2,15,15,L0\|L1},
5922		{&upd7810_device::SUBX_D, 2,15,15,L0\|L1}, {&upd7810_device::SUBX_H, 2,15,15,L0\|L1},
5923		{&upd7810_device::SUBX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::SUBX_Hp, 2,15,15,L0\|L1},
5924		{&upd7810_device::SUBX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::SUBX_Hm, 2,15,15,L0\|L1},
5925		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::NEAX_B, 2,15,15,L0\|L1},
5926		{&upd7810_device::NEAX_D, 2,15,15,L0\|L1}, {&upd7810_device::NEAX_H, 2,15,15,L0\|L1},
5927		{&upd7810_device::NEAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::NEAX_Hp, 2,15,15,L0\|L1},
5928		{&upd7810_device::NEAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::NEAX_Hm, 2,15,15,L0\|L1},
5929
5930		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SBBX_B, 2,15,15,L0\|L1},
5931		{&upd7810_device::SBBX_D, 2,15,15,L0\|L1}, {&upd7810_device::SBBX_H, 2,15,15,L0\|L1},
5932		{&upd7810_device::SBBX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::SBBX_Hp, 2,15,15,L0\|L1},
5933		{&upd7810_device::SBBX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::SBBX_Hm, 2,15,15,L0\|L1},
5934		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::EQAX_B, 2,15,15,L0\|L1},
5935		{&upd7810_device::EQAX_D, 2,15,15,L0\|L1}, {&upd7810_device::EQAX_H, 2,15,15,L0\|L1},
5936		{&upd7810_device::EQAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::EQAX_Hp, 2,15,15,L0\|L1},
5937		{&upd7810_device::EQAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::EQAX_Hm, 2,15,15,L0\|L1}
5938		};
5939
5940		/* prefix 74 */
5941		const struct upd7810_device::opcode_s upd7810_device::s_op74_78c06[256] =
5942		{
5943		/* 0x00 - 0x1F */
5944		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5945		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5946		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5947		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5948		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5949		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5950		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5951		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5952
5953		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5954		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5955		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5956		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5957		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5958		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5959		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5960		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5961
5962		/* 0x20 - 0x3F */
5963		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5964		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5965		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5966		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5967		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5968		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5969		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5970		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5971
5972		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5973		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5974		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5975		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5976		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5977		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5978		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5979		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5980
5981		/* 0x40 - 0x5F */
5982		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5983		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5984		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5985		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5986		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5987		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5988		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5989		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5990
5991		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5992		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5993		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5994		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5995		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5996		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5997		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5998		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
5999
6000		/* 0x60 - 0x7F */
6001		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6002		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6003		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6004		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6005		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6006		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6007		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6008		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6009
6010		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6011		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6012		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6013		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6014		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6015		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6016		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6017		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6018
6019		/* 0x80 - 0x9F */
6020		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6021		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6022		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6023		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6024		{&upd7810_device::ANAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6025		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6026		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6027		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6028
6029		{&upd7810_device::XRAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6030		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6031		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6032		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6033		{&upd7810_device::ORAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6034		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6035		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6036		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6037
6038		/* 0xA0 - 0xBF */
6039		{&upd7810_device::ADDNCW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6040		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6041		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6042		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6043		{&upd7810_device::GTAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6044		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6045		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6046		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6047
6048		{&upd7810_device::SUBNBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6049		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6050		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6051		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6052		{&upd7810_device::LTAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6053		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6054		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6055		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6056
6057		/* 0xC0 - 0xDF */
6058		{&upd7810_device::ADDW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6059		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6060		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6061		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6062		{&upd7810_device::ONAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6063		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6064		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6065		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6066
6067		{&upd7810_device::ADCW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6068		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6069		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6070		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6071		{&upd7810_device::OFFAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6072		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6073		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6074		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6075
6076		/* 0xE0 - 0xFF */
6077		{&upd7810_device::SUBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6078		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6079		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6080		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6081		{&upd7810_device::NEAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6082		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6083		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6084		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6085
6086		{&upd7810_device::SBBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6087		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6088		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6089		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6090		{&upd7810_device::EQAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6091		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6092		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
6093		{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1}
6094		};
6095
6096		const struct upd7810_device::opcode_s upd7810_device::s_opXX_78c06[256] =
6097		{
6098		/* 0x00 - 0x1F */
6099		{&upd7810_device::NOP, 1, 6, 6,L0\|L1}, {&upd7810_device::HALT, 1, 6, 6,L0\|L1},
6100		{&upd7810_device::INX_SP, 1, 9, 9,L0\|L1}, {&upd7810_device::DCX_SP, 1, 9, 9,L0\|L1},
6101		{&upd7810_device::LXI_S_w, 3,16,16,L0\|L1}, {&upd7810_device::ANIW_wa_xx, 3,22,22,L0\|L1},
6102		{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::ANI_A_xx, 2,11,11,L0\|L1},
6103		{&upd7810_device::RET, 1,12,12,L0\|L1}, {&upd7810_device::SIO, 1, 6, 6,L0\|L1},
6104		{&upd7810_device::MOV_A_B, 1, 6, 6,L0\|L1}, {&upd7810_device::MOV_A_C, 1, 6, 6,L0\|L1},
6105		{&upd7810_device::MOV_A_D, 1, 6, 6,L0\|L1}, {&upd7810_device::MOV_A_E, 1, 6, 6,L0\|L1},
6106		{&upd7810_device::MOV_A_H, 1, 6, 6,L0\|L1}, {&upd7810_device::MOV_A_L, 1, 6, 6,L0\|L1},
6107
6108		{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::illegal, 1, 6, 6,L0\|L1},
6109		{&upd7810_device::INX_BC, 1, 9, 9,L0\|L1}, {&upd7810_device::DCX_BC, 1, 9, 9,L0\|L1},
6110		{&upd7810_device::LXI_B_w, 3,16,16,L0\|L1}, {&upd7810_device::ORIW_wa_xx, 3,22,2,L0\|L1},
6111		{&upd7810_device::XRI_A_xx, 2,11,11,L0\|L1}, {&upd7810_device::ORI_A_xx, 2,11,11,L0\|L1},
6112		{&upd7810_device::RETS, 1,12,12,L0\|L1}, {&upd7810_device::STM, 1, 6, 6,L0\|L1},
6113		{&upd7810_device::MOV_B_A, 1, 6, 6,L0\|L1}, {&upd7810_device::MOV_C_A, 1, 6, 6,L0\|L1},
6114		{&upd7810_device::MOV_D_A, 1, 6, 6,L0\|L1}, {&upd7810_device::MOV_E_A, 1, 6, 6,L0\|L1},
6115		{&upd7810_device::MOV_H_A, 1, 6, 6,L0\|L1}, {&upd7810_device::MOV_L_A, 1, 6, 6,L0\|L1},
6116
6117		/* 0x20 - 0x3F */
6118		{&upd7810_device::INRW_wa_7801, 2,17,17,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
6119		{&upd7810_device::INX_DE, 1, 9, 9,L0\|L1}, {&upd7810_device::DCX_DE, 1, 9, 9,L0\|L1},
6120		{&upd7810_device::LXI_D_w, 3,16,16,L0\|L1}, {&upd7810_device::GTIW_wa_xx, 3,19,19,L0\|L1},
6121		{&upd7810_device::ADINC_A_xx, 2,11,11,L0\|L1}, {&upd7810_device::GTI_A_xx, 2,11,11,L0\|L1},
6122		{&upd7810_device::LDAW_wa, 2,14,14,L0\|L1}, {&upd7810_device::LDAX_B, 1, 9, 9,L0\|L1},
6123		{&upd7810_device::LDAX_D, 1, 9, 9,L0\|L1}, {&upd7810_device::LDAX_H, 1, 9, 9,L0\|L1},
6124		{&upd7810_device::LDAX_Dp, 1, 9, 9,L0\|L1}, {&upd7810_device::LDAX_Hp, 1, 9, 9,L0\|L1},
6125		{&upd7810_device::LDAX_Dm, 1, 9, 9,L0\|L1}, {&upd7810_device::LDAX_Hm, 1, 9, 9,L0\|L1},
6126
6127		{&upd7810_device::DCRW_wa_7801, 2,17,17,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
6128		{&upd7810_device::INX_HL, 1, 9, 9,L0\|L1}, {&upd7810_device::DCX_HL, 1, 9, 9,L0\|L1},
6129		{&upd7810_device::LXI_H_w, 3,16,16, L1}, {&upd7810_device::LTIW_wa_xx, 3,19,19,L0\|L1},
6130		{&upd7810_device::SUINB_A_xx, 2,11,11,L0\|L1}, {&upd7810_device::LTI_A_xx, 2,11,11,L0\|L1},
6131		{&upd7810_device::STAW_wa, 2,14,14,L0\|L1}, {&upd7810_device::STAX_B, 1, 9, 9,L0\|L1},
6132		{&upd7810_device::STAX_D, 1, 9, 9,L0\|L1}, {&upd7810_device::STAX_H, 1, 9, 9,L0\|L1},
6133		{&upd7810_device::STAX_Dp, 1, 9, 9,L0\|L1}, {&upd7810_device::STAX_Hp, 1, 9, 9,L0\|L1},
6134		{&upd7810_device::STAX_Dm, 1, 9, 9,L0\|L1}, {&upd7810_device::STAX_Hm, 1, 9, 9,L0\|L1},
6135
6136		/* 0x40 - 0x5F */
6137		{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::INR_A_7801, 1, 6, 6,L0\|L1},
6138		{&upd7810_device::INR_B_7801, 1, 6, 6,L0\|L1}, {&upd7810_device::INR_C_7801, 1, 6, 6,L0\|L1},
6139		{&upd7810_device::CALL_w, 3,22,22,L0\|L1}, {&upd7810_device::ONIW_wa_xx, 3,19,19,L0\|L1},
6140		{&upd7810_device::ADI_A_xx, 2,11,11,L0\|L1}, {&upd7810_device::ONI_A_xx, 2,11,11,L0\|L1},
6141		{&upd7810_device::PRE_48, 1, 0, 0,L0\|L1}, {&upd7810_device::illegal, 1, 6, 6,L0\|L1},
6142		{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::illegal, 1, 6, 6,L0\|L1},
6143		{&upd7810_device::PRE_4C, 1, 0, 0,L0\|L1}, {&upd7810_device::PRE_4D, 1, 0, 0,L0\|L1},
6144		{&upd7810_device::JRE, 2,17,17,L0\|L1}, {&upd7810_device::JRE, 2,17,17,L0\|L1},
6145
6146		{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::DCR_A_7801, 1, 6, 6,L0\|L1},
6147		{&upd7810_device::DCR_B_7801, 1, 6, 6,L0\|L1}, {&upd7810_device::DCR_C_7801, 1, 6, 6,L0\|L1},
6148		{&upd7810_device::JMP_w, 3,16,16,L0\|L1}, {&upd7810_device::OFFIW_wa_xx, 3,19,19,L0\|L1},
6149		{&upd7810_device::ACI_A_xx, 2,11,11,L0\|L1}, {&upd7810_device::OFFI_A_xx, 2,11,11,L0\|L1},
6150		{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::illegal, 1, 6, 6,L0\|L1},
6151		{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::illegal, 1, 6, 6,L0\|L1},
6152		{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::illegal, 1, 6, 6,L0\|L1},
6153		{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::illegal, 1, 6, 6,L0\|L1},
6154
6155		/* 0x60 - 0x7F */
6156		{&upd7810_device::PRE_60, 1, 0, 0,L0\|L1}, {&upd7810_device::DAA, 1, 6, 6,L0\|L1},
6157		{&upd7810_device::RETI, 1,15,15,L0\|L1}, {&upd7810_device::CALB, 2,13,13,L0\|L1},
6158		{&upd7810_device::PRE_64, 1, 0, 0,L0\|L1}, {&upd7810_device::NEIW_wa_xx, 3,19,19,L0\|L1},
6159		{&upd7810_device::SUI_A_xx, 2,11,11,L0\|L1}, {&upd7810_device::NEI_A_xx, 2,11,11,L0\|L1},
6160		{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::MVI_A_xx, 2,11,11,L0 },
6161		{&upd7810_device::MVI_B_xx, 2,11,11,L0\|L1}, {&upd7810_device::MVI_C_xx, 2,11,11,L0\|L1},
6162		{&upd7810_device::MVI_D_xx, 2,11,11,L0\|L1}, {&upd7810_device::MVI_E_xx, 2,11,11,L0\|L1},
6163		{&upd7810_device::MVI_H_xx, 2,11,11,L0\|L1}, {&upd7810_device::MVI_L_xx, 2,11,11, L1},
6164
6165		{&upd7810_device::PRE_70, 1, 0, 0,L0\|L1}, {&upd7810_device::MVIW_wa_xx, 3,13,13,L0\|L1},
6166		{&upd7810_device::SOFTI, 1,19,19,L0\|L1}, {&upd7810_device::JB, 1, 6, 6,L0\|L1},
6167		{&upd7810_device::PRE_74, 1, 0, 0,L0\|L1}, {&upd7810_device::EQIW_wa_xx, 3,19,19,L0\|L1},
6168		{&upd7810_device::SBI_A_xx, 2,11,11,L0\|L1}, {&upd7810_device::EQI_A_xx, 2,11,11,L0\|L1},
6169		{&upd7810_device::CALF, 2,17,17,L0\|L1}, {&upd7810_device::CALF, 2,17,17,L0\|L1},
6170		{&upd7810_device::CALF, 2,17,17,L0\|L1}, {&upd7810_device::CALF, 2,17,17,L0\|L1},
6171		{&upd7810_device::CALF, 2,17,17,L0\|L1}, {&upd7810_device::CALF, 2,17,17,L0\|L1},
6172		{&upd7810_device::CALF, 2,17,17,L0\|L1}, {&upd7810_device::CALF, 2,17,17,L0\|L1},
6173
6174		/* 0x80 - 0x9F */
6175		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6176		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6177		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6178		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6179		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6180		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6181		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6182		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6183
6184		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6185		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6186		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6187		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6188		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6189		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6190		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6191		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6192
6193		/* 0xA0 - 0xBF */
6194		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6195		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6196		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6197		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6198		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6199		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6200		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6201		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6202
6203		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6204		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6205		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6206		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6207		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6208		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6209		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6210		{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
6211
6212		/* 0xC0 - 0xDF */
6213		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6214		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6215		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6216		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6217		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6218		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6219		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6220		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6221
6222		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6223		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6224		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6225		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6226		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6227		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6228		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6229		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6230
6231		/* 0xE0 - 0xFF */
6232		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6233		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6234		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6235		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6236		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6237		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6238		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6239		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6240
6241		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6242		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6243		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6244		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6245		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6246		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6247		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
6248		{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1}
6249		};

trunk/src/emu/cpu/upd7810/upd7810_dasm.c
r0	r30938
	1	/*****************************************************************************
	2	*
	3	* Portable uPD7810/11, 7810H/11H, 78C10/C11/C14 disassembler
	4	* Copyright Juergen Buchmueller, all rights reserved.
	5	*
	6	* NS20030112: added 7807.
	7	*
	8	*****************************************************************************/
	9
	10	#include "emu.h"
	11	#include "debugger.h"
	12	#include "upd7810.h"
	13
	14	struct dasm_s {
	15	UINT8 token;
	16	const void *args;
	17	};
	18
	19	enum
	20	{
	21	illegal=1,
	22	ACI,
	23	ADC,
	24	ADCW,
	25	ADCX,
	26	ADD,
	27	ADDNC,
	28	ADDNCW,
	29	ADDNCX,
	30	ADDW,
	31	ADDX,
	32	ADI,
	33	ADINC,
	34	ANA,
	35	ANAW,
	36	ANAX,
	37	AND,
	38	ANI,
	39	ANIW,
	40	BIT,
	41	BLOCK,
	42	CALB,
	43	CALF,
	44	CALL,
	45	CALT,
	46	CLC,
	47	CLR, /* 7807 */
	48	CMC, /* 7807 */
	49	DAA,
	50	DADC,
	51	DADD,
	52	DADDNC,
	53	DAN,
	54	DCR,
	55	DCRW,
	56	DCX,
	57	DEQ,
	58	DGT,
	59	DI,
	60	DIV,
	61	DLT,
	62	DMOV,
	63	DNE,
	64	DOFF,
	65	DON,
	66	DOR,
	67	DRLL,
	68	DRLR,
	69	DSBB,
	70	DSLL,
	71	DSLR,
	72	DSUB,
	73	DSUBNB,
	74	DXR,
	75	EADD,
	76	EI,
	77	EQA,
	78	EQAW,
	79	EQAX,
	80	EQI,
	81	EQIW,
	82	ESUB,
	83	EX, /* 7801 */
	84	EXA,
	85	EXH,
	86	EXX,
	87	EXR, /* 7807 */
	88	GTA,
	89	GTAW,
	90	GTAX,
	91	GTI,
	92	GTIW,
	93	HALT,
	94	IN, /* 7801 */
	95	INR,
	96	INRW,
	97	INX,
	98	JB,
	99	JEA,
	100	JMP,
	101	JR,
	102	JRE,
	103	LBCD,
	104	LDAW,
	105	LDAX,
	106	LDEAX,
	107	LDED,
	108	LHLD,
	109	LSPD,
	110	LTA,
	111	LTAW,
	112	LTAX,
	113	LTI,
	114	LTIW,
	115	LXI,
	116	MOV,
	117	MUL,
	118	MVI,
	119	MVIW,
	120	MVIX,
	121	NEA,
	122	NEAW,
	123	NEAX,
	124	NEGA,
	125	NEI,
	126	NEIW,
	127	NOP,
	128	NOT, /* 7807 */
	129	OFFA,
	130	OFFAW,
	131	OFFAX,
	132	OFFI,
	133	OFFIW,
	134	ONA,
	135	ONAW,
	136	ONAX,
	137	ONI,
	138	ONIW,
	139	OR, /* 7807 */
	140	ORA,
	141	ORAW,
	142	ORAX,
	143	ORI,
	144	ORIW,
	145	OUT, /* 7801 */
	146	PER, /* 7801 */
	147	PEX, /* 7801 */
	148	POP,
	149	PUSH,
	150	RET,
	151	RETI,
	152	RETS,
	153	RLD,
	154	RLL,
	155	RLR,
	156	RRD,
	157	SBB,
	158	SBBW,
	159	SBBX,
	160	SBCD,
	161	SBI,
	162	SDED,
	163	SETB, /* 7807 */
	164	SHLD,
	165	SIO, /* 7801 */
	166	SK,
	167	SKIT,
	168	SKN,
	169	SKNIT,
	170	SLL,
	171	SLLC,
	172	SLR,
	173	SLRC,
	174	SOFTI,
	175	SSPD,
	176	STAW,
	177	STAX,
	178	STC,
	179	STEAX,
	180	STM, /* 7801 */
	181	STOP,
	182	SUB,
	183	SUBNB,
	184	SUBNBW,
	185	SUBNBX,
	186	SUBW,
	187	SUBX,
	188	SUI,
	189	SUINB,
	190	TABLE,
	191	XOR, /* 7807 */
	192	XRA,
	193	XRAW,
	194	XRAX,
	195	XRI
	196	};
	197
	198	static const char *const token[] =
	199	{
	200	"",
	201	"illegal",
	202	"ACI",
	203	"ADC",
	204	"ADCW",
	205	"ADCX",
	206	"ADD",
	207	"ADDNC",
	208	"ADDNCW",
	209	"ADDNCX",
	210	"ADDW",
	211	"ADDX",
	212	"ADI",
	213	"ADINC",
	214	"ANA",
	215	"ANAW",
	216	"ANAX",
	217	"AND",
	218	"ANI",
	219	"ANIW",
	220	"BIT",
	221	"BLOCK",
	222	"CALB",
	223	"CALF",
	224	"CALL",
	225	"CALT",
	226	"CLC",
	227	"CLR", /* 7807 */
	228	"CMC", /* 7807 */
	229	"DAA",
	230	"DADC",
	231	"DADD",
	232	"DADDNC",
	233	"DAN",
	234	"DCR",
	235	"DCRW",
	236	"DCX",
	237	"DEQ",
	238	"DGT",
	239	"DI",
	240	"DIV",
	241	"DLT",
	242	"DMOV",
	243	"DNE",
	244	"DOFF",
	245	"DON",
	246	"DOR",
	247	"DRLL",
	248	"DRLR",
	249	"DSBB",
	250	"DSLL",
	251	"DSLR",
	252	"DSUB",
	253	"DSUBNB",
	254	"DXR",
	255	"EADD",
	256	"EI",
	257	"EQA",
	258	"EQAW",
	259	"EQAX",
	260	"EQI",
	261	"EQIW",
	262	"ESUB",
	263	"EX", /* 7801 */
	264	"EXA",
	265	"EXH",
	266	"EXX",
	267	"EXR", /* 7807 */
	268	"GTA",
	269	"GTAW",
	270	"GTAX",
	271	"GTI",
	272	"GTIW",
	273	"HALT",
	274	"IN", /* 7801 */
	275	"INR",
	276	"INRW",
	277	"INX",
	278	"JB",
	279	"JEA",
	280	"JMP",
	281	"JR",
	282	"JRE",
	283	"LBCD",
	284	"LDAW",
	285	"LDAX",
	286	"LDEAX",
	287	"LDED",
	288	"LHLD",
	289	"LSPD",
	290	"LTA",
	291	"LTAW",
	292	"LTAX",
	293	"LTI",
	294	"LTIW",
	295	"LXI",
	296	"MOV",
	297	"MUL",
	298	"MVI",
	299	"MVIW",
	300	"MVIX",
	301	"NEA",
	302	"NEAW",
	303	"NEAX",
	304	"NEGA",
	305	"NEI",
	306	"NEIW",
	307	"NOP",
	308	"NOT", /* 7807 */
	309	"OFFA",
	310	"OFFAW",
	311	"OFFAX",
	312	"OFFI",
	313	"OFFIW",
	314	"ONA",
	315	"ONAW",
	316	"ONAX",
	317	"ONI",
	318	"ONIW",
	319	"OR", /* 7807 */
	320	"ORA",
	321	"ORAW",
	322	"ORAX",
	323	"ORI",
	324	"ORIW",
	325	"OUT", /* 7801 */
	326	"PER", /* 7801 */
	327	"PEX", /* 7801 */
	328	"POP",
	329	"PUSH",
	330	"RET",
	331	"RETI",
	332	"RETS",
	333	"RLD",
	334	"RLL",
	335	"RLR",
	336	"RRD",
	337	"SBB",
	338	"SBBW",
	339	"SBBX",
	340	"SBCD",
	341	"SBI",
	342	"SDED",
	343	"SETB", /* 7807 */
	344	"SHLD",
	345	"SIO", /* 7801 */
	346	"SK",
	347	"SKIT",
	348	"SKN",
	349	"SKNIT",
	350	"SLL",
	351	"SLLC",
	352	"SLR",
	353	"SLRC",
	354	"SOFTI",
	355	"SSPD",
	356	"STAW",
	357	"STAX",
	358	"STC",
	359	"STEAX",
	360	"STM", /7801 /
	361	"STOP",
	362	"SUB",
	363	"SUBNB",
	364	"SUBNBW",
	365	"SUBNBX",
	366	"SUBW",
	367	"SUBX",
	368	"SUI",
	369	"SUINB",
	370	"TABLE",
	371	"XOR", /* 7807 */
	372	"XRA",
	373	"XRAW",
	374	"XRAX",
	375	"XRI"
	376	};
	377
	378
	379	/* prefix 48 */
	380	static const struct dasm_s dasm48_7810[256] =
	381	{
	382	{illegal,0 }, /* 00: 0100 1000 0000 0000 */
	383	{SLRC,"A" }, /* 01: 0100 1000 0000 0001 */
	384	{SLRC,"B" }, /* 02: 0100 1000 0000 0010 */
	385	{SLRC,"C" }, /* 03: 0100 1000 0000 0011 */
	386	{illegal,0 }, /* 04: 0100 1000 0000 0100 */
	387	{SLLC,"A" }, /* 05: 0100 1000 0000 0101 */
	388	{SLLC,"B" }, /* 06: 0100 1000 0000 0110 */
	389	{SLLC,"C" }, /* 07: 0100 1000 0000 0111 */
	390	{SK,"NV" }, /* 08: 0100 1000 0000 1000 */
	391	{illegal,0 }, /* 09: 0100 1000 0000 1001 */
	392	{SK,"CY" }, /* 0a: 0100 1000 0000 1010 */
	393	{SK,"HC" }, /* 0b: 0100 1000 0000 1011 */
	394	{SK,"Z" }, /* 0c: 0100 1000 0000 1100 */
	395	{illegal,0 }, /* 0d: 0100 1000 0000 1101 */
	396	{illegal,0 }, /* 0e: 0100 1000 0000 1110 */
	397	{illegal,0 }, /* 0f: 0100 1000 0000 1111 */
	398
	399	{illegal,0 }, /* 10: 0100 1000 0001 0000 */
	400	{illegal,0 }, /* 11: 0100 1000 0001 0001 */
	401	{illegal,0 }, /* 12: 0100 1000 0001 0010 */
	402	{illegal,0 }, /* 13: 0100 1000 0001 0011 */
	403	{illegal,0 }, /* 14: 0100 1000 0001 0100 */
	404	{illegal,0 }, /* 15: 0100 1000 0001 0101 */
	405	{illegal,0 }, /* 16: 0100 1000 0001 0110 */
	406	{illegal,0 }, /* 17: 0100 1000 0001 0111 */
	407	{SKN,"NV" }, /* 18: 0100 1000 0001 1000 */
	408	{illegal,0 }, /* 19: 0100 1000 0001 1001 */
	409	{SKN,"CY" }, /* 1a: 0100 1000 0001 1010 */
	410	{SKN,"HC" }, /* 1b: 0100 1000 0001 1011 */
	411	{SKN,"Z" }, /* 1c: 0100 1000 0001 1100 */
	412	{illegal,0 }, /* 1d: 0100 1000 0001 1101 */
	413	{illegal,0 }, /* 1e: 0100 1000 0001 1110 */
	414	{illegal,0 }, /* 1f: 0100 1000 0001 1111 */
	415
	416	{illegal,0 }, /* 20: 0100 1000 0010 0000 */
	417	{SLR,"A" }, /* 21: 0100 1000 0010 0001 */
	418	{SLR,"B" }, /* 22: 0100 1000 0010 0010 */
	419	{SLR,"C" }, /* 23: 0100 1000 0010 0011 */
	420	{illegal,0 }, /* 24: 0100 1000 0010 0100 */
	421	{SLL,"A" }, /* 25: 0100 1000 0010 0101 */
	422	{SLL,"B" }, /* 26: 0100 1000 0010 0110 */
	423	{SLL,"C" }, /* 27: 0100 1000 0010 0111 */
	424	{JEA,0 }, /* 28: 0100 1000 0010 1000 */
	425	{CALB,0 }, /* 29: 0100 1000 0010 1001 */
	426	{CLC,0 }, /* 2a: 0100 1000 0010 1010 */
	427	{STC,0 }, /* 2b: 0100 1000 0010 1011 */
	428	{illegal,0 }, /* 2c: 0100 1000 0010 1100 */
	429	{MUL,"A" }, /* 2d: 0100 1000 0010 1101 */
	430	{MUL,"B" }, /* 2e: 0100 1000 0010 1110 */
	431	{MUL,"C" }, /* 2f: 0100 1000 0010 1111 */
	432
	433	{illegal,0 }, /* 30: 0100 1000 0011 0000 */
	434	{RLR,"A" }, /* 31: 0100 1000 0011 0001 */
	435	{RLR,"B" }, /* 32: 0100 1000 0011 0010 */
	436	{RLR,"C" }, /* 33: 0100 1000 0011 0011 */
	437	{illegal,0 }, /* 34: 0100 1000 0011 0100 */
	438	{RLL,"A" }, /* 35: 0100 1000 0011 0101 */
	439	{RLL,"B" }, /* 36: 0100 1000 0011 0110 */
	440	{RLL,"C" }, /* 37: 0100 1000 0011 0111 */
	441	{RLD,0 }, /* 38: 0100 1000 0011 1000 */
	442	{RRD,0 }, /* 39: 0100 1000 0011 1001 */
	443	{NEGA,0 }, /* 3a: 0100 1000 0011 1010 */
	444	{HALT,0 }, /* 3b: 0100 1000 0011 1011 */
	445	{illegal,0 }, /* 3c: 0100 1000 0011 1100 */
	446	{DIV,"A" }, /* 3d: 0100 1000 0011 1101 */
	447	{DIV,"B" }, /* 3e: 0100 1000 0011 1110 */
	448	{DIV,"C" }, /* 3f: 0100 1000 0011 1111 */
	449
	450	{SKIT,"NMI" }, /* 40: 0100 1000 0100 0000 */
	451	{SKIT,"FT0" }, /* 41: 0100 1000 0100 0001 */
	452	{SKIT,"FT1" }, /* 42: 0100 1000 0100 0010 */
	453	{SKIT,"F1" }, /* 43: 0100 1000 0100 0011 */
	454	{SKIT,"F2" }, /* 44: 0100 1000 0100 0100 */
	455	{SKIT,"FE0" }, /* 45: 0100 1000 0100 0101 */
	456	{SKIT,"FE1" }, /* 46: 0100 1000 0100 0110 */
	457	{SKIT,"FEIN" }, /* 47: 0100 1000 0100 0111 */
	458	{SKIT,"FAD" }, /* 48: 0100 1000 0100 1000 */
	459	{SKIT,"FSR" }, /* 49: 0100 1000 0100 1001 */
	460	{SKIT,"FST" }, /* 4a: 0100 1000 0100 1010 */
	461	{SKIT,"ER" }, /* 4b: 0100 1000 0100 1011 */
	462	{SKIT,"OV" }, /* 4c: 0100 1000 0100 1100 */
	463	{illegal,0 }, /* 4d: 0100 1000 0100 1101 */
	464	{illegal,0 }, /* 4e: 0100 1000 0100 1110 */
	465	{illegal,0 }, /* 4f: 0100 1000 0100 1111 */
	466
	467	{SKIT,"AN4" }, /* 50: 0100 1000 0101 0000 */
	468	{SKIT,"AN5" }, /* 51: 0100 1000 0101 0001 */
	469	{SKIT,"AN6" }, /* 52: 0100 1000 0101 0010 */
	470	{SKIT,"AN7" }, /* 53: 0100 1000 0101 0011 */
	471	{SKIT,"SB" }, /* 54: 0100 1000 0101 0100 */
	472	{illegal,0 }, /* 55: 0100 1000 0101 0101 */
	473	{illegal,0 }, /* 56: 0100 1000 0101 0110 */
	474	{illegal,0 }, /* 57: 0100 1000 0101 0111 */
	475	{illegal,0 }, /* 58: 0100 1000 0101 1000 */
	476	{illegal,0 }, /* 59: 0100 1000 0101 1001 */
	477	{illegal,0 }, /* 5a: 0100 1000 0101 1010 */
	478	{illegal,0 }, /* 5b: 0100 1000 0101 1011 */
	479	{illegal,0 }, /* 5c: 0100 1000 0101 1100 */
	480	{illegal,0 }, /* 5d: 0100 1000 0101 1101 */
	481	{illegal,0 }, /* 5e: 0100 1000 0101 1110 */
	482	{illegal,0 }, /* 5f: 0100 1000 0101 1111 */
	483
	484	{SKNIT,"NMI" }, /* 60: 0100 1000 0110 0000 */
	485	{SKNIT,"FT0" }, /* 61: 0100 1000 0110 0001 */
	486	{SKNIT,"FT1" }, /* 62: 0100 1000 0110 0010 */
	487	{SKNIT,"F1" }, /* 63: 0100 1000 0110 0011 */
	488	{SKNIT,"F2" }, /* 64: 0100 1000 0110 0100 */
	489	{SKNIT,"FE0" }, /* 65: 0100 1000 0110 0101 */
	490	{SKNIT,"FE1" }, /* 66: 0100 1000 0110 0110 */
	491	{SKNIT,"FEIN" }, /* 67: 0100 1000 0110 0111 */
	492	{SKNIT,"FAD" }, /* 68: 0100 1000 0110 1000 */
	493	{SKNIT,"FSR" }, /* 69: 0100 1000 0110 1001 */
	494	{SKNIT,"FST" }, /* 6a: 0100 1000 0110 1010 */
	495	{SKNIT,"ER" }, /* 6b: 0100 1000 0110 1011 */
	496	{SKNIT,"OV" }, /* 6c: 0100 1000 0110 1100 */
	497	{illegal,0 }, /* 6d: 0100 1000 0110 1101 */
	498	{illegal,0 }, /* 6e: 0100 1000 0110 1110 */
	499	{illegal,0 }, /* 6f: 0100 1000 0110 1111 */
	500
	501	{SKNIT,"AN4" }, /* 70: 0100 1000 0111 0000 */
	502	{SKNIT,"AN5" }, /* 71: 0100 1000 0111 0001 */
	503	{SKNIT,"AN6" }, /* 72: 0100 1000 0111 0010 */
	504	{SKNIT,"AN7" }, /* 73: 0100 1000 0111 0011 */
	505	{SKNIT,"SB" }, /* 74: 0100 1000 0111 0100 */
	506	{illegal,0 }, /* 75: 0100 1000 0111 0101 */
	507	{illegal,0 }, /* 76: 0100 1000 0111 0110 */
	508	{illegal,0 }, /* 77: 0100 1000 0111 0111 */
	509	{illegal,0 }, /* 78: 0100 1000 0111 1000 */
	510	{illegal,0 }, /* 79: 0100 1000 0111 1001 */
	511	{illegal,0 }, /* 7a: 0100 1000 0111 1010 */
	512	{illegal,0 }, /* 7b: 0100 1000 0111 1011 */
	513	{illegal,0 }, /* 7c: 0100 1000 0111 1100 */
	514	{illegal,0 }, /* 7d: 0100 1000 0111 1101 */
	515	{illegal,0 }, /* 7e: 0100 1000 0111 1110 */
	516	{illegal,0 }, /* 7f: 0100 1000 0111 1111 */
	517
	518	{illegal,0 }, /* 80: 0100 1000 1000 0000 */
	519	{illegal,0 }, /* 81: 0100 1000 1000 0001 */
	520	{LDEAX,"(DE)" }, /* 82: 0100 1000 1000 0010 */
	521	{LDEAX,"(HL)" }, /* 83: 0100 1000 1000 0011 */
	522	{LDEAX,"(DE++)" }, /* 84: 0100 1000 1000 0100 */
	523	{LDEAX,"(HL++)" }, /* 85: 0100 1000 1000 0101 */
	524	{illegal,0 }, /* 86: 0100 1000 1000 0110 */
	525	{illegal,0 }, /* 87: 0100 1000 1000 0111 */
	526	{illegal,0 }, /* 88: 0100 1000 1000 1000 */
	527	{illegal,0 }, /* 89: 0100 1000 1000 1001 */
	528	{illegal,0 }, /* 8a: 0100 1000 1000 1010 */
	529	{LDEAX,"(DE+%b)"}, /* 8b: 0100 1000 1000 1011 xxxx xxxx */
	530	{LDEAX,"(HL+A)" }, /* 8c: 0100 1000 1000 1100 */
	531	{LDEAX,"(HL+B)" }, /* 8d: 0100 1000 1000 1101 */
	532	{LDEAX,"(HL+EA)"}, /* 8e: 0100 1000 1000 1110 */
	533	{LDEAX,"(HL+%b)"}, /* 8f: 0100 1000 1000 1111 xxxx xxxx */
	534
	535	{illegal,0 }, /* 90: 0100 1000 1000 0000 */
	536	{illegal,0 }, /* 91: 0100 1000 1000 0001 */
	537	{STEAX,"(DE)" }, /* 92: 0100 1000 1000 0010 */
	538	{STEAX,"(HL)" }, /* 93: 0100 1000 1000 0011 */
	539	{STEAX,"(DE++)" }, /* 94: 0100 1000 1000 0100 */
	540	{STEAX,"(HL++)" }, /* 95: 0100 1000 1000 0101 */
	541	{illegal,0 }, /* 96: 0100 1000 1000 0110 */
	542	{illegal,0 }, /* 97: 0100 1000 1000 0111 */
	543	{illegal,0 }, /* 98: 0100 1000 1000 1000 */
	544	{illegal,0 }, /* 99: 0100 1000 1000 1001 */
	545	{illegal,0 }, /* 9a: 0100 1000 1000 1010 */
	546	{STEAX,"(DE+%b)"}, /* 9b: 0100 1000 1000 1011 xxxx xxxx */
	547	{STEAX,"(HL+A)" }, /* 9c: 0100 1000 1000 1100 */
	548	{STEAX,"(HL+B)" }, /* 9d: 0100 1000 1000 1101 */
	549	{STEAX,"(HL+EA)"}, /* 9e: 0100 1000 1000 1110 */
	550	{STEAX,"(HL+%b)"}, /* 9f: 0100 1000 1000 1111 xxxx xxxx */
	551
	552	{DSLR,"EA" }, /* a0: 0100 1000 1010 0000 */
	553	{illegal,0 }, /* a1: 0100 1000 1010 0001 */
	554	{illegal,0 }, /* a2: 0100 1000 1010 0010 */
	555	{illegal,0 }, /* a3: 0100 1000 1010 0011 */
	556	{DSLL,"EA" }, /* a4: 0100 1000 1010 0100 */
	557	{illegal,0 }, /* a5: 0100 1000 1010 0101 */
	558	{illegal,0 }, /* a6: 0100 1000 1010 0110 */
	559	{illegal,0 }, /* a7: 0100 1000 1010 0111 */
	560	{TABLE,0 }, /* a8: 0100 1000 1010 1000 */
	561	{illegal,0 }, /* a9: 0100 1000 1010 1001 */
	562	{illegal,0 }, /* aa: 0100 1000 1010 1010 */
	563	{illegal,0 }, /* ab: 0100 1000 1010 1011 */
	564	{illegal,0 }, /* ac: 0100 1000 1010 1100 */
	565	{illegal,0 }, /* ad: 0100 1000 1010 1101 */
	566	{illegal,0 }, /* ae: 0100 1000 1010 1110 */
	567	{illegal,0 }, /* af: 0100 1000 1010 1111 */
	568
	569	{DRLR,"EA" }, /* b0: 0100 1000 1011 0000 */
	570	{illegal,0 }, /* b1: 0100 1000 1011 0001 */
	571	{illegal,0 }, /* b2: 0100 1000 1011 0010 */
	572	{illegal,0 }, /* b3: 0100 1000 1011 0011 */
	573	{DRLL,"EA" }, /* b4: 0100 1000 1011 0100 */
	574	{illegal,0 }, /* b5: 0100 1000 1011 0101 */
	575	{illegal,0 }, /* b6: 0100 1000 1011 0110 */
	576	{illegal,0 }, /* b7: 0100 1000 1011 0111 */
	577	{illegal,0 }, /* b8: 0100 1000 1011 1000 */
	578	{illegal,0 }, /* b9: 0100 1000 1011 1001 */
	579	{illegal,0 }, /* ba: 0100 1000 1011 1010 */
	580	{STOP,0 }, /* bb: 0100 1000 1011 1011 / / 7810 */
	581	{illegal,0 }, /* bc: 0100 1000 1011 1100 */
	582	{illegal,0 }, /* bd: 0100 1000 1011 1101 */
	583	{illegal,0 }, /* be: 0100 1000 1011 1110 */
	584	{illegal,0 }, /* bf: 0100 1000 1011 1111 */
	585
	586	{DMOV,"EA,ECNT" }, /* c0: 0100 1000 1100 0000 */
	587	{DMOV,"EA,ECPT" }, /* c1: 0100 1000 1100 0001 / / 7810 */
	588	{illegal,0 }, /* c2: 0100 1000 1100 0010 */
	589	{illegal,0 }, /* c3: 0100 1000 1100 0011 */
	590	{illegal,0 }, /* c4: 0100 1000 1100 0100 */
	591	{illegal,0 }, /* c5: 0100 1000 1100 0101 */
	592	{illegal,0 }, /* c6: 0100 1000 1100 0110 */
	593	{illegal,0 }, /* c7: 0100 1000 1100 0111 */
	594	{illegal,0 }, /* c8: 0100 1000 1100 1000 */
	595	{illegal,0 }, /* c9: 0100 1000 1100 1001 */
	596	{illegal,0 }, /* ca: 0100 1000 1100 1010 */
	597	{illegal,0 }, /* cb: 0100 1000 1100 1011 */
	598	{illegal,0 }, /* cc: 0100 1000 1100 1100 */
	599	{illegal,0 }, /* cd: 0100 1000 1100 1101 */
	600	{illegal,0 }, /* ce: 0100 1000 1100 1110 */
	601	{illegal,0 }, /* cf: 0100 1000 1100 1111 */
	602
	603	{illegal,0 }, /* d0: 0100 1000 1101 0000 */
	604	{illegal,0 }, /* d1: 0100 1000 1101 0001 */
	605	{DMOV,"ETM0,EA" }, /* d2: 0100 1000 1101 0010 */
	606	{DMOV,"ETM1,EA" }, /* d3: 0100 1000 1101 0011 */
	607	{illegal,0 }, /* d4: 0100 1000 1101 0100 */
	608	{illegal,0 }, /* d5: 0100 1000 1101 0101 */
	609	{illegal,0 }, /* d6: 0100 1000 1101 0110 */
	610	{illegal,0 }, /* d7: 0100 1000 1101 0111 */
	611	{illegal,0 }, /* d8: 0100 1000 1101 1000 */
	612	{illegal,0 }, /* d9: 0100 1000 1101 1001 */
	613	{illegal,0 }, /* da: 0100 1000 1101 1010 */
	614	{illegal,0 }, /* db: 0100 1000 1101 1011 */
	615	{illegal,0 }, /* dc: 0100 1000 1101 1100 */
	616	{illegal,0 }, /* dd: 0100 1000 1101 1101 */
	617	{illegal,0 }, /* de: 0100 1000 1101 1110 */
	618	{illegal,0 }, /* df: 0100 1000 1101 1111 */
	619
	620	{illegal,0 }, /* e0: 0100 1000 1110 0000 */
	621	{illegal,0 }, /* e1: 0100 1000 1110 0001 */
	622	{illegal,0 }, /* e2: 0100 1000 1110 0010 */
	623	{illegal,0 }, /* e3: 0100 1000 1110 0011 */
	624	{illegal,0 }, /* e4: 0100 1000 1110 0100 */
	625	{illegal,0 }, /* e5: 0100 1000 1110 0101 */
	626	{illegal,0 }, /* e6: 0100 1000 1110 0110 */
	627	{illegal,0 }, /* e7: 0100 1000 1110 0111 */
	628	{illegal,0 }, /* e8: 0100 1000 1110 1000 */
	629	{illegal,0 }, /* e9: 0100 1000 1110 1001 */
	630	{illegal,0 }, /* ea: 0100 1000 1110 1010 */
	631	{illegal,0 }, /* eb: 0100 1000 1110 1011 */
	632	{illegal,0 }, /* ec: 0100 1000 1110 1100 */
	633	{illegal,0 }, /* ed: 0100 1000 1110 1101 */
	634	{illegal,0 }, /* ee: 0100 1000 1110 1110 */
	635	{illegal,0 }, /* ef: 0100 1000 1110 1111 */
	636
	637	{illegal,0 }, /* f0: 0100 1000 1111 0000 */
	638	{illegal,0 }, /* f1: 0100 1000 1111 0001 */
	639	{illegal,0 }, /* f2: 0100 1000 1111 0010 */
	640	{illegal,0 }, /* f3: 0100 1000 1111 0011 */
	641	{illegal,0 }, /* f4: 0100 1000 1111 0100 */
	642	{illegal,0 }, /* f5: 0100 1000 1111 0101 */
	643	{illegal,0 }, /* f6: 0100 1000 1111 0110 */
	644	{illegal,0 }, /* f7: 0100 1000 1111 0111 */
	645	{illegal,0 }, /* f8: 0100 1000 1111 1000 */
	646	{illegal,0 }, /* f9: 0100 1000 1111 1001 */
	647	{illegal,0 }, /* fa: 0100 1000 1111 1010 */
	648	{illegal,0 }, /* fb: 0100 1000 1111 1011 */
	649	{illegal,0 }, /* fc: 0100 1000 1111 1100 */
	650	{illegal,0 }, /* fd: 0100 1000 1111 1101 */
	651	{illegal,0 }, /* fe: 0100 1000 1111 1110 */
	652	{illegal,0 } /* ff: 0100 1000 1111 1111 */
	653	};
	654
	655	static const struct dasm_s dasm48_7807[256] =
	656	{
	657	{illegal,0 }, /* 00: 0100 1000 0000 0000 */
	658	{SLRC,"A" }, /* 01: 0100 1000 0000 0001 */
	659	{SLRC,"B" }, /* 02: 0100 1000 0000 0010 */
	660	{SLRC,"C" }, /* 03: 0100 1000 0000 0011 */
	661	{illegal,0 }, /* 04: 0100 1000 0000 0100 */
	662	{SLLC,"A" }, /* 05: 0100 1000 0000 0101 */
	663	{SLLC,"B" }, /* 06: 0100 1000 0000 0110 */
	664	{SLLC,"C" }, /* 07: 0100 1000 0000 0111 */
	665	{SK,"NV" }, /* 08: 0100 1000 0000 1000 */
	666	{illegal,0 }, /* 09: 0100 1000 0000 1001 */
	667	{SK,"CY" }, /* 0a: 0100 1000 0000 1010 */
	668	{SK,"HC" }, /* 0b: 0100 1000 0000 1011 */
	669	{SK,"Z" }, /* 0c: 0100 1000 0000 1100 */
	670	{illegal,0 }, /* 0d: 0100 1000 0000 1101 */
	671	{illegal,0 }, /* 0e: 0100 1000 0000 1110 */
	672	{illegal,0 }, /* 0f: 0100 1000 0000 1111 */
	673
	674	{illegal,0 }, /* 10: 0100 1000 0001 0000 */
	675	{illegal,0 }, /* 11: 0100 1000 0001 0001 */
	676	{illegal,0 }, /* 12: 0100 1000 0001 0010 */
	677	{illegal,0 }, /* 13: 0100 1000 0001 0011 */
	678	{illegal,0 }, /* 14: 0100 1000 0001 0100 */
	679	{illegal,0 }, /* 15: 0100 1000 0001 0101 */
	680	{illegal,0 }, /* 16: 0100 1000 0001 0110 */
	681	{illegal,0 }, /* 17: 0100 1000 0001 0111 */
	682	{SKN,"NV" }, /* 18: 0100 1000 0001 1000 */
	683	{illegal,0 }, /* 19: 0100 1000 0001 1001 */
	684	{SKN,"CY" }, /* 1a: 0100 1000 0001 1010 */
	685	{SKN,"HC" }, /* 1b: 0100 1000 0001 1011 */
	686	{SKN,"Z" }, /* 1c: 0100 1000 0001 1100 */
	687	{illegal,0 }, /* 1d: 0100 1000 0001 1101 */
	688	{illegal,0 }, /* 1e: 0100 1000 0001 1110 */
	689	{illegal,0 }, /* 1f: 0100 1000 0001 1111 */
	690
	691	{illegal,0 }, /* 20: 0100 1000 0010 0000 */
	692	{SLR,"A" }, /* 21: 0100 1000 0010 0001 */
	693	{SLR,"B" }, /* 22: 0100 1000 0010 0010 */
	694	{SLR,"C" }, /* 23: 0100 1000 0010 0011 */
	695	{illegal,0 }, /* 24: 0100 1000 0010 0100 */
	696	{SLL,"A" }, /* 25: 0100 1000 0010 0101 */
	697	{SLL,"B" }, /* 26: 0100 1000 0010 0110 */
	698	{SLL,"C" }, /* 27: 0100 1000 0010 0111 */
	699	{JEA,0 }, /* 28: 0100 1000 0010 1000 */
	700	{CALB,0 }, /* 29: 0100 1000 0010 1001 */
	701	{CLC,0 }, /* 2a: 0100 1000 0010 1010 */
	702	{STC,0 }, /* 2b: 0100 1000 0010 1011 */
	703	{illegal,0 }, /* 2c: 0100 1000 0010 1100 */
	704	{MUL,"A" }, /* 2d: 0100 1000 0010 1101 */
	705	{MUL,"B" }, /* 2e: 0100 1000 0010 1110 */
	706	{MUL,"C" }, /* 2f: 0100 1000 0010 1111 */
	707
	708	{illegal,0 }, /* 30: 0100 1000 0011 0000 */
	709	{RLR,"A" }, /* 31: 0100 1000 0011 0001 */
	710	{RLR,"B" }, /* 32: 0100 1000 0011 0010 */
	711	{RLR,"C" }, /* 33: 0100 1000 0011 0011 */
	712	{illegal,0 }, /* 34: 0100 1000 0011 0100 */
	713	{RLL,"A" }, /* 35: 0100 1000 0011 0101 */
	714	{RLL,"B" }, /* 36: 0100 1000 0011 0110 */
	715	{RLL,"C" }, /* 37: 0100 1000 0011 0111 */
	716	{RLD,0 }, /* 38: 0100 1000 0011 1000 */
	717	{RRD,0 }, /* 39: 0100 1000 0011 1001 */
	718	{NEGA,0 }, /* 3a: 0100 1000 0011 1010 */
	719	{HALT,0 }, /* 3b: 0100 1000 0011 1011 */
	720	{illegal,0 }, /* 3c: 0100 1000 0011 1100 */
	721	{DIV,"A" }, /* 3d: 0100 1000 0011 1101 */
	722	{DIV,"B" }, /* 3e: 0100 1000 0011 1110 */
	723	{DIV,"C" }, /* 3f: 0100 1000 0011 1111 */
	724
	725	{SKIT,"NMI" }, /* 40: 0100 1000 0100 0000 */
	726	{SKIT,"FT0" }, /* 41: 0100 1000 0100 0001 */
	727	{SKIT,"FT1" }, /* 42: 0100 1000 0100 0010 */
	728	{SKIT,"F1" }, /* 43: 0100 1000 0100 0011 */
	729	{SKIT,"F2" }, /* 44: 0100 1000 0100 0100 */
	730	{SKIT,"FE0" }, /* 45: 0100 1000 0100 0101 */
	731	{SKIT,"FE1" }, /* 46: 0100 1000 0100 0110 */
	732	{SKIT,"FEIN" }, /* 47: 0100 1000 0100 0111 */
	733	{SKIT,"FAD" }, /* 48: 0100 1000 0100 1000 */
	734	{SKIT,"FSR" }, /* 49: 0100 1000 0100 1001 */
	735	{SKIT,"FST" }, /* 4a: 0100 1000 0100 1010 */
	736	{SKIT,"ER" }, /* 4b: 0100 1000 0100 1011 */
	737	{SKIT,"OV" }, /* 4c: 0100 1000 0100 1100 */
	738	{illegal,0 }, /* 4d: 0100 1000 0100 1101 */
	739	{illegal,0 }, /* 4e: 0100 1000 0100 1110 */
	740	{illegal,0 }, /* 4f: 0100 1000 0100 1111 */
	741
	742	{SKIT,"AN4" }, /* 50: 0100 1000 0101 0000 */
	743	{SKIT,"AN5" }, /* 51: 0100 1000 0101 0001 */
	744	{SKIT,"AN6" }, /* 52: 0100 1000 0101 0010 */
	745	{SKIT,"AN7" }, /* 53: 0100 1000 0101 0011 */
	746	{SKIT,"SB" }, /* 54: 0100 1000 0101 0100 */
	747	{illegal,0 }, /* 55: 0100 1000 0101 0101 */
	748	{illegal,0 }, /* 56: 0100 1000 0101 0110 */
	749	{illegal,0 }, /* 57: 0100 1000 0101 0111 */
	750	{illegal,0 }, /* 58: 0100 1000 0101 1000 */
	751	{illegal,0 }, /* 59: 0100 1000 0101 1001 */
	752	{illegal,0 }, /* 5a: 0100 1000 0101 1010 */
	753	{illegal,0 }, /* 5b: 0100 1000 0101 1011 */
	754	{illegal,0 }, /* 5c: 0100 1000 0101 1100 */
	755	{illegal,0 }, /* 5d: 0100 1000 0101 1101 */
	756	{illegal,0 }, /* 5e: 0100 1000 0101 1110 */
	757	{illegal,0 }, /* 5f: 0100 1000 0101 1111 */
	758
	759	{SKNIT,"NMI" }, /* 60: 0100 1000 0110 0000 */
	760	{SKNIT,"FT0" }, /* 61: 0100 1000 0110 0001 */
	761	{SKNIT,"FT1" }, /* 62: 0100 1000 0110 0010 */
	762	{SKNIT,"F1" }, /* 63: 0100 1000 0110 0011 */
	763	{SKNIT,"F2" }, /* 64: 0100 1000 0110 0100 */
	764	{SKNIT,"FE0" }, /* 65: 0100 1000 0110 0101 */
	765	{SKNIT,"FE1" }, /* 66: 0100 1000 0110 0110 */
	766	{SKNIT,"FEIN" }, /* 67: 0100 1000 0110 0111 */
	767	{SKNIT,"FAD" }, /* 68: 0100 1000 0110 1000 */
	768	{SKNIT,"FSR" }, /* 69: 0100 1000 0110 1001 */
	769	{SKNIT,"FST" }, /* 6a: 0100 1000 0110 1010 */
	770	{SKNIT,"ER" }, /* 6b: 0100 1000 0110 1011 */
	771	{SKNIT,"OV" }, /* 6c: 0100 1000 0110 1100 */
	772	{illegal,0 }, /* 6d: 0100 1000 0110 1101 */
	773	{illegal,0 }, /* 6e: 0100 1000 0110 1110 */
	774	{illegal,0 }, /* 6f: 0100 1000 0110 1111 */
	775
	776	{SKNIT,"AN4" }, /* 70: 0100 1000 0111 0000 */
	777	{SKNIT,"AN5" }, /* 71: 0100 1000 0111 0001 */
	778	{SKNIT,"AN6" }, /* 72: 0100 1000 0111 0010 */
	779	{SKNIT,"AN7" }, /* 73: 0100 1000 0111 0011 */
	780	{SKNIT,"SB" }, /* 74: 0100 1000 0111 0100 */
	781	{illegal,0 }, /* 75: 0100 1000 0111 0101 */
	782	{illegal,0 }, /* 76: 0100 1000 0111 0110 */
	783	{illegal,0 }, /* 77: 0100 1000 0111 0111 */
	784	{illegal,0 }, /* 78: 0100 1000 0111 1000 */
	785	{illegal,0 }, /* 79: 0100 1000 0111 1001 */
	786	{illegal,0 }, /* 7a: 0100 1000 0111 1010 */
	787	{illegal,0 }, /* 7b: 0100 1000 0111 1011 */
	788	{illegal,0 }, /* 7c: 0100 1000 0111 1100 */
	789	{illegal,0 }, /* 7d: 0100 1000 0111 1101 */
	790	{illegal,0 }, /* 7e: 0100 1000 0111 1110 */
	791	{illegal,0 }, /* 7f: 0100 1000 0111 1111 */
	792
	793	{illegal,0 }, /* 80: 0100 1000 1000 0000 */
	794	{illegal,0 }, /* 81: 0100 1000 1000 0001 */
	795	{LDEAX,"(DE)" }, /* 82: 0100 1000 1000 0010 */
	796	{LDEAX,"(HL)" }, /* 83: 0100 1000 1000 0011 */
	797	{LDEAX,"(DE++)" }, /* 84: 0100 1000 1000 0100 */
	798	{LDEAX,"(HL++)" }, /* 85: 0100 1000 1000 0101 */
	799	{illegal,0 }, /* 86: 0100 1000 1000 0110 */
	800	{illegal,0 }, /* 87: 0100 1000 1000 0111 */
	801	{illegal,0 }, /* 88: 0100 1000 1000 1000 */
	802	{illegal,0 }, /* 89: 0100 1000 1000 1001 */
	803	{illegal,0 }, /* 8a: 0100 1000 1000 1010 */
	804	{LDEAX,"(DE+%b)"}, /* 8b: 0100 1000 1000 1011 xxxx xxxx */
	805	{LDEAX,"(HL+A)" }, /* 8c: 0100 1000 1000 1100 */
	806	{LDEAX,"(HL+B)" }, /* 8d: 0100 1000 1000 1101 */
	807	{LDEAX,"(HL+EA)"}, /* 8e: 0100 1000 1000 1110 */
	808	{LDEAX,"(HL+%b)"}, /* 8f: 0100 1000 1000 1111 xxxx xxxx */
	809
	810	{illegal,0 }, /* 90: 0100 1000 1000 0000 */
	811	{illegal,0 }, /* 91: 0100 1000 1000 0001 */
	812	{STEAX,"(DE)" }, /* 92: 0100 1000 1000 0010 */
	813	{STEAX,"(HL)" }, /* 93: 0100 1000 1000 0011 */
	814	{STEAX,"(DE++)" }, /* 94: 0100 1000 1000 0100 */
	815	{STEAX,"(HL++)" }, /* 95: 0100 1000 1000 0101 */
	816	{illegal,0 }, /* 96: 0100 1000 1000 0110 */
	817	{illegal,0 }, /* 97: 0100 1000 1000 0111 */
	818	{illegal,0 }, /* 98: 0100 1000 1000 1000 */
	819	{illegal,0 }, /* 99: 0100 1000 1000 1001 */
	820	{illegal,0 }, /* 9a: 0100 1000 1000 1010 */
	821	{STEAX,"(DE+%b)"}, /* 9b: 0100 1000 1000 1011 xxxx xxxx */
	822	{STEAX,"(HL+A)" }, /* 9c: 0100 1000 1000 1100 */
	823	{STEAX,"(HL+B)" }, /* 9d: 0100 1000 1000 1101 */
	824	{STEAX,"(HL+EA)"}, /* 9e: 0100 1000 1000 1110 */
	825	{STEAX,"(HL+%b)"}, /* 9f: 0100 1000 1000 1111 xxxx xxxx */
	826
	827	{DSLR,"EA" }, /* a0: 0100 1000 1010 0000 */
	828	{illegal,0 }, /* a1: 0100 1000 1010 0001 */
	829	{illegal,0 }, /* a2: 0100 1000 1010 0010 */
	830	{illegal,0 }, /* a3: 0100 1000 1010 0011 */
	831	{DSLL,"EA" }, /* a4: 0100 1000 1010 0100 */
	832	{illegal,0 }, /* a5: 0100 1000 1010 0101 */
	833	{illegal,0 }, /* a6: 0100 1000 1010 0110 */
	834	{illegal,0 }, /* a7: 0100 1000 1010 0111 */
	835	{TABLE,0 }, /* a8: 0100 1000 1010 1000 */
	836	{illegal,0 }, /* a9: 0100 1000 1010 1001 */
	837	{CMC,0 }, /* aa: 0100 1000 1010 1010 / / 7807 */
	838	{illegal,0 }, /* ab: 0100 1000 1010 1011 */
	839	{EXA,0 }, /* ac: 0100 1000 1010 1100 / / 7807 */
	840	{EXR,0 }, /* ad: 0100 1000 1010 1101 / / 7807 */
	841	{EXH,0 }, /* ae: 0100 1000 1010 1110 / / 7807 */
	842	{EXX,0 }, /* af: 0100 1000 1010 1111 / / 7807 */
	843
	844	{DRLR,"EA" }, /* b0: 0100 1000 1011 0000 */
	845	{illegal,0 }, /* b1: 0100 1000 1011 0001 */
	846	{illegal,0 }, /* b2: 0100 1000 1011 0010 */
	847	{illegal,0 }, /* b3: 0100 1000 1011 0011 */
	848	{DRLL,"EA" }, /* b4: 0100 1000 1011 0100 */
	849	{illegal,0 }, /* b5: 0100 1000 1011 0101 */
	850	{illegal,0 }, /* b6: 0100 1000 1011 0110 */
	851	{illegal,0 }, /* b7: 0100 1000 1011 0111 */
	852	{illegal,0 }, /* b8: 0100 1000 1011 1000 */
	853	{illegal,0 }, /* b9: 0100 1000 1011 1001 */
	854	{illegal,0 }, /* ba: 0100 1000 1011 1010 */
	855	{illegal,0 }, /* bb: 0100 1000 1011 1011 */
	856	{illegal,0 }, /* bc: 0100 1000 1011 1100 */
	857	{illegal,0 }, /* bd: 0100 1000 1011 1101 */
	858	{illegal,0 }, /* be: 0100 1000 1011 1110 */
	859	{illegal,0 }, /* bf: 0100 1000 1011 1111 */
	860
	861	{DMOV,"EA,ECNT" }, /* c0: 0100 1000 1100 0000 */
	862	{DMOV,"EA,ECPT0"}, /* c1: 0100 1000 1100 0001 / / 7807 */
	863	{DMOV,"EA,ECPT1"}, /* c2: 0100 1000 1100 0010 / / 7807 */
	864	{illegal,0 }, /* c3: 0100 1000 1100 0011 */
	865	{illegal,0 }, /* c4: 0100 1000 1100 0100 */
	866	{illegal,0 }, /* c5: 0100 1000 1100 0101 */
	867	{illegal,0 }, /* c6: 0100 1000 1100 0110 */
	868	{illegal,0 }, /* c7: 0100 1000 1100 0111 */
	869	{illegal,0 }, /* c8: 0100 1000 1100 1000 */
	870	{illegal,0 }, /* c9: 0100 1000 1100 1001 */
	871	{illegal,0 }, /* ca: 0100 1000 1100 1010 */
	872	{illegal,0 }, /* cb: 0100 1000 1100 1011 */
	873	{illegal,0 }, /* cc: 0100 1000 1100 1100 */
	874	{illegal,0 }, /* cd: 0100 1000 1100 1101 */
	875	{illegal,0 }, /* ce: 0100 1000 1100 1110 */
	876	{illegal,0 }, /* cf: 0100 1000 1100 1111 */
	877
	878	{illegal,0 }, /* d0: 0100 1000 1101 0000 */
	879	{illegal,0 }, /* d1: 0100 1000 1101 0001 */
	880	{DMOV,"ETM0,EA" }, /* d2: 0100 1000 1101 0010 */
	881	{DMOV,"ETM1,EA" }, /* d3: 0100 1000 1101 0011 */
	882	{illegal,0 }, /* d4: 0100 1000 1101 0100 */
	883	{illegal,0 }, /* d5: 0100 1000 1101 0101 */
	884	{illegal,0 }, /* d6: 0100 1000 1101 0110 */
	885	{illegal,0 }, /* d7: 0100 1000 1101 0111 */
	886	{illegal,0 }, /* d8: 0100 1000 1101 1000 */
	887	{illegal,0 }, /* d9: 0100 1000 1101 1001 */
	888	{illegal,0 }, /* da: 0100 1000 1101 1010 */
	889	{illegal,0 }, /* db: 0100 1000 1101 1011 */
	890	{illegal,0 }, /* dc: 0100 1000 1101 1100 */
	891	{illegal,0 }, /* dd: 0100 1000 1101 1101 */
	892	{illegal,0 }, /* de: 0100 1000 1101 1110 */
	893	{illegal,0 }, /* df: 0100 1000 1101 1111 */
	894
	895	{illegal,0 }, /* e0: 0100 1000 1110 0000 */
	896	{illegal,0 }, /* e1: 0100 1000 1110 0001 */
	897	{illegal,0 }, /* e2: 0100 1000 1110 0010 */
	898	{illegal,0 }, /* e3: 0100 1000 1110 0011 */
	899	{illegal,0 }, /* e4: 0100 1000 1110 0100 */
	900	{illegal,0 }, /* e5: 0100 1000 1110 0101 */
	901	{illegal,0 }, /* e6: 0100 1000 1110 0110 */
	902	{illegal,0 }, /* e7: 0100 1000 1110 0111 */
	903	{illegal,0 }, /* e8: 0100 1000 1110 1000 */
	904	{illegal,0 }, /* e9: 0100 1000 1110 1001 */
	905	{illegal,0 }, /* ea: 0100 1000 1110 1010 */
	906	{illegal,0 }, /* eb: 0100 1000 1110 1011 */
	907	{illegal,0 }, /* ec: 0100 1000 1110 1100 */
	908	{illegal,0 }, /* ed: 0100 1000 1110 1101 */
	909	{illegal,0 }, /* ee: 0100 1000 1110 1110 */
	910	{illegal,0 }, /* ef: 0100 1000 1110 1111 */
	911
	912	{illegal,0 }, /* f0: 0100 1000 1111 0000 */
	913	{illegal,0 }, /* f1: 0100 1000 1111 0001 */
	914	{illegal,0 }, /* f2: 0100 1000 1111 0010 */
	915	{illegal,0 }, /* f3: 0100 1000 1111 0011 */
	916	{illegal,0 }, /* f4: 0100 1000 1111 0100 */
	917	{illegal,0 }, /* f5: 0100 1000 1111 0101 */
	918	{illegal,0 }, /* f6: 0100 1000 1111 0110 */
	919	{illegal,0 }, /* f7: 0100 1000 1111 0111 */
	920	{illegal,0 }, /* f8: 0100 1000 1111 1000 */
	921	{illegal,0 }, /* f9: 0100 1000 1111 1001 */
	922	{illegal,0 }, /* fa: 0100 1000 1111 1010 */
	923	{illegal,0 }, /* fb: 0100 1000 1111 1011 */
	924	{illegal,0 }, /* fc: 0100 1000 1111 1100 */
	925	{illegal,0 }, /* fd: 0100 1000 1111 1101 */
	926	{illegal,0 }, /* fe: 0100 1000 1111 1110 */
	927	{illegal,0 } /* ff: 0100 1000 1111 1111 */
	928	};
	929
	930	/* prefix 4C */
	931	static const struct dasm_s dasm4C_7810[256] =
	932	{
	933	{illegal,0 }, /* 00: 0100 1100 0000 0000 */
	934	{illegal,0 }, /* 01: 0100 1100 0000 0001 */
	935	{illegal,0 }, /* 02: 0100 1100 0000 0010 */
	936	{illegal,0 }, /* 03: 0100 1100 0000 0011 */
	937	{illegal,0 }, /* 04: 0100 1100 0000 0100 */
	938	{illegal,0 }, /* 05: 0100 1100 0000 0101 */
	939	{illegal,0 }, /* 06: 0100 1100 0000 0110 */
	940	{illegal,0 }, /* 07: 0100 1100 0000 0111 */
	941	{illegal,0 }, /* 08: 0100 1100 0000 1000 */
	942	{illegal,0 }, /* 09: 0100 1100 0000 1001 */
	943	{illegal,0 }, /* 0a: 0100 1100 0000 1010 */
	944	{illegal,0 }, /* 0b: 0100 1100 0000 1011 */
	945	{illegal,0 }, /* 0c: 0100 1100 0000 1100 */
	946	{illegal,0 }, /* 0d: 0100 1100 0000 1101 */
	947	{illegal,0 }, /* 0e: 0100 1100 0000 1110 */
	948	{illegal,0 }, /* 0f: 0100 1100 0000 1111 */
	949
	950	{illegal,0 }, /* 10: 0100 1100 0001 0000 */
	951	{illegal,0 }, /* 11: 0100 1100 0001 0001 */
	952	{illegal,0 }, /* 12: 0100 1100 0001 0010 */
	953	{illegal,0 }, /* 13: 0100 1100 0001 0011 */
	954	{illegal,0 }, /* 14: 0100 1100 0001 0100 */
	955	{illegal,0 }, /* 15: 0100 1100 0001 0101 */
	956	{illegal,0 }, /* 16: 0100 1100 0001 0110 */
	957	{illegal,0 }, /* 17: 0100 1100 0001 0111 */
	958	{illegal,0 }, /* 18: 0100 1100 0001 1000 */
	959	{illegal,0 }, /* 19: 0100 1100 0001 1001 */
	960	{illegal,0 }, /* 1a: 0100 1100 0001 1010 */
	961	{illegal,0 }, /* 1b: 0100 1100 0001 1011 */
	962	{illegal,0 }, /* 1c: 0100 1100 0001 1100 */
	963	{illegal,0 }, /* 1d: 0100 1100 0001 1101 */
	964	{illegal,0 }, /* 1e: 0100 1100 0001 1110 */
	965	{illegal,0 }, /* 1f: 0100 1100 0001 1111 */
	966
	967	{illegal,0 }, /* 20: 0100 1100 0010 0000 */
	968	{illegal,0 }, /* 21: 0100 1100 0010 0001 */
	969	{illegal,0 }, /* 22: 0100 1100 0010 0010 */
	970	{illegal,0 }, /* 23: 0100 1100 0010 0011 */
	971	{illegal,0 }, /* 24: 0100 1100 0010 0100 */
	972	{illegal,0 }, /* 25: 0100 1100 0010 0101 */
	973	{illegal,0 }, /* 26: 0100 1100 0010 0110 */
	974	{illegal,0 }, /* 27: 0100 1100 0010 0111 */
	975	{illegal,0 }, /* 28: 0100 1100 0010 1000 */
	976	{illegal,0 }, /* 29: 0100 1100 0010 1001 */
	977	{illegal,0 }, /* 2a: 0100 1100 0010 1010 */
	978	{illegal,0 }, /* 2b: 0100 1100 0010 1011 */
	979	{illegal,0 }, /* 2c: 0100 1100 0010 1100 */
	980	{illegal,0 }, /* 2d: 0100 1100 0010 1101 */
	981	{illegal,0 }, /* 2e: 0100 1100 0010 1110 */
	982	{illegal,0 }, /* 2f: 0100 1100 0010 1111 */
	983
	984	{illegal,0 }, /* 30: 0100 1100 0011 0000 */
	985	{illegal,0 }, /* 31: 0100 1100 0011 0001 */
	986	{illegal,0 }, /* 32: 0100 1100 0011 0010 */
	987	{illegal,0 }, /* 33: 0100 1100 0011 0011 */
	988	{illegal,0 }, /* 34: 0100 1100 0011 0100 */
	989	{illegal,0 }, /* 35: 0100 1100 0011 0101 */
	990	{illegal,0 }, /* 36: 0100 1100 0011 0110 */
	991	{illegal,0 }, /* 37: 0100 1100 0011 0111 */
	992	{illegal,0 }, /* 38: 0100 1100 0011 1000 */
	993	{illegal,0 }, /* 39: 0100 1100 0011 1001 */
	994	{illegal,0 }, /* 3a: 0100 1100 0011 1010 */
	995	{illegal,0 }, /* 3b: 0100 1100 0011 1011 */
	996	{illegal,0 }, /* 3c: 0100 1100 0011 1100 */
	997	{illegal,0 }, /* 3d: 0100 1100 0011 1101 */
	998	{illegal,0 }, /* 3e: 0100 1100 0011 1110 */
	999	{illegal,0 }, /* 3f: 0100 1100 0011 1111 */
	1000
	1001	{illegal,0 }, /* 40: 0100 1100 0100 0000 */
	1002	{illegal,0 }, /* 41: 0100 1100 0100 0001 */
	1003	{illegal,0 }, /* 42: 0100 1100 0100 0010 */
	1004	{illegal,0 }, /* 43: 0100 1100 0100 0011 */
	1005	{illegal,0 }, /* 44: 0100 1100 0100 0100 */
	1006	{illegal,0 }, /* 45: 0100 1100 0100 0101 */
	1007	{illegal,0 }, /* 46: 0100 1100 0100 0110 */
	1008	{illegal,0 }, /* 47: 0100 1100 0100 0111 */
	1009	{illegal,0 }, /* 48: 0100 1100 0100 1000 */
	1010	{illegal,0 }, /* 49: 0100 1100 0100 1001 */
	1011	{illegal,0 }, /* 4a: 0100 1100 0100 1010 */
	1012	{illegal,0 }, /* 4b: 0100 1100 0100 1011 */
	1013	{illegal,0 }, /* 4c: 0100 1100 0100 1100 */
	1014	{illegal,0 }, /* 4d: 0100 1100 0100 1101 */
	1015	{illegal,0 }, /* 4e: 0100 1100 0100 1110 */
	1016	{illegal,0 }, /* 4f: 0100 1100 0100 1111 */
	1017
	1018	{illegal,0 }, /* 50: 0100 1100 0101 0000 */
	1019	{illegal,0 }, /* 51: 0100 1100 0101 0001 */
	1020	{illegal,0 }, /* 52: 0100 1100 0101 0010 */
	1021	{illegal,0 }, /* 53: 0100 1100 0101 0011 */
	1022	{illegal,0 }, /* 54: 0100 1100 0101 0100 */
	1023	{illegal,0 }, /* 55: 0100 1100 0101 0101 */
	1024	{illegal,0 }, /* 56: 0100 1100 0101 0110 */
	1025	{illegal,0 }, /* 57: 0100 1100 0101 0111 */
	1026	{illegal,0 }, /* 58: 0100 1100 0101 1000 */
	1027	{illegal,0 }, /* 59: 0100 1100 0101 1001 */
	1028	{illegal,0 }, /* 5a: 0100 1100 0101 1010 */
	1029	{illegal,0 }, /* 5b: 0100 1100 0101 1011 */
	1030	{illegal,0 }, /* 5c: 0100 1100 0101 1100 */
	1031	{illegal,0 }, /* 5d: 0100 1100 0101 1101 */
	1032	{illegal,0 }, /* 5e: 0100 1100 0101 1110 */
	1033	{illegal,0 }, /* 5f: 0100 1100 0101 1111 */
	1034
	1035	{illegal,0 }, /* 60: 0100 1100 0110 0000 */
	1036	{illegal,0 }, /* 61: 0100 1100 0110 0001 */
	1037	{illegal,0 }, /* 62: 0100 1100 0110 0010 */
	1038	{illegal,0 }, /* 63: 0100 1100 0110 0011 */
	1039	{illegal,0 }, /* 64: 0100 1100 0110 0100 */
	1040	{illegal,0 }, /* 65: 0100 1100 0110 0101 */
	1041	{illegal,0 }, /* 66: 0100 1100 0110 0110 */
	1042	{illegal,0 }, /* 67: 0100 1100 0110 0111 */
	1043	{illegal,0 }, /* 68: 0100 1100 0110 1000 */
	1044	{illegal,0 }, /* 69: 0100 1100 0110 1001 */
	1045	{illegal,0 }, /* 6a: 0100 1100 0110 1010 */
	1046	{illegal,0 }, /* 6b: 0100 1100 0110 1011 */
	1047	{illegal,0 }, /* 6c: 0100 1100 0110 1100 */
	1048	{illegal,0 }, /* 6d: 0100 1100 0110 1101 */
	1049	{illegal,0 }, /* 6e: 0100 1100 0110 1110 */
	1050	{illegal,0 }, /* 6f: 0100 1100 0110 1111 */
	1051
	1052	{illegal,0 }, /* 70: 0100 1100 0111 0000 */
	1053	{illegal,0 }, /* 71: 0100 1100 0111 0001 */
	1054	{illegal,0 }, /* 72: 0100 1100 0111 0010 */
	1055	{illegal,0 }, /* 73: 0100 1100 0111 0011 */
	1056	{illegal,0 }, /* 74: 0100 1100 0111 0100 */
	1057	{illegal,0 }, /* 75: 0100 1100 0111 0101 */
	1058	{illegal,0 }, /* 76: 0100 1100 0111 0110 */
	1059	{illegal,0 }, /* 77: 0100 1100 0111 0111 */
	1060	{illegal,0 }, /* 78: 0100 1100 0111 1000 */
	1061	{illegal,0 }, /* 79: 0100 1100 0111 1001 */
	1062	{illegal,0 }, /* 7a: 0100 1100 0111 1010 */
	1063	{illegal,0 }, /* 7b: 0100 1100 0111 1011 */
	1064	{illegal,0 }, /* 7c: 0100 1100 0111 1100 */
	1065	{illegal,0 }, /* 7d: 0100 1100 0111 1101 */
	1066	{illegal,0 }, /* 7e: 0100 1100 0111 1110 */
	1067	{illegal,0 }, /* 7f: 0100 1100 0111 1111 */
	1068
	1069	{illegal,0 }, /* 80: 0100 1100 1000 0000 */
	1070	{illegal,0 }, /* 81: 0100 1100 1000 0001 */
	1071	{illegal,0 }, /* 82: 0100 1100 1000 0010 */
	1072	{illegal,0 }, /* 83: 0100 1100 1000 0011 */
	1073	{illegal,0 }, /* 84: 0100 1100 1000 0100 */
	1074	{illegal,0 }, /* 85: 0100 1100 1000 0101 */
	1075	{illegal,0 }, /* 86: 0100 1100 1000 0110 */
	1076	{illegal,0 }, /* 87: 0100 1100 1000 0111 */
	1077	{illegal,0 }, /* 88: 0100 1100 1000 1000 */
	1078	{illegal,0 }, /* 89: 0100 1100 1000 1001 */
	1079	{illegal,0 }, /* 8a: 0100 1100 1000 1010 */
	1080	{illegal,0 }, /* 8b: 0100 1100 1000 1011 */
	1081	{illegal,0 }, /* 8c: 0100 1100 1000 1100 */
	1082	{illegal,0 }, /* 8d: 0100 1100 1000 1101 */
	1083	{illegal,0 }, /* 8e: 0100 1100 1000 1110 */
	1084	{illegal,0 }, /* 8f: 0100 1100 1000 1111 */
	1085
	1086	{illegal,0 }, /* 90: 0100 1100 1001 0000 */
	1087	{illegal,0 }, /* 91: 0100 1100 1001 0001 */
	1088	{illegal,0 }, /* 92: 0100 1100 1001 0010 */
	1089	{illegal,0 }, /* 93: 0100 1100 1001 0011 */
	1090	{illegal,0 }, /* 94: 0100 1100 1001 0100 */
	1091	{illegal,0 }, /* 95: 0100 1100 1001 0101 */
	1092	{illegal,0 }, /* 96: 0100 1100 1001 0110 */
	1093	{illegal,0 }, /* 97: 0100 1100 1001 0111 */
	1094	{illegal,0 }, /* 98: 0100 1100 1001 1000 */
	1095	{illegal,0 }, /* 99: 0100 1100 1001 1001 */
	1096	{illegal,0 }, /* 9a: 0100 1100 1001 1010 */
	1097	{illegal,0 }, /* 9b: 0100 1100 1001 1011 */
	1098	{illegal,0 }, /* 9c: 0100 1100 1001 1100 */
	1099	{illegal,0 }, /* 9d: 0100 1100 1001 1101 */
	1100	{illegal,0 }, /* 9e: 0100 1100 1001 1110 */
	1101	{illegal,0 }, /* 9f: 0100 1100 1001 1111 */
	1102
	1103	{illegal,0 }, /* a0: 0100 1100 1010 0000 */
	1104	{illegal,0 }, /* a1: 0100 1100 1010 0001 */
	1105	{illegal,0 }, /* a2: 0100 1100 1010 0010 */
	1106	{illegal,0 }, /* a3: 0100 1100 1010 0011 */
	1107	{illegal,0 }, /* a4: 0100 1100 1010 0100 */
	1108	{illegal,0 }, /* a5: 0100 1100 1010 0101 */
	1109	{illegal,0 }, /* a6: 0100 1100 1010 0110 */
	1110	{illegal,0 }, /* a7: 0100 1100 1010 0111 */
	1111	{illegal,0 }, /* a8: 0100 1100 1010 1000 */
	1112	{illegal,0 }, /* a9: 0100 1100 1010 1001 */
	1113	{illegal,0 }, /* aa: 0100 1100 1010 1010 */
	1114	{illegal,0 }, /* ab: 0100 1100 1010 1011 */
	1115	{illegal,0 }, /* ac: 0100 1100 1010 1100 */
	1116	{illegal,0 }, /* ad: 0100 1100 1010 1101 */
	1117	{illegal,0 }, /* ae: 0100 1100 1010 1110 */
	1118	{illegal,0 }, /* af: 0100 1100 1010 1111 */
	1119
	1120	{illegal,0 }, /* b0: 0100 1100 1011 0000 */
	1121	{illegal,0 }, /* b1: 0100 1100 1011 0001 */
	1122	{illegal,0 }, /* b2: 0100 1100 1011 0010 */
	1123	{illegal,0 }, /* b3: 0100 1100 1011 0011 */
	1124	{illegal,0 }, /* b4: 0100 1100 1011 0100 */
	1125	{illegal,0 }, /* b5: 0100 1100 1011 0101 */
	1126	{illegal,0 }, /* b6: 0100 1100 1011 0110 */
	1127	{illegal,0 }, /* b7: 0100 1100 1011 0111 */
	1128	{illegal,0 }, /* b8: 0100 1100 1011 1000 */
	1129	{illegal,0 }, /* b9: 0100 1100 1011 1001 */
	1130	{illegal,0 }, /* ba: 0100 1100 1011 1010 */
	1131	{illegal,0 }, /* bb: 0100 1100 1011 1011 */
	1132	{illegal,0 }, /* bc: 0100 1100 1011 1100 */
	1133	{illegal,0 }, /* bd: 0100 1100 1011 1101 */
	1134	{illegal,0 }, /* be: 0100 1100 1011 1110 */
	1135	{illegal,0 }, /* bf: 0100 1100 1011 1111 */
	1136
	1137	{MOV,"A,PA" }, /* c0: 0100 1100 1100 0000 */
	1138	{MOV,"A,PB" }, /* c1: 0100 1100 1100 0001 */
	1139	{MOV,"A,PC" }, /* c2: 0100 1100 1100 0010 */
	1140	{MOV,"A,PD" }, /* c3: 0100 1100 1100 0011 */
	1141	{illegal,0 }, /* c4: 0100 1100 1100 0100 */
	1142	{MOV,"A,PF" }, /* c5: 0100 1100 1100 0101 */
	1143	{MOV,"A,MKH" }, /* c6: 0100 1100 1100 0110 */
	1144	{MOV,"A,MKL" }, /* c7: 0100 1100 1100 0111 */
	1145	{MOV,"A,ANM" }, /* c8: 0100 1100 1100 1000 / / 7810 */
	1146	{MOV,"A,SMH" }, /* c9: 0100 1100 1100 1001 */
	1147	{illegal,0 }, /* ca: 0100 1100 1100 1010 */
	1148	{MOV,"A,EOM" }, /* cb: 0100 1100 1100 1011 */
	1149	{illegal,0 }, /* cc: 0100 1100 1100 1100 */
	1150	{MOV,"A,TMM" }, /* cd: 0100 1100 1100 1101 */
	1151	{illegal,0 }, /* ce: 0100 1100 1100 1110 */
	1152	{illegal,0 }, /* cf: 0100 1100 1100 1111 */
	1153
	1154	{illegal,0 }, /* d0: 0100 1100 1101 0000 */
	1155	{illegal,0 }, /* d1: 0100 1100 1101 0001 */
	1156	{illegal,0 }, /* d2: 0100 1100 1101 0010 */
	1157	{illegal,0 }, /* d3: 0100 1100 1101 0011 */
	1158	{illegal,0 }, /* d4: 0100 1100 1101 0100 */
	1159	{illegal,0 }, /* d5: 0100 1100 1101 0101 */
	1160	{illegal,0 }, /* d6: 0100 1100 1101 0110 */
	1161	{illegal,0 }, /* d7: 0100 1100 1101 0111 */
	1162	{illegal,0 }, /* d8: 0100 1100 1101 1000 */
	1163	{MOV,"A,RXB" }, /* d9: 0100 1100 1101 1001 */
	1164	{illegal,0 }, /* da: 0100 1100 1101 1010 */
	1165	{illegal,0 }, /* db: 0100 1100 1101 1011 */
	1166	{illegal,0 }, /* dc: 0100 1100 1101 1100 */
	1167	{illegal,0 }, /* dd: 0100 1100 1101 1101 */
	1168	{illegal,0 }, /* de: 0100 1100 1101 1110 */
	1169	{illegal,0 }, /* df: 0100 1100 1101 1111 */
	1170
	1171	{MOV,"A,CR0" }, /* e0: 0100 1100 1110 0000 / / 7810 */
	1172	{MOV,"A,CR1" }, /* e1: 0100 1100 1110 0001 / / 7810 */
	1173	{MOV,"A,CR2" }, /* e2: 0100 1100 1110 0010 / / 7810 */
	1174	{MOV,"A,CR3" }, /* e3: 0100 1100 1110 0011 / / 7810 */
	1175	{illegal,0 }, /* e4: 0100 1100 1110 0100 */
	1176	{illegal,0 }, /* e5: 0100 1100 1110 0101 */
	1177	{illegal,0 }, /* e6: 0100 1100 1110 0110 */
	1178	{illegal,0 }, /* e7: 0100 1100 1110 0111 */
	1179	{illegal,0 }, /* e8: 0100 1100 1110 1000 */
	1180	{illegal,0 }, /* e9: 0100 1100 1110 1001 */
	1181	{illegal,0 }, /* ea: 0100 1100 1110 1010 */
	1182	{illegal,0 }, /* eb: 0100 1100 1110 1011 */
	1183	{illegal,0 }, /* ec: 0100 1100 1110 1100 */
	1184	{illegal,0 }, /* ed: 0100 1100 1110 1101 */
	1185	{illegal,0 }, /* ee: 0100 1100 1110 1110 */
	1186	{illegal,0 }, /* ef: 0100 1100 1110 1111 */
	1187
	1188	{illegal,0 }, /* f0: 0100 1100 1111 0000 */
	1189	{illegal,0 }, /* f1: 0100 1100 1111 0001 */
	1190	{illegal,0 }, /* f2: 0100 1100 1111 0010 */
	1191	{illegal,0 }, /* f3: 0100 1100 1111 0011 */
	1192	{illegal,0 }, /* f4: 0100 1100 1111 0100 */
	1193	{illegal,0 }, /* f5: 0100 1100 1111 0101 */
	1194	{illegal,0 }, /* f6: 0100 1100 1111 0110 */
	1195	{illegal,0 }, /* f7: 0100 1100 1111 0111 */
	1196	{illegal,0 }, /* f8: 0100 1100 1111 1000 */
	1197	{illegal,0 }, /* f9: 0100 1100 1111 1001 */
	1198	{illegal,0 }, /* fa: 0100 1100 1111 1010 */
	1199	{illegal,0 }, /* fb: 0100 1100 1111 1011 */
	1200	{illegal,0 }, /* fc: 0100 1100 1111 1100 */
	1201	{illegal,0 }, /* fd: 0100 1100 1111 1101 */
	1202	{illegal,0 }, /* fe: 0100 1100 1111 1110 */
	1203	{illegal,0 } /* ff: 0100 1100 1111 1111 */
	1204	};
	1205
	1206	static const struct dasm_s dasm4C_7807[256] =
	1207	{
	1208	{illegal,0 }, /* 00: 0100 1100 0000 0000 */
	1209	{illegal,0 }, /* 01: 0100 1100 0000 0001 */
	1210	{illegal,0 }, /* 02: 0100 1100 0000 0010 */
	1211	{illegal,0 }, /* 03: 0100 1100 0000 0011 */
	1212	{illegal,0 }, /* 04: 0100 1100 0000 0100 */
	1213	{illegal,0 }, /* 05: 0100 1100 0000 0101 */
	1214	{illegal,0 }, /* 06: 0100 1100 0000 0110 */
	1215	{illegal,0 }, /* 07: 0100 1100 0000 0111 */
	1216	{illegal,0 }, /* 08: 0100 1100 0000 1000 */
	1217	{illegal,0 }, /* 09: 0100 1100 0000 1001 */
	1218	{illegal,0 }, /* 0a: 0100 1100 0000 1010 */
	1219	{illegal,0 }, /* 0b: 0100 1100 0000 1011 */
	1220	{illegal,0 }, /* 0c: 0100 1100 0000 1100 */
	1221	{illegal,0 }, /* 0d: 0100 1100 0000 1101 */
	1222	{illegal,0 }, /* 0e: 0100 1100 0000 1110 */
	1223	{illegal,0 }, /* 0f: 0100 1100 0000 1111 */
	1224
	1225	{illegal,0 }, /* 10: 0100 1100 0001 0000 */
	1226	{illegal,0 }, /* 11: 0100 1100 0001 0001 */
	1227	{illegal,0 }, /* 12: 0100 1100 0001 0010 */
	1228	{illegal,0 }, /* 13: 0100 1100 0001 0011 */
	1229	{illegal,0 }, /* 14: 0100 1100 0001 0100 */
	1230	{illegal,0 }, /* 15: 0100 1100 0001 0101 */
	1231	{illegal,0 }, /* 16: 0100 1100 0001 0110 */
	1232	{illegal,0 }, /* 17: 0100 1100 0001 0111 */
	1233	{illegal,0 }, /* 18: 0100 1100 0001 1000 */
	1234	{illegal,0 }, /* 19: 0100 1100 0001 1001 */
	1235	{illegal,0 }, /* 1a: 0100 1100 0001 1010 */
	1236	{illegal,0 }, /* 1b: 0100 1100 0001 1011 */
	1237	{illegal,0 }, /* 1c: 0100 1100 0001 1100 */
	1238	{illegal,0 }, /* 1d: 0100 1100 0001 1101 */
	1239	{illegal,0 }, /* 1e: 0100 1100 0001 1110 */
	1240	{illegal,0 }, /* 1f: 0100 1100 0001 1111 */
	1241
	1242	{illegal,0 }, /* 20: 0100 1100 0010 0000 */
	1243	{illegal,0 }, /* 21: 0100 1100 0010 0001 */
	1244	{illegal,0 }, /* 22: 0100 1100 0010 0010 */
	1245	{illegal,0 }, /* 23: 0100 1100 0010 0011 */
	1246	{illegal,0 }, /* 24: 0100 1100 0010 0100 */
	1247	{illegal,0 }, /* 25: 0100 1100 0010 0101 */
	1248	{illegal,0 }, /* 26: 0100 1100 0010 0110 */
	1249	{illegal,0 }, /* 27: 0100 1100 0010 0111 */
	1250	{illegal,0 }, /* 28: 0100 1100 0010 1000 */
	1251	{illegal,0 }, /* 29: 0100 1100 0010 1001 */
	1252	{illegal,0 }, /* 2a: 0100 1100 0010 1010 */
	1253	{illegal,0 }, /* 2b: 0100 1100 0010 1011 */
	1254	{illegal,0 }, /* 2c: 0100 1100 0010 1100 */
	1255	{illegal,0 }, /* 2d: 0100 1100 0010 1101 */
	1256	{illegal,0 }, /* 2e: 0100 1100 0010 1110 */
	1257	{illegal,0 }, /* 2f: 0100 1100 0010 1111 */
	1258
	1259	{illegal,0 }, /* 30: 0100 1100 0011 0000 */
	1260	{illegal,0 }, /* 31: 0100 1100 0011 0001 */
	1261	{illegal,0 }, /* 32: 0100 1100 0011 0010 */
	1262	{illegal,0 }, /* 33: 0100 1100 0011 0011 */
	1263	{illegal,0 }, /* 34: 0100 1100 0011 0100 */
	1264	{illegal,0 }, /* 35: 0100 1100 0011 0101 */
	1265	{illegal,0 }, /* 36: 0100 1100 0011 0110 */
	1266	{illegal,0 }, /* 37: 0100 1100 0011 0111 */
	1267	{illegal,0 }, /* 38: 0100 1100 0011 1000 */
	1268	{illegal,0 }, /* 39: 0100 1100 0011 1001 */
	1269	{illegal,0 }, /* 3a: 0100 1100 0011 1010 */
	1270	{illegal,0 }, /* 3b: 0100 1100 0011 1011 */
	1271	{illegal,0 }, /* 3c: 0100 1100 0011 1100 */
	1272	{illegal,0 }, /* 3d: 0100 1100 0011 1101 */
	1273	{illegal,0 }, /* 3e: 0100 1100 0011 1110 */
	1274	{illegal,0 }, /* 3f: 0100 1100 0011 1111 */
	1275
	1276	{illegal,0 }, /* 40: 0100 1100 0100 0000 */
	1277	{illegal,0 }, /* 41: 0100 1100 0100 0001 */
	1278	{illegal,0 }, /* 42: 0100 1100 0100 0010 */
	1279	{illegal,0 }, /* 43: 0100 1100 0100 0011 */
	1280	{illegal,0 }, /* 44: 0100 1100 0100 0100 */
	1281	{illegal,0 }, /* 45: 0100 1100 0100 0101 */
	1282	{illegal,0 }, /* 46: 0100 1100 0100 0110 */
	1283	{illegal,0 }, /* 47: 0100 1100 0100 0111 */
	1284	{illegal,0 }, /* 48: 0100 1100 0100 1000 */
	1285	{illegal,0 }, /* 49: 0100 1100 0100 1001 */
	1286	{illegal,0 }, /* 4a: 0100 1100 0100 1010 */
	1287	{illegal,0 }, /* 4b: 0100 1100 0100 1011 */
	1288	{illegal,0 }, /* 4c: 0100 1100 0100 1100 */
	1289	{illegal,0 }, /* 4d: 0100 1100 0100 1101 */
	1290	{illegal,0 }, /* 4e: 0100 1100 0100 1110 */
	1291	{illegal,0 }, /* 4f: 0100 1100 0100 1111 */
	1292
	1293	{illegal,0 }, /* 50: 0100 1100 0101 0000 */
	1294	{illegal,0 }, /* 51: 0100 1100 0101 0001 */
	1295	{illegal,0 }, /* 52: 0100 1100 0101 0010 */
	1296	{illegal,0 }, /* 53: 0100 1100 0101 0011 */
	1297	{illegal,0 }, /* 54: 0100 1100 0101 0100 */
	1298	{illegal,0 }, /* 55: 0100 1100 0101 0101 */
	1299	{illegal,0 }, /* 56: 0100 1100 0101 0110 */
	1300	{illegal,0 }, /* 57: 0100 1100 0101 0111 */
	1301	{illegal,0 }, /* 58: 0100 1100 0101 1000 */
	1302	{illegal,0 }, /* 59: 0100 1100 0101 1001 */
	1303	{illegal,0 }, /* 5a: 0100 1100 0101 1010 */
	1304	{illegal,0 }, /* 5b: 0100 1100 0101 1011 */
	1305	{illegal,0 }, /* 5c: 0100 1100 0101 1100 */
	1306	{illegal,0 }, /* 5d: 0100 1100 0101 1101 */
	1307	{illegal,0 }, /* 5e: 0100 1100 0101 1110 */
	1308	{illegal,0 }, /* 5f: 0100 1100 0101 1111 */
	1309
	1310	{illegal,0 }, /* 60: 0100 1100 0110 0000 */
	1311	{illegal,0 }, /* 61: 0100 1100 0110 0001 */
	1312	{illegal,0 }, /* 62: 0100 1100 0110 0010 */
	1313	{illegal,0 }, /* 63: 0100 1100 0110 0011 */
	1314	{illegal,0 }, /* 64: 0100 1100 0110 0100 */
	1315	{illegal,0 }, /* 65: 0100 1100 0110 0101 */
	1316	{illegal,0 }, /* 66: 0100 1100 0110 0110 */
	1317	{illegal,0 }, /* 67: 0100 1100 0110 0111 */
	1318	{illegal,0 }, /* 68: 0100 1100 0110 1000 */
	1319	{illegal,0 }, /* 69: 0100 1100 0110 1001 */
	1320	{illegal,0 }, /* 6a: 0100 1100 0110 1010 */
	1321	{illegal,0 }, /* 6b: 0100 1100 0110 1011 */
	1322	{illegal,0 }, /* 6c: 0100 1100 0110 1100 */
	1323	{illegal,0 }, /* 6d: 0100 1100 0110 1101 */
	1324	{illegal,0 }, /* 6e: 0100 1100 0110 1110 */
	1325	{illegal,0 }, /* 6f: 0100 1100 0110 1111 */
	1326
	1327	{illegal,0 }, /* 70: 0100 1100 0111 0000 */
	1328	{illegal,0 }, /* 71: 0100 1100 0111 0001 */
	1329	{illegal,0 }, /* 72: 0100 1100 0111 0010 */
	1330	{illegal,0 }, /* 73: 0100 1100 0111 0011 */
	1331	{illegal,0 }, /* 74: 0100 1100 0111 0100 */
	1332	{illegal,0 }, /* 75: 0100 1100 0111 0101 */
	1333	{illegal,0 }, /* 76: 0100 1100 0111 0110 */
	1334	{illegal,0 }, /* 77: 0100 1100 0111 0111 */
	1335	{illegal,0 }, /* 78: 0100 1100 0111 1000 */
	1336	{illegal,0 }, /* 79: 0100 1100 0111 1001 */
	1337	{illegal,0 }, /* 7a: 0100 1100 0111 1010 */
	1338	{illegal,0 }, /* 7b: 0100 1100 0111 1011 */
	1339	{illegal,0 }, /* 7c: 0100 1100 0111 1100 */
	1340	{illegal,0 }, /* 7d: 0100 1100 0111 1101 */
	1341	{illegal,0 }, /* 7e: 0100 1100 0111 1110 */
	1342	{illegal,0 }, /* 7f: 0100 1100 0111 1111 */
	1343
	1344	{illegal,0 }, /* 80: 0100 1100 1000 0000 */
	1345	{illegal,0 }, /* 81: 0100 1100 1000 0001 */
	1346	{illegal,0 }, /* 82: 0100 1100 1000 0010 */
	1347	{illegal,0 }, /* 83: 0100 1100 1000 0011 */
	1348	{illegal,0 }, /* 84: 0100 1100 1000 0100 */
	1349	{illegal,0 }, /* 85: 0100 1100 1000 0101 */
	1350	{illegal,0 }, /* 86: 0100 1100 1000 0110 */
	1351	{illegal,0 }, /* 87: 0100 1100 1000 0111 */
	1352	{illegal,0 }, /* 88: 0100 1100 1000 1000 */
	1353	{illegal,0 }, /* 89: 0100 1100 1000 1001 */
	1354	{illegal,0 }, /* 8a: 0100 1100 1000 1010 */
	1355	{illegal,0 }, /* 8b: 0100 1100 1000 1011 */
	1356	{illegal,0 }, /* 8c: 0100 1100 1000 1100 */
	1357	{illegal,0 }, /* 8d: 0100 1100 1000 1101 */
	1358	{illegal,0 }, /* 8e: 0100 1100 1000 1110 */
	1359	{illegal,0 }, /* 8f: 0100 1100 1000 1111 */
	1360
	1361	{illegal,0 }, /* 90: 0100 1100 1001 0000 */
	1362	{illegal,0 }, /* 91: 0100 1100 1001 0001 */
	1363	{illegal,0 }, /* 92: 0100 1100 1001 0010 */
	1364	{illegal,0 }, /* 93: 0100 1100 1001 0011 */
	1365	{illegal,0 }, /* 94: 0100 1100 1001 0100 */
	1366	{illegal,0 }, /* 95: 0100 1100 1001 0101 */
	1367	{illegal,0 }, /* 96: 0100 1100 1001 0110 */
	1368	{illegal,0 }, /* 97: 0100 1100 1001 0111 */
	1369	{illegal,0 }, /* 98: 0100 1100 1001 1000 */
	1370	{illegal,0 }, /* 99: 0100 1100 1001 1001 */
	1371	{illegal,0 }, /* 9a: 0100 1100 1001 1010 */
	1372	{illegal,0 }, /* 9b: 0100 1100 1001 1011 */
	1373	{illegal,0 }, /* 9c: 0100 1100 1001 1100 */
	1374	{illegal,0 }, /* 9d: 0100 1100 1001 1101 */
	1375	{illegal,0 }, /* 9e: 0100 1100 1001 1110 */
	1376	{illegal,0 }, /* 9f: 0100 1100 1001 1111 */
	1377
	1378	{illegal,0 }, /* a0: 0100 1100 1010 0000 */
	1379	{illegal,0 }, /* a1: 0100 1100 1010 0001 */
	1380	{illegal,0 }, /* a2: 0100 1100 1010 0010 */
	1381	{illegal,0 }, /* a3: 0100 1100 1010 0011 */
	1382	{illegal,0 }, /* a4: 0100 1100 1010 0100 */
	1383	{illegal,0 }, /* a5: 0100 1100 1010 0101 */
	1384	{illegal,0 }, /* a6: 0100 1100 1010 0110 */
	1385	{illegal,0 }, /* a7: 0100 1100 1010 0111 */
	1386	{illegal,0 }, /* a8: 0100 1100 1010 1000 */
	1387	{illegal,0 }, /* a9: 0100 1100 1010 1001 */
	1388	{illegal,0 }, /* aa: 0100 1100 1010 1010 */
	1389	{illegal,0 }, /* ab: 0100 1100 1010 1011 */
	1390	{illegal,0 }, /* ac: 0100 1100 1010 1100 */
	1391	{illegal,0 }, /* ad: 0100 1100 1010 1101 */
	1392	{illegal,0 }, /* ae: 0100 1100 1010 1110 */
	1393	{illegal,0 }, /* af: 0100 1100 1010 1111 */
	1394
	1395	{illegal,0 }, /* b0: 0100 1100 1011 0000 */
	1396	{illegal,0 }, /* b1: 0100 1100 1011 0001 */
	1397	{illegal,0 }, /* b2: 0100 1100 1011 0010 */
	1398	{illegal,0 }, /* b3: 0100 1100 1011 0011 */
	1399	{illegal,0 }, /* b4: 0100 1100 1011 0100 */
	1400	{illegal,0 }, /* b5: 0100 1100 1011 0101 */
	1401	{illegal,0 }, /* b6: 0100 1100 1011 0110 */
	1402	{illegal,0 }, /* b7: 0100 1100 1011 0111 */
	1403	{illegal,0 }, /* b8: 0100 1100 1011 1000 */
	1404	{illegal,0 }, /* b9: 0100 1100 1011 1001 */
	1405	{illegal,0 }, /* ba: 0100 1100 1011 1010 */
	1406	{illegal,0 }, /* bb: 0100 1100 1011 1011 */
	1407	{illegal,0 }, /* bc: 0100 1100 1011 1100 */
	1408	{illegal,0 }, /* bd: 0100 1100 1011 1101 */
	1409	{illegal,0 }, /* be: 0100 1100 1011 1110 */
	1410	{illegal,0 }, /* bf: 0100 1100 1011 1111 */
	1411
	1412	{MOV,"A,PA" }, /* c0: 0100 1100 1100 0000 */
	1413	{MOV,"A,PB" }, /* c1: 0100 1100 1100 0001 */
	1414	{MOV,"A,PC" }, /* c2: 0100 1100 1100 0010 */
	1415	{MOV,"A,PD" }, /* c3: 0100 1100 1100 0011 */
	1416	{illegal,0 }, /* c4: 0100 1100 1100 0100 */
	1417	{MOV,"A,PF" }, /* c5: 0100 1100 1100 0101 */
	1418	{MOV,"A,MKH" }, /* c6: 0100 1100 1100 0110 */
	1419	{MOV,"A,MKL" }, /* c7: 0100 1100 1100 0111 */
	1420	{illegal,0 }, /* c8: 0100 1100 1100 1000 */
	1421	{MOV,"A,SMH" }, /* c9: 0100 1100 1100 1001 */
	1422	{illegal,0 }, /* ca: 0100 1100 1100 1010 */
	1423	{MOV,"A,EOM" }, /* cb: 0100 1100 1100 1011 */
	1424	{illegal,0 }, /* cc: 0100 1100 1100 1100 */
	1425	{MOV,"A,TMM" }, /* cd: 0100 1100 1100 1101 */
	1426	{MOV,"A,PT" }, /* ce: 0100 1100 1100 1110 / / 7807 */
	1427	{illegal,0 }, /* cf: 0100 1100 1100 1111 */
	1428
	1429	{illegal,0 }, /* d0: 0100 1100 1101 0000 */
	1430	{illegal,0 }, /* d1: 0100 1100 1101 0001 */
	1431	{illegal,0 }, /* d2: 0100 1100 1101 0010 */
	1432	{illegal,0 }, /* d3: 0100 1100 1101 0011 */
	1433	{illegal,0 }, /* d4: 0100 1100 1101 0100 */
	1434	{illegal,0 }, /* d5: 0100 1100 1101 0101 */
	1435	{illegal,0 }, /* d6: 0100 1100 1101 0110 */
	1436	{illegal,0 }, /* d7: 0100 1100 1101 0111 */
	1437	{illegal,0 }, /* d8: 0100 1100 1101 1000 */
	1438	{MOV,"A,RXB" }, /* d9: 0100 1100 1101 1001 */
	1439	{illegal,0 }, /* da: 0100 1100 1101 1010 */
	1440	{illegal,0 }, /* db: 0100 1100 1101 1011 */
	1441	{illegal,0 }, /* dc: 0100 1100 1101 1100 */
	1442	{illegal,0 }, /* dd: 0100 1100 1101 1101 */
	1443	{illegal,0 }, /* de: 0100 1100 1101 1110 */
	1444	{illegal,0 }, /* df: 0100 1100 1101 1111 */
	1445
	1446	{illegal,0 }, /* e0: 0100 1100 1110 0000 */
	1447	{illegal,0 }, /* e1: 0100 1100 1110 0001 */
	1448	{illegal,0 }, /* e2: 0100 1100 1110 0010 */
	1449	{illegal,0 }, /* e3: 0100 1100 1110 0011 */
	1450	{illegal,0 }, /* e4: 0100 1100 1110 0100 */
	1451	{illegal,0 }, /* e5: 0100 1100 1110 0101 */
	1452	{illegal,0 }, /* e6: 0100 1100 1110 0110 */
	1453	{illegal,0 }, /* e7: 0100 1100 1110 0111 */
	1454	{illegal,0 }, /* e8: 0100 1100 1110 1000 */
	1455	{illegal,0 }, /* e9: 0100 1100 1110 1001 */
	1456	{illegal,0 }, /* ea: 0100 1100 1110 1010 */
	1457	{illegal,0 }, /* eb: 0100 1100 1110 1011 */
	1458	{illegal,0 }, /* ec: 0100 1100 1110 1100 */
	1459	{illegal,0 }, /* ed: 0100 1100 1110 1101 */
	1460	{illegal,0 }, /* ee: 0100 1100 1110 1110 */
	1461	{illegal,0 }, /* ef: 0100 1100 1110 1111 */
	1462
	1463	{illegal,0 }, /* f0: 0100 1100 1111 0000 */
	1464	{illegal,0 }, /* f1: 0100 1100 1111 0001 */
	1465	{illegal,0 }, /* f2: 0100 1100 1111 0010 */
	1466	{illegal,0 }, /* f3: 0100 1100 1111 0011 */
	1467	{illegal,0 }, /* f4: 0100 1100 1111 0100 */
	1468	{illegal,0 }, /* f5: 0100 1100 1111 0101 */
	1469	{illegal,0 }, /* f6: 0100 1100 1111 0110 */
	1470	{illegal,0 }, /* f7: 0100 1100 1111 0111 */
	1471	{illegal,0 }, /* f8: 0100 1100 1111 1000 */
	1472	{illegal,0 }, /* f9: 0100 1100 1111 1001 */
	1473	{illegal,0 }, /* fa: 0100 1100 1111 1010 */
	1474	{illegal,0 }, /* fb: 0100 1100 1111 1011 */
	1475	{illegal,0 }, /* fc: 0100 1100 1111 1100 */
	1476	{illegal,0 }, /* fd: 0100 1100 1111 1101 */
	1477	{illegal,0 }, /* fe: 0100 1100 1111 1110 */
	1478	{illegal,0 } /* ff: 0100 1100 1111 1111 */
	1479	};
	1480
	1481	/* prefix 4D */
	1482	static const struct dasm_s dasm4D_7810[256] =
	1483	{
	1484	{illegal,0 }, /* 00: 0100 1101 0000 0000 */
	1485	{illegal,0 }, /* 01: 0100 1101 0000 0001 */
	1486	{illegal,0 }, /* 02: 0100 1101 0000 0010 */
	1487	{illegal,0 }, /* 03: 0100 1101 0000 0011 */
	1488	{illegal,0 }, /* 04: 0100 1101 0000 0100 */
	1489	{illegal,0 }, /* 05: 0100 1101 0000 0101 */
	1490	{illegal,0 }, /* 06: 0100 1101 0000 0110 */
	1491	{illegal,0 }, /* 07: 0100 1101 0000 0111 */
	1492	{illegal,0 }, /* 08: 0100 1101 0000 1000 */
	1493	{illegal,0 }, /* 09: 0100 1101 0000 1001 */
	1494	{illegal,0 }, /* 0a: 0100 1101 0000 1010 */
	1495	{illegal,0 }, /* 0b: 0100 1101 0000 1011 */
	1496	{illegal,0 }, /* 0c: 0100 1101 0000 1100 */
	1497	{illegal,0 }, /* 0d: 0100 1101 0000 1101 */
	1498	{illegal,0 }, /* 0e: 0100 1101 0000 1110 */
	1499	{illegal,0 }, /* 0f: 0100 1101 0000 1111 */
	1500
	1501	{illegal,0 }, /* 10: 0100 1101 0001 0000 */
	1502	{illegal,0 }, /* 11: 0100 1101 0001 0001 */
	1503	{illegal,0 }, /* 12: 0100 1101 0001 0010 */
	1504	{illegal,0 }, /* 13: 0100 1101 0001 0011 */
	1505	{illegal,0 }, /* 14: 0100 1101 0001 0100 */
	1506	{illegal,0 }, /* 15: 0100 1101 0001 0101 */
	1507	{illegal,0 }, /* 16: 0100 1101 0001 0110 */
	1508	{illegal,0 }, /* 17: 0100 1101 0001 0111 */
	1509	{illegal,0 }, /* 18: 0100 1101 0001 1000 */
	1510	{illegal,0 }, /* 19: 0100 1101 0001 1001 */
	1511	{illegal,0 }, /* 1a: 0100 1101 0001 1010 */
	1512	{illegal,0 }, /* 1b: 0100 1101 0001 1011 */
	1513	{illegal,0 }, /* 1c: 0100 1101 0001 1100 */
	1514	{illegal,0 }, /* 1d: 0100 1101 0001 1101 */
	1515	{illegal,0 }, /* 1e: 0100 1101 0001 1110 */
	1516	{illegal,0 }, /* 1f: 0100 1101 0001 1111 */
	1517
	1518	{illegal,0 }, /* 20: 0100 1101 0010 0000 */
	1519	{illegal,0 }, /* 21: 0100 1101 0010 0001 */
	1520	{illegal,0 }, /* 22: 0100 1101 0010 0010 */
	1521	{illegal,0 }, /* 23: 0100 1101 0010 0011 */
	1522	{illegal,0 }, /* 24: 0100 1101 0010 0100 */
	1523	{illegal,0 }, /* 25: 0100 1101 0010 0101 */
	1524	{illegal,0 }, /* 26: 0100 1101 0010 0110 */
	1525	{illegal,0 }, /* 27: 0100 1101 0010 0111 */
	1526	{illegal,0 }, /* 28: 0100 1101 0010 1000 */
	1527	{illegal,0 }, /* 29: 0100 1101 0010 1001 */
	1528	{illegal,0 }, /* 2a: 0100 1101 0010 1010 */
	1529	{illegal,0 }, /* 2b: 0100 1101 0010 1011 */
	1530	{illegal,0 }, /* 2c: 0100 1101 0010 1100 */
	1531	{illegal,0 }, /* 2d: 0100 1101 0010 1101 */
	1532	{illegal,0 }, /* 2e: 0100 1101 0010 1110 */
	1533	{illegal,0 }, /* 2f: 0100 1101 0010 1111 */
	1534
	1535	{illegal,0 }, /* 30: 0100 1101 0011 0000 */
	1536	{illegal,0 }, /* 31: 0100 1101 0011 0001 */
	1537	{illegal,0 }, /* 32: 0100 1101 0011 0010 */
	1538	{illegal,0 }, /* 33: 0100 1101 0011 0011 */
	1539	{illegal,0 }, /* 34: 0100 1101 0011 0100 */
	1540	{illegal,0 }, /* 35: 0100 1101 0011 0101 */
	1541	{illegal,0 }, /* 36: 0100 1101 0011 0110 */
	1542	{illegal,0 }, /* 37: 0100 1101 0011 0111 */
	1543	{illegal,0 }, /* 38: 0100 1101 0011 1000 */
	1544	{illegal,0 }, /* 39: 0100 1101 0011 1001 */
	1545	{illegal,0 }, /* 3a: 0100 1101 0011 1010 */
	1546	{illegal,0 }, /* 3b: 0100 1101 0011 1011 */
	1547	{illegal,0 }, /* 3c: 0100 1101 0011 1100 */
	1548	{illegal,0 }, /* 3d: 0100 1101 0011 1101 */
	1549	{illegal,0 }, /* 3e: 0100 1101 0011 1110 */
	1550	{illegal,0 }, /* 3f: 0100 1101 0011 1111 */
	1551
	1552	{illegal,0 }, /* 40: 0100 1101 0100 0000 */
	1553	{illegal,0 }, /* 41: 0100 1101 0100 0001 */
	1554	{illegal,0 }, /* 42: 0100 1101 0100 0010 */
	1555	{illegal,0 }, /* 43: 0100 1101 0100 0011 */
	1556	{illegal,0 }, /* 44: 0100 1101 0100 0100 */
	1557	{illegal,0 }, /* 45: 0100 1101 0100 0101 */
	1558	{illegal,0 }, /* 46: 0100 1101 0100 0110 */
	1559	{illegal,0 }, /* 47: 0100 1101 0100 0111 */
	1560	{illegal,0 }, /* 48: 0100 1101 0100 1000 */
	1561	{illegal,0 }, /* 49: 0100 1101 0100 1001 */
	1562	{illegal,0 }, /* 4a: 0100 1101 0100 1010 */
	1563	{illegal,0 }, /* 4b: 0100 1101 0100 1011 */
	1564	{illegal,0 }, /* 4c: 0100 1101 0100 1100 */
	1565	{illegal,0 }, /* 4d: 0100 1101 0100 1101 */
	1566	{illegal,0 }, /* 4e: 0100 1101 0100 1110 */
	1567	{illegal,0 }, /* 4f: 0100 1101 0100 1111 */
	1568
	1569	{illegal,0 }, /* 50: 0100 1101 0101 0000 */
	1570	{illegal,0 }, /* 51: 0100 1101 0101 0001 */
	1571	{illegal,0 }, /* 52: 0100 1101 0101 0010 */
	1572	{illegal,0 }, /* 53: 0100 1101 0101 0011 */
	1573	{illegal,0 }, /* 54: 0100 1101 0101 0100 */
	1574	{illegal,0 }, /* 55: 0100 1101 0101 0101 */
	1575	{illegal,0 }, /* 56: 0100 1101 0101 0110 */
	1576	{illegal,0 }, /* 57: 0100 1101 0101 0111 */
	1577	{illegal,0 }, /* 58: 0100 1101 0101 1000 */
	1578	{illegal,0 }, /* 59: 0100 1101 0101 1001 */
	1579	{illegal,0 }, /* 5a: 0100 1101 0101 1010 */
	1580	{illegal,0 }, /* 5b: 0100 1101 0101 1011 */
	1581	{illegal,0 }, /* 5c: 0100 1101 0101 1100 */
	1582	{illegal,0 }, /* 5d: 0100 1101 0101 1101 */
	1583	{illegal,0 }, /* 5e: 0100 1101 0101 1110 */
	1584	{illegal,0 }, /* 5f: 0100 1101 0101 1111 */
	1585
	1586	{illegal,0 }, /* 60: 0100 1101 0110 0000 */
	1587	{illegal,0 }, /* 61: 0100 1101 0110 0001 */
	1588	{illegal,0 }, /* 62: 0100 1101 0110 0010 */
	1589	{illegal,0 }, /* 63: 0100 1101 0110 0011 */
	1590	{illegal,0 }, /* 64: 0100 1101 0110 0100 */
	1591	{illegal,0 }, /* 65: 0100 1101 0110 0101 */
	1592	{illegal,0 }, /* 66: 0100 1101 0110 0110 */
	1593	{illegal,0 }, /* 67: 0100 1101 0110 0111 */
	1594	{illegal,0 }, /* 68: 0100 1101 0110 1000 */
	1595	{illegal,0 }, /* 69: 0100 1101 0110 1001 */
	1596	{illegal,0 }, /* 6a: 0100 1101 0110 1010 */
	1597	{illegal,0 }, /* 6b: 0100 1101 0110 1011 */
	1598	{illegal,0 }, /* 6c: 0100 1101 0110 1100 */
	1599	{illegal,0 }, /* 6d: 0100 1101 0110 1101 */
	1600	{illegal,0 }, /* 6e: 0100 1101 0110 1110 */
	1601	{illegal,0 }, /* 6f: 0100 1101 0110 1111 */
	1602
	1603	{illegal,0 }, /* 70: 0100 1101 0111 0000 */
	1604	{illegal,0 }, /* 71: 0100 1101 0111 0001 */
	1605	{illegal,0 }, /* 72: 0100 1101 0111 0010 */
	1606	{illegal,0 }, /* 73: 0100 1101 0111 0011 */
	1607	{illegal,0 }, /* 74: 0100 1101 0111 0100 */
	1608	{illegal,0 }, /* 75: 0100 1101 0111 0101 */
	1609	{illegal,0 }, /* 76: 0100 1101 0111 0110 */
	1610	{illegal,0 }, /* 77: 0100 1101 0111 0111 */
	1611	{illegal,0 }, /* 78: 0100 1101 0111 1000 */
	1612	{illegal,0 }, /* 79: 0100 1101 0111 1001 */
	1613	{illegal,0 }, /* 7a: 0100 1101 0111 1010 */
	1614	{illegal,0 }, /* 7b: 0100 1101 0111 1011 */
	1615	{illegal,0 }, /* 7c: 0100 1101 0111 1100 */
	1616	{illegal,0 }, /* 7d: 0100 1101 0111 1101 */
	1617	{illegal,0 }, /* 7e: 0100 1101 0111 1110 */
	1618	{illegal,0 }, /* 7f: 0100 1101 0111 1111 */
	1619
	1620	{illegal,0 }, /* 80: 0100 1101 1000 0000 */
	1621	{illegal,0 }, /* 81: 0100 1101 1000 0001 */
	1622	{illegal,0 }, /* 82: 0100 1101 1000 0010 */
	1623	{illegal,0 }, /* 83: 0100 1101 1000 0011 */
	1624	{illegal,0 }, /* 84: 0100 1101 1000 0100 */
	1625	{illegal,0 }, /* 85: 0100 1101 1000 0101 */
	1626	{illegal,0 }, /* 86: 0100 1101 1000 0110 */
	1627	{illegal,0 }, /* 87: 0100 1101 1000 0111 */
	1628	{illegal,0 }, /* 88: 0100 1101 1000 1000 */
	1629	{illegal,0 }, /* 89: 0100 1101 1000 1001 */
	1630	{illegal,0 }, /* 8a: 0100 1101 1000 1010 */
	1631	{illegal,0 }, /* 8b: 0100 1101 1000 1011 */
	1632	{illegal,0 }, /* 8c: 0100 1101 1000 1100 */
	1633	{illegal,0 }, /* 8d: 0100 1101 1000 1101 */
	1634	{illegal,0 }, /* 8e: 0100 1101 1000 1110 */
	1635	{illegal,0 }, /* 8f: 0100 1101 1000 1111 */
	1636
	1637	{illegal,0 }, /* 90: 0100 1101 1001 0000 */
	1638	{illegal,0 }, /* 91: 0100 1101 1001 0001 */
	1639	{illegal,0 }, /* 92: 0100 1101 1001 0010 */
	1640	{illegal,0 }, /* 93: 0100 1101 1001 0011 */
	1641	{illegal,0 }, /* 94: 0100 1101 1001 0100 */
	1642	{illegal,0 }, /* 95: 0100 1101 1001 0101 */
	1643	{illegal,0 }, /* 96: 0100 1101 1001 0110 */
	1644	{illegal,0 }, /* 97: 0100 1101 1001 0111 */
	1645	{illegal,0 }, /* 98: 0100 1101 1001 1000 */
	1646	{illegal,0 }, /* 99: 0100 1101 1001 1001 */
	1647	{illegal,0 }, /* 9a: 0100 1101 1001 1010 */
	1648	{illegal,0 }, /* 9b: 0100 1101 1001 1011 */
	1649	{illegal,0 }, /* 9c: 0100 1101 1001 1100 */
	1650	{illegal,0 }, /* 9d: 0100 1101 1001 1101 */
	1651	{illegal,0 }, /* 9e: 0100 1101 1001 1110 */
	1652	{illegal,0 }, /* 9f: 0100 1101 1001 1111 */
	1653
	1654	{illegal,0 }, /* a0: 0100 1101 1010 0000 */
	1655	{illegal,0 }, /* a1: 0100 1101 1010 0001 */
	1656	{illegal,0 }, /* a2: 0100 1101 1010 0010 */
	1657	{illegal,0 }, /* a3: 0100 1101 1010 0011 */
	1658	{illegal,0 }, /* a4: 0100 1101 1010 0100 */
	1659	{illegal,0 }, /* a5: 0100 1101 1010 0101 */
	1660	{illegal,0 }, /* a6: 0100 1101 1010 0110 */
	1661	{illegal,0 }, /* a7: 0100 1101 1010 0111 */
	1662	{illegal,0 }, /* a8: 0100 1101 1010 1000 */
	1663	{illegal,0 }, /* a9: 0100 1101 1010 1001 */
	1664	{illegal,0 }, /* aa: 0100 1101 1010 1010 */
	1665	{illegal,0 }, /* ab: 0100 1101 1010 1011 */
	1666	{illegal,0 }, /* ac: 0100 1101 1010 1100 */
	1667	{illegal,0 }, /* ad: 0100 1101 1010 1101 */
	1668	{illegal,0 }, /* ae: 0100 1101 1010 1110 */
	1669	{illegal,0 }, /* af: 0100 1101 1010 1111 */
	1670
	1671	{illegal,0 }, /* b0: 0100 1101 1011 0000 */
	1672	{illegal,0 }, /* b1: 0100 1101 1011 0001 */
	1673	{illegal,0 }, /* b2: 0100 1101 1011 0010 */
	1674	{illegal,0 }, /* b3: 0100 1101 1011 0011 */
	1675	{illegal,0 }, /* b4: 0100 1101 1011 0100 */
	1676	{illegal,0 }, /* b5: 0100 1101 1011 0101 */
	1677	{illegal,0 }, /* b6: 0100 1101 1011 0110 */
	1678	{illegal,0 }, /* b7: 0100 1101 1011 0111 */
	1679	{illegal,0 }, /* b8: 0100 1101 1011 1000 */
	1680	{illegal,0 }, /* b9: 0100 1101 1011 1001 */
	1681	{illegal,0 }, /* ba: 0100 1101 1011 1010 */
	1682	{illegal,0 }, /* bb: 0100 1101 1011 1011 */
	1683	{illegal,0 }, /* bc: 0100 1101 1011 1100 */
	1684	{illegal,0 }, /* bd: 0100 1101 1011 1101 */
	1685	{illegal,0 }, /* be: 0100 1101 1011 1110 */
	1686	{illegal,0 }, /* bf: 0100 1101 1011 1111 */
	1687
	1688	{MOV,"PA,A" }, /* c0: 0100 1101 1100 0000 */
	1689	{MOV,"PB,A" }, /* c1: 0100 1101 1100 0001 */
	1690	{MOV,"PC,A" }, /* c2: 0100 1101 1100 0010 */
	1691	{MOV,"PD,A" }, /* c3: 0100 1101 1100 0011 */
	1692	{illegal,0 }, /* c4: 0100 1101 1100 0100 */
	1693	{MOV,"PF,A" }, /* c5: 0100 1101 1100 0101 */
	1694	{MOV,"MKH,A" }, /* c6: 0100 1101 1100 0110 */
	1695	{MOV,"MKL,A" }, /* c7: 0100 1101 1100 0111 */
	1696	{MOV,"ANM,A" }, /* c8: 0100 1101 1100 1000 / / 7810 */
	1697	{MOV,"SMH,A" }, /* c9: 0100 1101 1100 1001 */
	1698	{MOV,"SML,A" }, /* ca: 0100 1101 1100 1010 */
	1699	{MOV,"EOM,A" }, /* cb: 0100 1101 1100 1011 */
	1700	{MOV,"ETMM,A" }, /* cc: 0100 1101 1100 1100 */
	1701	{MOV,"TMM,A" }, /* cd: 0100 1101 1100 1101 */
	1702	{illegal,0 }, /* ce: 0100 1101 1100 1110 */
	1703	{illegal,0 }, /* cf: 0100 1101 1100 1111 */
	1704
	1705	{MOV,"MM,A" }, /* d0: 0100 1101 1101 0000 */
	1706	{MOV,"MCC,A" }, /* d1: 0100 1101 1101 0001 */
	1707	{MOV,"MA,A" }, /* d2: 0100 1101 1101 0010 */
	1708	{MOV,"MB,A" }, /* d3: 0100 1101 1101 0011 */
	1709	{MOV,"MC,A" }, /* d4: 0100 1101 1101 0100 */
	1710	{illegal,0 }, /* d5: 0100 1101 1101 0101 */
	1711	{illegal,0 }, /* d6: 0100 1101 1101 0110 */
	1712	{MOV,"MF,A" }, /* d7: 0100 1101 1101 0111 */
	1713	{MOV,"TXB,A" }, /* d8: 0100 1101 1101 1000 */
	1714	{illegal,0 }, /* d9: 0100 1101 1101 1001 */
	1715	{MOV,"TM0,A" }, /* da: 0100 1101 1101 1010 */
	1716	{MOV,"TM1,A" }, /* db: 0100 1101 1101 1011 */
	1717	{illegal,0 }, /* dc: 0100 1101 1101 1100 */
	1718	{illegal,0 }, /* dd: 0100 1101 1101 1101 */
	1719	{illegal,0 }, /* de: 0100 1101 1101 1110 */
	1720	{illegal,0 }, /* df: 0100 1101 1101 1111 */
	1721
	1722	{illegal,0 }, /* e0: 0100 1101 1110 0000 */
	1723	{illegal,0 }, /* e1: 0100 1101 1110 0001 */
	1724	{illegal,0 }, /* e2: 0100 1101 1110 0010 */
	1725	{illegal,0 }, /* e3: 0100 1101 1110 0011 */
	1726	{illegal,0 }, /* e4: 0100 1101 1110 0100 */
	1727	{illegal,0 }, /* e5: 0100 1101 1110 0101 */
	1728	{illegal,0 }, /* e6: 0100 1101 1110 0110 */
	1729	{illegal,0 }, /* e7: 0100 1101 1110 0111 */
	1730	{MOV,"ZCM,A" }, /* e8: 0100 1101 1110 1000 / / 7810 */
	1731	{illegal,0 }, /* e9: 0100 1101 1110 1001 */
	1732	{illegal,0 }, /* ea: 0100 1101 1110 1010 */
	1733	{illegal,0 }, /* eb: 0100 1101 1110 1011 */
	1734	{illegal,0 }, /* ec: 0100 1101 1110 1100 */
	1735	{illegal,0 }, /* ed: 0100 1101 1110 1101 */
	1736	{illegal,0 }, /* ee: 0100 1101 1110 1110 */
	1737	{illegal,0 }, /* ef: 0100 1101 1110 1111 */
	1738
	1739	{illegal,0 }, /* f0: 0100 1101 1111 0000 */
	1740	{illegal,0 }, /* f1: 0100 1101 1111 0001 */
	1741	{illegal,0 }, /* f2: 0100 1101 1111 0010 */
	1742	{illegal,0 }, /* f3: 0100 1101 1111 0011 */
	1743	{illegal,0 }, /* f4: 0100 1101 1111 0100 */
	1744	{illegal,0 }, /* f5: 0100 1101 1111 0101 */
	1745	{illegal,0 }, /* f6: 0100 1101 1111 0110 */
	1746	{illegal,0 }, /* f7: 0100 1101 1111 0111 */
	1747	{illegal,0 }, /* f8: 0100 1101 1111 1000 */
	1748	{illegal,0 }, /* f9: 0100 1101 1111 1001 */
	1749	{illegal,0 }, /* fa: 0100 1101 1111 1010 */
	1750	{illegal,0 }, /* fb: 0100 1101 1111 1011 */
	1751	{illegal,0 }, /* fc: 0100 1101 1111 1100 */
	1752	{illegal,0 }, /* fd: 0100 1101 1111 1101 */
	1753	{illegal,0 }, /* fe: 0100 1101 1111 1110 */
	1754	{illegal,0 } /* ff: 0100 1101 1111 1111 */
	1755	};
	1756
	1757	static const struct dasm_s dasm4D_7807[256] =
	1758	{
	1759	{illegal,0 }, /* 00: 0100 1101 0000 0000 */
	1760	{illegal,0 }, /* 01: 0100 1101 0000 0001 */
	1761	{illegal,0 }, /* 02: 0100 1101 0000 0010 */
	1762	{illegal,0 }, /* 03: 0100 1101 0000 0011 */
	1763	{illegal,0 }, /* 04: 0100 1101 0000 0100 */
	1764	{illegal,0 }, /* 05: 0100 1101 0000 0101 */
	1765	{illegal,0 }, /* 06: 0100 1101 0000 0110 */
	1766	{illegal,0 }, /* 07: 0100 1101 0000 0111 */
	1767	{illegal,0 }, /* 08: 0100 1101 0000 1000 */
	1768	{illegal,0 }, /* 09: 0100 1101 0000 1001 */
	1769	{illegal,0 }, /* 0a: 0100 1101 0000 1010 */
	1770	{illegal,0 }, /* 0b: 0100 1101 0000 1011 */
	1771	{illegal,0 }, /* 0c: 0100 1101 0000 1100 */
	1772	{illegal,0 }, /* 0d: 0100 1101 0000 1101 */
	1773	{illegal,0 }, /* 0e: 0100 1101 0000 1110 */
	1774	{illegal,0 }, /* 0f: 0100 1101 0000 1111 */
	1775
	1776	{illegal,0 }, /* 10: 0100 1101 0001 0000 */
	1777	{illegal,0 }, /* 11: 0100 1101 0001 0001 */
	1778	{illegal,0 }, /* 12: 0100 1101 0001 0010 */
	1779	{illegal,0 }, /* 13: 0100 1101 0001 0011 */
	1780	{illegal,0 }, /* 14: 0100 1101 0001 0100 */
	1781	{illegal,0 }, /* 15: 0100 1101 0001 0101 */
	1782	{illegal,0 }, /* 16: 0100 1101 0001 0110 */
	1783	{illegal,0 }, /* 17: 0100 1101 0001 0111 */
	1784	{illegal,0 }, /* 18: 0100 1101 0001 1000 */
	1785	{illegal,0 }, /* 19: 0100 1101 0001 1001 */
	1786	{illegal,0 }, /* 1a: 0100 1101 0001 1010 */
	1787	{illegal,0 }, /* 1b: 0100 1101 0001 1011 */
	1788	{illegal,0 }, /* 1c: 0100 1101 0001 1100 */
	1789	{illegal,0 }, /* 1d: 0100 1101 0001 1101 */
	1790	{illegal,0 }, /* 1e: 0100 1101 0001 1110 */
	1791	{illegal,0 }, /* 1f: 0100 1101 0001 1111 */
	1792
	1793	{illegal,0 }, /* 20: 0100 1101 0010 0000 */
	1794	{illegal,0 }, /* 21: 0100 1101 0010 0001 */
	1795	{illegal,0 }, /* 22: 0100 1101 0010 0010 */
	1796	{illegal,0 }, /* 23: 0100 1101 0010 0011 */
	1797	{illegal,0 }, /* 24: 0100 1101 0010 0100 */
	1798	{illegal,0 }, /* 25: 0100 1101 0010 0101 */
	1799	{illegal,0 }, /* 26: 0100 1101 0010 0110 */
	1800	{illegal,0 }, /* 27: 0100 1101 0010 0111 */
	1801	{illegal,0 }, /* 28: 0100 1101 0010 1000 */
	1802	{illegal,0 }, /* 29: 0100 1101 0010 1001 */
	1803	{illegal,0 }, /* 2a: 0100 1101 0010 1010 */
	1804	{illegal,0 }, /* 2b: 0100 1101 0010 1011 */
	1805	{illegal,0 }, /* 2c: 0100 1101 0010 1100 */
	1806	{illegal,0 }, /* 2d: 0100 1101 0010 1101 */
	1807	{illegal,0 }, /* 2e: 0100 1101 0010 1110 */
	1808	{illegal,0 }, /* 2f: 0100 1101 0010 1111 */
	1809
	1810	{illegal,0 }, /* 30: 0100 1101 0011 0000 */
	1811	{illegal,0 }, /* 31: 0100 1101 0011 0001 */
	1812	{illegal,0 }, /* 32: 0100 1101 0011 0010 */
	1813	{illegal,0 }, /* 33: 0100 1101 0011 0011 */
	1814	{illegal,0 }, /* 34: 0100 1101 0011 0100 */
	1815	{illegal,0 }, /* 35: 0100 1101 0011 0101 */
	1816	{illegal,0 }, /* 36: 0100 1101 0011 0110 */
	1817	{illegal,0 }, /* 37: 0100 1101 0011 0111 */
	1818	{illegal,0 }, /* 38: 0100 1101 0011 1000 */
	1819	{illegal,0 }, /* 39: 0100 1101 0011 1001 */
	1820	{illegal,0 }, /* 3a: 0100 1101 0011 1010 */
	1821	{illegal,0 }, /* 3b: 0100 1101 0011 1011 */
	1822	{illegal,0 }, /* 3c: 0100 1101 0011 1100 */
	1823	{illegal,0 }, /* 3d: 0100 1101 0011 1101 */
	1824	{illegal,0 }, /* 3e: 0100 1101 0011 1110 */
	1825	{illegal,0 }, /* 3f: 0100 1101 0011 1111 */
	1826
	1827	{illegal,0 }, /* 40: 0100 1101 0100 0000 */
	1828	{illegal,0 }, /* 41: 0100 1101 0100 0001 */
	1829	{illegal,0 }, /* 42: 0100 1101 0100 0010 */
	1830	{illegal,0 }, /* 43: 0100 1101 0100 0011 */
	1831	{illegal,0 }, /* 44: 0100 1101 0100 0100 */
	1832	{illegal,0 }, /* 45: 0100 1101 0100 0101 */
	1833	{illegal,0 }, /* 46: 0100 1101 0100 0110 */
	1834	{illegal,0 }, /* 47: 0100 1101 0100 0111 */
	1835	{illegal,0 }, /* 48: 0100 1101 0100 1000 */
	1836	{illegal,0 }, /* 49: 0100 1101 0100 1001 */
	1837	{illegal,0 }, /* 4a: 0100 1101 0100 1010 */
	1838	{illegal,0 }, /* 4b: 0100 1101 0100 1011 */
	1839	{illegal,0 }, /* 4c: 0100 1101 0100 1100 */
	1840	{illegal,0 }, /* 4d: 0100 1101 0100 1101 */
	1841	{illegal,0 }, /* 4e: 0100 1101 0100 1110 */
	1842	{illegal,0 }, /* 4f: 0100 1101 0100 1111 */
	1843
	1844	{illegal,0 }, /* 50: 0100 1101 0101 0000 */
	1845	{illegal,0 }, /* 51: 0100 1101 0101 0001 */
	1846	{illegal,0 }, /* 52: 0100 1101 0101 0010 */
	1847	{illegal,0 }, /* 53: 0100 1101 0101 0011 */
	1848	{illegal,0 }, /* 54: 0100 1101 0101 0100 */
	1849	{illegal,0 }, /* 55: 0100 1101 0101 0101 */
	1850	{illegal,0 }, /* 56: 0100 1101 0101 0110 */
	1851	{illegal,0 }, /* 57: 0100 1101 0101 0111 */
	1852	{illegal,0 }, /* 58: 0100 1101 0101 1000 */
	1853	{illegal,0 }, /* 59: 0100 1101 0101 1001 */
	1854	{illegal,0 }, /* 5a: 0100 1101 0101 1010 */
	1855	{illegal,0 }, /* 5b: 0100 1101 0101 1011 */
	1856	{illegal,0 }, /* 5c: 0100 1101 0101 1100 */
	1857	{illegal,0 }, /* 5d: 0100 1101 0101 1101 */
	1858	{illegal,0 }, /* 5e: 0100 1101 0101 1110 */
	1859	{illegal,0 }, /* 5f: 0100 1101 0101 1111 */
	1860
	1861	{illegal,0 }, /* 60: 0100 1101 0110 0000 */
	1862	{illegal,0 }, /* 61: 0100 1101 0110 0001 */
	1863	{illegal,0 }, /* 62: 0100 1101 0110 0010 */
	1864	{illegal,0 }, /* 63: 0100 1101 0110 0011 */
	1865	{illegal,0 }, /* 64: 0100 1101 0110 0100 */
	1866	{illegal,0 }, /* 65: 0100 1101 0110 0101 */
	1867	{illegal,0 }, /* 66: 0100 1101 0110 0110 */
	1868	{illegal,0 }, /* 67: 0100 1101 0110 0111 */
	1869	{illegal,0 }, /* 68: 0100 1101 0110 1000 */
	1870	{illegal,0 }, /* 69: 0100 1101 0110 1001 */
	1871	{illegal,0 }, /* 6a: 0100 1101 0110 1010 */
	1872	{illegal,0 }, /* 6b: 0100 1101 0110 1011 */
	1873	{illegal,0 }, /* 6c: 0100 1101 0110 1100 */
	1874	{illegal,0 }, /* 6d: 0100 1101 0110 1101 */
	1875	{illegal,0 }, /* 6e: 0100 1101 0110 1110 */
	1876	{illegal,0 }, /* 6f: 0100 1101 0110 1111 */
	1877
	1878	{illegal,0 }, /* 70: 0100 1101 0111 0000 */
	1879	{illegal,0 }, /* 71: 0100 1101 0111 0001 */
	1880	{illegal,0 }, /* 72: 0100 1101 0111 0010 */
	1881	{illegal,0 }, /* 73: 0100 1101 0111 0011 */
	1882	{illegal,0 }, /* 74: 0100 1101 0111 0100 */
	1883	{illegal,0 }, /* 75: 0100 1101 0111 0101 */
	1884	{illegal,0 }, /* 76: 0100 1101 0111 0110 */
	1885	{illegal,0 }, /* 77: 0100 1101 0111 0111 */
	1886	{illegal,0 }, /* 78: 0100 1101 0111 1000 */
	1887	{illegal,0 }, /* 79: 0100 1101 0111 1001 */
	1888	{illegal,0 }, /* 7a: 0100 1101 0111 1010 */
	1889	{illegal,0 }, /* 7b: 0100 1101 0111 1011 */
	1890	{illegal,0 }, /* 7c: 0100 1101 0111 1100 */
	1891	{illegal,0 }, /* 7d: 0100 1101 0111 1101 */
	1892	{illegal,0 }, /* 7e: 0100 1101 0111 1110 */
	1893	{illegal,0 }, /* 7f: 0100 1101 0111 1111 */
	1894
	1895	{illegal,0 }, /* 80: 0100 1101 1000 0000 */
	1896	{illegal,0 }, /* 81: 0100 1101 1000 0001 */
	1897	{illegal,0 }, /* 82: 0100 1101 1000 0010 */
	1898	{illegal,0 }, /* 83: 0100 1101 1000 0011 */
	1899	{illegal,0 }, /* 84: 0100 1101 1000 0100 */
	1900	{illegal,0 }, /* 85: 0100 1101 1000 0101 */
	1901	{illegal,0 }, /* 86: 0100 1101 1000 0110 */
	1902	{illegal,0 }, /* 87: 0100 1101 1000 0111 */
	1903	{illegal,0 }, /* 88: 0100 1101 1000 1000 */
	1904	{illegal,0 }, /* 89: 0100 1101 1000 1001 */
	1905	{illegal,0 }, /* 8a: 0100 1101 1000 1010 */
	1906	{illegal,0 }, /* 8b: 0100 1101 1000 1011 */
	1907	{illegal,0 }, /* 8c: 0100 1101 1000 1100 */
	1908	{illegal,0 }, /* 8d: 0100 1101 1000 1101 */
	1909	{illegal,0 }, /* 8e: 0100 1101 1000 1110 */
	1910	{illegal,0 }, /* 8f: 0100 1101 1000 1111 */
	1911
	1912	{illegal,0 }, /* 90: 0100 1101 1001 0000 */
	1913	{illegal,0 }, /* 91: 0100 1101 1001 0001 */
	1914	{illegal,0 }, /* 92: 0100 1101 1001 0010 */
	1915	{illegal,0 }, /* 93: 0100 1101 1001 0011 */
	1916	{illegal,0 }, /* 94: 0100 1101 1001 0100 */
	1917	{illegal,0 }, /* 95: 0100 1101 1001 0101 */
	1918	{illegal,0 }, /* 96: 0100 1101 1001 0110 */
	1919	{illegal,0 }, /* 97: 0100 1101 1001 0111 */
	1920	{illegal,0 }, /* 98: 0100 1101 1001 1000 */
	1921	{illegal,0 }, /* 99: 0100 1101 1001 1001 */
	1922	{illegal,0 }, /* 9a: 0100 1101 1001 1010 */
	1923	{illegal,0 }, /* 9b: 0100 1101 1001 1011 */
	1924	{illegal,0 }, /* 9c: 0100 1101 1001 1100 */
	1925	{illegal,0 }, /* 9d: 0100 1101 1001 1101 */
	1926	{illegal,0 }, /* 9e: 0100 1101 1001 1110 */
	1927	{illegal,0 }, /* 9f: 0100 1101 1001 1111 */
	1928
	1929	{illegal,0 }, /* a0: 0100 1101 1010 0000 */
	1930	{illegal,0 }, /* a1: 0100 1101 1010 0001 */
	1931	{illegal,0 }, /* a2: 0100 1101 1010 0010 */
	1932	{illegal,0 }, /* a3: 0100 1101 1010 0011 */
	1933	{illegal,0 }, /* a4: 0100 1101 1010 0100 */
	1934	{illegal,0 }, /* a5: 0100 1101 1010 0101 */
	1935	{illegal,0 }, /* a6: 0100 1101 1010 0110 */
	1936	{illegal,0 }, /* a7: 0100 1101 1010 0111 */
	1937	{illegal,0 }, /* a8: 0100 1101 1010 1000 */
	1938	{illegal,0 }, /* a9: 0100 1101 1010 1001 */
	1939	{illegal,0 }, /* aa: 0100 1101 1010 1010 */
	1940	{illegal,0 }, /* ab: 0100 1101 1010 1011 */
	1941	{illegal,0 }, /* ac: 0100 1101 1010 1100 */
	1942	{illegal,0 }, /* ad: 0100 1101 1010 1101 */
	1943	{illegal,0 }, /* ae: 0100 1101 1010 1110 */
	1944	{illegal,0 }, /* af: 0100 1101 1010 1111 */
	1945
	1946	{illegal,0 }, /* b0: 0100 1101 1011 0000 */
	1947	{illegal,0 }, /* b1: 0100 1101 1011 0001 */
	1948	{illegal,0 }, /* b2: 0100 1101 1011 0010 */
	1949	{illegal,0 }, /* b3: 0100 1101 1011 0011 */
	1950	{illegal,0 }, /* b4: 0100 1101 1011 0100 */
	1951	{illegal,0 }, /* b5: 0100 1101 1011 0101 */
	1952	{illegal,0 }, /* b6: 0100 1101 1011 0110 */
	1953	{illegal,0 }, /* b7: 0100 1101 1011 0111 */
	1954	{illegal,0 }, /* b8: 0100 1101 1011 1000 */
	1955	{illegal,0 }, /* b9: 0100 1101 1011 1001 */
	1956	{illegal,0 }, /* ba: 0100 1101 1011 1010 */
	1957	{illegal,0 }, /* bb: 0100 1101 1011 1011 */
	1958	{illegal,0 }, /* bc: 0100 1101 1011 1100 */
	1959	{illegal,0 }, /* bd: 0100 1101 1011 1101 */
	1960	{illegal,0 }, /* be: 0100 1101 1011 1110 */
	1961	{illegal,0 }, /* bf: 0100 1101 1011 1111 */
	1962
	1963	{MOV,"PA,A" }, /* c0: 0100 1101 1100 0000 */
	1964	{MOV,"PB,A" }, /* c1: 0100 1101 1100 0001 */
	1965	{MOV,"PC,A" }, /* c2: 0100 1101 1100 0010 */
	1966	{MOV,"PD,A" }, /* c3: 0100 1101 1100 0011 */
	1967	{illegal,0 }, /* c4: 0100 1101 1100 0100 */
	1968	{MOV,"PF,A" }, /* c5: 0100 1101 1100 0101 */
	1969	{MOV,"MKH,A" }, /* c6: 0100 1101 1100 0110 */
	1970	{MOV,"MKL,A" }, /* c7: 0100 1101 1100 0111 */
	1971	{illegal,0 }, /* c8: 0100 1101 1100 1000 */
	1972	{MOV,"SMH,A" }, /* c9: 0100 1101 1100 1001 */
	1973	{MOV,"SML,A" }, /* ca: 0100 1101 1100 1010 */
	1974	{MOV,"EOM,A" }, /* cb: 0100 1101 1100 1011 */
	1975	{MOV,"ETMM,A" }, /* cc: 0100 1101 1100 1100 */
	1976	{MOV,"TMM,A" }, /* cd: 0100 1101 1100 1101 */
	1977	{illegal,0 }, /* ce: 0100 1101 1100 1110 */
	1978	{illegal,0 }, /* cf: 0100 1101 1100 1111 */
	1979
	1980	{MOV,"MM,A" }, /* d0: 0100 1101 1101 0000 */
	1981	{MOV,"MCC,A" }, /* d1: 0100 1101 1101 0001 */
	1982	{MOV,"MA,A" }, /* d2: 0100 1101 1101 0010 */
	1983	{MOV,"MB,A" }, /* d3: 0100 1101 1101 0011 */
	1984	{MOV,"MC,A" }, /* d4: 0100 1101 1101 0100 */
	1985	{illegal,0 }, /* d5: 0100 1101 1101 0101 */
	1986	{illegal,0 }, /* d6: 0100 1101 1101 0110 */
	1987	{MOV,"MF,A" }, /* d7: 0100 1101 1101 0111 */
	1988	{MOV,"TXB,A" }, /* d8: 0100 1101 1101 1000 */
	1989	{illegal,0 }, /* d9: 0100 1101 1101 1001 */
	1990	{MOV,"TM0,A" }, /* da: 0100 1101 1101 1010 */
	1991	{MOV,"TM1,A" }, /* db: 0100 1101 1101 1011 */
	1992	{illegal,0 }, /* dc: 0100 1101 1101 1100 */
	1993	{illegal,0 }, /* dd: 0100 1101 1101 1101 */
	1994	{illegal,0 }, /* de: 0100 1101 1101 1110 */
	1995	{illegal,0 }, /* df: 0100 1101 1101 1111 */
	1996
	1997	{illegal,0 }, /* e0: 0100 1101 1110 0000 */
	1998	{illegal,0 }, /* e1: 0100 1101 1110 0001 */
	1999	{illegal,0 }, /* e2: 0100 1101 1110 0010 */
	2000	{illegal,0 }, /* e3: 0100 1101 1110 0011 */
	2001	{illegal,0 }, /* e4: 0100 1101 1110 0100 */
	2002	{MOV,"MT,A" }, /* e5: 0100 1101 1110 0101 / / 7807 */
	2003	{illegal,0 }, /* e6: 0100 1101 1110 0110 */
	2004	{illegal,0 }, /* e7: 0100 1101 1110 0111 */
	2005	{illegal,0 }, /* e8: 0100 1101 1110 1000 */
	2006	{illegal,0 }, /* e9: 0100 1101 1110 1001 */
	2007	{illegal,0 }, /* ea: 0100 1101 1110 1010 */
	2008	{illegal,0 }, /* eb: 0100 1101 1110 1011 */
	2009	{illegal,0 }, /* ec: 0100 1101 1110 1100 */
	2010	{illegal,0 }, /* ed: 0100 1101 1110 1101 */
	2011	{illegal,0 }, /* ee: 0100 1101 1110 1110 */
	2012	{illegal,0 }, /* ef: 0100 1101 1110 1111 */
	2013
	2014	{illegal,0 }, /* f0: 0100 1101 1111 0000 */
	2015	{illegal,0 }, /* f1: 0100 1101 1111 0001 */
	2016	{illegal,0 }, /* f2: 0100 1101 1111 0010 */
	2017	{illegal,0 }, /* f3: 0100 1101 1111 0011 */
	2018	{illegal,0 }, /* f4: 0100 1101 1111 0100 */
	2019	{illegal,0 }, /* f5: 0100 1101 1111 0101 */
	2020	{illegal,0 }, /* f6: 0100 1101 1111 0110 */
	2021	{illegal,0 }, /* f7: 0100 1101 1111 0111 */
	2022	{illegal,0 }, /* f8: 0100 1101 1111 1000 */
	2023	{illegal,0 }, /* f9: 0100 1101 1111 1001 */
	2024	{illegal,0 }, /* fa: 0100 1101 1111 1010 */
	2025	{illegal,0 }, /* fb: 0100 1101 1111 1011 */
	2026	{illegal,0 }, /* fc: 0100 1101 1111 1100 */
	2027	{illegal,0 }, /* fd: 0100 1101 1111 1101 */
	2028	{illegal,0 }, /* fe: 0100 1101 1111 1110 */
	2029	{illegal,0 } /* ff: 0100 1101 1111 1111 */
	2030	};
	2031
	2032	/* prefix 60 */
	2033	static const struct dasm_s dasm60[256] =
	2034	{
	2035	{illegal,0 }, /* 00: 0110 0000 0000 0000 */
	2036	{illegal,0 }, /* 01: 0110 0000 0000 0001 */
	2037	{illegal,0 }, /* 02: 0110 0000 0000 0010 */
	2038	{illegal,0 }, /* 03: 0110 0000 0000 0011 */
	2039	{illegal,0 }, /* 04: 0110 0000 0000 0100 */
	2040	{illegal,0 }, /* 05: 0110 0000 0000 0101 */
	2041	{illegal,0 }, /* 06: 0110 0000 0000 0110 */
	2042	{illegal,0 }, /* 07: 0110 0000 0000 0111 */
	2043	{ANA,"V,A" }, /* 08: 0110 0000 0000 1000 */
	2044	{ANA,"A,A" }, /* 09: 0110 0000 0000 1001 */
	2045	{ANA,"B,A" }, /* 0a: 0110 0000 0000 1010 */
	2046	{ANA,"C,A" }, /* 0b: 0110 0000 0000 1011 */
	2047	{ANA,"D,A" }, /* 0c: 0110 0000 0000 1100 */
	2048	{ANA,"E,A" }, /* 0d: 0110 0000 0000 1101 */
	2049	{ANA,"H,A" }, /* 0e: 0110 0000 0000 1110 */
	2050	{ANA,"L,A" }, /* 0f: 0110 0000 0000 1111 */
	2051
	2052	{XRA,"V,A" }, /* 10: 0110 0000 0001 0000 */
	2053	{XRA,"A,A" }, /* 11: 0110 0000 0001 0001 */
	2054	{XRA,"B,A" }, /* 12: 0110 0000 0001 0010 */
	2055	{XRA,"C,A" }, /* 13: 0110 0000 0001 0011 */
	2056	{XRA,"D,A" }, /* 14: 0110 0000 0001 0100 */
	2057	{XRA,"E,A" }, /* 15: 0110 0000 0001 0101 */
	2058	{XRA,"H,A" }, /* 16: 0110 0000 0001 0110 */
	2059	{XRA,"L,A" }, /* 17: 0110 0000 0001 0111 */
	2060	{ORA,"V,A" }, /* 18: 0110 0000 0001 1000 */
	2061	{ORA,"A,A" }, /* 19: 0110 0000 0001 1001 */
	2062	{ORA,"B,A" }, /* 1a: 0110 0000 0001 1010 */
	2063	{ORA,"C,A" }, /* 1b: 0110 0000 0001 1011 */
	2064	{ORA,"D,A" }, /* 1c: 0110 0000 0001 1100 */
	2065	{ORA,"E,A" }, /* 1d: 0110 0000 0001 1101 */
	2066	{ORA,"H,A" }, /* 1e: 0110 0000 0001 1110 */
	2067	{ORA,"L,A" }, /* 1f: 0110 0000 0001 1111 */
	2068
	2069	{ADDNC,"V,A" }, /* 20: 0110 0000 0010 0000 */
	2070	{ADDNC,"A,A" }, /* 21: 0110 0000 0010 0001 */
	2071	{ADDNC,"B,A" }, /* 22: 0110 0000 0010 0010 */
	2072	{ADDNC,"C,A" }, /* 23: 0110 0000 0010 0011 */
	2073	{ADDNC,"D,A" }, /* 24: 0110 0000 0010 0100 */
	2074	{ADDNC,"E,A" }, /* 25: 0110 0000 0010 0101 */
	2075	{ADDNC,"H,A" }, /* 26: 0110 0000 0010 0110 */
	2076	{ADDNC,"L,A" }, /* 27: 0110 0000 0010 0111 */
	2077	{GTA,"V,A" }, /* 28: 0110 0000 0010 1000 */
	2078	{GTA,"A,A" }, /* 29: 0110 0000 0010 1001 */
	2079	{GTA,"B,A" }, /* 2a: 0110 0000 0010 1010 */
	2080	{GTA,"C,A" }, /* 2b: 0110 0000 0010 1011 */
	2081	{GTA,"D,A" }, /* 2c: 0110 0000 0010 1100 */
	2082	{GTA,"E,A" }, /* 2d: 0110 0000 0010 1101 */
	2083	{GTA,"H,A" }, /* 2e: 0110 0000 0010 1110 */
	2084	{GTA,"L,A" }, /* 2f: 0110 0000 0010 1111 */
	2085
	2086	{SUBNB,"V,A" }, /* 30: 0110 0000 0011 0000 */
	2087	{SUBNB,"A,A" }, /* 31: 0110 0000 0011 0001 */
	2088	{SUBNB,"B,A" }, /* 32: 0110 0000 0011 0010 */
	2089	{SUBNB,"C,A" }, /* 33: 0110 0000 0011 0011 */
	2090	{SUBNB,"D,A" }, /* 34: 0110 0000 0011 0100 */
	2091	{SUBNB,"E,A" }, /* 35: 0110 0000 0011 0101 */
	2092	{SUBNB,"H,A" }, /* 36: 0110 0000 0011 0110 */
	2093	{SUBNB,"L,A" }, /* 37: 0110 0000 0011 0111 */
	2094	{LTA,"V,A" }, /* 38: 0110 0000 0011 1000 */
	2095	{LTA,"A,A" }, /* 39: 0110 0000 0011 1001 */
	2096	{LTA,"B,A" }, /* 3a: 0110 0000 0011 1010 */
	2097	{LTA,"C,A" }, /* 3b: 0110 0000 0011 1011 */
	2098	{LTA,"D,A" }, /* 3c: 0110 0000 0011 1100 */
	2099	{LTA,"E,A" }, /* 3d: 0110 0000 0011 1101 */
	2100	{LTA,"H,A" }, /* 3e: 0110 0000 0011 1110 */
	2101	{LTA,"L,A" }, /* 3f: 0110 0000 0011 1111 */
	2102
	2103	{ADD,"V,A" }, /* 40: 0110 0000 0100 0000 */
	2104	{ADD,"A,A" }, /* 41: 0110 0000 0100 0001 */
	2105	{ADD,"B,A" }, /* 42: 0110 0000 0100 0010 */
	2106	{ADD,"C,A" }, /* 43: 0110 0000 0100 0011 */
	2107	{ADD,"D,A" }, /* 44: 0110 0000 0100 0100 */
	2108	{ADD,"E,A" }, /* 45: 0110 0000 0100 0101 */
	2109	{ADD,"H,A" }, /* 46: 0110 0000 0100 0110 */
	2110	{ADD,"L,A" }, /* 47: 0110 0000 0100 0111 */
	2111	{illegal,0 }, /* 48: 0110 0000 0100 1000 */
	2112	{illegal,0 }, /* 49: 0110 0000 0100 1001 */
	2113	{illegal,0 }, /* 4a: 0110 0000 0100 1010 */
	2114	{illegal,0 }, /* 4b: 0110 0000 0100 1011 */
	2115	{illegal,0 }, /* 4c: 0110 0000 0100 1100 */
	2116	{illegal,0 }, /* 4d: 0110 0000 0100 1101 */
	2117	{illegal,0 }, /* 4e: 0110 0000 0100 1110 */
	2118	{illegal,0 }, /* 4f: 0110 0000 0100 1111 */
	2119
	2120	{ADC,"V,A" }, /* 50: 0110 0000 0101 0000 */
	2121	{ADC,"A,A" }, /* 51: 0110 0000 0101 0001 */
	2122	{ADC,"B,A" }, /* 52: 0110 0000 0101 0010 */
	2123	{ADC,"C,A" }, /* 53: 0110 0000 0101 0011 */
	2124	{ADC,"D,A" }, /* 54: 0110 0000 0101 0100 */
	2125	{ADC,"E,A" }, /* 55: 0110 0000 0101 0101 */
	2126	{ADC,"H,A" }, /* 56: 0110 0000 0101 0110 */
	2127	{ADC,"L,A" }, /* 57: 0110 0000 0101 0111 */
	2128	{illegal,0 }, /* 58: 0110 0000 0101 1000 */
	2129	{illegal,0 }, /* 59: 0110 0000 0101 1001 */
	2130	{illegal,0 }, /* 5a: 0110 0000 0101 1010 */
	2131	{illegal,0 }, /* 5b: 0110 0000 0101 1011 */
	2132	{illegal,0 }, /* 5c: 0110 0000 0101 1100 */
	2133	{illegal,0 }, /* 5d: 0110 0000 0101 1101 */
	2134	{illegal,0 }, /* 5e: 0110 0000 0101 1110 */
	2135	{illegal,0 }, /* 5f: 0110 0000 0101 1111 */
	2136
	2137	{SUB,"V,A" }, /* 60: 0110 0000 0110 0000 */
	2138	{SUB,"A,A" }, /* 61: 0110 0000 0110 0001 */
	2139	{SUB,"B,A" }, /* 62: 0110 0000 0110 0010 */
	2140	{SUB,"C,A" }, /* 63: 0110 0000 0110 0011 */
	2141	{SUB,"D,A" }, /* 64: 0110 0000 0110 0100 */
	2142	{SUB,"E,A" }, /* 65: 0110 0000 0110 0101 */
	2143	{SUB,"H,A" }, /* 66: 0110 0000 0110 0110 */
	2144	{SUB,"L,A" }, /* 67: 0110 0000 0110 0111 */
	2145	{NEA,"V,A" }, /* 68: 0110 0000 0110 1000 */
	2146	{NEA,"A,A" }, /* 69: 0110 0000 0110 1001 */
	2147	{NEA,"B,A" }, /* 6a: 0110 0000 0110 1010 */
	2148	{NEA,"C,A" }, /* 6b: 0110 0000 0110 1011 */
	2149	{NEA,"D,A" }, /* 6c: 0110 0000 0110 1100 */
	2150	{NEA,"E,A" }, /* 6d: 0110 0000 0110 1101 */
	2151	{NEA,"H,A" }, /* 6e: 0110 0000 0110 1110 */
	2152	{NEA,"L,A" }, /* 6f: 0110 0000 0110 1111 */
	2153
	2154	{SBB,"V,A" }, /* 70: 0110 0000 0111 0000 */
	2155	{SBB,"A,A" }, /* 71: 0110 0000 0111 0001 */
	2156	{SBB,"B,A" }, /* 72: 0110 0000 0111 0010 */
	2157	{SBB,"C,A" }, /* 73: 0110 0000 0111 0011 */
	2158	{SBB,"D,A" }, /* 74: 0110 0000 0111 0100 */
	2159	{SBB,"E,A" }, /* 75: 0110 0000 0111 0101 */
	2160	{SBB,"H,A" }, /* 76: 0110 0000 0111 0110 */
	2161	{SBB,"L,A" }, /* 77: 0110 0000 0111 0111 */
	2162	{EQA,"V,A" }, /* 78: 0110 0000 0111 1000 */
	2163	{EQA,"A,A" }, /* 79: 0110 0000 0111 1001 */
	2164	{EQA,"B,A" }, /* 7a: 0110 0000 0111 1010 */
	2165	{EQA,"C,A" }, /* 7b: 0110 0000 0111 1011 */
	2166	{EQA,"D,A" }, /* 7c: 0110 0000 0111 1100 */
	2167	{EQA,"E,A" }, /* 7d: 0110 0000 0111 1101 */
	2168	{EQA,"H,A" }, /* 7e: 0110 0000 0111 1110 */
	2169	{EQA,"L,A" }, /* 7f: 0110 0000 0111 1111 */
	2170
	2171	{illegal,0 }, /* 80: 0110 0000 1000 0000 */
	2172	{illegal,0 }, /* 81: 0110 0000 1000 0001 */
	2173	{illegal,0 }, /* 82: 0110 0000 1000 0010 */
	2174	{illegal,0 }, /* 83: 0110 0000 1000 0011 */
	2175	{illegal,0 }, /* 84: 0110 0000 1000 0100 */
	2176	{illegal,0 }, /* 85: 0110 0000 1000 0101 */
	2177	{illegal,0 }, /* 86: 0110 0000 1000 0110 */
	2178	{illegal,0 }, /* 87: 0110 0000 1000 0111 */
	2179	{ANA,"A,V" }, /* 88: 0110 0000 1000 1000 */
	2180	{ANA,"A,A" }, /* 89: 0110 0000 1000 1001 */
	2181	{ANA,"A,B" }, /* 8a: 0110 0000 1000 1010 */
	2182	{ANA,"A,C" }, /* 8b: 0110 0000 1000 1011 */
	2183	{ANA,"A,D" }, /* 8c: 0110 0000 1000 1100 */
	2184	{ANA,"A,E" }, /* 8d: 0110 0000 1000 1101 */
	2185	{ANA,"A,H" }, /* 8e: 0110 0000 1000 1110 */
	2186	{ANA,"A,L" }, /* 8f: 0110 0000 1000 1111 */
	2187
	2188	{XRA,"A,V" }, /* 90: 0110 0000 1001 0000 */
	2189	{XRA,"A,A" }, /* 91: 0110 0000 1001 0001 */
	2190	{XRA,"A,B" }, /* 92: 0110 0000 1001 0010 */
	2191	{XRA,"A,C" }, /* 93: 0110 0000 1001 0011 */
	2192	{XRA,"A,D" }, /* 94: 0110 0000 1001 0100 */
	2193	{XRA,"A,E" }, /* 95: 0110 0000 1001 0101 */
	2194	{XRA,"A,H" }, /* 96: 0110 0000 1001 0110 */
	2195	{XRA,"A,L" }, /* 97: 0110 0000 1001 0111 */
	2196	{ORA,"A,V" }, /* 98: 0110 0000 1001 1000 */
	2197	{ORA,"A,A" }, /* 99: 0110 0000 1001 1001 */
	2198	{ORA,"A,B" }, /* 9a: 0110 0000 1001 1010 */
	2199	{ORA,"A,C" }, /* 9b: 0110 0000 1001 1011 */
	2200	{ORA,"A,D" }, /* 9c: 0110 0000 1001 1100 */
	2201	{ORA,"A,E" }, /* 9d: 0110 0000 1001 1101 */
	2202	{ORA,"A,H" }, /* 9e: 0110 0000 1001 1110 */
	2203	{ORA,"A,L" }, /* 9f: 0110 0000 1001 1111 */
	2204
	2205	{ADDNC,"A,V" }, /* a0: 0110 0000 1010 0000 */
	2206	{ADDNC,"A,A" }, /* a1: 0110 0000 1010 0001 */
	2207	{ADDNC,"A,B" }, /* a2: 0110 0000 1010 0010 */
	2208	{ADDNC,"A,C" }, /* a3: 0110 0000 1010 0011 */
	2209	{ADDNC,"A,D" }, /* a4: 0110 0000 1010 0100 */
	2210	{ADDNC,"A,E" }, /* a5: 0110 0000 1010 0101 */
	2211	{ADDNC,"A,H" }, /* a6: 0110 0000 1010 0110 */
	2212	{ADDNC,"A,L" }, /* a7: 0110 0000 1010 0111 */
	2213	{GTA,"A,V" }, /* a8: 0110 0000 1010 1000 */
	2214	{GTA,"A,A" }, /* a9: 0110 0000 1010 1001 */
	2215	{GTA,"A,B" }, /* aa: 0110 0000 1010 1010 */
	2216	{GTA,"A,C" }, /* ab: 0110 0000 1010 1011 */
	2217	{GTA,"A,D" }, /* ac: 0110 0000 1010 1100 */
	2218	{GTA,"A,E" }, /* ad: 0110 0000 1010 1101 */
	2219	{GTA,"A,H" }, /* ae: 0110 0000 1010 1110 */
	2220	{GTA,"A,L" }, /* af: 0110 0000 1010 1111 */
	2221
	2222	{SUBNB,"A,V" }, /* b0: 0110 0000 1011 0000 */
	2223	{SUBNB,"A,A" }, /* b1: 0110 0000 1011 0001 */
	2224	{SUBNB,"A,B" }, /* b2: 0110 0000 1011 0010 */
	2225	{SUBNB,"A,C" }, /* b3: 0110 0000 1011 0011 */
	2226	{SUBNB,"A,D" }, /* b4: 0110 0000 1011 0100 */
	2227	{SUBNB,"A,E" }, /* b5: 0110 0000 1011 0101 */
	2228	{SUBNB,"A,H" }, /* b6: 0110 0000 1011 0110 */
	2229	{SUBNB,"A,L" }, /* b7: 0110 0000 1011 0111 */
	2230	{LTA,"A,V" }, /* b8: 0110 0000 1011 1000 */
	2231	{LTA,"A,A" }, /* b9: 0110 0000 1011 1001 */
	2232	{LTA,"A,B" }, /* ba: 0110 0000 1011 1010 */
	2233	{LTA,"A,C" }, /* bb: 0110 0000 1011 1011 */
	2234	{LTA,"A,D" }, /* bc: 0110 0000 1011 1100 */
	2235	{LTA,"A,E" }, /* bd: 0110 0000 1011 1101 */
	2236	{LTA,"A,H" }, /* be: 0110 0000 1011 1110 */
	2237	{LTA,"A,L" }, /* bf: 0110 0000 1011 1111 */
	2238
	2239	{ADD,"A,V" }, /* c0: 0110 0000 1100 0000 */
	2240	{ADD,"A,A" }, /* c1: 0110 0000 1100 0001 */
	2241	{ADD,"A,B" }, /* c2: 0110 0000 1100 0010 */
	2242	{ADD,"A,C" }, /* c3: 0110 0000 1100 0011 */
	2243	{ADD,"A,D" }, /* c4: 0110 0000 1100 0100 */
	2244	{ADD,"A,E" }, /* c5: 0110 0000 1100 0101 */
	2245	{ADD,"A,H" }, /* c6: 0110 0000 1100 0110 */
	2246	{ADD,"A,L" }, /* c7: 0110 0000 1100 0111 */
	2247	{ONA,"A,V" }, /* c8: 0110 0000 1100 1000 */
	2248	{ONA,"A,A" }, /* c9: 0110 0000 1100 1001 */
	2249	{ONA,"A,B" }, /* ca: 0110 0000 1100 1010 */
	2250	{ONA,"A,C" }, /* cb: 0110 0000 1100 1011 */
	2251	{ONA,"A,D" }, /* cc: 0110 0000 1100 1100 */
	2252	{ONA,"A,E" }, /* cd: 0110 0000 1100 1101 */
	2253	{ONA,"A,H" }, /* ce: 0110 0000 1100 1110 */
	2254	{ONA,"A,L" }, /* cf: 0110 0000 1100 1111 */
	2255
	2256	{ADC,"A,V" }, /* d0: 0110 0000 1101 0000 */
	2257	{ADC,"A,A" }, /* d1: 0110 0000 1101 0001 */
	2258	{ADC,"A,B" }, /* d2: 0110 0000 1101 0010 */
	2259	{ADC,"A,C" }, /* d3: 0110 0000 1101 0011 */
	2260	{ADC,"A,D" }, /* d4: 0110 0000 1101 0100 */
	2261	{ADC,"A,E" }, /* d5: 0110 0000 1101 0101 */
	2262	{ADC,"A,H" }, /* d6: 0110 0000 1101 0110 */
	2263	{ADC,"A,L" }, /* d7: 0110 0000 1101 0111 */
	2264	{OFFA,"A,V" }, /* d8: 0110 0000 1101 1000 */
	2265	{OFFA,"A,A" }, /* d9: 0110 0000 1101 1001 */
	2266	{OFFA,"A,B" }, /* da: 0110 0000 1101 1010 */
	2267	{OFFA,"A,C" }, /* db: 0110 0000 1101 1011 */
	2268	{OFFA,"A,D" }, /* dc: 0110 0000 1101 1100 */
	2269	{OFFA,"A,E" }, /* dd: 0110 0000 1101 1101 */
	2270	{OFFA,"A,H" }, /* de: 0110 0000 1101 1110 */
	2271	{OFFA,"A,L" }, /* df: 0110 0000 1101 1111 */
	2272
	2273	{SUB,"A,V" }, /* e0: 0110 0000 1110 0000 */
	2274	{SUB,"A,A" }, /* e1: 0110 0000 1110 0001 */
	2275	{SUB,"A,B" }, /* e2: 0110 0000 1110 0010 */
	2276	{SUB,"A,C" }, /* e3: 0110 0000 1110 0011 */
	2277	{SUB,"A,D" }, /* e4: 0110 0000 1110 0100 */
	2278	{SUB,"A,E" }, /* e5: 0110 0000 1110 0101 */
	2279	{SUB,"A,H" }, /* e6: 0110 0000 1110 0110 */
	2280	{SUB,"A,L" }, /* e7: 0110 0000 1110 0111 */
	2281	{NEA,"A,V" }, /* e8: 0110 0000 1110 1000 */
	2282	{NEA,"A,A" }, /* e9: 0110 0000 1110 1001 */
	2283	{NEA,"A,B" }, /* ea: 0110 0000 1110 1010 */
	2284	{NEA,"A,C" }, /* eb: 0110 0000 1110 1011 */
	2285	{NEA,"A,D" }, /* ec: 0110 0000 1110 1100 */
	2286	{NEA,"A,E" }, /* ed: 0110 0000 1110 1101 */
	2287	{NEA,"A,H" }, /* ee: 0110 0000 1110 1110 */
	2288	{NEA,"A,L" }, /* ef: 0110 0000 1110 1111 */
	2289
	2290	{SBB,"A,V" }, /* f0: 0110 0000 1111 0000 */
	2291	{SBB,"A,A" }, /* f1: 0110 0000 1111 0001 */
	2292	{SBB,"A,B" }, /* f2: 0110 0000 1111 0010 */
	2293	{SBB,"A,C" }, /* f3: 0110 0000 1111 0011 */
	2294	{SBB,"A,D" }, /* f4: 0110 0000 1111 0100 */
	2295	{SBB,"A,E" }, /* f5: 0110 0000 1111 0101 */
	2296	{SBB,"A,H" }, /* f6: 0110 0000 1111 0110 */
	2297	{SBB,"A,L" }, /* f7: 0110 0000 1111 0111 */
	2298	{EQA,"A,V" }, /* f8: 0110 0000 1111 1000 */
	2299	{EQA,"A,A" }, /* f9: 0110 0000 1111 1001 */
	2300	{EQA,"A,B" }, /* fa: 0110 0000 1111 1010 */
	2301	{EQA,"A,C" }, /* fb: 0110 0000 1111 1011 */
	2302	{EQA,"A,D" }, /* fc: 0110 0000 1111 1100 */
	2303	{EQA,"A,E" }, /* fd: 0110 0000 1111 1101 */
	2304	{EQA,"A,H" }, /* fe: 0110 0000 1111 1110 */
	2305	{EQA,"A,L" } /* ff: 0110 0000 1111 1111 */
	2306	};
	2307
	2308	/* prefix 64 */
	2309	static const struct dasm_s dasm64_7810[256] =
	2310	{
	2311	{MVI,"PA,%b" }, /* 00: 0110 0100 0000 0000 xxxx xxxx */
	2312	{MVI,"PB,%b" }, /* 01: 0110 0100 0000 0001 xxxx xxxx */
	2313	{MVI,"PC,%b" }, /* 02: 0110 0100 0000 0010 xxxx xxxx */
	2314	{MVI,"PD,%b" }, /* 03: 0110 0100 0000 0011 xxxx xxxx */
	2315	{illegal,0 }, /* 04: 0110 0100 0000 0100 xxxx xxxx */
	2316	{MVI,"PF,%b" }, /* 05: 0110 0100 0000 0101 xxxx xxxx */
	2317	{MVI,"MKH,%b" }, /* 06: 0110 0100 0000 0110 xxxx xxxx */
	2318	{MVI,"MKL,%b" }, /* 07: 0110 0100 0000 0111 xxxx xxxx */
	2319	{ANI,"PA,%b" }, /* 08: 0110 0100 0000 1000 xxxx xxxx */
	2320	{ANI,"PB,%b" }, /* 09: 0110 0100 0000 1001 xxxx xxxx */
	2321	{ANI,"PC,%b" }, /* 0a: 0110 0100 0000 1010 xxxx xxxx */
	2322	{ANI,"PD,%b" }, /* 0b: 0110 0100 0000 1011 xxxx xxxx */
	2323	{illegal,0 }, /* 0c: 0110 0100 0000 1100 xxxx xxxx */
	2324	{ANI,"PF,%b" }, /* 0d: 0110 0100 0000 1101 xxxx xxxx */
	2325	{ANI,"MKH,%b" }, /* 0e: 0110 0100 0000 1110 xxxx xxxx */
	2326	{ANI,"MKL,%b" }, /* 0f: 0110 0100 0000 1111 xxxx xxxx */
	2327
	2328	{XRI,"PA,%b" }, /* 10: 0110 0100 0001 0000 xxxx xxxx */
	2329	{XRI,"PB,%b" }, /* 11: 0110 0100 0001 0001 xxxx xxxx */
	2330	{XRI,"PC,%b" }, /* 12: 0110 0100 0001 0010 xxxx xxxx */
	2331	{XRI,"PD,%b" }, /* 13: 0110 0100 0001 0011 xxxx xxxx */
	2332	{illegal,0 }, /* 14: 0110 0100 0001 0100 xxxx xxxx */
	2333	{XRI,"PF,%b" }, /* 15: 0110 0100 0001 0101 xxxx xxxx */
	2334	{XRI,"MKH,%b" }, /* 16: 0110 0100 0001 0110 xxxx xxxx */
	2335	{XRI,"MKL,%b" }, /* 17: 0110 0100 0001 0111 xxxx xxxx */
	2336	{ORI,"PA,%b" }, /* 18: 0110 0100 0001 1000 xxxx xxxx */
	2337	{ORI,"PB,%b" }, /* 19: 0110 0100 0001 1001 xxxx xxxx */
	2338	{ORI,"PC,%b" }, /* 1a: 0110 0100 0001 1010 xxxx xxxx */
	2339	{ORI,"PD,%b" }, /* 1b: 0110 0100 0001 1011 xxxx xxxx */
	2340	{illegal,0 }, /* 1c: 0110 0100 0001 1100 xxxx xxxx */
	2341	{ORI,"PF,%b" }, /* 1d: 0110 0100 0001 1101 xxxx xxxx */
	2342	{ORI,"MKH,%b" }, /* 1e: 0110 0100 0001 1110 xxxx xxxx */
	2343	{ORI,"MKL,%b" }, /* 1f: 0110 0100 0001 1111 xxxx xxxx */
	2344
	2345	{ADINC,"PA,%b" }, /* 20: 0110 0100 0010 0000 xxxx xxxx */
	2346	{ADINC,"PB,%b" }, /* 21: 0110 0100 0010 0001 xxxx xxxx */
	2347	{ADINC,"PC,%b" }, /* 22: 0110 0100 0010 0010 xxxx xxxx */
	2348	{ADINC,"PD,%b" }, /* 23: 0110 0100 0010 0011 xxxx xxxx */
	2349	{illegal,0 }, /* 24: 0110 0100 0010 0100 xxxx xxxx */
	2350	{ADINC,"PF,%b" }, /* 25: 0110 0100 0010 0101 xxxx xxxx */
	2351	{ADINC,"MKH,%b" }, /* 26: 0110 0100 0010 0110 xxxx xxxx */
	2352	{ADINC,"MKL,%b" }, /* 27: 0110 0100 0010 0111 xxxx xxxx */
	2353	{GTI,"PA,%b" }, /* 28: 0110 0100 0010 1000 xxxx xxxx */
	2354	{GTI,"PB,%b" }, /* 29: 0110 0100 0010 1001 xxxx xxxx */
	2355	{GTI,"PC,%b" }, /* 2a: 0110 0100 0010 1010 xxxx xxxx */
	2356	{GTI,"PD,%b" }, /* 2b: 0110 0100 0010 1011 xxxx xxxx */
	2357	{illegal,0 }, /* 2c: 0110 0100 0010 1100 xxxx xxxx */
	2358	{GTI,"PF,%b" }, /* 2d: 0110 0100 0010 1101 xxxx xxxx */
	2359	{GTI,"MKH,%b" }, /* 2e: 0110 0100 0010 1110 xxxx xxxx */
	2360	{GTI,"MKL,%b" }, /* 2f: 0110 0100 0010 1111 xxxx xxxx */
	2361
	2362	{SUINB,"PA,%b" }, /* 30: 0110 0100 0011 0000 xxxx xxxx */
	2363	{SUINB,"PB,%b" }, /* 31: 0110 0100 0011 0001 xxxx xxxx */
	2364	{SUINB,"PC,%b" }, /* 32: 0110 0100 0011 0010 xxxx xxxx */
	2365	{SUINB,"PD,%b" }, /* 33: 0110 0100 0011 0011 xxxx xxxx */
	2366	{illegal,0 }, /* 34: 0110 0100 0011 0100 xxxx xxxx */
	2367	{SUINB,"PF,%b" }, /* 35: 0110 0100 0011 0101 xxxx xxxx */
	2368	{SUINB,"MKH,%b" }, /* 36: 0110 0100 0011 0110 xxxx xxxx */
	2369	{SUINB,"MKL,%b" }, /* 37: 0110 0100 0011 0111 xxxx xxxx */
	2370	{LTI,"PA,%b" }, /* 38: 0110 0100 0011 1000 xxxx xxxx */
	2371	{LTI,"PB,%b" }, /* 39: 0110 0100 0011 1001 xxxx xxxx */
	2372	{LTI,"PC,%b" }, /* 3a: 0110 0100 0011 1010 xxxx xxxx */
	2373	{LTI,"PD,%b" }, /* 3b: 0110 0100 0011 1011 xxxx xxxx */
	2374	{illegal,0 }, /* 3c: 0110 0100 0011 1100 xxxx xxxx */
	2375	{LTI,"PF,%b" }, /* 3d: 0110 0100 0011 1101 xxxx xxxx */
	2376	{LTI,"MKH,%b" }, /* 3e: 0110 0100 0011 1110 xxxx xxxx */
	2377	{LTI,"MKL,%b" }, /* 3f: 0110 0100 0011 1111 xxxx xxxx */
	2378
	2379	{ADI,"PA,%b" }, /* 40: 0110 0100 0100 0000 xxxx xxxx */
	2380	{ADI,"PB,%b" }, /* 41: 0110 0100 0100 0001 xxxx xxxx */
	2381	{ADI,"PC,%b" }, /* 42: 0110 0100 0100 0010 xxxx xxxx */
	2382	{ADI,"PD,%b" }, /* 43: 0110 0100 0100 0011 xxxx xxxx */
	2383	{illegal,0 }, /* 44: 0110 0100 0100 0100 xxxx xxxx */
	2384	{ADI,"PF,%b" }, /* 45: 0110 0100 0100 0101 xxxx xxxx */
	2385	{ADI,"MKH,%b" }, /* 46: 0110 0100 0100 0110 xxxx xxxx */
	2386	{ADI,"MKL,%b" }, /* 47: 0110 0100 0100 0111 xxxx xxxx */
	2387	{ONI,"PA,%b" }, /* 48: 0110 0100 0100 1000 xxxx xxxx */
	2388	{ONI,"PB,%b" }, /* 49: 0110 0100 0100 1001 xxxx xxxx */
	2389	{ONI,"PC,%b" }, /* 4a: 0110 0100 0100 1010 xxxx xxxx */
	2390	{ONI,"PD,%b" }, /* 4b: 0110 0100 0100 1011 xxxx xxxx */
	2391	{illegal,0 }, /* 4c: 0110 0100 0100 1100 xxxx xxxx */
	2392	{ONI,"PF,%b" }, /* 4d: 0110 0100 0100 1101 xxxx xxxx */
	2393	{ONI,"MKH,%b" }, /* 4e: 0110 0100 0100 1110 xxxx xxxx */
	2394	{ONI,"MKL,%b" }, /* 4f: 0110 0100 0100 1111 xxxx xxxx */
	2395
	2396	{ACI,"PA,%b" }, /* 50: 0110 0100 0101 0000 xxxx xxxx */
	2397	{ACI,"PB,%b" }, /* 51: 0110 0100 0101 0001 xxxx xxxx */
	2398	{ACI,"PC,%b" }, /* 52: 0110 0100 0101 0010 xxxx xxxx */
	2399	{ACI,"PD,%b" }, /* 53: 0110 0100 0101 0011 xxxx xxxx */
	2400	{illegal,0 }, /* 54: 0110 0100 0101 0100 xxxx xxxx */
	2401	{ACI,"PF,%b" }, /* 55: 0110 0100 0101 0101 xxxx xxxx */
	2402	{ACI,"MKH,%b" }, /* 56: 0110 0100 0101 0110 xxxx xxxx */
	2403	{ACI,"MKL,%b" }, /* 57: 0110 0100 0101 0111 xxxx xxxx */
	2404	{OFFI,"PA,%b" }, /* 58: 0110 0100 0101 1000 xxxx xxxx */
	2405	{OFFI,"PB,%b" }, /* 59: 0110 0100 0101 1001 xxxx xxxx */
	2406	{OFFI,"PC,%b" }, /* 5a: 0110 0100 0101 1010 xxxx xxxx */
	2407	{OFFI,"PD,%b" }, /* 5b: 0110 0100 0101 1011 xxxx xxxx */
	2408	{illegal,0 }, /* 5c: 0110 0100 0101 1100 xxxx xxxx */
	2409	{OFFI,"PF,%b" }, /* 5d: 0110 0100 0101 1101 xxxx xxxx */
	2410	{OFFI,"MKH,%b" }, /* 5e: 0110 0100 0101 1110 xxxx xxxx */
	2411	{OFFI,"MKL,%b" }, /* 5f: 0110 0100 0101 1111 xxxx xxxx */
	2412
	2413	{SUI,"PA,%b" }, /* 60: 0110 0100 0110 0000 xxxx xxxx */
	2414	{SUI,"PB,%b" }, /* 61: 0110 0100 0110 0001 xxxx xxxx */
	2415	{SUI,"PC,%b" }, /* 62: 0110 0100 0110 0010 xxxx xxxx */
	2416	{SUI,"PD,%b" }, /* 63: 0110 0100 0110 0011 xxxx xxxx */
	2417	{illegal,0 }, /* 64: 0110 0100 0110 0100 xxxx xxxx */
	2418	{SUI,"PF,%b" }, /* 65: 0110 0100 0110 0101 xxxx xxxx */
	2419	{SUI,"MKH,%b" }, /* 66: 0110 0100 0110 0110 xxxx xxxx */
	2420	{SUI,"MKL,%b" }, /* 67: 0110 0100 0110 0111 xxxx xxxx */
	2421	{NEI,"PA,%b" }, /* 68: 0110 0100 0110 1000 xxxx xxxx */
	2422	{NEI,"PB,%b" }, /* 69: 0110 0100 0110 1001 xxxx xxxx */
	2423	{NEI,"PC,%b" }, /* 6a: 0110 0100 0110 1010 xxxx xxxx */
	2424	{NEI,"PD,%b" }, /* 6b: 0110 0100 0110 1011 xxxx xxxx */
	2425	{illegal,0 }, /* 6c: 0110 0100 0110 1100 xxxx xxxx */
	2426	{NEI,"PF,%b" }, /* 6d: 0110 0100 0110 1101 xxxx xxxx */
	2427	{NEI,"MKH,%b" }, /* 6e: 0110 0100 0110 1110 xxxx xxxx */
	2428	{NEI,"MKL,%b" }, /* 6f: 0110 0100 0110 1111 xxxx xxxx */
	2429
	2430	{SBI,"PA,%b" }, /* 70: 0110 0100 0111 0000 xxxx xxxx */
	2431	{SBI,"PB,%b" }, /* 71: 0110 0100 0111 0001 xxxx xxxx */
	2432	{SBI,"PC,%b" }, /* 72: 0110 0100 0111 0010 xxxx xxxx */
	2433	{SBI,"PD,%b" }, /* 73: 0110 0100 0111 0011 xxxx xxxx */
	2434	{illegal,0 }, /* 74: 0110 0100 0111 0100 xxxx xxxx */
	2435	{SBI,"PF,%b" }, /* 75: 0110 0100 0111 0101 xxxx xxxx */
	2436	{SBI,"MKH,%b" }, /* 76: 0110 0100 0111 0110 xxxx xxxx */
	2437	{SBI,"MKL,%b" }, /* 77: 0110 0100 0111 0111 xxxx xxxx */
	2438	{EQI,"PA,%b" }, /* 78: 0110 0100 0111 1000 xxxx xxxx */
	2439	{EQI,"PB,%b" }, /* 79: 0110 0100 0111 1001 xxxx xxxx */
	2440	{EQI,"PC,%b" }, /* 7a: 0110 0100 0111 1010 xxxx xxxx */
	2441	{EQI,"PD,%b" }, /* 7b: 0110 0100 0111 1011 xxxx xxxx */
	2442	{illegal,0 }, /* 7c: 0110 0100 0111 1100 xxxx xxxx */
	2443	{EQI,"PF,%b" }, /* 7d: 0110 0100 0111 1101 xxxx xxxx */
	2444	{EQI,"MKH,%b" }, /* 7e: 0110 0100 0111 1110 xxxx xxxx */
	2445	{EQI,"MKL,%b" }, /* 7f: 0110 0100 0111 1111 xxxx xxxx */
	2446
	2447	{MVI,"ANM,%b" }, /* 80: 0110 0100 1000 0000 xxxx xxxx / / 7810 */
	2448	{MVI,"SMH,%b" }, /* 81: 0110 0100 1000 0001 xxxx xxxx */
	2449	{illegal,0 }, /* 82: 0110 0100 1000 0010 xxxx xxxx */
	2450	{MVI,"EOM,%b" }, /* 83: 0110 0100 1000 0011 xxxx xxxx */
	2451	{illegal,0 }, /* 84: 0110 0100 1000 0100 xxxx xxxx */
	2452	{MVI,"TMM,%b" }, /* 85: 0110 0100 1000 0101 xxxx xxxx */
	2453	{illegal,0 }, /* 86: 0110 0100 1000 0110 xxxx xxxx */
	2454	{illegal,0 }, /* 87: 0110 0100 1000 0111 xxxx xxxx */
	2455	{ANI,"ANM,%b" }, /* 88: 0110 0100 1000 1000 xxxx xxxx / / 7810 */
	2456	{ANI,"SMH,%b" }, /* 89: 0110 0100 1000 1001 xxxx xxxx */
	2457	{illegal,0 }, /* 8a: 0110 0100 1000 1010 xxxx xxxx */
	2458	{ANI,"EOM,%b" }, /* 8b: 0110 0100 1000 1011 xxxx xxxx */
	2459	{illegal,0 }, /* 8c: 0110 0100 1000 1100 xxxx xxxx */
	2460	{ANI,"TMM,%b" }, /* 8d: 0110 0100 1000 1101 xxxx xxxx */
	2461	{illegal,0 }, /* 8e: 0110 0100 1000 1110 xxxx xxxx */
	2462	{illegal,0 }, /* 8f: 0110 0100 1000 1111 xxxx xxxx */
	2463
	2464	{XRI,"ANM,%b" }, /* 90: 0110 0100 1001 0000 xxxx xxxx / / 7810 */
	2465	{XRI,"SMH,%b" }, /* 91: 0110 0100 1001 0001 xxxx xxxx */
	2466	{illegal,0 }, /* 92: 0110 0100 1001 0010 xxxx xxxx */
	2467	{XRI,"EOM,%b" }, /* 93: 0110 0100 1001 0011 xxxx xxxx */
	2468	{illegal,0 }, /* 94: 0110 0100 1001 0100 xxxx xxxx */
	2469	{XRI,"TMM,%b" }, /* 95: 0110 0100 1001 0101 xxxx xxxx */
	2470	{illegal,0 }, /* 96: 0110 0100 1001 0110 xxxx xxxx */
	2471	{illegal,0 }, /* 97: 0110 0100 1001 0111 xxxx xxxx */
	2472	{ORI,"ANM,%b" }, /* 98: 0110 0100 1001 1000 xxxx xxxx / / 7810 */
	2473	{ORI,"SMH,%b" }, /* 99: 0110 0100 1001 1001 xxxx xxxx */
	2474	{illegal,0 }, /* 9a: 0110 0100 1001 1010 xxxx xxxx */
	2475	{ORI,"EOM,%b" }, /* 9b: 0110 0100 1001 1011 xxxx xxxx */
	2476	{illegal,0 }, /* 9c: 0110 0100 1001 1100 xxxx xxxx */
	2477	{ORI,"TMM,%b" }, /* 9d: 0110 0100 1001 1101 xxxx xxxx */
	2478	{illegal,0 }, /* 9e: 0110 0100 1001 1110 xxxx xxxx */
	2479	{illegal,0 }, /* 9f: 0110 0100 1001 1111 xxxx xxxx */
	2480
	2481	{ADINC,"ANM,%b" }, /* a0: 0110 0100 1010 0000 xxxx xxxx / / 7810 */
	2482	{ADINC,"SMH,%b" }, /* a1: 0110 0100 1010 0001 xxxx xxxx */
	2483	{illegal,0 }, /* a2: 0110 0100 1010 0010 xxxx xxxx */
	2484	{ADINC,"EOM,%b" }, /* a3: 0110 0100 1010 0011 xxxx xxxx */
	2485	{illegal,0 }, /* a4: 0110 0100 1010 0100 xxxx xxxx */
	2486	{ADINC,"TMM,%b" }, /* a5: 0110 0100 1010 0101 xxxx xxxx */
	2487	{illegal,0 }, /* a6: 0110 0100 1010 0110 xxxx xxxx */
	2488	{illegal,0 }, /* a7: 0110 0100 1010 0111 xxxx xxxx */
	2489	{GTI,"ANM,%b" }, /* a8: 0110 0100 1010 1000 xxxx xxxx / / 7810 */
	2490	{GTI,"SMH,%b" }, /* a9: 0110 0100 1010 1001 xxxx xxxx */
	2491	{illegal,0 }, /* aa: 0110 0100 1010 1010 xxxx xxxx */
	2492	{GTI,"EOM,%b" }, /* ab: 0110 0100 1010 1011 xxxx xxxx */
	2493	{illegal,0 }, /* ac: 0110 0100 1010 1100 xxxx xxxx */
	2494	{GTI,"TMM,%b" }, /* ad: 0110 0100 1010 1101 xxxx xxxx */
	2495	{illegal,0 }, /* ae: 0110 0100 1010 1110 xxxx xxxx */
	2496	{illegal,0 }, /* af: 0110 0100 1010 1111 xxxx xxxx */
	2497
	2498	{SUINB,"ANM,%b" }, /* b0: 0110 0100 1011 0000 xxxx xxxx / / 7810 */
	2499	{SUINB,"SMH,%b" }, /* b1: 0110 0100 1011 0001 xxxx xxxx */
	2500	{illegal,0 }, /* b2: 0110 0100 1011 0010 xxxx xxxx */
	2501	{SUINB,"EOM,%b" }, /* b3: 0110 0100 1011 0011 xxxx xxxx */
	2502	{illegal,0 }, /* b4: 0110 0100 1011 0100 xxxx xxxx */
	2503	{SUINB,"TMM,%b" }, /* b5: 0110 0100 1011 0101 xxxx xxxx */
	2504	{illegal,0 }, /* b6: 0110 0100 1011 0110 xxxx xxxx */
	2505	{illegal,0 }, /* b7: 0110 0100 1011 0111 xxxx xxxx */
	2506	{LTI,"ANM,%b" }, /* b8: 0110 0100 1011 1000 xxxx xxxx / / 7810 */
	2507	{LTI,"SMH,%b" }, /* b9: 0110 0100 1011 1001 xxxx xxxx */
	2508	{illegal,0 }, /* ba: 0110 0100 1011 1010 xxxx xxxx */
	2509	{LTI,"EOM,%b" }, /* bb: 0110 0100 1011 1011 xxxx xxxx */
	2510	{illegal,0 }, /* bc: 0110 0100 1011 1100 xxxx xxxx */
	2511	{LTI,"TMM,%b" }, /* bd: 0110 0100 1011 1101 xxxx xxxx */
	2512	{illegal,0 }, /* be: 0110 0100 1011 1110 xxxx xxxx */
	2513	{illegal,0 }, /* bf: 0110 0100 1011 1111 xxxx xxxx */
	2514
	2515	{ADI,"ANM,%b" }, /* c0: 0110 0100 1100 0000 xxxx xxxx / / 7810 */
	2516	{ADI,"SMH,%b" }, /* c1: 0110 0100 1100 0001 xxxx xxxx */
	2517	{illegal,0 }, /* c2: 0110 0100 1100 0010 xxxx xxxx */
	2518	{ADI,"EOM,%b" }, /* c3: 0110 0100 1100 0011 xxxx xxxx */
	2519	{illegal,0 }, /* c4: 0110 0100 1100 0100 xxxx xxxx */
	2520	{ADI,"TMM,%b" }, /* c5: 0110 0100 1100 0101 xxxx xxxx */
	2521	{illegal,0 }, /* c6: 0110 0100 1100 0110 xxxx xxxx */
	2522	{illegal,0 }, /* c7: 0110 0100 1100 0111 xxxx xxxx */
	2523	{ONI,"ANM,%b" }, /* c8: 0110 0100 1100 1000 xxxx xxxx / / 7810 */
	2524	{ONI,"SMH,%b" }, /* c9: 0110 0100 1100 1001 xxxx xxxx */
	2525	{illegal,0 }, /* ca: 0110 0100 1100 1010 xxxx xxxx */
	2526	{ONI,"EOM,%b" }, /* cb: 0110 0100 1100 1011 xxxx xxxx */
	2527	{illegal,0 }, /* cc: 0110 0100 1100 1100 xxxx xxxx */
	2528	{ONI,"TMM,%b" }, /* cd: 0110 0100 1100 1101 xxxx xxxx */
	2529	{illegal,0 }, /* ce: 0110 0100 1100 1110 xxxx xxxx */
	2530	{illegal,0 }, /* cf: 0110 0100 1100 1111 xxxx xxxx */
	2531
	2532	{ACI,"ANM,%b" }, /* d0: 0110 0100 1101 0000 xxxx xxxx / / 7810 */
	2533	{ACI,"SMH,%b" }, /* d1: 0110 0100 1101 0001 xxxx xxxx */
	2534	{illegal,0 }, /* d2: 0110 0100 1101 0010 xxxx xxxx */
	2535	{ACI,"EOM,%b" }, /* d3: 0110 0100 1101 0011 xxxx xxxx */
	2536	{illegal,0 }, /* d4: 0110 0100 1101 0100 xxxx xxxx */
	2537	{ACI,"TMM,%b" }, /* d5: 0110 0100 1101 0101 xxxx xxxx */
	2538	{illegal,0 }, /* d6: 0110 0100 1101 0110 xxxx xxxx */
	2539	{illegal,0 }, /* d7: 0110 0100 1101 0111 xxxx xxxx */
	2540	{OFFI,"ANM,%b" }, /* d8: 0110 0100 1101 1000 xxxx xxxx / / 7810 */
	2541	{OFFI,"SMH,%b" }, /* d9: 0110 0100 1101 1001 xxxx xxxx */
	2542	{illegal,0 }, /* da: 0110 0100 1101 1010 xxxx xxxx */
	2543	{OFFI,"EOM,%b" }, /* db: 0110 0100 1101 1011 xxxx xxxx */
	2544	{illegal,0 }, /* dc: 0110 0100 1101 1100 xxxx xxxx */
	2545	{OFFI,"TMM,%b" }, /* dd: 0110 0100 1101 1101 xxxx xxxx */
	2546	{illegal,0 }, /* de: 0110 0100 1101 1110 xxxx xxxx */
	2547	{illegal,0 }, /* df: 0110 0100 1101 1111 xxxx xxxx */
	2548
	2549	{SUI,"ANM,%b" }, /* e0: 0110 0100 1110 0000 xxxx xxxx / / 7810 */
	2550	{SUI,"SMH,%b" }, /* e1: 0110 0100 1110 0001 xxxx xxxx */
	2551	{illegal,0 }, /* e2: 0110 0100 1110 0010 xxxx xxxx */
	2552	{SUI,"EOM,%b" }, /* e3: 0110 0100 1110 0011 xxxx xxxx */
	2553	{illegal,0 }, /* e4: 0110 0100 1110 0100 xxxx xxxx */
	2554	{SUI,"TMM,%b" }, /* e5: 0110 0100 1110 0101 xxxx xxxx */
	2555	{illegal,0 }, /* e6: 0110 0100 1110 0110 xxxx xxxx */
	2556	{illegal,0 }, /* e7: 0110 0100 1110 0111 xxxx xxxx */
	2557	{NEI,"ANM,%b" }, /* e8: 0110 0100 1110 1000 xxxx xxxx / / 7810 */
	2558	{NEI,"SMH,%b" }, /* e9: 0110 0100 1110 1001 xxxx xxxx */
	2559	{illegal,0 }, /* ea: 0110 0100 1110 1010 xxxx xxxx */
	2560	{NEI,"EOM,%b" }, /* eb: 0110 0100 1110 1011 xxxx xxxx */
	2561	{illegal,0 }, /* ec: 0110 0100 1110 1100 xxxx xxxx */
	2562	{NEI,"TMM,%b" }, /* ed: 0110 0100 1110 1101 xxxx xxxx */
	2563	{illegal,0 }, /* ee: 0110 0100 1110 1110 xxxx xxxx */
	2564	{illegal,0 }, /* ef: 0110 0100 1110 1111 xxxx xxxx */
	2565
	2566	{SBI,"ANM,%b" }, /* f0: 0110 0100 1111 0000 xxxx xxxx / / 7810 */
	2567	{SBI,"SMH,%b" }, /* f1: 0110 0100 1111 0001 xxxx xxxx */
	2568	{illegal,0 }, /* f2: 0110 0100 1111 0010 xxxx xxxx */
	2569	{SBI,"EOM,%b" }, /* f3: 0110 0100 1111 0011 xxxx xxxx */
	2570	{illegal,0 }, /* f4: 0110 0100 1111 0100 xxxx xxxx */
	2571	{SBI,"TMM,%b" }, /* f5: 0110 0100 1111 0101 xxxx xxxx */
	2572	{illegal,0 }, /* f6: 0110 0100 1111 0110 xxxx xxxx */
	2573	{illegal,0 }, /* f7: 0110 0100 1111 0111 xxxx xxxx */
	2574	{EQI,"ANM,%b" }, /* f8: 0110 0100 1111 1000 xxxx xxxx / / 7810 */
	2575	{EQI,"SMH,%b" }, /* f9: 0110 0100 1111 1001 xxxx xxxx */
	2576	{illegal,0 }, /* fa: 0110 0100 1111 1010 xxxx xxxx */
	2577	{EQI,"EOM,%b" }, /* fb: 0110 0100 1111 1011 xxxx xxxx */
	2578	{illegal,0 }, /* fc: 0110 0100 1111 1100 xxxx xxxx */
	2579	{EQI,"TMM,%b" }, /* fd: 0110 0100 1111 1101 xxxx xxxx */
	2580	{illegal,0 }, /* fe: 0110 0100 1111 1110 xxxx xxxx */
	2581	{illegal,0 } /* ff: 0110 0100 1111 1111 xxxx xxxx */
	2582	};
	2583
	2584	static const struct dasm_s dasm64_7807[256] =
	2585	{
	2586	{MVI,"PA,%b" }, /* 00: 0110 0100 0000 0000 xxxx xxxx */
	2587	{MVI,"PB,%b" }, /* 01: 0110 0100 0000 0001 xxxx xxxx */
	2588	{MVI,"PC,%b" }, /* 02: 0110 0100 0000 0010 xxxx xxxx */
	2589	{MVI,"PD,%b" }, /* 03: 0110 0100 0000 0011 xxxx xxxx */
	2590	{illegal,0 }, /* 04: 0110 0100 0000 0100 xxxx xxxx */
	2591	{MVI,"PF,%b" }, /* 05: 0110 0100 0000 0101 xxxx xxxx */
	2592	{MVI,"MKH,%b" }, /* 06: 0110 0100 0000 0110 xxxx xxxx */
	2593	{MVI,"MKL,%b" }, /* 07: 0110 0100 0000 0111 xxxx xxxx */
	2594	{ANI,"PA,%b" }, /* 08: 0110 0100 0000 1000 xxxx xxxx */
	2595	{ANI,"PB,%b" }, /* 09: 0110 0100 0000 1001 xxxx xxxx */
	2596	{ANI,"PC,%b" }, /* 0a: 0110 0100 0000 1010 xxxx xxxx */
	2597	{ANI,"PD,%b" }, /* 0b: 0110 0100 0000 1011 xxxx xxxx */
	2598	{illegal,0 }, /* 0c: 0110 0100 0000 1100 xxxx xxxx */
	2599	{ANI,"PF,%b" }, /* 0d: 0110 0100 0000 1101 xxxx xxxx */
	2600	{ANI,"MKH,%b" }, /* 0e: 0110 0100 0000 1110 xxxx xxxx */
	2601	{ANI,"MKL,%b" }, /* 0f: 0110 0100 0000 1111 xxxx xxxx */
	2602
	2603	{XRI,"PA,%b" }, /* 10: 0110 0100 0001 0000 xxxx xxxx */
	2604	{XRI,"PB,%b" }, /* 11: 0110 0100 0001 0001 xxxx xxxx */
	2605	{XRI,"PC,%b" }, /* 12: 0110 0100 0001 0010 xxxx xxxx */
	2606	{XRI,"PD,%b" }, /* 13: 0110 0100 0001 0011 xxxx xxxx */
	2607	{illegal,0 }, /* 14: 0110 0100 0001 0100 xxxx xxxx */
	2608	{XRI,"PF,%b" }, /* 15: 0110 0100 0001 0101 xxxx xxxx */
	2609	{XRI,"MKH,%b" }, /* 16: 0110 0100 0001 0110 xxxx xxxx */
	2610	{XRI,"MKL,%b" }, /* 17: 0110 0100 0001 0111 xxxx xxxx */
	2611	{ORI,"PA,%b" }, /* 18: 0110 0100 0001 1000 xxxx xxxx */
	2612	{ORI,"PB,%b" }, /* 19: 0110 0100 0001 1001 xxxx xxxx */
	2613	{ORI,"PC,%b" }, /* 1a: 0110 0100 0001 1010 xxxx xxxx */
	2614	{ORI,"PD,%b" }, /* 1b: 0110 0100 0001 1011 xxxx xxxx */
	2615	{illegal,0 }, /* 1c: 0110 0100 0001 1100 xxxx xxxx */
	2616	{ORI,"PF,%b" }, /* 1d: 0110 0100 0001 1101 xxxx xxxx */
	2617	{ORI,"MKH,%b" }, /* 1e: 0110 0100 0001 1110 xxxx xxxx */
	2618	{ORI,"MKL,%b" }, /* 1f: 0110 0100 0001 1111 xxxx xxxx */
	2619
	2620	{ADINC,"PA,%b" }, /* 20: 0110 0100 0010 0000 xxxx xxxx */
	2621	{ADINC,"PB,%b" }, /* 21: 0110 0100 0010 0001 xxxx xxxx */
	2622	{ADINC,"PC,%b" }, /* 22: 0110 0100 0010 0010 xxxx xxxx */
	2623	{ADINC,"PD,%b" }, /* 23: 0110 0100 0010 0011 xxxx xxxx */
	2624	{illegal,0 }, /* 24: 0110 0100 0010 0100 xxxx xxxx */
	2625	{ADINC,"PF,%b" }, /* 25: 0110 0100 0010 0101 xxxx xxxx */
	2626	{ADINC,"MKH,%b" }, /* 26: 0110 0100 0010 0110 xxxx xxxx */
	2627	{ADINC,"MKL,%b" }, /* 27: 0110 0100 0010 0111 xxxx xxxx */
	2628	{GTI,"PA,%b" }, /* 28: 0110 0100 0010 1000 xxxx xxxx */
	2629	{GTI,"PB,%b" }, /* 29: 0110 0100 0010 1001 xxxx xxxx */
	2630	{GTI,"PC,%b" }, /* 2a: 0110 0100 0010 1010 xxxx xxxx */
	2631	{GTI,"PD,%b" }, /* 2b: 0110 0100 0010 1011 xxxx xxxx */
	2632	{illegal,0 }, /* 2c: 0110 0100 0010 1100 xxxx xxxx */
	2633	{GTI,"PF,%b" }, /* 2d: 0110 0100 0010 1101 xxxx xxxx */
	2634	{GTI,"MKH,%b" }, /* 2e: 0110 0100 0010 1110 xxxx xxxx */
	2635	{GTI,"MKL,%b" }, /* 2f: 0110 0100 0010 1111 xxxx xxxx */
	2636
	2637	{SUINB,"PA,%b" }, /* 30: 0110 0100 0011 0000 xxxx xxxx */
	2638	{SUINB,"PB,%b" }, /* 31: 0110 0100 0011 0001 xxxx xxxx */
	2639	{SUINB,"PC,%b" }, /* 32: 0110 0100 0011 0010 xxxx xxxx */
	2640	{SUINB,"PD,%b" }, /* 33: 0110 0100 0011 0011 xxxx xxxx */
	2641	{illegal,0 }, /* 34: 0110 0100 0011 0100 xxxx xxxx */
	2642	{SUINB,"PF,%b" }, /* 35: 0110 0100 0011 0101 xxxx xxxx */
	2643	{SUINB,"MKH,%b" }, /* 36: 0110 0100 0011 0110 xxxx xxxx */
	2644	{SUINB,"MKL,%b" }, /* 37: 0110 0100 0011 0111 xxxx xxxx */
	2645	{LTI,"PA,%b" }, /* 38: 0110 0100 0011 1000 xxxx xxxx */
	2646	{LTI,"PB,%b" }, /* 39: 0110 0100 0011 1001 xxxx xxxx */
	2647	{LTI,"PC,%b" }, /* 3a: 0110 0100 0011 1010 xxxx xxxx */
	2648	{LTI,"PD,%b" }, /* 3b: 0110 0100 0011 1011 xxxx xxxx */
	2649	{illegal,0 }, /* 3c: 0110 0100 0011 1100 xxxx xxxx */
	2650	{LTI,"PF,%b" }, /* 3d: 0110 0100 0011 1101 xxxx xxxx */
	2651	{LTI,"MKH,%b" }, /* 3e: 0110 0100 0011 1110 xxxx xxxx */
	2652	{LTI,"MKL,%b" }, /* 3f: 0110 0100 0011 1111 xxxx xxxx */
	2653
	2654	{ADI,"PA,%b" }, /* 40: 0110 0100 0100 0000 xxxx xxxx */
	2655	{ADI,"PB,%b" }, /* 41: 0110 0100 0100 0001 xxxx xxxx */
	2656	{ADI,"PC,%b" }, /* 42: 0110 0100 0100 0010 xxxx xxxx */
	2657	{ADI,"PD,%b" }, /* 43: 0110 0100 0100 0011 xxxx xxxx */
	2658	{illegal,0 }, /* 44: 0110 0100 0100 0100 xxxx xxxx */
	2659	{ADI,"PF,%b" }, /* 45: 0110 0100 0100 0101 xxxx xxxx */
	2660	{ADI,"MKH,%b" }, /* 46: 0110 0100 0100 0110 xxxx xxxx */
	2661	{ADI,"MKL,%b" }, /* 47: 0110 0100 0100 0111 xxxx xxxx */
	2662	{ONI,"PA,%b" }, /* 48: 0110 0100 0100 1000 xxxx xxxx */
	2663	{ONI,"PB,%b" }, /* 49: 0110 0100 0100 1001 xxxx xxxx */
	2664	{ONI,"PC,%b" }, /* 4a: 0110 0100 0100 1010 xxxx xxxx */
	2665	{ONI,"PD,%b" }, /* 4b: 0110 0100 0100 1011 xxxx xxxx */
	2666	{illegal,0 }, /* 4c: 0110 0100 0100 1100 xxxx xxxx */
	2667	{ONI,"PF,%b" }, /* 4d: 0110 0100 0100 1101 xxxx xxxx */
	2668	{ONI,"MKH,%b" }, /* 4e: 0110 0100 0100 1110 xxxx xxxx */
	2669	{ONI,"MKL,%b" }, /* 4f: 0110 0100 0100 1111 xxxx xxxx */
	2670
	2671	{ACI,"PA,%b" }, /* 50: 0110 0100 0101 0000 xxxx xxxx */
	2672	{ACI,"PB,%b" }, /* 51: 0110 0100 0101 0001 xxxx xxxx */
	2673	{ACI,"PC,%b" }, /* 52: 0110 0100 0101 0010 xxxx xxxx */
	2674	{ACI,"PD,%b" }, /* 53: 0110 0100 0101 0011 xxxx xxxx */
	2675	{illegal,0 }, /* 54: 0110 0100 0101 0100 xxxx xxxx */
	2676	{ACI,"PF,%b" }, /* 55: 0110 0100 0101 0101 xxxx xxxx */
	2677	{ACI,"MKH,%b" }, /* 56: 0110 0100 0101 0110 xxxx xxxx */
	2678	{ACI,"MKL,%b" }, /* 57: 0110 0100 0101 0111 xxxx xxxx */
	2679	{OFFI,"PA,%b" }, /* 58: 0110 0100 0101 1000 xxxx xxxx */
	2680	{OFFI,"PB,%b" }, /* 59: 0110 0100 0101 1001 xxxx xxxx */
	2681	{OFFI,"PC,%b" }, /* 5a: 0110 0100 0101 1010 xxxx xxxx */
	2682	{OFFI,"PD,%b" }, /* 5b: 0110 0100 0101 1011 xxxx xxxx */
	2683	{illegal,0 }, /* 5c: 0110 0100 0101 1100 xxxx xxxx */
	2684	{OFFI,"PF,%b" }, /* 5d: 0110 0100 0101 1101 xxxx xxxx */
	2685	{OFFI,"MKH,%b" }, /* 5e: 0110 0100 0101 1110 xxxx xxxx */
	2686	{OFFI,"MKL,%b" }, /* 5f: 0110 0100 0101 1111 xxxx xxxx */
	2687
	2688	{SUI,"PA,%b" }, /* 60: 0110 0100 0110 0000 xxxx xxxx */
	2689	{SUI,"PB,%b" }, /* 61: 0110 0100 0110 0001 xxxx xxxx */
	2690	{SUI,"PC,%b" }, /* 62: 0110 0100 0110 0010 xxxx xxxx */
	2691	{SUI,"PD,%b" }, /* 63: 0110 0100 0110 0011 xxxx xxxx */
	2692	{illegal,0 }, /* 64: 0110 0100 0110 0100 xxxx xxxx */
	2693	{SUI,"PF,%b" }, /* 65: 0110 0100 0110 0101 xxxx xxxx */
	2694	{SUI,"MKH,%b" }, /* 66: 0110 0100 0110 0110 xxxx xxxx */
	2695	{SUI,"MKL,%b" }, /* 67: 0110 0100 0110 0111 xxxx xxxx */
	2696	{NEI,"PA,%b" }, /* 68: 0110 0100 0110 1000 xxxx xxxx */
	2697	{NEI,"PB,%b" }, /* 69: 0110 0100 0110 1001 xxxx xxxx */
	2698	{NEI,"PC,%b" }, /* 6a: 0110 0100 0110 1010 xxxx xxxx */
	2699	{NEI,"PD,%b" }, /* 6b: 0110 0100 0110 1011 xxxx xxxx */
	2700	{illegal,0 }, /* 6c: 0110 0100 0110 1100 xxxx xxxx */
	2701	{NEI,"PF,%b" }, /* 6d: 0110 0100 0110 1101 xxxx xxxx */
	2702	{NEI,"MKH,%b" }, /* 6e: 0110 0100 0110 1110 xxxx xxxx */
	2703	{NEI,"MKL,%b" }, /* 6f: 0110 0100 0110 1111 xxxx xxxx */
	2704
	2705	{SBI,"PA,%b" }, /* 70: 0110 0100 0111 0000 xxxx xxxx */
	2706	{SBI,"PB,%b" }, /* 71: 0110 0100 0111 0001 xxxx xxxx */
	2707	{SBI,"PC,%b" }, /* 72: 0110 0100 0111 0010 xxxx xxxx */
	2708	{SBI,"PD,%b" }, /* 73: 0110 0100 0111 0011 xxxx xxxx */
	2709	{illegal,0 }, /* 74: 0110 0100 0111 0100 xxxx xxxx */
	2710	{SBI,"PF,%b" }, /* 75: 0110 0100 0111 0101 xxxx xxxx */
	2711	{SBI,"MKH,%b" }, /* 76: 0110 0100 0111 0110 xxxx xxxx */
	2712	{SBI,"MKL,%b" }, /* 77: 0110 0100 0111 0111 xxxx xxxx */
	2713	{EQI,"PA,%b" }, /* 78: 0110 0100 0111 1000 xxxx xxxx */
	2714	{EQI,"PB,%b" }, /* 79: 0110 0100 0111 1001 xxxx xxxx */
	2715	{EQI,"PC,%b" }, /* 7a: 0110 0100 0111 1010 xxxx xxxx */
	2716	{EQI,"PD,%b" }, /* 7b: 0110 0100 0111 1011 xxxx xxxx */
	2717	{illegal,0 }, /* 7c: 0110 0100 0111 1100 xxxx xxxx */
	2718	{EQI,"PF,%b" }, /* 7d: 0110 0100 0111 1101 xxxx xxxx */
	2719	{EQI,"MKH,%b" }, /* 7e: 0110 0100 0111 1110 xxxx xxxx */
	2720	{EQI,"MKL,%b" }, /* 7f: 0110 0100 0111 1111 xxxx xxxx */
	2721
	2722	{illegal,0 }, /* 80: 0110 0100 1000 0000 xxxx xxxx */
	2723	{MVI,"SMH,%b" }, /* 81: 0110 0100 1000 0001 xxxx xxxx */
	2724	{illegal,0 }, /* 82: 0110 0100 1000 0010 xxxx xxxx */
	2725	{MVI,"EOM,%b" }, /* 83: 0110 0100 1000 0011 xxxx xxxx */
	2726	{illegal,0 }, /* 84: 0110 0100 1000 0100 xxxx xxxx */
	2727	{MVI,"TMM,%b" }, /* 85: 0110 0100 1000 0101 xxxx xxxx */
	2728	{illegal,0 }, /* 86: 0110 0100 1000 0110 xxxx xxxx */
	2729	{illegal,0 }, /* 87: 0110 0100 1000 0111 xxxx xxxx */
	2730	{illegal,0 }, /* 88: 0110 0100 1000 1000 xxxx xxxx */
	2731	{ANI,"SMH,%b" }, /* 89: 0110 0100 1000 1001 xxxx xxxx */
	2732	{illegal,0 }, /* 8a: 0110 0100 1000 1010 xxxx xxxx */
	2733	{ANI,"EOM,%b" }, /* 8b: 0110 0100 1000 1011 xxxx xxxx */
	2734	{illegal,0 }, /* 8c: 0110 0100 1000 1100 xxxx xxxx */
	2735	{ANI,"TMM,%b" }, /* 8d: 0110 0100 1000 1101 xxxx xxxx */
	2736	{illegal,0 }, /* 8e: 0110 0100 1000 1110 xxxx xxxx */
	2737	{illegal,0 }, /* 8f: 0110 0100 1000 1111 xxxx xxxx */
	2738
	2739	{illegal,0 }, /* 90: 0110 0100 1001 0000 xxxx xxxx */
	2740	{XRI,"SMH,%b" }, /* 91: 0110 0100 1001 0001 xxxx xxxx */
	2741	{illegal,0 }, /* 92: 0110 0100 1001 0010 xxxx xxxx */
	2742	{XRI,"EOM,%b" }, /* 93: 0110 0100 1001 0011 xxxx xxxx */
	2743	{illegal,0 }, /* 94: 0110 0100 1001 0100 xxxx xxxx */
	2744	{XRI,"TMM,%b" }, /* 95: 0110 0100 1001 0101 xxxx xxxx */
	2745	{illegal,0 }, /* 96: 0110 0100 1001 0110 xxxx xxxx */
	2746	{illegal,0 }, /* 97: 0110 0100 1001 0111 xxxx xxxx */
	2747	{illegal,0 }, /* 98: 0110 0100 1001 1000 xxxx xxxx */
	2748	{ORI,"SMH,%b" }, /* 99: 0110 0100 1001 1001 xxxx xxxx */
	2749	{illegal,0 }, /* 9a: 0110 0100 1001 1010 xxxx xxxx */
	2750	{ORI,"EOM,%b" }, /* 9b: 0110 0100 1001 1011 xxxx xxxx */
	2751	{illegal,0 }, /* 9c: 0110 0100 1001 1100 xxxx xxxx */
	2752	{ORI,"TMM,%b" }, /* 9d: 0110 0100 1001 1101 xxxx xxxx */
	2753	{illegal,0 }, /* 9e: 0110 0100 1001 1110 xxxx xxxx */
	2754	{illegal,0 }, /* 9f: 0110 0100 1001 1111 xxxx xxxx */
	2755
	2756	{illegal,0 }, /* a0: 0110 0100 1010 0000 xxxx xxxx */
	2757	{ADINC,"SMH,%b" }, /* a1: 0110 0100 1010 0001 xxxx xxxx */
	2758	{illegal,0 }, /* a2: 0110 0100 1010 0010 xxxx xxxx */
	2759	{ADINC,"EOM,%b" }, /* a3: 0110 0100 1010 0011 xxxx xxxx */
	2760	{illegal,0 }, /* a4: 0110 0100 1010 0100 xxxx xxxx */
	2761	{ADINC,"TMM,%b" }, /* a5: 0110 0100 1010 0101 xxxx xxxx */
	2762	{illegal,0 }, /* a6: 0110 0100 1010 0110 xxxx xxxx */
	2763	{illegal,0 }, /* a7: 0110 0100 1010 0111 xxxx xxxx */
	2764	{illegal,0 }, /* a8: 0110 0100 1010 1000 xxxx xxxx */
	2765	{GTI,"SMH,%b" }, /* a9: 0110 0100 1010 1001 xxxx xxxx */
	2766	{illegal,0 }, /* aa: 0110 0100 1010 1010 xxxx xxxx */
	2767	{GTI,"EOM,%b" }, /* ab: 0110 0100 1010 1011 xxxx xxxx */
	2768	{illegal,0 }, /* ac: 0110 0100 1010 1100 xxxx xxxx */
	2769	{GTI,"TMM,%b" }, /* ad: 0110 0100 1010 1101 xxxx xxxx */
	2770	{GTI,"PT,%b" }, /* ae: 0110 0100 1010 1110 xxxx xxxx */
	2771	{illegal,0 }, /* af: 0110 0100 1010 1111 xxxx xxxx */
	2772
	2773	{illegal,0 }, /* b0: 0110 0100 1011 0000 xxxx xxxx */
	2774	{SUINB,"SMH,%b" }, /* b1: 0110 0100 1011 0001 xxxx xxxx */
	2775	{illegal,0 }, /* b2: 0110 0100 1011 0010 xxxx xxxx */
	2776	{SUINB,"EOM,%b" }, /* b3: 0110 0100 1011 0011 xxxx xxxx */
	2777	{illegal,0 }, /* b4: 0110 0100 1011 0100 xxxx xxxx */
	2778	{SUINB,"TMM,%b" }, /* b5: 0110 0100 1011 0101 xxxx xxxx */
	2779	{illegal,0 }, /* b6: 0110 0100 1011 0110 xxxx xxxx */
	2780	{illegal,0 }, /* b7: 0110 0100 1011 0111 xxxx xxxx */
	2781	{illegal,0 }, /* b8: 0110 0100 1011 1000 xxxx xxxx */
	2782	{LTI,"SMH,%b" }, /* b9: 0110 0100 1011 1001 xxxx xxxx */
	2783	{illegal,0 }, /* ba: 0110 0100 1011 1010 xxxx xxxx */
	2784	{LTI,"EOM,%b" }, /* bb: 0110 0100 1011 1011 xxxx xxxx */
	2785	{illegal,0 }, /* bc: 0110 0100 1011 1100 xxxx xxxx */
	2786	{LTI,"TMM,%b" }, /* bd: 0110 0100 1011 1101 xxxx xxxx */
	2787	{LTI,"PT,%b" }, /* be: 0110 0100 1011 1110 xxxx xxxx */
	2788	{illegal,0 }, /* bf: 0110 0100 1011 1111 xxxx xxxx */
	2789
	2790	{illegal,0 }, /* c0: 0110 0100 1100 0000 xxxx xxxx */
	2791	{ADI,"SMH,%b" }, /* c1: 0110 0100 1100 0001 xxxx xxxx */
	2792	{illegal,0 }, /* c2: 0110 0100 1100 0010 xxxx xxxx */
	2793	{ADI,"EOM,%b" }, /* c3: 0110 0100 1100 0011 xxxx xxxx */
	2794	{illegal,0 }, /* c4: 0110 0100 1100 0100 xxxx xxxx */
	2795	{ADI,"TMM,%b" }, /* c5: 0110 0100 1100 0101 xxxx xxxx */
	2796	{illegal,0 }, /* c6: 0110 0100 1100 0110 xxxx xxxx */
	2797	{illegal,0 }, /* c7: 0110 0100 1100 0111 xxxx xxxx */
	2798	{illegal,0 }, /* c8: 0110 0100 1100 1000 xxxx xxxx */
	2799	{ONI,"SMH,%b" }, /* c9: 0110 0100 1100 1001 xxxx xxxx */
	2800	{illegal,0 }, /* ca: 0110 0100 1100 1010 xxxx xxxx */
	2801	{ONI,"EOM,%b" }, /* cb: 0110 0100 1100 1011 xxxx xxxx */
	2802	{illegal,0 }, /* cc: 0110 0100 1100 1100 xxxx xxxx */
	2803	{ONI,"TMM,%b" }, /* cd: 0110 0100 1100 1101 xxxx xxxx */
	2804	{ONI,"PT,%b" }, /* ce: 0110 0100 1100 1110 xxxx xxxx */
	2805	{illegal,0 }, /* cf: 0110 0100 1100 1111 xxxx xxxx */
	2806
	2807	{illegal,0 }, /* d0: 0110 0100 1101 0000 xxxx xxxx */
	2808	{ACI,"SMH,%b" }, /* d1: 0110 0100 1101 0001 xxxx xxxx */
	2809	{illegal,0 }, /* d2: 0110 0100 1101 0010 xxxx xxxx */
	2810	{ACI,"EOM,%b" }, /* d3: 0110 0100 1101 0011 xxxx xxxx */
	2811	{illegal,0 }, /* d4: 0110 0100 1101 0100 xxxx xxxx */
	2812	{ACI,"TMM,%b" }, /* d5: 0110 0100 1101 0101 xxxx xxxx */
	2813	{illegal,0 }, /* d6: 0110 0100 1101 0110 xxxx xxxx */
	2814	{illegal,0 }, /* d7: 0110 0100 1101 0111 xxxx xxxx */
	2815	{illegal,0 }, /* d8: 0110 0100 1101 1000 xxxx xxxx */
	2816	{OFFI,"SMH,%b" }, /* d9: 0110 0100 1101 1001 xxxx xxxx */
	2817	{illegal,0 }, /* da: 0110 0100 1101 1010 xxxx xxxx */
	2818	{OFFI,"EOM,%b" }, /* db: 0110 0100 1101 1011 xxxx xxxx */
	2819	{illegal,0 }, /* dc: 0110 0100 1101 1100 xxxx xxxx */
	2820	{OFFI,"TMM,%b" }, /* dd: 0110 0100 1101 1101 xxxx xxxx */
	2821	{OFFI,"PT,%b" }, /* de: 0110 0100 1101 1110 xxxx xxxx */
	2822	{illegal,0 }, /* df: 0110 0100 1101 1111 xxxx xxxx */
	2823
	2824	{illegal,0 }, /* e0: 0110 0100 1110 0000 xxxx xxxx */
	2825	{SUI,"SMH,%b" }, /* e1: 0110 0100 1110 0001 xxxx xxxx */
	2826	{illegal,0 }, /* e2: 0110 0100 1110 0010 xxxx xxxx */
	2827	{SUI,"EOM,%b" }, /* e3: 0110 0100 1110 0011 xxxx xxxx */
	2828	{illegal,0 }, /* e4: 0110 0100 1110 0100 xxxx xxxx */
	2829	{SUI,"TMM,%b" }, /* e5: 0110 0100 1110 0101 xxxx xxxx */
	2830	{illegal,0 }, /* e6: 0110 0100 1110 0110 xxxx xxxx */
	2831	{illegal,0 }, /* e7: 0110 0100 1110 0111 xxxx xxxx */
	2832	{illegal,0 }, /* e8: 0110 0100 1110 1000 xxxx xxxx */
	2833	{NEI,"SMH,%b" }, /* e9: 0110 0100 1110 1001 xxxx xxxx */
	2834	{illegal,0 }, /* ea: 0110 0100 1110 1010 xxxx xxxx */
	2835	{NEI,"EOM,%b" }, /* eb: 0110 0100 1110 1011 xxxx xxxx */
	2836	{illegal,0 }, /* ec: 0110 0100 1110 1100 xxxx xxxx */
	2837	{NEI,"TMM,%b" }, /* ed: 0110 0100 1110 1101 xxxx xxxx */
	2838	{NEI,"PT,%b" }, /* ee: 0110 0100 1110 1110 xxxx xxxx */
	2839	{illegal,0 }, /* ef: 0110 0100 1110 1111 xxxx xxxx */
	2840
	2841	{illegal,0 }, /* f0: 0110 0100 1111 0000 xxxx xxxx */
	2842	{SBI,"SMH,%b" }, /* f1: 0110 0100 1111 0001 xxxx xxxx */
	2843	{illegal,0 }, /* f2: 0110 0100 1111 0010 xxxx xxxx */
	2844	{SBI,"EOM,%b" }, /* f3: 0110 0100 1111 0011 xxxx xxxx */
	2845	{illegal,0 }, /* f4: 0110 0100 1111 0100 xxxx xxxx */
	2846	{SBI,"TMM,%b" }, /* f5: 0110 0100 1111 0101 xxxx xxxx */
	2847	{illegal,0 }, /* f6: 0110 0100 1111 0110 xxxx xxxx */
	2848	{illegal,0 }, /* f7: 0110 0100 1111 0111 xxxx xxxx */
	2849	{illegal,0 }, /* f8: 0110 0100 1111 1000 xxxx xxxx */
	2850	{EQI,"SMH,%b" }, /* f9: 0110 0100 1111 1001 xxxx xxxx */
	2851	{illegal,0 }, /* fa: 0110 0100 1111 1010 xxxx xxxx */
	2852	{EQI,"EOM,%b" }, /* fb: 0110 0100 1111 1011 xxxx xxxx */
	2853	{illegal,0 }, /* fc: 0110 0100 1111 1100 xxxx xxxx */
	2854	{EQI,"TMM,%b" }, /* fd: 0110 0100 1111 1101 xxxx xxxx */
	2855	{EQI,"PT,%b" }, /* fe: 0110 0100 1111 1110 xxxx xxxx */
	2856	{illegal,0 } /* ff: 0110 0100 1111 1111 xxxx xxxx */
	2857	};
	2858
	2859	/* prefix 70 */
	2860	static const struct dasm_s dasm70[256] =
	2861	{
	2862	{illegal,0 }, /* 00: 0111 0000 0000 0000 */
	2863	{illegal,0 }, /* 01: 0111 0000 0000 0001 */
	2864	{illegal,0 }, /* 02: 0111 0000 0000 0010 */
	2865	{illegal,0 }, /* 03: 0111 0000 0000 0011 */
	2866	{illegal,0 }, /* 04: 0111 0000 0000 0100 */
	2867	{illegal,0 }, /* 05: 0111 0000 0000 0101 */
	2868	{illegal,0 }, /* 06: 0111 0000 0000 0110 */
	2869	{illegal,0 }, /* 07: 0111 0000 0000 0111 */
	2870	{illegal,0 }, /* 08: 0111 0000 0000 1000 */
	2871	{illegal,0 }, /* 09: 0111 0000 0000 1001 */
	2872	{illegal,0 }, /* 0a: 0111 0000 0000 1010 */
	2873	{illegal,0 }, /* 0b: 0111 0000 0000 1011 */
	2874	{illegal,0 }, /* 0c: 0111 0000 0000 1100 */
	2875	{illegal,0 }, /* 0d: 0111 0000 0000 1101 */
	2876	{SSPD,"%w" }, /* 0e: 0111 0000 0000 1110 llll llll hhhh hhhh */
	2877	{LSPD,"%w" }, /* 0f: 0111 0000 0000 1111 llll llll hhhh hhhh */
	2878
	2879	{illegal,0 }, /* 10: 0111 0000 0001 0000 */
	2880	{illegal,0 }, /* 11: 0111 0000 0001 0001 */
	2881	{illegal,0 }, /* 12: 0111 0000 0001 0010 */
	2882	{illegal,0 }, /* 13: 0111 0000 0001 0011 */
	2883	{illegal,0 }, /* 14: 0111 0000 0001 0100 */
	2884	{illegal,0 }, /* 15: 0111 0000 0001 0101 */
	2885	{illegal,0 }, /* 16: 0111 0000 0001 0110 */
	2886	{illegal,0 }, /* 17: 0111 0000 0001 0111 */
	2887	{illegal,0 }, /* 18: 0111 0000 0001 1000 */
	2888	{illegal,0 }, /* 19: 0111 0000 0001 1001 */
	2889	{illegal,0 }, /* 1a: 0111 0000 0001 1010 */
	2890	{illegal,0 }, /* 1b: 0111 0000 0001 1011 */
	2891	{illegal,0 }, /* 1c: 0111 0000 0001 1100 */
	2892	{illegal,0 }, /* 1d: 0111 0000 0001 1101 */
	2893	{SBCD,"%w" }, /* 1e: 0111 0000 0001 1110 llll llll hhhh hhhh */
	2894	{LBCD,"%w" }, /* 1f: 0111 0000 0001 1111 llll llll hhhh hhhh */
	2895
	2896	{illegal,0 }, /* 20: 0111 0000 0010 0000 */
	2897	{illegal,0 }, /* 21: 0111 0000 0010 0001 */
	2898	{illegal,0 }, /* 22: 0111 0000 0010 0010 */
	2899	{illegal,0 }, /* 23: 0111 0000 0010 0011 */
	2900	{illegal,0 }, /* 24: 0111 0000 0010 0100 */
	2901	{illegal,0 }, /* 25: 0111 0000 0010 0101 */
	2902	{illegal,0 }, /* 26: 0111 0000 0010 0110 */
	2903	{illegal,0 }, /* 27: 0111 0000 0010 0111 */
	2904	{illegal,0 }, /* 28: 0111 0000 0010 1000 */
	2905	{illegal,0 }, /* 29: 0111 0000 0010 1001 */
	2906	{illegal,0 }, /* 2a: 0111 0000 0010 1010 */
	2907	{illegal,0 }, /* 2b: 0111 0000 0010 1011 */
	2908	{illegal,0 }, /* 2c: 0111 0000 0010 1100 */
	2909	{illegal,0 }, /* 2d: 0111 0000 0010 1101 */
	2910	{SDED,"%w" }, /* 2e: 0111 0000 0010 1110 llll llll hhhh hhhh */
	2911	{LDED,"%w" }, /* 2f: 0111 0000 0010 1111 llll llll hhhh hhhh */
	2912
	2913	{illegal,0 }, /* 30: 0111 0000 0011 0000 */
	2914	{illegal,0 }, /* 31: 0111 0000 0011 0001 */
	2915	{illegal,0 }, /* 32: 0111 0000 0011 0010 */
	2916	{illegal,0 }, /* 33: 0111 0000 0011 0011 */
	2917	{illegal,0 }, /* 34: 0111 0000 0011 0100 */
	2918	{illegal,0 }, /* 35: 0111 0000 0011 0101 */
	2919	{illegal,0 }, /* 36: 0111 0000 0011 0110 */
	2920	{illegal,0 }, /* 37: 0111 0000 0011 0111 */
	2921	{illegal,0 }, /* 38: 0111 0000 0011 1000 */
	2922	{illegal,0 }, /* 39: 0111 0000 0011 1001 */
	2923	{illegal,0 }, /* 3a: 0111 0000 0011 1010 */
	2924	{illegal,0 }, /* 3b: 0111 0000 0011 1011 */
	2925	{illegal,0 }, /* 3c: 0111 0000 0011 1100 */
	2926	{illegal,0 }, /* 3d: 0111 0000 0011 1101 */
	2927	{SHLD,"%w" }, /* 3e: 0111 0000 0011 1110 llll llll hhhh hhhh */
	2928	{LHLD,"%w" }, /* 3f: 0111 0000 0011 1111 llll llll hhhh hhhh */
	2929
	2930	{EADD,"EA,V" }, /* 40: 0111 0000 0100 0000 */
	2931	{EADD,"EA,A" }, /* 41: 0111 0000 0100 0001 */
	2932	{EADD,"EA,B" }, /* 42: 0111 0000 0100 0010 */
	2933	{EADD,"EA,C" }, /* 43: 0111 0000 0100 0011 */
	2934	{illegal,0 }, /* 44: 0111 0000 0100 0100 */
	2935	{illegal,0 }, /* 45: 0111 0000 0100 0101 */
	2936	{illegal,0 }, /* 46: 0111 0000 0100 0110 */
	2937	{illegal,0 }, /* 47: 0111 0000 0100 0111 */
	2938	{illegal,0 }, /* 48: 0111 0000 0100 1000 */
	2939	{illegal,0 }, /* 49: 0111 0000 0100 1001 */
	2940	{illegal,0 }, /* 4a: 0111 0000 0100 1010 */
	2941	{illegal,0 }, /* 4b: 0111 0000 0100 1011 */
	2942	{illegal,0 }, /* 4c: 0111 0000 0100 1100 */
	2943	{illegal,0 }, /* 4d: 0111 0000 0100 1101 */
	2944	{illegal,0 }, /* 4e: 0111 0000 0100 1110 */
	2945	{illegal,0 }, /* 4f: 0111 0000 0100 1111 */
	2946
	2947	{illegal,0 }, /* 50: 0111 0000 0101 0000 */
	2948	{illegal,0 }, /* 51: 0111 0000 0101 0001 */
	2949	{illegal,0 }, /* 52: 0111 0000 0101 0010 */
	2950	{illegal,0 }, /* 53: 0111 0000 0101 0011 */
	2951	{illegal,0 }, /* 54: 0111 0000 0101 0100 */
	2952	{illegal,0 }, /* 55: 0111 0000 0101 0101 */
	2953	{illegal,0 }, /* 56: 0111 0000 0101 0110 */
	2954	{illegal,0 }, /* 57: 0111 0000 0101 0111 */
	2955	{illegal,0 }, /* 58: 0111 0000 0101 1000 */
	2956	{illegal,0 }, /* 59: 0111 0000 0101 1001 */
	2957	{illegal,0 }, /* 5a: 0111 0000 0101 1010 */
	2958	{illegal,0 }, /* 5b: 0111 0000 0101 1011 */
	2959	{illegal,0 }, /* 5c: 0111 0000 0101 1100 */
	2960	{illegal,0 }, /* 5d: 0111 0000 0101 1101 */
	2961	{illegal,0 }, /* 5e: 0111 0000 0101 1110 */
	2962	{illegal,0 }, /* 5f: 0111 0000 0101 1111 */
	2963
	2964	{ESUB,"EA,V" }, /* 60: 0111 0000 0110 0000 */
	2965	{ESUB,"EA,A" }, /* 61: 0111 0000 0110 0001 */
	2966	{ESUB,"EA,B" }, /* 62: 0111 0000 0110 0010 */
	2967	{ESUB,"EA,C" }, /* 63: 0111 0000 0110 0011 */
	2968	{illegal,0 }, /* 64: 0111 0000 0110 0100 */
	2969	{illegal,0 }, /* 65: 0111 0000 0110 0101 */
	2970	{illegal,0 }, /* 66: 0111 0000 0110 0110 */
	2971	{illegal,0 }, /* 67: 0111 0000 0110 0111 */
	2972	{MOV,"V,(%w)" }, /* 68: 0111 0000 0110 1000 llll llll hhhh hhhh */
	2973	{MOV,"A,(%w)" }, /* 69: 0111 0000 0110 1001 llll llll hhhh hhhh */
	2974	{MOV,"B,(%w)" }, /* 6a: 0111 0000 0110 1010 llll llll hhhh hhhh */
	2975	{MOV,"C,(%w)" }, /* 6b: 0111 0000 0110 1011 llll llll hhhh hhhh */
	2976	{MOV,"D,(%w)" }, /* 6c: 0111 0000 0110 1100 llll llll hhhh hhhh */
	2977	{MOV,"E,(%w)" }, /* 6d: 0111 0000 0110 1101 llll llll hhhh hhhh */
	2978	{MOV,"H,(%w)" }, /* 6e: 0111 0000 0110 1110 llll llll hhhh hhhh */
	2979	{MOV,"L,(%w)" }, /* 6f: 0111 0000 0110 1111 llll llll hhhh hhhh */
	2980
	2981	{illegal,0 }, /* 70: 0111 0000 0111 0000 */
	2982	{illegal,0 }, /* 71: 0111 0000 0111 0001 */
	2983	{illegal,0 }, /* 72: 0111 0000 0111 0010 */
	2984	{illegal,0 }, /* 73: 0111 0000 0111 0011 */
	2985	{illegal,0 }, /* 74: 0111 0000 0111 0100 */
	2986	{illegal,0 }, /* 75: 0111 0000 0111 0101 */
	2987	{illegal,0 }, /* 76: 0111 0000 0111 0110 */
	2988	{illegal,0 }, /* 77: 0111 0000 0111 0111 */
	2989	{MOV,"(%w),V" }, /* 78: 0111 0000 0111 1000 llll llll hhhh hhhh */
	2990	{MOV,"(%w),A" }, /* 79: 0111 0000 0111 1001 llll llll hhhh hhhh */
	2991	{MOV,"(%w),B" }, /* 7a: 0111 0000 0111 1010 llll llll hhhh hhhh */
	2992	{MOV,"(%w),C" }, /* 7b: 0111 0000 0111 1011 llll llll hhhh hhhh */
	2993	{MOV,"(%w),D" }, /* 7c: 0111 0000 0111 1100 llll llll hhhh hhhh */
	2994	{MOV,"(%w),E" }, /* 7d: 0111 0000 0111 1101 llll llll hhhh hhhh */
	2995	{MOV,"(%w),H" }, /* 7e: 0111 0000 0111 1110 llll llll hhhh hhhh */
	2996	{MOV,"(%w),L" }, /* 7f: 0111 0000 0111 1111 llll llll hhhh hhhh */
	2997
	2998	{illegal,0 }, /* 80: 0111 0000 1000 0000 */
	2999	{illegal,0 }, /* 81: 0111 0000 1000 0001 */
	3000	{illegal,0 }, /* 82: 0111 0000 1000 0010 */
	3001	{illegal,0 }, /* 83: 0111 0000 1000 0011 */
	3002	{illegal,0 }, /* 84: 0111 0000 1000 0100 */
	3003	{illegal,0 }, /* 85: 0111 0000 1000 0101 */
	3004	{illegal,0 }, /* 86: 0111 0000 1000 0110 */
	3005	{illegal,0 }, /* 87: 0111 0000 1000 0111 */
	3006	{illegal,0 }, /* 88: 0111 0000 1000 1000 */
	3007	{ANAX,"(BC)" }, /* 89: 0111 0000 1000 1001 */
	3008	{ANAX,"(DE)" }, /* 8a: 0111 0000 1000 1010 */
	3009	{ANAX,"(HL)" }, /* 8b: 0111 0000 1000 1011 */
	3010	{ANAX,"(DE+)" }, /* 8c: 0111 0000 1000 1100 */
	3011	{ANAX,"(HL+)" }, /* 8d: 0111 0000 1000 1101 */
	3012	{ANAX,"(DE-)" }, /* 8e: 0111 0000 1000 1110 */
	3013	{ANAX,"(HL-)" }, /* 8f: 0111 0000 1000 1111 */
	3014
	3015	{illegal,0 }, /* 90: 0111 0000 1001 0000 */
	3016	{XRAX,"(BC)" }, /* 91: 0111 0000 1001 0001 */
	3017	{XRAX,"(DE)" }, /* 92: 0111 0000 1001 0010 */
	3018	{XRAX,"(HL)" }, /* 93: 0111 0000 1001 0011 */
	3019	{XRAX,"(DE+)" }, /* 94: 0111 0000 1001 0100 */
	3020	{XRAX,"(HL+)" }, /* 95: 0111 0000 1001 0101 */
	3021	{XRAX,"(DE-)" }, /* 96: 0111 0000 1001 0110 */
	3022	{XRAX,"(HL-)" }, /* 97: 0111 0000 1001 0111 */
	3023	{illegal,0 }, /* 98: 0111 0000 1001 1000 */
	3024	{ORAX,"(BC)" }, /* 99: 0111 0000 1001 1001 */
	3025	{ORAX,"(DE)" }, /* 9a: 0111 0000 1001 1010 */
	3026	{ORAX,"(HL)" }, /* 9b: 0111 0000 1001 1011 */
	3027	{ORAX,"(DE+)" }, /* 9c: 0111 0000 1001 1100 */
	3028	{ORAX,"(HL+)" }, /* 9d: 0111 0000 1001 1101 */
	3029	{ORAX,"(DE-)" }, /* 9e: 0111 0000 1001 1110 */
	3030	{ORAX,"(HL-)" }, /* 9f: 0111 0000 1001 1111 */
	3031
	3032	{illegal,0 }, /* a0: 0111 0000 1010 0000 */
	3033	{ADDNCX,"(BC)" }, /* a1: 0111 0000 1010 0001 */
	3034	{ADDNCX,"(DE)" }, /* a2: 0111 0000 1010 0010 */
	3035	{ADDNCX,"(HL)" }, /* a3: 0111 0000 1010 0011 */
	3036	{ADDNCX,"(DE+)" }, /* a4: 0111 0000 1010 0100 */
	3037	{ADDNCX,"(HL+)" }, /* a5: 0111 0000 1010 0101 */
	3038	{ADDNCX,"(DE-)" }, /* a6: 0111 0000 1010 0110 */
	3039	{ADDNCX,"(HL-)" }, /* a7: 0111 0000 1010 0111 */
	3040	{illegal,0 }, /* a8: 0111 0000 1010 1000 */
	3041	{GTAX,"(BC)" }, /* a9: 0111 0000 1010 1001 */
	3042	{GTAX,"(DE)" }, /* aa: 0111 0000 1010 1010 */
	3043	{GTAX,"(HL)" }, /* ab: 0111 0000 1010 1011 */
	3044	{GTAX,"(DE+)" }, /* ac: 0111 0000 1010 1100 */
	3045	{GTAX,"(HL+)" }, /* ad: 0111 0000 1010 1101 */
	3046	{GTAX,"(DE-)" }, /* ae: 0111 0000 1010 1110 */
	3047	{GTAX,"(HL-)" }, /* af: 0111 0000 1010 1111 */
	3048
	3049	{illegal,0 }, /* b0: 0111 0000 1011 0000 */
	3050	{SUBNBX,"(BC)" }, /* b1: 0111 0000 1011 0001 */
	3051	{SUBNBX,"(DE)" }, /* b2: 0111 0000 1011 0010 */
	3052	{SUBNBX,"(HL)" }, /* b3: 0111 0000 1011 0011 */
	3053	{SUBNBX,"(DE+)" }, /* b4: 0111 0000 1011 0100 */
	3054	{SUBNBX,"(HL+)" }, /* b5: 0111 0000 1011 0101 */
	3055	{SUBNBX,"(DE-)" }, /* b6: 0111 0000 1011 0110 */
	3056	{SUBNBX,"(HL-)" }, /* b7: 0111 0000 1011 0111 */
	3057	{illegal,0 }, /* b8: 0111 0000 1011 1000 */
	3058	{LTAX,"(BC)" }, /* b9: 0111 0000 1011 1001 */
	3059	{LTAX,"(DE)" }, /* ba: 0111 0000 1011 1010 */
	3060	{LTAX,"(HL)" }, /* bb: 0111 0000 1011 1011 */
	3061	{LTAX,"(DE+)" }, /* bc: 0111 0000 1011 1100 */
	3062	{LTAX,"(HL+)" }, /* bd: 0111 0000 1011 1101 */
	3063	{LTAX,"(DE-)" }, /* be: 0111 0000 1011 1110 */
	3064	{LTAX,"(HL-)" }, /* bf: 0111 0000 1011 1111 */
	3065
	3066	{illegal,0 }, /* c0: 0111 0000 1100 0000 */
	3067	{ADDX,"(BC)" }, /* c1: 0111 0000 1100 0001 */
	3068	{ADDX,"(DE)" }, /* c2: 0111 0000 1100 0010 */
	3069	{ADDX,"(HL)" }, /* c3: 0111 0000 1100 0011 */
	3070	{ADDX,"(DE+)" }, /* c4: 0111 0000 1100 0100 */
	3071	{ADDX,"(HL+)" }, /* c5: 0111 0000 1100 0101 */
	3072	{ADDX,"(DE-)" }, /* c6: 0111 0000 1100 0110 */
	3073	{ADDX,"(HL-)" }, /* c7: 0111 0000 1100 0111 */
	3074	{illegal,0 }, /* c8: 0111 0000 1100 1000 */
	3075	{ONAX,"(BC)" }, /* c9: 0111 0000 1100 1001 */
	3076	{ONAX,"(DE)" }, /* ca: 0111 0000 1100 1010 */
	3077	{ONAX,"(HL)" }, /* cb: 0111 0000 1100 1011 */
	3078	{ONAX,"(DE+)" }, /* cc: 0111 0000 1100 1100 */
	3079	{ONAX,"(HL+)" }, /* cd: 0111 0000 1100 1101 */
	3080	{ONAX,"(DE-)" }, /* ce: 0111 0000 1100 1110 */
	3081	{ONAX,"(HL-)" }, /* cf: 0111 0000 1100 1111 */
	3082
	3083	{illegal,0 }, /* d0: 0111 0000 1101 0000 */
	3084	{ADCX,"(BC)" }, /* d1: 0111 0000 1101 0001 */
	3085	{ADCX,"(DE)" }, /* d2: 0111 0000 1101 0010 */
	3086	{ADCX,"(HL)" }, /* d3: 0111 0000 1101 0011 */
	3087	{ADCX,"(DE+)" }, /* d4: 0111 0000 1101 0100 */
	3088	{ADCX,"(HL+)" }, /* d5: 0111 0000 1101 0101 */
	3089	{ADCX,"(DE-)" }, /* d6: 0111 0000 1101 0110 */
	3090	{ADCX,"(HL-)" }, /* d7: 0111 0000 1101 0111 */
	3091	{illegal,0 }, /* d8: 0111 0000 1101 1000 */
	3092	{OFFAX,"(BC)" }, /* d9: 0111 0000 1101 1001 */
	3093	{OFFAX,"(DE)" }, /* da: 0111 0000 1101 1010 */
	3094	{OFFAX,"(HL)" }, /* db: 0111 0000 1101 1011 */
	3095	{OFFAX,"(DE+)" }, /* dc: 0111 0000 1101 1100 */
	3096	{OFFAX,"(HL+)" }, /* dd: 0111 0000 1101 1101 */
	3097	{OFFAX,"(DE-)" }, /* de: 0111 0000 1101 1110 */
	3098	{OFFAX,"(HL-)" }, /* df: 0111 0000 1101 1111 */
	3099
	3100	{illegal,0 }, /* e0: 0111 0000 1110 0000 */
	3101	{SUBX,"(BC)" }, /* e1: 0111 0000 1110 0001 */
	3102	{SUBX,"(DE)" }, /* e2: 0111 0000 1110 0010 */
	3103	{SUBX,"(HL)" }, /* e3: 0111 0000 1110 0011 */
	3104	{SUBX,"(DE+)" }, /* e4: 0111 0000 1110 0100 */
	3105	{SUBX,"(HL+)" }, /* e5: 0111 0000 1110 0101 */
	3106	{SUBX,"(DE-)" }, /* e6: 0111 0000 1110 0110 */
	3107	{SUBX,"(HL-)" }, /* e7: 0111 0000 1110 0111 */
	3108	{illegal,0 }, /* e8: 0111 0000 1110 1000 */
	3109	{NEAX,"(BC)" }, /* e9: 0111 0000 1110 1001 */
	3110	{NEAX,"(DE)" }, /* ea: 0111 0000 1110 1010 */
	3111	{NEAX,"(HL)" }, /* eb: 0111 0000 1110 1011 */
	3112	{NEAX,"(DE+)" }, /* ec: 0111 0000 1110 1100 */
	3113	{NEAX,"(HL+)" }, /* ed: 0111 0000 1110 1101 */
	3114	{NEAX,"(DE-)" }, /* ee: 0111 0000 1110 1110 */
	3115	{NEAX,"(HL-)" }, /* ef: 0111 0000 1110 1111 */
	3116
	3117	{illegal,0 }, /* f0: 0111 0000 1111 0000 */
	3118	{SBBX,"(BC)" }, /* f1: 0111 0000 1111 0001 */
	3119	{SBBX,"(DE)" }, /* f2: 0111 0000 1111 0010 */
	3120	{SBBX,"(HL)" }, /* f3: 0111 0000 1111 0011 */
	3121	{SBBX,"(DE+)" }, /* f4: 0111 0000 1111 0100 */
	3122	{SBBX,"(HL+)" }, /* f5: 0111 0000 1111 0101 */
	3123	{SBBX,"(DE-)" }, /* f6: 0111 0000 1111 0110 */
	3124	{SBBX,"(HL-)" }, /* f7: 0111 0000 1111 0111 */
	3125	{illegal,0 }, /* f8: 0111 0000 1111 1000 */
	3126	{EQAX,"(BC)" }, /* f9: 0111 0000 1111 1001 */
	3127	{EQAX,"(DE)" }, /* fa: 0111 0000 1111 1010 */
	3128	{EQAX,"(HL)" }, /* fb: 0111 0000 1111 1011 */
	3129	{EQAX,"(DE+)" }, /* fc: 0111 0000 1111 1100 */
	3130	{EQAX,"(HL+)" }, /* fd: 0111 0000 1111 1101 */
	3131	{EQAX,"(DE-)" }, /* fe: 0111 0000 1111 1110 */
	3132	{EQAX,"(HL-)" } /* ff: 0111 0000 1111 1111 */
	3133	};
	3134
	3135	/* prefix 74 */
	3136	static const struct dasm_s dasm74[256] =
	3137	{
	3138	{illegal,0 }, /* 00: 0111 0100 0000 0000 */
	3139	{illegal,0 }, /* 01: 0111 0100 0000 0001 */
	3140	{illegal,0 }, /* 02: 0111 0100 0000 0010 */
	3141	{illegal,0 }, /* 03: 0111 0100 0000 0011 */
	3142	{illegal,0 }, /* 04: 0111 0100 0000 0100 */
	3143	{illegal,0 }, /* 05: 0111 0100 0000 0101 */
	3144	{illegal,0 }, /* 06: 0111 0100 0000 0110 */
	3145	{illegal,0 }, /* 07: 0111 0100 0000 0111 */
	3146	{ANI,"V,%b" }, /* 08: 0111 0100 0000 1000 xxxx xxxx */
	3147	{ANI,"A,%b" }, /* 09: 0111 0100 0000 1001 xxxx xxxx */
	3148	{ANI,"B,%b" }, /* 0a: 0111 0100 0000 1010 xxxx xxxx */
	3149	{ANI,"C,%b" }, /* 0b: 0111 0100 0000 1011 xxxx xxxx */
	3150	{ANI,"D,%b" }, /* 0c: 0111 0100 0000 1100 xxxx xxxx */
	3151	{ANI,"E,%b" }, /* 0d: 0111 0100 0000 1101 xxxx xxxx */
	3152	{ANI,"H,%b" }, /* 0e: 0111 0100 0000 1110 xxxx xxxx */
	3153	{ANI,"L,%b" }, /* 0f: 0111 0100 0000 1111 xxxx xxxx */
	3154
	3155	{XRI,"V,%b" }, /* 10: 0111 0100 0001 0000 xxxx xxxx */
	3156	{XRI,"A,%b" }, /* 11: 0111 0100 0001 0001 xxxx xxxx */
	3157	{XRI,"B,%b" }, /* 12: 0111 0100 0001 0010 xxxx xxxx */
	3158	{XRI,"C,%b" }, /* 13: 0111 0100 0001 0011 xxxx xxxx */
	3159	{XRI,"D,%b" }, /* 14: 0111 0100 0001 0100 xxxx xxxx */
	3160	{XRI,"E,%b" }, /* 15: 0111 0100 0001 0101 xxxx xxxx */
	3161	{XRI,"H,%b" }, /* 16: 0111 0100 0001 0110 xxxx xxxx */
	3162	{XRI,"L,%b" }, /* 17: 0111 0100 0001 0111 xxxx xxxx */
	3163	{ORI,"V,%b" }, /* 18: 0111 0100 0001 1000 xxxx xxxx */
	3164	{ORI,"A,%b" }, /* 19: 0111 0100 0001 1001 xxxx xxxx */
	3165	{ORI,"B,%b" }, /* 1a: 0111 0100 0001 1010 xxxx xxxx */
	3166	{ORI,"C,%b" }, /* 1b: 0111 0100 0001 1011 xxxx xxxx */
	3167	{ORI,"D,%b" }, /* 1c: 0111 0100 0001 1100 xxxx xxxx */
	3168	{ORI,"E,%b" }, /* 1d: 0111 0100 0001 1101 xxxx xxxx */
	3169	{ORI,"H,%b" }, /* 1e: 0111 0100 0001 1110 xxxx xxxx */
	3170	{ORI,"L,%b" }, /* 1f: 0111 0100 0001 1111 xxxx xxxx */
	3171
	3172	{ADINC,"V,%b" }, /* 20: 0111 0100 0010 0000 xxxx xxxx */
	3173	{ADINC,"A,%b" }, /* 21: 0111 0100 0010 0001 xxxx xxxx */
	3174	{ADINC,"B,%b" }, /* 22: 0111 0100 0010 0010 xxxx xxxx */
	3175	{ADINC,"C,%b" }, /* 23: 0111 0100 0010 0011 xxxx xxxx */
	3176	{ADINC,"D,%b" }, /* 24: 0111 0100 0010 0100 xxxx xxxx */
	3177	{ADINC,"E,%b" }, /* 25: 0111 0100 0010 0101 xxxx xxxx */
	3178	{ADINC,"H,%b" }, /* 26: 0111 0100 0010 0110 xxxx xxxx */
	3179	{ADINC,"L,%b" }, /* 27: 0111 0100 0010 0111 xxxx xxxx */
	3180	{GTI,"V,%b" }, /* 28: 0111 0100 0010 1000 xxxx xxxx */
	3181	{GTI,"A,%b" }, /* 29: 0111 0100 0010 1001 xxxx xxxx */
	3182	{GTI,"B,%b" }, /* 2a: 0111 0100 0010 1010 xxxx xxxx */
	3183	{GTI,"C,%b" }, /* 2b: 0111 0100 0010 1011 xxxx xxxx */
	3184	{GTI,"D,%b" }, /* 2c: 0111 0100 0010 1100 xxxx xxxx */
	3185	{GTI,"E,%b" }, /* 2d: 0111 0100 0010 1101 xxxx xxxx */
	3186	{GTI,"H,%b" }, /* 2e: 0111 0100 0010 1110 xxxx xxxx */
	3187	{GTI,"L,%b" }, /* 2f: 0111 0100 0010 1111 xxxx xxxx */
	3188
	3189	{SUINB,"V,%b" }, /* 30: 0111 0100 0011 0000 xxxx xxxx */
	3190	{SUINB,"A,%b" }, /* 31: 0111 0100 0011 0001 xxxx xxxx */
	3191	{SUINB,"B,%b" }, /* 32: 0111 0100 0011 0010 xxxx xxxx */
	3192	{SUINB,"C,%b" }, /* 33: 0111 0100 0011 0011 xxxx xxxx */
	3193	{SUINB,"D,%b" }, /* 34: 0111 0100 0011 0100 xxxx xxxx */
	3194	{SUINB,"E,%b" }, /* 35: 0111 0100 0011 0101 xxxx xxxx */
	3195	{SUINB,"H,%b" }, /* 36: 0111 0100 0011 0110 xxxx xxxx */
	3196	{SUINB,"L,%b" }, /* 37: 0111 0100 0011 0111 xxxx xxxx */
	3197	{LTI,"V,%b" }, /* 38: 0111 0100 0011 1000 xxxx xxxx */
	3198	{LTI,"A,%b" }, /* 39: 0111 0100 0011 1001 xxxx xxxx */
	3199	{LTI,"B,%b" }, /* 3a: 0111 0100 0011 1010 xxxx xxxx */
	3200	{LTI,"C,%b" }, /* 3b: 0111 0100 0011 1011 xxxx xxxx */
	3201	{LTI,"D,%b" }, /* 3c: 0111 0100 0011 1100 xxxx xxxx */
	3202	{LTI,"E,%b" }, /* 3d: 0111 0100 0011 1101 xxxx xxxx */
	3203	{LTI,"H,%b" }, /* 3e: 0111 0100 0011 1110 xxxx xxxx */
	3204	{LTI,"L,%b" }, /* 3f: 0111 0100 0011 1111 xxxx xxxx */
	3205
	3206	{ADI,"V,%b" }, /* 40: 0111 0100 0100 0000 xxxx xxxx */
	3207	{ADI,"A,%b" }, /* 41: 0111 0100 0100 0001 xxxx xxxx */
	3208	{ADI,"B,%b" }, /* 42: 0111 0100 0100 0010 xxxx xxxx */
	3209	{ADI,"C,%b" }, /* 43: 0111 0100 0100 0011 xxxx xxxx */
	3210	{ADI,"D,%b" }, /* 44: 0111 0100 0100 0100 xxxx xxxx */
	3211	{ADI,"E,%b" }, /* 45: 0111 0100 0100 0101 xxxx xxxx */
	3212	{ADI,"H,%b" }, /* 46: 0111 0100 0100 0110 xxxx xxxx */
	3213	{ADI,"L,%b" }, /* 47: 0111 0100 0100 0111 xxxx xxxx */
	3214	{ONI,"V,%b" }, /* 48: 0111 0100 0100 1000 xxxx xxxx */
	3215	{ONI,"A,%b" }, /* 49: 0111 0100 0100 1001 xxxx xxxx */
	3216	{ONI,"B,%b" }, /* 4a: 0111 0100 0100 1010 xxxx xxxx */
	3217	{ONI,"C,%b" }, /* 4b: 0111 0100 0100 1011 xxxx xxxx */
	3218	{ONI,"D,%b" }, /* 4c: 0111 0100 0100 1100 xxxx xxxx */
	3219	{ONI,"E,%b" }, /* 4d: 0111 0100 0100 1101 xxxx xxxx */
	3220	{ONI,"H,%b" }, /* 4e: 0111 0100 0100 1110 xxxx xxxx */
	3221	{ONI,"L,%b" }, /* 4f: 0111 0100 0100 1111 xxxx xxxx */
	3222
	3223	{ACI,"V,%b" }, /* 50: 0111 0100 0101 0000 xxxx xxxx */
	3224	{ACI,"A,%b" }, /* 51: 0111 0100 0101 0001 xxxx xxxx */
	3225	{ACI,"B,%b" }, /* 52: 0111 0100 0101 0010 xxxx xxxx */
	3226	{ACI,"C,%b" }, /* 53: 0111 0100 0101 0011 xxxx xxxx */
	3227	{ACI,"D,%b" }, /* 54: 0111 0100 0101 0100 xxxx xxxx */
	3228	{ACI,"E,%b" }, /* 55: 0111 0100 0101 0101 xxxx xxxx */
	3229	{ACI,"H,%b" }, /* 56: 0111 0100 0101 0110 xxxx xxxx */
	3230	{ACI,"L,%b" }, /* 57: 0111 0100 0101 0111 xxxx xxxx */
	3231	{OFFI,"V,%b" }, /* 58: 0111 0100 0101 1000 xxxx xxxx */
	3232	{OFFI,"A,%b" }, /* 59: 0111 0100 0101 1001 xxxx xxxx */
	3233	{OFFI,"B,%b" }, /* 5a: 0111 0100 0101 1010 xxxx xxxx */
	3234	{OFFI,"C,%b" }, /* 5b: 0111 0100 0101 1011 xxxx xxxx */
	3235	{OFFI,"D,%b" }, /* 5c: 0111 0100 0101 1100 xxxx xxxx */
	3236	{OFFI,"E,%b" }, /* 5d: 0111 0100 0101 1101 xxxx xxxx */
	3237	{OFFI,"H,%b" }, /* 5e: 0111 0100 0101 1110 xxxx xxxx */
	3238	{OFFI,"L,%b" }, /* 5f: 0111 0100 0101 1111 xxxx xxxx */
	3239
	3240	{SUI,"V,%b" }, /* 60: 0111 0100 0110 0000 xxxx xxxx */
	3241	{SUI,"A,%b" }, /* 61: 0111 0100 0110 0001 xxxx xxxx */
	3242	{SUI,"B,%b" }, /* 62: 0111 0100 0110 0010 xxxx xxxx */
	3243	{SUI,"C,%b" }, /* 63: 0111 0100 0110 0011 xxxx xxxx */
	3244	{SUI,"D,%b" }, /* 64: 0111 0100 0110 0100 xxxx xxxx */
	3245	{SUI,"E,%b" }, /* 65: 0111 0100 0110 0101 xxxx xxxx */
	3246	{SUI,"H,%b" }, /* 66: 0111 0100 0110 0110 xxxx xxxx */
	3247	{SUI,"L,%b" }, /* 67: 0111 0100 0110 0111 xxxx xxxx */
	3248	{NEI,"V,%b" }, /* 68: 0111 0100 0110 1000 xxxx xxxx */
	3249	{NEI,"A,%b" }, /* 69: 0111 0100 0110 1001 xxxx xxxx */
	3250	{NEI,"B,%b" }, /* 6a: 0111 0100 0110 1010 xxxx xxxx */
	3251	{NEI,"C,%b" }, /* 6b: 0111 0100 0110 1011 xxxx xxxx */
	3252	{NEI,"D,%b" }, /* 6c: 0111 0100 0110 1100 xxxx xxxx */
	3253	{NEI,"E,%b" }, /* 6d: 0111 0100 0110 1101 xxxx xxxx */
	3254	{NEI,"H,%b" }, /* 6e: 0111 0100 0110 1110 xxxx xxxx */
	3255	{NEI,"L,%b" }, /* 6f: 0111 0100 0110 1111 xxxx xxxx */
	3256
	3257	{SBI,"V,%b" }, /* 70: 0111 0100 0111 0000 xxxx xxxx */
	3258	{SBI,"A,%b" }, /* 71: 0111 0100 0111 0001 xxxx xxxx */
	3259	{SBI,"B,%b" }, /* 72: 0111 0100 0111 0010 xxxx xxxx */
	3260	{SBI,"C,%b" }, /* 73: 0111 0100 0111 0011 xxxx xxxx */
	3261	{SBI,"D,%b" }, /* 74: 0111 0100 0111 0100 xxxx xxxx */
	3262	{SBI,"E,%b" }, /* 75: 0111 0100 0111 0101 xxxx xxxx */
	3263	{SBI,"H,%b" }, /* 76: 0111 0100 0111 0110 xxxx xxxx */
	3264	{SBI,"L,%b" }, /* 77: 0111 0100 0111 0111 xxxx xxxx */
	3265	{EQI,"V,%b" }, /* 78: 0111 0100 0111 1000 xxxx xxxx */
	3266	{EQI,"A,%b" }, /* 79: 0111 0100 0111 1001 xxxx xxxx */
	3267	{EQI,"B,%b" }, /* 7a: 0111 0100 0111 1010 xxxx xxxx */
	3268	{EQI,"C,%b" }, /* 7b: 0111 0100 0111 1011 xxxx xxxx */
	3269	{EQI,"D,%b" }, /* 7c: 0111 0100 0111 1100 xxxx xxxx */
	3270	{EQI,"E,%b" }, /* 7d: 0111 0100 0111 1101 xxxx xxxx */
	3271	{EQI,"H,%b" }, /* 7e: 0111 0100 0111 1110 xxxx xxxx */
	3272	{EQI,"L,%b" }, /* 7f: 0111 0100 0111 1111 xxxx xxxx */
	3273
	3274	{illegal,0 }, /* 80: 0111 0100 1000 0000 */
	3275	{illegal,0 }, /* 81: 0111 0100 1000 0001 */
	3276	{illegal,0 }, /* 82: 0111 0100 1000 0010 */
	3277	{illegal,0 }, /* 83: 0111 0100 1000 0011 */
	3278	{illegal,0 }, /* 84: 0111 0100 1000 0100 */
	3279	{illegal,0 }, /* 85: 0111 0100 1000 0101 */
	3280	{illegal,0 }, /* 86: 0111 0100 1000 0110 */
	3281	{illegal,0 }, /* 87: 0111 0100 1000 0111 */
	3282	{ANAW,"%a" }, /* 88: 0111 0100 1000 1000 oooo oooo */
	3283	{illegal,0 }, /* 89: 0111 0100 1000 1001 */
	3284	{illegal,0 }, /* 8a: 0111 0100 1000 1010 */
	3285	{illegal,0 }, /* 8b: 0111 0100 1000 1011 */
	3286	{illegal,0 }, /* 8c: 0111 0100 1000 1100 */
	3287	{DAN,"EA,BC" }, /* 8d: 0111 0100 1000 1101 */
	3288	{DAN,"EA,DE" }, /* 8e: 0111 0100 1000 1110 */
	3289	{DAN,"EA,HL" }, /* 8f: 0111 0100 1000 1111 */
	3290
	3291	{XRAW,"%a" }, /* 90: 0111 0100 1001 0000 oooo oooo */
	3292	{illegal,0 }, /* 91: 0111 0100 1001 0001 */
	3293	{illegal,0 }, /* 92: 0111 0100 1001 0010 */
	3294	{illegal,0 }, /* 93: 0111 0100 1001 0011 */
	3295	{illegal,0 }, /* 94: 0111 0100 1001 0100 */
	3296	{DXR,"EA,BC" }, /* 95: 0111 0100 1001 0101 */
	3297	{DXR,"EA,DE" }, /* 96: 0111 0100 1001 0110 */
	3298	{DXR,"EA,HL" }, /* 97: 0111 0100 1001 0111 */
	3299	{ORAW,"%a" }, /* 98: 0111 0100 1001 1000 oooo oooo */
	3300	{illegal,0 }, /* 99: 0111 0100 1001 1001 */
	3301	{illegal,0 }, /* 9a: 0111 0100 1001 1010 */
	3302	{illegal,0 }, /* 9b: 0111 0100 1001 1011 */
	3303	{illegal,0 }, /* 9c: 0111 0100 1001 1100 */
	3304	{DOR,"EA,BC" }, /* 9d: 0111 0100 1001 1101 */
	3305	{DOR,"EA,DE" }, /* 9e: 0111 0100 1001 1110 */
	3306	{DOR,"EA,HL" }, /* 9f: 0111 0100 1001 1111 */
	3307
	3308	{ADDNCW,"%a" }, /* a0: 0111 0100 1010 0000 oooo oooo */
	3309	{illegal,0 }, /* a1: 0111 0100 1010 0001 */
	3310	{illegal,0 }, /* a2: 0111 0100 1010 0010 */
	3311	{illegal,0 }, /* a3: 0111 0100 1010 0011 */
	3312	{illegal,0 }, /* a4: 0111 0100 1010 0100 */
	3313	{DADDNC,"EA,BC" }, /* a5: 0111 0100 1010 0101 */
	3314	{DADDNC,"EA,DE" }, /* a6: 0111 0100 1010 0110 */
	3315	{DADDNC,"EA,HL" }, /* a7: 0111 0100 1010 0111 */
	3316	{GTAW,"%a" }, /* a8: 0111 0100 1010 1000 oooo oooo */
	3317	{illegal,0 }, /* a9: 0111 0100 1010 1001 */
	3318	{illegal,0 }, /* aa: 0111 0100 1010 1010 */
	3319	{illegal,0 }, /* ab: 0111 0100 1010 1011 */
	3320	{illegal,0 }, /* ac: 0111 0100 1010 1100 */
	3321	{DGT,"EA,BC" }, /* ad: 0111 0100 1010 1101 */
	3322	{DGT,"EA,DE" }, /* ae: 0111 0100 1010 1110 */
	3323	{DGT,"EA,HL" }, /* af: 0111 0100 1010 1111 */
	3324
	3325	{SUBNBW,"%a" }, /* b0: 0111 0100 1011 0000 oooo oooo */
	3326	{illegal,0 }, /* b1: 0111 0100 1011 0001 */
	3327	{illegal,0 }, /* b2: 0111 0100 1011 0010 */
	3328	{illegal,0 }, /* b3: 0111 0100 1011 0011 */
	3329	{illegal,0 }, /* b4: 0111 0100 1011 0100 */
	3330	{DSUBNB,"EA,BC" }, /* b5: 0111 0100 1011 0101 */
	3331	{DSUBNB,"EA,DE" }, /* b6: 0111 0100 1011 0110 */
	3332	{DSUBNB,"EA,HL" }, /* b7: 0111 0100 1011 0111 */
	3333	{LTAW,"%a" }, /* b8: 0111 0100 1011 1000 oooo oooo */
	3334	{illegal,0 }, /* b9: 0111 0100 1011 1001 */
	3335	{illegal,0 }, /* ba: 0111 0100 1011 1010 */
	3336	{illegal,0 }, /* bb: 0111 0100 1011 1011 */
	3337	{illegal,0 }, /* bc: 0111 0100 1011 1100 */
	3338	{DLT,"EA,BC" }, /* bd: 0111 0100 1011 1101 */
	3339	{DLT,"EA,DE" }, /* be: 0111 0100 1011 1110 */
	3340	{DLT,"EA,HL" }, /* bf: 0111 0100 1011 1111 */
	3341
	3342	{ADDW,"%a" }, /* c0: 0111 0100 1100 0000 oooo oooo */
	3343	{illegal,0 }, /* c1: 0111 0100 1100 0001 */
	3344	{illegal,0 }, /* c2: 0111 0100 1100 0010 */
	3345	{illegal,0 }, /* c3: 0111 0100 1100 0011 */
	3346	{illegal,0 }, /* c4: 0111 0100 1100 0100 */
	3347	{DADD,"EA,BC" }, /* c5: 0111 0100 1100 0101 */
	3348	{DADD,"EA,DE" }, /* c6: 0111 0100 1100 0110 */
	3349	{DADD,"EA,HL" }, /* c7: 0111 0100 1100 0111 */
	3350	{ONAW,"%a" }, /* c8: 0111 0100 1100 1000 oooo oooo */
	3351	{illegal,0 }, /* c9: 0111 0100 1100 1001 */
	3352	{illegal,0 }, /* ca: 0111 0100 1100 1010 */
	3353	{illegal,0 }, /* cb: 0111 0100 1100 1011 */
	3354	{illegal,0 }, /* cc: 0111 0100 1100 1100 */
	3355	{DON,"EA,BC" }, /* cd: 0111 0100 1100 1101 */
	3356	{DON,"EA,DE" }, /* ce: 0111 0100 1100 1110 */
	3357	{DON,"EA,HL" }, /* cf: 0111 0100 1100 1111 */
	3358
	3359	{ADCW,"%a" }, /* d0: 0111 0100 1101 0000 oooo oooo */
	3360	{illegal,0 }, /* d1: 0111 0100 1101 0001 */
	3361	{illegal,0 }, /* d2: 0111 0100 1101 0010 */
	3362	{illegal,0 }, /* d3: 0111 0100 1101 0011 */
	3363	{illegal,0 }, /* d4: 0111 0100 1101 0100 */
	3364	{DADC,"EA,BC" }, /* d5: 0111 0100 1101 0101 */
	3365	{DADC,"EA,DE" }, /* d6: 0111 0100 1101 0110 */
	3366	{DADC,"EA,HL" }, /* d7: 0111 0100 1101 0111 */
	3367	{OFFAW,"%a" }, /* d8: 0111 0100 1101 1000 oooo oooo */
	3368	{illegal,0 }, /* d9: 0111 0100 1101 1001 */
	3369	{illegal,0 }, /* da: 0111 0100 1101 1010 */
	3370	{illegal,0 }, /* db: 0111 0100 1101 1011 */
	3371	{illegal,0 }, /* dc: 0111 0100 1101 1100 */
	3372	{DOFF,"EA,BC" }, /* dd: 0111 0100 1101 1101 */
	3373	{DOFF,"EA,DE" }, /* de: 0111 0100 1101 1110 */
	3374	{DOFF,"EA,HL" }, /* df: 0111 0100 1101 1111 */
	3375
	3376	{SUBW,"%a" }, /* e0: 0111 0100 1110 0000 oooo oooo */
	3377	{illegal,0 }, /* e1: 0111 0100 1110 0001 */
	3378	{illegal,0 }, /* e2: 0111 0100 1110 0010 */
	3379	{illegal,0 }, /* e3: 0111 0100 1110 0011 */
	3380	{illegal,0 }, /* e4: 0111 0100 1110 0100 */
	3381	{DSUB,"EA,BC" }, /* e5: 0111 0100 1110 0101 */
	3382	{DSUB,"EA,DE" }, /* e6: 0111 0100 1110 0110 */
	3383	{DSUB,"EA,HL" }, /* e7: 0111 0100 1110 0111 */
	3384	{NEAW,"%a" }, /* e8: 0111 0100 1110 1000 oooo oooo */
	3385	{illegal,0 }, /* e9: 0111 0100 1110 1001 */
	3386	{illegal,0 }, /* ea: 0111 0100 1110 1010 */
	3387	{illegal,0 }, /* eb: 0111 0100 1110 1011 */
	3388	{illegal,0 }, /* ec: 0111 0100 1110 1100 */
	3389	{DNE,"EA,BC" }, /* ed: 0111 0100 1110 1101 */
	3390	{DNE,"EA,DE" }, /* ee: 0111 0100 1110 1110 */
	3391	{DNE,"EA,HL" }, /* ef: 0111 0100 1110 1111 */
	3392
	3393	{SBBW,"%a" }, /* f0: 0111 0100 1111 0000 oooo oooo */
	3394	{illegal,0 }, /* f1: 0111 0100 1111 0001 */
	3395	{illegal,0 }, /* f2: 0111 0100 1111 0010 */
	3396	{illegal,0 }, /* f3: 0111 0100 1111 0011 */
	3397	{illegal,0 }, /* f4: 0111 0100 1111 0100 */
	3398	{DSBB,"EA,BC" }, /* f5: 0111 0100 1111 0101 */
	3399	{DSBB,"EA,DE" }, /* f6: 0111 0100 1111 0110 */
	3400	{DSBB,"EA,HL" }, /* f7: 0111 0100 1111 0111 */
	3401	{EQAW,"%a" }, /* f8: 0111 0100 1111 1000 oooo oooo */
	3402	{illegal,0 }, /* f9: 0111 0100 1111 1001 */
	3403	{illegal,0 }, /* fa: 0111 0100 1111 1010 */
	3404	{illegal,0 }, /* fb: 0111 0100 1111 1011 */
	3405	{illegal,0 }, /* fc: 0111 0100 1111 1100 */
	3406	{DEQ,"EA,BC" }, /* fd: 0111 0100 1111 1101 */
	3407	{DEQ,"EA,DE" }, /* fe: 0111 0100 1111 1110 */
	3408	{DEQ,"EA,HL" } /* ff: 0111 0100 1111 1111 */
	3409	};
	3410
	3411	/* main opcodes */
	3412	static const struct dasm_s dasmXX_7810[256] =
	3413	{
	3414	{NOP,0 }, /* 00: 0000 0000 */
	3415	{LDAW,"%a" }, /* 01: 0000 0001 oooo oooo */
	3416	{INX,"SP" }, /* 02: 0000 0010 */
	3417	{DCX,"SP" }, /* 03: 0000 0011 */
	3418	{LXI,"SP,%w" }, /* 04: 0000 0100 llll llll hhhh hhhh */
	3419	{ANIW,"%a,%b" }, /* 05: 0000 0101 oooo oooo xxxx xxxx */
	3420	{illegal,0 }, /* 06: */
	3421	{ANI,"A,%b" }, /* 07: 0000 0111 xxxx xxxx */
	3422	{MOV,"A,EAH" }, /* 08: 0000 1000 */
	3423	{MOV,"A,EAL" }, /* 09: 0000 1001 */
	3424	{MOV,"A,B" }, /* 0a: 0000 1010 */
	3425	{MOV,"A,C" }, /* 0b: 0000 1011 */
	3426	{MOV,"A,D" }, /* 0c: 0000 1100 */
	3427	{MOV,"A,E" }, /* 0d: 0000 1101 */
	3428	{MOV,"A,H" }, /* 0e: 0000 1110 */
	3429	{MOV,"A,L" }, /* 0f: 0000 1111 */
	3430
	3431	{EXA,0 }, /* 10: 0001 0000 / / 7810 */
	3432	{EXX,0 }, /* 11: 0001 0001 / / 7810 */
	3433	{INX,"BC" }, /* 12: 0001 0010 */
	3434	{DCX,"BC" }, /* 13: 0001 0011 */
	3435	{LXI,"BC,%w" }, /* 14: 0001 0100 llll llll hhhh hhhh */
	3436	{ORIW,"%a,%b" }, /* 15: 0001 0101 oooo oooo xxxx xxxx */
	3437	{XRI,"A,%b" }, /* 16: 0001 0110 xxxx xxxx */
	3438	{ORI,"A,%b" }, /* 17: 0001 0111 xxxx xxxx */
	3439	{MOV,"EAH,A" }, /* 18: 0001 1000 */
	3440	{MOV,"EAL,A" }, /* 19: 0001 1001 */
	3441	{MOV,"B,A" }, /* 1a: 0001 1010 */
	3442	{MOV,"C,A" }, /* 1b: 0001 1011 */
	3443	{MOV,"D,A" }, /* 1c: 0001 1100 */
	3444	{MOV,"E,A" }, /* 1d: 0001 1101 */
	3445	{MOV,"H,A" }, /* 1e: 0001 1110 */
	3446	{MOV,"L,A" }, /* 1f: 0001 1111 */
	3447
	3448	{INRW,"%a" }, /* 20: 0010 0000 oooo oooo */
	3449	{JB,0 }, /* 21: 0010 0001 */
	3450	{INX,"DE" }, /* 22: 0010 0010 */
	3451	{DCX,"DE" }, /* 23: 0010 0011 */
	3452	{LXI,"DE,%w" }, /* 24: 0010 0100 llll llll hhhh hhhh */
	3453	{GTIW,"%a,%b" }, /* 25: 0010 0101 oooo oooo xxxx xxxx */
	3454	{ADINC,"A,%b" }, /* 26: 0010 0110 xxxx xxxx */
	3455	{GTI,"A,%b" }, /* 27: 0010 0111 xxxx xxxx */
	3456	{illegal,0 }, /* 28: 0010 1000 */
	3457	{LDAX,"(BC)" }, /* 29: 0010 1001 */
	3458	{LDAX,"(DE)" }, /* 2a: 0010 1010 */
	3459	{LDAX,"(HL)" }, /* 2b: 0010 1011 */
	3460	{LDAX,"(DE+)" }, /* 2c: 0010 1100 */
	3461	{LDAX,"(HL+)" }, /* 2d: 0010 1101 */
	3462	{LDAX,"(DE-)" }, /* 2e: 0010 1110 */
	3463	{LDAX,"(HL-)" }, /* 2f: 0010 1111 */
	3464
	3465	{DCRW,"%a" }, /* 30: 0011 0000 oooo oooo */
	3466	{BLOCK,0 }, /* 31: 0011 0001 / / 7810 */
	3467	{INX,"HL", }, /* 32: 0011 0010 */
	3468	{DCX,"HL", }, /* 33: 0011 0011 */
	3469	{LXI,"HL,%w" }, /* 34: 0011 0100 llll llll hhhh hhhh */
	3470	{LTIW,"%a,%b" }, /* 35: 0011 0101 oooo oooo xxxx xxxx */
	3471	{SUINB,"A,%b" }, /* 36: 0011 0110 xxxx xxxx */
	3472	{LTI,"A,%b" }, /* 37: 0011 0111 xxxx xxxx */
	3473	{illegal,0 }, /* 38: */
	3474	{STAX,"(BC)" }, /* 39: 0011 1001 */
	3475	{STAX,"(DE)" }, /* 3a: 0011 1010 */
	3476	{STAX,"(HL)" }, /* 3b: 0011 1011 */
	3477	{STAX,"(DE+)" }, /* 3c: 0011 1100 */
	3478	{STAX,"(HL+)" }, /* 3d: 0011 1101 */
	3479	{STAX,"(DE-)" }, /* 3e: 0011 1110 */
	3480	{STAX,"(HL-)" }, /* 3f: 0011 1111 */
	3481
	3482	{CALL,"%w" }, /* 40: 0100 0000 llll llll hhhh hhhh */
	3483	{INR,"A" }, /* 41: 0100 0001 */
	3484	{INR,"B" }, /* 42: 0100 0010 */
	3485	{INR,"C" }, /* 43: 0100 0011 */
	3486	{LXI,"EA,%w" }, /* 44: 0100 0100 llll llll hhhh hhhh */
	3487	{ONIW,"%a,%b" }, /* 45: 0100 0101 oooo oooo xxxx xxxx */
	3488	{ADI,"A,%b" }, /* 46: 0100 0110 xxxx xxxx */
	3489	{ONI,"A,%b" }, /* 47: 0100 0111 xxxx xxxx */
	3490	{0,dasm48_7810 }, /* 48: prefix */
	3491	{MVIX,"BC,%b" }, /* 49: 0100 1001 xxxx xxxx */
	3492	{MVIX,"DE,%b" }, /* 4a: 0100 1010 xxxx xxxx */
	3493	{MVIX,"HL,%b" }, /* 4b: 0100 1011 xxxx xxxx */
	3494	{0,dasm4C_7810 }, /* 4c: prefix */
	3495	{0,dasm4D_7810 }, /* 4d: prefix */
	3496	{JRE,"%d" }, /* 4e: 0100 111d dddd dddd */
	3497	{JRE,"%d" }, /* 4f: 0100 111d dddd dddd */
	3498
	3499	{EXH,0 }, /* 50: 0101 0000 / / 7810 */
	3500	{DCR,"A" }, /* 51: 0101 0001 */
	3501	{DCR,"B" }, /* 52: 0101 0010 */
	3502	{DCR,"C" }, /* 53: 0101 0011 */
	3503	{JMP,"%w" }, /* 54: 0101 0100 llll llll hhhh hhhh */
	3504	{OFFIW,"%a,%b" }, /* 55: 0101 0101 oooo oooo xxxx xxxx */
	3505	{ACI,"A,%b" }, /* 56: 0101 0110 xxxx xxxx */
	3506	{OFFI,"A,%b" }, /* 57: 0101 0111 xxxx xxxx */
	3507	{BIT,"0,%a", }, /* 58: 0101 1000 oooo oooo / / 7810 */
	3508	{BIT,"1,%a", }, /* 59: 0101 1001 oooo oooo / / 7810 */
	3509	{BIT,"2,%a", }, /* 5a: 0101 1010 oooo oooo / / 7810 */
	3510	{BIT,"3,%a", }, /* 5b: 0101 1011 oooo oooo / / 7810 */
	3511	{BIT,"4,%a", }, /* 5c: 0101 1100 oooo oooo / / 7810 */
	3512	{BIT,"5,%a", }, /* 5d: 0101 1101 oooo oooo / / 7810 */
	3513	{BIT,"6,%a", }, /* 5e: 0101 1110 oooo oooo / / 7810 */
	3514	{BIT,"7,%a", }, /* 5f: 0101 1111 oooo oooo / / 7810 */
	3515
	3516	{0,dasm60 }, /* 60: prefix */
	3517	{DAA,0 }, /* 61: 0110 0001 */
	3518	{RETI,0 }, /* 62: 0110 0010 */
	3519	{STAW,"%a" }, /* 63: 0110 0011 oooo oooo */
	3520	{0,dasm64_7810 }, /* 64: prefix */
	3521	{NEIW,"%a,%b" }, /* 65: 0110 0101 oooo oooo xxxx xxxx */
	3522	{SUI,"A,%b" }, /* 66: 0110 0110 xxxx xxxx */
	3523	{NEI,"A,%b" }, /* 67: 0110 0111 xxxx xxxx */
	3524	{MVI,"V,%b" }, /* 68: 0110 1000 xxxx xxxx */
	3525	{MVI,"A,%b" }, /* 69: 0110 1001 xxxx xxxx */
	3526	{MVI,"B,%b" }, /* 6a: 0110 1010 xxxx xxxx */
	3527	{MVI,"C,%b" }, /* 6b: 0110 1011 xxxx xxxx */
	3528	{MVI,"D,%b" }, /* 6c: 0110 1100 xxxx xxxx */
	3529	{MVI,"E,%b" }, /* 6d: 0110 1101 xxxx xxxx */
	3530	{MVI,"H,%b" }, /* 6e: 0110 1110 xxxx xxxx */
	3531	{MVI,"L,%b" }, /* 6f: 0110 1111 xxxx xxxx */
	3532
	3533	{0,dasm70 }, /* 70: prefix */
	3534	{MVIW,"%a,%b" }, /* 71: 0111 0001 oooo oooo xxxx xxxx */
	3535	{SOFTI,0 }, /* 72: 0111 0010 */
	3536	{illegal,0 }, /* 73: */
	3537	{0,dasm74 }, /* 74: prefix */
	3538	{EQIW,"%a,%b" }, /* 75: 0111 0101 oooo oooo xxxx xxxx */
	3539	{SBI,"A,%b" }, /* 76: 0111 0110 xxxx xxxx */
	3540	{EQI,"A,%b" }, /* 77: 0111 0111 xxxx xxxx */
	3541	{CALF,"%f" }, /* 78: 0111 1ddd dddd dddd */
	3542	{CALF,"%f" }, /* 79: 0111 1ddd dddd dddd */
	3543	{CALF,"%f" }, /* 7a: 0111 1ddd dddd dddd */
	3544	{CALF,"%f" }, /* 7b: 0111 1ddd dddd dddd */
	3545	{CALF,"%f" }, /* 7c: 0111 1ddd dddd dddd */
	3546	{CALF,"%f" }, /* 7d: 0111 1ddd dddd dddd */
	3547	{CALF,"%f" }, /* 7e: 0111 1ddd dddd dddd */
	3548	{CALF,"%f" }, /* 7f: 0111 1ddd dddd dddd */
	3549
	3550	{CALT,"%t" }, /* 80: 100t tttt */
	3551	{CALT,"%t" }, /* 81: 100t tttt */
	3552	{CALT,"%t" }, /* 82: 100t tttt */
	3553	{CALT,"%t" }, /* 83: 100t tttt */
	3554	{CALT,"%t" }, /* 84: 100t tttt */
	3555	{CALT,"%t" }, /* 85: 100t tttt */
	3556	{CALT,"%t" }, /* 86: 100t tttt */
	3557	{CALT,"%t" }, /* 87: 100t tttt */
	3558	{CALT,"%t" }, /* 88: 100t tttt */
	3559	{CALT,"%t" }, /* 89: 100t tttt */
	3560	{CALT,"%t" }, /* 8a: 100t tttt */
	3561	{CALT,"%t" }, /* 8b: 100t tttt */
	3562	{CALT,"%t" }, /* 8c: 100t tttt */
	3563	{CALT,"%t" }, /* 8d: 100t tttt */
	3564	{CALT,"%t" }, /* 8e: 100t tttt */
	3565	{CALT,"%t" }, /* 8f: 100t tttt */
	3566
	3567	{CALT,"%t" }, /* 90: 100t tttt */
	3568	{CALT,"%t" }, /* 91: 100t tttt */
	3569	{CALT,"%t" }, /* 92: 100t tttt */
	3570	{CALT,"%t" }, /* 93: 100t tttt */
	3571	{CALT,"%t" }, /* 94: 100t tttt */
	3572	{CALT,"%t" }, /* 95: 100t tttt */
	3573	{CALT,"%t" }, /* 96: 100t tttt */
	3574	{CALT,"%t" }, /* 97: 100t tttt */
	3575	{CALT,"%t" }, /* 98: 100t tttt */
	3576	{CALT,"%t" }, /* 99: 100t tttt */
	3577	{CALT,"%t" }, /* 9a: 100t tttt */
	3578	{CALT,"%t" }, /* 9b: 100t tttt */
	3579	{CALT,"%t" }, /* 9c: 100t tttt */
	3580	{CALT,"%t" }, /* 9d: 100t tttt */
	3581	{CALT,"%t" }, /* 9e: 100t tttt */
	3582	{CALT,"%t" }, /* 9f: 100t tttt */
	3583
	3584	{POP,"VA" }, /* a0: 1010 0000 */
	3585	{POP,"BC" }, /* a1: 1010 0001 */
	3586	{POP,"DE" }, /* a2: 1010 0010 */
	3587	{POP,"HL", }, /* a3: 1010 0011 */
	3588	{POP,"EA" }, /* a4: 1010 0100 */
	3589	{DMOV,"EA,BC" }, /* a5: 1010 0101 */
	3590	{DMOV,"EA,DE" }, /* a6: 1010 0110 */
	3591	{DMOV,"EA,HL" }, /* a7: 1010 0111 */
	3592	{INX,"EA" }, /* a8: 1010 1000 */
	3593	{DCX,"EA" }, /* a9: 1010 1001 */
	3594	{EI,0 }, /* aa: 1010 1010 */
	3595	{LDAX,"(DE+%b)" }, /* ab: 1010 1011 dddd dddd */
	3596	{LDAX,"(HL+A)" }, /* ac: 1010 1100 */
	3597	{LDAX,"(HL+B)" }, /* ad: 1010 1101 */
	3598	{LDAX,"(HL+EA)" }, /* ae: 1010 1110 */
	3599	{LDAX,"(HL+%b)" }, /* af: 1010 1111 dddd dddd */
	3600
	3601	{PUSH,"VA" }, /* b0: 1011 0000 */
	3602	{PUSH,"BC" }, /* b1: 1011 0001 */
	3603	{PUSH,"DE" }, /* b2: 1011 0010 */
	3604	{PUSH,"HL", }, /* b3: 1011 0011 */
	3605	{PUSH,"EA" }, /* b4: 1011 0100 */
	3606	{DMOV,"BC,EA" }, /* b5: 1011 0101 */
	3607	{DMOV,"DE,EA" }, /* b6: 1011 0110 */
	3608	{DMOV,"HL,EA" }, /* b7: 1011 0111 */
	3609	{RET,0 }, /* b8: 1011 1000 */
	3610	{RETS,0 }, /* b9: 1011 1001 */
	3611	{DI,0 }, /* ba: 1011 1010 */
	3612	{STAX,"(DE+%b)" }, /* bb: 1011 1011 dddd dddd */
	3613	{STAX,"(HL+A)" }, /* bc: 1011 1100 */
	3614	{STAX,"(HL+B)" }, /* bd: 1011 1101 */
	3615	{STAX,"(HL+EA)" }, /* be: 1011 1110 */
	3616	{STAX,"(HL+%b)" }, /* bf: 1011 1111 dddd dddd */
	3617
	3618	{JR,"%o" }, /* c0: 11oo oooo */
	3619	{JR,"%o" }, /* c1: 11oo oooo */
	3620	{JR,"%o" }, /* c2: 11oo oooo */
	3621	{JR,"%o" }, /* c3: 11oo oooo */
	3622	{JR,"%o" }, /* c4: 11oo oooo */
	3623	{JR,"%o" }, /* c5: 11oo oooo */
	3624	{JR,"%o" }, /* c6: 11oo oooo */
	3625	{JR,"%o" }, /* c7: 11oo oooo */
	3626	{JR,"%o" }, /* c8: 11oo oooo */
	3627	{JR,"%o" }, /* c9: 11oo oooo */
	3628	{JR,"%o" }, /* ca: 11oo oooo */
	3629	{JR,"%o" }, /* cb: 11oo oooo */
	3630	{JR,"%o" }, /* cc: 11oo oooo */
	3631	{JR,"%o" }, /* cd: 11oo oooo */
	3632	{JR,"%o" }, /* ce: 11oo oooo */
	3633	{JR,"%o" }, /* cf: 11oo oooo */
	3634
	3635	{JR,"%o" }, /* d0: 11oo oooo */
	3636	{JR,"%o" }, /* d1: 11oo oooo */
	3637	{JR,"%o" }, /* d2: 11oo oooo */
	3638	{JR,"%o" }, /* d3: 11oo oooo */
	3639	{JR,"%o" }, /* d4: 11oo oooo */
	3640	{JR,"%o" }, /* d5: 11oo oooo */
	3641	{JR,"%o" }, /* d6: 11oo oooo */
	3642	{JR,"%o" }, /* d7: 11oo oooo */
	3643	{JR,"%o" }, /* d8: 11oo oooo */
	3644	{JR,"%o" }, /* d9: 11oo oooo */
	3645	{JR,"%o" }, /* da: 11oo oooo */
	3646	{JR,"%o" }, /* db: 11oo oooo */
	3647	{JR,"%o" }, /* dc: 11oo oooo */
	3648	{JR,"%o" }, /* dd: 11oo oooo */
	3649	{JR,"%o" }, /* de: 11oo oooo */
	3650	{JR,"%o" }, /* df: 11oo oooo */
	3651
	3652	{JR,"%o" }, /* e0: 11oo oooo */
	3653	{JR,"%o" }, /* e1: 11oo oooo */
	3654	{JR,"%o" }, /* e2: 11oo oooo */
	3655	{JR,"%o" }, /* e3: 11oo oooo */
	3656	{JR,"%o" }, /* e4: 11oo oooo */
	3657	{JR,"%o" }, /* e5: 11oo oooo */
	3658	{JR,"%o" }, /* e6: 11oo oooo */
	3659	{JR,"%o" }, /* e7: 11oo oooo */
	3660	{JR,"%o" }, /* e8: 11oo oooo */
	3661	{JR,"%o" }, /* e9: 11oo oooo */
	3662	{JR,"%o" }, /* ea: 11oo oooo */
	3663	{JR,"%o" }, /* eb: 11oo oooo */
	3664	{JR,"%o" }, /* ec: 11oo oooo */
	3665	{JR,"%o" }, /* ed: 11oo oooo */
	3666	{JR,"%o" }, /* ee: 11oo oooo */
	3667	{JR,"%o" }, /* ef: 11oo oooo */
	3668
	3669	{JR,"%o" }, /* f0: 11oo oooo */
	3670	{JR,"%o" }, /* f1: 11oo oooo */
	3671	{JR,"%o" }, /* f2: 11oo oooo */
	3672	{JR,"%o" }, /* f3: 11oo oooo */
	3673	{JR,"%o" }, /* f4: 11oo oooo */
	3674	{JR,"%o" }, /* f5: 11oo oooo */
	3675	{JR,"%o" }, /* f6: 11oo oooo */
	3676	{JR,"%o" }, /* f7: 11oo oooo */
	3677	{JR,"%o" }, /* f8: 11oo oooo */
	3678	{JR,"%o" }, /* f9: 11oo oooo */
	3679	{JR,"%o" }, /* fa: 11oo oooo */
	3680	{JR,"%o" }, /* fb: 11oo oooo */
	3681	{JR,"%o" }, /* fc: 11oo oooo */
	3682	{JR,"%o" }, /* fd: 11oo oooo */
	3683	{JR,"%o" }, /* fe: 11oo oooo */
	3684	{JR,"%o" } /* ff: 11oo oooo */
	3685	};
	3686
	3687	static const struct dasm_s dasmXX_7807[256] =
	3688	{
	3689	{NOP,0 }, /* 00: 0000 0000 */
	3690	{LDAW,"%a" }, /* 01: 0000 0001 oooo oooo */
	3691	{INX,"SP" }, /* 02: 0000 0010 */
	3692	{DCX,"SP" }, /* 03: 0000 0011 */
	3693	{LXI,"SP,%w" }, /* 04: 0000 0100 llll llll hhhh hhhh */
	3694	{ANIW,"%a,%b" }, /* 05: 0000 0101 oooo oooo xxxx xxxx */
	3695	{illegal,0 }, /* 06: */
	3696	{ANI,"A,%b" }, /* 07: 0000 0111 xxxx xxxx */
	3697	{MOV,"A,EAH" }, /* 08: 0000 1000 */
	3698	{MOV,"A,EAL" }, /* 09: 0000 1001 */
	3699	{MOV,"A,B" }, /* 0a: 0000 1010 */
	3700	{MOV,"A,C" }, /* 0b: 0000 1011 */
	3701	{MOV,"A,D" }, /* 0c: 0000 1100 */
	3702	{MOV,"A,E" }, /* 0d: 0000 1101 */
	3703	{MOV,"A,H" }, /* 0e: 0000 1110 */
	3704	{MOV,"A,L" }, /* 0f: 0000 1111 */
	3705
	3706	{BLOCK,"D+" }, /* 10: 0001 0000 / / 7807 */
	3707	{BLOCK,"D-" }, /* 11: 0001 0001 / / 7807 */
	3708	{INX,"BC" }, /* 12: 0001 0010 */
	3709	{DCX,"BC" }, /* 13: 0001 0011 */
	3710	{LXI,"BC,%w" }, /* 14: 0001 0100 llll llll hhhh hhhh */
	3711	{ORIW,"%a,%b" }, /* 15: 0001 0101 oooo oooo xxxx xxxx */
	3712	{XRI,"A,%b" }, /* 16: 0001 0110 xxxx xxxx */
	3713	{ORI,"A,%b" }, /* 17: 0001 0111 xxxx xxxx */
	3714	{MOV,"EAH,A" }, /* 18: 0001 1000 */
	3715	{MOV,"EAL,A" }, /* 19: 0001 1001 */
	3716	{MOV,"B,A" }, /* 1a: 0001 1010 */
	3717	{MOV,"C,A" }, /* 1b: 0001 1011 */
	3718	{MOV,"D,A" }, /* 1c: 0001 1100 */
	3719	{MOV,"E,A" }, /* 1d: 0001 1101 */
	3720	{MOV,"H,A" }, /* 1e: 0001 1110 */
	3721	{MOV,"L,A" }, /* 1f: 0001 1111 */
	3722
	3723	{INRW,"%a" }, /* 20: 0010 0000 oooo oooo */
	3724	{JB,0 }, /* 21: 0010 0001 */
	3725	{INX,"DE" }, /* 22: 0010 0010 */
	3726	{DCX,"DE" }, /* 23: 0010 0011 */
	3727	{LXI,"DE,%w" }, /* 24: 0010 0100 llll llll hhhh hhhh */
	3728	{GTIW,"%a,%b" }, /* 25: 0010 0101 oooo oooo xxxx xxxx */
	3729	{ADINC,"A,%b" }, /* 26: 0010 0110 xxxx xxxx */
	3730	{GTI,"A,%b" }, /* 27: 0010 0111 xxxx xxxx */
	3731	{illegal,0 }, /* 28: 0010 1000 */
	3732	{LDAX,"(BC)" }, /* 29: 0010 1001 */
	3733	{LDAX,"(DE)" }, /* 2a: 0010 1010 */
	3734	{LDAX,"(HL)" }, /* 2b: 0010 1011 */
	3735	{LDAX,"(DE+)" }, /* 2c: 0010 1100 */
	3736	{LDAX,"(HL+)" }, /* 2d: 0010 1101 */
	3737	{LDAX,"(DE-)" }, /* 2e: 0010 1110 */
	3738	{LDAX,"(HL-)" }, /* 2f: 0010 1111 */
	3739
	3740	{DCRW,"%a" }, /* 30: 0011 0000 oooo oooo */
	3741	{AND,"CY,%i" }, /* 31: 0011 0001 bbbb bbbb / / 7807 */
	3742	{INX,"HL", }, /* 32: 0011 0010 */
	3743	{DCX,"HL", }, /* 33: 0011 0011 */
	3744	{LXI,"HL,%w" }, /* 34: 0011 0100 llll llll hhhh hhhh */
	3745	{LTIW,"%a,%b" }, /* 35: 0011 0101 oooo oooo xxxx xxxx */
	3746	{SUINB,"A,%b" }, /* 36: 0011 0110 xxxx xxxx */
	3747	{LTI,"A,%b" }, /* 37: 0011 0111 xxxx xxxx */
	3748	{illegal,0 }, /* 38: */
	3749	{STAX,"(BC)" }, /* 39: 0011 1001 */
	3750	{STAX,"(DE)" }, /* 3a: 0011 1010 */
	3751	{STAX,"(HL)" }, /* 3b: 0011 1011 */
	3752	{STAX,"(DE+)" }, /* 3c: 0011 1100 */
	3753	{STAX,"(HL+)" }, /* 3d: 0011 1101 */
	3754	{STAX,"(DE-)" }, /* 3e: 0011 1110 */
	3755	{STAX,"(HL-)" }, /* 3f: 0011 1111 */
	3756
	3757	{CALL,"%w" }, /* 40: 0100 0000 llll llll hhhh hhhh */
	3758	{INR,"A" }, /* 41: 0100 0001 */
	3759	{INR,"B" }, /* 42: 0100 0010 */
	3760	{INR,"C" }, /* 43: 0100 0011 */
	3761	{LXI,"EA,%w" }, /* 44: 0100 0100 llll llll hhhh hhhh */
	3762	{ONIW,"%a,%b" }, /* 45: 0100 0101 oooo oooo xxxx xxxx */
	3763	{ADI,"A,%b" }, /* 46: 0100 0110 xxxx xxxx */
	3764	{ONI,"A,%b" }, /* 47: 0100 0111 xxxx xxxx */
	3765	{0,dasm48_7807 }, /* 48: prefix */
	3766	{MVIX,"BC,%b" }, /* 49: 0100 1001 xxxx xxxx */
	3767	{MVIX,"DE,%b" }, /* 4a: 0100 1010 xxxx xxxx */
	3768	{MVIX,"HL,%b" }, /* 4b: 0100 1011 xxxx xxxx */
	3769	{0,dasm4C_7807 }, /* 4c: prefix */
	3770	{0,dasm4D_7807 }, /* 4d: prefix */
	3771	{JRE,"%d" }, /* 4e: 0100 111d dddd dddd */
	3772	{JRE,"%d" }, /* 4f: 0100 111d dddd dddd */
	3773	{SKN,"%i" }, /* 50: 0101 0000 bbbb bbbb / / 7807 */
	3774	{DCR,"A" }, /* 51: 0101 0001 */
	3775	{DCR,"B" }, /* 52: 0101 0010 */
	3776	{DCR,"C" }, /* 53: 0101 0011 */
	3777	{JMP,"%w" }, /* 54: 0101 0100 llll llll hhhh hhhh */
	3778	{OFFIW,"%a,%b" }, /* 55: 0101 0101 oooo oooo xxxx xxxx */
	3779	{ACI,"A,%b" }, /* 56: 0101 0110 xxxx xxxx */
	3780	{OFFI,"A,%b" }, /* 57: 0101 0111 xxxx xxxx */
	3781	{SETB,"%i" }, /* 58: 0101 1000 bbbb bbbb / / 7807 */
	3782	{NOT,"%i" }, /* 59: 0101 1001 bbbb bbbb / / 7807 */
	3783	{MOV,"%i,CY" }, /* 5a: 0101 1010 bbbb bbbb / / 7807 */
	3784	{CLR,"%i" }, /* 5b: 0101 1011 bbbb bbbb / / 7807 */
	3785	{OR,"CY,%i" }, /* 5c: 0101 1100 bbbb bbbb / / 7807 */
	3786	{SK,"%i" }, /* 5d: 0101 1101 bbbb bbbb / / 7807 */
	3787	{XOR,"CY,%i" }, /* 5e: 0101 1110 bbbb bbbb / / 7807 */
	3788	{MOV,"CY,%i" }, /* 5f: 0101 1111 bbbb bbbb / / 7807 */
	3789
	3790	{0,dasm60 }, /* 60: prefix */
	3791	{DAA,0 }, /* 61: 0110 0001 */
	3792	{RETI,0 }, /* 62: 0110 0010 */
	3793	{STAW,"%a" }, /* 63: 0110 0011 oooo oooo */
	3794	{0,dasm64_7807 }, /* 64: prefix */
	3795	{NEIW,"%a,%b" }, /* 65: 0110 0101 oooo oooo xxxx xxxx */
	3796	{SUI,"A,%b" }, /* 66: 0110 0110 xxxx xxxx */
	3797	{NEI,"A,%b" }, /* 67: 0110 0111 xxxx xxxx */
	3798	{MVI,"V,%b" }, /* 68: 0110 1000 xxxx xxxx */
	3799	{MVI,"A,%b" }, /* 69: 0110 1001 xxxx xxxx */
	3800	{MVI,"B,%b" }, /* 6a: 0110 1010 xxxx xxxx */
	3801	{MVI,"C,%b" }, /* 6b: 0110 1011 xxxx xxxx */
	3802	{MVI,"D,%b" }, /* 6c: 0110 1100 xxxx xxxx */
	3803	{MVI,"E,%b" }, /* 6d: 0110 1101 xxxx xxxx */
	3804	{MVI,"H,%b" }, /* 6e: 0110 1110 xxxx xxxx */
	3805	{MVI,"L,%b" }, /* 6f: 0110 1111 xxxx xxxx */
	3806
	3807	{0,dasm70 }, /* 70: prefix */
	3808	{MVIW,"%a,%b" }, /* 71: 0111 0001 oooo oooo xxxx xxxx */
	3809	{SOFTI,0 }, /* 72: 0111 0010 */
	3810	{illegal,0 }, /* 73: */
	3811	{0,dasm74 }, /* 74: prefix */
	3812	{EQIW,"%a,%b" }, /* 75: 0111 0101 oooo oooo xxxx xxxx */
	3813	{SBI,"A,%b" }, /* 76: 0111 0110 xxxx xxxx */
	3814	{EQI,"A,%b" }, /* 77: 0111 0111 xxxx xxxx */
	3815	{CALF,"%f" }, /* 78: 0111 1ddd dddd dddd */
	3816	{CALF,"%f" }, /* 79: 0111 1ddd dddd dddd */
	3817	{CALF,"%f" }, /* 7a: 0111 1ddd dddd dddd */
	3818	{CALF,"%f" }, /* 7b: 0111 1ddd dddd dddd */
	3819	{CALF,"%f" }, /* 7c: 0111 1ddd dddd dddd */
	3820	{CALF,"%f" }, /* 7d: 0111 1ddd dddd dddd */
	3821	{CALF,"%f" }, /* 7e: 0111 1ddd dddd dddd */
	3822	{CALF,"%f" }, /* 7f: 0111 1ddd dddd dddd */
	3823
	3824	{CALT,"%t" }, /* 80: 100t tttt */
	3825	{CALT,"%t" }, /* 81: 100t tttt */
	3826	{CALT,"%t" }, /* 82: 100t tttt */
	3827	{CALT,"%t" }, /* 83: 100t tttt */
	3828	{CALT,"%t" }, /* 84: 100t tttt */
	3829	{CALT,"%t" }, /* 85: 100t tttt */
	3830	{CALT,"%t" }, /* 86: 100t tttt */
	3831	{CALT,"%t" }, /* 87: 100t tttt */
	3832	{CALT,"%t" }, /* 88: 100t tttt */
	3833	{CALT,"%t" }, /* 89: 100t tttt */
	3834	{CALT,"%t" }, /* 8a: 100t tttt */
	3835	{CALT,"%t" }, /* 8b: 100t tttt */
	3836	{CALT,"%t" }, /* 8c: 100t tttt */
	3837	{CALT,"%t" }, /* 8d: 100t tttt */
	3838	{CALT,"%t" }, /* 8e: 100t tttt */
	3839	{CALT,"%t" }, /* 8f: 100t tttt */
	3840
	3841	{CALT,"%t" }, /* 90: 100t tttt */
	3842	{CALT,"%t" }, /* 91: 100t tttt */
	3843	{CALT,"%t" }, /* 92: 100t tttt */
	3844	{CALT,"%t" }, /* 93: 100t tttt */
	3845	{CALT,"%t" }, /* 94: 100t tttt */
	3846	{CALT,"%t" }, /* 95: 100t tttt */
	3847	{CALT,"%t" }, /* 96: 100t tttt */
	3848	{CALT,"%t" }, /* 97: 100t tttt */
	3849	{CALT,"%t" }, /* 98: 100t tttt */
	3850	{CALT,"%t" }, /* 99: 100t tttt */
	3851	{CALT,"%t" }, /* 9a: 100t tttt */
	3852	{CALT,"%t" }, /* 9b: 100t tttt */
	3853	{CALT,"%t" }, /* 9c: 100t tttt */
	3854	{CALT,"%t" }, /* 9d: 100t tttt */
	3855	{CALT,"%t" }, /* 9e: 100t tttt */
	3856	{CALT,"%t" }, /* 9f: 100t tttt */
	3857
	3858	{POP,"VA" }, /* a0: 1010 0000 */
	3859	{POP,"BC" }, /* a1: 1010 0001 */
	3860	{POP,"DE" }, /* a2: 1010 0010 */
	3861	{POP,"HL", }, /* a3: 1010 0011 */
	3862	{POP,"EA" }, /* a4: 1010 0100 */
	3863	{DMOV,"EA,BC" }, /* a5: 1010 0101 */
	3864	{DMOV,"EA,DE" }, /* a6: 1010 0110 */
	3865	{DMOV,"EA,HL" }, /* a7: 1010 0111 */
	3866	{INX,"EA" }, /* a8: 1010 1000 */
	3867	{DCX,"EA" }, /* a9: 1010 1001 */
	3868	{EI,0 }, /* aa: 1010 1010 */
	3869	{LDAX,"(DE+%b)" }, /* ab: 1010 1011 dddd dddd */
	3870	{LDAX,"(HL+A)" }, /* ac: 1010 1100 */
	3871	{LDAX,"(HL+B)" }, /* ad: 1010 1101 */
	3872	{LDAX,"(HL+EA)" }, /* ae: 1010 1110 */
	3873	{LDAX,"(HL+%b)" }, /* af: 1010 1111 dddd dddd */
	3874
	3875	{PUSH,"VA" }, /* b0: 1011 0000 */
	3876	{PUSH,"BC" }, /* b1: 1011 0001 */
	3877	{PUSH,"DE" }, /* b2: 1011 0010 */
	3878	{PUSH,"HL", }, /* b3: 1011 0011 */
	3879	{PUSH,"EA" }, /* b4: 1011 0100 */
	3880	{DMOV,"BC,EA" }, /* b5: 1011 0101 */
	3881	{DMOV,"DE,EA" }, /* b6: 1011 0110 */
	3882	{DMOV,"HL,EA" }, /* b7: 1011 0111 */
	3883	{RET,0 }, /* b8: 1011 1000 */
	3884	{RETS,0 }, /* b9: 1011 1001 */
	3885	{DI,0 }, /* ba: 1011 1010 */
	3886	{STAX,"(DE+%b)" }, /* bb: 1011 1011 dddd dddd */
	3887	{STAX,"(HL+A)" }, /* bc: 1011 1100 */
	3888	{STAX,"(HL+B)" }, /* bd: 1011 1101 */
	3889	{STAX,"(HL+EA)" }, /* be: 1011 1110 */
	3890	{STAX,"(HL+%b)" }, /* bf: 1011 1111 dddd dddd */
	3891
	3892	{JR,"%o" }, /* c0: 11oo oooo */
	3893	{JR,"%o" }, /* c1: 11oo oooo */
	3894	{JR,"%o" }, /* c2: 11oo oooo */
	3895	{JR,"%o" }, /* c3: 11oo oooo */
	3896	{JR,"%o" }, /* c4: 11oo oooo */
	3897	{JR,"%o" }, /* c5: 11oo oooo */
	3898	{JR,"%o" }, /* c6: 11oo oooo */
	3899	{JR,"%o" }, /* c7: 11oo oooo */
	3900	{JR,"%o" }, /* c8: 11oo oooo */
	3901	{JR,"%o" }, /* c9: 11oo oooo */
	3902	{JR,"%o" }, /* ca: 11oo oooo */
	3903	{JR,"%o" }, /* cb: 11oo oooo */
	3904	{JR,"%o" }, /* cc: 11oo oooo */
	3905	{JR,"%o" }, /* cd: 11oo oooo */
	3906	{JR,"%o" }, /* ce: 11oo oooo */
	3907	{JR,"%o" }, /* cf: 11oo oooo */
	3908
	3909	{JR,"%o" }, /* d0: 11oo oooo */
	3910	{JR,"%o" }, /* d1: 11oo oooo */
	3911	{JR,"%o" }, /* d2: 11oo oooo */
	3912	{JR,"%o" }, /* d3: 11oo oooo */
	3913	{JR,"%o" }, /* d4: 11oo oooo */
	3914	{JR,"%o" }, /* d5: 11oo oooo */
	3915	{JR,"%o" }, /* d6: 11oo oooo */
	3916	{JR,"%o" }, /* d7: 11oo oooo */
	3917	{JR,"%o" }, /* d8: 11oo oooo */
	3918	{JR,"%o" }, /* d9: 11oo oooo */
	3919	{JR,"%o" }, /* da: 11oo oooo */
	3920	{JR,"%o" }, /* db: 11oo oooo */
	3921	{JR,"%o" }, /* dc: 11oo oooo */
	3922	{JR,"%o" }, /* dd: 11oo oooo */
	3923	{JR,"%o" }, /* de: 11oo oooo */
	3924	{JR,"%o" }, /* df: 11oo oooo */
	3925
	3926	{JR,"%o" }, /* e0: 11oo oooo */
	3927	{JR,"%o" }, /* e1: 11oo oooo */
	3928	{JR,"%o" }, /* e2: 11oo oooo */
	3929	{JR,"%o" }, /* e3: 11oo oooo */
	3930	{JR,"%o" }, /* e4: 11oo oooo */
	3931	{JR,"%o" }, /* e5: 11oo oooo */
	3932	{JR,"%o" }, /* e6: 11oo oooo */
	3933	{JR,"%o" }, /* e7: 11oo oooo */
	3934	{JR,"%o" }, /* e8: 11oo oooo */
	3935	{JR,"%o" }, /* e9: 11oo oooo */
	3936	{JR,"%o" }, /* ea: 11oo oooo */
	3937	{JR,"%o" }, /* eb: 11oo oooo */
	3938	{JR,"%o" }, /* ec: 11oo oooo */
	3939	{JR,"%o" }, /* ed: 11oo oooo */
	3940	{JR,"%o" }, /* ee: 11oo oooo */
	3941	{JR,"%o" }, /* ef: 11oo oooo */
	3942
	3943	{JR,"%o" }, /* f0: 11oo oooo */
	3944	{JR,"%o" }, /* f1: 11oo oooo */
	3945	{JR,"%o" }, /* f2: 11oo oooo */
	3946	{JR,"%o" }, /* f3: 11oo oooo */
	3947	{JR,"%o" }, /* f4: 11oo oooo */
	3948	{JR,"%o" }, /* f5: 11oo oooo */
	3949	{JR,"%o" }, /* f6: 11oo oooo */
	3950	{JR,"%o" }, /* f7: 11oo oooo */
	3951	{JR,"%o" }, /* f8: 11oo oooo */
	3952	{JR,"%o" }, /* f9: 11oo oooo */
	3953	{JR,"%o" }, /* fa: 11oo oooo */
	3954	{JR,"%o" }, /* fb: 11oo oooo */
	3955	{JR,"%o" }, /* fc: 11oo oooo */
	3956	{JR,"%o" }, /* fd: 11oo oooo */
	3957	{JR,"%o" }, /* fe: 11oo oooo */
	3958	{JR,"%o" } /* ff: 11oo oooo */
	3959	};
	3960
	3961	/*********************************************************
	3962	*
	3963	* uPD7801
	3964	*
	3965	*********************************************************/
	3966
	3967	static const struct dasm_s dasm48_7801[256] = {
	3968	/* 0x00 - 0x3F */
	3969	{ SKIT, "F0" }, { SKIT, "FT" }, { SKIT, "F1" }, { SKIT, "F2" },
	3970	{ SKIT, "FS" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	3971	{ illegal, 0 }, { illegal, 0 }, { SK, "CY" }, { illegal, 0 },
	3972	{ SK, "Z" }, { illegal, 0 }, { PUSH, "VA" }, { POP, "VA" },
	3973
	3974	{ SKNIT, "F0" }, { SKNIT, "FT" }, { SKNIT, "F1" }, { SKNIT, "F2" },
	3975	{ SKNIT, "FS" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	3976	{ illegal, 0 }, { illegal, 0 }, { SKN, "CY" }, { illegal, 0 },
	3977	{ SKN, "Z" }, { illegal, 0 }, { PUSH, "BC" }, { POP, "BC" },
	3978
	3979	{ EI, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	3980	{ DI, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	3981	{ illegal, 0 }, { illegal, 0 }, { CLC, 0 }, { STC, 0 },
	3982	{ PER, 0 }, { PEX, 0 }, { PUSH, "DE" }, { POP, "DE" },
	3983
	3984	{ RLL, "A" }, { RLR, "A" }, { RLL, "C" }, { RLR, "C" },
	3985	{ SLL, "A" }, { SLR, "A" }, { SLL, "C" }, { SLR, "C" },
	3986	{ RLD, 0 }, { RRD, 0 }, { illegal, 0 }, { illegal, 0 },
	3987	{ PER, 0 }, { illegal, 0 }, { PUSH, "HL" }, { POP, "HL" },
	3988
	3989	/* 0x40 - 0x7F */
	3990	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	3991	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	3992	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	3993	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	3994
	3995	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	3996	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	3997	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	3998	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	3999
	4000	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4001	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4002	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4003	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4004
	4005	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4006	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4007	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4008	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4009
	4010	/* 0x80 - 0xBF */
	4011	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4012	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4013	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4014	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4015
	4016	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4017	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4018	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4019	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4020
	4021	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4022	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4023	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4024	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4025
	4026	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4027	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4028	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4029	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4030
	4031	/* 0xC0 - 0xFF */
	4032	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4033	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4034	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4035	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4036
	4037	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4038	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4039	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4040	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4041
	4042	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4043	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4044	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4045	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4046
	4047	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4048	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4049	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4050	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
	4051	};
	4052
	4053	static const struct dasm_s dasm4c_7801[256] = {
	4054	/* 0x00 - 0x3F */
	4055	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4056	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4057	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4058	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4059
	4060	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4061	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4062	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4063	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4064
	4065	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4066	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4067	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4068	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4069
	4070	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4071	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4072	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4073	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4074
	4075	/* 0x40 - 0x7F */
	4076	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4077	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4078	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4079	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4080
	4081	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4082	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4083	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4084	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4085
	4086	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4087	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4088	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4089	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4090
	4091	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4092	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4093	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4094	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4095
	4096	/* 0x80 - 0xBF */
	4097	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4098	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4099	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4100	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4101
	4102	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4103	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4104	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4105	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4106
	4107	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4108	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4109	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4110	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4111
	4112	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4113	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4114	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4115	{ IN, 0 }, { IN, 0 }, { IN, 0 }, { IN, 0 },
	4116
	4117	/* 0xC0 - 0xFF */
	4118	{ MOV, "A,PA" }, { MOV, "A,PB" }, { MOV, "A,PC" }, { MOV, "A,MK" },
	4119	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4120	{ MOV, "A,S" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4121	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4122
	4123	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4124	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4125	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4126	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4127
	4128	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4129	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4130	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4131	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4132
	4133	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4134	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4135	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4136	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
	4137	};
	4138
	4139	static const struct dasm_s dasm4d_7801[256] = {
	4140	/* 0x00 - 0x3F */
	4141	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4142	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4143	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4144	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4145
	4146	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4147	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4148	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4149	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4150
	4151	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4152	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4153	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4154	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4155
	4156	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4157	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4158	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4159	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4160
	4161	/* 0x40 - 0x7F */
	4162	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4163	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4164	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4165	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4166
	4167	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4168	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4169	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4170	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4171
	4172	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4173	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4174	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4175	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4176
	4177	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4178	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4179	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4180	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4181
	4182	/* 0x80 - 0xBF */
	4183	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4184	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4185	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4186	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4187
	4188	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4189	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4190	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4191	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4192
	4193	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4194	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4195	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4196	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4197
	4198	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4199	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4200	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4201	{ OUT, 0 }, { OUT, 0 }, { OUT, 0 }, { OUT, 0 },
	4202
	4203	/* 0xC0 - 0xFF */
	4204	{ MOV, "PA,A" }, { MOV, "PB,A" }, { MOV, "PC,A" }, { MOV, "MK,A" },
	4205	{ MOV, "MB,A" }, { MOV, "MC,A" }, { MOV, "TM0,A" }, { MOV, "TM1,A" },
	4206	{ MOV, "S,A" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4207	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4208
	4209	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4210	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4211	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4212	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4213
	4214	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4215	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4216	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4217	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4218
	4219	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4220	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4221	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4222	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
	4223	};
	4224
	4225	static const struct dasm_s dasm60_7801[256] = {
	4226	/* 0x00 - 0x3F */
	4227	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4228	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4229	{ ANA, "V,A" }, { ANA, "A,A" }, { ANA, "B,A" }, { ANA, "C,A" },
	4230	{ ANA, "D,A" }, { ANA, "E,A" }, { ANA, "H,A" }, { ANA, "L,A" },
	4231
	4232	{ XRA, "V,A" }, { XRA, "A,A" }, { XRA, "B,A" }, { XRA, "C,A" },
	4233	{ XRA, "D,A" }, { XRA, "E,A" }, { XRA, "H,A" }, { XRA, "L,A" },
	4234	{ ORA, "V,A" }, { ORA, "A,A" }, { ORA, "B,A" }, { ORA, "C,A" },
	4235	{ ORA, "D,A" }, { ORA, "E,A" }, { ORA, "H,A" }, { ORA, "L,A" },
	4236
	4237	{ ADDNC, "V,A" }, { ADDNC, "A,A" }, { ADDNC, "B,A" }, { ADDNC, "C,A" },
	4238	{ ADDNC, "D,A" }, { ADDNC, "E,A" }, { ADDNC, "H,A" }, { ADDNC, "L,A" },
	4239	{ GTA, "V,A" }, { GTA, "A,A" }, { GTA, "B,A" }, { GTA, "C,A" },
	4240	{ GTA, "D,A" }, { GTA, "E,A" }, { GTA, "H,A" }, { GTA, "L,A" },
	4241
	4242	{ SUBNB, "V,A" }, { SUBNB, "A,A" }, { SUBNB, "B,A" }, { SUBNB, "C,A" },
	4243	{ SUBNB, "D,A" }, { SUBNB, "E,A" }, { SUBNB, "H,A" }, { SUBNB, "L,A" },
	4244	{ LTA, "V,A" }, { LTA, "A,A" }, { LTA, "B,A" }, { LTA, "C,A" },
	4245	{ LTA, "D,A" }, { LTA, "E,A" }, { LTA, "H,A" }, { LTA, "L,A" },
	4246
	4247	/* 0x40 - 0x7F */
	4248	{ ADD, "V,A" }, { ADD, "A,A" }, { ADD, "B,A" }, { ADD, "C,A" },
	4249	{ ADD, "D,A" }, { ADD, "E,A" }, { ADD, "H,A" }, { ADD, "L,A" },
	4250	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4251	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4252
	4253	{ ADC, "V,A" }, { ADC, "A,A" }, { ADC, "B,A" }, { ADC, "C,A" },
	4254	{ ADC, "D,A" }, { ADC, "E,A" }, { ADC, "H,A" }, { ADC, "L,A" },
	4255	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4256	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4257
	4258	{ SUB, "V,A" }, { SUB, "A,A" }, { SUB, "B,A" }, { SUB, "C,A" },
	4259	{ SUB, "D,A" }, { SUB, "E,A" }, { SUB, "H,A" }, { SUB, "L,A" },
	4260	{ NEA, "V,A" }, { NEA, "A,A" }, { NEA, "B,A" }, { NEA, "C,A" },
	4261	{ NEA, "D,A" }, { NEA, "E,A" }, { NEA, "H,A" }, { NEA, "L,A" },
	4262
	4263	{ SBB, "V,A" }, { SBB, "A,A" }, { SBB, "B,A" }, { SBB, "C,A" },
	4264	{ SBB, "D,A" }, { SBB, "E,A" }, { SBB, "H,A" }, { SBB, "L,A" },
	4265	{ EQA, "V,A" }, { EQA, "A,A" }, { EQA, "B,A" }, { EQA, "C,A" },
	4266	{ EQA, "D,A" }, { EQA, "E,A" }, { EQA, "H,A" }, { EQA, "L,A" },
	4267
	4268	/* 0x80 - 0xBF */
	4269	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4270	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4271	{ ANA, "A,V" }, { ANA, "A,A" }, { ANA, "A,B" }, { ANA, "A,C" },
	4272	{ ANA, "A,D" }, { ANA, "A,E" }, { ANA, "A,H" }, { ANA, "A,L" },
	4273
	4274	{ XRA, "A,V" }, { XRA, "A,A" }, { XRA, "A,B" }, { XRA, "A,C" },
	4275	{ XRA, "A,D" }, { XRA, "A,E" }, { XRA, "A,H" }, { XRA, "A,L" },
	4276	{ ORA, "A,V" }, { ORA, "A,A" }, { ORA, "A,B" }, { ORA, "A,C" },
	4277	{ ORA, "A,D" }, { ORA, "A,E" }, { ORA, "A,H" }, { ORA, "A,L" },
	4278
	4279	{ ADDNC, "A,V" }, { ADDNC, "A,A" }, { ADDNC, "A,B" }, { ADDNC, "A,C" },
	4280	{ ADDNC, "A,D" }, { ADDNC, "A,E" }, { ADDNC, "A,H" }, { ADDNC, "A,L" },
	4281	{ GTA, "A,V" }, { GTA, "A,A" }, { GTA, "A,B" }, { GTA, "A,C" },
	4282	{ GTA, "A,D" }, { GTA, "A,E" }, { GTA, "A,H" }, { GTA, "A,L" },
	4283
	4284	{ SUBNB, "A,V" }, { SUBNB, "A,A" }, { SUBNB, "A,B" }, { SUBNB, "A,C" },
	4285	{ SUBNB, "A,D" }, { SUBNB, "A,E" }, { SUBNB, "A,H" }, { SUBNB, "A,L" },
	4286	{ LTA, "A,V" }, { LTA, "A,A" }, { LTA, "A,B" }, { LTA, "A,C" },
	4287	{ LTA, "A,D" }, { LTA, "A,E" }, { LTA, "A,H" }, { LTA, "A,L" },
	4288
	4289	/* 0xC0 - 0xFF */
	4290	{ ADD, "A,V" }, { ADD, "A,A" }, { ADD, "A,B" }, { ADD, "A,C" },
	4291	{ ADD, "A,D" }, { ADD, "A,E" }, { ADD, "A,H" }, { ADD, "A,L" },
	4292	{ ONA, "A,V" }, { ONA, "A,A" }, { ONA, "A,B" }, { ONA, "A,C" },
	4293	{ ONA, "A,D" }, { ONA, "A,E" }, { ONA, "A,H" }, { ONA, "A,L" },
	4294
	4295	{ ADC, "A,V" }, { ADC, "A,A" }, { ADC, "A,B" }, { ADC, "A,C" },
	4296	{ ADC, "A,D" }, { ADC, "A,E" }, { ADC, "A,H" }, { ADC, "A,L" },
	4297	{ OFFA, "A,V" }, { OFFA, "A,A" }, { OFFA, "A,B" }, { OFFA, "A,C" },
	4298	{ OFFA, "A,D" }, { OFFA, "A,E" }, { OFFA, "A,H" }, { OFFA, "A,L" },
	4299
	4300	{ SUB, "A,V" }, { SUB, "A,A" }, { SUB, "A,B" }, { SUB, "A,C" },
	4301	{ SUB, "A,D" }, { SUB, "A,E" }, { SUB, "A,H" }, { SUB, "A,L" },
	4302	{ NEA, "A,V" }, { NEA, "A,A" }, { NEA, "A,B" }, { NEA, "A,C" },
	4303	{ NEA, "A,D" }, { NEA, "A,E" }, { NEA, "A,H" }, { NEA, "A,L" },
	4304
	4305	{ SBB, "A,V" }, { SBB, "A,A" }, { SBB, "A,B" }, { SBB, "A,C" },
	4306	{ SBB, "A,D" }, { SBB, "A,E" }, { SBB, "A,H" }, { SBB, "A,L" },
	4307	{ EQA, "A,V" }, { EQA, "A,A" }, { EQA, "A,B" }, { EQA, "A,C" },
	4308	{ EQA, "A,D" }, { EQA, "A,E" }, { EQA, "A,H" }, { EQA, "A,L" }
	4309	};
	4310
	4311	static const struct dasm_s dasm64_7801[256] = {
	4312	/* 0x00 - 0x3F */
	4313	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4314	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4315	{ ANI, "V,%b" }, { ANI, "A,%b" }, { ANI, "B,%b" }, { ANI, "C,%b" },
	4316	{ ANI, "D,%b" }, { ANI, "E,%b" }, { ANI, "H,%b" }, { ANI, "L,%b" },
	4317
	4318	{ XRI, "V,%b" }, { XRI, "A,%b" }, { XRI, "B,%b" }, { XRI, "C,%b" },
	4319	{ XRI, "D,%b" }, { XRI, "E,%b" }, { XRI, "H,%b" }, { XRI, "L,%b" },
	4320	{ ORI, "V,%b" }, { ORI, "A,%b" }, { ORI, "B,%b" }, { ORI, "C,%b" },
	4321	{ ORI, "D,%b" }, { ORI, "E,%b" }, { ORI, "H,%b" }, { ORI, "L,%b" },
	4322
	4323	{ ADINC, "V,%b" }, { ADINC, "A,%b" }, { ADINC, "B,%b" }, { ADINC, "C,%b" },
	4324	{ ADINC, "D,%b" }, { ADINC, "E,%b" }, { ADINC, "H,%b" }, { ADINC, "L,%b" },
	4325	{ GTI, "V,%b" }, { GTI, "A,%b" }, { GTI, "B,%b" }, { GTI, "C,%b" },
	4326	{ GTI, "D,%b" }, { GTI, "E,%b" }, { GTI, "H,%b" }, { GTI, "L,%b" },
	4327
	4328	{ SUINB, "V,%b" }, { SUINB, "A,%b" }, { SUINB, "B,%b" }, { SUINB, "C,%b" },
	4329	{ SUINB, "D,%b" }, { SUINB, "E,%b" }, { SUINB, "H,%b" }, { SUINB, "L,%b" },
	4330	{ LTI, "V,%b" }, { LTI, "A,%b" }, { LTI, "B,%b" }, { LTI, "C,%b" },
	4331	{ LTI, "D,%b" }, { LTI, "E,%b" }, { LTI, "H,%b" }, { LTI, "L,%b" },
	4332
	4333	/* 0x40 - 0x7F */
	4334	{ ADI, "V,%b" }, { ADI, "A,%b" }, { ADI, "B,%b" }, { ADI, "C,%b" },
	4335	{ ADI, "D,%b" }, { ADI, "E,%b" }, { ADI, "H,%b" }, { ADI, "L,%b" },
	4336	{ ONI, "V,%b" }, { ONI, "A,%b" }, { ONI, "B,%b" }, { ONI, "C,%b" },
	4337	{ ONI, "D,%b" }, { ONI, "E,%b" }, { ONI, "H,%b" }, { ONI, "L,%b" },
	4338
	4339	{ ACI, "V,%b" }, { ACI, "A,%b" }, { ACI, "B,%b" }, { ACI, "C,%b" },
	4340	{ ACI, "D,%b" }, { ACI, "E,%b" }, { ACI, "H,%b" }, { ACI, "L,%b" },
	4341	{ OFFI, "V,%b" }, { OFFI, "A,%b" }, { OFFI, "B,%b" }, { OFFI, "C,%b" },
	4342	{ OFFI, "D,%b" }, { OFFI, "E,%b" }, { OFFI, "H,%b" }, { OFFI, "L,%b" },
	4343
	4344	{ SUI, "V,%b" }, { SUI, "A,%b" }, { SUI, "B,%b" }, { SUI, "C,%b" },
	4345	{ SUI, "D,%b" }, { SUI, "E,%b" }, { SUI, "H,%b" }, { SUI, "L,%b" },
	4346	{ NEI, "V,%b" }, { NEI, "A,%b" }, { NEI, "B,%b" }, { NEI, "C,%b" },
	4347	{ NEI, "D,%b" }, { NEI, "E,%b" }, { NEI, "H,%b" }, { NEI, "L,%b" },
	4348
	4349	{ SBI, "V,%b" }, { SBI, "A,%b" }, { SBI, "B,%b" }, { SBI, "C,%b" },
	4350	{ SBI, "D,%b" }, { SBI, "E,%b" }, { SBI, "H,%b" }, { SBI, "L,%b" },
	4351	{ EQI, "V,%b" }, { EQI, "A,%b" }, { EQI, "B,%b" }, { EQI, "C,%b" },
	4352	{ EQI, "D,%b" }, { EQI, "E,%b" }, { EQI, "H,%b" }, { EQI, "L,%b" },
	4353
	4354	/* 0x80 - 0xBF */
	4355	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4356	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4357	{ ANI, "PA,%b" }, { ANI, "PB,%b" }, { ANI, "PC,%b" }, { ANI, "MK,%b" },
	4358	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4359
	4360	{ XRI, "PA,%b" }, { XRI, "PB,%b" }, { XRI, "PC,%b" }, { XRI, "MK,%b" },
	4361	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4362	{ ORI, "PA,%b" }, { ORI, "PB,%b" }, { ORI, "PC,%b" }, { ORI, "MK,%b" },
	4363	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4364
	4365	{ ADINC, "PA,%b" }, { ADINC, "PB,%b" }, { ADINC, "PC,%b" }, { ADINC, "MK,%b" },
	4366	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4367	{ GTI, "PA,%b" }, { GTI, "PB,%b" }, { GTI, "PC,%b" }, { GTI, "MK,%b" },
	4368	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4369
	4370	{ SUINB, "PA,%b" }, { SUINB, "PB,%b" }, { SUINB, "PC,%b" }, { SUINB, "MK,%b" },
	4371	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4372	{ LTI, "PA,%b" }, { LTI, "PB,%b" }, { LTI, "PC,%b" }, { LTI, "MK,%b" },
	4373	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4374
	4375	/* 0xC0 - 0xFF */
	4376	{ ADI, "PA,%b" }, { ADI, "PB,%b" }, { ADI, "PC,%b" }, { ADI, "MK,%b" },
	4377	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4378	{ ONI, "PA,%b" }, { ONI, "PB,%b" }, { ONI, "PC,%b" }, { ONI, "MK,%b" },
	4379	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4380
	4381	{ ACI, "PA,%b" }, { ACI, "PB,%b" }, { ACI, "PC,%b" }, { ACI, "MK,%b" },
	4382	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4383	{ OFFI, "PA,%b" }, { OFFI, "PB,%b" }, { OFFI, "PC,%b" }, { OFFI, "MK,%b" },
	4384	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4385
	4386	{ SUI, "PA,%b" }, { SUI, "PB,%b" }, { SUI, "PC,%b" }, { SUI, "MK,%b" },
	4387	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4388	{ NEI, "PA,%b" }, { NEI, "PB,%b" }, { NEI, "PC,%b" }, { NEI, "MK,%b" },
	4389	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4390
	4391	{ SBI, "PA,%b" }, { SBI, "PB,%b" }, { SBI, "PC,%b" }, { SBI, "MK,%b" },
	4392	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4393	{ EQI, "PA,%b" }, { EQI, "PB,%b" }, { EQI, "PC,%b" }, { EQI, "MK,%b" },
	4394	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
	4395	};
	4396
	4397	static const struct dasm_s dasm70_7801[256] = {
	4398	/* 0x00 - 0x3F */
	4399	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4400	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4401	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4402	{ illegal, 0 }, { illegal, 0 }, { SSPD, "%w" }, { LSPD, "%w" },
	4403
	4404	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4405	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4406	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4407	{ illegal, 0 }, { illegal, 0 }, { SBCD, "%w" }, { LBCD, "%w" },
	4408
	4409	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4410	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4411	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4412	{ illegal, 0 }, { illegal, 0 }, { SDED, "%w" }, { LDED, "%w" },
	4413
	4414	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4415	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4416	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4417	{ illegal, 0 }, { illegal, 0 }, { SHLD, "%w" }, { LHLD, "%w" },
	4418
	4419	/* 0x40 - 0x7F */
	4420	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4421	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4422	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4423	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4424
	4425	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4426	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4427	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4428	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4429
	4430	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4431	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4432	{ MOV, "V,%w" }, { MOV, "A,%w" }, { MOV, "B,%w" }, { MOV, "C,%w" },
	4433	{ MOV, "D,%w" }, { MOV, "E,%w" }, { MOV, "H,%w" }, { MOV, "L,%w" },
	4434
	4435	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4436	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4437	{ MOV, "%w,V" }, { MOV, "%w,A" }, { MOV, "%w,B" }, { MOV, "%w,C" },
	4438	{ MOV, "%w,D" }, { MOV, "%w,E" }, { MOV, "%w,H" }, { MOV, "%w,L" },
	4439
	4440	/* 0x80 - 0xBF */
	4441	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4442	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4443	{ illegal, 0 }, { ANAX, "BC" }, { ANAX, "DE" }, { ANAX, "HL" },
	4444	{ ANAX, "DE+" }, { ANAX, "HL+" }, { ANAX, "DE-" }, { ANAX, "HL-" },
	4445
	4446	{ illegal, 0 }, { XRAX, "BC" }, { XRAX, "DE" }, { XRAX, "HL" },
	4447	{ XRAX, "DE+" }, { XRAX, "HL+" }, { XRAX, "DE-" }, { XRAX, "HL-" },
	4448	{ illegal, 0 }, { ORAX, "BC" }, { ORAX, "DE" }, { ORAX, "HL" },
	4449	{ ORAX, "DE+" }, { ORAX, "HL+" }, { ORAX, "DE-" }, { ORAX, "HL-" },
	4450
	4451	{ illegal, 0 }, { ADDNCX, "BC" }, { ADDNCX, "DE" }, { ADDNCX, "HL" },
	4452	{ ADDNCX, "DE+" }, { ADDNCX, "HL+" }, { ADDNCX, "DE-" }, { ADDNCX, "HL-" },
	4453	{ illegal, 0 }, { GTAX, "BC" }, { GTAX, "DE" }, { GTAX, "HL" },
	4454	{ GTAX, "DE+" }, { GTAX, "HL+" }, { GTAX, "DE-" }, { GTAX, "HL-" },
	4455
	4456	{ illegal, 0 }, { SUBNBX, "BC" }, { SUBNBX, "DE" }, { SUBNBX, "HL" },
	4457	{ SUBNBX, "DE+" }, { SUBNBX, "HL+" }, { SUBNBX, }, { SUBNBX, "HL-" },
	4458	{ illegal, 0 }, { LTAX, "BC" }, { LTAX, "DE" }, { LTAX, "HL" },
	4459	{ LTAX, "DE+" }, { LTAX, "HL+" }, { LTAX, "DE-" }, { LTAX, "HL-" },
	4460
	4461	/* 0xC0 - 0xFF */
	4462	{ illegal, 0 }, { ADDX, "BC" }, { ADDX, "DE" }, { ADDX, "HL" },
	4463	{ ADDX, "DE+" }, { ADDX, "HL+" }, { ADDX, "DE-" }, { ADDX, "HL-" },
	4464	{ illegal, 0 }, { ONAX, "BC" }, { ONAX, "DE" }, { ONAX, "HL" },
	4465	{ ONAX, "DE+" }, { ONAX, "HL+" }, { ONAX, "DE-" }, { ONAX, "HL-" },
	4466
	4467	{ illegal, 0 }, { ADCX, "BC" }, { ADCX, "DE" }, { ADCX, "HL" },
	4468	{ ADCX, "DE+" }, { ADCX, "HL+" }, { ADCX, "DE-" }, { ADCX, "HL-" },
	4469	{ illegal, 0 }, { OFFAX, "BC" }, { OFFAX, "DE" }, { OFFAX, "HL" },
	4470	{ OFFAX, "DE+" }, { OFFAX, "HL+" }, { OFFAX, "DE-" }, { OFFAX, "HL-" },
	4471
	4472	{ illegal, 0 }, { SUBX, "BC" }, { SUBX, "DE" }, { SUBX, "HL" },
	4473	{ SUBX, "DE+" }, { SUBX, "HL+" }, { SUBX, "DE-" }, { SUBX, "HL-" },
	4474	{ illegal, 0 }, { NEAX, "BC" }, { NEAX, "DE" }, { NEAX, "HL" },
	4475	{ NEAX, "DE+" }, { NEAX, "HL+" }, { NEAX, "DE-" }, { NEAX, "HL-" },
	4476
	4477	{ illegal, 0 }, { SBBX, "BC" }, { SBBX, "DE" }, { SBBX, "HL" },
	4478	{ SBBX, "DE+" }, { SBBX, "HL+" }, { SBBX, "DE-" }, { SBBX, "HL-" },
	4479	{ illegal, 0 }, { EQAX, "BC" }, { EQAX, "DE" }, { EQAX, "HL" },
	4480	{ EQAX, "DE+" }, { EQAX, "HL+" }, { EQAX, "DE-" }, { EQAX, "HL-" },
	4481	};
	4482
	4483	static const struct dasm_s dasm74_7801[256] = {
	4484	/* 0x00 - 0x3F */
	4485	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4486	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4487	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4488	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4489
	4490	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4491	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4492	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4493	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4494
	4495	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4496	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4497	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4498	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4499
	4500	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4501	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4502	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4503	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4504
	4505	/* 0x40 - 0x7F */
	4506	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4507	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4508	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4509	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4510
	4511	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4512	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4513	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4514	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4515
	4516	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4517	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4518	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4519	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4520
	4521	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4522	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4523	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4524	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4525
	4526	/* 0x80 - 0xBF */
	4527	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4528	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4529	{ ANAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4530	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4531
	4532	{ XRAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4533	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4534	{ ORAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4535	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4536
	4537	{ ADDNCW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4538	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4539	{ GTAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4540	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4541
	4542	{ SUBNBW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4543	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4544	{ LTAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4545	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4546
	4547	/* 0xC0 - 0xFF */
	4548	{ ADDW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4549	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4550	{ ONAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4551	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4552
	4553	{ ADCW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4554	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4555	{ OFFAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4556	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4557
	4558	{ SUBW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4559	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4560	{ NEAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4561	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4562
	4563	{ SBBW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4564	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4565	{ EQAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4566	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
	4567	};
	4568
	4569	static const struct dasm_s dasmXX_7801[256] = {
	4570	/* 0x00 - 0x3F */
	4571	{ NOP, 0 }, { HALT, 0 }, { INX, "SP" }, { DCX, "SP" },
	4572	{ LXI, "SP,%w" }, { ANIW, "%a,%b" }, { illegal, 0 }, { ANI, "A,%b" },
	4573	{ RET, 0 }, { SIO, 0 }, { MOV, "A,B" }, { MOV, "A,C" },
	4574	{ MOV, "A,D" }, { MOV, "A,E" }, { MOV, "A,H" }, { MOV, "A,L" },
	4575
	4576	{ EX, 0 }, { EXX, 0 }, { INX, "BC" }, { DCX, "BC" },
	4577	{ LXI, "BC,%w" }, { ORIW, "%a,%b" }, { XRI, "A,%b" }, { ORI, "A,%b" },
	4578	{ RETS, 0 }, { STM, 0 }, { MOV, "B,A" }, { MOV, "C,A" },
	4579	{ MOV, "D,A" }, { MOV, "E,A" }, { MOV, "H,A" }, { MOV, "L,A" },
	4580
	4581	{ INRW, "%a" }, { TABLE, 0 }, { INX, "DE" }, { DCX, "DE" },
	4582	{ LXI, "DE,%w" }, { GTIW, "%a,%b" }, { ADINC, "A,%b" }, { GTI, "A,%b" },
	4583	{ LDAW, "%a" }, { LDAX, "BC" }, { LDAX, "DE" }, { LDAX, "HL" },
	4584	{ LDAX, "DE+" }, { LDAX, "HL+" }, { LDAX, "DE-" }, { LDAX, "HL-" },
	4585
	4586	{ DCRW, "%a" }, { BLOCK, 0 }, { INX, "HL" }, { DCX, "HL" },
	4587	{ LXI, "HL,%w" }, { LTIW, "%a,%b" }, { SUINB, "A,%b" }, { LTI, "A,%b" },
	4588	{ STAW, "%a" }, { STAX, "BC" }, { STAX, "DE" }, { STAX, "HL" },
	4589	{ STAX, "DE+" }, { STAX, "HL+" }, { STAX, "DE-" }, { STAX, "HL-" },
	4590
	4591	/* 0x40 - 0x7F */
	4592	{ illegal, 0 }, { INR, "A" }, { INR, "B" }, { INR, "C" },
	4593	{ CALL, "%w" }, { ONIW, "%a,%b" }, { ADI, "A,%b" }, { ONI, "A,%b" },
	4594	{ 0, dasm48_7801 }, { MVIX, "BC,%b" }, { MVIX, "DE,%b" }, { MVIX, "HL,%b" },
	4595	{ 0, dasm4c_7801 }, { 0, dasm4d_7801 }, { JRE, "%d" }, { JRE, "%d" },
	4596
	4597	{ illegal, 0 }, { DCR, "A" }, { DCR, "B" }, { DCR, "C" },
	4598	{ JMP, "%w" }, { OFFIW, "%a,%b" }, { ACI, "A,%b" }, { OFFI, "A,%b" },
	4599	{ BIT, "0,%a" }, { BIT, "1,%a" }, { BIT," 2,%a" }, { BIT, "3,%a" },
	4600	{ BIT, "4,%a" }, { BIT, "5,%a" }, { BIT, "6,%a" }, { BIT, "7,%a" },
	4601
	4602	{ 0, dasm60_7801 }, { DAA, 0 }, { RETI, 0 }, { CALB, 0 },
	4603	{ 0, dasm64_7801 }, { NEIW, "%a,%b" }, { SUI, "A,%b" }, { NEI, "A,%b" },
	4604	{ MVI, "V,%b" }, { MVI, "A,%b" }, { MVI, "B,%b" }, { MVI, "C,%b" },
	4605	{ MVI, "D,%b" }, { MVI, "E,%b" }, { MVI, "H,%b" }, { MVI, "L,%b" },
	4606
	4607	{ 0, dasm70_7801 }, { MVIW, "%a,%b" }, { SOFTI, 0 }, { JB, 0 },
	4608	{ 0, dasm74_7801 }, { EQIW, "%a,%b" }, { SBI, "A,%b" }, { EQI, "A,%b" },
	4609	{ CALF, "%f" }, { CALF, "%f" }, { CALF, "%f" }, { CALF, "%f" },
	4610	{ CALF, "%f" }, { CALF, "%f" }, { CALF, "%f" }, { CALF, "%f" },
	4611
	4612	/* 0x80 - 0xBF */
	4613	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	4614	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	4615	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	4616	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	4617
	4618	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	4619	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	4620	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	4621	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	4622
	4623	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	4624	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	4625	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	4626	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	4627
	4628	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	4629	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	4630	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	4631	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	4632
	4633	/* 0xC0 - 0xFF */
	4634	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	4635	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	4636	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	4637	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	4638
	4639	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	4640	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	4641	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	4642	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	4643
	4644	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	4645	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	4646	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	4647	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	4648
	4649	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	4650	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	4651	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	4652	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" }
	4653	};
	4654
	4655	/*********************************************************
	4656	*
	4657	* uPD7801
	4658	*
	4659	*********************************************************/
	4660
	4661	static const struct dasm_s dasm48_78c05[256] = {
	4662	/* 0x00 - 0x3F */
	4663	{ SKIT, "F0" }, { SKIT, "FT" }, { SKIT, "F1" }, { illegal, 0 }, /* TODO: PDF doesn't mention SKIT and SK */
	4664	{ SKIT, "FS" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4665	{ illegal, 0 }, { illegal, 0 }, { SK, "CY" }, { illegal, 0 },
	4666	{ SK, "Z" }, { illegal, 0 }, { PUSH, "VA" }, { POP, "VA" },
	4667
	4668	{ SKNIT, "F0" }, { SKNIT, "FT" }, { SKNIT, "F1" }, { illegal, 0 },
	4669	{ SKNIT, "FS" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4670	{ illegal, 0 }, { illegal, 0 }, { SKN, "CY" }, { illegal, 0 },
	4671	{ SKN, "Z" }, { illegal, 0 }, { PUSH, "BC" }, { POP, "BC" },
	4672
	4673	{ EI, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4674	{ DI, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4675	{ illegal, 0 }, { illegal, 0 }, { CLC, 0 }, { STC, 0 },
	4676	{ illegal, 0 }, { PEX, 0 }, { PUSH, "DE" }, { POP, "DE" },
	4677
	4678	{ RLL, "A" }, { RLR, "A" }, { illegal, 0 }, { illegal, 0 },
	4679	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4680	{ RLD, 0 }, { RRD, 0 }, { illegal, 0 }, { illegal, 0 },
	4681	{ PER, 0 }, { illegal, 0 }, { PUSH, "HL" }, { POP, "HL" },
	4682
	4683	/* 0x40 - 0x7F */
	4684	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4685	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4686	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4687	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4688
	4689	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4690	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4691	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4692	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4693
	4694	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4695	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4696	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4697	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4698
	4699	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4700	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4701	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4702	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4703
	4704	/* 0x80 - 0xBF */
	4705	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4706	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4707	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4708	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4709
	4710	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4711	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4712	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4713	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4714
	4715	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4716	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4717	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4718	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4719
	4720	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4721	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4722	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4723	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4724
	4725	/* 0xC0 - 0xFF */
	4726	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4727	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4728	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4729	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4730
	4731	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4732	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4733	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4734	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4735
	4736	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4737	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4738	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4739	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4740
	4741	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4742	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4743	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4744	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
	4745	};
	4746
	4747	static const struct dasm_s dasm4c_78c05[256] = {
	4748	/* 0x00 - 0x3F */
	4749	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4750	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4751	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4752	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4753
	4754	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4755	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4756	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4757	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4758
	4759	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4760	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4761	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4762	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4763
	4764	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4765	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4766	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4767	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4768
	4769	/* 0x40 - 0x7F */
	4770	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4771	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4772	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4773	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4774
	4775	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4776	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4777	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4778	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4779
	4780	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4781	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4782	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4783	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4784
	4785	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4786	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4787	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4788	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4789
	4790	/* 0x80 - 0xBF */
	4791	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4792	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4793	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4794	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4795
	4796	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4797	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4798	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4799	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4800
	4801	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4802	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4803	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4804	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4805
	4806	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4807	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4808	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4809	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4810
	4811	/* 0xC0 - 0xFF */
	4812	{ MOV, "A,PA" }, { MOV, "A,PB" }, { MOV, "A,PC" }, { MOV, "A,MK" },
	4813	{ MOV, "A,MB" }, { MOV, "A,MC" }, { MOV, "A,TM0" }, { MOV, "A,TM1" },
	4814	{ MOV, "A,S" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }, /* TODO: Figure out what regsiter C9 indicates */
	4815	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4816
	4817	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4818	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4819	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4820	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4821
	4822	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4823	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4824	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4825	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4826
	4827	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4828	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4829	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4830	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
	4831	};
	4832
	4833	static const struct dasm_s dasm4d_78c05[256] = {
	4834	/* 0x00 - 0x3F */
	4835	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4836	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4837	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4838	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4839
	4840	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4841	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4842	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4843	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4844
	4845	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4846	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4847	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4848	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4849
	4850	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4851	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4852	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4853	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4854
	4855	/* 0x40 - 0x7F */
	4856	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4857	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4858	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4859	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4860
	4861	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4862	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4863	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4864	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4865
	4866	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4867	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4868	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4869	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4870
	4871	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4872	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4873	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4874	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4875
	4876	/* 0x80 - 0xBF */
	4877	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4878	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4879	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4880	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4881
	4882	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4883	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4884	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4885	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4886
	4887	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4888	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4889	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4890	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4891
	4892	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4893	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4894	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4895	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4896
	4897	/* 0xC0 - 0xFF */
	4898	{ MOV, "PA,A" }, { MOV, "PB,A" }, { MOV, "PC,A" }, { MOV, "MK,A" },
	4899	{ MOV, "MB,A" }, { MOV, "MC,A" }, { MOV, "TM0,A" }, { MOV, "TM1,A" },
	4900	{ MOV, "S,A" }, { MOV, "TMM,A" }, { illegal, 0 }, { illegal, 0 },
	4901	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4902
	4903	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4904	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4905	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4906	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4907
	4908	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4909	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4910	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4911	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4912
	4913	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4914	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4915	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4916	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
	4917	};
	4918
	4919	static const struct dasm_s dasm60_78c05[256] = {
	4920	/* 0x00 - 0x3F */
	4921	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4922	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4923	{ illegal, 0 }, { ANA, "A,A" }, { illegal, 0 }, { illegal, 0 },
	4924	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4925
	4926	{ illegal, 0 }, { XRA, "A,A" }, { illegal, 0 }, { illegal, 0 },
	4927	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4928	{ illegal, 0 }, { ORA, "A,A" }, { illegal, 0 }, { illegal, 0 },
	4929	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4930
	4931	{ illegal, 0 }, { ADDNC, "A,A" }, { illegal, 0 }, { illegal, 0 },
	4932	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4933	{ illegal, 0 }, { GTA, "A,A" }, { illegal, 0 }, { illegal, 0 },
	4934	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4935
	4936	{ illegal, 0 }, { SUBNB, "A,A" }, { illegal, 0 }, { illegal, 0 },
	4937	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4938	{ illegal, 0 }, { LTA, "A,A" }, { illegal, 0 }, { illegal, 0 },
	4939	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4940
	4941	/* 0x40 - 0x7F */
	4942	{ illegal, 0 }, { ADD, "A,A" }, { illegal, 0 }, { illegal, 0 },
	4943	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4944	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4945	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4946
	4947	{ illegal, 0 }, { ADC, "A,A" }, { illegal, 0 }, { illegal, 0 },
	4948	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4949	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4950	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4951
	4952	{ illegal, 0 }, { SUB, "A,A" }, { illegal, 0 }, { illegal, 0 },
	4953	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4954	{ illegal, 0 }, { NEA, "A,A" }, { illegal, 0 }, { illegal, 0 },
	4955	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4956
	4957	{ illegal, 0 }, { SBB, "A,A" }, { illegal, 0 }, { illegal, 0 },
	4958	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4959	{ illegal, 0 }, { EQA, "A,A" }, { illegal, 0 }, { illegal, 0 },
	4960	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4961
	4962	/* 0x80 - 0xBF */
	4963	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4964	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	4965	{ illegal, 0 }, { ANA, "A,A" }, { ANA, "A,B" }, { ANA, "A,C" },
	4966	{ ANA, "A,D" }, { ANA, "A,E" }, { ANA, "A,H" }, { ANA, "A,L" },
	4967
	4968	{ illegal, 0 }, { XRA, "A,A" }, { XRA, "A,B" }, { XRA, "A,C" },
	4969	{ XRA, "A,D" }, { XRA, "A,E" }, { XRA, "A,H" }, { XRA, "A,L" },
	4970	{ illegal, 0 }, { ORA, "A,A" }, { ORA, "A,B" }, { ORA, "A,C" },
	4971	{ ORA, "A,D" }, { ORA, "A,E" }, { ORA, "A,H" }, { ORA, "A,L" },
	4972
	4973	{ illegal, 0 }, { ADDNC, "A,A" }, { ADDNC, "A,B" }, { ADDNC, "A,C" },
	4974	{ ADDNC, "A,D" }, { ADDNC, "A,E" }, { ADDNC, "A,H" }, { ADDNC, "A,L" },
	4975	{ illegal, 0 }, { GTA, "A,A" }, { GTA, "A,B" }, { GTA, "A,C" },
	4976	{ GTA, "A,D" }, { GTA, "A,E" }, { GTA, "A,H" }, { GTA, "A,L" },
	4977
	4978	{ illegal, 0 }, { SUBNB, "A,A" }, { SUBNB, "A,B" }, { SUBNB, "A,C" },
	4979	{ SUBNB, "A,D" }, { SUBNB, "A,E" }, { SUBNB, "A,H" }, { SUBNB, "A,L" },
	4980	{ illegal, 0 }, { LTA, "A,A" }, { LTA, "A,B" }, { LTA, "A,C" },
	4981	{ LTA, "A,D" }, { LTA, "A,E" }, { LTA, "A,H" }, { LTA, "A,L" },
	4982
	4983	/* 0xC0 - 0xFF */
	4984	{ illegal, 0 }, { ADD, "A,A" }, { ADD, "A,B" }, { ADD, "A,C" },
	4985	{ ADD, "A,D" }, { ADD, "A,E" }, { ADD, "A,H" }, { ADD, "A,L" },
	4986	{ illegal, 0 }, { ONA, "A,A" }, { ONA, "A,B" }, { ONA, "A,C" },
	4987	{ ONA, "A,D" }, { ONA, "A,E" }, { ONA, "A,H" }, { ONA, "A,L" },
	4988
	4989	{ illegal, 0 }, { ADC, "A,A" }, { ADC, "A,B" }, { ADC, "A,C" },
	4990	{ ADC, "A,D" }, { ADC, "A,E" }, { ADC, "A,H" }, { ADC, "A,L" },
	4991	{ illegal, 0 }, { OFFA, "A,A" }, { OFFA, "A,B" }, { OFFA, "A,C" },
	4992	{ OFFA, "A,D" }, { OFFA, "A,E" }, { OFFA, "A,H" }, { OFFA, "A,L" },
	4993
	4994	{ illegal, 0 }, { SUB, "A,A" }, { SUB, "A,B" }, { SUB, "A,C" },
	4995	{ SUB, "A,D" }, { SUB, "A,E" }, { SUB, "A,H" }, { SUB, "A,L" },
	4996	{ illegal, 0 }, { NEA, "A,A" }, { NEA, "A,B" }, { NEA, "A,C" },
	4997	{ NEA, "A,D" }, { NEA, "A,E" }, { NEA, "A,H" }, { NEA, "A,L" },
	4998
	4999	{ illegal, 0 }, { SBB, "A,A" }, { SBB, "A,B" }, { SBB, "A,C" },
	5000	{ SBB, "A,D" }, { SBB, "A,E" }, { SBB, "A,H" }, { SBB, "A,L" },
	5001	{ illegal, 0 }, { EQA, "A,A" }, { EQA, "A,B" }, { EQA, "A,C" },
	5002	{ EQA, "A,D" }, { EQA, "A,E" }, { EQA, "A,H" }, { EQA, "A,L" }
	5003	};
	5004
	5005	static const struct dasm_s dasm64_78c05[256] = {
	5006	/* 0x00 - 0x3F */
	5007	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5008	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5009	{ illegal, 0 }, { ANI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
	5010	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5011
	5012	{ illegal, 0 }, { XRI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
	5013	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5014	{ illegal, 0 }, { ORI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
	5015	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5016
	5017	{ illegal, 0 }, { ADINC, "A,%b" }, { illegal, 0 }, { illegal, 0 },
	5018	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5019	{ illegal, 0 }, { GTI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
	5020	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5021
	5022	{ illegal, 0 }, { SUINB, "A,%b" }, { illegal, 0 }, { illegal, 0 },
	5023	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5024	{ illegal, 0 }, { LTI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
	5025	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5026
	5027	/* 0x40 - 0x7F */
	5028	{ illegal, 0 }, { ADI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
	5029	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5030	{ illegal, 0 }, { ONI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
	5031	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5032
	5033	{ illegal, 0 }, { ACI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
	5034	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5035	{ illegal, 0 }, { OFFI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
	5036	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5037
	5038	{ illegal, 0 }, { SUI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
	5039	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5040	{ illegal, 0 }, { NEI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
	5041	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5042
	5043	{ illegal, 0 }, { SBI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
	5044	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5045	{ illegal, 0 }, { EQI, "A,%b" }, { illegal, 0 }, { illegal, 0 },
	5046	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5047
	5048	/* 0x80 - 0xBF */
	5049	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5050	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5051	{ ANI, "PA,%b" }, { ANI, "PB,%b" }, { ANI, "PC,%b" }, { ANI, "MK,%b" },
	5052	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5053
	5054	{ XRI, "PA,%b" }, { XRI, "PB,%b" }, { XRI, "PC,%b" }, { XRI, "MK,%b" },
	5055	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5056	{ ORI, "PA,%b" }, { ORI, "PB,%b" }, { ORI, "PC,%b" }, { ORI, "MK,%b" },
	5057	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5058
	5059	{ ADINC, "PA,%b" }, { ADINC, "PB,%b" }, { ADINC, "PC,%b" }, { ADINC, "MK,%b" },
	5060	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5061	{ GTI, "PA,%b" }, { GTI, "PB,%b" }, { GTI, "PC,%b" }, { GTI, "MK,%b" },
	5062	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5063
	5064	{ SUINB, "PA,%b" }, { SUINB, "PB,%b" }, { SUINB, "PC,%b" }, { SUINB, "MK,%b" },
	5065	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5066	{ LTI, "PA,%b" }, { LTI, "PB,%b" }, { LTI, "PC,%b" }, { LTI, "MK,%b" },
	5067	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5068
	5069	/* 0xC0 - 0xFF */
	5070	{ ADI, "PA,%b" }, { ADI, "PB,%b" }, { ADI, "PC,%b" }, { ADI, "MK,%b" },
	5071	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5072	{ ONI, "PA,%b" }, { ONI, "PB,%b" }, { ONI, "PC,%b" }, { ONI, "MK,%b" },
	5073	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5074
	5075	{ ACI, "PA,%b" }, { ACI, "PB,%b" }, { ACI, "PC,%b" }, { ACI, "MK,%b" },
	5076	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5077	{ SUI, "PA,%b" }, { SUI, "PB,%b" }, { SUI, "PC,%b" }, { SUI, "MK,%b" },
	5078	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5079
	5080	{ NEI, "PA,%b" }, { NEI, "PB,%b" }, { NEI, "PC,%b" }, { NEI, "MK,%b" },
	5081	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5082	{ SBI, "PA,%b" }, { SBI, "PB,%b" }, { SBI, "PC,%b" }, { SBI, "MK,%b" },
	5083	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5084
	5085	{ SBI, "PA,%b" }, { SBI, "PB,%b" }, { SBI, "PC,%b" }, { SBI, "MK,%b" },
	5086	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5087	{ EQI, "PA,%b" }, { EQI, "PB,%b" }, { EQI, "PC,%b" }, { EQI, "MK,%b" },
	5088	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 }
	5089	};
	5090
	5091	static const struct dasm_s dasm70_78c05[256] = {
	5092	/* 0x00 - 0x3F */
	5093	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5094	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5095	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5096	{ illegal, 0 }, { illegal, 0 }, { SSPD, "%w" }, { LSPD, "%w" },
	5097
	5098	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5099	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5100	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5101	{ illegal, 0 }, { illegal, 0 }, { SBCD, "%w" }, { LBCD, "%w" },
	5102
	5103	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5104	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5105	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5106	{ illegal, 0 }, { illegal, 0 }, { SDED, "%w" }, { LDED, "%w" },
	5107
	5108	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5109	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5110	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5111	{ illegal, 0 }, { illegal, 0 }, { SHLD, "%w" }, { LHLD, "%w" },
	5112
	5113	/* 0x40 - 0x7F */
	5114	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5115	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5116	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5117	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5118
	5119	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5120	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5121	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5122	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5123
	5124	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5125	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5126	{ illegal, 0 }, { MOV, "A,%w" }, { MOV, "B,%w" }, { MOV, "C,%w" },
	5127	{ MOV, "D,%w" }, { MOV, "E,%w" }, { MOV, "H,%w" }, { MOV, "L,%w" },
	5128
	5129	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5130	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5131	{ illegal, 0 }, { MOV, "%w,A" }, { MOV, "%w,B" }, { MOV, "%w,C" },
	5132	{ MOV, "%w,D" }, { MOV, "%w,E" }, { MOV, "%w,H" }, { MOV, "%w,L" },
	5133
	5134	/* 0x80 - 0xBF */
	5135	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5136	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5137	{ illegal, 0 }, { ANAX, "BC" }, { ANAX, "DE" }, { ANAX, "HL" },
	5138	{ ANAX, "DE+" }, { ANAX, "HL+" }, { ANAX, "DE-" }, { ANAX, "HL-" },
	5139
	5140	{ illegal, 0 }, { XRAX, "BC" }, { XRAX, "DE" }, { XRAX, "HL" },
	5141	{ XRAX, "DE+" }, { XRAX, "HL+" }, { XRAX, "DE-" }, { XRAX, "HL-" },
	5142	{ illegal, 0 }, { ORAX, "BC" }, { ORAX, "DE" }, { ORAX, "HL" },
	5143	{ ORAX, "DE+" }, { ORAX, "HL+" }, { ORAX, "DE-" }, { ORAX, "HL-" },
	5144
	5145	{ illegal, 0 }, { ADDNCX, "BC" }, { ADDNCX, "DE" }, { ADDNCX, "HL" },
	5146	{ ADDNCX, "DE+" }, { ADDNCX, "HL+" }, { ADDNCX, "DE-" }, { ADDNCX, "HL-" },
	5147	{ illegal, 0 }, { GTAX, "BC" }, { GTAX, "DE" }, { GTAX, "HL" },
	5148	{ GTAX, "DE+" }, { GTAX, "HL+" }, { GTAX, "DE-" }, { GTAX, "HL-" },
	5149
	5150	{ illegal, 0 }, { SUBNBX, "BC" }, { SUBNBX, "DE" }, { SUBNBX, "HL" },
	5151	{ SUBNBX, "DE+" }, { SUBNBX, "HL+" }, { SUBNBX, "DE-" }, { SUBNBX, "HL-" },
	5152	{ illegal, 0 }, { LTAX, "BC" }, { LTAX, "DE" }, { LTAX, "HL" },
	5153	{ LTAX, "DE+" }, { LTAX, "HL+" }, { LTAX, "DE-" }, { LTAX, "HL-" },
	5154
	5155	/* 0xC0 - 0xFF */
	5156	{ illegal, 0 }, { ADDX, "BC" }, { ADDX, "DE" }, { ADDX, "HL" },
	5157	{ ADDX, "DE+" }, { ADDX, "HL+" }, { ADDX, "DE-" }, { ADDX, "HL-" },
	5158	{ illegal, 0 }, { ONAX, "BC" }, { ONAX, "DE" }, { ONAX, "HL" },
	5159	{ ONAX, "DE+" }, { ONAX, "HL+" }, { ONAX, "DE-" }, { ONAX, "HL-" },
	5160
	5161	{ illegal, 0 }, { ADCX, "BC" }, { ADCX, "DE" }, { ADCX, "HL" },
	5162	{ ADCX, "DE+" }, { ADCX, "HL+" }, { ADCX, "DE-" }, { ADCX, "HL-" },
	5163	{ illegal, 0 }, { OFFAX, "BC" }, { OFFAX, "DE" }, { OFFAX, "HL" },
	5164	{ OFFAX, "DE+" }, { OFFAX, "HL+" }, { OFFAX, "DE-" }, { OFFAX, "HL-" },
	5165
	5166	{ illegal, 0 }, { SUBX, "BC" }, { SUBX, "DE" }, { SUBX, "HL" },
	5167	{ SUBX, "DE+" }, { SUBX, "HL+" }, { SUBX, "DE-" }, { SUBX, "HL-" },
	5168	{ illegal, 0 }, { NEAX, "BC" }, { NEAX, "DE" }, { NEAX, "HL" },
	5169	{ NEAX, "DE+" }, { NEAX, "HL+" }, { NEAX, "DE-" }, { NEAX, "HL-" },
	5170
	5171	{ illegal, 0 }, { SBBX, "BC" }, { SBBX, "DE" }, { SBBX, "HL" },
	5172	{ SBBX, "DE+" }, { SBBX, "HL+" }, { SBBX, "DE-" }, { SBBX, "HL-" },
	5173	{ illegal, 0 }, { EQAX, "BC" }, { EQAX, "DE" }, { EQAX, "HL" },
	5174	{ EQAX, "DE+" }, { EQAX, "HL+" }, { EQAX, "DE-" }, { EQAX, "HL-" },
	5175	};
	5176
	5177	static const struct dasm_s dasm74_78c05[256] = {
	5178	/* 0x00 - 0x3F */
	5179	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5180	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5181	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5182	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5183
	5184	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5185	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5186	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5187	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5188
	5189	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5190	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5191	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5192	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5193
	5194	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5195	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5196	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5197	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5198
	5199	/* 0x40 - 0x7F */
	5200	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5201	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5202	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5203	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5204
	5205	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5206	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5207	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5208	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5209
	5210	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5211	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5212	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5213	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5214
	5215	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5216	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5217	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5218	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5219
	5220	/* 0x80 - 0xBF */
	5221	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5222	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5223	{ ANAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5224	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5225
	5226	{ XRAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5227	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5228	{ ORAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5229	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5230
	5231	{ ADDNCW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5232	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5233	{ GTAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5234	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5235
	5236	{ SUBNBW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5237	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5238	{ LTAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5239	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5240
	5241	/* 0xC0 - 0xFF */
	5242	{ ADDW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5243	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5244	{ ONAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5245	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5246
	5247	{ ADCW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5248	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5249	{ OFFAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5250	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5251
	5252	{ SUBW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5253	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5254	{ NEAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5255	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5256
	5257	{ SBBW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5258	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5259	{ EQAW, "%a" }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5260	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5261	};
	5262
	5263	static const struct dasm_s dasmXX_78c05[256] = {
	5264	/* 0x00 - 0x3F */
	5265	{ NOP, 0 }, { HALT, 0 }, { INX, "SP" }, { DCX, "SP" },
	5266	{ LXI, "SP,%w" }, { ANIW, "%a,%b" }, { illegal, 0 }, { ANI, "A,%b" },
	5267	{ RET, 0 }, { SIO, 0 }, { MOV, "A,B" }, { MOV, "A,C" },
	5268	{ MOV, "A,D" }, { MOV, "A,E" }, { MOV, "A,H" }, { MOV, "A,L" },
	5269
	5270	{ illegal, 0 }, { illegal, 0 }, { INX, "BC" }, { DCX, "BC" },
	5271	{ LXI, "BC,%w" }, { ORIW, "%a,%b" }, { XRI, "A,%b" }, { ORI, "A,%b" },
	5272	{ RETS, 0 }, { STM, 0 }, { MOV, "B,A" }, { MOV, "C,A" },
	5273	{ MOV, "D,A" }, { MOV, "E,A" }, { MOV, "H,A" }, { MOV, "L,A" },
	5274
	5275	{ INRW, "%a" }, { illegal, 0 }, { INX, "DE" }, { DCX, "DE" },
	5276	{ LXI, "DE,%w" }, { GTIW, "%a,%b" }, { ADINC, "A,%b" }, { GTI, "A,%b" },
	5277	{ LDAW, "%a" }, { LDAX, "BC" }, { LDAX, "DE" }, { LDAX, "HL" },
	5278	{ LDAX, "DE+" }, { LDAX, "HL+" }, { LDAX, "DE-" }, { LDAX, "HL-" },
	5279
	5280	{ DCRW, "%a" }, { illegal, 0 }, { INX, "HL" }, { DCX, "HL" },
	5281	{ LXI, "HL,%w" }, { LTIW, "%a,%b" }, { SUINB, "A,%b" }, { LTI, "A,%b" },
	5282	{ STAW, "%a" }, { STAX, "BC" }, { STAX, "DE" }, { STAX, "HL" },
	5283	{ STAX, "DE+" }, { STAX, "HL+" }, { STAX, "DE-" }, { STAX, "HL-" },
	5284
	5285	/* 0x40 - 0x7F */
	5286	{ illegal, 0 }, { INR, "A" }, { INR, "B" }, { INR, "C" },
	5287	{ CALL, "%w" }, { ONIW, "%a,%b" }, { ADI, "A,%b" }, { ONI, "A,%b" },
	5288	{ 0, dasm48_78c05 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5289	{ 0, dasm4c_78c05 }, { 0, dasm4d_78c05 }, { JRE, "%d" }, { JRE, "%d" },
	5290
	5291	{ illegal, 0 }, { DCR, "A" }, { DCR, "B" }, { DCR, "C" },
	5292	{ JMP, "%w" }, { OFFIW, "%a,%b" }, { ACI, "A,%b" }, { OFFI, "A,%b" },
	5293	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5294	{ illegal, 0 }, { illegal, 0 }, { illegal, 0 }, { illegal, 0 },
	5295
	5296	{ 0, dasm60_78c05 }, { DAA, 0 }, { RETI, 0 }, { CALB, 0 },
	5297	{ 0, dasm64_78c05 }, { NEIW, "%a,%b" }, { SUI, "A,%b" }, { NEI, "A,%b" },
	5298	{ illegal, 0 }, { MVI, "A,%b" }, { MVI, "B,%b" }, { MVI, "C,%b" },
	5299	{ MVI, "D,%b" }, { MVI, "E,%b" }, { MVI, "H,%b" }, { MVI, "L,%b" },
	5300
	5301	{ 0, dasm70_78c05 }, { MVIW, "%a,%b" }, { SOFTI, 0 }, { JB, 0 },
	5302	{ 0, dasm74_78c05 }, { EQIW, "%a,%b" }, { SBI, "A,%b" }, { EQI, "A,%b" },
	5303	{ CALF, "%f" }, { CALF, "%f" }, { CALF, "%f" }, { CALF, "%f" },
	5304	{ CALF, "%f" }, { CALF, "%f" }, { CALF, "%f" }, { CALF, "%f" },
	5305
	5306	/* 0x80 - 0xBF */
	5307	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	5308	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	5309	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	5310	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	5311
	5312	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	5313	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	5314	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	5315	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	5316
	5317	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	5318	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	5319	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	5320	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	5321
	5322	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	5323	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	5324	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	5325	{ CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" }, { CALT, "%t" },
	5326
	5327	/* 0xC0 - 0xFF */
	5328	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	5329	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	5330	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	5331	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	5332
	5333	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	5334	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	5335	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	5336	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	5337
	5338	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	5339	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	5340	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	5341	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	5342
	5343	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	5344	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	5345	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" },
	5346	{ JR, "%o" }, { JR, "%o" }, { JR, "%o" }, { JR, "%o" }
	5347	};
	5348
	5349
	5350	/* register names for bit manipulation instructions */
	5351	static const char *const regname[32] =
	5352	{
	5353	"illegal", "illegal", "illegal", "illegal",
	5354	"illegal", "illegal", "illegal", "illegal",
	5355	"illegal", "illegal", "illegal", "illegal",
	5356	"illegal", "illegal", "illegal", "illegal",
	5357	"PA", "PB", "PC", "PD",
	5358	"illegal", "PF", "MKH", "MKL",
	5359	"illegal", "SMH", "illegal", "EOM",
	5360	"illegal", "TMM", "PT", "illegal"
	5361	};
	5362
	5363	static offs_t Dasm( char buffer, offs_t pc, const struct dasm_s dasmXX, const UINT8 oprom, const UINT8 opram, int is_7810 )
	5364	{
	5365	int idx = 0;
	5366	UINT8 op = oprom[idx++], op2, t;
	5367	int offset;
	5368	UINT16 ea;
	5369	const char *a;
	5370	UINT32 flags = 0;
	5371
	5372	t = dasmXX[op].token;
	5373	a = (const char *)dasmXX[op].args;
	5374
	5375	/* 0 token means prefix opcode (use table from args) */
	5376	if (0 == t)
	5377	{
	5378	struct dasm_s p_dasm = (struct dasm_s )a;
	5379
	5380	op2 = oprom[idx++];
	5381	t = p_dasm[op2].token;
	5382	a = (const char *)p_dasm[op2].args;
	5383	}
	5384
	5385	buffer += sprintf(buffer, "%-8.8s", token[t]);
	5386
	5387	if (t == CALB \|\| t == CALF \|\| t == CALL \|\| t == CALT)
	5388	flags = DASMFLAG_STEP_OVER;
	5389	else if (t == RET \|\| t == RETI)
	5390	flags = DASMFLAG_STEP_OUT;
	5391
	5392	while (a && *a)
	5393	{
	5394	if ('%' == *a)
	5395	{
	5396	a++;
	5397	switch (*a)
	5398	{
	5399	case 'a': /* address V * 256 + offset */
	5400	op2 = opram[idx++];
	5401	buffer += sprintf(buffer, "VV:%02X", op2);
	5402	break;
	5403	case 'b': /* immediate byte */
	5404	buffer += sprintf(buffer, "$%02X", opram[idx++]);
	5405	break;
	5406	case 'w': /* immediate word */
	5407	ea = opram[idx++];
	5408	ea += opram[idx++] << 8;
	5409	buffer += sprintf(buffer, "$%04X", ea);
	5410	break;
	5411	case 'd': /* JRE address */
	5412	op2 = oprom[idx++];
	5413	offset = (op & 1) ? -(256 - op2): + op2;
	5414	buffer += sprintf(buffer, "$%04X", ( pc + idx + offset ) & 0xFFFF );
	5415	break;
	5416	case 't': /* CALT address */
	5417	ea = 0x80 + 2 * (op & (is_7810 ? 0x1f : 0x3f));
	5418	buffer += sprintf(buffer, "($%04X)", ea);
	5419	break;
	5420	case 'f': /* CALF address */
	5421	op2 = oprom[idx++];
	5422	ea = 0x800 + 0x100 * (op & 0x07) + op2;
	5423	buffer += sprintf(buffer, "$%04X", ea);
	5424	break;
	5425	case 'o': /* JR offset */
	5426	offset = ( ( op & 0x20 ) ? -0x20 : 0 ) + ( op & 0x1F );
	5427	buffer += sprintf(buffer, "$%04X", ( pc + idx + offset ) & 0xFFFF );
	5428	break;
	5429	case 'i': /* bit manipulation */
	5430	op2 = oprom[idx++];
	5431	buffer += sprintf(buffer, "%s,%d", regname[op2 & 0x1f], op2 >> 5);
	5432	break;
	5433	default:
	5434	buffer++ = a;
	5435	}
	5436	}
	5437	else
	5438	buffer++ = a;
	5439	a++;
	5440	}
	5441	*buffer = '\0';
	5442
	5443	return idx \| flags \| DASMFLAG_SUPPORTED;
	5444	}
	5445
	5446	CPU_DISASSEMBLE( upd7810 )
	5447	{
	5448	return Dasm( buffer, pc, dasmXX_7810, oprom, opram, 1 );
	5449	}
	5450
	5451	CPU_DISASSEMBLE( upd7807 )
	5452	{
	5453	return Dasm( buffer, pc, dasmXX_7807, oprom, opram, 1 );
	5454	}
	5455
	5456	CPU_DISASSEMBLE( upd7801 )
	5457	{
	5458	return Dasm( buffer, pc, dasmXX_7801, oprom, opram, 0 );
	5459	}
	5460
	5461	CPU_DISASSEMBLE( upd78c05 )
	5462	{
	5463	return Dasm( buffer, pc, dasmXX_78c05, oprom, opram, 0 );
	5464	}

Property changes on: trunk/src/emu/cpu/upd7810/upd7810_dasm.c
Added: svn:mime-type + text/plain Added: svn:eol-style + native

trunk/src/emu/cpu/upd7810/upd7810.h
r30937	r30938
102	102	template<class _Object> static devcb_base &set_an7_func(device_t &device, _Object object) { return downcast<upd7810_device &>(device).m_an7_func.set_callback(object); }
103	103
104	104	protected:
	105	// flags
	106	enum
	107	{
	108	CY = 0x01,
	109	F1 = 0x02,
	110	L0 = 0x04,
	111	L1 = 0x08,
	112	HC = 0x10,
	113	SK = 0x20,
	114	Z = 0x40,
	115	F7 = 0x80
	116	};
	117
	118	// IRR flags
	119	enum
	120	{
	121	INTNMI = 0x0001,
	122	INTFT0 = 0x0002,
	123	INTFT1 = 0x0004,
	124	INTF1 = 0x0008,
	125	INTF2 = 0x0010,
	126	INTFE0 = 0x0020,
	127	INTFE1 = 0x0040,
	128	INTFEIN = 0x0080,
	129	INTFAD = 0x0100,
	130	INTFSR = 0x0200,
	131	INTFST = 0x0400,
	132	INTER = 0x0800,
	133	INTOV = 0x1000,
	134	INTF0 = 0x2000
	135	};
	136
	137	// ITF flags
	138	enum
	139	{
	140	INTAN4 = 0x0001,
	141	INTAN5 = 0x0002,
	142	INTAN6 = 0x0004,
	143	INTAN7 = 0x0008,
	144	INTSB = 0x0010
	145	};
	146
105	147	// device-level overrides
106	148	virtual void device_start();
107	149	virtual void device_reset();

trunk/src/emu/cpu/upd7810/upd7810_table.c
r0	r30938
	1	/*****************************************************************************
	2	*
	3	* Portable uPD7810/11, 7810H/11H, 78C10/C11/C14 emulator V0.2
	4	* Copyright Juergen Buchmueller, all rights reserved.
	5	*
	6	* 7810tbl.inc - function pointer tables
	7	*
	8	*****************************************************************************/
	9
	10	#include "emu.h"
	11	#include "upd7810.h"
	12
	13	const struct upd7810_device::opcode_s upd7810_device::s_op48[256] =
	14	{
	15	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 00: 0100 1000 0000 0000 */
	16	{&upd7810_device::SLRC_A, 2, 8, 8,L0\|L1}, /* 01: 0100 1000 0000 0001 */
	17	{&upd7810_device::SLRC_B, 2, 8, 8,L0\|L1}, /* 02: 0100 1000 0000 0010 */
	18	{&upd7810_device::SLRC_C, 2, 8, 8,L0\|L1}, /* 03: 0100 1000 0000 0011 */
	19	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 04: 0100 1000 0000 0100 */
	20	{&upd7810_device::SLLC_A, 2, 8, 8,L0\|L1}, /* 05: 0100 1000 0000 0101 */
	21	{&upd7810_device::SLLC_B, 2, 8, 8,L0\|L1}, /* 06: 0100 1000 0000 0110 */
	22	{&upd7810_device::SLLC_C, 2, 8, 8,L0\|L1}, /* 07: 0100 1000 0000 0111 */
	23	{&upd7810_device::SK_NV, 2, 8, 8,L0\|L1}, /* 08: 0100 1000 0000 1000 */
	24	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 09: 0100 1000 0000 1001 */
	25	{&upd7810_device::SK_CY, 2, 8, 8,L0\|L1}, /* 0a: 0100 1000 0000 1010 */
	26	{&upd7810_device::SK_HC, 2, 8, 8,L0\|L1}, /* 0b: 0100 1000 0000 1011 */
	27	{&upd7810_device::SK_Z, 2, 8, 8,L0\|L1}, /* 0c: 0100 1000 0000 1100 */
	28	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 0d: 0100 1000 0000 1101 */
	29	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 0e: 0100 1000 0000 1110 */
	30	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 0f: 0100 1000 0000 1111 */
	31
	32	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 10: 0100 1000 0001 0000 */
	33	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 11: 0100 1000 0001 0001 */
	34	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 12: 0100 1000 0001 0010 */
	35	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 13: 0100 1000 0001 0011 */
	36	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 14: 0100 1000 0001 0100 */
	37	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 15: 0100 1000 0001 0101 */
	38	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 16: 0100 1000 0001 0110 */
	39	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 17: 0100 1000 0001 0111 */
	40	{&upd7810_device::SKN_NV, 2, 8, 8,L0\|L1}, /* 18: 0100 1000 0001 1000 */
	41	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 19: 0100 1000 0001 1001 */
	42	{&upd7810_device::SKN_CY, 2, 8, 8,L0\|L1}, /* 1a: 0100 1000 0001 1010 */
	43	{&upd7810_device::SKN_HC, 2, 8, 8,L0\|L1}, /* 1b: 0100 1000 0001 1011 */
	44	{&upd7810_device::SKN_Z, 2, 8, 8,L0\|L1}, /* 1c: 0100 1000 0001 1100 */
	45	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 1d: 0100 1000 0001 1101 */
	46	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 1e: 0100 1000 0001 1110 */
	47	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 1f: 0100 1000 0001 1111 */
	48
	49	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 20: 0100 1000 0010 0000 */
	50	{&upd7810_device::SLR_A, 2, 8, 8,L0\|L1}, /* 21: 0100 1000 0010 0001 */
	51	{&upd7810_device::SLR_B, 2, 8, 8,L0\|L1}, /* 22: 0100 1000 0010 0010 */
	52	{&upd7810_device::SLR_C, 2, 8, 8,L0\|L1}, /* 23: 0100 1000 0010 0011 */
	53	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 24: 0100 1000 0010 0100 */
	54	{&upd7810_device::SLL_A, 2, 8, 8,L0\|L1}, /* 25: 0100 1000 0010 0101 */
	55	{&upd7810_device::SLL_B, 2, 8, 8,L0\|L1}, /* 26: 0100 1000 0010 0110 */
	56	{&upd7810_device::SLL_C, 2, 8, 8,L0\|L1}, /* 27: 0100 1000 0010 0111 */
	57	{&upd7810_device::JEA, 2, 8, 8,L0\|L1}, /* 28: 0100 1000 0010 1000 */
	58	{&upd7810_device::CALB, 2,17,17,L0\|L1}, /* 29: 0100 1000 0010 1001 */
	59	{&upd7810_device::CLC, 2, 8, 8,L0\|L1}, /* 2a: 0100 1000 0010 1010 */
	60	{&upd7810_device::STC, 2, 8, 8,L0\|L1}, /* 2b: 0100 1000 0010 1011 */
	61	{&upd7810_device::illegal, 2,32,32,L0\|L1}, /* 2c: 0100 1000 0010 1100 */
	62	{&upd7810_device::MUL_A, 2,32,32,L0\|L1}, /* 2d: 0100 1000 0010 1101 */
	63	{&upd7810_device::MUL_B, 2,32,32,L0\|L1}, /* 2e: 0100 1000 0010 1110 */
	64	{&upd7810_device::MUL_C, 2,32,32,L0\|L1}, /* 2f: 0100 1000 0010 1111 */
	65
	66	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 30: 0100 1000 0011 0000 */
	67	{&upd7810_device::RLR_A, 2, 8, 8,L0\|L1}, /* 31: 0100 1000 0011 0001 */
	68	{&upd7810_device::RLR_B, 2, 8, 8,L0\|L1}, /* 32: 0100 1000 0011 0010 */
	69	{&upd7810_device::RLR_C, 2, 8, 8,L0\|L1}, /* 33: 0100 1000 0011 0011 */
	70	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 34: 0100 1000 0011 0100 */
	71	{&upd7810_device::RLL_A, 2, 8, 8,L0\|L1}, /* 35: 0100 1000 0011 0101 */
	72	{&upd7810_device::RLL_B, 2, 8, 8,L0\|L1}, /* 36: 0100 1000 0011 0110 */
	73	{&upd7810_device::RLL_C, 2, 8, 8,L0\|L1}, /* 37: 0100 1000 0011 0111 */
	74	{&upd7810_device::RLD, 2,17,17,L0\|L1}, /* 38: 0100 1000 0011 1000 */
	75	{&upd7810_device::RRD, 2,17,17,L0\|L1}, /* 39: 0100 1000 0011 1001 */
	76	{&upd7810_device::NEGA, 2, 8, 8,L0\|L1}, /* 3a: 0100 1000 0011 1010 */
	77	{&upd7810_device::HALT, 2,12,12,L0\|L1}, /* 3b: 0100 1000 0011 1011 */
	78	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 3c: 0100 1000 0011 1100 */
	79	{&upd7810_device::DIV_A, 2,59,59,L0\|L1}, /* 3d: 0100 1000 0011 1101 */
	80	{&upd7810_device::DIV_B, 2,59,59,L0\|L1}, /* 3e: 0100 1000 0011 1110 */
	81	{&upd7810_device::DIV_C, 2,59,59,L0\|L1}, /* 3f: 0100 1000 0011 1111 */
	82
	83	{&upd7810_device::SKIT_NMI, 2, 8, 8,L0\|L1}, /* 40: 0100 1000 0100 0000 */
	84	{&upd7810_device::SKIT_FT0, 2, 8, 8,L0\|L1}, /* 41: 0100 1000 0100 0001 */
	85	{&upd7810_device::SKIT_FT1, 2, 8, 8,L0\|L1}, /* 42: 0100 1000 0100 0010 */
	86	{&upd7810_device::SKIT_F1, 2, 8, 8,L0\|L1}, /* 43: 0100 1000 0100 0011 */
	87	{&upd7810_device::SKIT_F2, 2, 8, 8,L0\|L1}, /* 44: 0100 1000 0100 0100 */
	88	{&upd7810_device::SKIT_FE0, 2, 8, 8,L0\|L1}, /* 45: 0100 1000 0100 0101 */
	89	{&upd7810_device::SKIT_FE1, 2, 8, 8,L0\|L1}, /* 46: 0100 1000 0100 0110 */
	90	{&upd7810_device::SKIT_FEIN, 2, 8, 8,L0\|L1}, /* 47: 0100 1000 0100 0111 */
	91	{&upd7810_device::SKIT_FAD, 2, 8, 8,L0\|L1}, /* 48: 0100 1000 0100 1000 */
	92	{&upd7810_device::SKIT_FSR, 2, 8, 8,L0\|L1}, /* 49: 0100 1000 0100 1001 */
	93	{&upd7810_device::SKIT_FST, 2, 8, 8,L0\|L1}, /* 4a: 0100 1000 0100 1010 */
	94	{&upd7810_device::SKIT_ER, 2, 8, 8,L0\|L1}, /* 4b: 0100 1000 0100 1011 */
	95	{&upd7810_device::SKIT_OV, 2, 8, 8,L0\|L1}, /* 4c: 0100 1000 0100 1100 */
	96	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4d: 0100 1000 0100 1101 */
	97	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4e: 0100 1000 0100 1110 */
	98	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4f: 0100 1000 0100 1111 */
	99
	100	{&upd7810_device::SKIT_AN4, 2, 8, 8,L0\|L1}, /* 50: 0100 1000 0101 0000 */
	101	{&upd7810_device::SKIT_AN5, 2, 8, 8,L0\|L1}, /* 51: 0100 1000 0101 0001 */
	102	{&upd7810_device::SKIT_AN6, 2, 8, 8,L0\|L1}, /* 52: 0100 1000 0101 0010 */
	103	{&upd7810_device::SKIT_AN7, 2, 8, 8,L0\|L1}, /* 53: 0100 1000 0101 0011 */
	104	{&upd7810_device::SKIT_SB, 2, 8, 8,L0\|L1}, /* 54: 0100 1000 0101 0100 */
	105	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 55: 0100 1000 0101 0101 */
	106	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 56: 0100 1000 0101 0110 */
	107	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 57: 0100 1000 0101 0111 */
	108	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 58: 0100 1000 0101 1000 */
	109	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 59: 0100 1000 0101 1001 */
	110	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5a: 0100 1000 0101 1010 */
	111	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5b: 0100 1000 0101 1011 */
	112	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5c: 0100 1000 0101 1100 */
	113	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5d: 0100 1000 0101 1101 */
	114	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5e: 0100 1000 0101 1110 */
	115	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5f: 0100 1000 0101 1111 */
	116
	117	{&upd7810_device::SKNIT_NMI, 2, 8, 8,L0\|L1}, /* 60: 0100 1000 0110 0000 */
	118	{&upd7810_device::SKNIT_FT0, 2, 8, 8,L0\|L1}, /* 61: 0100 1000 0110 0001 */
	119	{&upd7810_device::SKNIT_FT1, 2, 8, 8,L0\|L1}, /* 62: 0100 1000 0110 0010 */
	120	{&upd7810_device::SKNIT_F1, 2, 8, 8,L0\|L1}, /* 63: 0100 1000 0110 0011 */
	121	{&upd7810_device::SKNIT_F2, 2, 8, 8,L0\|L1}, /* 64: 0100 1000 0110 0100 */
	122	{&upd7810_device::SKNIT_FE0, 2, 8, 8,L0\|L1}, /* 65: 0100 1000 0110 0101 */
	123	{&upd7810_device::SKNIT_FE1, 2, 8, 8,L0\|L1}, /* 66: 0100 1000 0110 0110 */
	124	{&upd7810_device::SKNIT_FEIN, 2, 8, 8,L0\|L1}, /* 67: 0100 1000 0110 0111 */
	125	{&upd7810_device::SKNIT_FAD, 2, 8, 8,L0\|L1}, /* 68: 0100 1000 0110 1000 */
	126	{&upd7810_device::SKNIT_FSR, 2, 8, 8,L0\|L1}, /* 69: 0100 1000 0110 1001 */
	127	{&upd7810_device::SKNIT_FST, 2, 8, 8,L0\|L1}, /* 6a: 0100 1000 0110 1010 */
	128	{&upd7810_device::SKNIT_ER, 2, 8, 8,L0\|L1}, /* 6b: 0100 1000 0110 1011 */
	129	{&upd7810_device::SKNIT_OV, 2, 8, 8,L0\|L1}, /* 6c: 0100 1000 0110 1100 */
	130	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6d: 0100 1000 0110 1101 */
	131	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6e: 0100 1000 0110 1110 */
	132	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6f: 0100 1000 0110 1111 */
	133
	134	{&upd7810_device::SKNIT_AN4, 2, 8, 8,L0\|L1}, /* 70: 0100 1000 0111 0000 */
	135	{&upd7810_device::SKNIT_AN5, 2, 8, 8,L0\|L1}, /* 71: 0100 1000 0111 0001 */
	136	{&upd7810_device::SKNIT_AN6, 2, 8, 8,L0\|L1}, /* 72: 0100 1000 0111 0010 */
	137	{&upd7810_device::SKNIT_AN7, 2, 8, 8,L0\|L1}, /* 73: 0100 1000 0111 0011 */
	138	{&upd7810_device::SKNIT_SB, 2, 8, 8,L0\|L1}, /* 74: 0100 1000 0111 0100 */
	139	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 75: 0100 1000 0111 0101 */
	140	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 76: 0100 1000 0111 0110 */
	141	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 77: 0100 1000 0111 0111 */
	142	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 78: 0100 1000 0111 1000 */
	143	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 79: 0100 1000 0111 1001 */
	144	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7a: 0100 1000 0111 1010 */
	145	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7b: 0100 1000 0111 1011 */
	146	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7c: 0100 1000 0111 1100 */
	147	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7d: 0100 1000 0111 1101 */
	148	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7e: 0100 1000 0111 1110 */
	149	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7f: 0100 1000 0111 1111 */
	150
	151	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 80: 0100 1000 1000 0000 */
	152	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 81: 0100 1000 1000 0001 */
	153	{&upd7810_device::LDEAX_D, 2,14,11,L0\|L1}, /* 82: 0100 1000 1000 0010 */
	154	{&upd7810_device::LDEAX_H, 2,14,11,L0\|L1}, /* 83: 0100 1000 1000 0011 */
	155	{&upd7810_device::LDEAX_Dp, 2,14,11,L0\|L1}, /* 84: 0100 1000 1000 0100 */
	156	{&upd7810_device::LDEAX_Hp, 2,14,11,L0\|L1}, /* 85: 0100 1000 1000 0101 */
	157	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 86: 0100 1000 1000 0110 */
	158	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 87: 0100 1000 1000 0111 */
	159	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 88: 0100 1000 1000 1000 */
	160	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 89: 0100 1000 1000 1001 */
	161	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8a: 0100 1000 1000 1010 */
	162	{&upd7810_device::LDEAX_D_xx, 3,20,20,L0\|L1}, /* 8b: 0100 1000 1000 1011 xxxx xxxx */
	163	{&upd7810_device::LDEAX_H_A, 2,20,20,L0\|L1}, /* 8c: 0100 1000 1000 1100 */
	164	{&upd7810_device::LDEAX_H_B, 2,20,20,L0\|L1}, /* 8d: 0100 1000 1000 1101 */
	165	{&upd7810_device::LDEAX_H_EA, 2,20,20,L0\|L1}, /* 8e: 0100 1000 1000 1110 */
	166	{&upd7810_device::LDEAX_H_xx, 3,20,20,L0\|L1}, /* 8f: 0100 1000 1000 1111 xxxx xxxx */
	167
	168	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 90: 0100 1000 1000 0000 */
	169	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 91: 0100 1000 1000 0001 */
	170	{&upd7810_device::STEAX_D, 2,14,11,L0\|L1}, /* 92: 0100 1000 1000 0010 */
	171	{&upd7810_device::STEAX_H, 2,14,11,L0\|L1}, /* 93: 0100 1000 1000 0011 */
	172	{&upd7810_device::STEAX_Dp, 2,14,11,L0\|L1}, /* 94: 0100 1000 1000 0100 */
	173	{&upd7810_device::STEAX_Hp, 2,14,11,L0\|L1}, /* 95: 0100 1000 1000 0101 */
	174	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 96: 0100 1000 1000 0110 */
	175	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 97: 0100 1000 1000 0111 */
	176	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 98: 0100 1000 1000 1000 */
	177	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 99: 0100 1000 1000 1001 */
	178	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9a: 0100 1000 1000 1010 */
	179	{&upd7810_device::STEAX_D_xx, 3,20,20,L0\|L1}, /* 9b: 0100 1000 1000 1011 xxxx xxxx */
	180	{&upd7810_device::STEAX_H_A, 2,20,20,L0\|L1}, /* 9c: 0100 1000 1000 1100 */
	181	{&upd7810_device::STEAX_H_B, 2,20,20,L0\|L1}, /* 9d: 0100 1000 1000 1101 */
	182	{&upd7810_device::STEAX_H_EA, 2,20,20,L0\|L1}, /* 9e: 0100 1000 1000 1110 */
	183	{&upd7810_device::STEAX_H_xx, 3,20,20,L0\|L1}, /* 9f: 0100 1000 1000 1111 xxxx xxxx */
	184
	185	{&upd7810_device::DSLR_EA, 2, 8, 8,L0\|L1}, /* a0: 0100 1000 1010 0000 */
	186	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a1: 0100 1000 1010 0001 */
	187	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a2: 0100 1000 1010 0010 */
	188	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a3: 0100 1000 1010 0011 */
	189	{&upd7810_device::DSLL_EA, 2, 8, 8,L0\|L1}, /* a4: 0100 1000 1010 0100 */
	190	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a5: 0100 1000 1010 0101 */
	191	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a6: 0100 1000 1010 0110 */
	192	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a7: 0100 1000 1010 0111 */
	193	{&upd7810_device::TABLE, 2,17,17,L0\|L1}, /* a8: 0100 1000 1010 1000 */
	194	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a9: 0100 1000 1010 1001 */
	195	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* aa: 0100 1000 1010 1010 */
	196	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ab: 0100 1000 1010 1011 */
	197	// {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ac: 0100 1000 1010 1100 */
	198	// {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ad: 0100 1000 1010 1101 */
	199	// {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ae: 0100 1000 1010 1110 */
	200	// {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* af: 0100 1000 1010 1111 */
	201	{&upd7810_device::EXA, 2, 8, 8,L0\|L1}, /* ac: 0100 1000 1010 1100 / / 7807 */
	202	{&upd7810_device::EXR, 2, 8, 8,L0\|L1}, /* ad: 0100 1000 1010 1101 / / 7807 */
	203	{&upd7810_device::EXH, 2, 8, 8,L0\|L1}, /* ae: 0100 1000 1010 1110 / / 7807 */
	204	{&upd7810_device::EXX, 2, 8, 8,L0\|L1}, /* af: 0100 1000 1010 1111 / / 7807 */
	205	{&upd7810_device::DRLR_EA, 2, 8, 8,L0\|L1}, /* b0: 0100 1000 1011 0000 */
	206	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b1: 0100 1000 1011 0001 */
	207	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b2: 0100 1000 1011 0010 */
	208	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b3: 0100 1000 1011 0011 */
	209	{&upd7810_device::DRLL_EA, 2, 8, 8,L0\|L1}, /* b4: 0100 1000 1011 0100 */
	210	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b5: 0100 1000 1011 0101 */
	211	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b6: 0100 1000 1011 0110 */
	212	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b7: 0100 1000 1011 0111 */
	213	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b8: 0100 1000 1011 1000 */
	214	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b9: 0100 1000 1011 1001 */
	215	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ba: 0100 1000 1011 1010 */
	216	{&upd7810_device::STOP, 2,12,12,L0\|L1}, /* bb: 0100 1000 1011 1011 */
	217	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bc: 0100 1000 1011 1100 */
	218	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bd: 0100 1000 1011 1101 */
	219	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* be: 0100 1000 1011 1110 */
	220	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bf: 0100 1000 1011 1111 */
	221
	222	{&upd7810_device::DMOV_EA_ECNT, 2,14,11,L0\|L1}, /* c0: 0100 1000 1100 0000 */
	223	{&upd7810_device::DMOV_EA_ECPT, 2,14,11,L0\|L1}, /* c1: 0100 1000 1100 0001 */
	224	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c2: 0100 1000 1100 0010 */
	225	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c3: 0100 1000 1100 0011 */
	226	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c4: 0100 1000 1100 0100 */
	227	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c5: 0100 1000 1100 0101 */
	228	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c6: 0100 1000 1100 0110 */
	229	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c7: 0100 1000 1100 0111 */
	230	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c8: 0100 1000 1100 1000 */
	231	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c9: 0100 1000 1100 1001 */
	232	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ca: 0100 1000 1100 1010 */
	233	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* cb: 0100 1000 1100 1011 */
	234	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* cc: 0100 1000 1100 1100 */
	235	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* cd: 0100 1000 1100 1101 */
	236	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ce: 0100 1000 1100 1110 */
	237	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* cf: 0100 1000 1100 1111 */
	238
	239	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d0: 0100 1000 1101 0000 */
	240	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d1: 0100 1000 1101 0001 */
	241	{&upd7810_device::DMOV_ETM0_EA, 2,14,11,L0\|L1}, /* d2: 0100 1000 1101 0010 */
	242	{&upd7810_device::DMOV_ETM1_EA, 2,14,11,L0\|L1}, /* d3: 0100 1000 1101 0011 */
	243	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d4: 0100 1000 1101 0100 */
	244	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d5: 0100 1000 1101 0101 */
	245	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d6: 0100 1000 1101 0110 */
	246	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d7: 0100 1000 1101 0111 */
	247	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d8: 0100 1000 1101 1000 */
	248	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d9: 0100 1000 1101 1001 */
	249	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* da: 0100 1000 1101 1010 */
	250	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* db: 0100 1000 1101 1011 */
	251	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* dc: 0100 1000 1101 1100 */
	252	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* dd: 0100 1000 1101 1101 */
	253	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* de: 0100 1000 1101 1110 */
	254	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* df: 0100 1000 1101 1111 */
	255
	256	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e0: 0100 1000 1110 0000 */
	257	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e1: 0100 1000 1110 0001 */
	258	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e2: 0100 1000 1110 0010 */
	259	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e3: 0100 1000 1110 0011 */
	260	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e4: 0100 1000 1110 0100 */
	261	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e5: 0100 1000 1110 0101 */
	262	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e6: 0100 1000 1110 0110 */
	263	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e7: 0100 1000 1110 0111 */
	264	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e8: 0100 1000 1110 1000 */
	265	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e9: 0100 1000 1110 1001 */
	266	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ea: 0100 1000 1110 1010 */
	267	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* eb: 0100 1000 1110 1011 */
	268	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ec: 0100 1000 1110 1100 */
	269	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ed: 0100 1000 1110 1101 */
	270	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ee: 0100 1000 1110 1110 */
	271	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ef: 0100 1000 1110 1111 */
	272
	273	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f0: 0100 1000 1111 0000 */
	274	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f1: 0100 1000 1111 0001 */
	275	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f2: 0100 1000 1111 0010 */
	276	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f3: 0100 1000 1111 0011 */
	277	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f4: 0100 1000 1111 0100 */
	278	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f5: 0100 1000 1111 0101 */
	279	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f6: 0100 1000 1111 0110 */
	280	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f7: 0100 1000 1111 0111 */
	281	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f8: 0100 1000 1111 1000 */
	282	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f9: 0100 1000 1111 1001 */
	283	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* fa: 0100 1000 1111 1010 */
	284	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* fb: 0100 1000 1111 1011 */
	285	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* fc: 0100 1000 1111 1100 */
	286	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* fd: 0100 1000 1111 1101 */
	287	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* fe: 0100 1000 1111 1110 */
	288	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1} /* ff: 0100 1000 1111 1111 */
	289	};
	290
	291	/* prefix 4C */
	292	const struct upd7810_device::opcode_s upd7810_device::s_op4C[256] =
	293	{
	294	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 00: 0100 1100 0000 0000 */
	295	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 01: 0100 1100 0000 0001 */
	296	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 02: 0100 1100 0000 0010 */
	297	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 03: 0100 1100 0000 0011 */
	298	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 04: 0100 1100 0000 0100 */
	299	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 05: 0100 1100 0000 0101 */
	300	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 06: 0100 1100 0000 0110 */
	301	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 07: 0100 1100 0000 0111 */
	302	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 08: 0100 1100 0000 1000 */
	303	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 09: 0100 1100 0000 1001 */
	304	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0a: 0100 1100 0000 1010 */
	305	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0b: 0100 1100 0000 1011 */
	306	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0c: 0100 1100 0000 1100 */
	307	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0d: 0100 1100 0000 1101 */
	308	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0e: 0100 1100 0000 1110 */
	309	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0f: 0100 1100 0000 1111 */
	310
	311	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 10: 0100 1100 0001 0000 */
	312	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 11: 0100 1100 0001 0001 */
	313	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 12: 0100 1100 0001 0010 */
	314	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 13: 0100 1100 0001 0011 */
	315	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 14: 0100 1100 0001 0100 */
	316	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 15: 0100 1100 0001 0101 */
	317	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 16: 0100 1100 0001 0110 */
	318	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 17: 0100 1100 0001 0111 */
	319	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 18: 0100 1100 0001 1000 */
	320	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 19: 0100 1100 0001 1001 */
	321	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1a: 0100 1100 0001 1010 */
	322	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1b: 0100 1100 0001 1011 */
	323	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1c: 0100 1100 0001 1100 */
	324	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1d: 0100 1100 0001 1101 */
	325	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1e: 0100 1100 0001 1110 */
	326	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1f: 0100 1100 0001 1111 */
	327
	328	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 20: 0100 1100 0010 0000 */
	329	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 21: 0100 1100 0010 0001 */
	330	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 22: 0100 1100 0010 0010 */
	331	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 23: 0100 1100 0010 0011 */
	332	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 24: 0100 1100 0010 0100 */
	333	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 25: 0100 1100 0010 0101 */
	334	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 26: 0100 1100 0010 0110 */
	335	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 27: 0100 1100 0010 0111 */
	336	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 28: 0100 1100 0010 1000 */
	337	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 29: 0100 1100 0010 1001 */
	338	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2a: 0100 1100 0010 1010 */
	339	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2b: 0100 1100 0010 1011 */
	340	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2c: 0100 1100 0010 1100 */
	341	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2d: 0100 1100 0010 1101 */
	342	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2e: 0100 1100 0010 1110 */
	343	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2f: 0100 1100 0010 1111 */
	344
	345	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 30: 0100 1100 0011 0000 */
	346	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 31: 0100 1100 0011 0001 */
	347	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 32: 0100 1100 0011 0010 */
	348	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 33: 0100 1100 0011 0011 */
	349	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 34: 0100 1100 0011 0100 */
	350	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 35: 0100 1100 0011 0101 */
	351	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 36: 0100 1100 0011 0110 */
	352	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 37: 0100 1100 0011 0111 */
	353	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 38: 0100 1100 0011 1000 */
	354	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 39: 0100 1100 0011 1001 */
	355	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3a: 0100 1100 0011 1010 */
	356	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3b: 0100 1100 0011 1011 */
	357	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3c: 0100 1100 0011 1100 */
	358	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3d: 0100 1100 0011 1101 */
	359	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3e: 0100 1100 0011 1110 */
	360	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3f: 0100 1100 0011 1111 */
	361
	362	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 40: 0100 1100 0100 0000 */
	363	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 41: 0100 1100 0100 0001 */
	364	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 42: 0100 1100 0100 0010 */
	365	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 43: 0100 1100 0100 0011 */
	366	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 44: 0100 1100 0100 0100 */
	367	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 45: 0100 1100 0100 0101 */
	368	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 46: 0100 1100 0100 0110 */
	369	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 47: 0100 1100 0100 0111 */
	370	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 48: 0100 1100 0100 1000 */
	371	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 49: 0100 1100 0100 1001 */
	372	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4a: 0100 1100 0100 1010 */
	373	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4b: 0100 1100 0100 1011 */
	374	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4c: 0100 1100 0100 1100 */
	375	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4d: 0100 1100 0100 1101 */
	376	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4e: 0100 1100 0100 1110 */
	377	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4f: 0100 1100 0100 1111 */
	378
	379	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 50: 0100 1100 0101 0000 */
	380	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 51: 0100 1100 0101 0001 */
	381	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 52: 0100 1100 0101 0010 */
	382	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 53: 0100 1100 0101 0011 */
	383	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 54: 0100 1100 0101 0100 */
	384	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 55: 0100 1100 0101 0101 */
	385	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 56: 0100 1100 0101 0110 */
	386	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 57: 0100 1100 0101 0111 */
	387	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 58: 0100 1100 0101 1000 */
	388	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 59: 0100 1100 0101 1001 */
	389	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5a: 0100 1100 0101 1010 */
	390	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5b: 0100 1100 0101 1011 */
	391	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5c: 0100 1100 0101 1100 */
	392	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5d: 0100 1100 0101 1101 */
	393	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5e: 0100 1100 0101 1110 */
	394	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5f: 0100 1100 0101 1111 */
	395
	396	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 60: 0100 1100 0110 0000 */
	397	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 61: 0100 1100 0110 0001 */
	398	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 62: 0100 1100 0110 0010 */
	399	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 63: 0100 1100 0110 0011 */
	400	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 64: 0100 1100 0110 0100 */
	401	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 65: 0100 1100 0110 0101 */
	402	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 66: 0100 1100 0110 0110 */
	403	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 67: 0100 1100 0110 0111 */
	404	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 68: 0100 1100 0110 1000 */
	405	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 69: 0100 1100 0110 1001 */
	406	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6a: 0100 1100 0110 1010 */
	407	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6b: 0100 1100 0110 1011 */
	408	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6c: 0100 1100 0110 1100 */
	409	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6d: 0100 1100 0110 1101 */
	410	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6e: 0100 1100 0110 1110 */
	411	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6f: 0100 1100 0110 1111 */
	412
	413	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 70: 0100 1100 0111 0000 */
	414	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 71: 0100 1100 0111 0001 */
	415	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 72: 0100 1100 0111 0010 */
	416	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 73: 0100 1100 0111 0011 */
	417	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 74: 0100 1100 0111 0100 */
	418	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 75: 0100 1100 0111 0101 */
	419	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 76: 0100 1100 0111 0110 */
	420	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 77: 0100 1100 0111 0111 */
	421	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 78: 0100 1100 0111 1000 */
	422	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 79: 0100 1100 0111 1001 */
	423	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7a: 0100 1100 0111 1010 */
	424	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7b: 0100 1100 0111 1011 */
	425	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7c: 0100 1100 0111 1100 */
	426	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7d: 0100 1100 0111 1101 */
	427	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7e: 0100 1100 0111 1110 */
	428	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7f: 0100 1100 0111 1111 */
	429
	430	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 80: 0100 1100 1000 0000 */
	431	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 81: 0100 1100 1000 0001 */
	432	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 82: 0100 1100 1000 0010 */
	433	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 83: 0100 1100 1000 0011 */
	434	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 84: 0100 1100 1000 0100 */
	435	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 85: 0100 1100 1000 0101 */
	436	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 86: 0100 1100 1000 0110 */
	437	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 87: 0100 1100 1000 0111 */
	438	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 88: 0100 1100 1000 1000 */
	439	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 89: 0100 1100 1000 1001 */
	440	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8a: 0100 1100 1000 1010 */
	441	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8b: 0100 1100 1000 1011 */
	442	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8c: 0100 1100 1000 1100 */
	443	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8d: 0100 1100 1000 1101 */
	444	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8e: 0100 1100 1000 1110 */
	445	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8f: 0100 1100 1000 1111 */
	446
	447	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 90: 0100 1100 1001 0000 */
	448	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 91: 0100 1100 1001 0001 */
	449	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 92: 0100 1100 1001 0010 */
	450	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 93: 0100 1100 1001 0011 */
	451	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 94: 0100 1100 1001 0100 */
	452	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 95: 0100 1100 1001 0101 */
	453	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 96: 0100 1100 1001 0110 */
	454	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 97: 0100 1100 1001 0111 */
	455	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 98: 0100 1100 1001 1000 */
	456	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 99: 0100 1100 1001 1001 */
	457	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9a: 0100 1100 1001 1010 */
	458	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9b: 0100 1100 1001 1011 */
	459	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9c: 0100 1100 1001 1100 */
	460	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9d: 0100 1100 1001 1101 */
	461	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9e: 0100 1100 1001 1110 */
	462	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9f: 0100 1100 1001 1111 */
	463
	464	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a0: 0100 1100 1010 0000 */
	465	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a1: 0100 1100 1010 0001 */
	466	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a2: 0100 1100 1010 0010 */
	467	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a3: 0100 1100 1010 0011 */
	468	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a4: 0100 1100 1010 0100 */
	469	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a5: 0100 1100 1010 0101 */
	470	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a6: 0100 1100 1010 0110 */
	471	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a7: 0100 1100 1010 0111 */
	472	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a8: 0100 1100 1010 1000 */
	473	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a9: 0100 1100 1010 1001 */
	474	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* aa: 0100 1100 1010 1010 */
	475	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ab: 0100 1100 1010 1011 */
	476	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ac: 0100 1100 1010 1100 */
	477	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ad: 0100 1100 1010 1101 */
	478	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ae: 0100 1100 1010 1110 */
	479	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* af: 0100 1100 1010 1111 */
	480
	481	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b0: 0100 1100 1011 0000 */
	482	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b1: 0100 1100 1011 0001 */
	483	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b2: 0100 1100 1011 0010 */
	484	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b3: 0100 1100 1011 0011 */
	485	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b4: 0100 1100 1011 0100 */
	486	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b5: 0100 1100 1011 0101 */
	487	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b6: 0100 1100 1011 0110 */
	488	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b7: 0100 1100 1011 0111 */
	489	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b8: 0100 1100 1011 1000 */
	490	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b9: 0100 1100 1011 1001 */
	491	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ba: 0100 1100 1011 1010 */
	492	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bb: 0100 1100 1011 1011 */
	493	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bc: 0100 1100 1011 1100 */
	494	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bd: 0100 1100 1011 1101 */
	495	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* be: 0100 1100 1011 1110 */
	496	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bf: 0100 1100 1011 1111 */
	497
	498	{&upd7810_device::MOV_A_PA, 2,10,10,L0\|L1}, /* c0: 0100 1100 1100 0000 */
	499	{&upd7810_device::MOV_A_PB, 2,10,10,L0\|L1}, /* c1: 0100 1100 1100 0001 */
	500	{&upd7810_device::MOV_A_PC, 2,10,10,L0\|L1}, /* c2: 0100 1100 1100 0010 */
	501	{&upd7810_device::MOV_A_PD, 2,10,10,L0\|L1}, /* c3: 0100 1100 1100 0011 */
	502	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* c4: 0100 1100 1100 0100 */
	503	{&upd7810_device::MOV_A_PF, 2,10,10,L0\|L1}, /* c5: 0100 1100 1100 0101 */
	504	{&upd7810_device::MOV_A_MKH, 2,10,10,L0\|L1}, /* c6: 0100 1100 1100 0110 */
	505	{&upd7810_device::MOV_A_MKL, 2,10,10,L0\|L1}, /* c7: 0100 1100 1100 0111 */
	506	{&upd7810_device::MOV_A_ANM, 2,10,10,L0\|L1}, /* c8: 0100 1100 1100 1000 */
	507	{&upd7810_device::MOV_A_SMH, 2,10,10,L0\|L1}, /* c9: 0100 1100 1100 1001 */
	508	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ca: 0100 1100 1100 1010 */
	509	{&upd7810_device::MOV_A_EOM, 2,10,10,L0\|L1}, /* cb: 0100 1100 1100 1011 */
	510	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* cc: 0100 1100 1100 1100 */
	511	{&upd7810_device::MOV_A_TMM, 2,10,10,L0\|L1}, /* cd: 0100 1100 1100 1101 */
	512	// {&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ce: 0100 1100 1100 1110 */
	513	{&upd7810_device::MOV_A_PT, 2,10,10,L0\|L1}, /* ce: 0100 1100 1100 1110 / / 7807 */
	514	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* cf: 0100 1100 1100 1111 */
	515
	516	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d0: 0100 1100 1101 0000 */
	517	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d1: 0100 1100 1101 0001 */
	518	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d2: 0100 1100 1101 0010 */
	519	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d3: 0100 1100 1101 0011 */
	520	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d4: 0100 1100 1101 0100 */
	521	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d5: 0100 1100 1101 0101 */
	522	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d6: 0100 1100 1101 0110 */
	523	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d7: 0100 1100 1101 0111 */
	524	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d8: 0100 1100 1101 1000 */
	525	{&upd7810_device::MOV_A_RXB, 2,10,10,L0\|L1}, /* d9: 0100 1100 1101 1001 */
	526	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* da: 0100 1100 1101 1010 */
	527	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* db: 0100 1100 1101 1011 */
	528	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* dc: 0100 1100 1101 1100 */
	529	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* dd: 0100 1100 1101 1101 */
	530	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* de: 0100 1100 1101 1110 */
	531	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* df: 0100 1100 1101 1111 */
	532
	533	{&upd7810_device::MOV_A_CR0, 2,10,10,L0\|L1}, /* e0: 0100 1100 1110 0000 */
	534	{&upd7810_device::MOV_A_CR1, 2,10,10,L0\|L1}, /* e1: 0100 1100 1110 0001 */
	535	{&upd7810_device::MOV_A_CR2, 2,10,10,L0\|L1}, /* e2: 0100 1100 1110 0010 */
	536	{&upd7810_device::MOV_A_CR3, 2,10,10,L0\|L1}, /* e3: 0100 1100 1110 0011 */
	537	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e4: 0100 1100 1110 0100 */
	538	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e5: 0100 1100 1110 0101 */
	539	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e6: 0100 1100 1110 0110 */
	540	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e7: 0100 1100 1110 0111 */
	541	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e8: 0100 1100 1110 1000 */
	542	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e9: 0100 1100 1110 1001 */
	543	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ea: 0100 1100 1110 1010 */
	544	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* eb: 0100 1100 1110 1011 */
	545	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ec: 0100 1100 1110 1100 */
	546	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ed: 0100 1100 1110 1101 */
	547	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ee: 0100 1100 1110 1110 */
	548	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ef: 0100 1100 1110 1111 */
	549
	550	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f0: 0100 1100 1111 0000 */
	551	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f1: 0100 1100 1111 0001 */
	552	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f2: 0100 1100 1111 0010 */
	553	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f3: 0100 1100 1111 0011 */
	554	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f4: 0100 1100 1111 0100 */
	555	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f5: 0100 1100 1111 0101 */
	556	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f6: 0100 1100 1111 0110 */
	557	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f7: 0100 1100 1111 0111 */
	558	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f8: 0100 1100 1111 1000 */
	559	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f9: 0100 1100 1111 1001 */
	560	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fa: 0100 1100 1111 1010 */
	561	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fb: 0100 1100 1111 1011 */
	562	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fc: 0100 1100 1111 1100 */
	563	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fd: 0100 1100 1111 1101 */
	564	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fe: 0100 1100 1111 1110 */
	565	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ff: 0100 1100 1111 1111 */
	566	};
	567
	568	/* prefix 4D */
	569	const struct upd7810_device::opcode_s upd7810_device::s_op4D[256] =
	570	{
	571	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 00: 0100 1101 0000 0000 */
	572	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 01: 0100 1101 0000 0001 */
	573	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 02: 0100 1101 0000 0010 */
	574	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 03: 0100 1101 0000 0011 */
	575	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 04: 0100 1101 0000 0100 */
	576	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 05: 0100 1101 0000 0101 */
	577	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 06: 0100 1101 0000 0110 */
	578	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 07: 0100 1101 0000 0111 */
	579	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 08: 0100 1101 0000 1000 */
	580	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 09: 0100 1101 0000 1001 */
	581	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0a: 0100 1101 0000 1010 */
	582	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0b: 0100 1101 0000 1011 */
	583	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0c: 0100 1101 0000 1100 */
	584	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0d: 0100 1101 0000 1101 */
	585	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0e: 0100 1101 0000 1110 */
	586	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0f: 0100 1101 0000 1111 */
	587
	588	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 10: 0100 1101 0001 0000 */
	589	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 11: 0100 1101 0001 0001 */
	590	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 12: 0100 1101 0001 0010 */
	591	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 13: 0100 1101 0001 0011 */
	592	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 14: 0100 1101 0001 0100 */
	593	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 15: 0100 1101 0001 0101 */
	594	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 16: 0100 1101 0001 0110 */
	595	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 17: 0100 1101 0001 0111 */
	596	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 18: 0100 1101 0001 1000 */
	597	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 19: 0100 1101 0001 1001 */
	598	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1a: 0100 1101 0001 1010 */
	599	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1b: 0100 1101 0001 1011 */
	600	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1c: 0100 1101 0001 1100 */
	601	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1d: 0100 1101 0001 1101 */
	602	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1e: 0100 1101 0001 1110 */
	603	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1f: 0100 1101 0001 1111 */
	604
	605	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 20: 0100 1101 0010 0000 */
	606	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 21: 0100 1101 0010 0001 */
	607	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 22: 0100 1101 0010 0010 */
	608	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 23: 0100 1101 0010 0011 */
	609	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 24: 0100 1101 0010 0100 */
	610	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 25: 0100 1101 0010 0101 */
	611	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 26: 0100 1101 0010 0110 */
	612	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 27: 0100 1101 0010 0111 */
	613	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 28: 0100 1101 0010 1000 */
	614	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 29: 0100 1101 0010 1001 */
	615	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2a: 0100 1101 0010 1010 */
	616	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2b: 0100 1101 0010 1011 */
	617	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2c: 0100 1101 0010 1100 */
	618	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2d: 0100 1101 0010 1101 */
	619	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2e: 0100 1101 0010 1110 */
	620	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2f: 0100 1101 0010 1111 */
	621
	622	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 30: 0100 1101 0011 0000 */
	623	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 31: 0100 1101 0011 0001 */
	624	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 32: 0100 1101 0011 0010 */
	625	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 33: 0100 1101 0011 0011 */
	626	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 34: 0100 1101 0011 0100 */
	627	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 35: 0100 1101 0011 0101 */
	628	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 36: 0100 1101 0011 0110 */
	629	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 37: 0100 1101 0011 0111 */
	630	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 38: 0100 1101 0011 1000 */
	631	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 39: 0100 1101 0011 1001 */
	632	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3a: 0100 1101 0011 1010 */
	633	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3b: 0100 1101 0011 1011 */
	634	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3c: 0100 1101 0011 1100 */
	635	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3d: 0100 1101 0011 1101 */
	636	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3e: 0100 1101 0011 1110 */
	637	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3f: 0100 1101 0011 1111 */
	638
	639	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 40: 0100 1101 0100 0000 */
	640	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 41: 0100 1101 0100 0001 */
	641	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 42: 0100 1101 0100 0010 */
	642	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 43: 0100 1101 0100 0011 */
	643	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 44: 0100 1101 0100 0100 */
	644	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 45: 0100 1101 0100 0101 */
	645	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 46: 0100 1101 0100 0110 */
	646	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 47: 0100 1101 0100 0111 */
	647	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 48: 0100 1101 0100 1000 */
	648	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 49: 0100 1101 0100 1001 */
	649	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4a: 0100 1101 0100 1010 */
	650	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4b: 0100 1101 0100 1011 */
	651	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4c: 0100 1101 0100 1100 */
	652	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4d: 0100 1101 0100 1101 */
	653	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4e: 0100 1101 0100 1110 */
	654	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4f: 0100 1101 0100 1111 */
	655
	656	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 50: 0100 1101 0101 0000 */
	657	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 51: 0100 1101 0101 0001 */
	658	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 52: 0100 1101 0101 0010 */
	659	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 53: 0100 1101 0101 0011 */
	660	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 54: 0100 1101 0101 0100 */
	661	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 55: 0100 1101 0101 0101 */
	662	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 56: 0100 1101 0101 0110 */
	663	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 57: 0100 1101 0101 0111 */
	664	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 58: 0100 1101 0101 1000 */
	665	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 59: 0100 1101 0101 1001 */
	666	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5a: 0100 1101 0101 1010 */
	667	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5b: 0100 1101 0101 1011 */
	668	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5c: 0100 1101 0101 1100 */
	669	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5d: 0100 1101 0101 1101 */
	670	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5e: 0100 1101 0101 1110 */
	671	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5f: 0100 1101 0101 1111 */
	672
	673	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 60: 0100 1101 0110 0000 */
	674	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 61: 0100 1101 0110 0001 */
	675	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 62: 0100 1101 0110 0010 */
	676	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 63: 0100 1101 0110 0011 */
	677	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 64: 0100 1101 0110 0100 */
	678	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 65: 0100 1101 0110 0101 */
	679	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 66: 0100 1101 0110 0110 */
	680	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 67: 0100 1101 0110 0111 */
	681	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 68: 0100 1101 0110 1000 */
	682	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 69: 0100 1101 0110 1001 */
	683	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6a: 0100 1101 0110 1010 */
	684	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6b: 0100 1101 0110 1011 */
	685	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6c: 0100 1101 0110 1100 */
	686	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6d: 0100 1101 0110 1101 */
	687	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6e: 0100 1101 0110 1110 */
	688	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 6f: 0100 1101 0110 1111 */
	689
	690	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 70: 0100 1101 0111 0000 */
	691	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 71: 0100 1101 0111 0001 */
	692	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 72: 0100 1101 0111 0010 */
	693	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 73: 0100 1101 0111 0011 */
	694	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 74: 0100 1101 0111 0100 */
	695	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 75: 0100 1101 0111 0101 */
	696	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 76: 0100 1101 0111 0110 */
	697	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 77: 0100 1101 0111 0111 */
	698	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 78: 0100 1101 0111 1000 */
	699	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 79: 0100 1101 0111 1001 */
	700	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7a: 0100 1101 0111 1010 */
	701	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7b: 0100 1101 0111 1011 */
	702	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7c: 0100 1101 0111 1100 */
	703	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7d: 0100 1101 0111 1101 */
	704	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7e: 0100 1101 0111 1110 */
	705	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 7f: 0100 1101 0111 1111 */
	706
	707	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 80: 0100 1101 1000 0000 */
	708	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 81: 0100 1101 1000 0001 */
	709	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 82: 0100 1101 1000 0010 */
	710	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 83: 0100 1101 1000 0011 */
	711	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 84: 0100 1101 1000 0100 */
	712	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 85: 0100 1101 1000 0101 */
	713	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 86: 0100 1101 1000 0110 */
	714	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 87: 0100 1101 1000 0111 */
	715	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 88: 0100 1101 1000 1000 */
	716	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 89: 0100 1101 1000 1001 */
	717	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8a: 0100 1101 1000 1010 */
	718	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8b: 0100 1101 1000 1011 */
	719	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8c: 0100 1101 1000 1100 */
	720	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8d: 0100 1101 1000 1101 */
	721	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8e: 0100 1101 1000 1110 */
	722	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8f: 0100 1101 1000 1111 */
	723
	724	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 90: 0100 1101 1001 0000 */
	725	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 91: 0100 1101 1001 0001 */
	726	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 92: 0100 1101 1001 0010 */
	727	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 93: 0100 1101 1001 0011 */
	728	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 94: 0100 1101 1001 0100 */
	729	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 95: 0100 1101 1001 0101 */
	730	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 96: 0100 1101 1001 0110 */
	731	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 97: 0100 1101 1001 0111 */
	732	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 98: 0100 1101 1001 1000 */
	733	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 99: 0100 1101 1001 1001 */
	734	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9a: 0100 1101 1001 1010 */
	735	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9b: 0100 1101 1001 1011 */
	736	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9c: 0100 1101 1001 1100 */
	737	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9d: 0100 1101 1001 1101 */
	738	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9e: 0100 1101 1001 1110 */
	739	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9f: 0100 1101 1001 1111 */
	740
	741	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a0: 0100 1101 1010 0000 */
	742	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a1: 0100 1101 1010 0001 */
	743	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a2: 0100 1101 1010 0010 */
	744	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a3: 0100 1101 1010 0011 */
	745	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a4: 0100 1101 1010 0100 */
	746	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a5: 0100 1101 1010 0101 */
	747	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a6: 0100 1101 1010 0110 */
	748	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a7: 0100 1101 1010 0111 */
	749	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a8: 0100 1101 1010 1000 */
	750	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a9: 0100 1101 1010 1001 */
	751	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* aa: 0100 1101 1010 1010 */
	752	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ab: 0100 1101 1010 1011 */
	753	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ac: 0100 1101 1010 1100 */
	754	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ad: 0100 1101 1010 1101 */
	755	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ae: 0100 1101 1010 1110 */
	756	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* af: 0100 1101 1010 1111 */
	757
	758	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b0: 0100 1101 1011 0000 */
	759	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b1: 0100 1101 1011 0001 */
	760	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b2: 0100 1101 1011 0010 */
	761	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b3: 0100 1101 1011 0011 */
	762	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b4: 0100 1101 1011 0100 */
	763	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b5: 0100 1101 1011 0101 */
	764	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b6: 0100 1101 1011 0110 */
	765	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b7: 0100 1101 1011 0111 */
	766	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b8: 0100 1101 1011 1000 */
	767	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b9: 0100 1101 1011 1001 */
	768	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ba: 0100 1101 1011 1010 */
	769	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bb: 0100 1101 1011 1011 */
	770	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bc: 0100 1101 1011 1100 */
	771	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bd: 0100 1101 1011 1101 */
	772	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* be: 0100 1101 1011 1110 */
	773	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bf: 0100 1101 1011 1111 */
	774
	775	{&upd7810_device::MOV_PA_A, 2,10,10,L0\|L1}, /* c0: 0100 1101 1100 0000 */
	776	{&upd7810_device::MOV_PB_A, 2,10,10,L0\|L1}, /* c1: 0100 1101 1100 0001 */
	777	{&upd7810_device::MOV_PC_A, 2,10,10,L0\|L1}, /* c2: 0100 1101 1100 0010 */
	778	{&upd7810_device::MOV_PD_A, 2,10,10,L0\|L1}, /* c3: 0100 1101 1100 0011 */
	779	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* c4: 0100 1101 1100 0100 */
	780	{&upd7810_device::MOV_PF_A, 2,10,10,L0\|L1}, /* c5: 0100 1101 1100 0101 */
	781	{&upd7810_device::MOV_MKH_A, 2,10,10,L0\|L1}, /* c6: 0100 1101 1100 0110 */
	782	{&upd7810_device::MOV_MKL_A, 2,10,10,L0\|L1}, /* c7: 0100 1101 1100 0111 */
	783	{&upd7810_device::MOV_ANM_A, 2,10,10,L0\|L1}, /* c8: 0100 1101 1100 1000 */
	784	{&upd7810_device::MOV_SMH_A, 2,10,10,L0\|L1}, /* c9: 0100 1101 1100 1001 */
	785	{&upd7810_device::MOV_SML_A, 2,10,10,L0\|L1}, /* ca: 0100 1101 1100 1010 */
	786	{&upd7810_device::MOV_EOM_A, 2,10,10,L0\|L1}, /* cb: 0100 1101 1100 1011 */
	787	{&upd7810_device::MOV_ETMM_A, 2,10,10,L0\|L1}, /* cc: 0100 1101 1100 1100 */
	788	{&upd7810_device::MOV_TMM_A, 2,10,10,L0\|L1}, /* cd: 0100 1101 1100 1101 */
	789	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ce: 0100 1101 1100 1110 */
	790	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* cf: 0100 1101 1100 1111 */
	791
	792	{&upd7810_device::MOV_MM_A, 2,10,10,L0\|L1}, /* d0: 0100 1101 1101 0000 */
	793	{&upd7810_device::MOV_MCC_A, 2,10,10,L0\|L1}, /* d1: 0100 1101 1101 0001 */
	794	{&upd7810_device::MOV_MA_A, 2,10,10,L0\|L1}, /* d2: 0100 1101 1101 0010 */
	795	{&upd7810_device::MOV_MB_A, 2,10,10,L0\|L1}, /* d3: 0100 1101 1101 0011 */
	796	{&upd7810_device::MOV_MC_A, 2,10,10,L0\|L1}, /* d4: 0100 1101 1101 0100 */
	797	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d5: 0100 1101 1101 0101 */
	798	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d6: 0100 1101 1101 0110 */
	799	{&upd7810_device::MOV_MF_A, 2,10,10,L0\|L1}, /* d7: 0100 1101 1101 0111 */
	800	{&upd7810_device::MOV_TXB_A, 2,10,10,L0\|L1}, /* d8: 0100 1101 1101 1000 */
	801	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* d9: 0100 1101 1101 1001 */
	802	{&upd7810_device::MOV_TM0_A, 2,10,10,L0\|L1}, /* da: 0100 1101 1101 1010 */
	803	{&upd7810_device::MOV_TM1_A, 2,10,10,L0\|L1}, /* db: 0100 1101 1101 1011 */
	804	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* dc: 0100 1101 1101 1100 */
	805	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* dd: 0100 1101 1101 1101 */
	806	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* de: 0100 1101 1101 1110 */
	807	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* df: 0100 1101 1101 1111 */
	808
	809	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e0: 0100 1101 1110 0000 */
	810	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e1: 0100 1101 1110 0001 */
	811	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e2: 0100 1101 1110 0010 */
	812	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e3: 0100 1101 1110 0011 */
	813	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e4: 0100 1101 1110 0100 */
	814	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e5: 0100 1101 1110 0101 */
	815	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e6: 0100 1101 1110 0110 */
	816	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e7: 0100 1101 1110 0111 */
	817	{&upd7810_device::MOV_ZCM_A, 2,10,10,L0\|L1}, /* e8: 0100 1101 1110 1000 */
	818	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* e9: 0100 1101 1110 1001 */
	819	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ea: 0100 1101 1110 1010 */
	820	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* eb: 0100 1101 1110 1011 */
	821	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ec: 0100 1101 1110 1100 */
	822	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ed: 0100 1101 1110 1101 */
	823	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ee: 0100 1101 1110 1110 */
	824	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* ef: 0100 1101 1110 1111 */
	825
	826	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f0: 0100 1101 1111 0000 */
	827	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f1: 0100 1101 1111 0001 */
	828	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f2: 0100 1101 1111 0010 */
	829	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f3: 0100 1101 1111 0011 */
	830	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f4: 0100 1101 1111 0100 */
	831	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f5: 0100 1101 1111 0101 */
	832	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f6: 0100 1101 1111 0110 */
	833	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f7: 0100 1101 1111 0111 */
	834	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f8: 0100 1101 1111 1000 */
	835	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* f9: 0100 1101 1111 1001 */
	836	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fa: 0100 1101 1111 1010 */
	837	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fb: 0100 1101 1111 1011 */
	838	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fc: 0100 1101 1111 1100 */
	839	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fd: 0100 1101 1111 1101 */
	840	{&upd7810_device::illegal2, 2,10,10,L0\|L1}, /* fe: 0100 1101 1111 1110 */
	841	{&upd7810_device::illegal2, 2,10,10,L0\|L1} /* ff: 0100 1101 1111 1111 */
	842	};
	843
	844	/* prefix 60 */
	845	const struct upd7810_device::opcode_s upd7810_device::s_op60[256] =
	846	{
	847	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 00: 0110 0000 0000 0000 */
	848	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 01: 0110 0000 0000 0001 */
	849	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 02: 0110 0000 0000 0010 */
	850	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 03: 0110 0000 0000 0011 */
	851	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 04: 0110 0000 0000 0100 */
	852	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 05: 0110 0000 0000 0101 */
	853	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 06: 0110 0000 0000 0110 */
	854	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 07: 0110 0000 0000 0111 */
	855	{&upd7810_device::ANA_V_A, 2, 8, 8,L0\|L1}, /* 08: 0110 0000 0000 1000 */
	856	{&upd7810_device::ANA_A_A, 2, 8, 8,L0\|L1}, /* 09: 0110 0000 0000 1001 */
	857	{&upd7810_device::ANA_B_A, 2, 8, 8,L0\|L1}, /* 0a: 0110 0000 0000 1010 */
	858	{&upd7810_device::ANA_C_A, 2, 8, 8,L0\|L1}, /* 0b: 0110 0000 0000 1011 */
	859	{&upd7810_device::ANA_D_A, 2, 8, 8,L0\|L1}, /* 0c: 0110 0000 0000 1100 */
	860	{&upd7810_device::ANA_E_A, 2, 8, 8,L0\|L1}, /* 0d: 0110 0000 0000 1101 */
	861	{&upd7810_device::ANA_H_A, 2, 8, 8,L0\|L1}, /* 0e: 0110 0000 0000 1110 */
	862	{&upd7810_device::ANA_L_A, 2, 8, 8,L0\|L1}, /* 0f: 0110 0000 0000 1111 */
	863
	864	{&upd7810_device::XRA_V_A, 2, 8, 8,L0\|L1}, /* 10: 0110 0000 0001 0000 */
	865	{&upd7810_device::XRA_A_A, 2, 8, 8,L0\|L1}, /* 11: 0110 0000 0001 0001 */
	866	{&upd7810_device::XRA_B_A, 2, 8, 8,L0\|L1}, /* 12: 0110 0000 0001 0010 */
	867	{&upd7810_device::XRA_C_A, 2, 8, 8,L0\|L1}, /* 13: 0110 0000 0001 0011 */
	868	{&upd7810_device::XRA_D_A, 2, 8, 8,L0\|L1}, /* 14: 0110 0000 0001 0100 */
	869	{&upd7810_device::XRA_E_A, 2, 8, 8,L0\|L1}, /* 15: 0110 0000 0001 0101 */
	870	{&upd7810_device::XRA_H_A, 2, 8, 8,L0\|L1}, /* 16: 0110 0000 0001 0110 */
	871	{&upd7810_device::XRA_L_A, 2, 8, 8,L0\|L1}, /* 17: 0110 0000 0001 0111 */
	872	{&upd7810_device::ORA_V_A, 2, 8, 8,L0\|L1}, /* 18: 0110 0000 0001 1000 */
	873	{&upd7810_device::ORA_A_A, 2, 8, 8,L0\|L1}, /* 19: 0110 0000 0001 1001 */
	874	{&upd7810_device::ORA_B_A, 2, 8, 8,L0\|L1}, /* 1a: 0110 0000 0001 1010 */
	875	{&upd7810_device::ORA_C_A, 2, 8, 8,L0\|L1}, /* 1b: 0110 0000 0001 1011 */
	876	{&upd7810_device::ORA_D_A, 2, 8, 8,L0\|L1}, /* 1c: 0110 0000 0001 1100 */
	877	{&upd7810_device::ORA_E_A, 2, 8, 8,L0\|L1}, /* 1d: 0110 0000 0001 1101 */
	878	{&upd7810_device::ORA_H_A, 2, 8, 8,L0\|L1}, /* 1e: 0110 0000 0001 1110 */
	879	{&upd7810_device::ORA_L_A, 2, 8, 8,L0\|L1}, /* 1f: 0110 0000 0001 1111 */
	880
	881	{&upd7810_device::ADDNC_V_A, 2, 8, 8,L0\|L1}, /* 20: 0110 0000 0010 0000 */
	882	{&upd7810_device::ADDNC_A_A, 2, 8, 8,L0\|L1}, /* 21: 0110 0000 0010 0001 */
	883	{&upd7810_device::ADDNC_B_A, 2, 8, 8,L0\|L1}, /* 22: 0110 0000 0010 0010 */
	884	{&upd7810_device::ADDNC_C_A, 2, 8, 8,L0\|L1}, /* 23: 0110 0000 0010 0011 */
	885	{&upd7810_device::ADDNC_D_A, 2, 8, 8,L0\|L1}, /* 24: 0110 0000 0010 0100 */
	886	{&upd7810_device::ADDNC_E_A, 2, 8, 8,L0\|L1}, /* 25: 0110 0000 0010 0101 */
	887	{&upd7810_device::ADDNC_H_A, 2, 8, 8,L0\|L1}, /* 26: 0110 0000 0010 0110 */
	888	{&upd7810_device::ADDNC_L_A, 2, 8, 8,L0\|L1}, /* 27: 0110 0000 0010 0111 */
	889	{&upd7810_device::GTA_V_A, 2, 8, 8,L0\|L1}, /* 28: 0110 0000 0010 1000 */
	890	{&upd7810_device::GTA_A_A, 2, 8, 8,L0\|L1}, /* 29: 0110 0000 0010 1001 */
	891	{&upd7810_device::GTA_B_A, 2, 8, 8,L0\|L1}, /* 2a: 0110 0000 0010 1010 */
	892	{&upd7810_device::GTA_C_A, 2, 8, 8,L0\|L1}, /* 2b: 0110 0000 0010 1011 */
	893	{&upd7810_device::GTA_D_A, 2, 8, 8,L0\|L1}, /* 2c: 0110 0000 0010 1100 */
	894	{&upd7810_device::GTA_E_A, 2, 8, 8,L0\|L1}, /* 2d: 0110 0000 0010 1101 */
	895	{&upd7810_device::GTA_H_A, 2, 8, 8,L0\|L1}, /* 2e: 0110 0000 0010 1110 */
	896	{&upd7810_device::GTA_L_A, 2, 8, 8,L0\|L1}, /* 2f: 0110 0000 0010 1111 */
	897
	898	{&upd7810_device::SUBNB_V_A, 2, 8, 8,L0\|L1}, /* 30: 0110 0000 0011 0000 */
	899	{&upd7810_device::SUBNB_A_A, 2, 8, 8,L0\|L1}, /* 31: 0110 0000 0011 0001 */
	900	{&upd7810_device::SUBNB_B_A, 2, 8, 8,L0\|L1}, /* 32: 0110 0000 0011 0010 */
	901	{&upd7810_device::SUBNB_C_A, 2, 8, 8,L0\|L1}, /* 33: 0110 0000 0011 0011 */
	902	{&upd7810_device::SUBNB_D_A, 2, 8, 8,L0\|L1}, /* 34: 0110 0000 0011 0100 */
	903	{&upd7810_device::SUBNB_E_A, 2, 8, 8,L0\|L1}, /* 35: 0110 0000 0011 0101 */
	904	{&upd7810_device::SUBNB_H_A, 2, 8, 8,L0\|L1}, /* 36: 0110 0000 0011 0110 */
	905	{&upd7810_device::SUBNB_L_A, 2, 8, 8,L0\|L1}, /* 37: 0110 0000 0011 0111 */
	906	{&upd7810_device::LTA_V_A, 2, 8, 8,L0\|L1}, /* 38: 0110 0000 0011 1000 */
	907	{&upd7810_device::LTA_A_A, 2, 8, 8,L0\|L1}, /* 39: 0110 0000 0011 1001 */
	908	{&upd7810_device::LTA_B_A, 2, 8, 8,L0\|L1}, /* 3a: 0110 0000 0011 1010 */
	909	{&upd7810_device::LTA_C_A, 2, 8, 8,L0\|L1}, /* 3b: 0110 0000 0011 1011 */
	910	{&upd7810_device::LTA_D_A, 2, 8, 8,L0\|L1}, /* 3c: 0110 0000 0011 1100 */
	911	{&upd7810_device::LTA_E_A, 2, 8, 8,L0\|L1}, /* 3d: 0110 0000 0011 1101 */
	912	{&upd7810_device::LTA_H_A, 2, 8, 8,L0\|L1}, /* 3e: 0110 0000 0011 1110 */
	913	{&upd7810_device::LTA_L_A, 2, 8, 8,L0\|L1}, /* 3f: 0110 0000 0011 1111 */
	914
	915	{&upd7810_device::ADD_V_A, 2, 8, 8,L0\|L1}, /* 40: 0110 0000 0100 0000 */
	916	{&upd7810_device::ADD_A_A, 2, 8, 8,L0\|L1}, /* 41: 0110 0000 0100 0001 */
	917	{&upd7810_device::ADD_B_A, 2, 8, 8,L0\|L1}, /* 42: 0110 0000 0100 0010 */
	918	{&upd7810_device::ADD_C_A, 2, 8, 8,L0\|L1}, /* 43: 0110 0000 0100 0011 */
	919	{&upd7810_device::ADD_D_A, 2, 8, 8,L0\|L1}, /* 44: 0110 0000 0100 0100 */
	920	{&upd7810_device::ADD_E_A, 2, 8, 8,L0\|L1}, /* 45: 0110 0000 0100 0101 */
	921	{&upd7810_device::ADD_H_A, 2, 8, 8,L0\|L1}, /* 46: 0110 0000 0100 0110 */
	922	{&upd7810_device::ADD_L_A, 2, 8, 8,L0\|L1}, /* 47: 0110 0000 0100 0111 */
	923	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 48: 0110 0000 0100 1000 */
	924	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 49: 0110 0000 0100 1001 */
	925	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4a: 0110 0000 0100 1010 */
	926	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4b: 0110 0000 0100 1011 */
	927	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4c: 0110 0000 0100 1100 */
	928	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4d: 0110 0000 0100 1101 */
	929	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4e: 0110 0000 0100 1110 */
	930	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4f: 0110 0000 0100 1111 */
	931
	932	{&upd7810_device::ADC_V_A, 2, 8, 8,L0\|L1}, /* 50: 0110 0000 0101 0000 */
	933	{&upd7810_device::ADC_A_A, 2, 8, 8,L0\|L1}, /* 51: 0110 0000 0101 0001 */
	934	{&upd7810_device::ADC_B_A, 2, 8, 8,L0\|L1}, /* 52: 0110 0000 0101 0010 */
	935	{&upd7810_device::ADC_C_A, 2, 8, 8,L0\|L1}, /* 53: 0110 0000 0101 0011 */
	936	{&upd7810_device::ADC_D_A, 2, 8, 8,L0\|L1}, /* 54: 0110 0000 0101 0100 */
	937	{&upd7810_device::ADC_E_A, 2, 8, 8,L0\|L1}, /* 55: 0110 0000 0101 0101 */
	938	{&upd7810_device::ADC_H_A, 2, 8, 8,L0\|L1}, /* 56: 0110 0000 0101 0110 */
	939	{&upd7810_device::ADC_L_A, 2, 8, 8,L0\|L1}, /* 57: 0110 0000 0101 0111 */
	940	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 58: 0110 0000 0101 1000 */
	941	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 59: 0110 0000 0101 1001 */
	942	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5a: 0110 0000 0101 1010 */
	943	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5b: 0110 0000 0101 1011 */
	944	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5c: 0110 0000 0101 1100 */
	945	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5d: 0110 0000 0101 1101 */
	946	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5e: 0110 0000 0101 1110 */
	947	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5f: 0110 0000 0101 1111 */
	948
	949	{&upd7810_device::SUB_V_A, 2, 8, 8,L0\|L1}, /* 60: 0110 0000 0110 0000 */
	950	{&upd7810_device::SUB_A_A, 2, 8, 8,L0\|L1}, /* 61: 0110 0000 0110 0001 */
	951	{&upd7810_device::SUB_B_A, 2, 8, 8,L0\|L1}, /* 62: 0110 0000 0110 0010 */
	952	{&upd7810_device::SUB_C_A, 2, 8, 8,L0\|L1}, /* 63: 0110 0000 0110 0011 */
	953	{&upd7810_device::SUB_D_A, 2, 8, 8,L0\|L1}, /* 64: 0110 0000 0110 0100 */
	954	{&upd7810_device::SUB_E_A, 2, 8, 8,L0\|L1}, /* 65: 0110 0000 0110 0101 */
	955	{&upd7810_device::SUB_H_A, 2, 8, 8,L0\|L1}, /* 66: 0110 0000 0110 0110 */
	956	{&upd7810_device::SUB_L_A, 2, 8, 8,L0\|L1}, /* 67: 0110 0000 0110 0111 */
	957	{&upd7810_device::NEA_V_A, 2, 8, 8,L0\|L1}, /* 68: 0110 0000 0110 1000 */
	958	{&upd7810_device::NEA_A_A, 2, 8, 8,L0\|L1}, /* 69: 0110 0000 0110 1001 */
	959	{&upd7810_device::NEA_B_A, 2, 8, 8,L0\|L1}, /* 6a: 0110 0000 0110 1010 */
	960	{&upd7810_device::NEA_C_A, 2, 8, 8,L0\|L1}, /* 6b: 0110 0000 0110 1011 */
	961	{&upd7810_device::NEA_D_A, 2, 8, 8,L0\|L1}, /* 6c: 0110 0000 0110 1100 */
	962	{&upd7810_device::NEA_E_A, 2, 8, 8,L0\|L1}, /* 6d: 0110 0000 0110 1101 */
	963	{&upd7810_device::NEA_H_A, 2, 8, 8,L0\|L1}, /* 6e: 0110 0000 0110 1110 */
	964	{&upd7810_device::NEA_L_A, 2, 8, 8,L0\|L1}, /* 6f: 0110 0000 0110 1111 */
	965
	966	{&upd7810_device::SBB_V_A, 2, 8, 8,L0\|L1}, /* 70: 0110 0000 0111 0000 */
	967	{&upd7810_device::SBB_A_A, 2, 8, 8,L0\|L1}, /* 71: 0110 0000 0111 0001 */
	968	{&upd7810_device::SBB_B_A, 2, 8, 8,L0\|L1}, /* 72: 0110 0000 0111 0010 */
	969	{&upd7810_device::SBB_C_A, 2, 8, 8,L0\|L1}, /* 73: 0110 0000 0111 0011 */
	970	{&upd7810_device::SBB_D_A, 2, 8, 8,L0\|L1}, /* 74: 0110 0000 0111 0100 */
	971	{&upd7810_device::SBB_E_A, 2, 8, 8,L0\|L1}, /* 75: 0110 0000 0111 0101 */
	972	{&upd7810_device::SBB_H_A, 2, 8, 8,L0\|L1}, /* 76: 0110 0000 0111 0110 */
	973	{&upd7810_device::SBB_L_A, 2, 8, 8,L0\|L1}, /* 77: 0110 0000 0111 0111 */
	974	{&upd7810_device::EQA_V_A, 2, 8, 8,L0\|L1}, /* 78: 0110 0000 0111 1000 */
	975	{&upd7810_device::EQA_A_A, 2, 8, 8,L0\|L1}, /* 79: 0110 0000 0111 1001 */
	976	{&upd7810_device::EQA_B_A, 2, 8, 8,L0\|L1}, /* 7a: 0110 0000 0111 1010 */
	977	{&upd7810_device::EQA_C_A, 2, 8, 8,L0\|L1}, /* 7b: 0110 0000 0111 1011 */
	978	{&upd7810_device::EQA_D_A, 2, 8, 8,L0\|L1}, /* 7c: 0110 0000 0111 1100 */
	979	{&upd7810_device::EQA_E_A, 2, 8, 8,L0\|L1}, /* 7d: 0110 0000 0111 1101 */
	980	{&upd7810_device::EQA_H_A, 2, 8, 8,L0\|L1}, /* 7e: 0110 0000 0111 1110 */
	981	{&upd7810_device::EQA_L_A, 2, 8, 8,L0\|L1}, /* 7f: 0110 0000 0111 1111 */
	982
	983	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 80: 0110 0000 1000 0000 */
	984	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 81: 0110 0000 1000 0001 */
	985	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 82: 0110 0000 1000 0010 */
	986	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 83: 0110 0000 1000 0011 */
	987	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 84: 0110 0000 1000 0100 */
	988	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 85: 0110 0000 1000 0101 */
	989	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 86: 0110 0000 1000 0110 */
	990	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 87: 0110 0000 1000 0111 */
	991	{&upd7810_device::ANA_A_V, 2, 8, 8,L0\|L1}, /* 88: 0110 0000 1000 1000 */
	992	{&upd7810_device::ANA_A_A, 2, 8, 8,L0\|L1}, /* 89: 0110 0000 1000 1001 */
	993	{&upd7810_device::ANA_A_B, 2, 8, 8,L0\|L1}, /* 8a: 0110 0000 1000 1010 */
	994	{&upd7810_device::ANA_A_C, 2, 8, 8,L0\|L1}, /* 8b: 0110 0000 1000 1011 */
	995	{&upd7810_device::ANA_A_D, 2, 8, 8,L0\|L1}, /* 8c: 0110 0000 1000 1100 */
	996	{&upd7810_device::ANA_A_E, 2, 8, 8,L0\|L1}, /* 8d: 0110 0000 1000 1101 */
	997	{&upd7810_device::ANA_A_H, 2, 8, 8,L0\|L1}, /* 8e: 0110 0000 1000 1110 */
	998	{&upd7810_device::ANA_A_L, 2, 8, 8,L0\|L1}, /* 8f: 0110 0000 1000 1111 */
	999
	1000	{&upd7810_device::XRA_A_V, 2, 8, 8,L0\|L1}, /* 90: 0110 0000 1001 0000 */
	1001	{&upd7810_device::XRA_A_A, 2, 8, 8,L0\|L1}, /* 91: 0110 0000 1001 0001 */
	1002	{&upd7810_device::XRA_A_B, 2, 8, 8,L0\|L1}, /* 92: 0110 0000 1001 0010 */
	1003	{&upd7810_device::XRA_A_C, 2, 8, 8,L0\|L1}, /* 93: 0110 0000 1001 0011 */
	1004	{&upd7810_device::XRA_A_D, 2, 8, 8,L0\|L1}, /* 94: 0110 0000 1001 0100 */
	1005	{&upd7810_device::XRA_A_E, 2, 8, 8,L0\|L1}, /* 95: 0110 0000 1001 0101 */
	1006	{&upd7810_device::XRA_A_H, 2, 8, 8,L0\|L1}, /* 96: 0110 0000 1001 0110 */
	1007	{&upd7810_device::XRA_A_L, 2, 8, 8,L0\|L1}, /* 97: 0110 0000 1001 0111 */
	1008	{&upd7810_device::ORA_A_V, 2, 8, 8,L0\|L1}, /* 98: 0110 0000 1001 1000 */
	1009	{&upd7810_device::ORA_A_A, 2, 8, 8,L0\|L1}, /* 99: 0110 0000 1001 1001 */
	1010	{&upd7810_device::ORA_A_B, 2, 8, 8,L0\|L1}, /* 9a: 0110 0000 1001 1010 */
	1011	{&upd7810_device::ORA_A_C, 2, 8, 8,L0\|L1}, /* 9b: 0110 0000 1001 1011 */
	1012	{&upd7810_device::ORA_A_D, 2, 8, 8,L0\|L1}, /* 9c: 0110 0000 1001 1100 */
	1013	{&upd7810_device::ORA_A_E, 2, 8, 8,L0\|L1}, /* 9d: 0110 0000 1001 1101 */
	1014	{&upd7810_device::ORA_A_H, 2, 8, 8,L0\|L1}, /* 9e: 0110 0000 1001 1110 */
	1015	{&upd7810_device::ORA_A_L, 2, 8, 8,L0\|L1}, /* 9f: 0110 0000 1001 1111 */
	1016
	1017	{&upd7810_device::ADDNC_A_V, 2, 8, 8,L0\|L1}, /* a0: 0110 0000 1010 0000 */
	1018	{&upd7810_device::ADDNC_A_A, 2, 8, 8,L0\|L1}, /* a1: 0110 0000 1010 0001 */
	1019	{&upd7810_device::ADDNC_A_B, 2, 8, 8,L0\|L1}, /* a2: 0110 0000 1010 0010 */
	1020	{&upd7810_device::ADDNC_A_C, 2, 8, 8,L0\|L1}, /* a3: 0110 0000 1010 0011 */
	1021	{&upd7810_device::ADDNC_A_D, 2, 8, 8,L0\|L1}, /* a4: 0110 0000 1010 0100 */
	1022	{&upd7810_device::ADDNC_A_E, 2, 8, 8,L0\|L1}, /* a5: 0110 0000 1010 0101 */
	1023	{&upd7810_device::ADDNC_A_H, 2, 8, 8,L0\|L1}, /* a6: 0110 0000 1010 0110 */
	1024	{&upd7810_device::ADDNC_A_L, 2, 8, 8,L0\|L1}, /* a7: 0110 0000 1010 0111 */
	1025	{&upd7810_device::GTA_A_V, 2, 8, 8,L0\|L1}, /* a8: 0110 0000 1010 1000 */
	1026	{&upd7810_device::GTA_A_A, 2, 8, 8,L0\|L1}, /* a9: 0110 0000 1010 1001 */
	1027	{&upd7810_device::GTA_A_B, 2, 8, 8,L0\|L1}, /* aa: 0110 0000 1010 1010 */
	1028	{&upd7810_device::GTA_A_C, 2, 8, 8,L0\|L1}, /* ab: 0110 0000 1010 1011 */
	1029	{&upd7810_device::GTA_A_D, 2, 8, 8,L0\|L1}, /* ac: 0110 0000 1010 1100 */
	1030	{&upd7810_device::GTA_A_E, 2, 8, 8,L0\|L1}, /* ad: 0110 0000 1010 1101 */
	1031	{&upd7810_device::GTA_A_H, 2, 8, 8,L0\|L1}, /* ae: 0110 0000 1010 1110 */
	1032	{&upd7810_device::GTA_A_L, 2, 8, 8,L0\|L1}, /* af: 0110 0000 1010 1111 */
	1033
	1034	{&upd7810_device::SUBNB_A_V, 2, 8, 8,L0\|L1}, /* b0: 0110 0000 1011 0000 */
	1035	{&upd7810_device::SUBNB_A_A, 2, 8, 8,L0\|L1}, /* b1: 0110 0000 1011 0001 */
	1036	{&upd7810_device::SUBNB_A_B, 2, 8, 8,L0\|L1}, /* b2: 0110 0000 1011 0010 */
	1037	{&upd7810_device::SUBNB_A_C, 2, 8, 8,L0\|L1}, /* b3: 0110 0000 1011 0011 */
	1038	{&upd7810_device::SUBNB_A_D, 2, 8, 8,L0\|L1}, /* b4: 0110 0000 1011 0100 */
	1039	{&upd7810_device::SUBNB_A_E, 2, 8, 8,L0\|L1}, /* b5: 0110 0000 1011 0101 */
	1040	{&upd7810_device::SUBNB_A_H, 2, 8, 8,L0\|L1}, /* b6: 0110 0000 1011 0110 */
	1041	{&upd7810_device::SUBNB_A_L, 2, 8, 8,L0\|L1}, /* b7: 0110 0000 1011 0111 */
	1042	{&upd7810_device::LTA_A_V, 2, 8, 8,L0\|L1}, /* b8: 0110 0000 1011 1000 */
	1043	{&upd7810_device::LTA_A_A, 2, 8, 8,L0\|L1}, /* b9: 0110 0000 1011 1001 */
	1044	{&upd7810_device::LTA_A_B, 2, 8, 8,L0\|L1}, /* ba: 0110 0000 1011 1010 */
	1045	{&upd7810_device::LTA_A_C, 2, 8, 8,L0\|L1}, /* bb: 0110 0000 1011 1011 */
	1046	{&upd7810_device::LTA_A_D, 2, 8, 8,L0\|L1}, /* bc: 0110 0000 1011 1100 */
	1047	{&upd7810_device::LTA_A_E, 2, 8, 8,L0\|L1}, /* bd: 0110 0000 1011 1101 */
	1048	{&upd7810_device::LTA_A_H, 2, 8, 8,L0\|L1}, /* be: 0110 0000 1011 1110 */
	1049	{&upd7810_device::LTA_A_L, 2, 8, 8,L0\|L1}, /* bf: 0110 0000 1011 1111 */
	1050
	1051	{&upd7810_device::ADD_A_V, 2, 8, 8,L0\|L1}, /* c0: 0110 0000 1100 0000 */
	1052	{&upd7810_device::ADD_A_A, 2, 8, 8,L0\|L1}, /* c1: 0110 0000 1100 0001 */
	1053	{&upd7810_device::ADD_A_B, 2, 8, 8,L0\|L1}, /* c2: 0110 0000 1100 0010 */
	1054	{&upd7810_device::ADD_A_C, 2, 8, 8,L0\|L1}, /* c3: 0110 0000 1100 0011 */
	1055	{&upd7810_device::ADD_A_D, 2, 8, 8,L0\|L1}, /* c4: 0110 0000 1100 0100 */
	1056	{&upd7810_device::ADD_A_E, 2, 8, 8,L0\|L1}, /* c5: 0110 0000 1100 0101 */
	1057	{&upd7810_device::ADD_A_H, 2, 8, 8,L0\|L1}, /* c6: 0110 0000 1100 0110 */
	1058	{&upd7810_device::ADD_A_L, 2, 8, 8,L0\|L1}, /* c7: 0110 0000 1100 0111 */
	1059	{&upd7810_device::ONA_A_V, 2, 8, 8,L0\|L1}, /* c8: 0110 0000 1100 1000 */
	1060	{&upd7810_device::ONA_A_A, 2, 8, 8,L0\|L1}, /* c9: 0110 0000 1100 1001 */
	1061	{&upd7810_device::ONA_A_B, 2, 8, 8,L0\|L1}, /* ca: 0110 0000 1100 1010 */
	1062	{&upd7810_device::ONA_A_C, 2, 8, 8,L0\|L1}, /* cb: 0110 0000 1100 1011 */
	1063	{&upd7810_device::ONA_A_D, 2, 8, 8,L0\|L1}, /* cc: 0110 0000 1100 1100 */
	1064	{&upd7810_device::ONA_A_E, 2, 8, 8,L0\|L1}, /* cd: 0110 0000 1100 1101 */
	1065	{&upd7810_device::ONA_A_H, 2, 8, 8,L0\|L1}, /* ce: 0110 0000 1100 1110 */
	1066	{&upd7810_device::ONA_A_L, 2, 8, 8,L0\|L1}, /* cf: 0110 0000 1100 1111 */
	1067
	1068	{&upd7810_device::ADC_A_V, 2, 8, 8,L0\|L1}, /* d0: 0110 0000 1101 0000 */
	1069	{&upd7810_device::ADC_A_A, 2, 8, 8,L0\|L1}, /* d1: 0110 0000 1101 0001 */
	1070	{&upd7810_device::ADC_A_B, 2, 8, 8,L0\|L1}, /* d2: 0110 0000 1101 0010 */
	1071	{&upd7810_device::ADC_A_C, 2, 8, 8,L0\|L1}, /* d3: 0110 0000 1101 0011 */
	1072	{&upd7810_device::ADC_A_D, 2, 8, 8,L0\|L1}, /* d4: 0110 0000 1101 0100 */
	1073	{&upd7810_device::ADC_A_E, 2, 8, 8,L0\|L1}, /* d5: 0110 0000 1101 0101 */
	1074	{&upd7810_device::ADC_A_H, 2, 8, 8,L0\|L1}, /* d6: 0110 0000 1101 0110 */
	1075	{&upd7810_device::ADC_A_L, 2, 8, 8,L0\|L1}, /* d7: 0110 0000 1101 0111 */
	1076	{&upd7810_device::OFFA_A_V, 2, 8, 8,L0\|L1}, /* d8: 0110 0000 1101 1000 */
	1077	{&upd7810_device::OFFA_A_A, 2, 8, 8,L0\|L1}, /* d9: 0110 0000 1101 1001 */
	1078	{&upd7810_device::OFFA_A_B, 2, 8, 8,L0\|L1}, /* da: 0110 0000 1101 1010 */
	1079	{&upd7810_device::OFFA_A_C, 2, 8, 8,L0\|L1}, /* db: 0110 0000 1101 1011 */
	1080	{&upd7810_device::OFFA_A_D, 2, 8, 8,L0\|L1}, /* dc: 0110 0000 1101 1100 */
	1081	{&upd7810_device::OFFA_A_E, 2, 8, 8,L0\|L1}, /* dd: 0110 0000 1101 1101 */
	1082	{&upd7810_device::OFFA_A_H, 2, 8, 8,L0\|L1}, /* de: 0110 0000 1101 1110 */
	1083	{&upd7810_device::OFFA_A_L, 2, 8, 8,L0\|L1}, /* df: 0110 0000 1101 1111 */
	1084
	1085	{&upd7810_device::SUB_A_V, 2, 8, 8,L0\|L1}, /* e0: 0110 0000 1110 0000 */
	1086	{&upd7810_device::SUB_A_A, 2, 8, 8,L0\|L1}, /* e1: 0110 0000 1110 0001 */
	1087	{&upd7810_device::SUB_A_B, 2, 8, 8,L0\|L1}, /* e2: 0110 0000 1110 0010 */
	1088	{&upd7810_device::SUB_A_C, 2, 8, 8,L0\|L1}, /* e3: 0110 0000 1110 0011 */
	1089	{&upd7810_device::SUB_A_D, 2, 8, 8,L0\|L1}, /* e4: 0110 0000 1110 0100 */
	1090	{&upd7810_device::SUB_A_E, 2, 8, 8,L0\|L1}, /* e5: 0110 0000 1110 0101 */
	1091	{&upd7810_device::SUB_A_H, 2, 8, 8,L0\|L1}, /* e6: 0110 0000 1110 0110 */
	1092	{&upd7810_device::SUB_A_L, 2, 8, 8,L0\|L1}, /* e7: 0110 0000 1110 0111 */
	1093	{&upd7810_device::NEA_A_V, 2, 8, 8,L0\|L1}, /* e8: 0110 0000 1110 1000 */
	1094	{&upd7810_device::NEA_A_A, 2, 8, 8,L0\|L1}, /* e9: 0110 0000 1110 1001 */
	1095	{&upd7810_device::NEA_A_B, 2, 8, 8,L0\|L1}, /* ea: 0110 0000 1110 1010 */
	1096	{&upd7810_device::NEA_A_C, 2, 8, 8,L0\|L1}, /* eb: 0110 0000 1110 1011 */
	1097	{&upd7810_device::NEA_A_D, 2, 8, 8,L0\|L1}, /* ec: 0110 0000 1110 1100 */
	1098	{&upd7810_device::NEA_A_E, 2, 8, 8,L0\|L1}, /* ed: 0110 0000 1110 1101 */
	1099	{&upd7810_device::NEA_A_H, 2, 8, 8,L0\|L1}, /* ee: 0110 0000 1110 1110 */
	1100	{&upd7810_device::NEA_A_L, 2, 8, 8,L0\|L1}, /* ef: 0110 0000 1110 1111 */
	1101
	1102	{&upd7810_device::SBB_A_V, 2, 8, 8,L0\|L1}, /* f0: 0110 0000 1111 0000 */
	1103	{&upd7810_device::SBB_A_A, 2, 8, 8,L0\|L1}, /* f1: 0110 0000 1111 0001 */
	1104	{&upd7810_device::SBB_A_B, 2, 8, 8,L0\|L1}, /* f2: 0110 0000 1111 0010 */
	1105	{&upd7810_device::SBB_A_C, 2, 8, 8,L0\|L1}, /* f3: 0110 0000 1111 0011 */
	1106	{&upd7810_device::SBB_A_D, 2, 8, 8,L0\|L1}, /* f4: 0110 0000 1111 0100 */
	1107	{&upd7810_device::SBB_A_E, 2, 8, 8,L0\|L1}, /* f5: 0110 0000 1111 0101 */
	1108	{&upd7810_device::SBB_A_H, 2, 8, 8,L0\|L1}, /* f6: 0110 0000 1111 0110 */
	1109	{&upd7810_device::SBB_A_L, 2, 8, 8,L0\|L1}, /* f7: 0110 0000 1111 0111 */
	1110	{&upd7810_device::EQA_A_V, 2, 8, 8,L0\|L1}, /* f8: 0110 0000 1111 1000 */
	1111	{&upd7810_device::EQA_A_A, 2, 8, 8,L0\|L1}, /* f9: 0110 0000 1111 1001 */
	1112	{&upd7810_device::EQA_A_B, 2, 8, 8,L0\|L1}, /* fa: 0110 0000 1111 1010 */
	1113	{&upd7810_device::EQA_A_C, 2, 8, 8,L0\|L1}, /* fb: 0110 0000 1111 1011 */
	1114	{&upd7810_device::EQA_A_D, 2, 8, 8,L0\|L1}, /* fc: 0110 0000 1111 1100 */
	1115	{&upd7810_device::EQA_A_E, 2, 8, 8,L0\|L1}, /* fd: 0110 0000 1111 1101 */
	1116	{&upd7810_device::EQA_A_H, 2, 8, 8,L0\|L1}, /* fe: 0110 0000 1111 1110 */
	1117	{&upd7810_device::EQA_A_L, 2, 8, 8,L0\|L1} /* ff: 0110 0000 1111 1111 */
	1118	};
	1119
	1120	/* prefix 64 */
	1121	const struct upd7810_device::opcode_s upd7810_device::s_op64[256] =
	1122	{
	1123	{&upd7810_device::MVI_PA_xx, 3,14,11,L0\|L1}, /* 00: 0110 0100 0000 0000 xxxx xxxx */
	1124	{&upd7810_device::MVI_PB_xx, 3,14,11,L0\|L1}, /* 01: 0110 0100 0000 0001 xxxx xxxx */
	1125	{&upd7810_device::MVI_PC_xx, 3,14,11,L0\|L1}, /* 02: 0110 0100 0000 0010 xxxx xxxx */
	1126	{&upd7810_device::MVI_PD_xx, 3,14,11,L0\|L1}, /* 03: 0110 0100 0000 0011 xxxx xxxx */
	1127	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 04: 0110 0100 0000 0100 xxxx xxxx */
	1128	{&upd7810_device::MVI_PF_xx, 3,14,11,L0\|L1}, /* 05: 0110 0100 0000 0101 xxxx xxxx */
	1129	{&upd7810_device::MVI_MKH_xx, 3,14,11,L0\|L1}, /* 06: 0110 0100 0000 0110 xxxx xxxx */
	1130	{&upd7810_device::MVI_MKL_xx, 3,14,11,L0\|L1}, /* 07: 0110 0100 0000 0111 xxxx xxxx */
	1131	{&upd7810_device::ANI_PA_xx, 3,20,11,L0\|L1}, /* 08: 0110 0100 0000 1000 xxxx xxxx */
	1132	{&upd7810_device::ANI_PB_xx, 3,20,11,L0\|L1}, /* 09: 0110 0100 0000 1001 xxxx xxxx */
	1133	{&upd7810_device::ANI_PC_xx, 3,20,11,L0\|L1}, /* 0a: 0110 0100 0000 1010 xxxx xxxx */
	1134	{&upd7810_device::ANI_PD_xx, 3,20,11,L0\|L1}, /* 0b: 0110 0100 0000 1011 xxxx xxxx */
	1135	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 0c: 0110 0100 0000 1100 xxxx xxxx */
	1136	{&upd7810_device::ANI_PF_xx, 3,20,11,L0\|L1}, /* 0d: 0110 0100 0000 1101 xxxx xxxx */
	1137	{&upd7810_device::ANI_MKH_xx, 3,20,11,L0\|L1}, /* 0e: 0110 0100 0000 1110 xxxx xxxx */
	1138	{&upd7810_device::ANI_MKL_xx, 3,20,11,L0\|L1}, /* 0f: 0110 0100 0000 1111 xxxx xxxx */
	1139
	1140	{&upd7810_device::XRI_PA_xx, 3,20,11,L0\|L1}, /* 10: 0110 0100 0001 0000 xxxx xxxx */
	1141	{&upd7810_device::XRI_PB_xx, 3,20,11,L0\|L1}, /* 11: 0110 0100 0001 0001 xxxx xxxx */
	1142	{&upd7810_device::XRI_PC_xx, 3,20,11,L0\|L1}, /* 12: 0110 0100 0001 0010 xxxx xxxx */
	1143	{&upd7810_device::XRI_PD_xx, 3,20,11,L0\|L1}, /* 13: 0110 0100 0001 0011 xxxx xxxx */
	1144	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 14: 0110 0100 0001 0100 xxxx xxxx */
	1145	{&upd7810_device::XRI_PF_xx, 3,20,11,L0\|L1}, /* 15: 0110 0100 0001 0101 xxxx xxxx */
	1146	{&upd7810_device::XRI_MKH_xx, 3,20,11,L0\|L1}, /* 16: 0110 0100 0001 0110 xxxx xxxx */
	1147	{&upd7810_device::XRI_MKL_xx, 3,20,11,L0\|L1}, /* 17: 0110 0100 0001 0111 xxxx xxxx */
	1148	{&upd7810_device::ORI_PA_xx, 3,20,11,L0\|L1}, /* 18: 0110 0100 0001 1000 xxxx xxxx */
	1149	{&upd7810_device::ORI_PB_xx, 3,20,11,L0\|L1}, /* 19: 0110 0100 0001 1001 xxxx xxxx */
	1150	{&upd7810_device::ORI_PC_xx, 3,20,11,L0\|L1}, /* 1a: 0110 0100 0001 1010 xxxx xxxx */
	1151	{&upd7810_device::ORI_PD_xx, 3,20,11,L0\|L1}, /* 1b: 0110 0100 0001 1011 xxxx xxxx */
	1152	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 1c: 0110 0100 0001 1100 xxxx xxxx */
	1153	{&upd7810_device::ORI_PF_xx, 3,20,11,L0\|L1}, /* 1d: 0110 0100 0001 1101 xxxx xxxx */
	1154	{&upd7810_device::ORI_MKH_xx, 3,20,11,L0\|L1}, /* 1e: 0110 0100 0001 1110 xxxx xxxx */
	1155	{&upd7810_device::ORI_MKL_xx, 3,20,11,L0\|L1}, /* 1f: 0110 0100 0001 1111 xxxx xxxx */
	1156
	1157	{&upd7810_device::ADINC_PA_xx, 3,20,11,L0\|L1}, /* 20: 0110 0100 0010 0000 xxxx xxxx */
	1158	{&upd7810_device::ADINC_PB_xx, 3,20,11,L0\|L1}, /* 21: 0110 0100 0010 0001 xxxx xxxx */
	1159	{&upd7810_device::ADINC_PC_xx, 3,20,11,L0\|L1}, /* 22: 0110 0100 0010 0010 xxxx xxxx */
	1160	{&upd7810_device::ADINC_PD_xx, 3,20,11,L0\|L1}, /* 23: 0110 0100 0010 0011 xxxx xxxx */
	1161	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 24: 0110 0100 0010 0100 xxxx xxxx */
	1162	{&upd7810_device::ADINC_PF_xx, 3,20,11,L0\|L1}, /* 25: 0110 0100 0010 0101 xxxx xxxx */
	1163	{&upd7810_device::ADINC_MKH_xx, 3,20,11,L0\|L1}, /* 26: 0110 0100 0010 0110 xxxx xxxx */
	1164	{&upd7810_device::ADINC_MKL_xx, 3,20,11,L0\|L1}, /* 27: 0110 0100 0010 0111 xxxx xxxx */
	1165	{&upd7810_device::GTI_PA_xx, 3,20,11,L0\|L1}, /* 28: 0110 0100 0010 1000 xxxx xxxx */
	1166	{&upd7810_device::GTI_PB_xx, 3,20,11,L0\|L1}, /* 29: 0110 0100 0010 1001 xxxx xxxx */
	1167	{&upd7810_device::GTI_PC_xx, 3,20,11,L0\|L1}, /* 2a: 0110 0100 0010 1010 xxxx xxxx */
	1168	{&upd7810_device::GTI_PD_xx, 3,20,11,L0\|L1}, /* 2b: 0110 0100 0010 1011 xxxx xxxx */
	1169	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 2c: 0110 0100 0010 1100 xxxx xxxx */
	1170	{&upd7810_device::GTI_PF_xx, 3,20,11,L0\|L1}, /* 2d: 0110 0100 0010 1101 xxxx xxxx */
	1171	{&upd7810_device::GTI_MKH_xx, 3,20,11,L0\|L1}, /* 2e: 0110 0100 0010 1110 xxxx xxxx */
	1172	{&upd7810_device::GTI_MKL_xx, 3,20,11,L0\|L1}, /* 2f: 0110 0100 0010 1111 xxxx xxxx */
	1173
	1174	{&upd7810_device::SUINB_PA_xx, 3,20,11,L0\|L1}, /* 30: 0110 0100 0011 0000 xxxx xxxx */
	1175	{&upd7810_device::SUINB_PB_xx, 3,20,11,L0\|L1}, /* 31: 0110 0100 0011 0001 xxxx xxxx */
	1176	{&upd7810_device::SUINB_PC_xx, 3,20,11,L0\|L1}, /* 32: 0110 0100 0011 0010 xxxx xxxx */
	1177	{&upd7810_device::SUINB_PD_xx, 3,20,11,L0\|L1}, /* 33: 0110 0100 0011 0011 xxxx xxxx */
	1178	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 34: 0110 0100 0011 0100 xxxx xxxx */
	1179	{&upd7810_device::SUINB_PF_xx, 3,20,11,L0\|L1}, /* 35: 0110 0100 0011 0101 xxxx xxxx */
	1180	{&upd7810_device::SUINB_MKH_xx, 3,20,11,L0\|L1}, /* 36: 0110 0100 0011 0110 xxxx xxxx */
	1181	{&upd7810_device::SUINB_MKL_xx, 3,20,11,L0\|L1}, /* 37: 0110 0100 0011 0111 xxxx xxxx */
	1182	{&upd7810_device::LTI_PA_xx, 3,20,11,L0\|L1}, /* 38: 0110 0100 0011 1000 xxxx xxxx */
	1183	{&upd7810_device::LTI_PB_xx, 3,20,11,L0\|L1}, /* 39: 0110 0100 0011 1001 xxxx xxxx */
	1184	{&upd7810_device::LTI_PC_xx, 3,20,11,L0\|L1}, /* 3a: 0110 0100 0011 1010 xxxx xxxx */
	1185	{&upd7810_device::LTI_PD_xx, 3,20,11,L0\|L1}, /* 3b: 0110 0100 0011 1011 xxxx xxxx */
	1186	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 3c: 0110 0100 0011 1100 xxxx xxxx */
	1187	{&upd7810_device::LTI_PF_xx, 3,20,11,L0\|L1}, /* 3d: 0110 0100 0011 1101 xxxx xxxx */
	1188	{&upd7810_device::LTI_MKH_xx, 3,20,11,L0\|L1}, /* 3e: 0110 0100 0011 1110 xxxx xxxx */
	1189	{&upd7810_device::LTI_MKL_xx, 3,20,11,L0\|L1}, /* 3f: 0110 0100 0011 1111 xxxx xxxx */
	1190
	1191	{&upd7810_device::ADI_PA_xx, 3,20,11,L0\|L1}, /* 40: 0110 0100 0100 0000 xxxx xxxx */
	1192	{&upd7810_device::ADI_PB_xx, 3,20,11,L0\|L1}, /* 41: 0110 0100 0100 0001 xxxx xxxx */
	1193	{&upd7810_device::ADI_PC_xx, 3,20,11,L0\|L1}, /* 42: 0110 0100 0100 0010 xxxx xxxx */
	1194	{&upd7810_device::ADI_PD_xx, 3,20,11,L0\|L1}, /* 43: 0110 0100 0100 0011 xxxx xxxx */
	1195	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 44: 0110 0100 0100 0100 xxxx xxxx */
	1196	{&upd7810_device::ADI_PF_xx, 3,20,11,L0\|L1}, /* 45: 0110 0100 0100 0101 xxxx xxxx */
	1197	{&upd7810_device::ADI_MKH_xx, 3,20,11,L0\|L1}, /* 46: 0110 0100 0100 0110 xxxx xxxx */
	1198	{&upd7810_device::ADI_MKL_xx, 3,20,11,L0\|L1}, /* 47: 0110 0100 0100 0111 xxxx xxxx */
	1199	{&upd7810_device::ONI_PA_xx, 3,20,11,L0\|L1}, /* 48: 0110 0100 0100 1000 xxxx xxxx */
	1200	{&upd7810_device::ONI_PB_xx, 3,20,11,L0\|L1}, /* 49: 0110 0100 0100 1001 xxxx xxxx */
	1201	{&upd7810_device::ONI_PC_xx, 3,20,11,L0\|L1}, /* 4a: 0110 0100 0100 1010 xxxx xxxx */
	1202	{&upd7810_device::ONI_PD_xx, 3,20,11,L0\|L1}, /* 4b: 0110 0100 0100 1011 xxxx xxxx */
	1203	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 4c: 0110 0100 0100 1100 xxxx xxxx */
	1204	{&upd7810_device::ONI_PF_xx, 3,20,11,L0\|L1}, /* 4d: 0110 0100 0100 1101 xxxx xxxx */
	1205	{&upd7810_device::ONI_MKH_xx, 3,20,11,L0\|L1}, /* 4e: 0110 0100 0100 1110 xxxx xxxx */
	1206	{&upd7810_device::ONI_MKL_xx, 3,20,11,L0\|L1}, /* 4f: 0110 0100 0100 1111 xxxx xxxx */
	1207
	1208	{&upd7810_device::ACI_PA_xx, 3,20,11,L0\|L1}, /* 50: 0110 0100 0101 0000 xxxx xxxx */
	1209	{&upd7810_device::ACI_PB_xx, 3,20,11,L0\|L1}, /* 51: 0110 0100 0101 0001 xxxx xxxx */
	1210	{&upd7810_device::ACI_PC_xx, 3,20,11,L0\|L1}, /* 52: 0110 0100 0101 0010 xxxx xxxx */
	1211	{&upd7810_device::ACI_PD_xx, 3,20,11,L0\|L1}, /* 53: 0110 0100 0101 0011 xxxx xxxx */
	1212	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 54: 0110 0100 0101 0100 xxxx xxxx */
	1213	{&upd7810_device::ACI_PF_xx, 3,20,11,L0\|L1}, /* 55: 0110 0100 0101 0101 xxxx xxxx */
	1214	{&upd7810_device::ACI_MKH_xx, 3,20,11,L0\|L1}, /* 56: 0110 0100 0101 0110 xxxx xxxx */
	1215	{&upd7810_device::ACI_MKL_xx, 3,20,11,L0\|L1}, /* 57: 0110 0100 0101 0111 xxxx xxxx */
	1216	{&upd7810_device::OFFI_PA_xx, 3,20,11,L0\|L1}, /* 58: 0110 0100 0101 1000 xxxx xxxx */
	1217	{&upd7810_device::OFFI_PB_xx, 3,20,11,L0\|L1}, /* 59: 0110 0100 0101 1001 xxxx xxxx */
	1218	{&upd7810_device::OFFI_PC_xx, 3,20,11,L0\|L1}, /* 5a: 0110 0100 0101 1010 xxxx xxxx */
	1219	{&upd7810_device::OFFI_PD_xx, 3,20,11,L0\|L1}, /* 5b: 0110 0100 0101 1011 xxxx xxxx */
	1220	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 5c: 0110 0100 0101 1100 xxxx xxxx */
	1221	{&upd7810_device::OFFI_PF_xx, 3,20,11,L0\|L1}, /* 5d: 0110 0100 0101 1101 xxxx xxxx */
	1222	{&upd7810_device::OFFI_MKH_xx, 3,20,11,L0\|L1}, /* 5e: 0110 0100 0101 1110 xxxx xxxx */
	1223	{&upd7810_device::OFFI_MKL_xx, 3,20,11,L0\|L1}, /* 5f: 0110 0100 0101 1111 xxxx xxxx */
	1224
	1225	{&upd7810_device::SUI_PA_xx, 3,20,11,L0\|L1}, /* 60: 0110 0100 0110 0000 xxxx xxxx */
	1226	{&upd7810_device::SUI_PB_xx, 3,20,11,L0\|L1}, /* 61: 0110 0100 0110 0001 xxxx xxxx */
	1227	{&upd7810_device::SUI_PC_xx, 3,20,11,L0\|L1}, /* 62: 0110 0100 0110 0010 xxxx xxxx */
	1228	{&upd7810_device::SUI_PD_xx, 3,20,11,L0\|L1}, /* 63: 0110 0100 0110 0011 xxxx xxxx */
	1229	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 64: 0110 0100 0110 0100 xxxx xxxx */
	1230	{&upd7810_device::SUI_PF_xx, 3,20,11,L0\|L1}, /* 65: 0110 0100 0110 0101 xxxx xxxx */
	1231	{&upd7810_device::SUI_MKH_xx, 3,20,11,L0\|L1}, /* 66: 0110 0100 0110 0110 xxxx xxxx */
	1232	{&upd7810_device::SUI_MKL_xx, 3,20,11,L0\|L1}, /* 67: 0110 0100 0110 0111 xxxx xxxx */
	1233	{&upd7810_device::NEI_PA_xx, 3,20,11,L0\|L1}, /* 68: 0110 0100 0110 1000 xxxx xxxx */
	1234	{&upd7810_device::NEI_PB_xx, 3,20,11,L0\|L1}, /* 69: 0110 0100 0110 1001 xxxx xxxx */
	1235	{&upd7810_device::NEI_PC_xx, 3,20,11,L0\|L1}, /* 6a: 0110 0100 0110 1010 xxxx xxxx */
	1236	{&upd7810_device::NEI_PD_xx, 3,20,11,L0\|L1}, /* 6b: 0110 0100 0110 1011 xxxx xxxx */
	1237	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 6c: 0110 0100 0110 1100 xxxx xxxx */
	1238	{&upd7810_device::NEI_PF_xx, 3,20,11,L0\|L1}, /* 6d: 0110 0100 0110 1101 xxxx xxxx */
	1239	{&upd7810_device::NEI_MKH_xx, 3,20,11,L0\|L1}, /* 6e: 0110 0100 0110 1110 xxxx xxxx */
	1240	{&upd7810_device::NEI_MKL_xx, 3,20,11,L0\|L1}, /* 6f: 0110 0100 0110 1111 xxxx xxxx */
	1241
	1242	{&upd7810_device::SBI_PA_xx, 3,20,11,L0\|L1}, /* 70: 0110 0100 0111 0000 xxxx xxxx */
	1243	{&upd7810_device::SBI_PB_xx, 3,20,11,L0\|L1}, /* 71: 0110 0100 0111 0001 xxxx xxxx */
	1244	{&upd7810_device::SBI_PC_xx, 3,20,11,L0\|L1}, /* 72: 0110 0100 0111 0010 xxxx xxxx */
	1245	{&upd7810_device::SBI_PD_xx, 3,20,11,L0\|L1}, /* 73: 0110 0100 0111 0011 xxxx xxxx */
	1246	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 74: 0110 0100 0111 0100 xxxx xxxx */
	1247	{&upd7810_device::SBI_PF_xx, 3,20,11,L0\|L1}, /* 75: 0110 0100 0111 0101 xxxx xxxx */
	1248	{&upd7810_device::SBI_MKH_xx, 3,20,11,L0\|L1}, /* 76: 0110 0100 0111 0110 xxxx xxxx */
	1249	{&upd7810_device::SBI_MKL_xx, 3,20,11,L0\|L1}, /* 77: 0110 0100 0111 0111 xxxx xxxx */
	1250	{&upd7810_device::EQI_PA_xx, 3,20,11,L0\|L1}, /* 78: 0110 0100 0111 1000 xxxx xxxx */
	1251	{&upd7810_device::EQI_PB_xx, 3,20,11,L0\|L1}, /* 79: 0110 0100 0111 1001 xxxx xxxx */
	1252	{&upd7810_device::EQI_PC_xx, 3,20,11,L0\|L1}, /* 7a: 0110 0100 0111 1010 xxxx xxxx */
	1253	{&upd7810_device::EQI_PD_xx, 3,20,11,L0\|L1}, /* 7b: 0110 0100 0111 1011 xxxx xxxx */
	1254	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 7c: 0110 0100 0111 1100 xxxx xxxx */
	1255	{&upd7810_device::EQI_PF_xx, 3,20,11,L0\|L1}, /* 7d: 0110 0100 0111 1101 xxxx xxxx */
	1256	{&upd7810_device::EQI_MKH_xx, 3,20,11,L0\|L1}, /* 7e: 0110 0100 0111 1110 xxxx xxxx */
	1257	{&upd7810_device::EQI_MKL_xx, 3,20,11,L0\|L1}, /* 7f: 0110 0100 0111 1111 xxxx xxxx */
	1258
	1259	{&upd7810_device::MVI_ANM_xx, 3,14,11,L0\|L1}, /* 80: 0110 0100 1000 0000 xxxx xxxx */
	1260	{&upd7810_device::MVI_SMH_xx, 3,14,11,L0\|L1}, /* 81: 0110 0100 1000 0001 xxxx xxxx */
	1261	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 82: 0110 0100 1000 0010 xxxx xxxx */
	1262	{&upd7810_device::MVI_EOM_xx, 3,14,11,L0\|L1}, /* 83: 0110 0100 1000 0011 xxxx xxxx */
	1263	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 84: 0110 0100 1000 0100 xxxx xxxx */
	1264	{&upd7810_device::MVI_TMM_xx, 3,14,11,L0\|L1}, /* 85: 0110 0100 1000 0101 xxxx xxxx */
	1265	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 86: 0110 0100 1000 0110 xxxx xxxx */
	1266	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 87: 0110 0100 1000 0111 xxxx xxxx */
	1267	{&upd7810_device::ANI_ANM_xx, 3,20,11,L0\|L1}, /* 88: 0110 0100 1000 1000 xxxx xxxx */
	1268	{&upd7810_device::ANI_SMH_xx, 3,20,11,L0\|L1}, /* 89: 0110 0100 1000 1001 xxxx xxxx */
	1269	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 8a: 0110 0100 1000 1010 xxxx xxxx */
	1270	{&upd7810_device::ANI_EOM_xx, 3,20,11,L0\|L1}, /* 8b: 0110 0100 1000 1011 xxxx xxxx */
	1271	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 8c: 0110 0100 1000 1100 xxxx xxxx */
	1272	{&upd7810_device::ANI_TMM_xx, 3,20,11,L0\|L1}, /* 8d: 0110 0100 1000 1101 xxxx xxxx */
	1273	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 8e: 0110 0100 1000 1110 xxxx xxxx */
	1274	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 8f: 0110 0100 1000 1111 xxxx xxxx */
	1275
	1276	{&upd7810_device::XRI_ANM_xx, 3,20,11,L0\|L1}, /* 90: 0110 0100 1001 0000 xxxx xxxx */
	1277	{&upd7810_device::XRI_SMH_xx, 3,20,11,L0\|L1}, /* 91: 0110 0100 1001 0001 xxxx xxxx */
	1278	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 92: 0110 0100 1001 0010 xxxx xxxx */
	1279	{&upd7810_device::XRI_EOM_xx, 3,20,11,L0\|L1}, /* 93: 0110 0100 1001 0011 xxxx xxxx */
	1280	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 94: 0110 0100 1001 0100 xxxx xxxx */
	1281	{&upd7810_device::XRI_TMM_xx, 3,20,11,L0\|L1}, /* 95: 0110 0100 1001 0101 xxxx xxxx */
	1282	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 96: 0110 0100 1001 0110 xxxx xxxx */
	1283	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 97: 0110 0100 1001 0111 xxxx xxxx */
	1284	{&upd7810_device::ORI_ANM_xx, 3,20,11,L0\|L1}, /* 98: 0110 0100 1001 1000 xxxx xxxx */
	1285	{&upd7810_device::ORI_SMH_xx, 3,20,11,L0\|L1}, /* 99: 0110 0100 1001 1001 xxxx xxxx */
	1286	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 9a: 0110 0100 1001 1010 xxxx xxxx */
	1287	{&upd7810_device::ORI_EOM_xx, 3,20,11,L0\|L1}, /* 9b: 0110 0100 1001 1011 xxxx xxxx */
	1288	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 9c: 0110 0100 1001 1100 xxxx xxxx */
	1289	{&upd7810_device::ORI_TMM_xx, 3,20,11,L0\|L1}, /* 9d: 0110 0100 1001 1101 xxxx xxxx */
	1290	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 9e: 0110 0100 1001 1110 xxxx xxxx */
	1291	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* 9f: 0110 0100 1001 1111 xxxx xxxx */
	1292
	1293	{&upd7810_device::ADINC_ANM_xx, 3,20,11,L0\|L1}, /* a0: 0110 0100 1010 0000 xxxx xxxx */
	1294	{&upd7810_device::ADINC_SMH_xx, 3,20,11,L0\|L1}, /* a1: 0110 0100 1010 0001 xxxx xxxx */
	1295	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* a2: 0110 0100 1010 0010 xxxx xxxx */
	1296	{&upd7810_device::ADINC_EOM_xx, 3,20,11,L0\|L1}, /* a3: 0110 0100 1010 0011 xxxx xxxx */
	1297	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* a4: 0110 0100 1010 0100 xxxx xxxx */
	1298	{&upd7810_device::ADINC_TMM_xx, 3,20,11,L0\|L1}, /* a5: 0110 0100 1010 0101 xxxx xxxx */
	1299	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* a6: 0110 0100 1010 0110 xxxx xxxx */
	1300	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* a7: 0110 0100 1010 0111 xxxx xxxx */
	1301	{&upd7810_device::GTI_ANM_xx, 3,20,11,L0\|L1}, /* a8: 0110 0100 1010 1000 xxxx xxxx */
	1302	{&upd7810_device::GTI_SMH_xx, 3,20,11,L0\|L1}, /* a9: 0110 0100 1010 1001 xxxx xxxx */
	1303	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* aa: 0110 0100 1010 1010 xxxx xxxx */
	1304	{&upd7810_device::GTI_EOM_xx, 3,20,11,L0\|L1}, /* ab: 0110 0100 1010 1011 xxxx xxxx */
	1305	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ac: 0110 0100 1010 1100 xxxx xxxx */
	1306	{&upd7810_device::GTI_TMM_xx, 3,20,11,L0\|L1}, /* ad: 0110 0100 1010 1101 xxxx xxxx */
	1307	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ae: 0110 0100 1010 1110 xxxx xxxx */
	1308	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* af: 0110 0100 1010 1111 xxxx xxxx */
	1309
	1310	{&upd7810_device::SUINB_ANM_xx, 3,20,11,L0\|L1}, /* b0: 0110 0100 1011 0000 xxxx xxxx */
	1311	{&upd7810_device::SUINB_SMH_xx, 3,20,11,L0\|L1}, /* b1: 0110 0100 1011 0001 xxxx xxxx */
	1312	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* b2: 0110 0100 1011 0010 xxxx xxxx */
	1313	{&upd7810_device::SUINB_EOM_xx, 3,20,11,L0\|L1}, /* b3: 0110 0100 1011 0011 xxxx xxxx */
	1314	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* b4: 0110 0100 1011 0100 xxxx xxxx */
	1315	{&upd7810_device::SUINB_TMM_xx, 3,20,11,L0\|L1}, /* b5: 0110 0100 1011 0101 xxxx xxxx */
	1316	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* b6: 0110 0100 1011 0110 xxxx xxxx */
	1317	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* b7: 0110 0100 1011 0111 xxxx xxxx */
	1318	{&upd7810_device::LTI_ANM_xx, 3,20,11,L0\|L1}, /* b8: 0110 0100 1011 1000 xxxx xxxx */
	1319	{&upd7810_device::LTI_SMH_xx, 3,20,11,L0\|L1}, /* b9: 0110 0100 1011 1001 xxxx xxxx */
	1320	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ba: 0110 0100 1011 1010 xxxx xxxx */
	1321	{&upd7810_device::LTI_EOM_xx, 3,20,11,L0\|L1}, /* bb: 0110 0100 1011 1011 xxxx xxxx */
	1322	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* bc: 0110 0100 1011 1100 xxxx xxxx */
	1323	{&upd7810_device::LTI_TMM_xx, 3,20,11,L0\|L1}, /* bd: 0110 0100 1011 1101 xxxx xxxx */
	1324	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* be: 0110 0100 1011 1110 xxxx xxxx */
	1325	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* bf: 0110 0100 1011 1111 xxxx xxxx */
	1326
	1327	{&upd7810_device::ADI_ANM_xx, 3,20,11,L0\|L1}, /* c0: 0110 0100 1100 0000 xxxx xxxx */
	1328	{&upd7810_device::ADI_SMH_xx, 3,20,11,L0\|L1}, /* c1: 0110 0100 1100 0001 xxxx xxxx */
	1329	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* c2: 0110 0100 1100 0010 xxxx xxxx */
	1330	{&upd7810_device::ADI_EOM_xx, 3,20,11,L0\|L1}, /* c3: 0110 0100 1100 0011 xxxx xxxx */
	1331	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* c4: 0110 0100 1100 0100 xxxx xxxx */
	1332	{&upd7810_device::ADI_TMM_xx, 3,20,11,L0\|L1}, /* c5: 0110 0100 1100 0101 xxxx xxxx */
	1333	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* c6: 0110 0100 1100 0110 xxxx xxxx */
	1334	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* c7: 0110 0100 1100 0111 xxxx xxxx */
	1335	{&upd7810_device::ONI_ANM_xx, 3,20,11,L0\|L1}, /* c8: 0110 0100 1100 1000 xxxx xxxx */
	1336	{&upd7810_device::ONI_SMH_xx, 3,20,11,L0\|L1}, /* c9: 0110 0100 1100 1001 xxxx xxxx */
	1337	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ca: 0110 0100 1100 1010 xxxx xxxx */
	1338	{&upd7810_device::ONI_EOM_xx, 3,20,11,L0\|L1}, /* cb: 0110 0100 1100 1011 xxxx xxxx */
	1339	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* cc: 0110 0100 1100 1100 xxxx xxxx */
	1340	{&upd7810_device::ONI_TMM_xx, 3,20,11,L0\|L1}, /* cd: 0110 0100 1100 1101 xxxx xxxx */
	1341	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ce: 0110 0100 1100 1110 xxxx xxxx */
	1342	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* cf: 0110 0100 1100 1111 xxxx xxxx */
	1343
	1344	{&upd7810_device::ACI_ANM_xx, 3,20,11,L0\|L1}, /* d0: 0110 0100 1101 0000 xxxx xxxx */
	1345	{&upd7810_device::ACI_SMH_xx, 3,20,11,L0\|L1}, /* d1: 0110 0100 1101 0001 xxxx xxxx */
	1346	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* d2: 0110 0100 1101 0010 xxxx xxxx */
	1347	{&upd7810_device::ACI_EOM_xx, 3,20,11,L0\|L1}, /* d3: 0110 0100 1101 0011 xxxx xxxx */
	1348	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* d4: 0110 0100 1101 0100 xxxx xxxx */
	1349	{&upd7810_device::ACI_TMM_xx, 3,20,11,L0\|L1}, /* d5: 0110 0100 1101 0101 xxxx xxxx */
	1350	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* d6: 0110 0100 1101 0110 xxxx xxxx */
	1351	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* d7: 0110 0100 1101 0111 xxxx xxxx */
	1352	{&upd7810_device::OFFI_ANM_xx, 3,20,11,L0\|L1}, /* d8: 0110 0100 1101 1000 xxxx xxxx */
	1353	{&upd7810_device::OFFI_SMH_xx, 3,20,11,L0\|L1}, /* d9: 0110 0100 1101 1001 xxxx xxxx */
	1354	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* da: 0110 0100 1101 1010 xxxx xxxx */
	1355	{&upd7810_device::OFFI_EOM_xx, 3,20,11,L0\|L1}, /* db: 0110 0100 1101 1011 xxxx xxxx */
	1356	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* dc: 0110 0100 1101 1100 xxxx xxxx */
	1357	{&upd7810_device::OFFI_TMM_xx, 3,20,11,L0\|L1}, /* dd: 0110 0100 1101 1101 xxxx xxxx */
	1358	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* de: 0110 0100 1101 1110 xxxx xxxx */
	1359	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* df: 0110 0100 1101 1111 xxxx xxxx */
	1360
	1361	{&upd7810_device::SUI_ANM_xx, 3,20,11,L0\|L1}, /* e0: 0110 0100 1110 0000 xxxx xxxx */
	1362	{&upd7810_device::SUI_SMH_xx, 3,20,11,L0\|L1}, /* e1: 0110 0100 1110 0001 xxxx xxxx */
	1363	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* e2: 0110 0100 1110 0010 xxxx xxxx */
	1364	{&upd7810_device::SUI_EOM_xx, 3,20,11,L0\|L1}, /* e3: 0110 0100 1110 0011 xxxx xxxx */
	1365	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* e4: 0110 0100 1110 0100 xxxx xxxx */
	1366	{&upd7810_device::SUI_TMM_xx, 3,20,11,L0\|L1}, /* e5: 0110 0100 1110 0101 xxxx xxxx */
	1367	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* e6: 0110 0100 1110 0110 xxxx xxxx */
	1368	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* e7: 0110 0100 1110 0111 xxxx xxxx */
	1369	{&upd7810_device::NEI_ANM_xx, 3,20,11,L0\|L1}, /* e8: 0110 0100 1110 1000 xxxx xxxx */
	1370	{&upd7810_device::NEI_SMH_xx, 3,20,11,L0\|L1}, /* e9: 0110 0100 1110 1001 xxxx xxxx */
	1371	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ea: 0110 0100 1110 1010 xxxx xxxx */
	1372	{&upd7810_device::NEI_EOM_xx, 3,20,11,L0\|L1}, /* eb: 0110 0100 1110 1011 xxxx xxxx */
	1373	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ec: 0110 0100 1110 1100 xxxx xxxx */
	1374	{&upd7810_device::NEI_TMM_xx, 3,20,11,L0\|L1}, /* ed: 0110 0100 1110 1101 xxxx xxxx */
	1375	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ee: 0110 0100 1110 1110 xxxx xxxx */
	1376	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* ef: 0110 0100 1110 1111 xxxx xxxx */
	1377
	1378	{&upd7810_device::SBI_ANM_xx, 3,20,11,L0\|L1}, /* f0: 0110 0100 1111 0000 xxxx xxxx */
	1379	{&upd7810_device::SBI_SMH_xx, 3,20,11,L0\|L1}, /* f1: 0110 0100 1111 0001 xxxx xxxx */
	1380	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* f2: 0110 0100 1111 0010 xxxx xxxx */
	1381	{&upd7810_device::SBI_EOM_xx, 3,20,11,L0\|L1}, /* f3: 0110 0100 1111 0011 xxxx xxxx */
	1382	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* f4: 0110 0100 1111 0100 xxxx xxxx */
	1383	{&upd7810_device::SBI_TMM_xx, 3,20,11,L0\|L1}, /* f5: 0110 0100 1111 0101 xxxx xxxx */
	1384	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* f6: 0110 0100 1111 0110 xxxx xxxx */
	1385	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* f7: 0110 0100 1111 0111 xxxx xxxx */
	1386	{&upd7810_device::EQI_ANM_xx, 3,20,11,L0\|L1}, /* f8: 0110 0100 1111 1000 xxxx xxxx */
	1387	{&upd7810_device::EQI_SMH_xx, 3,20,11,L0\|L1}, /* f9: 0110 0100 1111 1001 xxxx xxxx */
	1388	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* fa: 0110 0100 1111 1010 xxxx xxxx */
	1389	{&upd7810_device::EQI_EOM_xx, 3,20,11,L0\|L1}, /* fb: 0110 0100 1111 1011 xxxx xxxx */
	1390	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* fc: 0110 0100 1111 1100 xxxx xxxx */
	1391	{&upd7810_device::EQI_TMM_xx, 3,20,11,L0\|L1}, /* fd: 0110 0100 1111 1101 xxxx xxxx */
	1392	{&upd7810_device::illegal2, 3,11,11,L0\|L1}, /* fe: 0110 0100 1111 1110 xxxx xxxx */
	1393	{&upd7810_device::illegal2, 3,11,11,L0\|L1} /* ff: 0110 0100 1111 1111 xxxx xxxx */
	1394	};
	1395
	1396	/* prefix 70 */
	1397	const struct upd7810_device::opcode_s upd7810_device::s_op70[256] =
	1398	{
	1399	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 00: 0111 0000 0000 0000 */
	1400	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 01: 0111 0000 0000 0001 */
	1401	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 02: 0111 0000 0000 0010 */
	1402	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 03: 0111 0000 0000 0011 */
	1403	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 04: 0111 0000 0000 0100 */
	1404	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 05: 0111 0000 0000 0101 */
	1405	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 06: 0111 0000 0000 0110 */
	1406	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 07: 0111 0000 0000 0111 */
	1407	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 08: 0111 0000 0000 1000 */
	1408	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 09: 0111 0000 0000 1001 */
	1409	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0a: 0111 0000 0000 1010 */
	1410	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0b: 0111 0000 0000 1011 */
	1411	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0c: 0111 0000 0000 1100 */
	1412	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 0d: 0111 0000 0000 1101 */
	1413	{&upd7810_device::SSPD_w, 4,20,20,L0\|L1}, /* 0e: 0111 0000 0000 1110 llll llll hhhh hhhh */
	1414	{&upd7810_device::LSPD_w, 4,20,20,L0\|L1}, /* 0f: 0111 0000 0000 1111 llll llll hhhh hhhh */
	1415
	1416	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 10: 0111 0000 0001 0000 */
	1417	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 11: 0111 0000 0001 0001 */
	1418	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 12: 0111 0000 0001 0010 */
	1419	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 13: 0111 0000 0001 0011 */
	1420	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 14: 0111 0000 0001 0100 */
	1421	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 15: 0111 0000 0001 0101 */
	1422	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 16: 0111 0000 0001 0110 */
	1423	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 17: 0111 0000 0001 0111 */
	1424	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 18: 0111 0000 0001 1000 */
	1425	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 19: 0111 0000 0001 1001 */
	1426	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1a: 0111 0000 0001 1010 */
	1427	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1b: 0111 0000 0001 1011 */
	1428	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1c: 0111 0000 0001 1100 */
	1429	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 1d: 0111 0000 0001 1101 */
	1430	{&upd7810_device::SBCD_w, 4,20,20,L0\|L1}, /* 1e: 0111 0000 0001 1110 llll llll hhhh hhhh */
	1431	{&upd7810_device::LBCD_w, 4,20,20,L0\|L1}, /* 1f: 0111 0000 0001 1111 llll llll hhhh hhhh */
	1432
	1433	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 20: 0111 0000 0010 0000 */
	1434	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 21: 0111 0000 0010 0001 */
	1435	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 22: 0111 0000 0010 0010 */
	1436	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 23: 0111 0000 0010 0011 */
	1437	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 24: 0111 0000 0010 0100 */
	1438	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 25: 0111 0000 0010 0101 */
	1439	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 26: 0111 0000 0010 0110 */
	1440	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 27: 0111 0000 0010 0111 */
	1441	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 28: 0111 0000 0010 1000 */
	1442	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 29: 0111 0000 0010 1001 */
	1443	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2a: 0111 0000 0010 1010 */
	1444	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2b: 0111 0000 0010 1011 */
	1445	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2c: 0111 0000 0010 1100 */
	1446	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 2d: 0111 0000 0010 1101 */
	1447	{&upd7810_device::SDED_w, 4,20,20,L0\|L1}, /* 2e: 0111 0000 0010 1110 llll llll hhhh hhhh */
	1448	{&upd7810_device::LDED_w, 4,20,20,L0\|L1}, /* 2f: 0111 0000 0010 1111 llll llll hhhh hhhh */
	1449
	1450	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 30: 0111 0000 0011 0000 */
	1451	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 31: 0111 0000 0011 0001 */
	1452	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 32: 0111 0000 0011 0010 */
	1453	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 33: 0111 0000 0011 0011 */
	1454	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 34: 0111 0000 0011 0100 */
	1455	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 35: 0111 0000 0011 0101 */
	1456	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 36: 0111 0000 0011 0110 */
	1457	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 37: 0111 0000 0011 0111 */
	1458	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 38: 0111 0000 0011 1000 */
	1459	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 39: 0111 0000 0011 1001 */
	1460	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3a: 0111 0000 0011 1010 */
	1461	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3b: 0111 0000 0011 1011 */
	1462	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3c: 0111 0000 0011 1100 */
	1463	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 3d: 0111 0000 0011 1101 */
	1464	{&upd7810_device::SHLD_w, 4,20,20,L0\|L1}, /* 3e: 0111 0000 0011 1110 llll llll hhhh hhhh */
	1465	{&upd7810_device::LHLD_w, 4,20,20,L0\|L1}, /* 3f: 0111 0000 0011 1111 llll llll hhhh hhhh */
	1466
	1467	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 40: 0111 0000 0100 0000 */
	1468	{&upd7810_device::EADD_EA_A, 2,11,11,L0\|L1}, /* 41: 0111 0000 0100 0001 */
	1469	{&upd7810_device::EADD_EA_B, 2,11,11,L0\|L1}, /* 42: 0111 0000 0100 0010 */
	1470	{&upd7810_device::EADD_EA_C, 2,11,11,L0\|L1}, /* 43: 0111 0000 0100 0011 */
	1471	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 44: 0111 0000 0100 0100 */
	1472	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 45: 0111 0000 0100 0101 */
	1473	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 46: 0111 0000 0100 0110 */
	1474	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 47: 0111 0000 0100 0111 */
	1475	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 48: 0111 0000 0100 1000 */
	1476	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 49: 0111 0000 0100 1001 */
	1477	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4a: 0111 0000 0100 1010 */
	1478	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4b: 0111 0000 0100 1011 */
	1479	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4c: 0111 0000 0100 1100 */
	1480	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4d: 0111 0000 0100 1101 */
	1481	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4e: 0111 0000 0100 1110 */
	1482	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 4f: 0111 0000 0100 1111 */
	1483
	1484	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 50: 0111 0000 0101 0000 */
	1485	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 51: 0111 0000 0101 0001 */
	1486	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 52: 0111 0000 0101 0010 */
	1487	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 53: 0111 0000 0101 0011 */
	1488	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 54: 0111 0000 0101 0100 */
	1489	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 55: 0111 0000 0101 0101 */
	1490	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 56: 0111 0000 0101 0110 */
	1491	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 57: 0111 0000 0101 0111 */
	1492	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 58: 0111 0000 0101 1000 */
	1493	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 59: 0111 0000 0101 1001 */
	1494	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5a: 0111 0000 0101 1010 */
	1495	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5b: 0111 0000 0101 1011 */
	1496	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5c: 0111 0000 0101 1100 */
	1497	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5d: 0111 0000 0101 1101 */
	1498	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5e: 0111 0000 0101 1110 */
	1499	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 5f: 0111 0000 0101 1111 */
	1500
	1501	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 60: 0111 0000 0110 0000 */
	1502	{&upd7810_device::ESUB_EA_A, 2,11,11,L0\|L1}, /* 61: 0111 0000 0110 0001 */
	1503	{&upd7810_device::ESUB_EA_B, 2,11,11,L0\|L1}, /* 62: 0111 0000 0110 0010 */
	1504	{&upd7810_device::ESUB_EA_C, 2,11,11,L0\|L1}, /* 63: 0111 0000 0110 0011 */
	1505	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 64: 0111 0000 0110 0100 */
	1506	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 65: 0111 0000 0110 0101 */
	1507	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 66: 0111 0000 0110 0110 */
	1508	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 67: 0111 0000 0110 0111 */
	1509	{&upd7810_device::MOV_V_w, 4,17,17,L0\|L1}, /* 68: 0111 0000 0110 1000 llll llll hhhh hhhh */
	1510	{&upd7810_device::MOV_A_w, 4,17,17,L0\|L1}, /* 69: 0111 0000 0110 1001 llll llll hhhh hhhh */
	1511	{&upd7810_device::MOV_B_w, 4,17,17,L0\|L1}, /* 6a: 0111 0000 0110 1010 llll llll hhhh hhhh */
	1512	{&upd7810_device::MOV_C_w, 4,17,17,L0\|L1}, /* 6b: 0111 0000 0110 1011 llll llll hhhh hhhh */
	1513	{&upd7810_device::MOV_D_w, 4,17,17,L0\|L1}, /* 6c: 0111 0000 0110 1100 llll llll hhhh hhhh */
	1514	{&upd7810_device::MOV_E_w, 4,17,17,L0\|L1}, /* 6d: 0111 0000 0110 1101 llll llll hhhh hhhh */
	1515	{&upd7810_device::MOV_H_w, 4,17,17,L0\|L1}, /* 6e: 0111 0000 0110 1110 llll llll hhhh hhhh */
	1516	{&upd7810_device::MOV_L_w, 4,17,17,L0\|L1}, /* 6f: 0111 0000 0110 1111 llll llll hhhh hhhh */
	1517
	1518	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 70: 0111 0000 0111 0000 */
	1519	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 71: 0111 0000 0111 0001 */
	1520	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 72: 0111 0000 0111 0010 */
	1521	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 73: 0111 0000 0111 0011 */
	1522	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 74: 0111 0000 0111 0100 */
	1523	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 75: 0111 0000 0111 0101 */
	1524	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 76: 0111 0000 0111 0110 */
	1525	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 77: 0111 0000 0111 0111 */
	1526	{&upd7810_device::MOV_w_V, 4,17,17,L0\|L1}, /* 78: 0111 0000 0111 1000 llll llll hhhh hhhh */
	1527	{&upd7810_device::MOV_w_A, 4,17,17,L0\|L1}, /* 79: 0111 0000 0111 1001 llll llll hhhh hhhh */
	1528	{&upd7810_device::MOV_w_B, 4,17,17,L0\|L1}, /* 7a: 0111 0000 0111 1010 llll llll hhhh hhhh */
	1529	{&upd7810_device::MOV_w_C, 4,17,17,L0\|L1}, /* 7b: 0111 0000 0111 1011 llll llll hhhh hhhh */
	1530	{&upd7810_device::MOV_w_D, 4,17,17,L0\|L1}, /* 7c: 0111 0000 0111 1100 llll llll hhhh hhhh */
	1531	{&upd7810_device::MOV_w_E, 4,17,17,L0\|L1}, /* 7d: 0111 0000 0111 1101 llll llll hhhh hhhh */
	1532	{&upd7810_device::MOV_w_H, 4,17,17,L0\|L1}, /* 7e: 0111 0000 0111 1110 llll llll hhhh hhhh */
	1533	{&upd7810_device::MOV_w_L, 4,17,17,L0\|L1}, /* 7f: 0111 0000 0111 1111 llll llll hhhh hhhh */
	1534
	1535	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 80: 0111 0000 1000 0000 */
	1536	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 81: 0111 0000 1000 0001 */
	1537	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 82: 0111 0000 1000 0010 */
	1538	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 83: 0111 0000 1000 0011 */
	1539	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 84: 0111 0000 1000 0100 */
	1540	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 85: 0111 0000 1000 0101 */
	1541	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 86: 0111 0000 1000 0110 */
	1542	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 87: 0111 0000 1000 0111 */
	1543	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 88: 0111 0000 1000 1000 */
	1544	{&upd7810_device::ANAX_B, 2,11,11,L0\|L1}, /* 89: 0111 0000 1000 1001 */
	1545	{&upd7810_device::ANAX_D, 2,11,11,L0\|L1}, /* 8a: 0111 0000 1000 1010 */
	1546	{&upd7810_device::ANAX_H, 2,11,11,L0\|L1}, /* 8b: 0111 0000 1000 1011 */
	1547	{&upd7810_device::ANAX_Dp, 2,11,11,L0\|L1}, /* 8c: 0111 0000 1000 1100 */
	1548	{&upd7810_device::ANAX_Hp, 2,11,11,L0\|L1}, /* 8d: 0111 0000 1000 1101 */
	1549	{&upd7810_device::ANAX_Dm, 2,11,11,L0\|L1}, /* 8e: 0111 0000 1000 1110 */
	1550	{&upd7810_device::ANAX_Hm, 2,11,11,L0\|L1}, /* 8f: 0111 0000 1000 1111 */
	1551
	1552	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 90: 0111 0000 1001 0000 */
	1553	{&upd7810_device::XRAX_B, 2,11,11,L0\|L1}, /* 91: 0111 0000 1001 0001 */
	1554	{&upd7810_device::XRAX_D, 2,11,11,L0\|L1}, /* 92: 0111 0000 1001 0010 */
	1555	{&upd7810_device::XRAX_H, 2,11,11,L0\|L1}, /* 93: 0111 0000 1001 0011 */
	1556	{&upd7810_device::XRAX_Dp, 2,11,11,L0\|L1}, /* 94: 0111 0000 1001 0100 */
	1557	{&upd7810_device::XRAX_Hp, 2,11,11,L0\|L1}, /* 95: 0111 0000 1001 0101 */
	1558	{&upd7810_device::XRAX_Dm, 2,11,11,L0\|L1}, /* 96: 0111 0000 1001 0110 */
	1559	{&upd7810_device::XRAX_Hm, 2,11,11,L0\|L1}, /* 97: 0111 0000 1001 0111 */
	1560	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 98: 0111 0000 1001 1000 */
	1561	// orax added, timings not verified
	1562	{&upd7810_device::ORAX_B, 2,11, 8,L0\|L1}, /* 99: 0111 0000 1001 1001 */
	1563	{&upd7810_device::ORAX_D, 2,11, 8,L0\|L1}, /* 9a: 0111 0000 1001 1010 */
	1564	{&upd7810_device::ORAX_H, 2,11, 8,L0\|L1}, /* 9b: 0111 0000 1001 1011 */
	1565	{&upd7810_device::ORAX_Dp, 2,11, 8,L0\|L1}, /* 9c: 0111 0000 1001 1100 */
	1566	{&upd7810_device::ORAX_Hp, 2,11, 8,L0\|L1}, /* 9d: 0111 0000 1001 1101 */
	1567	{&upd7810_device::ORAX_Dm, 2,11, 8,L0\|L1}, /* 9e: 0111 0000 1001 1110 */
	1568	{&upd7810_device::ORAX_Hm, 2,11, 8,L0\|L1}, /* 9f: 0111 0000 1001 1111 */
	1569
	1570	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a0: 0111 0000 1010 0000 */
	1571	{&upd7810_device::ADDNCX_B, 2,11, 8,L0\|L1}, /* a1: 0111 0000 1010 0001 */
	1572	{&upd7810_device::ADDNCX_D, 2,11, 8,L0\|L1}, /* a2: 0111 0000 1010 0010 */
	1573	{&upd7810_device::ADDNCX_H, 2,11, 8,L0\|L1}, /* a3: 0111 0000 1010 0011 */
	1574	{&upd7810_device::ADDNCX_Dp, 2,11, 8,L0\|L1}, /* a4: 0111 0000 1010 0100 */
	1575	{&upd7810_device::ADDNCX_Hp, 2,11, 8,L0\|L1}, /* a5: 0111 0000 1010 0101 */
	1576	{&upd7810_device::ADDNCX_Dm, 2,11, 8,L0\|L1}, /* a6: 0111 0000 1010 0110 */
	1577	{&upd7810_device::ADDNCX_Hm, 2,11, 8,L0\|L1}, /* a7: 0111 0000 1010 0111 */
	1578	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a8: 0111 0000 1010 1000 */
	1579	{&upd7810_device::GTAX_B, 2,11,11,L0\|L1}, /* a9: 0111 0000 1010 1001 */
	1580	{&upd7810_device::GTAX_D, 2,11,11,L0\|L1}, /* aa: 0111 0000 1010 1010 */
	1581	{&upd7810_device::GTAX_H, 2,11,11,L0\|L1}, /* ab: 0111 0000 1010 1011 */
	1582	{&upd7810_device::GTAX_Dp, 2,11,11,L0\|L1}, /* ac: 0111 0000 1010 1100 */
	1583	{&upd7810_device::GTAX_Hp, 2,11,11,L0\|L1}, /* ad: 0111 0000 1010 1101 */
	1584	{&upd7810_device::GTAX_Dm, 2,11,11,L0\|L1}, /* ae: 0111 0000 1010 1110 */
	1585	{&upd7810_device::GTAX_Hm, 2,11,11,L0\|L1}, /* af: 0111 0000 1010 1111 */
	1586
	1587	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b0: 0111 0000 1011 0000 */
	1588	{&upd7810_device::SUBNBX_B, 2,11,11,L0\|L1}, /* b1: 0111 0000 1011 0001 */
	1589	{&upd7810_device::SUBNBX_D, 2,11,11,L0\|L1}, /* b2: 0111 0000 1011 0010 */
	1590	{&upd7810_device::SUBNBX_H, 2,11,11,L0\|L1}, /* b3: 0111 0000 1011 0011 */
	1591	{&upd7810_device::SUBNBX_Dp, 2,11,11,L0\|L1}, /* b4: 0111 0000 1011 0100 */
	1592	{&upd7810_device::SUBNBX_Hp, 2,11,11,L0\|L1}, /* b5: 0111 0000 1011 0101 */
	1593	{&upd7810_device::SUBNBX_Dm, 2,11,11,L0\|L1}, /* b6: 0111 0000 1011 0110 */
	1594	{&upd7810_device::SUBNBX_Hm, 2,11,11,L0\|L1}, /* b7: 0111 0000 1011 0111 */
	1595	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b8: 0111 0000 1011 1000 */
	1596	{&upd7810_device::LTAX_B, 2,11,11,L0\|L1}, /* b9: 0111 0000 1011 1001 */
	1597	{&upd7810_device::LTAX_D, 2,11,11,L0\|L1}, /* ba: 0111 0000 1011 1010 */
	1598	{&upd7810_device::LTAX_H, 2,11,11,L0\|L1}, /* bb: 0111 0000 1011 1011 */
	1599	{&upd7810_device::LTAX_Dp, 2,11,11,L0\|L1}, /* bc: 0111 0000 1011 1100 */
	1600	{&upd7810_device::LTAX_Hp, 2,11,11,L0\|L1}, /* bd: 0111 0000 1011 1101 */
	1601	{&upd7810_device::LTAX_Dm, 2,11,11,L0\|L1}, /* be: 0111 0000 1011 1110 */
	1602	{&upd7810_device::LTAX_Hm, 2,11,11,L0\|L1}, /* bf: 0111 0000 1011 1111 */
	1603
	1604	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c0: 0111 0000 1100 0000 */
	1605	{&upd7810_device::ADDX_B, 2,11, 8,L0\|L1}, /* c1: 0111 0000 1100 0001 */
	1606	{&upd7810_device::ADDX_D, 2,11, 8,L0\|L1}, /* c2: 0111 0000 1100 0010 */
	1607	{&upd7810_device::ADDX_H, 2,11, 8,L0\|L1}, /* c3: 0111 0000 1100 0011 */
	1608	{&upd7810_device::ADDX_Dp, 2,11, 8,L0\|L1}, /* c4: 0111 0000 1100 0100 */
	1609	{&upd7810_device::ADDX_Hp, 2,11, 8,L0\|L1}, /* c5: 0111 0000 1100 0101 */
	1610	{&upd7810_device::ADDX_Dm, 2,11, 8,L0\|L1}, /* c6: 0111 0000 1100 0110 */
	1611	{&upd7810_device::ADDX_Hm, 2,11, 8,L0\|L1}, /* c7: 0111 0000 1100 0111 */
	1612	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c8: 0111 0000 1100 1000 */
	1613	{&upd7810_device::ONAX_B, 2,11, 8,L0\|L1}, /* c9: 0111 0000 1100 1001 */
	1614	{&upd7810_device::ONAX_D, 2,11, 8,L0\|L1}, /* ca: 0111 0000 1100 1010 */
	1615	{&upd7810_device::ONAX_H, 2,11, 8,L0\|L1}, /* cb: 0111 0000 1100 1011 */
	1616	{&upd7810_device::ONAX_Dp, 2,11, 8,L0\|L1}, /* cc: 0111 0000 1100 1100 */
	1617	{&upd7810_device::ONAX_Hp, 2,11, 8,L0\|L1}, /* cd: 0111 0000 1100 1101 */
	1618	{&upd7810_device::ONAX_Dm, 2,11, 8,L0\|L1}, /* ce: 0111 0000 1100 1110 */
	1619	{&upd7810_device::ONAX_Hm, 2,11, 8,L0\|L1}, /* cf: 0111 0000 1100 1111 */
	1620
	1621	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d0: 0111 0000 1101 0000 */
	1622	{&upd7810_device::ADCX_B, 2,11, 8,L0\|L1}, /* d1: 0111 0000 1101 0001 */
	1623	{&upd7810_device::ADCX_D, 2,11, 8,L0\|L1}, /* d2: 0111 0000 1101 0010 */
	1624	{&upd7810_device::ADCX_H, 2,11, 8,L0\|L1}, /* d3: 0111 0000 1101 0011 */
	1625	{&upd7810_device::ADCX_Dp, 2,11, 8,L0\|L1}, /* d4: 0111 0000 1101 0100 */
	1626	{&upd7810_device::ADCX_Hp, 2,11, 8,L0\|L1}, /* d5: 0111 0000 1101 0101 */
	1627	{&upd7810_device::ADCX_Dm, 2,11, 8,L0\|L1}, /* d6: 0111 0000 1101 0110 */
	1628	{&upd7810_device::ADCX_Hm, 2,11, 8,L0\|L1}, /* d7: 0111 0000 1101 0111 */
	1629	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d8: 0111 0000 1101 1000 */
	1630	{&upd7810_device::OFFAX_B, 2,11, 8,L0\|L1}, /* d9: 0111 0000 1101 1001 */
	1631	{&upd7810_device::OFFAX_D, 2,11, 8,L0\|L1}, /* da: 0111 0000 1101 1010 */
	1632	{&upd7810_device::OFFAX_H, 2,11, 8,L0\|L1}, /* db: 0111 0000 1101 1011 */
	1633	{&upd7810_device::OFFAX_Dp, 2,11, 8,L0\|L1}, /* dc: 0111 0000 1101 1100 */
	1634	{&upd7810_device::OFFAX_Hp, 2,11, 8,L0\|L1}, /* dd: 0111 0000 1101 1101 */
	1635	{&upd7810_device::OFFAX_Dm, 2,11, 8,L0\|L1}, /* de: 0111 0000 1101 1110 */
	1636	{&upd7810_device::OFFAX_Hm, 2,11, 8,L0\|L1}, /* df: 0111 0000 1101 1111 */
	1637
	1638	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e0: 0111 0000 1110 0000 */
	1639	{&upd7810_device::SUBX_B, 2,11,11,L0\|L1}, /* e1: 0111 0000 1110 0001 */
	1640	{&upd7810_device::SUBX_D, 2,11,11,L0\|L1}, /* e2: 0111 0000 1110 0010 */
	1641	{&upd7810_device::SUBX_H, 2,11,11,L0\|L1}, /* e3: 0111 0000 1110 0011 */
	1642	{&upd7810_device::SUBX_Dp, 2,11,11,L0\|L1}, /* e4: 0111 0000 1110 0100 */
	1643	{&upd7810_device::SUBX_Hp, 2,11,11,L0\|L1}, /* e5: 0111 0000 1110 0101 */
	1644	{&upd7810_device::SUBX_Dm, 2,11,11,L0\|L1}, /* e6: 0111 0000 1110 0110 */
	1645	{&upd7810_device::SUBX_Hm, 2,11,11,L0\|L1}, /* e7: 0111 0000 1110 0111 */
	1646	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e8: 0111 0000 1110 1000 */
	1647	{&upd7810_device::NEAX_B, 2,11,11,L0\|L1}, /* e9: 0111 0000 1110 1001 */
	1648	{&upd7810_device::NEAX_D, 2,11,11,L0\|L1}, /* ea: 0111 0000 1110 1010 */
	1649	{&upd7810_device::NEAX_H, 2,11,11,L0\|L1}, /* eb: 0111 0000 1110 1011 */
	1650	{&upd7810_device::NEAX_Dp, 2,11,11,L0\|L1}, /* ec: 0111 0000 1110 1100 */
	1651	{&upd7810_device::NEAX_Hp, 2,11,11,L0\|L1}, /* ed: 0111 0000 1110 1101 */
	1652	{&upd7810_device::NEAX_Dm, 2,11,11,L0\|L1}, /* ee: 0111 0000 1110 1110 */
	1653	{&upd7810_device::NEAX_Hm, 2,11,11,L0\|L1}, /* ef: 0111 0000 1110 1111 */
	1654
	1655	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f0: 0111 0000 1111 0000 */
	1656	{&upd7810_device::SBBX_B, 2,11,11,L0\|L1}, /* f1: 0111 0000 1111 0001 */
	1657	{&upd7810_device::SBBX_D, 2,11,11,L0\|L1}, /* f2: 0111 0000 1111 0010 */
	1658	{&upd7810_device::SBBX_H, 2,11,11,L0\|L1}, /* f3: 0111 0000 1111 0011 */
	1659	{&upd7810_device::SBBX_Dp, 2,11,11,L0\|L1}, /* f4: 0111 0000 1111 0100 */
	1660	{&upd7810_device::SBBX_Hp, 2,11,11,L0\|L1}, /* f5: 0111 0000 1111 0101 */
	1661	{&upd7810_device::SBBX_Dm, 2,11,11,L0\|L1}, /* f6: 0111 0000 1111 0110 */
	1662	{&upd7810_device::SBBX_Hm, 2,11,11,L0\|L1}, /* f7: 0111 0000 1111 0111 */
	1663	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f8: 0111 0000 1111 1000 */
	1664	{&upd7810_device::EQAX_B, 2,11,11,L0\|L1}, /* f9: 0111 0000 1111 1001 */
	1665	{&upd7810_device::EQAX_D, 2,11,11,L0\|L1}, /* fa: 0111 0000 1111 1010 */
	1666	{&upd7810_device::EQAX_H, 2,11,11,L0\|L1}, /* fb: 0111 0000 1111 1011 */
	1667	{&upd7810_device::EQAX_Dp, 2,11,11,L0\|L1}, /* fc: 0111 0000 1111 1100 */
	1668	{&upd7810_device::EQAX_Hp, 2,11,11,L0\|L1}, /* fd: 0111 0000 1111 1101 */
	1669	{&upd7810_device::EQAX_Dm, 2,11,11,L0\|L1}, /* fe: 0111 0000 1111 1110 */
	1670	{&upd7810_device::EQAX_Hm, 2,11,11,L0\|L1} /* ff: 0111 0000 1111 1111 */
	1671	};
	1672
	1673	/* prefix 74 */
	1674	const struct upd7810_device::opcode_s upd7810_device::s_op74[256] =
	1675	{
	1676	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 00: 0111 0100 0000 0000 */
	1677	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 01: 0111 0100 0000 0001 */
	1678	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 02: 0111 0100 0000 0010 */
	1679	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 03: 0111 0100 0000 0011 */
	1680	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 04: 0111 0100 0000 0100 */
	1681	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 05: 0111 0100 0000 0101 */
	1682	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 06: 0111 0100 0000 0110 */
	1683	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 07: 0111 0100 0000 0111 */
	1684	{&upd7810_device::ANI_V_xx, 3,11,11,L0\|L1}, /* 08: 0111 0100 0000 1000 xxxx xxxx */
	1685	{&upd7810_device::ANI_A_xx, 3,11,11,L0\|L1}, /* 09: 0111 0100 0000 1001 xxxx xxxx */
	1686	{&upd7810_device::ANI_B_xx, 3,11,11,L0\|L1}, /* 0a: 0111 0100 0000 1010 xxxx xxxx */
	1687	{&upd7810_device::ANI_C_xx, 3,11,11,L0\|L1}, /* 0b: 0111 0100 0000 1011 xxxx xxxx */
	1688	{&upd7810_device::ANI_D_xx, 3,11,11,L0\|L1}, /* 0c: 0111 0100 0000 1100 xxxx xxxx */
	1689	{&upd7810_device::ANI_E_xx, 3,11,11,L0\|L1}, /* 0d: 0111 0100 0000 1101 xxxx xxxx */
	1690	{&upd7810_device::ANI_H_xx, 3,11,11,L0\|L1}, /* 0e: 0111 0100 0000 1110 xxxx xxxx */
	1691	{&upd7810_device::ANI_L_xx, 3,11,11,L0\|L1}, /* 0f: 0111 0100 0000 1111 xxxx xxxx */
	1692
	1693	{&upd7810_device::XRI_V_xx, 3,11,11,L0\|L1}, /* 10: 0111 0100 0001 0000 xxxx xxxx */
	1694	{&upd7810_device::XRI_A_xx, 3,11,11,L0\|L1}, /* 11: 0111 0100 0001 0001 xxxx xxxx */
	1695	{&upd7810_device::XRI_B_xx, 3,11,11,L0\|L1}, /* 12: 0111 0100 0001 0010 xxxx xxxx */
	1696	{&upd7810_device::XRI_C_xx, 3,11,11,L0\|L1}, /* 13: 0111 0100 0001 0011 xxxx xxxx */
	1697	{&upd7810_device::XRI_D_xx, 3,11,11,L0\|L1}, /* 14: 0111 0100 0001 0100 xxxx xxxx */
	1698	{&upd7810_device::XRI_E_xx, 3,11,11,L0\|L1}, /* 15: 0111 0100 0001 0101 xxxx xxxx */
	1699	{&upd7810_device::XRI_H_xx, 3,11,11,L0\|L1}, /* 16: 0111 0100 0001 0110 xxxx xxxx */
	1700	{&upd7810_device::XRI_L_xx, 3,11,11,L0\|L1}, /* 17: 0111 0100 0001 0111 xxxx xxxx */
	1701	{&upd7810_device::ORI_V_xx, 3,11,11,L0\|L1}, /* 18: 0111 0100 0001 1000 xxxx xxxx */
	1702	{&upd7810_device::ORI_A_xx, 3,11,11,L0\|L1}, /* 19: 0111 0100 0001 1001 xxxx xxxx */
	1703	{&upd7810_device::ORI_B_xx, 3,11,11,L0\|L1}, /* 1a: 0111 0100 0001 1010 xxxx xxxx */
	1704	{&upd7810_device::ORI_C_xx, 3,11,11,L0\|L1}, /* 1b: 0111 0100 0001 1011 xxxx xxxx */
	1705	{&upd7810_device::ORI_D_xx, 3,11,11,L0\|L1}, /* 1c: 0111 0100 0001 1100 xxxx xxxx */
	1706	{&upd7810_device::ORI_E_xx, 3,11,11,L0\|L1}, /* 1d: 0111 0100 0001 1101 xxxx xxxx */
	1707	{&upd7810_device::ORI_H_xx, 3,11,11,L0\|L1}, /* 1e: 0111 0100 0001 1110 xxxx xxxx */
	1708	{&upd7810_device::ORI_L_xx, 3,11,11,L0\|L1}, /* 1f: 0111 0100 0001 1111 xxxx xxxx */
	1709
	1710	{&upd7810_device::ADINC_V_xx, 3,11,11,L0\|L1}, /* 20: 0111 0100 0010 0000 xxxx xxxx */
	1711	{&upd7810_device::ADINC_A_xx, 3,11,11,L0\|L1}, /* 21: 0111 0100 0010 0001 xxxx xxxx */
	1712	{&upd7810_device::ADINC_B_xx, 3,11,11,L0\|L1}, /* 22: 0111 0100 0010 0010 xxxx xxxx */
	1713	{&upd7810_device::ADINC_C_xx, 3,11,11,L0\|L1}, /* 23: 0111 0100 0010 0011 xxxx xxxx */
	1714	{&upd7810_device::ADINC_D_xx, 3,11,11,L0\|L1}, /* 24: 0111 0100 0010 0100 xxxx xxxx */
	1715	{&upd7810_device::ADINC_E_xx, 3,11,11,L0\|L1}, /* 25: 0111 0100 0010 0101 xxxx xxxx */
	1716	{&upd7810_device::ADINC_H_xx, 3,11,11,L0\|L1}, /* 26: 0111 0100 0010 0110 xxxx xxxx */
	1717	{&upd7810_device::ADINC_L_xx, 3,11,11,L0\|L1}, /* 27: 0111 0100 0010 0111 xxxx xxxx */
	1718	{&upd7810_device::GTI_V_xx, 3,11,11,L0\|L1}, /* 28: 0111 0100 0010 1000 xxxx xxxx */
	1719	{&upd7810_device::GTI_A_xx, 3,11,11,L0\|L1}, /* 29: 0111 0100 0010 1001 xxxx xxxx */
	1720	{&upd7810_device::GTI_B_xx, 3,11,11,L0\|L1}, /* 2a: 0111 0100 0010 1010 xxxx xxxx */
	1721	{&upd7810_device::GTI_C_xx, 3,11,11,L0\|L1}, /* 2b: 0111 0100 0010 1011 xxxx xxxx */
	1722	{&upd7810_device::GTI_D_xx, 3,11,11,L0\|L1}, /* 2c: 0111 0100 0010 1100 xxxx xxxx */
	1723	{&upd7810_device::GTI_E_xx, 3,11,11,L0\|L1}, /* 2d: 0111 0100 0010 1101 xxxx xxxx */
	1724	{&upd7810_device::GTI_H_xx, 3,11,11,L0\|L1}, /* 2e: 0111 0100 0010 1110 xxxx xxxx */
	1725	{&upd7810_device::GTI_L_xx, 3,11,11,L0\|L1}, /* 2f: 0111 0100 0010 1111 xxxx xxxx */
	1726
	1727	{&upd7810_device::SUINB_V_xx, 3,11,11,L0\|L1}, /* 30: 0111 0100 0011 0000 xxxx xxxx */
	1728	{&upd7810_device::SUINB_A_xx, 3,11,11,L0\|L1}, /* 31: 0111 0100 0011 0001 xxxx xxxx */
	1729	{&upd7810_device::SUINB_B_xx, 3,11,11,L0\|L1}, /* 32: 0111 0100 0011 0010 xxxx xxxx */
	1730	{&upd7810_device::SUINB_C_xx, 3,11,11,L0\|L1}, /* 33: 0111 0100 0011 0011 xxxx xxxx */
	1731	{&upd7810_device::SUINB_D_xx, 3,11,11,L0\|L1}, /* 34: 0111 0100 0011 0100 xxxx xxxx */
	1732	{&upd7810_device::SUINB_E_xx, 3,11,11,L0\|L1}, /* 35: 0111 0100 0011 0101 xxxx xxxx */
	1733	{&upd7810_device::SUINB_H_xx, 3,11,11,L0\|L1}, /* 36: 0111 0100 0011 0110 xxxx xxxx */
	1734	{&upd7810_device::SUINB_L_xx, 3,11,11,L0\|L1}, /* 37: 0111 0100 0011 0111 xxxx xxxx */
	1735	{&upd7810_device::LTI_V_xx, 3,11,11,L0\|L1}, /* 38: 0111 0100 0011 1000 xxxx xxxx */
	1736	{&upd7810_device::LTI_A_xx, 3,11,11,L0\|L1}, /* 39: 0111 0100 0011 1001 xxxx xxxx */
	1737	{&upd7810_device::LTI_B_xx, 3,11,11,L0\|L1}, /* 3a: 0111 0100 0011 1010 xxxx xxxx */
	1738	{&upd7810_device::LTI_C_xx, 3,11,11,L0\|L1}, /* 3b: 0111 0100 0011 1011 xxxx xxxx */
	1739	{&upd7810_device::LTI_D_xx, 3,11,11,L0\|L1}, /* 3c: 0111 0100 0011 1100 xxxx xxxx */
	1740	{&upd7810_device::LTI_E_xx, 3,11,11,L0\|L1}, /* 3d: 0111 0100 0011 1101 xxxx xxxx */
	1741	{&upd7810_device::LTI_H_xx, 3,11,11,L0\|L1}, /* 3e: 0111 0100 0011 1110 xxxx xxxx */
	1742	{&upd7810_device::LTI_L_xx, 3,11,11,L0\|L1}, /* 3f: 0111 0100 0011 1111 xxxx xxxx */
	1743
	1744	{&upd7810_device::ADI_V_xx, 3,11,11,L0\|L1}, /* 40: 0111 0100 0100 0000 xxxx xxxx */
	1745	{&upd7810_device::ADI_A_xx, 3,11,11,L0\|L1}, /* 41: 0111 0100 0100 0001 xxxx xxxx */
	1746	{&upd7810_device::ADI_B_xx, 3,11,11,L0\|L1}, /* 42: 0111 0100 0100 0010 xxxx xxxx */
	1747	{&upd7810_device::ADI_C_xx, 3,11,11,L0\|L1}, /* 43: 0111 0100 0100 0011 xxxx xxxx */
	1748	{&upd7810_device::ADI_D_xx, 3,11,11,L0\|L1}, /* 44: 0111 0100 0100 0100 xxxx xxxx */
	1749	{&upd7810_device::ADI_E_xx, 3,11,11,L0\|L1}, /* 45: 0111 0100 0100 0101 xxxx xxxx */
	1750	{&upd7810_device::ADI_H_xx, 3,11,11,L0\|L1}, /* 46: 0111 0100 0100 0110 xxxx xxxx */
	1751	{&upd7810_device::ADI_L_xx, 3,11,11,L0\|L1}, /* 47: 0111 0100 0100 0111 xxxx xxxx */
	1752	{&upd7810_device::ONI_V_xx, 3,11,11,L0\|L1}, /* 48: 0111 0100 0100 1000 xxxx xxxx */
	1753	{&upd7810_device::ONI_A_xx, 3,11,11,L0\|L1}, /* 49: 0111 0100 0100 1001 xxxx xxxx */
	1754	{&upd7810_device::ONI_B_xx, 3,11,11,L0\|L1}, /* 4a: 0111 0100 0100 1010 xxxx xxxx */
	1755	{&upd7810_device::ONI_C_xx, 3,11,11,L0\|L1}, /* 4b: 0111 0100 0100 1011 xxxx xxxx */
	1756	{&upd7810_device::ONI_D_xx, 3,11,11,L0\|L1}, /* 4c: 0111 0100 0100 1100 xxxx xxxx */
	1757	{&upd7810_device::ONI_E_xx, 3,11,11,L0\|L1}, /* 4d: 0111 0100 0100 1101 xxxx xxxx */
	1758	{&upd7810_device::ONI_H_xx, 3,11,11,L0\|L1}, /* 4e: 0111 0100 0100 1110 xxxx xxxx */
	1759	{&upd7810_device::ONI_L_xx, 3,11,11,L0\|L1}, /* 4f: 0111 0100 0100 1111 xxxx xxxx */
	1760
	1761	{&upd7810_device::ACI_V_xx, 3,11,11,L0\|L1}, /* 50: 0111 0100 0101 0000 xxxx xxxx */
	1762	{&upd7810_device::ACI_A_xx, 3,11,11,L0\|L1}, /* 51: 0111 0100 0101 0001 xxxx xxxx */
	1763	{&upd7810_device::ACI_B_xx, 3,11,11,L0\|L1}, /* 52: 0111 0100 0101 0010 xxxx xxxx */
	1764	{&upd7810_device::ACI_C_xx, 3,11,11,L0\|L1}, /* 53: 0111 0100 0101 0011 xxxx xxxx */
	1765	{&upd7810_device::ACI_D_xx, 3,11,11,L0\|L1}, /* 54: 0111 0100 0101 0100 xxxx xxxx */
	1766	{&upd7810_device::ACI_E_xx, 3,11,11,L0\|L1}, /* 55: 0111 0100 0101 0101 xxxx xxxx */
	1767	{&upd7810_device::ACI_H_xx, 3,11,11,L0\|L1}, /* 56: 0111 0100 0101 0110 xxxx xxxx */
	1768	{&upd7810_device::ACI_L_xx, 3,11,11,L0\|L1}, /* 57: 0111 0100 0101 0111 xxxx xxxx */
	1769	{&upd7810_device::OFFI_V_xx, 3,11,11,L0\|L1}, /* 58: 0111 0100 0101 1000 xxxx xxxx */
	1770	{&upd7810_device::OFFI_A_xx, 3,11,11,L0\|L1}, /* 59: 0111 0100 0101 1001 xxxx xxxx */
	1771	{&upd7810_device::OFFI_B_xx, 3,11,11,L0\|L1}, /* 5a: 0111 0100 0101 1010 xxxx xxxx */
	1772	{&upd7810_device::OFFI_C_xx, 3,11,11,L0\|L1}, /* 5b: 0111 0100 0101 1011 xxxx xxxx */
	1773	{&upd7810_device::OFFI_D_xx, 3,11,11,L0\|L1}, /* 5c: 0111 0100 0101 1100 xxxx xxxx */
	1774	{&upd7810_device::OFFI_E_xx, 3,11,11,L0\|L1}, /* 5d: 0111 0100 0101 1101 xxxx xxxx */
	1775	{&upd7810_device::OFFI_H_xx, 3,11,11,L0\|L1}, /* 5e: 0111 0100 0101 1110 xxxx xxxx */
	1776	{&upd7810_device::OFFI_L_xx, 3,11,11,L0\|L1}, /* 5f: 0111 0100 0101 1111 xxxx xxxx */
	1777
	1778	{&upd7810_device::SUI_V_xx, 3,11,11,L0\|L1}, /* 60: 0111 0100 0110 0000 xxxx xxxx */
	1779	{&upd7810_device::SUI_A_xx, 3,11,11,L0\|L1}, /* 61: 0111 0100 0110 0001 xxxx xxxx */
	1780	{&upd7810_device::SUI_B_xx, 3,11,11,L0\|L1}, /* 62: 0111 0100 0110 0010 xxxx xxxx */
	1781	{&upd7810_device::SUI_C_xx, 3,11,11,L0\|L1}, /* 63: 0111 0100 0110 0011 xxxx xxxx */
	1782	{&upd7810_device::SUI_D_xx, 3,11,11,L0\|L1}, /* 64: 0111 0100 0110 0100 xxxx xxxx */
	1783	{&upd7810_device::SUI_E_xx, 3,11,11,L0\|L1}, /* 65: 0111 0100 0110 0101 xxxx xxxx */
	1784	{&upd7810_device::SUI_H_xx, 3,11,11,L0\|L1}, /* 66: 0111 0100 0110 0110 xxxx xxxx */
	1785	{&upd7810_device::SUI_L_xx, 3,11,11,L0\|L1}, /* 67: 0111 0100 0110 0111 xxxx xxxx */
	1786	{&upd7810_device::NEI_V_xx, 3,11,11,L0\|L1}, /* 68: 0111 0100 0110 1000 xxxx xxxx */
	1787	{&upd7810_device::NEI_A_xx, 3,11,11,L0\|L1}, /* 69: 0111 0100 0110 1001 xxxx xxxx */
	1788	{&upd7810_device::NEI_B_xx, 3,11,11,L0\|L1}, /* 6a: 0111 0100 0110 1010 xxxx xxxx */
	1789	{&upd7810_device::NEI_C_xx, 3,11,11,L0\|L1}, /* 6b: 0111 0100 0110 1011 xxxx xxxx */
	1790	{&upd7810_device::NEI_D_xx, 3,11,11,L0\|L1}, /* 6c: 0111 0100 0110 1100 xxxx xxxx */
	1791	{&upd7810_device::NEI_E_xx, 3,11,11,L0\|L1}, /* 6d: 0111 0100 0110 1101 xxxx xxxx */
	1792	{&upd7810_device::NEI_H_xx, 3,11,11,L0\|L1}, /* 6e: 0111 0100 0110 1110 xxxx xxxx */
	1793	{&upd7810_device::NEI_L_xx, 3,11,11,L0\|L1}, /* 6f: 0111 0100 0110 1111 xxxx xxxx */
	1794
	1795	{&upd7810_device::SBI_V_xx, 3,11,11,L0\|L1}, /* 70: 0111 0100 0111 0000 xxxx xxxx */
	1796	{&upd7810_device::SBI_A_xx, 3,11,11,L0\|L1}, /* 71: 0111 0100 0111 0001 xxxx xxxx */
	1797	{&upd7810_device::SBI_B_xx, 3,11,11,L0\|L1}, /* 72: 0111 0100 0111 0010 xxxx xxxx */
	1798	{&upd7810_device::SBI_C_xx, 3,11,11,L0\|L1}, /* 73: 0111 0100 0111 0011 xxxx xxxx */
	1799	{&upd7810_device::SBI_D_xx, 3,11,11,L0\|L1}, /* 74: 0111 0100 0111 0100 xxxx xxxx */
	1800	{&upd7810_device::SBI_E_xx, 3,11,11,L0\|L1}, /* 75: 0111 0100 0111 0101 xxxx xxxx */
	1801	{&upd7810_device::SBI_H_xx, 3,11,11,L0\|L1}, /* 76: 0111 0100 0111 0110 xxxx xxxx */
	1802	{&upd7810_device::SBI_L_xx, 3,11,11,L0\|L1}, /* 77: 0111 0100 0111 0111 xxxx xxxx */
	1803	{&upd7810_device::EQI_V_xx, 3,11,11,L0\|L1}, /* 78: 0111 0100 0111 1000 xxxx xxxx */
	1804	{&upd7810_device::EQI_A_xx, 3,11,11,L0\|L1}, /* 79: 0111 0100 0111 1001 xxxx xxxx */
	1805	{&upd7810_device::EQI_B_xx, 3,11,11,L0\|L1}, /* 7a: 0111 0100 0111 1010 xxxx xxxx */
	1806	{&upd7810_device::EQI_C_xx, 3,11,11,L0\|L1}, /* 7b: 0111 0100 0111 1011 xxxx xxxx */
	1807	{&upd7810_device::EQI_D_xx, 3,11,11,L0\|L1}, /* 7c: 0111 0100 0111 1100 xxxx xxxx */
	1808	{&upd7810_device::EQI_E_xx, 3,11,11,L0\|L1}, /* 7d: 0111 0100 0111 1101 xxxx xxxx */
	1809	{&upd7810_device::EQI_H_xx, 3,11,11,L0\|L1}, /* 7e: 0111 0100 0111 1110 xxxx xxxx */
	1810	{&upd7810_device::EQI_L_xx, 3,11,11,L0\|L1}, /* 7f: 0111 0100 0111 1111 xxxx xxxx */
	1811
	1812	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 80: 0111 0100 1000 0000 */
	1813	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 81: 0111 0100 1000 0001 */
	1814	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 82: 0111 0100 1000 0010 */
	1815	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 83: 0111 0100 1000 0011 */
	1816	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 84: 0111 0100 1000 0100 */
	1817	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 85: 0111 0100 1000 0101 */
	1818	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 86: 0111 0100 1000 0110 */
	1819	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 87: 0111 0100 1000 0111 */
	1820	{&upd7810_device::ANAW_wa, 3,14,11,L0\|L1}, /* 88: 0111 0100 1000 1000 oooo oooo */
	1821	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 89: 0111 0100 1000 1001 */
	1822	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8a: 0111 0100 1000 1010 */
	1823	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8b: 0111 0100 1000 1011 */
	1824	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 8c: 0111 0100 1000 1100 */
	1825	{&upd7810_device::DAN_EA_BC, 2,11,11,L0\|L1}, /* 8d: 0111 0100 1000 1101 */
	1826	{&upd7810_device::DAN_EA_DE, 2,11,11,L0\|L1}, /* 8e: 0111 0100 1000 1110 */
	1827	{&upd7810_device::DAN_EA_HL, 2,11,11,L0\|L1}, /* 8f: 0111 0100 1000 1111 */
	1828
	1829	{&upd7810_device::XRAW_wa, 3,14,11,L0\|L1}, /* 90: 0111 0100 1001 0000 oooo oooo */
	1830	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 91: 0111 0100 1001 0001 */
	1831	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 92: 0111 0100 1001 0010 */
	1832	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 93: 0111 0100 1001 0011 */
	1833	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 94: 0111 0100 1001 0100 */
	1834	{&upd7810_device::DXR_EA_BC, 2,11,11,L0\|L1}, /* 95: 0111 0100 1001 0101 */
	1835	{&upd7810_device::DXR_EA_DE, 2,11,11,L0\|L1}, /* 96: 0111 0100 1001 0110 */
	1836	{&upd7810_device::DXR_EA_HL, 2,11,11,L0\|L1}, /* 97: 0111 0100 1001 0111 */
	1837	{&upd7810_device::ORAW_wa, 3,14,11,L0\|L1}, /* 98: 0111 0100 1001 1000 oooo oooo */
	1838	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 99: 0111 0100 1001 1001 */
	1839	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9a: 0111 0100 1001 1010 */
	1840	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9b: 0111 0100 1001 1011 */
	1841	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* 9c: 0111 0100 1001 1100 */
	1842	{&upd7810_device::DOR_EA_BC, 2,11,11,L0\|L1}, /* 9d: 0111 0100 1001 1101 */
	1843	{&upd7810_device::DOR_EA_DE, 2,11,11,L0\|L1}, /* 9e: 0111 0100 1001 1110 */
	1844	{&upd7810_device::DOR_EA_HL, 2,11,11,L0\|L1}, /* 9f: 0111 0100 1001 1111 */
	1845
	1846	{&upd7810_device::ADDNCW_wa, 3,14,11,L0\|L1}, /* a0: 0111 0100 1010 0000 oooo oooo */
	1847	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a1: 0111 0100 1010 0001 */
	1848	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a2: 0111 0100 1010 0010 */
	1849	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a3: 0111 0100 1010 0011 */
	1850	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a4: 0111 0100 1010 0100 */
	1851	{&upd7810_device::DADDNC_EA_BC, 2,11,11,L0\|L1}, /* a5: 0111 0100 1010 0101 */
	1852	{&upd7810_device::DADDNC_EA_DE, 2,11,11,L0\|L1}, /* a6: 0111 0100 1010 0110 */
	1853	{&upd7810_device::DADDNC_EA_HL, 2,11,11,L0\|L1}, /* a7: 0111 0100 1010 0111 */
	1854	{&upd7810_device::GTAW_wa, 3,14,11,L0\|L1}, /* a8: 0111 0100 1010 1000 oooo oooo */
	1855	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* a9: 0111 0100 1010 1001 */
	1856	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* aa: 0111 0100 1010 1010 */
	1857	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ab: 0111 0100 1010 1011 */
	1858	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ac: 0111 0100 1010 1100 */
	1859	{&upd7810_device::DGT_EA_BC, 2,11,11,L0\|L1}, /* ad: 0111 0100 1010 1101 */
	1860	{&upd7810_device::DGT_EA_DE, 2,11,11,L0\|L1}, /* ae: 0111 0100 1010 1110 */
	1861	{&upd7810_device::DGT_EA_HL, 2,11,11,L0\|L1}, /* af: 0111 0100 1010 1111 */
	1862
	1863	{&upd7810_device::SUBNBW_wa, 3,14,11,L0\|L1}, /* b0: 0111 0100 1011 0000 oooo oooo */
	1864	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b1: 0111 0100 1011 0001 */
	1865	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b2: 0111 0100 1011 0010 */
	1866	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b3: 0111 0100 1011 0011 */
	1867	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b4: 0111 0100 1011 0100 */
	1868	{&upd7810_device::DSUBNB_EA_BC, 2,11,11,L0\|L1}, /* b5: 0111 0100 1011 0101 */
	1869	{&upd7810_device::DSUBNB_EA_DE, 2,11,11,L0\|L1}, /* b6: 0111 0100 1011 0110 */
	1870	{&upd7810_device::DSUBNB_EA_HL, 2,11,11,L0\|L1}, /* b7: 0111 0100 1011 0111 */
	1871	{&upd7810_device::LTAW_wa, 3,14,11,L0\|L1}, /* b8: 0111 0100 1011 1000 oooo oooo */
	1872	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* b9: 0111 0100 1011 1001 */
	1873	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ba: 0111 0100 1011 1010 */
	1874	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bb: 0111 0100 1011 1011 */
	1875	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* bc: 0111 0100 1011 1100 */
	1876	{&upd7810_device::DLT_EA_BC, 2,11,11,L0\|L1}, /* bd: 0111 0100 1011 1101 */
	1877	{&upd7810_device::DLT_EA_DE, 2,11,11,L0\|L1}, /* be: 0111 0100 1011 1110 */
	1878	{&upd7810_device::DLT_EA_HL, 2,11,11,L0\|L1}, /* bf: 0111 0100 1011 1111 */
	1879
	1880	{&upd7810_device::ADDW_wa, 3,14,11,L0\|L1}, /* c0: 0111 0100 1100 0000 oooo oooo */
	1881	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c1: 0111 0100 1100 0001 */
	1882	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c2: 0111 0100 1100 0010 */
	1883	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c3: 0111 0100 1100 0011 */
	1884	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c4: 0111 0100 1100 0100 */
	1885	{&upd7810_device::DADD_EA_BC, 2,11,11,L0\|L1}, /* c5: 0111 0100 1100 0101 */
	1886	{&upd7810_device::DADD_EA_DE, 2,11,11,L0\|L1}, /* c6: 0111 0100 1100 0110 */
	1887	{&upd7810_device::DADD_EA_HL, 2,11,11,L0\|L1}, /* c7: 0111 0100 1100 0111 */
	1888	{&upd7810_device::ONAW_wa, 3,14,11,L0\|L1}, /* c8: 0111 0100 1100 1000 oooo oooo */
	1889	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* c9: 0111 0100 1100 1001 */
	1890	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ca: 0111 0100 1100 1010 */
	1891	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* cb: 0111 0100 1100 1011 */
	1892	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* cc: 0111 0100 1100 1100 */
	1893	{&upd7810_device::DON_EA_BC, 2,11,11,L0\|L1}, /* cd: 0111 0100 1100 1101 */
	1894	{&upd7810_device::DON_EA_DE, 2,11,11,L0\|L1}, /* ce: 0111 0100 1100 1110 */
	1895	{&upd7810_device::DON_EA_HL, 2,11,11,L0\|L1}, /* cf: 0111 0100 1100 1111 */
	1896
	1897	{&upd7810_device::ADCW_wa, 3,14,11,L0\|L1}, /* d0: 0111 0100 1101 0000 oooo oooo */
	1898	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d1: 0111 0100 1101 0001 */
	1899	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d2: 0111 0100 1101 0010 */
	1900	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d3: 0111 0100 1101 0011 */
	1901	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d4: 0111 0100 1101 0100 */
	1902	{&upd7810_device::DADC_EA_BC, 2,11,11,L0\|L1}, /* d5: 0111 0100 1101 0101 */
	1903	{&upd7810_device::DADC_EA_DE, 2,11,11,L0\|L1}, /* d6: 0111 0100 1101 0110 */
	1904	{&upd7810_device::DADC_EA_HL, 2,11,11,L0\|L1}, /* d7: 0111 0100 1101 0111 */
	1905	{&upd7810_device::OFFAW_wa, 3,14,11,L0\|L1}, /* d8: 0111 0100 1101 1000 oooo oooo */
	1906	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* d9: 0111 0100 1101 1001 */
	1907	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* da: 0111 0100 1101 1010 */
	1908	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* db: 0111 0100 1101 1011 */
	1909	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* dc: 0111 0100 1101 1100 */
	1910	{&upd7810_device::DOFF_EA_BC, 2,11,11,L0\|L1}, /* dd: 0111 0100 1101 1101 */
	1911	{&upd7810_device::DOFF_EA_DE, 2,11,11,L0\|L1}, /* de: 0111 0100 1101 1110 */
	1912	{&upd7810_device::DOFF_EA_HL, 2,11,11,L0\|L1}, /* df: 0111 0100 1101 1111 */
	1913
	1914	{&upd7810_device::SUBW_wa, 3,14,11,L0\|L1}, /* e0: 0111 0100 1110 0000 oooo oooo */
	1915	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e1: 0111 0100 1110 0001 */
	1916	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e2: 0111 0100 1110 0010 */
	1917	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e3: 0111 0100 1110 0011 */
	1918	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e4: 0111 0100 1110 0100 */
	1919	{&upd7810_device::DSUB_EA_BC, 2,11,11,L0\|L1}, /* e5: 0111 0100 1110 0101 */
	1920	{&upd7810_device::DSUB_EA_DE, 2,11,11,L0\|L1}, /* e6: 0111 0100 1110 0110 */
	1921	{&upd7810_device::DSUB_EA_HL, 2,11,11,L0\|L1}, /* e7: 0111 0100 1110 0111 */
	1922	{&upd7810_device::NEAW_wa, 3,14,11,L0\|L1}, /* e8: 0111 0100 1110 1000 oooo oooo */
	1923	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* e9: 0111 0100 1110 1001 */
	1924	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ea: 0111 0100 1110 1010 */
	1925	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* eb: 0111 0100 1110 1011 */
	1926	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* ec: 0111 0100 1110 1100 */
	1927	{&upd7810_device::DNE_EA_BC, 2,11,11,L0\|L1}, /* ed: 0111 0100 1110 1101 */
	1928	{&upd7810_device::DNE_EA_DE, 2,11,11,L0\|L1}, /* ee: 0111 0100 1110 1110 */
	1929	{&upd7810_device::DNE_EA_HL, 2,11,11,L0\|L1}, /* ef: 0111 0100 1110 1111 */
	1930
	1931	{&upd7810_device::SBBW_wa, 3,14,11,L0\|L1}, /* f0: 0111 0100 1111 0000 oooo oooo */
	1932	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f1: 0111 0100 1111 0001 */
	1933	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f2: 0111 0100 1111 0010 */
	1934	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f3: 0111 0100 1111 0011 */
	1935	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f4: 0111 0100 1111 0100 */
	1936	{&upd7810_device::DSBB_EA_BC, 2,11,11,L0\|L1}, /* f5: 0111 0100 1111 0101 */
	1937	{&upd7810_device::DSBB_EA_DE, 2,11,11,L0\|L1}, /* f6: 0111 0100 1111 0110 */
	1938	{&upd7810_device::DSBB_EA_HL, 2,11,11,L0\|L1}, /* f7: 0111 0100 1111 0111 */
	1939	{&upd7810_device::EQAW_wa, 3,14,11,L0\|L1}, /* f8: 0111 0100 1111 1000 oooo oooo */
	1940	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* f9: 0111 0100 1111 1001 */
	1941	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* fa: 0111 0100 1111 1010 */
	1942	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* fb: 0111 0100 1111 1011 */
	1943	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, /* fc: 0111 0100 1111 1100 */
	1944	{&upd7810_device::DEQ_EA_BC, 2,11,11,L0\|L1}, /* fd: 0111 0100 1111 1101 */
	1945	{&upd7810_device::DEQ_EA_DE, 2,11,11,L0\|L1}, /* fe: 0111 0100 1111 1110 */
	1946	{&upd7810_device::DEQ_EA_HL, 2,11,11,L0\|L1} /* ff: 0111 0100 1111 1111 */
	1947	};
	1948
	1949	/* main opcodes */
	1950	const struct upd7810_device::opcode_s upd7810_device::s_opXX_7810[256] =
	1951	{
	1952	{&upd7810_device::NOP, 1, 4, 4,L0\|L1}, /* 00: 0000 0000 */
	1953	{&upd7810_device::LDAW_wa, 2,10,10,L0\|L1}, /* 01: 0000 0001 oooo oooo */
	1954	{&upd7810_device::INX_SP, 1, 7, 7,L0\|L1}, /* 02: 0000 0010 */
	1955	{&upd7810_device::DCX_SP, 1, 7, 7,L0\|L1}, /* 03: 0000 0011 */
	1956	{&upd7810_device::LXI_S_w, 3,10,10,L0\|L1}, /* 04: 0000 0100 llll llll hhhh hhhh */
	1957	{&upd7810_device::ANIW_wa_xx, 3,19,19,L0\|L1}, /* 05: 0000 0101 oooo oooo xxxx xxxx */
	1958	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, /* 06: */
	1959	{&upd7810_device::ANI_A_xx, 2, 7, 7,L0\|L1}, /* 07: 0000 0111 xxxx xxxx */
	1960	{&upd7810_device::MOV_A_EAH, 1, 4, 4,L0\|L1}, /* 08: 0000 1000 */
	1961	{&upd7810_device::MOV_A_EAL, 1, 4, 4,L0\|L1}, /* 09: 0000 1001 */
	1962	{&upd7810_device::MOV_A_B, 1, 4, 4,L0\|L1}, /* 0a: 0000 1010 */
	1963	{&upd7810_device::MOV_A_C, 1, 4, 4,L0\|L1}, /* 0b: 0000 1011 */
	1964	{&upd7810_device::MOV_A_D, 1, 4, 4,L0\|L1}, /* 0c: 0000 1100 */
	1965	{&upd7810_device::MOV_A_E, 1, 4, 4,L0\|L1}, /* 0d: 0000 1101 */
	1966	{&upd7810_device::MOV_A_H, 1, 4, 4,L0\|L1}, /* 0e: 0000 1110 */
	1967	{&upd7810_device::MOV_A_L, 1, 4, 4,L0\|L1}, /* 0f: 0000 1111 */
	1968
	1969	{&upd7810_device::EXA, 1, 4, 4,L0\|L1}, /* 10: 0001 0000 */
	1970	{&upd7810_device::EXX, 1, 4, 4,L0\|L1}, /* 11: 0001 0001 */
	1971	{&upd7810_device::INX_BC, 1, 7, 7,L0\|L1}, /* 12: 0001 0010 */
	1972	{&upd7810_device::DCX_BC, 1, 7, 7,L0\|L1}, /* 13: 0001 0011 */
	1973	{&upd7810_device::LXI_B_w, 3,10,10,L0\|L1}, /* 14: 0001 0100 llll llll hhhh hhhh */
	1974	{&upd7810_device::ORIW_wa_xx, 3,19,19,L0\|L1}, /* 15: 0001 0101 oooo oooo xxxx xxxx */
	1975	{&upd7810_device::XRI_A_xx, 2, 7, 7,L0\|L1}, /* 16: 0001 0110 xxxx xxxx */
	1976	{&upd7810_device::ORI_A_xx, 2, 7, 7,L0\|L1}, /* 17: 0001 0111 xxxx xxxx */
	1977	{&upd7810_device::MOV_EAH_A, 1, 4, 4,L0\|L1}, /* 18: 0001 1000 */
	1978	{&upd7810_device::MOV_EAL_A, 1, 4, 4,L0\|L1}, /* 19: 0001 1001 */
	1979	{&upd7810_device::MOV_B_A, 1, 4, 4,L0\|L1}, /* 1a: 0001 1010 */
	1980	{&upd7810_device::MOV_C_A, 1, 4, 4,L0\|L1}, /* 1b: 0001 1011 */
	1981	{&upd7810_device::MOV_D_A, 1, 4, 4,L0\|L1}, /* 1c: 0001 1100 */
	1982	{&upd7810_device::MOV_E_A, 1, 4, 4,L0\|L1}, /* 1d: 0001 1101 */
	1983	{&upd7810_device::MOV_H_A, 1, 4, 4,L0\|L1}, /* 1e: 0001 1110 */
	1984	{&upd7810_device::MOV_L_A, 1, 4, 4,L0\|L1}, /* 1f: 0001 1111 */
	1985
	1986	{&upd7810_device::INRW_wa, 2,16,16,L0\|L1}, /* 20: 0010 0000 oooo oooo */
	1987	{&upd7810_device::JB, 1, 4, 4,L0\|L1}, /* 21: 0010 0001 */
	1988	{&upd7810_device::INX_DE, 1, 7, 7,L0\|L1}, /* 22: 0010 0010 */
	1989	{&upd7810_device::DCX_DE, 1, 7, 7,L0\|L1}, /* 23: 0010 0011 */
	1990	{&upd7810_device::LXI_D_w, 3,10,10,L0\|L1}, /* 24: 0010 0100 llll llll hhhh hhhh */
	1991	{&upd7810_device::GTIW_wa_xx, 3,19,19,L0\|L1}, /* 25: 0010 0101 oooo oooo xxxx xxxx */
	1992	{&upd7810_device::ADINC_A_xx, 2, 7, 7,L0\|L1}, /* 26: 0010 0110 xxxx xxxx */
	1993	{&upd7810_device::GTI_A_xx, 2, 7, 7,L0\|L1}, /* 27: 0010 0111 xxxx xxxx */
	1994	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, /* 28: */
	1995	{&upd7810_device::LDAX_B, 2, 7, 7,L0\|L1}, /* 29: 0010 1001 dddd dddd */
	1996	{&upd7810_device::LDAX_D, 2, 7, 7,L0\|L1}, /* 2a: 0010 1010 dddd dddd */
	1997	{&upd7810_device::LDAX_H, 2, 7, 7,L0\|L1}, /* 2b: 0010 1011 dddd dddd */
	1998	{&upd7810_device::LDAX_Dp, 2, 7, 7,L0\|L1}, /* 2c: 0010 1100 dddd dddd */
	1999	{&upd7810_device::LDAX_Hp, 2, 7, 7,L0\|L1}, /* 2d: 0010 1101 dddd dddd */
	2000	{&upd7810_device::LDAX_Dm, 2, 7, 7,L0\|L1}, /* 2e: 0010 1110 dddd dddd */
	2001	{&upd7810_device::LDAX_Hm, 2, 7, 7,L0\|L1}, /* 2f: 0010 1111 dddd dddd */
	2002
	2003	{&upd7810_device::DCRW_wa, 2,16,16,L0\|L1}, /* 30: 0011 0000 oooo oooo */
	2004	{&upd7810_device::BLOCK, 1,13,13,L0\|L1}, /* 31: 0011 0001 / / 7810 */
	2005	{&upd7810_device::INX_HL, 1, 7, 7,L0\|L1}, /* 32: 0011 0010 */
	2006	{&upd7810_device::DCX_HL, 1, 7, 7,L0\|L1}, /* 33: 0011 0011 */
	2007	{&upd7810_device::LXI_H_w, 3,10,10, L1}, /* 34: 0011 0100 llll llll hhhh hhhh */
	2008	{&upd7810_device::LTIW_wa_xx, 3,19,19,L0\|L1}, /* 35: 0011 0101 oooo oooo xxxx xxxx */
	2009	{&upd7810_device::SUINB_A_xx, 2, 7, 7,L0\|L1}, /* 36: 0011 0110 xxxx xxxx */
	2010	{&upd7810_device::LTI_A_xx, 2, 7, 7,L0\|L1}, /* 37: 0011 0111 xxxx xxxx */
	2011	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, /* 38: */
	2012	{&upd7810_device::STAX_B, 2, 7, 7,L0\|L1}, /* 39: 0011 1001 dddd dddd */
	2013	{&upd7810_device::STAX_D, 2, 7, 7,L0\|L1}, /* 3a: 0011 1010 dddd dddd */
	2014	{&upd7810_device::STAX_H, 2, 7, 7,L0\|L1}, /* 3b: 0011 1011 dddd dddd */
	2015	{&upd7810_device::STAX_Dp, 2, 7, 7,L0\|L1}, /* 3c: 0011 1100 dddd dddd */
	2016	{&upd7810_device::STAX_Hp, 2, 7, 7,L0\|L1}, /* 3d: 0011 1101 dddd dddd */
	2017	{&upd7810_device::STAX_Dm, 2, 7, 7,L0\|L1}, /* 3e: 0011 1110 dddd dddd */
	2018	{&upd7810_device::STAX_Hm, 2, 7, 7,L0\|L1}, /* 3f: 0011 1111 dddd dddd */
	2019
	2020	{&upd7810_device::CALL_w, 3,16,16,L0\|L1}, /* 40: 0100 0000 llll llll hhhh hhhh */
	2021	{&upd7810_device::INR_A, 1, 4, 4,L0\|L1}, /* 41: 0100 0001 */
	2022	{&upd7810_device::INR_B, 1, 4, 4,L0\|L1}, /* 42: 0100 0010 */
	2023	{&upd7810_device::INR_C, 1, 4, 4,L0\|L1}, /* 43: 0100 0011 */
	2024	{&upd7810_device::LXI_EA_s, 3,10,10,L0\|L1}, /* 44: 0100 0100 llll llll hhhh hhhh */
	2025	{&upd7810_device::ONIW_wa_xx, 3,19,19,L0\|L1}, /* 45: 0100 0101 oooo oooo xxxx xxxx */
	2026	{&upd7810_device::ADI_A_xx, 2, 7, 7,L0\|L1}, /* 46: 0100 0110 xxxx xxxx */
	2027	{&upd7810_device::ONI_A_xx, 2, 7, 7,L0\|L1}, /* 47: 0100 0111 xxxx xxxx */
	2028	{&upd7810_device::PRE_48, 1, 0, 0,L0\|L1}, /* 48: prefix */
	2029	{&upd7810_device::MVIX_BC_xx, 2,10,10,L0\|L1}, /* 49: 0100 1001 xxxx xxxx */
	2030	{&upd7810_device::MVIX_DE_xx, 2,10,10,L0\|L1}, /* 4a: 0100 1010 xxxx xxxx */
	2031	{&upd7810_device::MVIX_HL_xx, 2,10,10,L0\|L1}, /* 4b: 0100 1011 xxxx xxxx */
	2032	{&upd7810_device::PRE_4C, 1, 0, 0,L0\|L1}, /* 4c: prefix */
	2033	{&upd7810_device::PRE_4D, 1, 4, 4,L0\|L1}, /* 4d: prefix */
	2034	{&upd7810_device::JRE, 2,10,10,L0\|L1}, /* 4e: 0100 111d dddd dddd */
	2035	{&upd7810_device::JRE, 2,10,10,L0\|L1}, /* 4f: 0100 111d dddd dddd */
	2036
	2037	{&upd7810_device::EXH, 1, 4, 4,L0\|L1}, /* 50: 0101 0000 / / 7810 */
	2038	{&upd7810_device::DCR_A, 1, 4, 4,L0\|L1}, /* 51: 0101 0001 */
	2039	{&upd7810_device::DCR_B, 1, 4, 4,L0\|L1}, /* 52: 0101 0010 */
	2040	{&upd7810_device::DCR_C, 1, 4, 4,L0\|L1}, /* 53: 0101 0011 */
	2041	{&upd7810_device::JMP_w, 3,10,10,L0\|L1}, /* 54: 0101 0100 llll llll hhhh hhhh */
	2042	{&upd7810_device::OFFIW_wa_xx, 3,19,19,L0\|L1}, /* 55: 0101 0101 oooo oooo xxxx xxxx */
	2043	{&upd7810_device::ACI_A_xx, 2, 7, 7,L0\|L1}, /* 56: 0101 0110 xxxx xxxx */
	2044	{&upd7810_device::OFFI_A_xx, 2, 7, 7,L0\|L1}, /* 57: 0101 0111 xxxx xxxx */
	2045	{&upd7810_device::BIT_0_wa, 2,10,10,L0\|L1}, /* 58: 0101 1000 oooo oooo / / 7810 */
	2046	{&upd7810_device::BIT_1_wa, 2,10,10,L0\|L1}, /* 59: 0101 1001 oooo oooo / / 7810 */
	2047	{&upd7810_device::BIT_2_wa, 2,10,10,L0\|L1}, /* 5a: 0101 1010 oooo oooo / / 7810 */
	2048	{&upd7810_device::BIT_3_wa, 2,10,10,L0\|L1}, /* 5b: 0101 1011 oooo oooo / / 7810 */
	2049	{&upd7810_device::BIT_4_wa, 2,10,10,L0\|L1}, /* 5c: 0101 1100 oooo oooo / / 7810 */
	2050	{&upd7810_device::BIT_5_wa, 2,10,10,L0\|L1}, /* 5d: 0101 1101 oooo oooo / / 7810 */
	2051	{&upd7810_device::BIT_6_wa, 2,10,10,L0\|L1}, /* 5e: 0101 1110 oooo oooo / / 7810 */
	2052	{&upd7810_device::BIT_7_wa, 2,10,10,L0\|L1}, /* 5f: 0101 1111 oooo oooo / / 7810 */
	2053
	2054	{&upd7810_device::PRE_60, 1, 0, 0,L0\|L1}, /* 60: */
	2055	{&upd7810_device::DAA, 1, 4, 4,L0\|L1}, /* 61: 0110 0001 */
	2056	{&upd7810_device::RETI, 1,13,13,L0\|L1}, /* 62: 0110 0010 */
	2057	{&upd7810_device::STAW_wa, 2,10,10,L0\|L1}, /* 63: 0110 0011 oooo oooo */
	2058	{&upd7810_device::PRE_64, 1, 0, 0,L0\|L1}, /* 64: */
	2059	{&upd7810_device::NEIW_wa_xx, 3,19,19,L0\|L1}, /* 65: 0110 0101 oooo oooo xxxx xxxx */
	2060	{&upd7810_device::SUI_A_xx, 2, 7, 7,L0\|L1}, /* 66: 0110 0110 xxxx xxxx */
	2061	{&upd7810_device::NEI_A_xx, 2, 7, 7,L0\|L1}, /* 67: 0110 0111 xxxx xxxx */
	2062	{&upd7810_device::MVI_V_xx, 2, 7, 7,L0\|L1}, /* 68: 0110 1000 xxxx xxxx */
	2063	{&upd7810_device::MVI_A_xx, 2, 7, 7,L0 }, /* 69: 0110 1001 xxxx xxxx */
	2064	{&upd7810_device::MVI_B_xx, 2, 7, 7,L0\|L1}, /* 6a: 0110 1010 xxxx xxxx */
	2065	{&upd7810_device::MVI_C_xx, 2, 7, 7,L0\|L1}, /* 6b: 0110 1011 xxxx xxxx */
	2066	{&upd7810_device::MVI_D_xx, 2, 7, 7,L0\|L1}, /* 6c: 0110 1100 xxxx xxxx */
	2067	{&upd7810_device::MVI_E_xx, 2, 7, 7,L0\|L1}, /* 6d: 0110 1101 xxxx xxxx */
	2068	{&upd7810_device::MVI_H_xx, 2, 7, 7,L0\|L1}, /* 6e: 0110 1110 xxxx xxxx */
	2069	{&upd7810_device::MVI_L_xx, 2, 7, 7, L1}, /* 6f: 0110 1111 xxxx xxxx */
	2070
	2071	{&upd7810_device::PRE_70, 1, 0, 0,L0\|L1}, /* 70: */
	2072	{&upd7810_device::MVIW_wa_xx, 3,13,13,L0\|L1}, /* 71: 0111 0001 oooo oooo xxxx xxxx */
	2073	{&upd7810_device::SOFTI, 1,16,16,L0\|L1}, /* 72: 0111 0010 */
	2074	{&upd7810_device::illegal, 1, 0, 0,L0\|L1}, /* 73: */
	2075	{&upd7810_device::PRE_74, 1, 0, 0,L0\|L1}, /* 74: prefix */
	2076	{&upd7810_device::EQIW_wa_xx, 3,19,19,L0\|L1}, /* 75: 0111 0101 oooo oooo xxxx xxxx */
	2077	{&upd7810_device::SBI_A_xx, 2, 7, 7,L0\|L1}, /* 76: 0111 0110 xxxx xxxx */
	2078	{&upd7810_device::EQI_A_xx, 2, 7, 7,L0\|L1}, /* 77: 0111 0111 xxxx xxxx */
	2079	{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 78: 0111 1xxx xxxx xxxx */
	2080	{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 79: 0111 1xxx xxxx xxxx */
	2081	{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7a: 0111 1xxx xxxx xxxx */
	2082	{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7b: 0111 1xxx xxxx xxxx */
	2083	{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7c: 0111 1xxx xxxx xxxx */
	2084	{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7d: 0111 1xxx xxxx xxxx */
	2085	{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7e: 0111 1xxx xxxx xxxx */
	2086	{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7f: 0111 1xxx xxxx xxxx */
	2087
	2088	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 80: 100x xxxx */
	2089	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 81: 100x xxxx */
	2090	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 82: 100x xxxx */
	2091	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 83: 100x xxxx */
	2092	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 84: 100x xxxx */
	2093	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 85: 100x xxxx */
	2094	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 86: 100x xxxx */
	2095	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 87: 100x xxxx */
	2096	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 88: 100x xxxx */
	2097	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 89: 100x xxxx */
	2098	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8a: 100x xxxx */
	2099	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8b: 100x xxxx */
	2100	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8c: 100x xxxx */
	2101	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8d: 100x xxxx */
	2102	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8e: 100x xxxx */
	2103	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8f: 100x xxxx */
	2104
	2105	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 90: 100x xxxx */
	2106	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 91: 100x xxxx */
	2107	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 92: 100x xxxx */
	2108	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 93: 100x xxxx */
	2109	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 94: 100x xxxx */
	2110	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 95: 100x xxxx */
	2111	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 96: 100x xxxx */
	2112	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 97: 100x xxxx */
	2113	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 98: 100x xxxx */
	2114	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 99: 100x xxxx */
	2115	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9a: 100x xxxx */
	2116	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9b: 100x xxxx */
	2117	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9c: 100x xxxx */
	2118	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9d: 100x xxxx */
	2119	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9e: 100x xxxx */
	2120	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9f: 100x xxxx */
	2121
	2122	{&upd7810_device::POP_VA, 1,10,10,L0\|L1}, /* a0: 1010 0000 */
	2123	{&upd7810_device::POP_BC, 1,10,10,L0\|L1}, /* a1: 1010 0001 */
	2124	{&upd7810_device::POP_DE, 1,10,10,L0\|L1}, /* a2: 1010 0010 */
	2125	{&upd7810_device::POP_HL, 1,10,10,L0\|L1}, /* a3: 1010 0011 */
	2126	{&upd7810_device::POP_EA, 1,10,10,L0\|L1}, /* a4: 1010 0100 */
	2127	{&upd7810_device::DMOV_EA_BC, 1, 4, 4,L0\|L1}, /* a5: 1010 0101 */
	2128	{&upd7810_device::DMOV_EA_DE, 1, 4, 4,L0\|L1}, /* a6: 1010 0110 */
	2129	{&upd7810_device::DMOV_EA_HL, 1, 4, 4,L0\|L1}, /* a7: 1010 0111 */
	2130	{&upd7810_device::INX_EA, 1, 7, 7,L0\|L1}, /* a8: 1010 1000 */
	2131	{&upd7810_device::DCX_EA, 1, 7, 7,L0\|L1}, /* a9: 1010 1001 */
	2132	{&upd7810_device::EI, 1, 4, 4,L0\|L1}, /* aa: 1010 1010 */
	2133	{&upd7810_device::LDAX_D_xx, 2, 7, 7,L0\|L1}, /* ab: 1010 1011 dddd dddd */
	2134	{&upd7810_device::LDAX_H_A, 1, 7, 7,L0\|L1}, /* ac: 1010 1100 */
	2135	{&upd7810_device::LDAX_H_B, 1, 7, 7,L0\|L1}, /* ad: 1010 1101 */
	2136	{&upd7810_device::LDAX_H_EA, 1, 7, 7,L0\|L1}, /* ae: 1010 1110 */
	2137	{&upd7810_device::LDAX_H_xx, 2, 7, 7,L0\|L1}, /* af: 1010 1111 dddd dddd */
	2138
	2139	{&upd7810_device::PUSH_VA, 1,13,13,L0\|L1}, /* b0: 1011 0000 */
	2140	{&upd7810_device::PUSH_BC, 1,13,13,L0\|L1}, /* b1: 1011 0001 */
	2141	{&upd7810_device::PUSH_DE, 1,13,13,L0\|L1}, /* b2: 1011 0010 */
	2142	{&upd7810_device::PUSH_HL, 1,13,13,L0\|L1}, /* b3: 1011 0011 */
	2143	{&upd7810_device::PUSH_EA, 1,13,13,L0\|L1}, /* b4: 1011 0100 */
	2144	{&upd7810_device::DMOV_BC_EA, 1, 4, 4,L0\|L1}, /* b5: 1011 0101 */
	2145	{&upd7810_device::DMOV_DE_EA, 1, 4, 4,L0\|L1}, /* b6: 1011 0110 */
	2146	{&upd7810_device::DMOV_HL_EA, 1, 4, 4,L0\|L1}, /* b7: 1011 0111 */
	2147	{&upd7810_device::RET, 1,10,10,L0\|L1}, /* b8: 1011 1000 */
	2148	{&upd7810_device::RETS, 1,10,10,L0\|L1}, /* b9: 1011 1001 */
	2149	{&upd7810_device::DI, 1, 4, 4,L0\|L1}, /* ba: 1011 1010 */
	2150	{&upd7810_device::STAX_D_xx, 2, 7, 7,L0\|L1}, /* bb: 1011 1011 dddd dddd */
	2151	{&upd7810_device::STAX_H_A, 1, 7, 7,L0\|L1}, /* bc: 1011 1100 */
	2152	{&upd7810_device::STAX_H_B, 1, 7, 7,L0\|L1}, /* bd: 1011 1101 */
	2153	{&upd7810_device::STAX_H_EA, 1, 7, 7,L0\|L1}, /* be: 1011 1110 */
	2154	{&upd7810_device::STAX_H_xx, 2, 7, 7,L0\|L1}, /* bf: 1011 1111 dddd dddd */
	2155
	2156	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c0: 1100 0000 */
	2157	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c1: 1100 0001 */
	2158	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c2: 1100 0010 */
	2159	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c3: 1100 0011 */
	2160	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c4: 1100 0100 */
	2161	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c5: 1100 0101 */
	2162	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c6: 1100 0110 */
	2163	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c7: 1100 0111 */
	2164	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c8: 1100 1000 */
	2165	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c9: 1100 1001 */
	2166	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ca: 1100 1010 */
	2167	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* cb: 1100 1011 */
	2168	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* cc: 1100 1100 */
	2169	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* cd: 1100 1101 */
	2170	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ce: 1100 1110 */
	2171	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* cf: 1100 1111 */
	2172
	2173	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d0: 1101 0000 */
	2174	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d1: 1101 0001 */
	2175	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d2: 1101 0010 */
	2176	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d3: 1101 0011 */
	2177	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d4: 1101 0100 */
	2178	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d5: 1101 0101 */
	2179	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d6: 1101 0110 */
	2180	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d7: 1101 0111 */
	2181	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d8: 1101 1000 */
	2182	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d9: 1101 1001 */
	2183	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* da: 1101 1010 */
	2184	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* db: 1101 1011 */
	2185	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* dc: 1101 1100 */
	2186	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* dd: 1101 1101 */
	2187	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* de: 1101 1110 */
	2188	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* df: 1101 1111 */
	2189
	2190	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e0: 1110 0000 */
	2191	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e1: 1110 0001 */
	2192	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e2: 1110 0010 */
	2193	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e3: 1110 0011 */
	2194	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e4: 1110 0100 */
	2195	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e5: 1110 0101 */
	2196	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e6: 1110 0110 */
	2197	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e7: 1110 0111 */
	2198	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e8: 1110 1000 */
	2199	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e9: 1110 1001 */
	2200	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ea: 1110 1010 */
	2201	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* eb: 1110 1011 */
	2202	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ec: 1110 1100 */
	2203	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ed: 1110 1101 */
	2204	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ee: 1110 1110 */
	2205	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ef: 1110 1111 */
	2206
	2207	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f0: 1111 0000 */
	2208	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f1: 1111 0001 */
	2209	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f2: 1111 0010 */
	2210	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f3: 1111 0011 */
	2211	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f4: 1111 0100 */
	2212	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f5: 1111 0101 */
	2213	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f6: 1111 0110 */
	2214	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f7: 1111 0111 */
	2215	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f8: 1111 1000 */
	2216	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f9: 1111 1001 */
	2217	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fa: 1111 1010 */
	2218	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fb: 1111 1011 */
	2219	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fc: 1111 1100 */
	2220	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fd: 1111 1101 */
	2221	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fe: 1111 1110 */
	2222	{&upd7810_device::JR, 1,10,10,L0\|L1} /* ff: 1111 1111 */
	2223	};
	2224
	2225	const struct upd7810_device::opcode_s upd7810_device::s_opXX_7807[256] =
	2226	{
	2227	{&upd7810_device::NOP, 1, 4, 4,L0\|L1}, /* 00: 0000 0000 */
	2228	{&upd7810_device::LDAW_wa, 2,10,10,L0\|L1}, /* 01: 0000 0001 oooo oooo */
	2229	{&upd7810_device::INX_SP, 1, 7, 7,L0\|L1}, /* 02: 0000 0010 */
	2230	{&upd7810_device::DCX_SP, 1, 7, 7,L0\|L1}, /* 03: 0000 0011 */
	2231	{&upd7810_device::LXI_S_w, 3,10,10,L0\|L1}, /* 04: 0000 0100 llll llll hhhh hhhh */
	2232	{&upd7810_device::ANIW_wa_xx, 3,19,19,L0\|L1}, /* 05: 0000 0101 oooo oooo xxxx xxxx */
	2233	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, /* 06: */
	2234	{&upd7810_device::ANI_A_xx, 2, 7, 7,L0\|L1}, /* 07: 0000 0111 xxxx xxxx */
	2235	{&upd7810_device::MOV_A_EAH, 1, 4, 4,L0\|L1}, /* 08: 0000 1000 */
	2236	{&upd7810_device::MOV_A_EAL, 1, 4, 4,L0\|L1}, /* 09: 0000 1001 */
	2237	{&upd7810_device::MOV_A_B, 1, 4, 4,L0\|L1}, /* 0a: 0000 1010 */
	2238	{&upd7810_device::MOV_A_C, 1, 4, 4,L0\|L1}, /* 0b: 0000 1011 */
	2239	{&upd7810_device::MOV_A_D, 1, 4, 4,L0\|L1}, /* 0c: 0000 1100 */
	2240	{&upd7810_device::MOV_A_E, 1, 4, 4,L0\|L1}, /* 0d: 0000 1101 */
	2241	{&upd7810_device::MOV_A_H, 1, 4, 4,L0\|L1}, /* 0e: 0000 1110 */
	2242	{&upd7810_device::MOV_A_L, 1, 4, 4,L0\|L1}, /* 0f: 0000 1111 */
	2243
	2244	{&upd7810_device::illegal, 1,13, 4,L0\|L1}, /* 10: 0001 0000 / / 7807 */
	2245	{&upd7810_device::illegal, 1,13, 4,L0\|L1}, /* 11: 0001 0001 / / 7807 */
	2246	{&upd7810_device::INX_BC, 1, 7, 7,L0\|L1}, /* 12: 0001 0010 */
	2247	{&upd7810_device::DCX_BC, 1, 7, 7,L0\|L1}, /* 13: 0001 0011 */
	2248	{&upd7810_device::LXI_B_w, 3,10,10,L0\|L1}, /* 14: 0001 0100 llll llll hhhh hhhh */
	2249	{&upd7810_device::ORIW_wa_xx, 3,19,19,L0\|L1}, /* 15: 0001 0101 oooo oooo xxxx xxxx */
	2250	{&upd7810_device::XRI_A_xx, 2, 7, 7,L0\|L1}, /* 16: 0001 0110 xxxx xxxx */
	2251	{&upd7810_device::ORI_A_xx, 2, 7, 7,L0\|L1}, /* 17: 0001 0111 xxxx xxxx */
	2252	{&upd7810_device::MOV_EAH_A, 1, 4, 4,L0\|L1}, /* 18: 0001 1000 */
	2253	{&upd7810_device::MOV_EAL_A, 1, 4, 4,L0\|L1}, /* 19: 0001 1001 */
	2254	{&upd7810_device::MOV_B_A, 1, 4, 4,L0\|L1}, /* 1a: 0001 1010 */
	2255	{&upd7810_device::MOV_C_A, 1, 4, 4,L0\|L1}, /* 1b: 0001 1011 */
	2256	{&upd7810_device::MOV_D_A, 1, 4, 4,L0\|L1}, /* 1c: 0001 1100 */
	2257	{&upd7810_device::MOV_E_A, 1, 4, 4,L0\|L1}, /* 1d: 0001 1101 */
	2258	{&upd7810_device::MOV_H_A, 1, 4, 4,L0\|L1}, /* 1e: 0001 1110 */
	2259	{&upd7810_device::MOV_L_A, 1, 4, 4,L0\|L1}, /* 1f: 0001 1111 */
	2260
	2261	{&upd7810_device::INRW_wa, 2,16,16,L0\|L1}, /* 20: 0010 0000 oooo oooo */
	2262	{&upd7810_device::JB, 1, 4, 4,L0\|L1}, /* 21: 0010 0001 */
	2263	{&upd7810_device::INX_DE, 1, 7, 7,L0\|L1}, /* 22: 0010 0010 */
	2264	{&upd7810_device::DCX_DE, 1, 7, 7,L0\|L1}, /* 23: 0010 0011 */
	2265	{&upd7810_device::LXI_D_w, 3,10,10,L0\|L1}, /* 24: 0010 0100 llll llll hhhh hhhh */
	2266	{&upd7810_device::GTIW_wa_xx, 3,19,19,L0\|L1}, /* 25: 0010 0101 oooo oooo xxxx xxxx */
	2267	{&upd7810_device::ADINC_A_xx, 2, 7, 7,L0\|L1}, /* 26: 0010 0110 xxxx xxxx */
	2268	{&upd7810_device::GTI_A_xx, 2, 7, 7,L0\|L1}, /* 27: 0010 0111 xxxx xxxx */
	2269	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, /* 28: */
	2270	{&upd7810_device::LDAX_B, 2, 7, 7,L0\|L1}, /* 29: 0010 1001 dddd dddd */
	2271	{&upd7810_device::LDAX_D, 2, 7, 7,L0\|L1}, /* 2a: 0010 1010 dddd dddd */
	2272	{&upd7810_device::LDAX_H, 2, 7, 7,L0\|L1}, /* 2b: 0010 1011 dddd dddd */
	2273	{&upd7810_device::LDAX_Dp, 2, 7, 7,L0\|L1}, /* 2c: 0010 1100 dddd dddd */
	2274	{&upd7810_device::LDAX_Hp, 2, 7, 7,L0\|L1}, /* 2d: 0010 1101 dddd dddd */
	2275	{&upd7810_device::LDAX_Dm, 2, 7, 7,L0\|L1}, /* 2e: 0010 1110 dddd dddd */
	2276	{&upd7810_device::LDAX_Hm, 2, 7, 7,L0\|L1}, /* 2f: 0010 1111 dddd dddd */
	2277
	2278	{&upd7810_device::DCRW_wa, 2,16,16,L0\|L1}, /* 30: 0011 0000 oooo oooo */
	2279	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 31: 0011 0001 bbbb bbbb / / 7807 */
	2280	{&upd7810_device::INX_HL, 1, 7, 7,L0\|L1}, /* 32: 0011 0010 */
	2281	{&upd7810_device::DCX_HL, 1, 7, 7,L0\|L1}, /* 33: 0011 0011 */
	2282	{&upd7810_device::LXI_H_w, 3,10,10, L1}, /* 34: 0011 0100 llll llll hhhh hhhh */
	2283	{&upd7810_device::LTIW_wa_xx, 3,19,19,L0\|L1}, /* 35: 0011 0101 oooo oooo xxxx xxxx */
	2284	{&upd7810_device::SUINB_A_xx, 2, 7, 7,L0\|L1}, /* 36: 0011 0110 xxxx xxxx */
	2285	{&upd7810_device::LTI_A_xx, 2, 7, 7,L0\|L1}, /* 37: 0011 0111 xxxx xxxx */
	2286	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, /* 38: */
	2287	{&upd7810_device::STAX_B, 2, 7, 7,L0\|L1}, /* 39: 0011 1001 dddd dddd */
	2288	{&upd7810_device::STAX_D, 2, 7, 7,L0\|L1}, /* 3a: 0011 1010 dddd dddd */
	2289	{&upd7810_device::STAX_H, 2, 7, 7,L0\|L1}, /* 3b: 0011 1011 dddd dddd */
	2290	{&upd7810_device::STAX_Dp, 2, 7, 7,L0\|L1}, /* 3c: 0011 1100 dddd dddd */
	2291	{&upd7810_device::STAX_Hp, 2, 7, 7,L0\|L1}, /* 3d: 0011 1101 dddd dddd */
	2292	{&upd7810_device::STAX_Dm, 2, 7, 7,L0\|L1}, /* 3e: 0011 1110 dddd dddd */
	2293	{&upd7810_device::STAX_Hm, 2, 7, 7,L0\|L1}, /* 3f: 0011 1111 dddd dddd */
	2294
	2295	{&upd7810_device::CALL_w, 3,16,16,L0\|L1}, /* 40: 0100 0000 llll llll hhhh hhhh */
	2296	{&upd7810_device::INR_A, 1, 4, 4,L0\|L1}, /* 41: 0100 0001 */
	2297	{&upd7810_device::INR_B, 1, 4, 4,L0\|L1}, /* 42: 0100 0010 */
	2298	{&upd7810_device::INR_C, 1, 4, 4,L0\|L1}, /* 43: 0100 0011 */
	2299	{&upd7810_device::LXI_EA_s, 3,10,10,L0\|L1}, /* 44: 0100 0100 llll llll hhhh hhhh */
	2300	{&upd7810_device::ONIW_wa_xx, 3,19,19,L0\|L1}, /* 45: 0100 0101 oooo oooo xxxx xxxx */
	2301	{&upd7810_device::ADI_A_xx, 2, 7, 7,L0\|L1}, /* 46: 0100 0110 xxxx xxxx */
	2302	{&upd7810_device::ONI_A_xx, 2, 7, 7,L0\|L1}, /* 47: 0100 0111 xxxx xxxx */
	2303	{&upd7810_device::PRE_48, 1, 0, 0,L0\|L1}, /* 48: prefix */
	2304	{&upd7810_device::MVIX_BC_xx, 2,10,10,L0\|L1}, /* 49: 0100 1001 xxxx xxxx */
	2305	{&upd7810_device::MVIX_DE_xx, 2,10,10,L0\|L1}, /* 4a: 0100 1010 xxxx xxxx */
	2306	{&upd7810_device::MVIX_HL_xx, 2,10,10,L0\|L1}, /* 4b: 0100 1011 xxxx xxxx */
	2307	{&upd7810_device::PRE_4C, 1, 0, 0,L0\|L1}, /* 4c: prefix */
	2308	{&upd7810_device::PRE_4D, 1, 4, 4,L0\|L1}, /* 4d: prefix */
	2309	{&upd7810_device::JRE, 2,10,10,L0\|L1}, /* 4e: 0100 111d dddd dddd */
	2310	{&upd7810_device::JRE, 2,10,10,L0\|L1}, /* 4f: 0100 111d dddd dddd */
	2311
	2312	{&upd7810_device::SKN_bit, 2,13,13,L0\|L1}, /* 50: 0101 0000 bbbb bbbb / / 7807 */
	2313	{&upd7810_device::DCR_A, 1, 4, 4,L0\|L1}, /* 51: 0101 0001 */
	2314	{&upd7810_device::DCR_B, 1, 4, 4,L0\|L1}, /* 52: 0101 0010 */
	2315	{&upd7810_device::DCR_C, 1, 4, 4,L0\|L1}, /* 53: 0101 0011 */
	2316	{&upd7810_device::JMP_w, 3,10,10,L0\|L1}, /* 54: 0101 0100 llll llll hhhh hhhh */
	2317	{&upd7810_device::OFFIW_wa_xx, 3,19,19,L0\|L1}, /* 55: 0101 0101 oooo oooo xxxx xxxx */
	2318	{&upd7810_device::ACI_A_xx, 2, 7, 7,L0\|L1}, /* 56: 0101 0110 xxxx xxxx */
	2319	{&upd7810_device::OFFI_A_xx, 2, 7, 7,L0\|L1}, /* 57: 0101 0111 xxxx xxxx */
	2320	{&upd7810_device::SETB, 2,13,13,L0\|L1}, /* 58: 0101 1000 bbbb bbbb / / 7807 */
	2321	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 59: 0101 1001 bbbb bbbb / / 7807 */
	2322	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 5a: 0101 1010 bbbb bbbb / / 7807 */
	2323	{&upd7810_device::CLR, 2,13,13,L0\|L1}, /* 5b: 0101 1011 bbbb bbbb / / 7807 */
	2324	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 5c: 0101 1100 bbbb bbbb / / 7807 */
	2325	{&upd7810_device::SK_bit, 2,10,10,L0\|L1}, /* 5d: 0101 1101 bbbb bbbb / / 7807 */
	2326	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 5e: 0101 1110 bbbb bbbb / / 7807 */
	2327	{&upd7810_device::illegal, 2, 8, 8,L0\|L1}, /* 5f: 0101 1111 bbbb bbbb / / 7807 */
	2328
	2329	{&upd7810_device::PRE_60, 1, 0, 0,L0\|L1}, /* 60: */
	2330	{&upd7810_device::DAA, 1, 4, 4,L0\|L1}, /* 61: 0110 0001 */
	2331	{&upd7810_device::RETI, 1,13,13,L0\|L1}, /* 62: 0110 0010 */
	2332	{&upd7810_device::STAW_wa, 2,10,10,L0\|L1}, /* 63: 0110 0011 oooo oooo */
	2333	{&upd7810_device::PRE_64, 1, 0, 0,L0\|L1}, /* 64: */
	2334	{&upd7810_device::NEIW_wa_xx, 3,19,19,L0\|L1}, /* 65: 0110 0101 oooo oooo xxxx xxxx */
	2335	{&upd7810_device::SUI_A_xx, 2, 7, 7,L0\|L1}, /* 66: 0110 0110 xxxx xxxx */
	2336	{&upd7810_device::NEI_A_xx, 2, 7, 7,L0\|L1}, /* 67: 0110 0111 xxxx xxxx */
	2337	{&upd7810_device::MVI_V_xx, 2, 7, 7,L0\|L1}, /* 68: 0110 1000 xxxx xxxx */
	2338	{&upd7810_device::MVI_A_xx, 2, 7, 7,L0 }, /* 69: 0110 1001 xxxx xxxx */
	2339	{&upd7810_device::MVI_B_xx, 2, 7, 7,L0\|L1}, /* 6a: 0110 1010 xxxx xxxx */
	2340	{&upd7810_device::MVI_C_xx, 2, 7, 7,L0\|L1}, /* 6b: 0110 1011 xxxx xxxx */
	2341	{&upd7810_device::MVI_D_xx, 2, 7, 7,L0\|L1}, /* 6c: 0110 1100 xxxx xxxx */
	2342	{&upd7810_device::MVI_E_xx, 2, 7, 7,L0\|L1}, /* 6d: 0110 1101 xxxx xxxx */
	2343	{&upd7810_device::MVI_H_xx, 2, 7, 7,L0\|L1}, /* 6e: 0110 1110 xxxx xxxx */
	2344	{&upd7810_device::MVI_L_xx, 2, 7, 7, L1}, /* 6f: 0110 1111 xxxx xxxx */
	2345
	2346	{&upd7810_device::PRE_70, 1, 0, 0,L0\|L1}, /* 70: */
	2347	{&upd7810_device::MVIW_wa_xx, 3,13,13,L0\|L1}, /* 71: 0111 0001 oooo oooo xxxx xxxx */
	2348	{&upd7810_device::SOFTI, 1,16,16,L0\|L1}, /* 72: 0111 0010 */
	2349	{&upd7810_device::illegal, 1, 0, 0,L0\|L1}, /* 73: */
	2350	{&upd7810_device::PRE_74, 1, 0, 0,L0\|L1}, /* 74: prefix */
	2351	{&upd7810_device::EQIW_wa_xx, 3,19,19,L0\|L1}, /* 75: 0111 0101 oooo oooo xxxx xxxx */
	2352	{&upd7810_device::SBI_A_xx, 2, 7, 7,L0\|L1}, /* 76: 0111 0110 xxxx xxxx */
	2353	{&upd7810_device::EQI_A_xx, 2, 7, 7,L0\|L1}, /* 77: 0111 0111 xxxx xxxx */
	2354	{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 78: 0111 1xxx xxxx xxxx */
	2355	{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 79: 0111 1xxx xxxx xxxx */
	2356	{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7a: 0111 1xxx xxxx xxxx */
	2357	{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7b: 0111 1xxx xxxx xxxx */
	2358	{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7c: 0111 1xxx xxxx xxxx */
	2359	{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7d: 0111 1xxx xxxx xxxx */
	2360	{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7e: 0111 1xxx xxxx xxxx */
	2361	{&upd7810_device::CALF, 2,13,13,L0\|L1}, /* 7f: 0111 1xxx xxxx xxxx */
	2362
	2363	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 80: 100x xxxx */
	2364	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 81: 100x xxxx */
	2365	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 82: 100x xxxx */
	2366	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 83: 100x xxxx */
	2367	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 84: 100x xxxx */
	2368	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 85: 100x xxxx */
	2369	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 86: 100x xxxx */
	2370	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 87: 100x xxxx */
	2371	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 88: 100x xxxx */
	2372	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 89: 100x xxxx */
	2373	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8a: 100x xxxx */
	2374	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8b: 100x xxxx */
	2375	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8c: 100x xxxx */
	2376	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8d: 100x xxxx */
	2377	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8e: 100x xxxx */
	2378	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 8f: 100x xxxx */
	2379
	2380	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 90: 100x xxxx */
	2381	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 91: 100x xxxx */
	2382	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 92: 100x xxxx */
	2383	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 93: 100x xxxx */
	2384	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 94: 100x xxxx */
	2385	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 95: 100x xxxx */
	2386	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 96: 100x xxxx */
	2387	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 97: 100x xxxx */
	2388	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 98: 100x xxxx */
	2389	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 99: 100x xxxx */
	2390	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9a: 100x xxxx */
	2391	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9b: 100x xxxx */
	2392	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9c: 100x xxxx */
	2393	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9d: 100x xxxx */
	2394	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9e: 100x xxxx */
	2395	{&upd7810_device::CALT, 1,16,16,L0\|L1}, /* 9f: 100x xxxx */
	2396
	2397	{&upd7810_device::POP_VA, 1,10,10,L0\|L1}, /* a0: 1010 0000 */
	2398	{&upd7810_device::POP_BC, 1,10,10,L0\|L1}, /* a1: 1010 0001 */
	2399	{&upd7810_device::POP_DE, 1,10,10,L0\|L1}, /* a2: 1010 0010 */
	2400	{&upd7810_device::POP_HL, 1,10,10,L0\|L1}, /* a3: 1010 0011 */
	2401	{&upd7810_device::POP_EA, 1,10,10,L0\|L1}, /* a4: 1010 0100 */
	2402	{&upd7810_device::DMOV_EA_BC, 1, 4, 4,L0\|L1}, /* a5: 1010 0101 */
	2403	{&upd7810_device::DMOV_EA_DE, 1, 4, 4,L0\|L1}, /* a6: 1010 0110 */
	2404	{&upd7810_device::DMOV_EA_HL, 1, 4, 4,L0\|L1}, /* a7: 1010 0111 */
	2405	{&upd7810_device::INX_EA, 1, 7, 7,L0\|L1}, /* a8: 1010 1000 */
	2406	{&upd7810_device::DCX_EA, 1, 7, 7,L0\|L1}, /* a9: 1010 1001 */
	2407	{&upd7810_device::EI, 1, 4, 4,L0\|L1}, /* aa: 1010 1010 */
	2408	{&upd7810_device::LDAX_D_xx, 2, 7, 7,L0\|L1}, /* ab: 1010 1011 dddd dddd */
	2409	{&upd7810_device::LDAX_H_A, 1, 7, 7,L0\|L1}, /* ac: 1010 1100 */
	2410	{&upd7810_device::LDAX_H_B, 1, 7, 7,L0\|L1}, /* ad: 1010 1101 */
	2411	{&upd7810_device::LDAX_H_EA, 1, 7, 7,L0\|L1}, /* ae: 1010 1110 */
	2412	{&upd7810_device::LDAX_H_xx, 2, 7, 7,L0\|L1}, /* af: 1010 1111 dddd dddd */
	2413
	2414	{&upd7810_device::PUSH_VA, 1,13,13,L0\|L1}, /* b0: 1011 0000 */
	2415	{&upd7810_device::PUSH_BC, 1,13,13,L0\|L1}, /* b1: 1011 0001 */
	2416	{&upd7810_device::PUSH_DE, 1,13,13,L0\|L1}, /* b2: 1011 0010 */
	2417	{&upd7810_device::PUSH_HL, 1,13,13,L0\|L1}, /* b3: 1011 0011 */
	2418	{&upd7810_device::PUSH_EA, 1,13,13,L0\|L1}, /* b4: 1011 0100 */
	2419	{&upd7810_device::DMOV_BC_EA, 1, 4, 4,L0\|L1}, /* b5: 1011 0101 */
	2420	{&upd7810_device::DMOV_DE_EA, 1, 4, 4,L0\|L1}, /* b6: 1011 0110 */
	2421	{&upd7810_device::DMOV_HL_EA, 1, 4, 4,L0\|L1}, /* b7: 1011 0111 */
	2422	{&upd7810_device::RET, 1,10,10,L0\|L1}, /* b8: 1011 1000 */
	2423	{&upd7810_device::RETS, 1,10,10,L0\|L1}, /* b9: 1011 1001 */
	2424	{&upd7810_device::DI, 1, 4, 4,L0\|L1}, /* ba: 1011 1010 */
	2425	{&upd7810_device::STAX_D_xx, 2, 7, 7,L0\|L1}, /* bb: 1011 1011 dddd dddd */
	2426	{&upd7810_device::STAX_H_A, 1, 7, 7,L0\|L1}, /* bc: 1011 1100 */
	2427	{&upd7810_device::STAX_H_B, 1, 7, 7,L0\|L1}, /* bd: 1011 1101 */
	2428	{&upd7810_device::STAX_H_EA, 1, 7, 7,L0\|L1}, /* be: 1011 1110 */
	2429	{&upd7810_device::STAX_H_xx, 2, 7, 7,L0\|L1}, /* bf: 1011 1111 dddd dddd */
	2430
	2431	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c0: 1100 0000 */
	2432	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c1: 1100 0001 */
	2433	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c2: 1100 0010 */
	2434	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c3: 1100 0011 */
	2435	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c4: 1100 0100 */
	2436	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c5: 1100 0101 */
	2437	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c6: 1100 0110 */
	2438	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c7: 1100 0111 */
	2439	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c8: 1100 1000 */
	2440	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* c9: 1100 1001 */
	2441	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ca: 1100 1010 */
	2442	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* cb: 1100 1011 */
	2443	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* cc: 1100 1100 */
	2444	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* cd: 1100 1101 */
	2445	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ce: 1100 1110 */
	2446	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* cf: 1100 1111 */
	2447
	2448	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d0: 1101 0000 */
	2449	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d1: 1101 0001 */
	2450	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d2: 1101 0010 */
	2451	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d3: 1101 0011 */
	2452	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d4: 1101 0100 */
	2453	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d5: 1101 0101 */
	2454	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d6: 1101 0110 */
	2455	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d7: 1101 0111 */
	2456	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d8: 1101 1000 */
	2457	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* d9: 1101 1001 */
	2458	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* da: 1101 1010 */
	2459	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* db: 1101 1011 */
	2460	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* dc: 1101 1100 */
	2461	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* dd: 1101 1101 */
	2462	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* de: 1101 1110 */
	2463	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* df: 1101 1111 */
	2464
	2465	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e0: 1110 0000 */
	2466	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e1: 1110 0001 */
	2467	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e2: 1110 0010 */
	2468	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e3: 1110 0011 */
	2469	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e4: 1110 0100 */
	2470	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e5: 1110 0101 */
	2471	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e6: 1110 0110 */
	2472	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e7: 1110 0111 */
	2473	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e8: 1110 1000 */
	2474	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* e9: 1110 1001 */
	2475	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ea: 1110 1010 */
	2476	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* eb: 1110 1011 */
	2477	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ec: 1110 1100 */
	2478	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ed: 1110 1101 */
	2479	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ee: 1110 1110 */
	2480	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* ef: 1110 1111 */
	2481
	2482	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f0: 1111 0000 */
	2483	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f1: 1111 0001 */
	2484	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f2: 1111 0010 */
	2485	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f3: 1111 0011 */
	2486	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f4: 1111 0100 */
	2487	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f5: 1111 0101 */
	2488	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f6: 1111 0110 */
	2489	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f7: 1111 0111 */
	2490	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f8: 1111 1000 */
	2491	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* f9: 1111 1001 */
	2492	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fa: 1111 1010 */
	2493	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fb: 1111 1011 */
	2494	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fc: 1111 1100 */
	2495	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fd: 1111 1101 */
	2496	{&upd7810_device::JR, 1,10,10,L0\|L1}, /* fe: 1111 1110 */
	2497	{&upd7810_device::JR, 1,10,10,L0\|L1} /* ff: 1111 1111 */
	2498	};
	2499
	2500
	2501	/***********************************************************************
	2502	*
	2503	* uPD7801
	2504	*
	2505	**********************************************************************/
	2506
	2507	const struct upd7810_device::opcode_s upd7810_device::s_op48_7801[256] =
	2508	{
	2509	/* 0x00 - 0x1F */
	2510	{&upd7810_device::SKIT_F0, 2, 8, 8,L0\|L1}, {&upd7810_device::SKIT_FT0, 2, 8, 8,L0\|L1},
	2511	{&upd7810_device::SKIT_F1, 2, 8, 8,L0\|L1}, {&upd7810_device::SKIT_F2, 2, 8, 8,L0\|L1},
	2512	{&upd7810_device::SKIT_FST, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2513	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2514	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2515	{&upd7810_device::SK_CY, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2516	{&upd7810_device::SK_Z, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2517	{&upd7810_device::PUSH_VA, 2,17,17,L0\|L1}, {&upd7810_device::POP_VA, 2,15,15,L0\|L1},
	2518
	2519	{&upd7810_device::SKNIT_F0, 2, 8, 8,L0\|L1}, {&upd7810_device::SKNIT_FT0, 2, 8, 8,L0\|L1},
	2520	{&upd7810_device::SKNIT_F1, 2, 8, 8,L0\|L1}, {&upd7810_device::SKNIT_F2, 2, 8, 8,L0\|L1},
	2521	{&upd7810_device::SKNIT_FST, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2522	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2523	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal, 2, 8, 8,L0\|L1},
	2524	{&upd7810_device::SKN_CY, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2525	{&upd7810_device::SKN_Z, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2526	{&upd7810_device::PUSH_BC, 2,17,17,L0\|L1}, {&upd7810_device::POP_BC, 2,15,15,L0\|L1},
	2527
	2528	/* 0x20 - 0x3F */
	2529	{&upd7810_device::EI, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2530	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2531	{&upd7810_device::DI, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2532	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2533	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2534	{&upd7810_device::CLC, 2, 8, 8,L0\|L1}, {&upd7810_device::STC, 2, 8, 8,L0\|L1},
	2535	{&upd7810_device::PEN, 2,11,11,L0\|L1}, {&upd7810_device::PEX, 2,11,11,L0\|L1},
	2536	{&upd7810_device::PUSH_DE, 2,17,17,L0\|L1}, {&upd7810_device::POP_DE, 2,15,15,L0\|L1},
	2537
	2538	{&upd7810_device::RLL_A, 2, 8, 8,L0\|L1}, {&upd7810_device::RLR_A, 2, 8, 8,L0\|L1},
	2539	{&upd7810_device::RLL_C, 2, 8, 8,L0\|L1}, {&upd7810_device::RLR_C, 2, 8, 8,L0\|L1},
	2540	{&upd7810_device::SLL_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SLR_A, 2, 8, 8,L0\|L1},
	2541	{&upd7810_device::SLL_C, 2, 8, 8,L0\|L1}, {&upd7810_device::SLR_C, 2, 8, 8,L0\|L1},
	2542	{&upd7810_device::RLD, 2,17,17,L0\|L1}, {&upd7810_device::RRD, 2,17,17,L0\|L1},
	2543	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2544	{&upd7810_device::PER, 2,11,11,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2545	{&upd7810_device::PUSH_HL, 2,17,17,L0\|L1}, {&upd7810_device::POP_HL, 2,15,15,L0\|L1},
	2546
	2547	/* 0x40 - 0x5F */
	2548	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2549	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2550	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2551	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2552	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2553	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2554	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2555	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2556
	2557	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2558	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2559	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2560	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2561	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2562	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2563	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2564	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2565
	2566	/* 0x60 - 0x7F */
	2567	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2568	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2569	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2570	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2571	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2572	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2573	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2574	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2575
	2576	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2577	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2578	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2579	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2580	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2581	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2582	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2583	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2584
	2585	/* 0x80 - 0x9F */
	2586	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2587	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2588	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2589	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2590	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2591	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2592	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2593	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2594
	2595	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2596	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2597	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2598	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2599	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2600	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2601	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2602	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2603
	2604	/* 0xA0 - 0xBF */
	2605	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2606	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2607	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2608	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2609	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2610	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2611	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2612	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2613
	2614	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2615	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2616	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2617	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2618	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2619	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2620	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2621	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2622
	2623	/* 0xC0 - 0xDF */
	2624	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2625	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2626	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2627	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2628	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2629	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2630	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2631	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2632
	2633	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2634	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2635	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2636	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2637	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2638	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2639	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2640	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2641
	2642	/* 0xE0 - 0xFF */
	2643	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2644	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2645	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2646	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2647	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2648	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2649	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2650	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2651
	2652	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2653	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2654	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2655	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2656	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2657	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2658	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2659	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
	2660	};
	2661
	2662	const struct upd7810_device::opcode_s upd7810_device::s_op4C_7801[256] =
	2663	{
	2664	/* 0x00 - 0x1F */
	2665	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2666	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2667	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2668	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2669	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2670	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2671	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2672	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2673
	2674	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2675	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2676	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2677	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2678	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2679	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2680	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2681	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2682
	2683	/* 0x20 - 0x3F */
	2684	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2685	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2686	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2687	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2688	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2689	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2690	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2691	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2692
	2693	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2694	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2695	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2696	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2697	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2698	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2699	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2700	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2701
	2702	/* 0x40 - 0x5F */
	2703	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2704	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2705	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2706	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2707	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2708	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2709	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2710	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2711
	2712	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2713	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2714	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2715	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2716	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2717	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2718	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2719	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2720
	2721	/* 0x60 - 0x7F */
	2722	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2723	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2724	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2725	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2726	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2727	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2728	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2729	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2730
	2731	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2732	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2733	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2734	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2735	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2736	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2737	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2738	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2739
	2740	/* 0x80 - 0x9F */
	2741	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2742	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2743	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2744	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2745	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2746	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2747	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2748	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2749
	2750	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2751	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2752	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2753	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2754	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2755	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2756	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2757	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2758
	2759	/* 0xA0 - 0xBF */
	2760	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2761	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2762	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2763	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2764	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2765	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2766	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2767	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2768
	2769	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2770	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2771	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2772	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2773	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2774	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2775	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2776	{&upd7810_device::IN, 2,10,10,L0\|L1}, {&upd7810_device::IN, 2,10,10,L0\|L1},
	2777
	2778	/* 0xC0 - 0xDF */
	2779	{&upd7810_device::MOV_A_PA, 2,10,10,L0\|L1}, {&upd7810_device::MOV_A_PB, 2,10,10,L0\|L1},
	2780	{&upd7810_device::MOV_A_PC, 2,10,10,L0\|L1}, {&upd7810_device::MOV_A_MKL, 2,10,10,L0\|L1},
	2781	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2782	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2783	{&upd7810_device::MOV_A_S, 2,10,10,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2784	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2785	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2786	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2787
	2788	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2789	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2790	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2791	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2792	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2793	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2794	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2795	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2796
	2797	/* 0xE0 - 0xFF */
	2798	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2799	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2800	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2801	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2802	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2803	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2804	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2805	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2806
	2807	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2808	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2809	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2810	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2811	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2812	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2813	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2814	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
	2815	};
	2816
	2817	/* prefix 4D */
	2818	const struct upd7810_device::opcode_s upd7810_device::s_op4D_7801[256] =
	2819	{
	2820	/* 0x00 - 0x1F */
	2821	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2822	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2823	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2824	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2825	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2826	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2827	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2828	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2829
	2830	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2831	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2832	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2833	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2834	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2835	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2836	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2837	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2838
	2839	/* 0x20 - 0x3F */
	2840	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2841	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2842	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2843	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2844	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2845	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2846	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2847	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2848
	2849	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2850	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2851	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2852	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2853	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2854	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2855	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2856	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2857
	2858	/* 0x40 - 0x5F */
	2859	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2860	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2861	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2862	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2863	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2864	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2865	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2866	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2867
	2868	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2869	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2870	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2871	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2872	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2873	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2874	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2875	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2876
	2877	/* 0x60 - 0x7F */
	2878	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2879	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2880	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2881	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2882	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2883	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2884	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2885	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2886
	2887	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2888	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2889	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2890	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2891	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2892	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2893	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2894	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2895
	2896	/* 0x80 - 0x9F */
	2897	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2898	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2899	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2900	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2901	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2902	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2903	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2904	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2905
	2906	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2907	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2908	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2909	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2910	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2911	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2912	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2913	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2914
	2915	/* 0xA0 - 0xBF */
	2916	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2917	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2918	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2919	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2920	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2921	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2922	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2923	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2924
	2925	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2926	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2927	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2928	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2929	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2930	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2931	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2932	{&upd7810_device::OUT, 2,10,10,L0\|L1}, {&upd7810_device::OUT, 2,10,10,L0\|L1},
	2933
	2934	/* 0xC0 - 0xDF */
	2935	{&upd7810_device::MOV_PA_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_PB_A, 2,10,10,L0\|L1},
	2936	{&upd7810_device::MOV_PC_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_MKL_A, 2,10,10,L0\|L1},
	2937	{&upd7810_device::MOV_MB_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_MC_A_7801, 2,10,10,L0\|L1},
	2938	{&upd7810_device::MOV_TM0_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_TM1_A, 2,10,10,L0\|L1},
	2939	{&upd7810_device::MOV_S_A, 2,10,10,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2940	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2941	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2942	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2943
	2944	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2945	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2946	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2947	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2948	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2949	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2950	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2951	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2952
	2953	/* 0xE0 - 0xFF */
	2954	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2955	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2956	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2957	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2958	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2959	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2960	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2961	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2962
	2963	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2964	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2965	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2966	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2967	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2968	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2969	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2970	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
	2971	};
	2972
	2973	/* prefix 60 */
	2974	const struct upd7810_device::opcode_s upd7810_device::s_op60_7801[256] =
	2975	{
	2976	/* 0x00 - 0x1F */
	2977	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2978	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2979	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2980	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	2981	{&upd7810_device::ANA_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_A, 2, 8, 8,L0\|L1},
	2982	{&upd7810_device::ANA_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_C_A, 2, 8, 8,L0\|L1},
	2983	{&upd7810_device::ANA_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_E_A, 2, 8, 8,L0\|L1},
	2984	{&upd7810_device::ANA_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_L_A, 2, 8, 8,L0\|L1},
	2985
	2986	{&upd7810_device::XRA_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_A, 2, 8, 8,L0\|L1},
	2987	{&upd7810_device::XRA_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_C_A, 2, 8, 8,L0\|L1},
	2988	{&upd7810_device::XRA_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_E_A, 2, 8, 8,L0\|L1},
	2989	{&upd7810_device::XRA_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_L_A, 2, 8, 8,L0\|L1},
	2990	{&upd7810_device::ORA_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_A, 2, 8, 8,L0\|L1},
	2991	{&upd7810_device::ORA_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_C_A, 2, 8, 8,L0\|L1},
	2992	{&upd7810_device::ORA_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_E_A, 2, 8, 8,L0\|L1},
	2993	{&upd7810_device::ORA_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_L_A, 2, 8, 8,L0\|L1},
	2994
	2995	/* 0x20 - 0x3F */
	2996	{&upd7810_device::ADDNC_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_A, 2, 8, 8,L0\|L1},
	2997	{&upd7810_device::ADDNC_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_C_A, 2, 8, 8,L0\|L1},
	2998	{&upd7810_device::ADDNC_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_E_A, 2, 8, 8,L0\|L1},
	2999	{&upd7810_device::ADDNC_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_L_A, 2, 8, 8,L0\|L1},
	3000	{&upd7810_device::GTA_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_A, 2, 8, 8,L0\|L1},
	3001	{&upd7810_device::GTA_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_C_A, 2, 8, 8,L0\|L1},
	3002	{&upd7810_device::GTA_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_E_A, 2, 8, 8,L0\|L1},
	3003	{&upd7810_device::GTA_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_L_A, 2, 8, 8,L0\|L1},
	3004
	3005	{&upd7810_device::SUBNB_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_A, 2, 8, 8,L0\|L1},
	3006	{&upd7810_device::SUBNB_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_C_A, 2, 8, 8,L0\|L1},
	3007	{&upd7810_device::SUBNB_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_E_A, 2, 8, 8,L0\|L1},
	3008	{&upd7810_device::SUBNB_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_L_A, 2, 8, 8,L0\|L1},
	3009	{&upd7810_device::LTA_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_A, 2, 8, 8,L0\|L1},
	3010	{&upd7810_device::LTA_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_C_A, 2, 8, 8,L0\|L1},
	3011	{&upd7810_device::LTA_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_E_A, 2, 8, 8,L0\|L1},
	3012	{&upd7810_device::LTA_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_L_A, 2, 8, 8,L0\|L1},
	3013
	3014	/* 0x40 - 0x5F */
	3015	{&upd7810_device::ADD_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_A, 2, 8, 8,L0\|L1},
	3016	{&upd7810_device::ADD_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_C_A, 2, 8, 8,L0\|L1},
	3017	{&upd7810_device::ADD_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_E_A, 2, 8, 8,L0\|L1},
	3018	{&upd7810_device::ADD_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_L_A, 2, 8, 8,L0\|L1},
	3019	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3020	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3021	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3022	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3023
	3024	{&upd7810_device::ADC_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_A, 2, 8, 8,L0\|L1},
	3025	{&upd7810_device::ADC_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_C_A, 2, 8, 8,L0\|L1},
	3026	{&upd7810_device::ADC_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_E_A, 2, 8, 8,L0\|L1},
	3027	{&upd7810_device::ADC_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_L_A, 2, 8, 8,L0\|L1},
	3028	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3029	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3030	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3031	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3032
	3033	/* 0x60 - 0x7F */
	3034	{&upd7810_device::SUB_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_A, 2, 8, 8,L0\|L1},
	3035	{&upd7810_device::SUB_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_C_A, 2, 8, 8,L0\|L1},
	3036	{&upd7810_device::SUB_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_E_A, 2, 8, 8,L0\|L1},
	3037	{&upd7810_device::SUB_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_L_A, 2, 8, 8,L0\|L1},
	3038	{&upd7810_device::NEA_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_A, 2, 8, 8,L0\|L1},
	3039	{&upd7810_device::NEA_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_C_A, 2, 8, 8,L0\|L1},
	3040	{&upd7810_device::NEA_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_E_A, 2, 8, 8,L0\|L1},
	3041	{&upd7810_device::NEA_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_L_A, 2, 8, 8,L0\|L1},
	3042
	3043	{&upd7810_device::SBB_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_A, 2, 8, 8,L0\|L1},
	3044	{&upd7810_device::SBB_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_C_A, 2, 8, 8,L0\|L1},
	3045	{&upd7810_device::SBB_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_E_A, 2, 8, 8,L0\|L1},
	3046	{&upd7810_device::SBB_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_L_A, 2, 8, 8,L0\|L1},
	3047	{&upd7810_device::EQA_V_A, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_A, 2, 8, 8,L0\|L1},
	3048	{&upd7810_device::EQA_B_A, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_C_A, 2, 8, 8,L0\|L1},
	3049	{&upd7810_device::EQA_D_A, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_E_A, 2, 8, 8,L0\|L1},
	3050	{&upd7810_device::EQA_H_A, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_L_A, 2, 8, 8,L0\|L1},
	3051
	3052	/* 0x80 - 0x9F */
	3053	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3054	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3055	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3056	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3057	{&upd7810_device::ANA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_A, 2, 8, 8,L0\|L1},
	3058	{&upd7810_device::ANA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_C, 2, 8, 8,L0\|L1},
	3059	{&upd7810_device::ANA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_E, 2, 8, 8,L0\|L1},
	3060	{&upd7810_device::ANA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_L, 2, 8, 8,L0\|L1},
	3061
	3062	{&upd7810_device::XRA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_A, 2, 8, 8,L0\|L1},
	3063	{&upd7810_device::XRA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_C, 2, 8, 8,L0\|L1},
	3064	{&upd7810_device::XRA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_E, 2, 8, 8,L0\|L1},
	3065	{&upd7810_device::XRA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_L, 2, 8, 8,L0\|L1},
	3066	{&upd7810_device::ORA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_A, 2, 8, 8,L0\|L1},
	3067	{&upd7810_device::ORA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_C, 2, 8, 8,L0\|L1},
	3068	{&upd7810_device::ORA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_E, 2, 8, 8,L0\|L1},
	3069	{&upd7810_device::ORA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_L, 2, 8, 8,L0\|L1},
	3070
	3071	/* 0xA0 - 0xBF */
	3072	{&upd7810_device::ADDNC_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_A, 2, 8, 8,L0\|L1},
	3073	{&upd7810_device::ADDNC_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_C, 2, 8, 8,L0\|L1},
	3074	{&upd7810_device::ADDNC_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_E, 2, 8, 8,L0\|L1},
	3075	{&upd7810_device::ADDNC_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_L, 2, 8, 8,L0\|L1},
	3076	{&upd7810_device::GTA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_A, 2, 8, 8,L0\|L1},
	3077	{&upd7810_device::GTA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_C, 2, 8, 8,L0\|L1},
	3078	{&upd7810_device::GTA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_E, 2, 8, 8,L0\|L1},
	3079	{&upd7810_device::GTA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_L, 2, 8, 8,L0\|L1},
	3080
	3081	{&upd7810_device::SUBNB_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_A, 2, 8, 8,L0\|L1},
	3082	{&upd7810_device::SUBNB_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_C, 2, 8, 8,L0\|L1},
	3083	{&upd7810_device::SUBNB_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_E, 2, 8, 8,L0\|L1},
	3084	{&upd7810_device::SUBNB_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_L, 2, 8, 8,L0\|L1},
	3085	{&upd7810_device::LTA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_A, 2, 8, 8,L0\|L1},
	3086	{&upd7810_device::LTA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_C, 2, 8, 8,L0\|L1},
	3087	{&upd7810_device::LTA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_E, 2, 8, 8,L0\|L1},
	3088	{&upd7810_device::LTA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_L, 2, 8, 8,L0\|L1},
	3089
	3090	/* 0xC0 - 0xDF */
	3091	{&upd7810_device::ADD_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_A, 2, 8, 8,L0\|L1},
	3092	{&upd7810_device::ADD_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_C, 2, 8, 8,L0\|L1},
	3093	{&upd7810_device::ADD_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_E, 2, 8, 8,L0\|L1},
	3094	{&upd7810_device::ADD_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_L, 2, 8, 8,L0\|L1},
	3095	{&upd7810_device::ONA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::ONA_A_A, 2, 8, 8,L0\|L1},
	3096	{&upd7810_device::ONA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ONA_A_C, 2, 8, 8,L0\|L1},
	3097	{&upd7810_device::ONA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ONA_A_E, 2, 8, 8,L0\|L1},
	3098	{&upd7810_device::ONA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ONA_A_L, 2, 8, 8,L0\|L1},
	3099
	3100	{&upd7810_device::ADC_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_A, 2, 8, 8,L0\|L1},
	3101	{&upd7810_device::ADC_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_C, 2, 8, 8,L0\|L1},
	3102	{&upd7810_device::ADC_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_E, 2, 8, 8,L0\|L1},
	3103	{&upd7810_device::ADC_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_L, 2, 8, 8,L0\|L1},
	3104	{&upd7810_device::OFFA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFA_A_A, 2, 8, 8,L0\|L1},
	3105	{&upd7810_device::OFFA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFA_A_C, 2, 8, 8,L0\|L1},
	3106	{&upd7810_device::OFFA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFA_A_E, 2, 8, 8,L0\|L1},
	3107	{&upd7810_device::OFFA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFA_A_L, 2, 8, 8,L0\|L1},
	3108
	3109	/* 0xE0 - 0xFF */
	3110	{&upd7810_device::SUB_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_A, 2, 8, 8,L0\|L1},
	3111	{&upd7810_device::SUB_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_C, 2, 8, 8,L0\|L1},
	3112	{&upd7810_device::SUB_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_E, 2, 8, 8,L0\|L1},
	3113	{&upd7810_device::SUB_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_L, 2, 8, 8,L0\|L1},
	3114	{&upd7810_device::NEA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_A, 2, 8, 8,L0\|L1},
	3115	{&upd7810_device::NEA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_C, 2, 8, 8,L0\|L1},
	3116	{&upd7810_device::NEA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_E, 2, 8, 8,L0\|L1},
	3117	{&upd7810_device::NEA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_L, 2, 8, 8,L0\|L1},
	3118
	3119	{&upd7810_device::SBB_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_A, 2, 8, 8,L0\|L1},
	3120	{&upd7810_device::SBB_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_C, 2, 8, 8,L0\|L1},
	3121	{&upd7810_device::SBB_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_E, 2, 8, 8,L0\|L1},
	3122	{&upd7810_device::SBB_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_L, 2, 8, 8,L0\|L1},
	3123	{&upd7810_device::EQA_A_V, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_A, 2, 8, 8,L0\|L1},
	3124	{&upd7810_device::EQA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_C, 2, 8, 8,L0\|L1},
	3125	{&upd7810_device::EQA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_E, 2, 8, 8,L0\|L1},
	3126	{&upd7810_device::EQA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_L, 2, 8, 8,L0\|L1}
	3127	};
	3128
	3129	/* prefix 64 */
	3130	const struct upd7810_device::opcode_s upd7810_device::s_op64_7801[256] =
	3131	{
	3132	/* 0x00 - 0x1F */
	3133	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3134	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3135	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3136	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3137	{&upd7810_device::ANI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::ANI_A_xx, 3,11,11,L0\|L1},
	3138	{&upd7810_device::ANI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::ANI_C_xx, 3,11,11,L0\|L1},
	3139	{&upd7810_device::ANI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::ANI_E_xx, 3,11,11,L0\|L1},
	3140	{&upd7810_device::ANI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::ANI_L_xx, 3,11,11,L0\|L1},
	3141
	3142	{&upd7810_device::XRI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::XRI_A_xx, 3,11,11,L0\|L1},
	3143	{&upd7810_device::XRI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::XRI_C_xx, 3,11,11,L0\|L1},
	3144	{&upd7810_device::XRI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::XRI_E_xx, 3,11,11,L0\|L1},
	3145	{&upd7810_device::XRI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::XRI_L_xx, 3,11,11,L0\|L1},
	3146	{&upd7810_device::ORI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::ORI_A_xx, 3,11,11,L0\|L1},
	3147	{&upd7810_device::ORI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::ORI_C_xx, 3,11,11,L0\|L1},
	3148	{&upd7810_device::ORI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::ORI_E_xx, 3,11,11,L0\|L1},
	3149	{&upd7810_device::ORI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::ORI_L_xx, 3,11,11,L0\|L1},
	3150
	3151	/* 0x20 - 0x3F */
	3152	{&upd7810_device::ADINC_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::ADINC_A_xx, 3,11,11,L0\|L1},
	3153	{&upd7810_device::ADINC_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::ADINC_C_xx, 3,11,11,L0\|L1},
	3154	{&upd7810_device::ADINC_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::ADINC_E_xx, 3,11,11,L0\|L1},
	3155	{&upd7810_device::ADINC_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::ADINC_L_xx, 3,11,11,L0\|L1},
	3156	{&upd7810_device::GTI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::GTI_A_xx, 3,11,11,L0\|L1},
	3157	{&upd7810_device::GTI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::GTI_C_xx, 3,11,11,L0\|L1},
	3158	{&upd7810_device::GTI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::GTI_E_xx, 3,11,11,L0\|L1},
	3159	{&upd7810_device::GTI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::GTI_L_xx, 3,11,11,L0\|L1},
	3160
	3161	{&upd7810_device::SUINB_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::SUINB_A_xx, 3,11,11,L0\|L1},
	3162	{&upd7810_device::SUINB_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::SUINB_C_xx, 3,11,11,L0\|L1},
	3163	{&upd7810_device::SUINB_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::SUINB_E_xx, 3,11,11,L0\|L1},
	3164	{&upd7810_device::SUINB_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::SUINB_L_xx, 3,11,11,L0\|L1},
	3165	{&upd7810_device::LTI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::LTI_A_xx, 3,11,11,L0\|L1},
	3166	{&upd7810_device::LTI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::LTI_C_xx, 3,11,11,L0\|L1},
	3167	{&upd7810_device::LTI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::LTI_E_xx, 3,11,11,L0\|L1},
	3168	{&upd7810_device::LTI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::LTI_L_xx, 3,11,11,L0\|L1},
	3169
	3170	/* 0x40 - 0x5F */
	3171	{&upd7810_device::ADI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::ADI_A_xx, 3,11,11,L0\|L1},
	3172	{&upd7810_device::ADI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::ADI_C_xx, 3,11,11,L0\|L1},
	3173	{&upd7810_device::ADI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::ADI_E_xx, 3,11,11,L0\|L1},
	3174	{&upd7810_device::ADI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::ADI_L_xx, 3,11,11,L0\|L1},
	3175	{&upd7810_device::ONI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::ONI_A_xx, 3,11,11,L0\|L1},
	3176	{&upd7810_device::ONI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::ONI_C_xx, 3,11,11,L0\|L1},
	3177	{&upd7810_device::ONI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::ONI_E_xx, 3,11,11,L0\|L1},
	3178	{&upd7810_device::ONI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::ONI_L_xx, 3,11,11,L0\|L1},
	3179
	3180	{&upd7810_device::ACI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::ACI_A_xx, 3,11,11,L0\|L1},
	3181	{&upd7810_device::ACI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::ACI_C_xx, 3,11,11,L0\|L1},
	3182	{&upd7810_device::ACI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::ACI_E_xx, 3,11,11,L0\|L1},
	3183	{&upd7810_device::ACI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::ACI_L_xx, 3,11,11,L0\|L1},
	3184	{&upd7810_device::OFFI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::OFFI_A_xx, 3,11,11,L0\|L1},
	3185	{&upd7810_device::OFFI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::OFFI_C_xx, 3,11,11,L0\|L1},
	3186	{&upd7810_device::OFFI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::OFFI_E_xx, 3,11,11,L0\|L1},
	3187	{&upd7810_device::OFFI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::OFFI_L_xx, 3,11,11,L0\|L1},
	3188
	3189	/* 0x60 - 0x7F */
	3190	{&upd7810_device::SUI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::SUI_A_xx, 3,11,11,L0\|L1},
	3191	{&upd7810_device::SUI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::SUI_C_xx, 3,11,11,L0\|L1},
	3192	{&upd7810_device::SUI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::SUI_E_xx, 3,11,11,L0\|L1},
	3193	{&upd7810_device::SUI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::SUI_L_xx, 3,11,11,L0\|L1},
	3194	{&upd7810_device::NEI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::NEI_A_xx, 3,11,11,L0\|L1},
	3195	{&upd7810_device::NEI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::NEI_C_xx, 3,11,11,L0\|L1},
	3196	{&upd7810_device::NEI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::NEI_E_xx, 3,11,11,L0\|L1},
	3197	{&upd7810_device::NEI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::NEI_L_xx, 3,11,11,L0\|L1},
	3198
	3199	{&upd7810_device::SBI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::SBI_A_xx, 3,11,11,L0\|L1},
	3200	{&upd7810_device::SBI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::SBI_C_xx, 3,11,11,L0\|L1},
	3201	{&upd7810_device::SBI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::SBI_E_xx, 3,11,11,L0\|L1},
	3202	{&upd7810_device::SBI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::SBI_L_xx, 3,11,11,L0\|L1},
	3203	{&upd7810_device::EQI_V_xx, 3,11,11,L0\|L1}, {&upd7810_device::EQI_A_xx, 3,11,11,L0\|L1},
	3204	{&upd7810_device::EQI_B_xx, 3,11,11,L0\|L1}, {&upd7810_device::EQI_C_xx, 3,11,11,L0\|L1},
	3205	{&upd7810_device::EQI_D_xx, 3,11,11,L0\|L1}, {&upd7810_device::EQI_E_xx, 3,11,11,L0\|L1},
	3206	{&upd7810_device::EQI_H_xx, 3,11,11,L0\|L1}, {&upd7810_device::EQI_L_xx, 3,11,11,L0\|L1},
	3207
	3208	/* 0x80 - 0x9F */
	3209	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3210	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3211	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3212	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3213	{&upd7810_device::ANI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ANI_PB_xx, 3,17,17,L0\|L1},
	3214	{&upd7810_device::ANI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ANI_MKL_xx, 3,17,17,L0\|L1},
	3215	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3216	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3217
	3218	{&upd7810_device::XRI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::XRI_PB_xx, 3,17,17,L0\|L1},
	3219	{&upd7810_device::XRI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::XRI_MKL_xx, 3,17,17,L0\|L1},
	3220	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3221	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3222	{&upd7810_device::ORI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ORI_PB_xx, 3,17,17,L0\|L1},
	3223	{&upd7810_device::ORI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ORI_MKL_xx, 3,17,17,L0\|L1},
	3224	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3225	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3226
	3227	/* 0xA0 - 0xBF */
	3228	{&upd7810_device::ADINC_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ADINC_PB_xx, 3,17,17,L0\|L1},
	3229	{&upd7810_device::ADINC_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ADINC_MKL_xx, 3,17,17,L0\|L1},
	3230	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3231	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3232	{&upd7810_device::GTI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::GTI_PB_xx, 3,14,14,L0\|L1},
	3233	{&upd7810_device::GTI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::GTI_MKL_xx, 3,14,14,L0\|L1},
	3234	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3235	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3236
	3237	{&upd7810_device::SUINB_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::SUINB_PB_xx, 3,17,17,L0\|L1},
	3238	{&upd7810_device::SUINB_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::SUINB_MKL_xx, 3,17,17,L0\|L1},
	3239	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3240	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3241	{&upd7810_device::LTI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::LTI_PB_xx, 3,14,14,L0\|L1},
	3242	{&upd7810_device::LTI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::LTI_MKL_xx, 3,14,14,L0\|L1},
	3243	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3244	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3245
	3246	/* 0xC0 - 0xDF */
	3247	{&upd7810_device::ADI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ADI_PB_xx, 3,17,17,L0\|L1},
	3248	{&upd7810_device::ADI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ADI_MKL_xx, 3,17,17,L0\|L1},
	3249	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3250	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3251	{&upd7810_device::ONI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::ONI_PB_xx, 3,14,14,L0\|L1},
	3252	{&upd7810_device::ONI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::ONI_MKL_xx, 3,14,14,L0\|L1},
	3253	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3254	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3255
	3256	{&upd7810_device::ACI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ACI_PB_xx, 3,17,17,L0\|L1},
	3257	{&upd7810_device::ACI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ACI_MKL_xx, 3,17,17,L0\|L1},
	3258	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3259	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3260	{&upd7810_device::OFFI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::OFFI_PB_xx, 3,14,14,L0\|L1},
	3261	{&upd7810_device::OFFI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::OFFI_MKL_xx, 3,14,14,L0\|L1},
	3262	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3263	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3264
	3265	/* 0xE0 - 0xFF */
	3266	{&upd7810_device::SUI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::SUI_PB_xx, 3,17,17,L0\|L1},
	3267	{&upd7810_device::SUI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::SUI_MKL_xx, 3,17,17,L0\|L1},
	3268	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3269	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3270	{&upd7810_device::NEI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::NEI_PB_xx, 3,14,14,L0\|L1},
	3271	{&upd7810_device::NEI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::NEI_MKL_xx, 3,14,14,L0\|L1},
	3272	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3273	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3274
	3275	{&upd7810_device::SBI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::SBI_PB_xx, 3,17,17,L0\|L1},
	3276	{&upd7810_device::SBI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::SBI_MKL_xx, 3,17,17,L0\|L1},
	3277	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3278	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3279	{&upd7810_device::EQI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::EQI_PB_xx, 3,14,14,L0\|L1},
	3280	{&upd7810_device::EQI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::EQI_MKL_xx, 3,14,14,L0\|L1},
	3281	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3282	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
	3283	};
	3284
	3285	/* prefix 70 */
	3286	const struct upd7810_device::opcode_s upd7810_device::s_op70_7801[256] =
	3287	{
	3288	/* 0x00 - 0x1F */
	3289	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3290	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3291	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3292	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3293	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3294	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3295	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3296	{&upd7810_device::SSPD_w, 4,20,20,L0\|L1}, {&upd7810_device::LSPD_w, 4,20,20,L0\|L1},
	3297
	3298	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3299	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3300	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3301	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3302	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3303	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3304	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3305	{&upd7810_device::SBCD_w, 4,20,20,L0\|L1}, {&upd7810_device::LBCD_w, 4,20,20,L0\|L1},
	3306
	3307	/* 0x20 - 0x3F */
	3308	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3309	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3310	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3311	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3312	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3313	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3314	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3315	{&upd7810_device::SDED_w, 4,20,20,L0\|L1}, {&upd7810_device::LDED_w, 4,20,20,L0\|L1},
	3316
	3317	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3318	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3319	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3320	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3321	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3322	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3323	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3324	{&upd7810_device::SHLD_w, 4,20,20,L0\|L1}, {&upd7810_device::LHLD_w, 4,20,20,L0\|L1},
	3325
	3326	/* 0x40 - 0x5F */
	3327	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3328	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3329	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3330	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3331	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3332	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3333	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3334	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3335
	3336	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3337	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3338	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3339	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3340	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3341	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3342	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3343	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3344
	3345	/* 0x60 - 0x7F */
	3346	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3347	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3348	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3349	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3350	{&upd7810_device::MOV_V_w, 4,17,17,L0\|L1}, {&upd7810_device::MOV_A_w, 4,17,17,L0\|L1},
	3351	{&upd7810_device::MOV_B_w, 4,17,17,L0\|L1}, {&upd7810_device::MOV_C_w, 4,17,17,L0\|L1},
	3352	{&upd7810_device::MOV_D_w, 4,17,17,L0\|L1}, {&upd7810_device::MOV_E_w, 4,17,17,L0\|L1},
	3353	{&upd7810_device::MOV_H_w, 4,17,17,L0\|L1}, {&upd7810_device::MOV_L_w, 4,17,17,L0\|L1},
	3354
	3355	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3356	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3357	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3358	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3359	{&upd7810_device::MOV_w_V, 4,17,17,L0\|L1}, {&upd7810_device::MOV_w_A, 4,17,17,L0\|L1},
	3360	{&upd7810_device::MOV_w_B, 4,17,17,L0\|L1}, {&upd7810_device::MOV_w_C, 4,17,17,L0\|L1},
	3361	{&upd7810_device::MOV_w_D, 4,17,17,L0\|L1}, {&upd7810_device::MOV_w_E, 4,17,17,L0\|L1},
	3362	{&upd7810_device::MOV_w_H, 4,17,17,L0\|L1}, {&upd7810_device::MOV_w_L, 4,17,17,L0\|L1},
	3363
	3364	/* 0x80 - 0x9F */
	3365	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3366	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3367	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3368	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3369	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ANAX_B, 2,11,11,L0\|L1},
	3370	{&upd7810_device::ANAX_D, 2,11,11,L0\|L1}, {&upd7810_device::ANAX_H, 2,11,11,L0\|L1},
	3371	{&upd7810_device::ANAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ANAX_Hp, 2,11,11,L0\|L1},
	3372	{&upd7810_device::ANAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ANAX_Hm, 2,11,11,L0\|L1},
	3373
	3374	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::XRAX_B, 2,11,11,L0\|L1},
	3375	{&upd7810_device::XRAX_D, 2,11,11,L0\|L1}, {&upd7810_device::XRAX_H, 2,11,11,L0\|L1},
	3376	{&upd7810_device::XRAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::XRAX_Hp, 2,11,11,L0\|L1},
	3377	{&upd7810_device::XRAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::XRAX_Hm, 2,11,11,L0\|L1},
	3378	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ORAX_B, 2,11,11,L0\|L1},
	3379	{&upd7810_device::ORAX_D, 2,11,11,L0\|L1}, {&upd7810_device::ORAX_H, 2,11,11,L0\|L1},
	3380	{&upd7810_device::ORAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ORAX_Hp, 2,11,11,L0\|L1},
	3381	{&upd7810_device::ORAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ORAX_Hm, 2,11,11,L0\|L1},
	3382
	3383	/* 0xA0 - 0xBF */
	3384	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNCX_B, 2,11,11,L0\|L1},
	3385	{&upd7810_device::ADDNCX_D, 2,11,11,L0\|L1}, {&upd7810_device::ADDNCX_H, 2,11,11,L0\|L1},
	3386	{&upd7810_device::ADDNCX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ADDNCX_Hp, 2,11,11,L0\|L1},
	3387	{&upd7810_device::ADDNCX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ADDNCX_Hm, 2,11,11,L0\|L1},
	3388	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::GTAX_B, 2,11,11,L0\|L1},
	3389	{&upd7810_device::GTAX_D, 2,11,11,L0\|L1}, {&upd7810_device::GTAX_H, 2,11,11,L0\|L1},
	3390	{&upd7810_device::GTAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::GTAX_Hp, 2,11,11,L0\|L1},
	3391	{&upd7810_device::GTAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::GTAX_Hm, 2,11,11,L0\|L1},
	3392
	3393	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNBX_B, 2,11,11,L0\|L1},
	3394	{&upd7810_device::SUBNBX_D, 2,11,11,L0\|L1}, {&upd7810_device::SUBNBX_H, 2,11,11,L0\|L1},
	3395	{&upd7810_device::SUBNBX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::SUBNBX_Hp, 2,11,11,L0\|L1},
	3396	{&upd7810_device::SUBNBX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::SUBNBX_Hm, 2,11,11,L0\|L1},
	3397	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::LTAX_B, 2,11,11,L0\|L1},
	3398	{&upd7810_device::LTAX_D, 2,11,11,L0\|L1}, {&upd7810_device::LTAX_H, 2,11,11,L0\|L1},
	3399	{&upd7810_device::LTAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::LTAX_Hp, 2,11,11,L0\|L1},
	3400	{&upd7810_device::LTAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::LTAX_Hm, 2,11,11,L0\|L1},
	3401
	3402	/* 0xC0 - 0xDF */
	3403	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDX_B, 2,11,11,L0\|L1},
	3404	{&upd7810_device::ADDX_D, 2,11,11,L0\|L1}, {&upd7810_device::ADDX_H, 2,11,11,L0\|L1},
	3405	{&upd7810_device::ADDX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ADDX_Hp, 2,11,11,L0\|L1},
	3406	{&upd7810_device::ADDX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ADDX_Hm, 2,11,11,L0\|L1},
	3407	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ONAX_B, 2,11,11,L0\|L1},
	3408	{&upd7810_device::ONAX_D, 2,11,11,L0\|L1}, {&upd7810_device::ONAX_H, 2,11,11,L0\|L1},
	3409	{&upd7810_device::ONAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ONAX_Hp, 2,11,11,L0\|L1},
	3410	{&upd7810_device::ONAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ONAX_Hm, 2,11,11,L0\|L1},
	3411
	3412	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADCX_B, 2,11,11,L0\|L1},
	3413	{&upd7810_device::ADCX_D, 2,11,11,L0\|L1}, {&upd7810_device::ADCX_H, 2,11,11,L0\|L1},
	3414	{&upd7810_device::ADCX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ADCX_Hp, 2,11,11,L0\|L1},
	3415	{&upd7810_device::ADCX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ADCX_Hm, 2,11,11,L0\|L1},
	3416	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFAX_B, 2,11,11,L0\|L1},
	3417	{&upd7810_device::OFFAX_D, 2,11,11,L0\|L1}, {&upd7810_device::OFFAX_H, 2,11,11,L0\|L1},
	3418	{&upd7810_device::OFFAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::OFFAX_Hp, 2,11,11,L0\|L1},
	3419	{&upd7810_device::OFFAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::OFFAX_Hm, 2,11,11,L0\|L1},
	3420
	3421	/* 0xE0 - 0xFF */
	3422	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBX_B, 2,11,11,L0\|L1},
	3423	{&upd7810_device::SUBX_D, 2,11,11,L0\|L1}, {&upd7810_device::SUBX_H, 2,11,11,L0\|L1},
	3424	{&upd7810_device::SUBX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::SUBX_Hp, 2,11,11,L0\|L1},
	3425	{&upd7810_device::SUBX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::SUBX_Hm, 2,11,11,L0\|L1},
	3426	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::NEAX_B, 2,11,11,L0\|L1},
	3427	{&upd7810_device::NEAX_D, 2,11,11,L0\|L1}, {&upd7810_device::NEAX_H, 2,11,11,L0\|L1},
	3428	{&upd7810_device::NEAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::NEAX_Hp, 2,11,11,L0\|L1},
	3429	{&upd7810_device::NEAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::NEAX_Hm, 2,11,11,L0\|L1},
	3430
	3431	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SBBX_B, 2,11,11,L0\|L1},
	3432	{&upd7810_device::SBBX_D, 2,11,11,L0\|L1}, {&upd7810_device::SBBX_H, 2,11,11,L0\|L1},
	3433	{&upd7810_device::SBBX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::SBBX_Hp, 2,11,11,L0\|L1},
	3434	{&upd7810_device::SBBX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::SBBX_Hm, 2,11,11,L0\|L1},
	3435	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::EQAX_B, 2,11,11,L0\|L1},
	3436	{&upd7810_device::EQAX_D, 2,11,11,L0\|L1}, {&upd7810_device::EQAX_H, 2,11,11,L0\|L1},
	3437	{&upd7810_device::EQAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::EQAX_Hp, 2,11,11,L0\|L1},
	3438	{&upd7810_device::EQAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::EQAX_Hm, 2,11,11,L0\|L1}
	3439	};
	3440
	3441	/* prefix 74 */
	3442	const struct upd7810_device::opcode_s upd7810_device::s_op74_7801[256] =
	3443	{
	3444	/* 0x00 - 0x1F */
	3445	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3446	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3447	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3448	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3449	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3450	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3451	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3452	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3453
	3454	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3455	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3456	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3457	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3458	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3459	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3460	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3461	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3462
	3463	/* 0x20 - 0x3F */
	3464	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3465	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3466	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3467	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3468	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3469	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3470	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3471	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3472
	3473	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3474	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3475	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3476	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3477	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3478	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3479	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3480	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3481
	3482	/* 0x40 - 0x5F */
	3483	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3484	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3485	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3486	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3487	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3488	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3489	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3490	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3491
	3492	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3493	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3494	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3495	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3496	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3497	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3498	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3499	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3500
	3501	/* 0x60 - 0x7F */
	3502	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3503	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3504	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3505	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3506	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3507	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3508	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3509	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3510
	3511	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3512	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3513	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3514	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3515	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3516	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3517	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3518	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3519
	3520	/* 0x80 - 0x9F */
	3521	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3522	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3523	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3524	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3525	{&upd7810_device::ANAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3526	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3527	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3528	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3529
	3530	{&upd7810_device::XRAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3531	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3532	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3533	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3534	{&upd7810_device::ORAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3535	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3536	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3537	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3538
	3539	/* 0xA0 - 0xBF */
	3540	{&upd7810_device::ADDNCW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3541	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3542	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3543	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3544	{&upd7810_device::GTAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3545	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3546	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3547	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3548
	3549	{&upd7810_device::SUBNBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3550	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3551	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3552	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3553	{&upd7810_device::LTAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3554	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3555	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3556	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3557
	3558	/* 0xC0 - 0xDF */
	3559	{&upd7810_device::ADDW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3560	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3561	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3562	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3563	{&upd7810_device::ONAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3564	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3565	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3566	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3567
	3568	{&upd7810_device::ADCW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3569	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3570	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3571	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3572	{&upd7810_device::OFFAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3573	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3574	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3575	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3576
	3577	/* 0xE0 - 0xFF */
	3578	{&upd7810_device::SUBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3579	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3580	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3581	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3582	{&upd7810_device::NEAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3583	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3584	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3585	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3586
	3587	{&upd7810_device::SBBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3588	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3589	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3590	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3591	{&upd7810_device::EQAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3592	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3593	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3594	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
	3595	};
	3596
	3597	const struct upd7810_device::opcode_s upd7810_device::s_opXX_7801[256] =
	3598	{
	3599	/* 0x00 - 0x1F */
	3600	{&upd7810_device::NOP, 1, 4, 4,L0\|L1}, {&upd7810_device::HALT, 1, 6, 6,L0\|L1},
	3601	{&upd7810_device::INX_SP, 1, 7, 7,L0\|L1}, {&upd7810_device::DCX_SP, 1, 7, 7,L0\|L1},
	3602	{&upd7810_device::LXI_S_w, 3,10,10,L0\|L1}, {&upd7810_device::ANIW_wa_xx, 3,16,16,L0\|L1},
	3603	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::ANI_A_xx, 2, 7, 7,L0\|L1},
	3604	{&upd7810_device::RET, 1,11,11,L0\|L1}, {&upd7810_device::SIO, 1, 4, 4,L0\|L1},
	3605	{&upd7810_device::MOV_A_B, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_A_C, 1, 4, 4,L0\|L1},
	3606	{&upd7810_device::MOV_A_D, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_A_E, 1, 4, 4,L0\|L1},
	3607	{&upd7810_device::MOV_A_H, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_A_L, 1, 4, 4,L0\|L1},
	3608
	3609	{&upd7810_device::EXA, 1, 4, 4,L0\|L1}, {&upd7810_device::EXX, 1, 4, 4,L0\|L1},
	3610	{&upd7810_device::INX_BC, 1, 7, 7,L0\|L1}, {&upd7810_device::DCX_BC, 1, 7, 7,L0\|L1},
	3611	{&upd7810_device::LXI_B_w, 3,10,10,L0\|L1}, {&upd7810_device::ORIW_wa_xx, 3,16,16,L0\|L1},
	3612	{&upd7810_device::XRI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::ORI_A_xx, 2, 7, 7,L0\|L1},
	3613	{&upd7810_device::RETS, 1,11,11,L0\|L1}, {&upd7810_device::STM_7801, 1, 4, 4,L0\|L1},
	3614	{&upd7810_device::MOV_B_A, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_C_A, 1, 4, 4,L0\|L1},
	3615	{&upd7810_device::MOV_D_A, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_E_A, 1, 4, 4,L0\|L1},
	3616	{&upd7810_device::MOV_H_A, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_L_A, 1, 4, 4,L0\|L1},
	3617
	3618	/* 0x20 - 0x3F */
	3619	{&upd7810_device::INRW_wa_7801, 2,13,13,L0\|L1}, {&upd7810_device::TABLE, 1,19,19,L0\|L1},
	3620	{&upd7810_device::INX_DE, 1, 7, 7,L0\|L1}, {&upd7810_device::DCX_DE, 1, 7, 7,L0\|L1},
	3621	{&upd7810_device::LXI_D_w, 3,10,10,L0\|L1}, {&upd7810_device::GTIW_wa_xx, 3,13,13,L0\|L1},
	3622	{&upd7810_device::ADINC_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::GTI_A_xx, 2, 7, 7,L0\|L1},
	3623	{&upd7810_device::LDAW_wa, 2,10,10,L0\|L1}, {&upd7810_device::LDAX_B, 1, 7, 7,L0\|L1},
	3624	{&upd7810_device::LDAX_D, 1, 7, 7,L0\|L1}, {&upd7810_device::LDAX_H, 1, 7, 7,L0\|L1},
	3625	{&upd7810_device::LDAX_Dp, 1, 7, 7,L0\|L1}, {&upd7810_device::LDAX_Hp, 1, 7, 7,L0\|L1},
	3626	{&upd7810_device::LDAX_Dm, 1, 7, 7,L0\|L1}, {&upd7810_device::LDAX_Hm, 1, 7, 7,L0\|L1},
	3627
	3628	{&upd7810_device::DCRW_wa_7801, 2,13,13,L0\|L1}, {&upd7810_device::BLOCK, 1,13,13,L0\|L1},
	3629	{&upd7810_device::INX_HL, 1, 7, 7,L0\|L1}, {&upd7810_device::DCX_HL, 1, 7, 7,L0\|L1},
	3630	{&upd7810_device::LXI_H_w, 3,10,10, L1}, {&upd7810_device::LTIW_wa_xx, 3,13,13,L0\|L1},
	3631	{&upd7810_device::SUINB_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::LTI_A_xx, 2, 7, 7,L0\|L1},
	3632	{&upd7810_device::STAW_wa, 2,10,10,L0\|L1}, {&upd7810_device::STAX_B, 1, 7, 7,L0\|L1},
	3633	{&upd7810_device::STAX_D, 1, 7, 7,L0\|L1}, {&upd7810_device::STAX_H, 1, 7, 7,L0\|L1},
	3634	{&upd7810_device::STAX_Dp, 1, 7, 7,L0\|L1}, {&upd7810_device::STAX_Hp, 1, 7, 7,L0\|L1},
	3635	{&upd7810_device::STAX_Dm, 1, 7, 7,L0\|L1}, {&upd7810_device::STAX_Hm, 1, 7, 7,L0\|L1},
	3636
	3637	/* 0x40 - 0x5F */
	3638	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::INR_A_7801, 1, 4, 4,L0\|L1},
	3639	{&upd7810_device::INR_B_7801, 1, 4, 4,L0\|L1}, {&upd7810_device::INR_C_7801, 1, 4, 4,L0\|L1},
	3640	{&upd7810_device::CALL_w, 3,16,16,L0\|L1}, {&upd7810_device::ONIW_wa_xx, 3,13,13,L0\|L1},
	3641	{&upd7810_device::ADI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::ONI_A_xx, 2, 7, 7,L0\|L1},
	3642	{&upd7810_device::PRE_48, 1, 0, 0,L0\|L1}, {&upd7810_device::MVIX_BC_xx, 2,10,10,L0\|L1},
	3643	{&upd7810_device::MVIX_DE_xx, 2,10,10,L0\|L1}, {&upd7810_device::MVIX_HL_xx, 2,10,10,L0\|L1},
	3644	{&upd7810_device::PRE_4C, 1, 0, 0,L0\|L1}, {&upd7810_device::PRE_4D, 1, 0, 0,L0\|L1},
	3645	{&upd7810_device::JRE, 2,17,17,L0\|L1}, {&upd7810_device::JRE, 2,17,17,L0\|L1},
	3646
	3647	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::DCR_A_7801, 1, 4, 4,L0\|L1},
	3648	{&upd7810_device::DCR_B_7801, 1, 4, 4,L0\|L1}, {&upd7810_device::DCR_C_7801, 1, 4, 4,L0\|L1},
	3649	{&upd7810_device::JMP_w, 3,10,10,L0\|L1}, {&upd7810_device::OFFIW_wa_xx, 3,13,13,L0\|L1},
	3650	{&upd7810_device::ACI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::OFFI_A_xx, 2, 7, 7,L0\|L1},
	3651	{&upd7810_device::BIT_0_wa, 2,10,10,L0\|L1}, {&upd7810_device::BIT_1_wa, 2,10,10,L0\|L1},
	3652	{&upd7810_device::BIT_2_wa, 2,10,10,L0\|L1}, {&upd7810_device::BIT_3_wa, 2,10,10,L0\|L1},
	3653	{&upd7810_device::BIT_4_wa, 2,10,10,L0\|L1}, {&upd7810_device::BIT_5_wa, 2,10,10,L0\|L1},
	3654	{&upd7810_device::BIT_6_wa, 2,10,10,L0\|L1}, {&upd7810_device::BIT_7_wa, 2,10,10,L0\|L1},
	3655
	3656	/* 0x60 - 0x7F */
	3657	{&upd7810_device::PRE_60, 1, 0, 0,L0\|L1}, {&upd7810_device::DAA, 1, 4, 4,L0\|L1},
	3658	{&upd7810_device::RETI, 1,15,15,L0\|L1}, {&upd7810_device::CALB, 2,13,13,L0\|L1},
	3659	{&upd7810_device::PRE_64, 1, 0, 0,L0\|L1}, {&upd7810_device::NEIW_wa_xx, 3,13,13,L0\|L1},
	3660	{&upd7810_device::SUI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::NEI_A_xx, 2, 7, 7,L0\|L1},
	3661	{&upd7810_device::MVI_V_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::MVI_A_xx, 2, 7, 7,L0 },
	3662	{&upd7810_device::MVI_B_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::MVI_C_xx, 2, 7, 7,L0\|L1},
	3663	{&upd7810_device::MVI_D_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::MVI_E_xx, 2, 7, 7,L0\|L1},
	3664	{&upd7810_device::MVI_H_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::MVI_L_xx, 2, 7, 7, L1},
	3665
	3666	{&upd7810_device::PRE_70, 1, 0, 0,L0\|L1}, {&upd7810_device::MVIW_wa_xx, 3,13,13,L0\|L1},
	3667	{&upd7810_device::SOFTI, 1,19,19,L0\|L1}, {&upd7810_device::JB, 1, 4, 4,L0\|L1},
	3668	{&upd7810_device::PRE_74, 1, 0, 0,L0\|L1}, {&upd7810_device::EQIW_wa_xx, 3,13,13,L0\|L1},
	3669	{&upd7810_device::SBI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::EQI_A_xx, 2, 7, 7,L0\|L1},
	3670	{&upd7810_device::CALF, 2,16,16,L0\|L1}, {&upd7810_device::CALF, 2,16,16,L0\|L1},
	3671	{&upd7810_device::CALF, 2,16,16,L0\|L1}, {&upd7810_device::CALF, 2,16,16,L0\|L1},
	3672	{&upd7810_device::CALF, 2,16,16,L0\|L1}, {&upd7810_device::CALF, 2,16,16,L0\|L1},
	3673	{&upd7810_device::CALF, 2,16,16,L0\|L1}, {&upd7810_device::CALF, 2,16,16,L0\|L1},
	3674
	3675	/* 0x80 - 0x9F */
	3676	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3677	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3678	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3679	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3680	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3681	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3682	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3683	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3684
	3685	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3686	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3687	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3688	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3689	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3690	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3691	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3692	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3693
	3694	/* 0xA0 - 0xBF */
	3695	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3696	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3697	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3698	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3699	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3700	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3701	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3702	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3703
	3704	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3705	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3706	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3707	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3708	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3709	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3710	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3711	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	3712
	3713	/* 0xC0 - 0xDF */
	3714	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3715	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3716	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3717	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3718	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3719	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3720	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3721	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3722
	3723	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3724	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3725	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3726	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3727	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3728	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3729	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3730	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3731
	3732	/* 0xE0 - 0xFF */
	3733	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3734	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3735	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3736	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3737	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3738	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3739	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3740	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3741
	3742	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3743	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3744	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3745	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3746	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3747	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3748	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1},
	3749	{&upd7810_device::JR, 1,13,13,L0\|L1}, {&upd7810_device::JR, 1,13,13,L0\|L1}
	3750	};
	3751
	3752	/***********************************************************************
	3753	*
	3754	* uPD78C05(A)
	3755	*
	3756	**********************************************************************/
	3757
	3758	const struct upd7810_device::opcode_s upd7810_device::s_op48_78c05[256] =
	3759	{
	3760	/* 0x00 - 0x1F */
	3761	{&upd7810_device::SKIT_F0, 2, 8, 8,L0\|L1}, {&upd7810_device::SKIT_FT0, 2, 8, 8,L0\|L1},
	3762	{&upd7810_device::SKIT_F1, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3763	{&upd7810_device::SKIT_FST, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3764	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3765	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3766	{&upd7810_device::SK_CY, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3767	{&upd7810_device::SK_Z, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3768	{&upd7810_device::PUSH_VA, 2,17,17,L0\|L1}, {&upd7810_device::POP_VA, 2,14,14,L0\|L1},
	3769
	3770	{&upd7810_device::SKNIT_F0, 2, 8, 8,L0\|L1}, {&upd7810_device::SKNIT_FT0, 2, 8, 8,L0\|L1},
	3771	{&upd7810_device::SKNIT_F1, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3772	{&upd7810_device::SKNIT_FST, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3773	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3774	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3775	{&upd7810_device::SKN_CY, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3776	{&upd7810_device::SKN_Z, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3777	{&upd7810_device::PUSH_BC, 2,17,17,L0\|L1}, {&upd7810_device::POP_BC, 2,14,14,L0\|L1},
	3778
	3779	/* 0x20 - 0x3F */
	3780	{&upd7810_device::EI, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3781	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3782	{&upd7810_device::DI, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3783	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3784	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3785	{&upd7810_device::CLC, 2, 8, 8,L0\|L1}, {&upd7810_device::STC, 2, 8, 8,L0\|L1},
	3786	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::PEX, 2,11,11,L0\|L1},
	3787	{&upd7810_device::PUSH_DE, 2,17,17,L0\|L1}, {&upd7810_device::POP_DE, 2,14,14,L0\|L1},
	3788
	3789	{&upd7810_device::RLL_A, 2, 8, 8,L0\|L1}, {&upd7810_device::RLR_A, 2, 8, 8,L0\|L1},
	3790	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3791	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3792	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3793	{&upd7810_device::RLD, 2,17,17,L0\|L1}, {&upd7810_device::RRD, 2,17,17,L0\|L1},
	3794	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3795	{&upd7810_device::PER, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3796	{&upd7810_device::PUSH_HL, 2,17,17,L0\|L1}, {&upd7810_device::POP_HL, 2,14,14,L0\|L1},
	3797
	3798	/* 0x40 - 0x5F */
	3799	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3800	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3801	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3802	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3803	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3804	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3805	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3806	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3807
	3808	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3809	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3810	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3811	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3812	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3813	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3814	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3815	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3816
	3817	/* 0x60 - 0x7F */
	3818	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3819	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3820	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3821	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3822	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3823	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3824	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3825	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3826
	3827	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3828	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3829	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3830	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3831	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3832	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3833	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3834	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3835
	3836	/* 0x80 - 0x9F */
	3837	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3838	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3839	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3840	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3841	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3842	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3843	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3844	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3845
	3846	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3847	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3848	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3849	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3850	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3851	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3852	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3853	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3854
	3855	/* 0xA0 - 0xBF */
	3856	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3857	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3858	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3859	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3860	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3861	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3862	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3863	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3864
	3865	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3866	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3867	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3868	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3869	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3870	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3871	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3872	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3873
	3874	/* 0xC0 - 0xDF */
	3875	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3876	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3877	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3878	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3879	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3880	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3881	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3882	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3883
	3884	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3885	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3886	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3887	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3888	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3889	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3890	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3891	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3892
	3893	/* 0xE0 - 0xFF */
	3894	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3895	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3896	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3897	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3898	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3899	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3900	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3901	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3902
	3903	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3904	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3905	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3906	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3907	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3908	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3909	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3910	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
	3911	};
	3912
	3913	const struct upd7810_device::opcode_s upd7810_device::s_op4C_78c05[256] =
	3914	{
	3915	/* 0x00 - 0x1F */
	3916	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3917	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3918	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3919	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3920	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3921	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3922	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3923	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3924
	3925	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3926	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3927	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3928	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3929	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3930	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3931	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3932	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3933
	3934	/* 0x20 - 0x3F */
	3935	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3936	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3937	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3938	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3939	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3940	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3941	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3942	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3943
	3944	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3945	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3946	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3947	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3948	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3949	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3950	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3951	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3952
	3953	/* 0x40 - 0x5F */
	3954	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3955	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3956	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3957	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3958	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3959	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3960	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3961	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3962
	3963	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3964	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3965	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3966	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3967	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3968	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3969	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3970	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3971
	3972	/* 0x60 - 0x7F */
	3973	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3974	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3975	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3976	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3977	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3978	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3979	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3980	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3981
	3982	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3983	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3984	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3985	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3986	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3987	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3988	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3989	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3990
	3991	/* 0x80 - 0x9F */
	3992	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3993	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3994	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3995	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3996	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3997	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3998	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	3999	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4000
	4001	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4002	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4003	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4004	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4005	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4006	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4007	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4008	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4009
	4010	/* 0xA0 - 0xBF */
	4011	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4012	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4013	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4014	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4015	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4016	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4017	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4018	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4019
	4020	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4021	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4022	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4023	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4024	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4025	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4026	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4027	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4028
	4029	/* 0xC0 - 0xDF */
	4030	{&upd7810_device::MOV_A_PA, 2,10,10,L0\|L1}, {&upd7810_device::MOV_A_PB, 2,10,10,L0\|L1},
	4031	{&upd7810_device::MOV_A_PC, 2,10,10,L0\|L1}, {&upd7810_device::MOV_A_MKL, 2,10,10,L0\|L1},
	4032	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4033	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4034	{&upd7810_device::MOV_A_S, 2,10,10,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4035	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4036	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4037	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4038
	4039	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4040	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4041	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4042	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4043	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4044	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4045	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4046	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4047
	4048	/* 0xE0 - 0xFF */
	4049	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4050	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4051	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4052	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4053	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4054	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4055	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4056	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4057
	4058	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4059	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4060	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4061	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4062	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4063	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4064	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4065	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
	4066	};
	4067
	4068	/* prefix 4D */
	4069	const struct upd7810_device::opcode_s upd7810_device::s_op4D_78c05[256] =
	4070	{
	4071	/* 0x00 - 0x1F */
	4072	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4073	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4074	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4075	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4076	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4077	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4078	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4079	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4080
	4081	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4082	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4083	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4084	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4085	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4086	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4087	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4088	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4089
	4090	/* 0x20 - 0x3F */
	4091	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4092	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4093	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4094	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4095	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4096	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4097	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4098	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4099
	4100	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4101	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4102	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4103	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4104	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4105	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4106	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4107	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4108
	4109	/* 0x40 - 0x5F */
	4110	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4111	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4112	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4113	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4114	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4115	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4116	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4117	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4118
	4119	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4120	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4121	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4122	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4123	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4124	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4125	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4126	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4127
	4128	/* 0x60 - 0x7F */
	4129	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4130	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4131	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4132	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4133	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4134	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4135	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4136	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4137
	4138	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4139	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4140	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4141	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4142	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4143	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4144	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4145	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4146
	4147	/* 0x80 - 0x9F */
	4148	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4149	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4150	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4151	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4152	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4153	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4154	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4155	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4156
	4157	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4158	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4159	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4160	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4161	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4162	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4163	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4164	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4165
	4166	/* 0xA0 - 0xBF */
	4167	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4168	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4169	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4170	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4171	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4172	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4173	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4174	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4175
	4176	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4177	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4178	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4179	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4180	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4181	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4182	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4183	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4184
	4185	/* 0xC0 - 0xDF */
	4186	{&upd7810_device::MOV_PA_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_PB_A, 2,10,10,L0\|L1},
	4187	{&upd7810_device::MOV_PC_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_MKL_A, 2,10,10,L0\|L1},
	4188	{&upd7810_device::MOV_MB_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_MC_A, 2,10,10,L0\|L1},
	4189	{&upd7810_device::MOV_TM0_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_TM1_A, 2,10,10,L0\|L1},
	4190	{&upd7810_device::MOV_S_A, 2,10,10,L0\|L1}, {&upd7810_device::MOV_TMM_A, 2,10,10,L0\|L1},
	4191	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4192	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4193	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4194
	4195	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4196	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4197	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4198	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4199	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4200	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4201	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4202	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4203
	4204	/* 0xE0 - 0xFF */
	4205	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4206	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4207	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4208	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4209	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4210	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4211	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4212	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4213
	4214	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4215	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4216	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4217	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4218	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4219	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4220	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4221	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
	4222	};
	4223
	4224	/* prefix 60 */
	4225	const struct upd7810_device::opcode_s upd7810_device::s_op60_78c05[256] =
	4226	{
	4227	/* 0x00 - 0x1F */
	4228	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4229	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4230	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4231	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4232	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_A, 2, 8, 8,L0\|L1},
	4233	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4234	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4235	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4236
	4237	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_A, 2, 8, 8,L0\|L1},
	4238	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4239	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4240	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4241	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_A, 2, 8, 8,L0\|L1},
	4242	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4243	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4244	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4245
	4246	/* 0x20 - 0x3F */
	4247	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_A, 2, 8, 8,L0\|L1},
	4248	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4249	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4250	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4251	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_A, 2, 8, 8,L0\|L1},
	4252	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4253	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4254	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4255
	4256	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_A, 2, 8, 8,L0\|L1},
	4257	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4258	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4259	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4260	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_A, 2, 8, 8,L0\|L1},
	4261	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4262	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4263	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4264
	4265	/* 0x40 - 0x5F */
	4266	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_A, 2, 8, 8,L0\|L1},
	4267	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4268	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4269	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4270	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4271	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4272	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4273	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4274
	4275	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_A, 2, 8, 8,L0\|L1},
	4276	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4277	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4278	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4279	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4280	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4281	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4282	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4283	/* 0x60 - 0x7F */
	4284	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_A, 2, 8, 8,L0\|L1},
	4285	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4286	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4287	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4288	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_A, 2, 8, 8,L0\|L1},
	4289	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4290	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4291	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4292
	4293	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_A, 2, 8, 8,L0\|L1},
	4294	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4295	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4296	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4297	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_A, 2, 8, 8,L0\|L1},
	4298	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4299	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4300	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4301
	4302	/* 0x80 - 0x9F */
	4303	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4304	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4305	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4306	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4307	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_A, 2, 8, 8,L0\|L1},
	4308	{&upd7810_device::ANA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_C, 2, 8, 8,L0\|L1},
	4309	{&upd7810_device::ANA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_E, 2, 8, 8,L0\|L1},
	4310	{&upd7810_device::ANA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ANA_A_L, 2, 8, 8,L0\|L1},
	4311
	4312	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_A, 2, 8, 8,L0\|L1},
	4313	{&upd7810_device::XRA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_C, 2, 8, 8,L0\|L1},
	4314	{&upd7810_device::XRA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_E, 2, 8, 8,L0\|L1},
	4315	{&upd7810_device::XRA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::XRA_A_L, 2, 8, 8,L0\|L1},
	4316	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_A, 2, 8, 8,L0\|L1},
	4317	{&upd7810_device::ORA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_C, 2, 8, 8,L0\|L1},
	4318	{&upd7810_device::ORA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_E, 2, 8, 8,L0\|L1},
	4319	{&upd7810_device::ORA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ORA_A_L, 2, 8, 8,L0\|L1},
	4320
	4321	/* 0xA0 - 0xBF */
	4322	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_A, 2, 8, 8,L0\|L1},
	4323	{&upd7810_device::ADDNC_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_C, 2, 8, 8,L0\|L1},
	4324	{&upd7810_device::ADDNC_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_E, 2, 8, 8,L0\|L1},
	4325	{&upd7810_device::ADDNC_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNC_A_L, 2, 8, 8,L0\|L1},
	4326	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_A, 2, 8, 8,L0\|L1},
	4327	{&upd7810_device::GTA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_C, 2, 8, 8,L0\|L1},
	4328	{&upd7810_device::GTA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_E, 2, 8, 8,L0\|L1},
	4329	{&upd7810_device::GTA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::GTA_A_L, 2, 8, 8,L0\|L1},
	4330
	4331	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_A, 2, 8, 8,L0\|L1},
	4332	{&upd7810_device::SUBNB_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_C, 2, 8, 8,L0\|L1},
	4333	{&upd7810_device::SUBNB_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_E, 2, 8, 8,L0\|L1},
	4334	{&upd7810_device::SUBNB_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNB_A_L, 2, 8, 8,L0\|L1},
	4335	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_A, 2, 8, 8,L0\|L1},
	4336	{&upd7810_device::LTA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_C, 2, 8, 8,L0\|L1},
	4337	{&upd7810_device::LTA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_E, 2, 8, 8,L0\|L1},
	4338	{&upd7810_device::LTA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::LTA_A_L, 2, 8, 8,L0\|L1},
	4339
	4340	/* 0xC0 - 0xDF */
	4341	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_A, 2, 8, 8,L0\|L1},
	4342	{&upd7810_device::ADD_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_C, 2, 8, 8,L0\|L1},
	4343	{&upd7810_device::ADD_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_E, 2, 8, 8,L0\|L1},
	4344	{&upd7810_device::ADD_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ADD_A_L, 2, 8, 8,L0\|L1},
	4345	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ONA_A_A, 2, 8, 8,L0\|L1},
	4346	{&upd7810_device::ONA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ONA_A_C, 2, 8, 8,L0\|L1},
	4347	{&upd7810_device::ONA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ONA_A_E, 2, 8, 8,L0\|L1},
	4348	{&upd7810_device::ONA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ONA_A_L, 2, 8, 8,L0\|L1},
	4349
	4350	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_A, 2, 8, 8,L0\|L1},
	4351	{&upd7810_device::ADC_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_C, 2, 8, 8,L0\|L1},
	4352	{&upd7810_device::ADC_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_E, 2, 8, 8,L0\|L1},
	4353	{&upd7810_device::ADC_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::ADC_A_L, 2, 8, 8,L0\|L1},
	4354	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFA_A_A, 2, 8, 8,L0\|L1},
	4355	{&upd7810_device::OFFA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFA_A_C, 2, 8, 8,L0\|L1},
	4356	{&upd7810_device::OFFA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFA_A_E, 2, 8, 8,L0\|L1},
	4357	{&upd7810_device::OFFA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFA_A_L, 2, 8, 8,L0\|L1},
	4358
	4359	/* 0xE0 - 0xFF */
	4360	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_A, 2, 8, 8,L0\|L1},
	4361	{&upd7810_device::SUB_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_C, 2, 8, 8,L0\|L1},
	4362	{&upd7810_device::SUB_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_E, 2, 8, 8,L0\|L1},
	4363	{&upd7810_device::SUB_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_L, 2, 8, 8,L0\|L1},
	4364	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_A, 2, 8, 8,L0\|L1},
	4365	{&upd7810_device::NEA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_C, 2, 8, 8,L0\|L1},
	4366	{&upd7810_device::NEA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_E, 2, 8, 8,L0\|L1},
	4367	{&upd7810_device::NEA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::NEA_A_L, 2, 8, 8,L0\|L1},
	4368
	4369	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_A, 2, 8, 8,L0\|L1},
	4370	{&upd7810_device::SBB_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_C, 2, 8, 8,L0\|L1},
	4371	{&upd7810_device::SBB_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_E, 2, 8, 8,L0\|L1},
	4372	{&upd7810_device::SBB_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::SBB_A_L, 2, 8, 8,L0\|L1},
	4373	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_A, 2, 8, 8,L0\|L1},
	4374	{&upd7810_device::EQA_A_B, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_C, 2, 8, 8,L0\|L1},
	4375	{&upd7810_device::EQA_A_D, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_E, 2, 8, 8,L0\|L1},
	4376	{&upd7810_device::EQA_A_H, 2, 8, 8,L0\|L1}, {&upd7810_device::EQA_A_L, 2, 8, 8,L0\|L1}
	4377	};
	4378
	4379	/* prefix 64 */
	4380	const struct upd7810_device::opcode_s upd7810_device::s_op64_78c05[256] =
	4381	{
	4382	/* 0x00 - 0x1F */
	4383	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4384	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4385	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4386	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4387	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ANI_A_xx, 3,11,11,L0\|L1},
	4388	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4389	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4390	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4391
	4392	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::XRI_A_xx, 3,11,11,L0\|L1},
	4393	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4394	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4395	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4396	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ORI_A_xx, 3,11,11,L0\|L1},
	4397	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4398	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4399	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4400
	4401	/* 0x20 - 0x3F */
	4402	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADINC_A_xx, 3,11,11,L0\|L1},
	4403	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4404	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4405	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4406	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::GTI_A_xx, 3,11,11,L0\|L1},
	4407	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4408	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4409	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4410
	4411	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUINB_A_xx, 3,11,11,L0\|L1},
	4412	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4413	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4414	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4415	{&upd7810_device::illegal2, 3, 8, 8,L0\|L1}, {&upd7810_device::LTI_A_xx, 3,11,11,L0\|L1},
	4416	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4417	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4418	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4419
	4420	/* 0x40 - 0x5F */
	4421	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADI_A_xx, 3,11,11,L0\|L1},
	4422	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4423	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4424	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4425	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ONI_A_xx, 3,11,11,L0\|L1},
	4426	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4427	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4428	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4429
	4430	{&upd7810_device::illegal2, 3, 8, 8,L0\|L1}, {&upd7810_device::ACI_A_xx, 3,11,11,L0\|L1},
	4431	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4432	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4433	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4434	{&upd7810_device::illegal2, 3, 8, 8,L0\|L1}, {&upd7810_device::OFFI_A_xx, 3,11,11,L0\|L1},
	4435	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4436	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4437	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4438
	4439	/* 0x60 - 0x7F */
	4440	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUI_A_xx, 3,11,11,L0\|L1},
	4441	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4442	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4443	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4444	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::NEI_A_xx, 3,11,11,L0\|L1},
	4445	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4446	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4447	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4448
	4449	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SBI_A_xx, 3,11,11,L0\|L1},
	4450	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4451	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4452	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4453	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::EQI_A_xx, 3,11,11,L0\|L1},
	4454	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4455	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4456	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4457
	4458	/* 0x80 - 0x9F */
	4459	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4460	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4461	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4462	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4463	{&upd7810_device::ANI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ANI_PB_xx, 3,17,17,L0\|L1},
	4464	{&upd7810_device::ANI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ANI_MKL_xx, 3,17,17,L0\|L1},
	4465	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4466	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4467
	4468	{&upd7810_device::XRI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::XRI_PB_xx, 3,17,17,L0\|L1},
	4469	{&upd7810_device::XRI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::XRI_MKL_xx, 3,17,17,L0\|L1},
	4470	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4471	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4472	{&upd7810_device::ORI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ORI_PB_xx, 3,17,17,L0\|L1},
	4473	{&upd7810_device::ORI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ORI_MKL_xx, 3,17,17,L0\|L1},
	4474	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4475	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4476
	4477	/* 0xA0 - 0xBF */
	4478	{&upd7810_device::ADINC_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ADINC_PB_xx, 3,17,17,L0\|L1},
	4479	{&upd7810_device::ADINC_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ADINC_MKL_xx, 3,17,17,L0\|L1},
	4480	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4481	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4482	{&upd7810_device::GTI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::GTI_PB_xx, 3,14,14,L0\|L1},
	4483	{&upd7810_device::GTI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::GTI_MKL_xx, 3,14,14,L0\|L1},
	4484	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4485	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4486
	4487	{&upd7810_device::SUINB_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::SUINB_PB_xx, 3,17,17,L0\|L1},
	4488	{&upd7810_device::SUINB_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::SUINB_MKL_xx, 3,17,17,L0\|L1},
	4489	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4490	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4491	{&upd7810_device::LTI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::LTI_PB_xx, 3,14,14,L0\|L1},
	4492	{&upd7810_device::LTI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::LTI_MKL_xx, 3,14,14,L0\|L1},
	4493	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4494	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4495
	4496	/* 0xC0 - 0xDF */
	4497	{&upd7810_device::ADI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ADI_PB_xx, 3,17,17,L0\|L1},
	4498	{&upd7810_device::ADI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ADI_MKL_xx, 3,17,17,L0\|L1},
	4499	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4500	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4501	{&upd7810_device::ONI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::ONI_PB_xx, 3,14,14,L0\|L1},
	4502	{&upd7810_device::ONI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::ONI_MKL_xx, 3,14,14,L0\|L1},
	4503	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4504	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4505
	4506	{&upd7810_device::ACI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::ACI_PB_xx, 3,17,17,L0\|L1},
	4507	{&upd7810_device::ACI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::ACI_MKL_xx, 3,17,17,L0\|L1},
	4508	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4509	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4510	{&upd7810_device::OFFI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::OFFI_PB_xx, 3,14,14,L0\|L1},
	4511	{&upd7810_device::OFFI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::OFFI_MKL_xx, 3,14,14,L0\|L1},
	4512	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4513	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4514
	4515	/* 0xE0 - 0xFF */
	4516	{&upd7810_device::SUI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::SUI_PB_xx, 3,17,17,L0\|L1},
	4517	{&upd7810_device::SUI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::SUI_MKL_xx, 3,17,17,L0\|L1},
	4518	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4519	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4520	{&upd7810_device::NEI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::NEI_PB_xx, 3,14,14,L0\|L1},
	4521	{&upd7810_device::NEI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::NEI_MKL_xx, 3,14,14,L0\|L1},
	4522	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4523	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4524
	4525	{&upd7810_device::SBI_PA_xx, 3,17,17,L0\|L1}, {&upd7810_device::SBI_PB_xx, 3,17,17,L0\|L1},
	4526	{&upd7810_device::SBI_PC_xx, 3,17,17,L0\|L1}, {&upd7810_device::SBI_MKL_xx, 3,17,17,L0\|L1},
	4527	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4528	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4529	{&upd7810_device::EQI_PA_xx, 3,14,14,L0\|L1}, {&upd7810_device::EQI_PB_xx, 3,14,14,L0\|L1},
	4530	{&upd7810_device::EQI_PC_xx, 3,14,14,L0\|L1}, {&upd7810_device::EQI_MKL_xx, 3,14,14,L0\|L1},
	4531	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4532	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
	4533	};
	4534
	4535	/* prefix 70 */
	4536	const struct upd7810_device::opcode_s upd7810_device::s_op70_78c05[256] =
	4537	{
	4538	/* 0x00 - 0x1F */
	4539	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4540	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4541	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4542	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4543	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4544	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4545	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4546	{&upd7810_device::SSPD_w, 4,20,20,L0\|L1}, {&upd7810_device::LSPD_w, 4,20,20,L0\|L1},
	4547
	4548	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4549	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4550	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4551	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4552	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4553	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4554	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4555	{&upd7810_device::SBCD_w, 4,20,20,L0\|L1}, {&upd7810_device::LBCD_w, 4,20,20,L0\|L1},
	4556
	4557	/* 0x20 - 0x3F */
	4558	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4559	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4560	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4561	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4562	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4563	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4564	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4565	{&upd7810_device::SDED_w, 4,20,20,L0\|L1}, {&upd7810_device::LDED_w, 4,20,20,L0\|L1},
	4566
	4567	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4568	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4569	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4570	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4571	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4572	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4573	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4574	{&upd7810_device::SHLD_w, 4,20,20,L0\|L1}, {&upd7810_device::LHLD_w, 4,20,20,L0\|L1},
	4575
	4576	/* 0x40 - 0x5F */
	4577	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4578	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4579	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4580	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4581	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4582	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4583	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4584	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4585
	4586	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4587	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4588	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4589	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4590	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4591	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4592	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4593	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4594
	4595	/* 0x60 - 0x7F */
	4596	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4597	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4598	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4599	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4600	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::MOV_A_w, 4,17,17,L0\|L1},
	4601	{&upd7810_device::MOV_B_w, 4,17,17,L0\|L1}, {&upd7810_device::MOV_C_w, 4,17,17,L0\|L1},
	4602	{&upd7810_device::MOV_D_w, 4,17,17,L0\|L1}, {&upd7810_device::MOV_E_w, 4,17,17,L0\|L1},
	4603	{&upd7810_device::MOV_H_w, 4,17,17,L0\|L1}, {&upd7810_device::MOV_L_w, 4,17,17,L0\|L1},
	4604
	4605	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4606	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4607	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4608	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4609	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::MOV_w_A, 4,17,17,L0\|L1},
	4610	{&upd7810_device::MOV_w_B, 4,17,17,L0\|L1}, {&upd7810_device::MOV_w_C, 4,17,17,L0\|L1},
	4611	{&upd7810_device::MOV_w_D, 4,17,17,L0\|L1}, {&upd7810_device::MOV_w_E, 4,17,17,L0\|L1},
	4612	{&upd7810_device::MOV_w_H, 4,17,17,L0\|L1}, {&upd7810_device::MOV_w_L, 4,17,17,L0\|L1},
	4613
	4614	/* 0x80 - 0x9F */
	4615	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4616	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4617	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4618	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4619	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ANAX_B, 2,11,11,L0\|L1},
	4620	{&upd7810_device::ANAX_D, 2,11,11,L0\|L1}, {&upd7810_device::ANAX_H, 2,11,11,L0\|L1},
	4621	{&upd7810_device::ANAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ANAX_Hp, 2,11,11,L0\|L1},
	4622	{&upd7810_device::ANAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ANAX_Hm, 2,11,11,L0\|L1},
	4623
	4624	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::XRAX_B, 2,11,11,L0\|L1},
	4625	{&upd7810_device::XRAX_D, 2,11,11,L0\|L1}, {&upd7810_device::XRAX_H, 2,11,11,L0\|L1},
	4626	{&upd7810_device::XRAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::XRAX_Hp, 2,11,11,L0\|L1},
	4627	{&upd7810_device::XRAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::XRAX_Hm, 2,11,11,L0\|L1},
	4628	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ORAX_B, 2,11,11,L0\|L1},
	4629	{&upd7810_device::ORAX_D, 2,11,11,L0\|L1}, {&upd7810_device::ORAX_H, 2,11,11,L0\|L1},
	4630	{&upd7810_device::ORAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ORAX_Hp, 2,11,11,L0\|L1},
	4631	{&upd7810_device::ORAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ORAX_Hm, 2,11,11,L0\|L1},
	4632
	4633	/* 0xA0 - 0xBF */
	4634	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDNCX_B, 2,11,11,L0\|L1},
	4635	{&upd7810_device::ADDNCX_D, 2,11,11,L0\|L1}, {&upd7810_device::ADDNCX_H, 2,11,11,L0\|L1},
	4636	{&upd7810_device::ADDNCX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ADDNCX_Hp, 2,11,11,L0\|L1},
	4637	{&upd7810_device::ADDNCX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ADDNCX_Hm, 2,11,11,L0\|L1},
	4638	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::GTAX_B, 2,11,11,L0\|L1},
	4639	{&upd7810_device::GTAX_D, 2,11,11,L0\|L1}, {&upd7810_device::GTAX_H, 2,11,11,L0\|L1},
	4640	{&upd7810_device::GTAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::GTAX_Hp, 2,11,11,L0\|L1},
	4641	{&upd7810_device::GTAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::GTAX_Hm, 2,11,11,L0\|L1},
	4642
	4643	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBNBX_B, 2,11,11,L0\|L1},
	4644	{&upd7810_device::SUBNBX_D, 2,11,11,L0\|L1}, {&upd7810_device::SUBNBX_H, 2,11,11,L0\|L1},
	4645	{&upd7810_device::SUBNBX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::SUBNBX_Hp, 2,11,11,L0\|L1},
	4646	{&upd7810_device::SUBNBX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::SUBNBX_Hm, 2,11,11,L0\|L1},
	4647	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::LTAX_B, 2,11,11,L0\|L1},
	4648	{&upd7810_device::LTAX_D, 2,11,11,L0\|L1}, {&upd7810_device::LTAX_H, 2,11,11,L0\|L1},
	4649	{&upd7810_device::LTAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::LTAX_Hp, 2,11,11,L0\|L1},
	4650	{&upd7810_device::LTAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::LTAX_Hm, 2,11,11,L0\|L1},
	4651
	4652	/* 0xC0 - 0xDF */
	4653	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADDX_B, 2,11,11,L0\|L1},
	4654	{&upd7810_device::ADDX_D, 2,11,11,L0\|L1}, {&upd7810_device::ADDX_H, 2,11,11,L0\|L1},
	4655	{&upd7810_device::ADDX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ADDX_Hp, 2,11,11,L0\|L1},
	4656	{&upd7810_device::ADDX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ADDX_Hm, 2,11,11,L0\|L1},
	4657	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ONAX_B, 2,11,11,L0\|L1},
	4658	{&upd7810_device::ONAX_D, 2,11,11,L0\|L1}, {&upd7810_device::ONAX_H, 2,11,11,L0\|L1},
	4659	{&upd7810_device::ONAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ONAX_Hp, 2,11,11,L0\|L1},
	4660	{&upd7810_device::ONAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ONAX_Hm, 2,11,11,L0\|L1},
	4661
	4662	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::ADCX_B, 2,11,11,L0\|L1},
	4663	{&upd7810_device::ADCX_D, 2,11,11,L0\|L1}, {&upd7810_device::ADCX_H, 2,11,11,L0\|L1},
	4664	{&upd7810_device::ADCX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::ADCX_Hp, 2,11,11,L0\|L1},
	4665	{&upd7810_device::ADCX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::ADCX_Hm, 2,11,11,L0\|L1},
	4666	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::OFFAX_B, 2,11,11,L0\|L1},
	4667	{&upd7810_device::OFFAX_D, 2,11,11,L0\|L1}, {&upd7810_device::OFFAX_H, 2,11,11,L0\|L1},
	4668	{&upd7810_device::OFFAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::OFFAX_Hp, 2,11,11,L0\|L1},
	4669	{&upd7810_device::OFFAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::OFFAX_Hm, 2,11,11,L0\|L1},
	4670
	4671	/* 0xE0 - 0xFF */
	4672	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUBX_B, 2,11,11,L0\|L1},
	4673	{&upd7810_device::SUBX_D, 2,11,11,L0\|L1}, {&upd7810_device::SUBX_H, 2,11,11,L0\|L1},
	4674	{&upd7810_device::SUBX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::SUBX_Hp, 2,11,11,L0\|L1},
	4675	{&upd7810_device::SUBX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::SUBX_Hm, 2,11,11,L0\|L1},
	4676	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::NEAX_B, 2,11,11,L0\|L1},
	4677	{&upd7810_device::NEAX_D, 2,11,11,L0\|L1}, {&upd7810_device::NEAX_H, 2,11,11,L0\|L1},
	4678	{&upd7810_device::NEAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::NEAX_Hp, 2,11,11,L0\|L1},
	4679	{&upd7810_device::NEAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::NEAX_Hm, 2,11,11,L0\|L1},
	4680
	4681	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SBBX_B, 2,11,11,L0\|L1},
	4682	{&upd7810_device::SBBX_D, 2,11,11,L0\|L1}, {&upd7810_device::SBBX_H, 2,11,11,L0\|L1},
	4683	{&upd7810_device::SBBX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::SBBX_Hp, 2,11,11,L0\|L1},
	4684	{&upd7810_device::SBBX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::SBBX_Hm, 2,11,11,L0\|L1},
	4685	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::EQAX_B, 2,11,11,L0\|L1},
	4686	{&upd7810_device::EQAX_D, 2,11,11,L0\|L1}, {&upd7810_device::EQAX_H, 2,11,11,L0\|L1},
	4687	{&upd7810_device::EQAX_Dp, 2,11,11,L0\|L1}, {&upd7810_device::EQAX_Hp, 2,11,11,L0\|L1},
	4688	{&upd7810_device::EQAX_Dm, 2,11,11,L0\|L1}, {&upd7810_device::EQAX_Hm, 2,11,11,L0\|L1}
	4689	};
	4690
	4691	/* prefix 74 */
	4692	const struct upd7810_device::opcode_s upd7810_device::s_op74_78c05[256] =
	4693	{
	4694	/* 0x00 - 0x1F */
	4695	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4696	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4697	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4698	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4699	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4700	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4701	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4702	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4703
	4704	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4705	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4706	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4707	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4708	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4709	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4710	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4711	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4712
	4713	/* 0x20 - 0x3F */
	4714	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4715	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4716	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4717	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4718	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4719	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4720	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4721	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4722
	4723	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4724	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4725	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4726	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4727	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4728	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4729	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4730	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4731
	4732	/* 0x40 - 0x5F */
	4733	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4734	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4735	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4736	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4737	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4738	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4739	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4740	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4741
	4742	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4743	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4744	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4745	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4746	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4747	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4748	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4749	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4750
	4751	/* 0x60 - 0x7F */
	4752	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4753	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4754	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4755	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4756	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4757	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4758	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4759	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4760
	4761	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4762	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4763	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4764	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4765	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4766	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4767	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4768	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4769
	4770	/* 0x80 - 0x9F */
	4771	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4772	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4773	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4774	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4775	{&upd7810_device::ANAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4776	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4777	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4778	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4779
	4780	{&upd7810_device::XRAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4781	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4782	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4783	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4784	{&upd7810_device::ORAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4785	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4786	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4787	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4788
	4789	/* 0xA0 - 0xBF */
	4790	{&upd7810_device::ADDNCW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4791	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4792	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4793	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4794	{&upd7810_device::GTAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4795	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4796	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4797	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4798
	4799	{&upd7810_device::SUBNBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4800	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4801	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4802	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4803	{&upd7810_device::LTAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4804	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4805	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4806	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4807
	4808	/* 0xC0 - 0xDF */
	4809	{&upd7810_device::ADDW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4810	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4811	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4812	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4813	{&upd7810_device::ONAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4814	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4815	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4816	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4817
	4818	{&upd7810_device::ADCW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4819	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4820	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4821	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4822	{&upd7810_device::OFFAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4823	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4824	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4825	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4826
	4827	/* 0xE0 - 0xFF */
	4828	{&upd7810_device::SUBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4829	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4830	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4831	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4832	{&upd7810_device::NEAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4833	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4834	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4835	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4836
	4837	{&upd7810_device::SBBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4838	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4839	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4840	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4841	{&upd7810_device::EQAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4842	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4843	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1},
	4844	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0\|L1}
	4845	};
	4846
	4847	const struct upd7810_device::opcode_s upd7810_device::s_opXX_78c05[256] =
	4848	{
	4849	/* 0x00 - 0x1F */
	4850	{&upd7810_device::NOP, 1, 4, 4,L0\|L1}, {&upd7810_device::HALT, 1, 6, 6,L0\|L1},
	4851	{&upd7810_device::INX_SP, 1, 7, 7,L0\|L1}, {&upd7810_device::DCX_SP, 1, 7, 7,L0\|L1},
	4852	{&upd7810_device::LXI_S_w, 3,10,10,L0\|L1}, {&upd7810_device::ANIW_wa_xx, 3,16,16,L0\|L1},
	4853	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::ANI_A_xx, 2, 7, 7,L0\|L1},
	4854	{&upd7810_device::RET, 1,10,10,L0\|L1}, {&upd7810_device::SIO, 1, 4, 4,L0\|L1},
	4855	{&upd7810_device::MOV_A_B, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_A_C, 1, 4, 4,L0\|L1},
	4856	{&upd7810_device::MOV_A_D, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_A_E, 1, 4, 4,L0\|L1},
	4857	{&upd7810_device::MOV_A_H, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_A_L, 1, 4, 4,L0\|L1},
	4858
	4859	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
	4860	{&upd7810_device::INX_BC, 1, 7, 7,L0\|L1}, {&upd7810_device::DCX_BC, 1, 7, 7,L0\|L1},
	4861	{&upd7810_device::LXI_B_w, 3,10,10,L0\|L1}, {&upd7810_device::ORIW_wa_xx, 3,16,16,L0\|L1},
	4862	{&upd7810_device::XRI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::ORI_A_xx, 2, 7, 7,L0\|L1},
	4863	{&upd7810_device::RETS, 1,10,10,L0\|L1}, {&upd7810_device::STM, 1, 4, 4,L0\|L1},
	4864	{&upd7810_device::MOV_B_A, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_C_A, 1, 4, 4,L0\|L1},
	4865	{&upd7810_device::MOV_D_A, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_E_A, 1, 4, 4,L0\|L1},
	4866	{&upd7810_device::MOV_H_A, 1, 4, 4,L0\|L1}, {&upd7810_device::MOV_L_A, 1, 4, 4,L0\|L1},
	4867
	4868	/* 0x20 - 0x3F */
	4869	{&upd7810_device::INRW_wa_7801, 2,13,13,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
	4870	{&upd7810_device::INX_DE, 1, 7, 7,L0\|L1}, {&upd7810_device::DCX_DE, 1, 7, 7,L0\|L1},
	4871	{&upd7810_device::LXI_D_w, 3,10,10,L0\|L1}, {&upd7810_device::GTIW_wa_xx, 3,13,13,L0\|L1},
	4872	{&upd7810_device::ADINC_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::GTI_A_xx, 2, 7, 7,L0\|L1},
	4873	{&upd7810_device::LDAW_wa, 2,10,10,L0\|L1}, {&upd7810_device::LDAX_B, 1, 7, 7,L0\|L1},
	4874	{&upd7810_device::LDAX_D, 1, 7, 7,L0\|L1}, {&upd7810_device::LDAX_H, 1, 7, 7,L0\|L1},
	4875	{&upd7810_device::LDAX_Dp, 1, 7, 7,L0\|L1}, {&upd7810_device::LDAX_Hp, 1, 7, 7,L0\|L1},
	4876	{&upd7810_device::LDAX_Dm, 1, 7, 7,L0\|L1}, {&upd7810_device::LDAX_Hm, 1, 7, 7,L0\|L1},
	4877
	4878	{&upd7810_device::DCRW_wa_7801, 2,13,13,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
	4879	{&upd7810_device::INX_HL, 1, 7, 7,L0\|L1}, {&upd7810_device::DCX_HL, 1, 7, 7,L0\|L1},
	4880	{&upd7810_device::LXI_H_w, 3,10,10, L1}, {&upd7810_device::LTIW_wa_xx, 3,13,13,L0\|L1},
	4881	{&upd7810_device::SUINB_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::LTI_A_xx, 2, 7, 7,L0\|L1},
	4882	{&upd7810_device::STAW_wa, 2,10,10,L0\|L1}, {&upd7810_device::STAX_B, 1, 7, 7,L0\|L1},
	4883	{&upd7810_device::STAX_D, 1, 7, 7,L0\|L1}, {&upd7810_device::STAX_H, 1, 7, 7,L0\|L1},
	4884	{&upd7810_device::STAX_Dp, 1, 7, 7,L0\|L1}, {&upd7810_device::STAX_Hp, 1, 7, 7,L0\|L1},
	4885	{&upd7810_device::STAX_Dm, 1, 7, 7,L0\|L1}, {&upd7810_device::STAX_Hm, 1, 7, 7,L0\|L1},
	4886
	4887	/* 0x40 - 0x5F */
	4888	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::INR_A_7801, 1, 4, 4,L0\|L1},
	4889	{&upd7810_device::INR_B_7801, 1, 4, 4,L0\|L1}, {&upd7810_device::INR_C_7801, 1, 4, 4,L0\|L1},
	4890	{&upd7810_device::CALL_w, 3,16,16,L0\|L1}, {&upd7810_device::ONIW_wa_xx, 3,13,13,L0\|L1},
	4891	{&upd7810_device::ADI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::ONI_A_xx, 2, 7, 7,L0\|L1},
	4892	{&upd7810_device::PRE_48, 1, 0, 0,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
	4893	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
	4894	{&upd7810_device::PRE_4C, 1, 0, 0,L0\|L1}, {&upd7810_device::PRE_4D, 1, 0, 0,L0\|L1},
	4895	{&upd7810_device::JRE, 2,13,13,L0\|L1}, {&upd7810_device::JRE, 2,13,13,L0\|L1},
	4896
	4897	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::DCR_A_7801, 1, 4, 4,L0\|L1},
	4898	{&upd7810_device::DCR_B_7801, 1, 4, 4,L0\|L1}, {&upd7810_device::DCR_C_7801, 1, 4, 4,L0\|L1},
	4899	{&upd7810_device::JMP_w, 3,10,10,L0\|L1}, {&upd7810_device::OFFIW_wa_xx, 3,13,13,L0\|L1},
	4900	{&upd7810_device::ACI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::OFFI_A_xx, 2, 7, 7,L0\|L1},
	4901	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
	4902	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
	4903	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
	4904	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
	4905
	4906	/* 0x60 - 0x7F */
	4907	{&upd7810_device::PRE_60, 1, 0, 0,L0\|L1}, {&upd7810_device::DAA, 1, 4, 4,L0\|L1},
	4908	{&upd7810_device::RETI, 1,13,13,L0\|L1}, {&upd7810_device::CALB, 2,13,13,L0\|L1},
	4909	{&upd7810_device::PRE_64, 1, 0, 0,L0\|L1}, {&upd7810_device::NEIW_wa_xx, 3,13,13,L0\|L1},
	4910	{&upd7810_device::SUI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::NEI_A_xx, 2, 7, 7,L0\|L1},
	4911	{&upd7810_device::illegal, 1, 4, 4,L0\|L1}, {&upd7810_device::MVI_A_xx, 2, 7, 7,L0 },
	4912	{&upd7810_device::MVI_B_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::MVI_C_xx, 2, 7, 7,L0\|L1},
	4913	{&upd7810_device::MVI_D_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::MVI_E_xx, 2, 7, 7,L0\|L1},
	4914	{&upd7810_device::MVI_H_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::MVI_L_xx, 2, 7, 7, L1},
	4915
	4916	{&upd7810_device::PRE_70, 1, 0, 0,L0\|L1}, {&upd7810_device::MVIW_wa_xx, 3,13,13,L0\|L1},
	4917	{&upd7810_device::SOFTI, 1,19,19,L0\|L1}, {&upd7810_device::JB, 1, 4, 4,L0\|L1},
	4918	{&upd7810_device::PRE_74, 1, 0, 0,L0\|L1}, {&upd7810_device::EQIW_wa_xx, 3,13,13,L0\|L1},
	4919	{&upd7810_device::SBI_A_xx, 2, 7, 7,L0\|L1}, {&upd7810_device::EQI_A_xx, 2, 7, 7,L0\|L1},
	4920	{&upd7810_device::CALF, 2,13,13,L0\|L1}, {&upd7810_device::CALF, 2,13,13,L0\|L1},
	4921	{&upd7810_device::CALF, 2,13,13,L0\|L1}, {&upd7810_device::CALF, 2,13,13,L0\|L1},
	4922	{&upd7810_device::CALF, 2,13,13,L0\|L1}, {&upd7810_device::CALF, 2,13,13,L0\|L1},
	4923	{&upd7810_device::CALF, 2,13,13,L0\|L1}, {&upd7810_device::CALF, 2,13,13,L0\|L1},
	4924
	4925	/* 0x80 - 0x9F */
	4926	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4927	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4928	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4929	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4930	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4931	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4932	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4933	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4934
	4935	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4936	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4937	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4938	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4939	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4940	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4941	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4942	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4943
	4944	/* 0xA0 - 0xBF */
	4945	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4946	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4947	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4948	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4949	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4950	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4951	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4952	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4953
	4954	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4955	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4956	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4957	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4958	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4959	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4960	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4961	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	4962
	4963	/* 0xC0 - 0xDF */
	4964	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4965	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4966	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4967	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4968	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4969	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4970	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4971	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4972
	4973	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4974	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4975	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4976	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4977	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4978	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4979	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4980	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4981
	4982	/* 0xE0 - 0xFF */
	4983	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4984	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4985	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4986	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4987	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4988	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4989	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4990	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4991
	4992	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4993	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4994	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4995	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4996	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4997	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4998	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1},
	4999	{&upd7810_device::JR, 1,10,10,L0\|L1}, {&upd7810_device::JR, 1,10,10,L0\|L1}
	5000	};
	5001
	5002	/***********************************************************************
	5003	*
	5004	* uPD78C06(A) - Same as uPD78C05 but with different instruction timing
	5005	*
	5006	**********************************************************************/
	5007
	5008	const struct upd7810_device::opcode_s upd7810_device::s_op48_78c06[256] =
	5009	{
	5010	/* 0x00 - 0x1F */
	5011	{&upd7810_device::SKIT_F0, 2,12,12,L0\|L1}, {&upd7810_device::SKIT_FT0, 2,12,12,L0\|L1},
	5012	{&upd7810_device::SKIT_F1, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5013	{&upd7810_device::SKIT_FST, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5014	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5015	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5016	{&upd7810_device::SK_CY, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5017	{&upd7810_device::SK_Z, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5018	{&upd7810_device::PUSH_VA, 2,21,21,L0\|L1}, {&upd7810_device::POP_VA, 2,18,18,L0\|L1},
	5019
	5020	{&upd7810_device::SKNIT_F0, 2,12,12,L0\|L1}, {&upd7810_device::SKNIT_FT0, 2,12,12,L0\|L1},
	5021	{&upd7810_device::SKNIT_F1, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5022	{&upd7810_device::SKNIT_FST, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5023	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5024	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5025	{&upd7810_device::SKN_CY, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5026	{&upd7810_device::SKN_Z, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5027	{&upd7810_device::PUSH_BC, 2,21,21,L0\|L1}, {&upd7810_device::POP_BC, 2,18,18,L0\|L1},
	5028
	5029	/* 0x20 - 0x3F */
	5030	{&upd7810_device::EI, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5031	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5032	{&upd7810_device::DI, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5033	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5034	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5035	{&upd7810_device::CLC, 2,12,12,L0\|L1}, {&upd7810_device::STC, 2,12,12,L0\|L1},
	5036	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::PEX, 2,15,15,L0\|L1},
	5037	{&upd7810_device::PUSH_DE, 2,21,21,L0\|L1}, {&upd7810_device::POP_DE, 2,18,18,L0\|L1},
	5038
	5039	{&upd7810_device::RLL_A, 2,12,12,L0\|L1}, {&upd7810_device::RLR_A, 2,12,12,L0\|L1},
	5040	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5041	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5042	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5043	{&upd7810_device::RLD, 2,21,21,L0\|L1}, {&upd7810_device::RRD, 2,21,21,L0\|L1},
	5044	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5045	{&upd7810_device::PER, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5046	{&upd7810_device::PUSH_HL, 2,21,21,L0\|L1}, {&upd7810_device::POP_HL, 2,18,18,L0\|L1},
	5047
	5048	/* 0x40 - 0x5F */
	5049	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5050	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5051	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5052	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5053	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5054	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5055	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5056	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5057
	5058	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5059	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5060	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5061	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5062	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5063	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5064	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5065	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5066
	5067	/* 0x60 - 0x7F */
	5068	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5069	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5070	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5071	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5072	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5073	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5074	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5075	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5076
	5077	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5078	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5079	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5080	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5081	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5082	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5083	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5084	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5085
	5086	/* 0x80 - 0x9F */
	5087	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5088	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5089	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5090	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5091	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5092	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5093	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5094	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5095
	5096	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5097	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5098	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5099	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5100	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5101	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5102	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5103	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5104
	5105	/* 0xA0 - 0xBF */
	5106	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5107	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5108	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5109	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5110	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5111	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5112	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5113	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5114
	5115	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5116	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5117	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5118	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5119	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5120	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5121	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5122	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5123
	5124	/* 0xC0 - 0xDF */
	5125	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5126	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5127	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5128	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5129	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5130	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5131	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5132	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5133
	5134	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5135	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5136	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5137	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5138	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5139	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5140	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5141	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5142
	5143	/* 0xE0 - 0xFF */
	5144	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5145	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5146	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5147	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5148	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5149	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5150	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5151	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5152
	5153	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5154	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5155	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5156	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5157	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5158	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5159	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5160	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1}
	5161	};
	5162
	5163	const struct upd7810_device::opcode_s upd7810_device::s_op4C_78c06[256] =
	5164	{
	5165	/* 0x00 - 0x1F */
	5166	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5167	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5168	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5169	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5170	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5171	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5172	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5173	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5174
	5175	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5176	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5177	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5178	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5179	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5180	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5181	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5182	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5183
	5184	/* 0x20 - 0x3F */
	5185	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5186	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5187	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5188	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5189	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5190	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5191	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5192	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5193
	5194	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5195	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5196	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5197	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5198	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5199	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5200	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5201	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5202
	5203	/* 0x40 - 0x5F */
	5204	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5205	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5206	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5207	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5208	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5209	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5210	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5211	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5212
	5213	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5214	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5215	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5216	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5217	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5218	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5219	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5220	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5221
	5222	/* 0x60 - 0x7F */
	5223	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5224	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5225	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5226	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5227	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5228	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5229	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5230	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5231
	5232	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5233	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5234	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5235	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5236	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5237	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5238	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5239	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5240
	5241	/* 0x80 - 0x9F */
	5242	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5243	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5244	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5245	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5246	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5247	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5248	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5249	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5250
	5251	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5252	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5253	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5254	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5255	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5256	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5257	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5258	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5259
	5260	/* 0xA0 - 0xBF */
	5261	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5262	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5263	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5264	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5265	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5266	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5267	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5268	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5269
	5270	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5271	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5272	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5273	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5274	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5275	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5276	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5277	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5278
	5279	/* 0xC0 - 0xDF */
	5280	{&upd7810_device::MOV_A_PA, 2,14,14,L0\|L1}, {&upd7810_device::MOV_A_PB, 2,14,14,L0\|L1},
	5281	{&upd7810_device::MOV_A_PC, 2,14,14,L0\|L1}, {&upd7810_device::MOV_A_MKL, 2,14,14,L0\|L1},
	5282	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5283	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5284	{&upd7810_device::MOV_A_S, 2,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5285	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5286	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5287	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5288
	5289	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5290	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5291	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5292	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5293	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5294	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5295	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5296	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5297
	5298	/* 0xE0 - 0xFF */
	5299	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5300	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5301	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5302	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5303	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5304	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5305	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5306	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5307
	5308	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5309	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5310	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5311	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5312	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5313	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5314	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5315	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1}
	5316	};
	5317
	5318	/* prefix 4D */
	5319	const struct upd7810_device::opcode_s upd7810_device::s_op4D_78c06[256] =
	5320	{
	5321	/* 0x00 - 0x1F */
	5322	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5323	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5324	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5325	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5326	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5327	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5328	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5329	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5330
	5331	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5332	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5333	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5334	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5335	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5336	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5337	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5338	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5339
	5340	/* 0x20 - 0x3F */
	5341	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5342	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5343	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5344	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5345	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5346	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5347	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5348	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5349
	5350	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5351	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5352	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5353	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5354	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5355	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5356	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5357	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5358
	5359	/* 0x40 - 0x5F */
	5360	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5361	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5362	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5363	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5364	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5365	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5366	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5367	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5368
	5369	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5370	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5371	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5372	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5373	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5374	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5375	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5376	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5377
	5378	/* 0x60 - 0x7F */
	5379	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5380	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5381	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5382	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5383	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5384	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5385	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5386	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5387
	5388	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5389	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5390	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5391	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5392	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5393	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5394	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5395	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5396
	5397	/* 0x80 - 0x9F */
	5398	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5399	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5400	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5401	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5402	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5403	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5404	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5405	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5406
	5407	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5408	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5409	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5410	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5411	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5412	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5413	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5414	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5415
	5416	/* 0xA0 - 0xBF */
	5417	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5418	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5419	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5420	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5421	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5422	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5423	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5424	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5425
	5426	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5427	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5428	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5429	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5430	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5431	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5432	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5433	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5434
	5435	/* 0xC0 - 0xDF */
	5436	{&upd7810_device::MOV_PA_A, 2,14,14,L0\|L1}, {&upd7810_device::MOV_PB_A, 2,14,14,L0\|L1},
	5437	{&upd7810_device::MOV_PC_A, 2,14,14,L0\|L1}, {&upd7810_device::MOV_MKL_A, 2,14,14,L0\|L1},
	5438	{&upd7810_device::MOV_MB_A, 2,14,14,L0\|L1}, {&upd7810_device::MOV_MC_A, 2,14,14,L0\|L1},
	5439	{&upd7810_device::MOV_TM0_A, 2,14,14,L0\|L1}, {&upd7810_device::MOV_TM1_A, 2,14,14,L0\|L1},
	5440	{&upd7810_device::MOV_S_A, 2,14,14,L0\|L1}, {&upd7810_device::MOV_TMM_A, 2,14,14,L0\|L1},
	5441	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5442	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5443	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5444
	5445	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5446	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5447	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5448	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5449	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5450	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5451	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5452	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5453
	5454	/* 0xE0 - 0xFF */
	5455	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5456	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5457	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5458	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5459	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5460	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5461	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5462	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5463
	5464	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5465	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5466	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5467	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5468	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5469	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5470	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5471	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1}
	5472	};
	5473
	5474	/* prefix 60 */
	5475	const struct upd7810_device::opcode_s upd7810_device::s_op60_78c06[256] =
	5476	{
	5477	/* 0x00 - 0x1F */
	5478	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5479	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5480	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5481	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5482	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ANA_A_A, 2,12,12,L0\|L1},
	5483	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5484	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5485	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5486
	5487	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::XRA_A_A, 2,12,12,L0\|L1},
	5488	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5489	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5490	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5491	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ORA_A_A, 2,12,12,L0\|L1},
	5492	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5493	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5494	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5495
	5496	/* 0x20 - 0x3F */
	5497	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADDNC_A_A, 2,12,12,L0\|L1},
	5498	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5499	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5500	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5501	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::GTA_A_A, 2,12,12,L0\|L1},
	5502	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5503	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5504	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5505
	5506	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SUBNB_A_A, 2,12,12,L0\|L1},
	5507	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5508	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5509	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5510	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::LTA_A_A, 2,12,12,L0\|L1},
	5511	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5512	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5513	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5514
	5515	/* 0x40 - 0x5F */
	5516	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADD_A_A, 2,12,12,L0\|L1},
	5517	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5518	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5519	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5520	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5521	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5522	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5523	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5524
	5525	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADC_A_A, 2,12,12,L0\|L1},
	5526	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5527	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5528	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5529	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5530	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5531	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5532	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5533
	5534	/* 0x60 - 0x7F */
	5535	{&upd7810_device::illegal2, 2, 8, 8,L0\|L1}, {&upd7810_device::SUB_A_A, 2,12,12,L0\|L1},
	5536	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5537	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5538	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5539	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::NEA_A_A, 2,12,12,L0\|L1},
	5540	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5541	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5542	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5543
	5544	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SBB_A_A, 2,12,12,L0\|L1},
	5545	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5546	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5547	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5548	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::EQA_A_A, 2,12,12,L0\|L1},
	5549	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5550	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5551	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5552
	5553	/* 0x80 - 0x9F */
	5554	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5555	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5556	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5557	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5558	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ANA_A_A, 2,12,12,L0\|L1},
	5559	{&upd7810_device::ANA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::ANA_A_C, 2,12,12,L0\|L1},
	5560	{&upd7810_device::ANA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::ANA_A_E, 2,12,12,L0\|L1},
	5561	{&upd7810_device::ANA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::ANA_A_L, 2,12,12,L0\|L1},
	5562
	5563	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::XRA_A_A, 2,12,12,L0\|L1},
	5564	{&upd7810_device::XRA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::XRA_A_C, 2,12,12,L0\|L1},
	5565	{&upd7810_device::XRA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::XRA_A_E, 2,12,12,L0\|L1},
	5566	{&upd7810_device::XRA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::XRA_A_L, 2,12,12,L0\|L1},
	5567	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ORA_A_A, 2,12,12,L0\|L1},
	5568	{&upd7810_device::ORA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::ORA_A_C, 2,12,12,L0\|L1},
	5569	{&upd7810_device::ORA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::ORA_A_E, 2,12,12,L0\|L1},
	5570	{&upd7810_device::ORA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::ORA_A_L, 2,12,12,L0\|L1},
	5571
	5572	/* 0xA0 - 0xBF */
	5573	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADDNC_A_A, 2,12,12,L0\|L1},
	5574	{&upd7810_device::ADDNC_A_B, 2,12,12,L0\|L1}, {&upd7810_device::ADDNC_A_C, 2,12,12,L0\|L1},
	5575	{&upd7810_device::ADDNC_A_D, 2,12,12,L0\|L1}, {&upd7810_device::ADDNC_A_E, 2,12,12,L0\|L1},
	5576	{&upd7810_device::ADDNC_A_H, 2,12,12,L0\|L1}, {&upd7810_device::ADDNC_A_L, 2,12,12,L0\|L1},
	5577	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::GTA_A_A, 2,12,12,L0\|L1},
	5578	{&upd7810_device::GTA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::GTA_A_C, 2,12,12,L0\|L1},
	5579	{&upd7810_device::GTA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::GTA_A_E, 2,12,12,L0\|L1},
	5580	{&upd7810_device::GTA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::GTA_A_L, 2,12,12,L0\|L1},
	5581
	5582	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SUBNB_A_A, 2,12,12,L0\|L1},
	5583	{&upd7810_device::SUBNB_A_B, 2,12,12,L0\|L1}, {&upd7810_device::SUBNB_A_C, 2,12,12,L0\|L1},
	5584	{&upd7810_device::SUBNB_A_D, 2,12,12,L0\|L1}, {&upd7810_device::SUBNB_A_E, 2,12,12,L0\|L1},
	5585	{&upd7810_device::SUBNB_A_H, 2,12,12,L0\|L1}, {&upd7810_device::SUBNB_A_L, 2,12,12,L0\|L1},
	5586	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::LTA_A_A, 2,12,12,L0\|L1},
	5587	{&upd7810_device::LTA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::LTA_A_C, 2,12,12,L0\|L1},
	5588	{&upd7810_device::LTA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::LTA_A_E, 2,12,12,L0\|L1},
	5589	{&upd7810_device::LTA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::LTA_A_L, 2,12,12,L0\|L1},
	5590
	5591	/* 0xC0 - 0xDF */
	5592	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADD_A_A, 2,12,12,L0\|L1},
	5593	{&upd7810_device::ADD_A_B, 2,12,12,L0\|L1}, {&upd7810_device::ADD_A_C, 2,12,12,L0\|L1},
	5594	{&upd7810_device::ADD_A_D, 2,12,12,L0\|L1}, {&upd7810_device::ADD_A_E, 2,12,12,L0\|L1},
	5595	{&upd7810_device::ADD_A_H, 2,12,12,L0\|L1}, {&upd7810_device::ADD_A_L, 2,12,12,L0\|L1},
	5596	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ONA_A_A, 2,12,12,L0\|L1},
	5597	{&upd7810_device::ONA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::ONA_A_C, 2,12,12,L0\|L1},
	5598	{&upd7810_device::ONA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::ONA_A_E, 2,12,12,L0\|L1},
	5599	{&upd7810_device::ONA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::ONA_A_L, 2,12,12,L0\|L1},
	5600
	5601	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADC_A_A, 2,12,12,L0\|L1},
	5602	{&upd7810_device::ADC_A_B, 2,12,12,L0\|L1}, {&upd7810_device::ADC_A_C, 2,12,12,L0\|L1},
	5603	{&upd7810_device::ADC_A_D, 2,12,12,L0\|L1}, {&upd7810_device::ADC_A_E, 2,12,12,L0\|L1},
	5604	{&upd7810_device::ADC_A_H, 2,12,12,L0\|L1}, {&upd7810_device::ADC_A_L, 2,12,12,L0\|L1},
	5605	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::OFFA_A_A, 2,12,12,L0\|L1},
	5606	{&upd7810_device::OFFA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::OFFA_A_C, 2,12,12,L0\|L1},
	5607	{&upd7810_device::OFFA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::OFFA_A_E, 2,12,12,L0\|L1},
	5608	{&upd7810_device::OFFA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::OFFA_A_L, 2,12,12,L0\|L1},
	5609
	5610	/* 0xE0 - 0xFF */
	5611	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SUB_A_A, 2,12,12,L0\|L1},
	5612	{&upd7810_device::SUB_A_B, 2,12,12,L0\|L1}, {&upd7810_device::SUB_A_C, 2,12,12,L0\|L1},
	5613	{&upd7810_device::SUB_A_D, 2,12,12,L0\|L1}, {&upd7810_device::SUB_A_E, 2,12,12,L0\|L1},
	5614	{&upd7810_device::SUB_A_H, 2,12,12,L0\|L1}, {&upd7810_device::SUB_A_L, 2,12,12,L0\|L1},
	5615	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::NEA_A_A, 2,12,12,L0\|L1},
	5616	{&upd7810_device::NEA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::NEA_A_C, 2,12,12,L0\|L1},
	5617	{&upd7810_device::NEA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::NEA_A_E, 2,12,12,L0\|L1},
	5618	{&upd7810_device::NEA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::NEA_A_L, 2,12,12,L0\|L1},
	5619
	5620	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SBB_A_A, 2,12,12,L0\|L1},
	5621	{&upd7810_device::SBB_A_B, 2,12,12,L0\|L1}, {&upd7810_device::SBB_A_C, 2,12,12,L0\|L1},
	5622	{&upd7810_device::SBB_A_D, 2,12,12,L0\|L1}, {&upd7810_device::SBB_A_E, 2,12,12,L0\|L1},
	5623	{&upd7810_device::SBB_A_H, 2,12,12,L0\|L1}, {&upd7810_device::SBB_A_L, 2,12,12,L0\|L1},
	5624	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::EQA_A_A, 2,12,12,L0\|L1},
	5625	{&upd7810_device::EQA_A_B, 2,12,12,L0\|L1}, {&upd7810_device::EQA_A_C, 2,12,12,L0\|L1},
	5626	{&upd7810_device::EQA_A_D, 2,12,12,L0\|L1}, {&upd7810_device::EQA_A_E, 2,12,12,L0\|L1},
	5627	{&upd7810_device::EQA_A_H, 2,12,12,L0\|L1}, {&upd7810_device::EQA_A_L, 2,12,12,L0\|L1}
	5628	};
	5629
	5630	/* prefix 64 */
	5631	const struct upd7810_device::opcode_s upd7810_device::s_op64_78c06[256] =
	5632	{
	5633	/* 0x00 - 0x1F */
	5634	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5635	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5636	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5637	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5638	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ANI_A_xx, 3,17,17,L0\|L1},
	5639	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5640	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5641	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5642
	5643	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::XRI_A_xx, 3,17,17,L0\|L1},
	5644	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5645	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5646	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5647	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ORI_A_xx, 3,17,17,L0\|L1},
	5648	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5649	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5650	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5651
	5652	/* 0x20 - 0x3F */
	5653	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADINC_A_xx, 3,17,17,L0\|L1},
	5654	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5655	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5656	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5657	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::GTI_A_xx, 3,17,17,L0\|L1},
	5658	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5659	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5660	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5661
	5662	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SUINB_A_xx, 3,17,17,L0\|L1},
	5663	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5664	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5665	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5666	{&upd7810_device::illegal2, 3,12,12,L0\|L1}, {&upd7810_device::LTI_A_xx, 3,17,17,L0\|L1},
	5667	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5668	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5669	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5670
	5671	/* 0x40 - 0x5F */
	5672	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADI_A_xx, 3,17,17,L0\|L1},
	5673	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5674	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5675	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5676	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ONI_A_xx, 3,17,17,L0\|L1},
	5677	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5678	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5679	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5680
	5681	{&upd7810_device::illegal2, 3,12,12,L0\|L1}, {&upd7810_device::ACI_A_xx, 3,17,17,L0\|L1},
	5682	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5683	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5684	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5685	{&upd7810_device::illegal2, 3,12,12,L0\|L1}, {&upd7810_device::OFFI_A_xx, 3,17,17,L0\|L1},
	5686	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5687	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5688	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5689
	5690	/* 0x60 - 0x7F */
	5691	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SUI_A_xx, 3,17,17,L0\|L1},
	5692	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5693	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5694	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5695	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::NEI_A_xx, 3,17,17,L0\|L1},
	5696	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5697	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5698	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5699
	5700	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SBI_A_xx, 3,17,17,L0\|L1},
	5701	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5702	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5703	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5704	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::EQI_A_xx, 3,17,17,L0\|L1},
	5705	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5706	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5707	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5708
	5709	/* 0x80 - 0x9F */
	5710	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5711	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5712	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5713	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5714	{&upd7810_device::ANI_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::ANI_PB_xx, 3,23,23,L0\|L1},
	5715	{&upd7810_device::ANI_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::ANI_MKL_xx, 3,23,23,L0\|L1},
	5716	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5717	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5718
	5719	{&upd7810_device::XRI_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::XRI_PB_xx, 3,23,23,L0\|L1},
	5720	{&upd7810_device::XRI_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::XRI_MKL_xx, 3,23,23,L0\|L1},
	5721	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5722	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5723	{&upd7810_device::ORI_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::ORI_PB_xx, 3,23,23,L0\|L1},
	5724	{&upd7810_device::ORI_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::ORI_MKL_xx, 3,23,23,L0\|L1},
	5725	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5726	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5727
	5728	/* 0xA0 - 0xBF */
	5729	{&upd7810_device::ADINC_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::ADINC_PB_xx, 3,23,23,L0\|L1},
	5730	{&upd7810_device::ADINC_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::ADINC_MKL_xx, 3,23,23,L0\|L1},
	5731	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5732	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5733	{&upd7810_device::GTI_PA_xx, 3,20,20,L0\|L1}, {&upd7810_device::GTI_PB_xx, 3,20,20,L0\|L1},
	5734	{&upd7810_device::GTI_PC_xx, 3,20,20,L0\|L1}, {&upd7810_device::GTI_MKL_xx, 3,20,20,L0\|L1},
	5735	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5736	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5737
	5738	{&upd7810_device::SUINB_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::SUINB_PB_xx, 3,23,23,L0\|L1},
	5739	{&upd7810_device::SUINB_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::SUINB_MKL_xx, 3,23,23,L0\|L1},
	5740	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5741	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5742	{&upd7810_device::LTI_PA_xx, 3,20,20,L0\|L1}, {&upd7810_device::LTI_PB_xx, 3,20,20,L0\|L1},
	5743	{&upd7810_device::LTI_PC_xx, 3,20,20,L0\|L1}, {&upd7810_device::LTI_MKL_xx, 3,20,20,L0\|L1},
	5744	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5745	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5746
	5747	/* 0xC0 - 0xDF */
	5748	{&upd7810_device::ADI_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::ADI_PB_xx, 3,23,23,L0\|L1},
	5749	{&upd7810_device::ADI_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::ADI_MKL_xx, 3,23,23,L0\|L1},
	5750	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5751	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5752	{&upd7810_device::ONI_PA_xx, 3,20,20,L0\|L1}, {&upd7810_device::ONI_PB_xx, 3,20,20,L0\|L1},
	5753	{&upd7810_device::ONI_PC_xx, 3,20,20,L0\|L1}, {&upd7810_device::ONI_MKL_xx, 3,20,20,L0\|L1},
	5754	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5755	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5756
	5757	{&upd7810_device::ACI_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::ACI_PB_xx, 3,23,23,L0\|L1},
	5758	{&upd7810_device::ACI_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::ACI_MKL_xx, 3,23,23,L0\|L1},
	5759	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5760	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5761	{&upd7810_device::OFFI_PA_xx, 3,20,20,L0\|L1}, {&upd7810_device::OFFI_PB_xx, 3,20,20,L0\|L1},
	5762	{&upd7810_device::OFFI_PC_xx, 3,20,20,L0\|L1}, {&upd7810_device::OFFI_MKL_xx, 3,20,20,L0\|L1},
	5763	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5764	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5765
	5766	/* 0xE0 - 0xFF */
	5767	{&upd7810_device::SUI_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::SUI_PB_xx, 3,23,23,L0\|L1},
	5768	{&upd7810_device::SUI_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::SUI_MKL_xx, 3,23,23,L0\|L1},
	5769	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5770	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5771	{&upd7810_device::NEI_PA_xx, 3,20,20,L0\|L1}, {&upd7810_device::NEI_PB_xx, 3,20,20,L0\|L1},
	5772	{&upd7810_device::NEI_PC_xx, 3,20,20,L0\|L1}, {&upd7810_device::NEI_MKL_xx, 3,20,20,L0\|L1},
	5773	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5774	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5775
	5776	{&upd7810_device::SBI_PA_xx, 3,23,23,L0\|L1}, {&upd7810_device::SBI_PB_xx, 3,23,23,L0\|L1},
	5777	{&upd7810_device::SBI_PC_xx, 3,23,23,L0\|L1}, {&upd7810_device::SBI_MKL_xx, 3,23,23,L0\|L1},
	5778	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5779	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5780	{&upd7810_device::EQI_PA_xx, 3,20,20,L0\|L1}, {&upd7810_device::EQI_PB_xx, 3,20,20,L0\|L1},
	5781	{&upd7810_device::EQI_PC_xx, 3,20,20,L0\|L1}, {&upd7810_device::EQI_MKL_xx, 3,20,20,L0\|L1},
	5782	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5783	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1}
	5784	};
	5785
	5786	/* prefix 70 */
	5787	const struct upd7810_device::opcode_s upd7810_device::s_op70_78c06[256] =
	5788	{
	5789	/* 0x00 - 0x1F */
	5790	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5791	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5792	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5793	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5794	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5795	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5796	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5797	{&upd7810_device::SSPD_w, 4,28,28,L0\|L1}, {&upd7810_device::LSPD_w, 4,28,28,L0\|L1},
	5798
	5799	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5800	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5801	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5802	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5803	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5804	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5805	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5806	{&upd7810_device::SBCD_w, 4,28,28,L0\|L1}, {&upd7810_device::LBCD_w, 4,28,28,L0\|L1},
	5807
	5808	/* 0x20 - 0x3F */
	5809	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5810	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5811	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5812	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5813	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5814	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5815	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5816	{&upd7810_device::SDED_w, 4,28,28,L0\|L1}, {&upd7810_device::LDED_w, 4,28,28,L0\|L1},
	5817
	5818	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5819	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5820	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5821	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5822	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5823	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5824	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5825	{&upd7810_device::SHLD_w, 4,28,28,L0\|L1}, {&upd7810_device::LHLD_w, 4,28,28,L0\|L1},
	5826
	5827	/* 0x40 - 0x5F */
	5828	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5829	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5830	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5831	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5832	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5833	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5834	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5835	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5836
	5837	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5838	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5839	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5840	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5841	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5842	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5843	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5844	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5845
	5846	/* 0x60 - 0x7F */
	5847	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5848	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5849	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5850	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5851	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::MOV_A_w, 4,25,25,L0\|L1},
	5852	{&upd7810_device::MOV_B_w, 4,25,25,L0\|L1}, {&upd7810_device::MOV_C_w, 4,25,25,L0\|L1},
	5853	{&upd7810_device::MOV_D_w, 4,25,25,L0\|L1}, {&upd7810_device::MOV_E_w, 4,25,25,L0\|L1},
	5854	{&upd7810_device::MOV_H_w, 4,25,25,L0\|L1}, {&upd7810_device::MOV_L_w, 4,25,25,L0\|L1},
	5855
	5856	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5857	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5858	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5859	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5860	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::MOV_w_A, 4,25,25,L0\|L1},
	5861	{&upd7810_device::MOV_w_B, 4,25,25,L0\|L1}, {&upd7810_device::MOV_w_C, 4,25,25,L0\|L1},
	5862	{&upd7810_device::MOV_w_D, 4,25,25,L0\|L1}, {&upd7810_device::MOV_w_E, 4,25,25,L0\|L1},
	5863	{&upd7810_device::MOV_w_H, 4,25,25,L0\|L1}, {&upd7810_device::MOV_w_L, 4,25,25,L0\|L1},
	5864
	5865	/* 0x80 - 0x9F */
	5866	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5867	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5868	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5869	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5870	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ANAX_B, 2,15,15,L0\|L1},
	5871	{&upd7810_device::ANAX_D, 2,15,15,L0\|L1}, {&upd7810_device::ANAX_H, 2,15,15,L0\|L1},
	5872	{&upd7810_device::ANAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::ANAX_Hp, 2,15,15,L0\|L1},
	5873	{&upd7810_device::ANAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::ANAX_Hm, 2,15,15,L0\|L1},
	5874
	5875	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::XRAX_B, 2,15,15,L0\|L1},
	5876	{&upd7810_device::XRAX_D, 2,15,15,L0\|L1}, {&upd7810_device::XRAX_H, 2,15,15,L0\|L1},
	5877	{&upd7810_device::XRAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::XRAX_Hp, 2,15,15,L0\|L1},
	5878	{&upd7810_device::XRAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::XRAX_Hm, 2,15,15,L0\|L1},
	5879	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ORAX_B, 2,15,15,L0\|L1},
	5880	{&upd7810_device::ORAX_D, 2,15,15,L0\|L1}, {&upd7810_device::ORAX_H, 2,15,15,L0\|L1},
	5881	{&upd7810_device::ORAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::ORAX_Hp, 2,15,15,L0\|L1},
	5882	{&upd7810_device::ORAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::ORAX_Hm, 2,15,15,L0\|L1},
	5883
	5884	/* 0xA0 - 0xBF */
	5885	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADDNCX_B, 2,15,15,L0\|L1},
	5886	{&upd7810_device::ADDNCX_D, 2,15,15,L0\|L1}, {&upd7810_device::ADDNCX_H, 2,15,15,L0\|L1},
	5887	{&upd7810_device::ADDNCX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::ADDNCX_Hp, 2,15,15,L0\|L1},
	5888	{&upd7810_device::ADDNCX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::ADDNCX_Hm, 2,15,15,L0\|L1},
	5889	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::GTAX_B, 2,15,15,L0\|L1},
	5890	{&upd7810_device::GTAX_D, 2,15,15,L0\|L1}, {&upd7810_device::GTAX_H, 2,15,15,L0\|L1},
	5891	{&upd7810_device::GTAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::GTAX_Hp, 2,15,15,L0\|L1},
	5892	{&upd7810_device::GTAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::GTAX_Hm, 2,15,15,L0\|L1},
	5893
	5894	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SUBNBX_B, 2,15,15,L0\|L1},
	5895	{&upd7810_device::SUBNBX_D, 2,15,15,L0\|L1}, {&upd7810_device::SUBNBX_H, 2,15,15,L0\|L1},
	5896	{&upd7810_device::SUBNBX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::SUBNBX_Hp, 2,15,15,L0\|L1},
	5897	{&upd7810_device::SUBNBX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::SUBNBX_Hm, 2,15,15,L0\|L1},
	5898	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::LTAX_B, 2,15,15,L0\|L1},
	5899	{&upd7810_device::LTAX_D, 2,15,15,L0\|L1}, {&upd7810_device::LTAX_H, 2,15,15,L0\|L1},
	5900	{&upd7810_device::LTAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::LTAX_Hp, 2,15,15,L0\|L1},
	5901	{&upd7810_device::LTAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::LTAX_Hm, 2,15,15,L0\|L1},
	5902
	5903	/* 0xC0 - 0xDF */
	5904	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADDX_B, 2,15,15,L0\|L1},
	5905	{&upd7810_device::ADDX_D, 2,15,15,L0\|L1}, {&upd7810_device::ADDX_H, 2,15,15,L0\|L1},
	5906	{&upd7810_device::ADDX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::ADDX_Hp, 2,15,15,L0\|L1},
	5907	{&upd7810_device::ADDX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::ADDX_Hm, 2,15,15,L0\|L1},
	5908	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ONAX_B, 2,15,15,L0\|L1},
	5909	{&upd7810_device::ONAX_D, 2,15,15,L0\|L1}, {&upd7810_device::ONAX_H, 2,15,15,L0\|L1},
	5910	{&upd7810_device::ONAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::ONAX_Hp, 2,15,15,L0\|L1},
	5911	{&upd7810_device::ONAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::ONAX_Hm, 2,15,15,L0\|L1},
	5912
	5913	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::ADCX_B, 2,15,15,L0\|L1},
	5914	{&upd7810_device::ADCX_D, 2,15,15,L0\|L1}, {&upd7810_device::ADCX_H, 2,15,15,L0\|L1},
	5915	{&upd7810_device::ADCX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::ADCX_Hp, 2,15,15,L0\|L1},
	5916	{&upd7810_device::ADCX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::ADCX_Hm, 2,15,15,L0\|L1},
	5917	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::OFFAX_B, 2,15,15,L0\|L1},
	5918	{&upd7810_device::OFFAX_D, 2,15,15,L0\|L1}, {&upd7810_device::OFFAX_H, 2,15,15,L0\|L1},
	5919	{&upd7810_device::OFFAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::OFFAX_Hp, 2,15,15,L0\|L1},
	5920	{&upd7810_device::OFFAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::OFFAX_Hm, 2,15,15,L0\|L1},
	5921
	5922	/* 0xE0 - 0xFF */
	5923	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SUBX_B, 2,15,15,L0\|L1},
	5924	{&upd7810_device::SUBX_D, 2,15,15,L0\|L1}, {&upd7810_device::SUBX_H, 2,15,15,L0\|L1},
	5925	{&upd7810_device::SUBX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::SUBX_Hp, 2,15,15,L0\|L1},
	5926	{&upd7810_device::SUBX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::SUBX_Hm, 2,15,15,L0\|L1},
	5927	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::NEAX_B, 2,15,15,L0\|L1},
	5928	{&upd7810_device::NEAX_D, 2,15,15,L0\|L1}, {&upd7810_device::NEAX_H, 2,15,15,L0\|L1},
	5929	{&upd7810_device::NEAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::NEAX_Hp, 2,15,15,L0\|L1},
	5930	{&upd7810_device::NEAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::NEAX_Hm, 2,15,15,L0\|L1},
	5931
	5932	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::SBBX_B, 2,15,15,L0\|L1},
	5933	{&upd7810_device::SBBX_D, 2,15,15,L0\|L1}, {&upd7810_device::SBBX_H, 2,15,15,L0\|L1},
	5934	{&upd7810_device::SBBX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::SBBX_Hp, 2,15,15,L0\|L1},
	5935	{&upd7810_device::SBBX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::SBBX_Hm, 2,15,15,L0\|L1},
	5936	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::EQAX_B, 2,15,15,L0\|L1},
	5937	{&upd7810_device::EQAX_D, 2,15,15,L0\|L1}, {&upd7810_device::EQAX_H, 2,15,15,L0\|L1},
	5938	{&upd7810_device::EQAX_Dp, 2,15,15,L0\|L1}, {&upd7810_device::EQAX_Hp, 2,15,15,L0\|L1},
	5939	{&upd7810_device::EQAX_Dm, 2,15,15,L0\|L1}, {&upd7810_device::EQAX_Hm, 2,15,15,L0\|L1}
	5940	};
	5941
	5942	/* prefix 74 */
	5943	const struct upd7810_device::opcode_s upd7810_device::s_op74_78c06[256] =
	5944	{
	5945	/* 0x00 - 0x1F */
	5946	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5947	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5948	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5949	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5950	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5951	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5952	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5953	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5954
	5955	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5956	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5957	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5958	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5959	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5960	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5961	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5962	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5963
	5964	/* 0x20 - 0x3F */
	5965	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5966	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5967	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5968	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5969	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5970	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5971	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5972	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5973
	5974	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5975	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5976	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5977	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5978	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5979	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5980	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5981	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5982
	5983	/* 0x40 - 0x5F */
	5984	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5985	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5986	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5987	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5988	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5989	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5990	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5991	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5992
	5993	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5994	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5995	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5996	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5997	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5998	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	5999	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6000	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6001
	6002	/* 0x60 - 0x7F */
	6003	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6004	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6005	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6006	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6007	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6008	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6009	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6010	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6011
	6012	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6013	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6014	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6015	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6016	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6017	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6018	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6019	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6020
	6021	/* 0x80 - 0x9F */
	6022	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6023	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6024	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6025	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6026	{&upd7810_device::ANAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6027	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6028	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6029	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6030
	6031	{&upd7810_device::XRAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6032	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6033	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6034	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6035	{&upd7810_device::ORAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6036	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6037	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6038	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6039
	6040	/* 0xA0 - 0xBF */
	6041	{&upd7810_device::ADDNCW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6042	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6043	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6044	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6045	{&upd7810_device::GTAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6046	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6047	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6048	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6049
	6050	{&upd7810_device::SUBNBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6051	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6052	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6053	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6054	{&upd7810_device::LTAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6055	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6056	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6057	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6058
	6059	/* 0xC0 - 0xDF */
	6060	{&upd7810_device::ADDW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6061	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6062	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6063	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6064	{&upd7810_device::ONAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6065	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6066	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6067	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6068
	6069	{&upd7810_device::ADCW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6070	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6071	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6072	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6073	{&upd7810_device::OFFAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6074	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6075	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6076	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6077
	6078	/* 0xE0 - 0xFF */
	6079	{&upd7810_device::SUBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6080	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6081	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6082	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6083	{&upd7810_device::NEAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6084	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6085	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6086	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6087
	6088	{&upd7810_device::SBBW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6089	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6090	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6091	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6092	{&upd7810_device::EQAW_wa, 3,14,14,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6093	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6094	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1},
	6095	{&upd7810_device::illegal2, 2,12,12,L0\|L1}, {&upd7810_device::illegal2, 2,12,12,L0\|L1}
	6096	};
	6097
	6098	const struct upd7810_device::opcode_s upd7810_device::s_opXX_78c06[256] =
	6099	{
	6100	/* 0x00 - 0x1F */
	6101	{&upd7810_device::NOP, 1, 6, 6,L0\|L1}, {&upd7810_device::HALT, 1, 6, 6,L0\|L1},
	6102	{&upd7810_device::INX_SP, 1, 9, 9,L0\|L1}, {&upd7810_device::DCX_SP, 1, 9, 9,L0\|L1},
	6103	{&upd7810_device::LXI_S_w, 3,16,16,L0\|L1}, {&upd7810_device::ANIW_wa_xx, 3,22,22,L0\|L1},
	6104	{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::ANI_A_xx, 2,11,11,L0\|L1},
	6105	{&upd7810_device::RET, 1,12,12,L0\|L1}, {&upd7810_device::SIO, 1, 6, 6,L0\|L1},
	6106	{&upd7810_device::MOV_A_B, 1, 6, 6,L0\|L1}, {&upd7810_device::MOV_A_C, 1, 6, 6,L0\|L1},
	6107	{&upd7810_device::MOV_A_D, 1, 6, 6,L0\|L1}, {&upd7810_device::MOV_A_E, 1, 6, 6,L0\|L1},
	6108	{&upd7810_device::MOV_A_H, 1, 6, 6,L0\|L1}, {&upd7810_device::MOV_A_L, 1, 6, 6,L0\|L1},
	6109
	6110	{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::illegal, 1, 6, 6,L0\|L1},
	6111	{&upd7810_device::INX_BC, 1, 9, 9,L0\|L1}, {&upd7810_device::DCX_BC, 1, 9, 9,L0\|L1},
	6112	{&upd7810_device::LXI_B_w, 3,16,16,L0\|L1}, {&upd7810_device::ORIW_wa_xx, 3,22,2,L0\|L1},
	6113	{&upd7810_device::XRI_A_xx, 2,11,11,L0\|L1}, {&upd7810_device::ORI_A_xx, 2,11,11,L0\|L1},
	6114	{&upd7810_device::RETS, 1,12,12,L0\|L1}, {&upd7810_device::STM, 1, 6, 6,L0\|L1},
	6115	{&upd7810_device::MOV_B_A, 1, 6, 6,L0\|L1}, {&upd7810_device::MOV_C_A, 1, 6, 6,L0\|L1},
	6116	{&upd7810_device::MOV_D_A, 1, 6, 6,L0\|L1}, {&upd7810_device::MOV_E_A, 1, 6, 6,L0\|L1},
	6117	{&upd7810_device::MOV_H_A, 1, 6, 6,L0\|L1}, {&upd7810_device::MOV_L_A, 1, 6, 6,L0\|L1},
	6118
	6119	/* 0x20 - 0x3F */
	6120	{&upd7810_device::INRW_wa_7801, 2,17,17,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
	6121	{&upd7810_device::INX_DE, 1, 9, 9,L0\|L1}, {&upd7810_device::DCX_DE, 1, 9, 9,L0\|L1},
	6122	{&upd7810_device::LXI_D_w, 3,16,16,L0\|L1}, {&upd7810_device::GTIW_wa_xx, 3,19,19,L0\|L1},
	6123	{&upd7810_device::ADINC_A_xx, 2,11,11,L0\|L1}, {&upd7810_device::GTI_A_xx, 2,11,11,L0\|L1},
	6124	{&upd7810_device::LDAW_wa, 2,14,14,L0\|L1}, {&upd7810_device::LDAX_B, 1, 9, 9,L0\|L1},
	6125	{&upd7810_device::LDAX_D, 1, 9, 9,L0\|L1}, {&upd7810_device::LDAX_H, 1, 9, 9,L0\|L1},
	6126	{&upd7810_device::LDAX_Dp, 1, 9, 9,L0\|L1}, {&upd7810_device::LDAX_Hp, 1, 9, 9,L0\|L1},
	6127	{&upd7810_device::LDAX_Dm, 1, 9, 9,L0\|L1}, {&upd7810_device::LDAX_Hm, 1, 9, 9,L0\|L1},
	6128
	6129	{&upd7810_device::DCRW_wa_7801, 2,17,17,L0\|L1}, {&upd7810_device::illegal, 1, 4, 4,L0\|L1},
	6130	{&upd7810_device::INX_HL, 1, 9, 9,L0\|L1}, {&upd7810_device::DCX_HL, 1, 9, 9,L0\|L1},
	6131	{&upd7810_device::LXI_H_w, 3,16,16, L1}, {&upd7810_device::LTIW_wa_xx, 3,19,19,L0\|L1},
	6132	{&upd7810_device::SUINB_A_xx, 2,11,11,L0\|L1}, {&upd7810_device::LTI_A_xx, 2,11,11,L0\|L1},
	6133	{&upd7810_device::STAW_wa, 2,14,14,L0\|L1}, {&upd7810_device::STAX_B, 1, 9, 9,L0\|L1},
	6134	{&upd7810_device::STAX_D, 1, 9, 9,L0\|L1}, {&upd7810_device::STAX_H, 1, 9, 9,L0\|L1},
	6135	{&upd7810_device::STAX_Dp, 1, 9, 9,L0\|L1}, {&upd7810_device::STAX_Hp, 1, 9, 9,L0\|L1},
	6136	{&upd7810_device::STAX_Dm, 1, 9, 9,L0\|L1}, {&upd7810_device::STAX_Hm, 1, 9, 9,L0\|L1},
	6137
	6138	/* 0x40 - 0x5F */
	6139	{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::INR_A_7801, 1, 6, 6,L0\|L1},
	6140	{&upd7810_device::INR_B_7801, 1, 6, 6,L0\|L1}, {&upd7810_device::INR_C_7801, 1, 6, 6,L0\|L1},
	6141	{&upd7810_device::CALL_w, 3,22,22,L0\|L1}, {&upd7810_device::ONIW_wa_xx, 3,19,19,L0\|L1},
	6142	{&upd7810_device::ADI_A_xx, 2,11,11,L0\|L1}, {&upd7810_device::ONI_A_xx, 2,11,11,L0\|L1},
	6143	{&upd7810_device::PRE_48, 1, 0, 0,L0\|L1}, {&upd7810_device::illegal, 1, 6, 6,L0\|L1},
	6144	{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::illegal, 1, 6, 6,L0\|L1},
	6145	{&upd7810_device::PRE_4C, 1, 0, 0,L0\|L1}, {&upd7810_device::PRE_4D, 1, 0, 0,L0\|L1},
	6146	{&upd7810_device::JRE, 2,17,17,L0\|L1}, {&upd7810_device::JRE, 2,17,17,L0\|L1},
	6147
	6148	{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::DCR_A_7801, 1, 6, 6,L0\|L1},
	6149	{&upd7810_device::DCR_B_7801, 1, 6, 6,L0\|L1}, {&upd7810_device::DCR_C_7801, 1, 6, 6,L0\|L1},
	6150	{&upd7810_device::JMP_w, 3,16,16,L0\|L1}, {&upd7810_device::OFFIW_wa_xx, 3,19,19,L0\|L1},
	6151	{&upd7810_device::ACI_A_xx, 2,11,11,L0\|L1}, {&upd7810_device::OFFI_A_xx, 2,11,11,L0\|L1},
	6152	{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::illegal, 1, 6, 6,L0\|L1},
	6153	{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::illegal, 1, 6, 6,L0\|L1},
	6154	{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::illegal, 1, 6, 6,L0\|L1},
	6155	{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::illegal, 1, 6, 6,L0\|L1},
	6156
	6157	/* 0x60 - 0x7F */
	6158	{&upd7810_device::PRE_60, 1, 0, 0,L0\|L1}, {&upd7810_device::DAA, 1, 6, 6,L0\|L1},
	6159	{&upd7810_device::RETI, 1,15,15,L0\|L1}, {&upd7810_device::CALB, 2,13,13,L0\|L1},
	6160	{&upd7810_device::PRE_64, 1, 0, 0,L0\|L1}, {&upd7810_device::NEIW_wa_xx, 3,19,19,L0\|L1},
	6161	{&upd7810_device::SUI_A_xx, 2,11,11,L0\|L1}, {&upd7810_device::NEI_A_xx, 2,11,11,L0\|L1},
	6162	{&upd7810_device::illegal, 1, 6, 6,L0\|L1}, {&upd7810_device::MVI_A_xx, 2,11,11,L0 },
	6163	{&upd7810_device::MVI_B_xx, 2,11,11,L0\|L1}, {&upd7810_device::MVI_C_xx, 2,11,11,L0\|L1},
	6164	{&upd7810_device::MVI_D_xx, 2,11,11,L0\|L1}, {&upd7810_device::MVI_E_xx, 2,11,11,L0\|L1},
	6165	{&upd7810_device::MVI_H_xx, 2,11,11,L0\|L1}, {&upd7810_device::MVI_L_xx, 2,11,11, L1},
	6166
	6167	{&upd7810_device::PRE_70, 1, 0, 0,L0\|L1}, {&upd7810_device::MVIW_wa_xx, 3,13,13,L0\|L1},
	6168	{&upd7810_device::SOFTI, 1,19,19,L0\|L1}, {&upd7810_device::JB, 1, 6, 6,L0\|L1},
	6169	{&upd7810_device::PRE_74, 1, 0, 0,L0\|L1}, {&upd7810_device::EQIW_wa_xx, 3,19,19,L0\|L1},
	6170	{&upd7810_device::SBI_A_xx, 2,11,11,L0\|L1}, {&upd7810_device::EQI_A_xx, 2,11,11,L0\|L1},
	6171	{&upd7810_device::CALF, 2,17,17,L0\|L1}, {&upd7810_device::CALF, 2,17,17,L0\|L1},
	6172	{&upd7810_device::CALF, 2,17,17,L0\|L1}, {&upd7810_device::CALF, 2,17,17,L0\|L1},
	6173	{&upd7810_device::CALF, 2,17,17,L0\|L1}, {&upd7810_device::CALF, 2,17,17,L0\|L1},
	6174	{&upd7810_device::CALF, 2,17,17,L0\|L1}, {&upd7810_device::CALF, 2,17,17,L0\|L1},
	6175
	6176	/* 0x80 - 0x9F */
	6177	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6178	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6179	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6180	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6181	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6182	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6183	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6184	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6185
	6186	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6187	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6188	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6189	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6190	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6191	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6192	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6193	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6194
	6195	/* 0xA0 - 0xBF */
	6196	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6197	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6198	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6199	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6200	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6201	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6202	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6203	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6204
	6205	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6206	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6207	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6208	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6209	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6210	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6211	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6212	{&upd7810_device::CALT_7801, 1,19,19,L0\|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0\|L1},
	6213
	6214	/* 0xC0 - 0xDF */
	6215	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6216	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6217	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6218	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6219	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6220	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6221	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6222	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6223
	6224	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6225	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6226	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6227	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6228	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6229	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6230	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6231	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6232
	6233	/* 0xE0 - 0xFF */
	6234	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6235	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6236	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6237	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6238	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6239	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6240	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6241	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6242
	6243	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6244	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6245	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6246	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6247	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6248	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6249	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1},
	6250	{&upd7810_device::JR, 1,12,12,L0\|L1}, {&upd7810_device::JR, 1,12,12,L0\|L1}
	6251	};

Property changes on: trunk/src/emu/cpu/upd7810/upd7810_table.c
Added: svn:mime-type + text/plain Added: svn:eol-style + native

trunk/src/emu/cpu/upd7810/upd7810_macros.h
r0	r30938
	1	/***************************************************************************
	2
	3	uPD7810/11, 7810H/11H, 78C10/C11/C14 private use macros
	4
	5	***************************************************************************/
	6
	7	//**************************************************************************
	8	// REGISTER
	9	//**************************************************************************
	10
	11	#define PPC m_ppc.w.l
	12	#define PC m_pc.w.l
	13	#define PCL m_pc.b.l
	14	#define PCH m_pc.b.h
	15	#define PCD m_pc.d
	16	#define SP m_sp.w.l
	17	#define SPL m_sp.b.l
	18	#define SPH m_sp.b.h
	19	#define SPD m_sp.d
	20	#define PSW m_psw
	21	#define OP m_op
	22	#define OP2 m_op2
	23	#define IFF m_iff
	24	#define EA m_ea.w.l
	25	#define EAL m_ea.b.l
	26	#define EAH m_ea.b.h
	27	#define VA m_va.w.l
	28	#define V m_va.b.h
	29	#define A m_va.b.l
	30	#define VAD m_va.d
	31	#define BC m_bc.w.l
	32	#define B m_bc.b.h
	33	#define C m_bc.b.l
	34	#define DE m_de.w.l
	35	#define D m_de.b.h
	36	#define E m_de.b.l
	37	#define HL m_hl.w.l
	38	#define H m_hl.b.h
	39	#define L m_hl.b.l
	40	#define EA2 m_ea2.w.l
	41	#define VA2 m_va2.w.l
	42	#define BC2 m_bc2.w.l
	43	#define DE2 m_de2.w.l
	44	#define HL2 m_hl2.w.l
	45
	46	#define OVC0 m_ovc0
	47	#define OVC1 m_ovc1
	48	#define OVCE m_ovce
	49	#define OVCF m_ovcf
	50	#define OVCS m_ovcs
	51	#define EDGES m_edges
	52
	53	#define CNT0 m_cnt.b.l
	54	#define CNT1 m_cnt.b.h
	55	#define TM0 m_tm.b.l
	56	#define TM1 m_tm.b.h
	57	#define ECNT m_ecnt.w.l
	58	#define ECPT m_ecnt.w.h
	59	#define ETM0 m_etm.w.l
	60	#define ETM1 m_etm.w.h
	61
	62	#define MA m_ma
	63	#define MB m_mb
	64	#define MCC m_mcc
	65	#define MC m_mc
	66	#define MM m_mm
	67	#define MF m_mf
	68	#define TMM m_tmm
	69	#define ETMM m_etmm
	70	#define EOM m_eom
	71	#define SML m_sml
	72	#define SMH m_smh
	73	#define PANM m_panm
	74	#define ANM m_anm
	75	#define MKL m_mkl
	76	#define MKH m_mkh
	77	#define ZCM m_zcm
	78
	79	#define CR0 m_cr0
	80	#define CR1 m_cr1
	81	#define CR2 m_cr2
	82	#define CR3 m_cr3
	83	#define RXB m_rxb
	84	#define TXB m_txb
	85
	86	#define RXD m_rxd
	87	#define TXD m_txd
	88	#define SCK m_sck
	89	#define TI m_ti
	90	#define TO m_to
	91	#define CI m_ci
	92	#define CO0 m_co0
	93	#define CO1 m_co1
	94
	95	#define IRR m_irr
	96	#define ITF m_itf
	97
	98
	99	//**************************************************************************
	100	// MEMORY/OPCODE READ/WRITE
	101	//**************************************************************************
	102
	103	#define RDOP(O) O = m_direct->read_decrypted_byte(PCD); PC++
	104	#define RDOPARG(A) A = m_direct->read_raw_byte(PCD); PC++
	105	#define RM(A) m_program->read_byte(A)
	106	#define WM(A,V) m_program->write_byte(A,V)
	107
	108
	109	//**************************************************************************
	110	// PSW OPERATIONS
	111	//**************************************************************************
	112
	113	#define ZHC_ADD(after,before,carry) \
	114	if (after == 0) PSW \|= Z; else PSW &= ~Z; \
	115	if (after == before) \
	116	PSW = (PSW&~CY) \| (carry); \
	117	else if (after < before) \
	118	PSW \|= CY; \
	119	else \
	120	PSW &= ~CY; \
	121	if ((after & 15) < (before & 15)) \
	122	PSW \|= HC; \
	123	else \
	124	PSW &= ~HC;
	125
	126	#define ZHC_SUB(after,before,carry) \
	127	if (after == 0) PSW \|= Z; else PSW &= ~Z; \
	128	if (before == after) \
	129	PSW = (PSW & ~CY) \| (carry); \
	130	else if (after > before) \
	131	PSW \|= CY; \
	132	else \
	133	PSW &= ~CY; \
	134	if ((after & 15) > (before & 15)) \
	135	PSW \|= HC; \
	136	else \
	137	PSW &= ~HC;
	138
	139	#define SKIP_CY if (CY == (PSW & CY)) PSW \|= SK
	140	#define SKIP_NC if (0 == (PSW & CY)) PSW \|= SK
	141	#define SKIP_Z if (Z == (PSW & Z)) PSW \|= SK
	142	#define SKIP_NZ if (0 == (PSW & Z)) PSW \|= SK
	143
	144	#define SET_Z(n) if (n) PSW &= ~Z; else PSW \|= Z

Property changes on: trunk/src/emu/cpu/upd7810/upd7810_macros.h
Added: svn:mime-type + text/plain Added: svn:eol-style + native

trunk/src/emu/cpu/upd7810/upd7810_opcodes.c
r0	r30938
	1	/*****************************************************************************
	2	*
	3	* Portable uPD7810/11, 7810H/11H, 78C10/C11/C14 emulator V0.2
	4	* Copyright Juergen Buchmueller, all rights reserved.
	5	*
	6	* 7810ops.inc - opcode functions
	7	*
	8	*****************************************************************************/
	9
	10	#include "emu.h"
	11	#include "upd7810.h"
	12	#include "upd7810_macros.h"
	13
	14	void upd7810_device::illegal()
	15	{
	16	logerror("uPD7810 '%s': illegal opcode %02x at PC:%04x\n", tag(), OP, PC);
	17	}
	18
	19	void upd7810_device::illegal2()
	20	{
	21	logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", tag(), OP, OP2, PC);
	22	}
	23
	24	/* prefix 48 */
	25
	26	/* 48 01: 0100 1000 0000 0001 */
	27	void upd7810_device::SLRC_A()
	28	{
	29	PSW = (PSW & ~CY) \| (A & CY);
	30	A >>= 1;
	31	SKIP_CY;
	32	}
	33
	34	/* 48 02: 0100 1000 0000 0010 */
	35	void upd7810_device::SLRC_B()
	36	{
	37	PSW = (PSW & ~CY) \| (B & CY);
	38	B >>= 1;
	39	SKIP_CY;
	40	}
	41
	42	/* 48 03: 0100 1000 0000 0011 */
	43	void upd7810_device::SLRC_C()
	44	{
	45	PSW = (PSW & ~CY) \| (C & CY);
	46	C >>= 1;
	47	SKIP_CY;
	48	}
	49
	50
	51	/* 48 05: 0100 1000 0000 0101 */
	52	void upd7810_device::SLLC_A()
	53	{
	54	PSW = (PSW & ~CY) \| ((A >> 7) & CY);
	55	A <<= 1;
	56	SKIP_CY;
	57	}
	58
	59	/* 48 06: 0100 1000 0000 0110 */
	60	void upd7810_device::SLLC_B()
	61	{
	62	PSW = (PSW & ~CY) \| ((B >> 7) & CY);
	63	B <<= 1;
	64	SKIP_CY;
	65	}
	66
	67	/* 48 07: 0100 1000 0000 0111 */
	68	void upd7810_device::SLLC_C()
	69	{
	70	PSW = (PSW & ~CY) \| ((C >> 7) & CY);
	71	C <<= 1;
	72	SKIP_CY;
	73	}
	74
	75	/* 48 08: 0100 1000 0000 1000 */
	76	void upd7810_device::SK_NV()
	77	{
	78	/* 48 skip never */
	79	}
	80
	81	/* 48 0a: 0100 1000 0000 1010 */
	82	void upd7810_device::SK_CY()
	83	{
	84	if (CY == (PSW & CY))
	85	PSW \|= SK;
	86	}
	87
	88	/* 48 0b: 0100 1000 0000 1011 */
	89	void upd7810_device::SK_HC()
	90	{
	91	if (HC == (PSW & HC))
	92	PSW \|= SK;
	93	}
	94
	95	/* 48 0c: 0100 1000 0000 1100 */
	96	void upd7810_device::SK_Z()
	97	{
	98	if (Z == (PSW & Z))
	99	PSW \|= SK;
	100	}
	101
	102	/* 48 18: 0100 1000 0001 1000 */
	103	void upd7810_device::SKN_NV()
	104	{
	105	/* skip not never -> skip always ;-) */
	106	PSW \|= SK;
	107	}
	108
	109	/* 48 1a: 0100 1000 0001 1010 */
	110	void upd7810_device::SKN_CY()
	111	{
	112	if (0 == (PSW & CY))
	113	PSW \|= SK;
	114	}
	115
	116	/* 48 1b: 0100 1000 0001 1011 */
	117	void upd7810_device::SKN_HC()
	118	{
	119	if (0 == (PSW & HC))
	120	PSW \|= SK;
	121	}
	122
	123	/* 48 1c: 0100 1000 0001 1100 */
	124	void upd7810_device::SKN_Z()
	125	{
	126	if (0 == (PSW & Z))
	127	PSW \|= SK;
	128	}
	129
	130	/* 48 21: 0100 1000 0010 0001 */
	131	void upd7810_device::SLR_A()
	132	{
	133	PSW = (PSW & ~CY) \| (A & CY);
	134	A >>= 1;
	135	}
	136
	137	/* 48 22: 0100 1000 0010 0010 */
	138	void upd7810_device::SLR_B()
	139	{
	140	PSW = (PSW & ~CY) \| (B & CY);
	141	B >>= 1;
	142	}
	143
	144	/* 48 23: 0100 1000 0010 0011 */
	145	void upd7810_device::SLR_C()
	146	{
	147	PSW = (PSW & ~CY) \| (C & CY);
	148	C >>= 1;
	149	}
	150
	151	/* 48 25: 0100 1000 0010 0101 */
	152	void upd7810_device::SLL_A()
	153	{
	154	PSW = (PSW & ~CY) \| ((A >> 7) & CY);
	155	A <<= 1;
	156	}
	157
	158	/* 48 26: 0100 1000 0010 0110 */
	159	void upd7810_device::SLL_B()
	160	{
	161	PSW = (PSW & ~CY) \| ((B >> 7) & CY);
	162	B <<= 1;
	163	}
	164
	165	/* 48 27: 0100 1000 0010 0111 */
	166	void upd7810_device::SLL_C()
	167	{
	168	PSW = (PSW & ~CY) \| ((C >> 7) & CY);
	169	C <<= 1;
	170	}
	171
	172	/* 48 28: 0100 1000 0010 1000 */
	173	void upd7810_device::JEA()
	174	{
	175	PC = EA;
	176	}
	177
	178	/* 48 29: 0100 1000 0010 1001 */
	179	void upd7810_device::CALB()
	180	{
	181	SP--;
	182	WM( SPD, PCH );
	183	SP--;
	184	WM( SPD, PCL );
	185
	186	PC = BC;
	187	}
	188
	189	/* 48 2a: 0100 1000 0010 1010 */
	190	void upd7810_device::CLC()
	191	{
	192	PSW &= ~CY;
	193	}
	194
	195	/* 48 2b: 0100 1000 0010 1011 */
	196	void upd7810_device::STC()
	197	{
	198	PSW \|= CY;
	199	}
	200
	201	/* 48 2d: 0100 1000 0010 1101 */
	202	void upd7810_device::MUL_A()
	203	{
	204	EA = A * A;
	205	}
	206
	207	/* 48 2e: 0100 1000 0010 1110 */
	208	void upd7810_device::MUL_B()
	209	{
	210	EA = A * B;
	211	}
	212
	213	/* 48 2f: 0100 1000 0010 1111 */
	214	void upd7810_device::MUL_C()
	215	{
	216	EA = A * C;
	217	}
	218
	219	/* 48 31: 0100 1000 0011 0001 */
	220	void upd7810_device::RLR_A()
	221	{
	222	UINT8 carry=(PSW&CY)<<7;
	223	PSW = (PSW & ~CY) \| (A & CY);
	224	A = (A >> 1) \| carry;
	225	}
	226
	227	/* 48 32: 0100 1000 0011 0010 */
	228	void upd7810_device::RLR_B()
	229	{
	230	UINT8 carry=(PSW&CY)<<7;
	231	PSW = (PSW & ~CY) \| (B & CY);
	232	B = (B >> 1) \| carry;
	233	}
	234
	235	/* 48 33: 0100 1000 0011 0011 */
	236	void upd7810_device::RLR_C()
	237	{
	238	UINT8 carry=(PSW&CY)<<7;
	239	PSW = (PSW & ~CY) \| (C & CY);
	240	C = (C >> 1) \| carry;
	241	}
	242
	243	/* 48 35: 0100 1000 0011 0101 */
	244	void upd7810_device::RLL_A()
	245	{
	246	UINT8 carry=PSW&CY;
	247	PSW = (PSW & ~CY) \| ((A >> 7) & CY);
	248	A = (A << 1) \| carry;
	249	}
	250
	251	/* 48 36: 0100 1000 0011 0110 */
	252	void upd7810_device::RLL_B()
	253	{
	254	UINT8 carry=PSW&CY;
	255	PSW = (PSW & ~CY) \| ((B >> 7) & CY);
	256	B = (B << 1) \| carry;
	257	}
	258
	259	/* 48 37: 0100 1000 0011 0111 */
	260	void upd7810_device::RLL_C()
	261	{
	262	UINT8 carry=PSW&CY;
	263	PSW = (PSW & ~CY) \| ((C >> 7) & CY);
	264	C = (C << 1) \| carry;
	265	}
	266
	267	/* 48 38: 0100 1000 0011 1000 */
	268	void upd7810_device::RLD()
	269	{
	270	UINT8 m = RM( HL ), tmp;
	271	tmp = (m << 4) \| (A & 0x0f);
	272	A = (A & 0xf0) \| (m >> 4);
	273	WM( HL, tmp );
	274	}
	275
	276	/* 48 39: 0100 1000 0011 1001 */
	277	void upd7810_device::RRD()
	278	{
	279	UINT8 m = RM( HL ), tmp;
	280	tmp = (A << 4) \| (m >> 4);
	281	A = (A & 0xf0) \| (m & 0x0f);
	282	WM( HL, tmp );
	283	}
	284
	285	/* 48 3a: 0100 1000 0011 1010 */
	286	void upd7810_device::NEGA()
	287	{
	288	A = ~A + 1;
	289	}
	290
	291	/* 48 3b: 0100 1000 0011 1011 */
	292	void upd7810_device::HALT()
	293	{
	294	int cycles = (m_icount / 4) * 4;
	295	m_icount -= cycles;
	296	handle_timers(cycles);
	297	PC -= 1; /* continue executing HALT */
	298	}
	299
	300	/* 48 3d: 0100 1000 0011 1101 */
	301	void upd7810_device::DIV_A()
	302	{
	303	if (A)
	304	{
	305	UINT8 remainder;
	306	remainder = EA % A;
	307	EA /= A;
	308	A = remainder;
	309	}
	310	else
	311	EA = 0xffff; /* guess */
	312	}
	313
	314	/* 48 3e: 0100 1000 0011 1110 */
	315	void upd7810_device::DIV_B()
	316	{
	317	if (B)
	318	{
	319	UINT8 remainder;
	320	remainder = EA % B;
	321	EA /= B;
	322	B = remainder;
	323	}
	324	else
	325	EA = 0xffff; /* guess */
	326	}
	327
	328	/* 48 3f: 0100 1000 0011 1111 */
	329	void upd7810_device::DIV_C()
	330	{
	331	if (C)
	332	{
	333	UINT8 remainder;
	334	remainder = EA % C;
	335	EA /= C;
	336	C = remainder;
	337	}
	338	else
	339	EA = 0xffff; /* guess */
	340	}
	341
	342	/* 48 40: 0100 1000 0100 0000 */
	343	void upd7810_device::SKIT_NMI()
	344	{
	345	if (IRR & INTNMI)
	346	PSW \|= SK;
	347	IRR &= ~INTNMI;
	348	}
	349
	350	/* 48 41: 0100 1000 0100 0001 */
	351	void upd7810_device::SKIT_FT0()
	352	{
	353	if (IRR & INTFT0)
	354	PSW \|= SK;
	355	IRR &= ~INTFT0;
	356	}
	357
	358	/* 48 42: 0100 1000 0100 0010 */
	359	void upd7810_device::SKIT_FT1()
	360	{
	361	if (IRR & INTFT1)
	362	PSW \|= SK;
	363	IRR &= ~INTFT1;
	364	}
	365
	366	/* 48 43: 0100 1000 0100 0011 */
	367	void upd7810_device::SKIT_F1()
	368	{
	369	if (IRR & INTF1)
	370	PSW \|= SK;
	371	IRR &= ~INTF1;
	372	}
	373
	374	/* 48 44: 0100 1000 0100 0100 */
	375	void upd7810_device::SKIT_F2()
	376	{
	377	if (IRR & INTF2)
	378	PSW \|= SK;
	379	IRR &= ~INTF2;
	380	}
	381
	382	/* 48 45: 0100 1000 0100 0101 */
	383	void upd7810_device::SKIT_FE0()
	384	{
	385	if (IRR & INTFE0)
	386	PSW \|= SK;
	387	IRR &= ~INTFE0;
	388	}
	389
	390	/* 48 46: 0100 1000 0100 0110 */
	391	void upd7810_device::SKIT_FE1()
	392	{
	393	if (IRR & INTFE1)
	394	PSW \|= SK;
	395	IRR &= ~INTFE1;
	396	}
	397
	398	/* 48 47: 0100 1000 0100 0111 */
	399	void upd7810_device::SKIT_FEIN()
	400	{
	401	if (IRR & INTFEIN)
	402	PSW \|= SK;
	403	IRR &= ~INTFEIN;
	404	}
	405
	406	/* 48 48: 0100 1000 0100 1000 */
	407	void upd7810_device::SKIT_FAD()
	408	{
	409	if (IRR & INTFAD)
	410	PSW \|= SK;
	411	IRR &= ~INTFAD;
	412	}
	413
	414	/* 48 49: 0100 1000 0100 1001 */
	415	void upd7810_device::SKIT_FSR()
	416	{
	417	if (IRR & INTFSR)
	418	PSW \|= SK;
	419	IRR &= ~INTFSR;
	420	}
	421
	422	/* 48 4a: 0100 1000 0100 1010 */
	423	void upd7810_device::SKIT_FST()
	424	{
	425	if (IRR & INTFST)
	426	PSW \|= SK;
	427	IRR &= ~INTFST;
	428	}
	429
	430	/* 48 4b: 0100 1000 0100 1011 */
	431	void upd7810_device::SKIT_ER()
	432	{
	433	if (IRR & INTER)
	434	PSW \|= SK;
	435	IRR &= ~INTER;
	436	}
	437
	438	/* 48 4c: 0100 1000 0100 1100 */
	439	void upd7810_device::SKIT_OV()
	440	{
	441	if (IRR & INTOV)
	442	PSW \|= SK;
	443	IRR &= ~INTOV;
	444	}
	445
	446	/* 48 50: 0100 1000 0101 0000 */
	447	void upd7810_device::SKIT_AN4()
	448	{
	449	if (ITF & INTAN4)
	450	PSW \|= SK;
	451	ITF &= ~INTAN4;
	452	}
	453
	454	/* 48 51: 0100 1000 0101 0001 */
	455	void upd7810_device::SKIT_AN5()
	456	{
	457	if (ITF & INTAN5)
	458	PSW \|= SK;
	459	ITF &= ~INTAN5;
	460	}
	461
	462	/* 48 52: 0100 1000 0101 0010 */
	463	void upd7810_device::SKIT_AN6()
	464	{
	465	if (ITF & INTAN6)
	466	PSW \|= SK;
	467	ITF &= ~INTAN6;
	468	}
	469
	470	/* 48 53: 0100 1000 0101 0011 */
	471	void upd7810_device::SKIT_AN7()
	472	{
	473	if (ITF & INTAN7)
	474	PSW \|= SK;
	475	ITF &= ~INTAN7;
	476	}
	477
	478	/* 48 54: 0100 1000 0101 0100 */
	479	void upd7810_device::SKIT_SB()
	480	{
	481	if (ITF & INTSB)
	482	PSW \|= SK;
	483	ITF &= ~INTSB;
	484	}
	485
	486	/* 48 60: 0100 1000 0110 0000 */
	487	void upd7810_device::SKNIT_NMI()
	488	{
	489	if (0 == (IRR & INTNMI))
	490	PSW \|= SK;
	491	IRR &= ~INTNMI;
	492	}
	493
	494	/* 48 61: 0100 1000 0110 0001 */
	495	void upd7810_device::SKNIT_FT0()
	496	{
	497	if (0 == (IRR & INTFT0))
	498	PSW \|= SK;
	499	IRR &= ~INTFT0;
	500	}
	501
	502	/* 48 62: 0100 1000 0110 0010 */
	503	void upd7810_device::SKNIT_FT1()
	504	{
	505	if (0 == (IRR & INTFT1))
	506	PSW \|= SK;
	507	IRR &= ~INTFT1;
	508	}
	509
	510	/* 48 63: 0100 1000 0110 0011 */
	511	void upd7810_device::SKNIT_F1()
	512	{
	513	if (0 == (IRR & INTF1))
	514	PSW \|= SK;
	515	IRR &= ~INTF1;
	516	}
	517
	518	/* 48 64: 0100 1000 0110 0100 */
	519	void upd7810_device::SKNIT_F2()
	520	{
	521	if (0 == (IRR & INTF2))
	522	PSW \|= SK;
	523	IRR &= ~INTF2;
	524	}
	525
	526	/* 48 65: 0100 1000 0110 0101 */
	527	void upd7810_device::SKNIT_FE0()
	528	{
	529	if (0 == (IRR & INTFE0))
	530	PSW \|= SK;
	531	IRR &= ~INTFE0;
	532	}
	533
	534	/* 48 66: 0100 1000 0110 0110 */
	535	void upd7810_device::SKNIT_FE1()
	536	{
	537	if (0 == (IRR & INTFE1))
	538	PSW \|= SK;
	539	IRR &= ~INTFE1;
	540	}
	541
	542	/* 48 67: 0100 1000 0110 0111 */
	543	void upd7810_device::SKNIT_FEIN()
	544	{
	545	if (0 == (IRR & INTFEIN))
	546	PSW \|= SK;
	547	IRR &= ~INTFEIN;
	548	}
	549
	550	/* 48 68: 0100 1000 0110 1000 */
	551	void upd7810_device::SKNIT_FAD()
	552	{
	553	if (0 == (IRR & INTFAD))
	554	PSW \|= SK;
	555	IRR &= ~INTFAD;
	556	}
	557
	558	/* 48 69: 0100 1000 0110 1001 */
	559	void upd7810_device::SKNIT_FSR()
	560	{
	561	if (0 == (IRR & INTFSR))
	562	PSW \|= SK;
	563	IRR &= ~INTFSR;
	564	}
	565
	566	/* 48 6a: 0100 1000 0110 1010 */
	567	void upd7810_device::SKNIT_FST()
	568	{
	569	if (0 == (IRR & INTFST))
	570	PSW \|= SK;
	571	IRR &= ~INTFST;
	572	}
	573
	574	/* 48 6b: 0100 1000 0110 1011 */
	575	void upd7810_device::SKNIT_ER()
	576	{
	577	if (0 == (IRR & INTER))
	578	PSW \|= SK;
	579	IRR &= ~INTER;
	580	}
	581
	582	/* 48 6c: 0100 1000 0110 1100 */
	583	void upd7810_device::SKNIT_OV()
	584	{
	585	if (0 == (IRR & INTOV))
	586	PSW \|= SK;
	587	IRR &= ~INTOV;
	588	}
	589
	590	/* 48 70: 0100 1000 0111 0000 */
	591	void upd7810_device::SKNIT_AN4()
	592	{
	593	if (0 == (ITF & INTAN4))
	594	PSW \|= SK;
	595	ITF &= ~INTAN4;
	596	}
	597
	598	/* 48 71: 0100 1000 0111 0001 */
	599	void upd7810_device::SKNIT_AN5()
	600	{
	601	if (0 == (ITF & INTAN5))
	602	PSW \|= SK;
	603	ITF &= ~INTAN5;
	604	}
	605
	606	/* 48 72: 0100 1000 0111 0010 */
	607	void upd7810_device::SKNIT_AN6()
	608	{
	609	if (0 == (ITF & INTAN6))
	610	PSW \|= SK;
	611	ITF &= ~INTAN6;
	612	}
	613
	614	/* 48 73: 0100 1000 0111 0011 */
	615	void upd7810_device::SKNIT_AN7()
	616	{
	617	if (0 == (ITF & INTAN7))
	618	PSW \|= SK;
	619	ITF &= ~INTAN7;
	620	}
	621
	622	/* 48 74: 0100 1000 0111 0100 */
	623	void upd7810_device::SKNIT_SB()
	624	{
	625	if (0 == (ITF & INTSB))
	626	PSW \|= SK;
	627	ITF &= ~INTSB;
	628	}
	629
	630	/* 48 82: 0100 1000 1000 0010 */
	631	void upd7810_device::LDEAX_D()
	632	{
	633	EAL = RM( DE );
	634	EAH = RM( DE + 1 );
	635	}
	636
	637	/* 48 83: 0100 1000 1000 0011 */
	638	void upd7810_device::LDEAX_H()
	639	{
	640	EAL = RM( HL );
	641	EAH = RM( HL + 1 );
	642	}
	643
	644	/* 48 84: 0100 1000 1000 0100 */
	645	void upd7810_device::LDEAX_Dp()
	646	{
	647	EAL = RM( DE );
	648	EAH = RM( DE + 1 );
	649	DE += 2;
	650	}
	651
	652	/* 48 85: 0100 1000 1000 0101 */
	653	void upd7810_device::LDEAX_Hp()
	654	{
	655	EAL = RM( HL );
	656	EAH = RM( HL + 1 );
	657	HL += 2;
	658	}
	659
	660	/* 48 8b: 0100 1000 1000 1011 xxxx xxxx */
	661	void upd7810_device::LDEAX_D_xx()
	662	{
	663	UINT16 ea;
	664	RDOPARG( ea );
	665	ea += DE;
	666	EAL = RM( ea );
	667	EAH = RM( ea + 1 );
	668	}
	669
	670	/* 48 8c: 0100 1000 1000 1100 */
	671	void upd7810_device::LDEAX_H_A()
	672	{
	673	UINT16 ea = HL + A;
	674	EAL = RM( ea );
	675	EAH = RM( ea + 1 );
	676	}
	677
	678	/* 48 8d: 0100 1000 1000 1101 */
	679	void upd7810_device::LDEAX_H_B()
	680	{
	681	UINT16 ea = HL + B;
	682	EAL = RM( ea );
	683	EAH = RM( ea + 1 );
	684	}
	685
	686	/* 48 8e: 0100 1000 1000 1110 */
	687	void upd7810_device::LDEAX_H_EA()
	688	{
	689	UINT16 ea = HL + EA;
	690	EAL = RM( ea );
	691	EAH = RM( ea + 1 );
	692	}
	693
	694	/* 48 8f: 0100 1000 1000 1111 xxxx xxxx */
	695	void upd7810_device::LDEAX_H_xx()
	696	{
	697	UINT16 ea;
	698	RDOPARG( ea );
	699	ea += HL;
	700	EAL = RM( ea );
	701	EAH = RM( ea + 1 );
	702	}
	703
	704	/* 48 92: 0100 1000 1000 0010 */
	705	void upd7810_device::STEAX_D()
	706	{
	707	WM( DE, EAL );
	708	WM( DE + 1, EAH );
	709	}
	710
	711	/* 48 93: 0100 1000 1000 0011 */
	712	void upd7810_device::STEAX_H()
	713	{
	714	WM( HL, EAL );
	715	WM( HL + 1, EAH );
	716	}
	717
	718	/* 48 94: 0100 1000 1000 0100 */
	719	void upd7810_device::STEAX_Dp()
	720	{
	721	WM( DE, EAL );
	722	WM( DE + 1, EAH );
	723	DE += 2;
	724	}
	725
	726	/* 48 95: 0100 1000 1000 0101 */
	727	void upd7810_device::STEAX_Hp()
	728	{
	729	WM( HL, EAL );
	730	WM( HL + 1, EAH );
	731	HL += 2;
	732	}
	733
	734	/* 48 9b: 0100 1000 1000 1011 xxxx xxxx */
	735	void upd7810_device::STEAX_D_xx()
	736	{
	737	UINT16 ea;
	738	RDOPARG( ea );
	739	ea += DE;
	740	WM( ea, EAL );
	741	WM( ea + 1, EAH );
	742	}
	743
	744	/* 48 9c: 0100 1000 1000 1100 */
	745	void upd7810_device::STEAX_H_A()
	746	{
	747	UINT16 ea = HL + A;
	748	WM( ea, EAL );
	749	WM( ea + 1, EAH );
	750	}
	751
	752	/* 48 9d: 0100 1000 1000 1101 */
	753	void upd7810_device::STEAX_H_B()
	754	{
	755	UINT16 ea = HL + B;
	756	WM( ea, EAL );
	757	WM( ea + 1, EAH );
	758	}
	759
	760	/* 48 9e: 0100 1000 1000 1110 */
	761	void upd7810_device::STEAX_H_EA()
	762	{
	763	UINT16 ea = HL + EA;
	764	WM( ea, EAL );
	765	WM( ea + 1, EAH );
	766	}
	767
	768	/* 48 9f: 0100 1000 1000 1111 xxxx xxxx */
	769	void upd7810_device::STEAX_H_xx()
	770	{
	771	UINT16 ea;
	772	RDOPARG( ea );
	773	ea += HL;
	774	WM( ea, EAL );
	775	WM( ea + 1, EAH );
	776	}
	777
	778	/* 48 a0: 0100 1000 1010 0000 */
	779	void upd7810_device::DSLR_EA()
	780	{
	781	PSW = (PSW & ~CY) \| (EA & CY);
	782	EA >>= 1;
	783	}
	784
	785	/* 48 a4: 0100 1000 1010 0100 */
	786	void upd7810_device::DSLL_EA()
	787	{
	788	PSW = (PSW & ~CY) \| ((EA >> 15) & CY);
	789	EA <<= 1;
	790	}
	791
	792	/* 48 a8: 0100 1000 1010 1000 */
	793	void upd7810_device::TABLE()
	794	{
	795	UINT16 ea = PC + A + 1;
	796	C = RM( ea );
	797	B = RM( ea + 1 );
	798	}
	799
	800	/* 48 b0: 0100 1000 1011 0000 */
	801	void upd7810_device::DRLR_EA()
	802	{
	803	UINT8 carry=PSW&CY;
	804	PSW = (PSW & ~CY) \| (EA & CY);
	805	EA = (EA >> 1) \| (carry << 15);
	806	}
	807
	808	/* 48 b4: 0100 1000 1011 0100 */
	809	void upd7810_device::DRLL_EA()
	810	{
	811	UINT8 carry=PSW&CY;
	812	PSW = (PSW & ~CY) \| ((EA >> 15) & CY);
	813	EA = (EA << 1) \| carry;
	814	}
	815
	816	/* 48 bb: 0100 1000 1011 1011 */
	817	void upd7810_device::STOP()
	818	{
	819	int cycles = (m_icount / 4) * 4;
	820	m_icount -= cycles;
	821	handle_timers(cycles);
	822	PC -= 1;
	823	}
	824
	825	/* 48 c0: 0100 1000 1100 0000 */
	826	void upd7810_device::DMOV_EA_ECNT()
	827	{
	828	EA = ECNT;
	829	}
	830
	831	/* 48 c1: 0100 1000 1100 0001 */
	832	void upd7810_device::DMOV_EA_ECPT()
	833	{
	834	EA = ECPT;
	835	}
	836
	837	/* 48 d2: 0100 1000 1101 0010 */
	838	void upd7810_device::DMOV_ETM0_EA()
	839	{
	840	ETM0 = EA;
	841	}
	842
	843	/* 48 d3: 0100 1000 1101 0011 */
	844	void upd7810_device::DMOV_ETM1_EA()
	845	{
	846	ETM1 = EA;
	847	}
	848
	849	/* prefix 4C */
	850	/* 4c c0: 0100 1100 1100 0000 */
	851	void upd7810_device::MOV_A_PA()
	852	{
	853	A = RP( UPD7810_PORTA );
	854	}
	855
	856	/* 4c c1: 0100 1100 1100 0001 */
	857	void upd7810_device::MOV_A_PB()
	858	{
	859	A = RP( UPD7810_PORTB );
	860	}
	861
	862	/* 4c c2: 0100 1100 1100 0010 */
	863	void upd7810_device::MOV_A_PC()
	864	{
	865	A = RP( UPD7810_PORTC );
	866	}
	867
	868	/* 4c c3: 0100 1100 1100 0011 */
	869	void upd7810_device::MOV_A_PD()
	870	{
	871	A = RP( UPD7810_PORTD );
	872	}
	873
	874	/* 4c c5: 0100 1100 1100 0101 */
	875	void upd7810_device::MOV_A_PF()
	876	{
	877	A = RP( UPD7810_PORTF );
	878	}
	879
	880	/* 4c c6: 0100 1100 1100 0110 */
	881	void upd7810_device::MOV_A_MKH()
	882	{
	883	A = MKH;
	884	}
	885
	886	/* 4c c7: 0100 1100 1100 0111 */
	887	void upd7810_device::MOV_A_MKL()
	888	{
	889	A = MKL;
	890	}
	891
	892	/* 4c c8: 0100 1100 1100 1000 */
	893	void upd7810_device::MOV_A_ANM()
	894	{
	895	A = ANM;
	896	}
	897
	898	/* 4c c9: 0100 1100 1100 1001 */
	899	void upd7810_device::MOV_A_SMH()
	900	{
	901	A = SMH;
	902	}
	903
	904	/* 4c cb: 0100 1100 1100 1011 */
	905	void upd7810_device::MOV_A_EOM()
	906	{
	907	/* only bits #1 and #5 can be read */
	908	UINT8 eom = EOM & 0x22;
	909	A = eom;
	910	}
	911
	912	/* 4c cd: 0100 1100 1100 1101 */
	913	void upd7810_device::MOV_A_TMM()
	914	{
	915	A = TMM;
	916	}
	917
	918	/* 4c ce: 0100 1100 1110 0000 (7807 only) */
	919	void upd7810_device::MOV_A_PT()
	920	{
	921	A = RP( UPD7807_PORTT );
	922	}
	923
	924	/* 4c d9: 0100 1100 1101 1001 */
	925	void upd7810_device::MOV_A_RXB()
	926	{
	927	A = RXB;
	928	}
	929
	930	/* 4c e0: 0100 1100 1110 0000 */
	931	void upd7810_device::MOV_A_CR0()
	932	{
	933	A = CR0;
	934	}
	935
	936	/* 4c e1: 0100 1100 1110 0001 */
	937	void upd7810_device::MOV_A_CR1()
	938	{
	939	A = CR1;
	940	}
	941
	942	/* 4c e2: 0100 1100 1110 0010 */
	943	void upd7810_device::MOV_A_CR2()
	944	{
	945	A = CR2;
	946	}
	947
	948	/* 4c e3: 0100 1100 1110 0011 */
	949	void upd7810_device::MOV_A_CR3()
	950	{
	951	A = CR3;
	952	}
	953
	954	/* prefix 4D */
	955	/* 4d c0: 0100 1101 1100 0000 */
	956	void upd7810_device::MOV_PA_A()
	957	{
	958	WP( UPD7810_PORTA, A );
	959	}
	960
	961	/* 4d c1: 0100 1101 1100 0001 */
	962	void upd7810_device::MOV_PB_A()
	963	{
	964	WP( UPD7810_PORTB, A );
	965	}
	966
	967	/* 4d c2: 0100 1101 1100 0010 */
	968	void upd7810_device::MOV_PC_A()
	969	{
	970	WP( UPD7810_PORTC, A );
	971	}
	972
	973	/* 4d c3: 0100 1101 1100 0011 */
	974	void upd7810_device::MOV_PD_A()
	975	{
	976	WP( UPD7810_PORTD, A );
	977	}
	978
	979	/* 4d c5: 0100 1101 1100 0101 */
	980	void upd7810_device::MOV_PF_A()
	981	{
	982	WP( UPD7810_PORTF, A );
	983	}
	984
	985	/* 4d c6: 0100 1101 1100 0110 */
	986	void upd7810_device::MOV_MKH_A()
	987	{
	988	MKH = A;
	989	}
	990
	991	/* 4d c7: 0100 1101 1100 0111 */
	992	void upd7810_device::MOV_MKL_A()
	993	{
	994	MKL = A;
	995	}
	996
	997	/* 4d c8: 0100 1101 1100 1000 */
	998	void upd7810_device::MOV_ANM_A()
	999	{
	1000	ANM = A;
	1001	}
	1002
	1003	/* 4d c9: 0100 1101 1100 1001 */
	1004	void upd7810_device::MOV_SMH_A()
	1005	{
	1006	SMH = A;
	1007	}
	1008
	1009	/* 4d ca: 0100 1101 1100 1010 */
	1010	void upd7810_device::MOV_SML_A()
	1011	{
	1012	SML = A;
	1013	}
	1014
	1015	/* 4d cb: 0100 1101 1100 1011 */
	1016	void upd7810_device::MOV_EOM_A()
	1017	{
	1018	EOM = A;
	1019	upd7810_write_EOM();
	1020	}
	1021
	1022	/* 4d cc: 0100 1101 1100 1100 */
	1023	void upd7810_device::MOV_ETMM_A()
	1024	{
	1025	ETMM = A;
	1026	}
	1027
	1028	/* 4d cd: 0100 1101 1100 1101 */
	1029	void upd7810_device::MOV_TMM_A()
	1030	{
	1031	TMM = A;
	1032	}
	1033
	1034	/* 4d d0: 0100 1101 1101 0000 */
	1035	void upd7810_device::MOV_MM_A()
	1036	{
	1037	MM = A;
	1038	}
	1039
	1040	/* 4d d1: 0100 1101 1101 0001 */
	1041	void upd7810_device::MOV_MCC_A()
	1042	{
	1043	MCC = A;
	1044	}
	1045
	1046	/* 4d d2: 0100 1101 1101 0010 */
	1047	void upd7810_device::MOV_MA_A()
	1048	{
	1049	MA = A;
	1050	}
	1051
	1052	/* 4d d3: 0100 1101 1101 0011 */
	1053	void upd7810_device::MOV_MB_A()
	1054	{
	1055	MB = A;
	1056	}
	1057
	1058	/* 4d d4: 0100 1101 1101 0100 */
	1059	void upd7810_device::MOV_MC_A()
	1060	{
	1061	MC = A;
	1062	}
	1063
	1064	/* 4d d7: 0100 1101 1101 0111 */
	1065	void upd7810_device::MOV_MF_A()
	1066	{
	1067	MF = A;
	1068	}
	1069
	1070	/* 4d d8: 0100 1101 1101 1000 */
	1071	void upd7810_device::MOV_TXB_A()
	1072	{
	1073	TXB = A;
	1074	upd7810_write_TXB();
	1075	}
	1076
	1077	/* 4d da: 0100 1101 1101 1010 */
	1078	void upd7810_device::MOV_TM0_A()
	1079	{
	1080	TM0 = A;
	1081	}
	1082
	1083	/* 4d db: 0100 1101 1101 1011 */
	1084	void upd7810_device::MOV_TM1_A()
	1085	{
	1086	TM1 = A;
	1087	}
	1088
	1089	/* 4d e8: 0100 1101 1110 1000 */
	1090	void upd7810_device::MOV_ZCM_A()
	1091	{
	1092	ZCM = A;
	1093	}
	1094
	1095	/* prefix 60 */
	1096	/* 60 08: 0110 0000 0000 1000 */
	1097	void upd7810_device::ANA_V_A()
	1098	{
	1099	V &= A;
	1100	SET_Z(V);
	1101	}
	1102
	1103	/* 60 09: 0110 0000 0000 1001 */
	1104	void upd7810_device::ANA_A_A()
	1105	{
	1106	A &= A;
	1107	SET_Z(A);
	1108	}
	1109
	1110	/* 60 0a: 0110 0000 0000 1010 */
	1111	void upd7810_device::ANA_B_A()
	1112	{
	1113	B &= A;
	1114	SET_Z(B);
	1115	}
	1116
	1117	/* 60 0b: 0110 0000 0000 1011 */
	1118	void upd7810_device::ANA_C_A()
	1119	{
	1120	C &= A;
	1121	SET_Z(C);
	1122	}
	1123
	1124	/* 60 0c: 0110 0000 0000 1100 */
	1125	void upd7810_device::ANA_D_A()
	1126	{
	1127	D &= A;
	1128	SET_Z(D);
	1129	}
	1130
	1131	/* 60 0d: 0110 0000 0000 1101 */
	1132	void upd7810_device::ANA_E_A()
	1133	{
	1134	E &= A;
	1135	SET_Z(E);
	1136	}
	1137
	1138	/* 60 0e: 0110 0000 0000 1110 */
	1139	void upd7810_device::ANA_H_A()
	1140	{
	1141	H &= A;
	1142	SET_Z(H);
	1143	}
	1144
	1145	/* 60 0f: 0110 0000 0000 1111 */
	1146	void upd7810_device::ANA_L_A()
	1147	{
	1148	L &= A;
	1149	SET_Z(L);
	1150	}
	1151
	1152	/* 60 10: 0110 0000 0001 0000 */
	1153	void upd7810_device::XRA_V_A()
	1154	{
	1155	V ^= A;
	1156	SET_Z(V);
	1157	}
	1158
	1159	/* 60 11: 0110 0000 0001 0001 */
	1160	void upd7810_device::XRA_A_A()
	1161	{
	1162	A ^= A;
	1163	SET_Z(A);
	1164	}
	1165
	1166	/* 60 12: 0110 0000 0001 0010 */
	1167	void upd7810_device::XRA_B_A()
	1168	{
	1169	B ^= A;
	1170	SET_Z(B);
	1171	}
	1172
	1173	/* 60 13: 0110 0000 0001 0011 */
	1174	void upd7810_device::XRA_C_A()
	1175	{
	1176	C ^= A;
	1177	SET_Z(C);
	1178	}
	1179
	1180	/* 60 14: 0110 0000 0001 0100 */
	1181	void upd7810_device::XRA_D_A()
	1182	{
	1183	D ^= A;
	1184	SET_Z(D);
	1185	}
	1186
	1187	/* 60 15: 0110 0000 0001 0101 */
	1188	void upd7810_device::XRA_E_A()
	1189	{
	1190	E ^= A;
	1191	SET_Z(E);
	1192	}
	1193
	1194	/* 60 16: 0110 0000 0001 0110 */
	1195	void upd7810_device::XRA_H_A()
	1196	{
	1197	H ^= A;
	1198	SET_Z(H);
	1199	}
	1200
	1201	/* 60 17: 0110 0000 0001 0111 */
	1202	void upd7810_device::XRA_L_A()
	1203	{
	1204	L ^= A;
	1205	SET_Z(L);
	1206	}
	1207
	1208	/* 60 18: 0110 0000 0001 1000 */
	1209	void upd7810_device::ORA_V_A()
	1210	{
	1211	V \|= A;
	1212	SET_Z(V);
	1213	}
	1214
	1215	/* 60 19: 0110 0000 0001 1001 */
	1216	void upd7810_device::ORA_A_A()
	1217	{
	1218	A \|= A;
	1219	SET_Z(A);
	1220	}
	1221
	1222	/* 60 1a: 0110 0000 0001 1010 */
	1223	void upd7810_device::ORA_B_A()
	1224	{
	1225	B \|= A;
	1226	SET_Z(B);
	1227	}
	1228
	1229	/* 60 1b: 0110 0000 0001 1011 */
	1230	void upd7810_device::ORA_C_A()
	1231	{
	1232	C \|= A;
	1233	SET_Z(C);
	1234	}
	1235
	1236	/* 60 1c: 0110 0000 0001 1100 */
	1237	void upd7810_device::ORA_D_A()
	1238	{
	1239	D \|= A;
	1240	SET_Z(D);
	1241	}
	1242
	1243	/* 60 1d: 0110 0000 0001 1101 */
	1244	void upd7810_device::ORA_E_A()
	1245	{
	1246	E \|= A;
	1247	SET_Z(E);
	1248	}
	1249
	1250	/* 60 1e: 0110 0000 0001 1110 */
	1251	void upd7810_device::ORA_H_A()
	1252	{
	1253	H \|= A;
	1254	SET_Z(H);
	1255	}
	1256
	1257	/* 60 1f: 0110 0000 0001 1111 */
	1258	void upd7810_device::ORA_L_A()
	1259	{
	1260	L \|= A;
	1261	SET_Z(L);
	1262	}
	1263
	1264	/* 60 20: 0110 0000 0010 0000 */
	1265	void upd7810_device::ADDNC_V_A()
	1266	{
	1267	UINT8 tmp = V + A;
	1268	ZHC_ADD( tmp, V, 0 );
	1269	V = tmp;
	1270	SKIP_NC;
	1271	}
	1272
	1273	/* 60 21: 0110 0000 0010 0001 */
	1274	void upd7810_device::ADDNC_A_A()
	1275	{
	1276	UINT8 tmp = A + A;
	1277	ZHC_ADD( tmp, A, 0 );
	1278	A = tmp;
	1279	SKIP_NC;
	1280	}
	1281
	1282	/* 60 22: 0110 0000 0010 0010 */
	1283	void upd7810_device::ADDNC_B_A()
	1284	{
	1285	UINT8 tmp = B + A;
	1286	ZHC_ADD( tmp, B, 0 );
	1287	B = tmp;
	1288	SKIP_NC;
	1289	}
	1290
	1291	/* 60 23: 0110 0000 0010 0011 */
	1292	void upd7810_device::ADDNC_C_A()
	1293	{
	1294	UINT8 tmp = C + A;
	1295	ZHC_ADD( tmp, C, 0 );
	1296	C = tmp;
	1297	SKIP_NC;
	1298	}
	1299
	1300	/* 60 24: 0110 0000 0010 0100 */
	1301	void upd7810_device::ADDNC_D_A()
	1302	{
	1303	UINT8 tmp = D + A;
	1304	ZHC_ADD( tmp, D, 0 );
	1305	D = tmp;
	1306	SKIP_NC;
	1307	}
	1308
	1309	/* 60 25: 0110 0000 0010 0101 */
	1310	void upd7810_device::ADDNC_E_A()
	1311	{
	1312	UINT8 tmp = E + A;
	1313	ZHC_ADD( tmp, E, 0 );
	1314	E = tmp;
	1315	SKIP_NC;
	1316	}
	1317
	1318	/* 60 26: 0110 0000 0010 0110 */
	1319	void upd7810_device::ADDNC_H_A()
	1320	{
	1321	UINT8 tmp = H + A;
	1322	ZHC_ADD( tmp, H, 0 );
	1323	H = tmp;
	1324	SKIP_NC;
	1325	}
	1326
	1327	/* 60 27: 0110 0000 0010 0111 */
	1328	void upd7810_device::ADDNC_L_A()
	1329	{
	1330	UINT8 tmp = L + A;
	1331	ZHC_ADD( tmp, L, 0 );
	1332	L = tmp;
	1333	SKIP_NC;
	1334	}
	1335
	1336	/* 60 28: 0110 0000 0010 1000 */
	1337	void upd7810_device::GTA_V_A()
	1338	{
	1339	UINT16 tmp = V - A - 1;
	1340	ZHC_SUB( tmp, V, 0 );
	1341	SKIP_NC;
	1342	}
	1343
	1344	/* 60 29: 0110 0000 0010 1001 */
	1345	void upd7810_device::GTA_A_A()
	1346	{
	1347	UINT16 tmp = A - A - 1;
	1348	ZHC_SUB( tmp, A, 0 );
	1349	SKIP_NC;
	1350	}
	1351
	1352	/* 60 2a: 0110 0000 0010 1010 */
	1353	void upd7810_device::GTA_B_A()
	1354	{
	1355	UINT16 tmp = B - A - 1;
	1356	ZHC_SUB( tmp, B, 0 );
	1357	SKIP_NC;
	1358	}
	1359
	1360	/* 60 2b: 0110 0000 0010 1011 */
	1361	void upd7810_device::GTA_C_A()
	1362	{
	1363	UINT16 tmp = C - A - 1;
	1364	ZHC_SUB( tmp, C, 0 );
	1365	SKIP_NC;
	1366	}
	1367
	1368	/* 60 2c: 0110 0000 0010 1100 */
	1369	void upd7810_device::GTA_D_A()
	1370	{
	1371	UINT16 tmp = D - A - 1;
	1372	ZHC_SUB( tmp, D, 0 );
	1373	SKIP_NC;
	1374	}
	1375
	1376	/* 60 2d: 0110 0000 0010 1101 */
	1377	void upd7810_device::GTA_E_A()
	1378	{
	1379	UINT16 tmp = E - A - 1;
	1380	ZHC_SUB( tmp, E, 0 );
	1381	SKIP_NC;
	1382	}
	1383
	1384	/* 60 2e: 0110 0000 0010 1110 */
	1385	void upd7810_device::GTA_H_A()
	1386	{
	1387	UINT16 tmp = H - A - 1;
	1388	ZHC_SUB( tmp, H, 0 );
	1389	SKIP_NC;
	1390	}
	1391
	1392	/* 60 2f: 0110 0000 0010 1111 */
	1393	void upd7810_device::GTA_L_A()
	1394	{
	1395	UINT16 tmp = L - A - 1;
	1396	ZHC_SUB( tmp, L, 0 );
	1397	SKIP_NC;
	1398	}
	1399
	1400	/* 60 30: 0110 0000 0011 0000 */
	1401	void upd7810_device::SUBNB_V_A()
	1402	{
	1403	UINT8 tmp = V - A;
	1404	ZHC_SUB( tmp, V, 0 );
	1405	V = tmp;
	1406	SKIP_NC;
	1407	}
	1408
	1409	/* 60 31: 0110 0000 0011 0001 */
	1410	void upd7810_device::SUBNB_A_A()
	1411	{
	1412	UINT8 tmp = A - A;
	1413	ZHC_SUB( tmp, A, 0 );
	1414	A = tmp;
	1415	SKIP_NC;
	1416	}
	1417
	1418	/* 60 32: 0110 0000 0011 0010 */
	1419	void upd7810_device::SUBNB_B_A()
	1420	{
	1421	UINT8 tmp = B - A;
	1422	ZHC_SUB( tmp, B, 0 );
	1423	B = tmp;
	1424	SKIP_NC;
	1425	}
	1426
	1427	/* 60 33: 0110 0000 0011 0011 */
	1428	void upd7810_device::SUBNB_C_A()
	1429	{
	1430	UINT8 tmp = C - A;
	1431	ZHC_SUB( tmp, C, 0 );
	1432	C = tmp;
	1433	SKIP_NC;
	1434	}
	1435
	1436	/* 60 34: 0110 0000 0011 0100 */
	1437	void upd7810_device::SUBNB_D_A()
	1438	{
	1439	UINT8 tmp = D - A;
	1440	ZHC_SUB( tmp, D, 0 );
	1441	D = tmp;
	1442	SKIP_NC;
	1443	}
	1444
	1445	/* 60 35: 0110 0000 0011 0101 */
	1446	void upd7810_device::SUBNB_E_A()
	1447	{
	1448	UINT8 tmp = E - A;
	1449	ZHC_SUB( tmp, E, 0 );
	1450	E = tmp;
	1451	SKIP_NC;
	1452	}
	1453
	1454	/* 60 36: 0110 0000 0011 0110 */
	1455	void upd7810_device::SUBNB_H_A()
	1456	{
	1457	UINT8 tmp = H - A;
	1458	ZHC_SUB( tmp, H, 0 );
	1459	H = tmp;
	1460	SKIP_NC;
	1461	}
	1462
	1463	/* 60 37: 0110 0000 0011 0111 */
	1464	void upd7810_device::SUBNB_L_A()
	1465	{
	1466	UINT8 tmp = L - A;
	1467	ZHC_SUB( tmp, L, 0 );
	1468	L = tmp;
	1469	SKIP_NC;
	1470	}
	1471
	1472	/* 60 38: 0110 0000 0011 1000 */
	1473	void upd7810_device::LTA_V_A()
	1474	{
	1475	UINT8 tmp = V - A;
	1476	ZHC_SUB( tmp, V, 0 );
	1477	SKIP_CY;
	1478	}
	1479
	1480	/* 60 39: 0110 0000 0011 1001 */
	1481	void upd7810_device::LTA_A_A()
	1482	{
	1483	UINT8 tmp = A - A;
	1484	ZHC_SUB( tmp, A, 0 );
	1485	SKIP_CY;
	1486	}
	1487
	1488	/* 60 3a: 0110 0000 0011 1010 */
	1489	void upd7810_device::LTA_B_A()
	1490	{
	1491	UINT8 tmp = B - A;
	1492	ZHC_SUB( tmp, B, 0 );
	1493	SKIP_CY;
	1494	}
	1495
	1496	/* 60 3b: 0110 0000 0011 1011 */
	1497	void upd7810_device::LTA_C_A()
	1498	{
	1499	UINT8 tmp = C - A;
	1500	ZHC_SUB( tmp, C, 0 );
	1501	SKIP_CY;
	1502	}
	1503
	1504	/* 60 3c: 0110 0000 0011 1100 */
	1505	void upd7810_device::LTA_D_A()
	1506	{
	1507	UINT8 tmp = D - A;
	1508	ZHC_SUB( tmp, D, 0 );
	1509	SKIP_CY;
	1510	}
	1511
	1512	/* 60 3d: 0110 0000 0011 1101 */
	1513	void upd7810_device::LTA_E_A()
	1514	{
	1515	UINT8 tmp = E - A;
	1516	ZHC_SUB( tmp, E, 0 );
	1517	SKIP_CY;
	1518	}
	1519
	1520	/* 60 3e: 0110 0000 0011 1110 */
	1521	void upd7810_device::LTA_H_A()
	1522	{
	1523	UINT8 tmp = H - A;
	1524	ZHC_SUB( tmp, H, 0 );
	1525	SKIP_CY;
	1526	}
	1527
	1528	/* 60 3f: 0110 0000 0011 1111 */
	1529	void upd7810_device::LTA_L_A()
	1530	{
	1531	UINT8 tmp = L - A;
	1532	ZHC_SUB( tmp, L, 0 );
	1533	SKIP_CY;
	1534	}
	1535
	1536	/* 60 40: 0110 0000 0100 0000 */
	1537	void upd7810_device::ADD_V_A()
	1538	{
	1539	UINT8 tmp = V + A;
	1540	ZHC_ADD( tmp, V, 0 );
	1541	V = tmp;
	1542	}
	1543
	1544	/* 60 41: 0110 0000 0100 0001 */
	1545	void upd7810_device::ADD_A_A()
	1546	{
	1547	UINT8 tmp = A + A;
	1548	ZHC_ADD( tmp, A, 0 );
	1549	A = tmp;
	1550	}
	1551
	1552	/* 60 42: 0110 0000 0100 0010 */
	1553	void upd7810_device::ADD_B_A()
	1554	{
	1555	UINT8 tmp = B + A;
	1556	ZHC_ADD( tmp, B, 0 );
	1557	B = tmp;
	1558	}
	1559
	1560	/* 60 43: 0110 0000 0100 0011 */
	1561	void upd7810_device::ADD_C_A()
	1562	{
	1563	UINT8 tmp = C + A;
	1564	ZHC_ADD( tmp, C, 0 );
	1565	C = tmp;
	1566	}
	1567
	1568	/* 60 44: 0110 0000 0100 0100 */
	1569	void upd7810_device::ADD_D_A()
	1570	{
	1571	UINT8 tmp = D + A;
	1572	ZHC_ADD( tmp, D, 0 );
	1573	D = tmp;
	1574	}
	1575
	1576	/* 60 45: 0110 0000 0100 0101 */
	1577	void upd7810_device::ADD_E_A()
	1578	{
	1579	UINT8 tmp = E + A;
	1580	ZHC_ADD( tmp, E, 0 );
	1581	E = tmp;
	1582	}
	1583
	1584	/* 60 46: 0110 0000 0100 0110 */
	1585	void upd7810_device::ADD_H_A()
	1586	{
	1587	UINT8 tmp = H + A;
	1588	ZHC_ADD( tmp, H, 0 );
	1589	H = tmp;
	1590	}
	1591
	1592	/* 60 47: 0110 0000 0100 0111 */
	1593	void upd7810_device::ADD_L_A()
	1594	{
	1595	UINT8 tmp = L + A;
	1596	ZHC_ADD( tmp, L, 0 );
	1597	L = tmp;
	1598	}
	1599
	1600	/* 60 50: 0110 0000 0101 0000 */
	1601	void upd7810_device::ADC_V_A()
	1602	{
	1603	UINT8 tmp = V + A + (PSW & CY);
	1604	ZHC_ADD( tmp, V, (PSW & CY) );
	1605	V = tmp;
	1606	}
	1607
	1608	/* 60 51: 0110 0000 0101 0001 */
	1609	void upd7810_device::ADC_A_A()
	1610	{
	1611	UINT8 tmp = A + A + (PSW & CY);
	1612	ZHC_ADD( tmp, A, (PSW & CY) );
	1613	A = tmp;
	1614	}
	1615
	1616	/* 60 52: 0110 0000 0101 0010 */
	1617	void upd7810_device::ADC_B_A()
	1618	{
	1619	UINT8 tmp = B + A + (PSW & CY);
	1620	ZHC_ADD( tmp, B, (PSW & CY) );
	1621	B = tmp;
	1622	}
	1623
	1624	/* 60 53: 0110 0000 0101 0011 */
	1625	void upd7810_device::ADC_C_A()
	1626	{
	1627	UINT8 tmp = C + A + (PSW & CY);
	1628	ZHC_ADD( tmp, C, (PSW & CY) );
	1629	C = tmp;
	1630	}
	1631
	1632	/* 60 54: 0110 0000 0101 0100 */
	1633	void upd7810_device::ADC_D_A()
	1634	{
	1635	UINT8 tmp = D + A + (PSW & CY);
	1636	ZHC_ADD( tmp, D, (PSW & CY) );
	1637	D = tmp;
	1638	}
	1639
	1640	/* 60 55: 0110 0000 0101 0101 */
	1641	void upd7810_device::ADC_E_A()
	1642	{
	1643	UINT8 tmp = E + A + (PSW & CY);
	1644	ZHC_ADD( tmp, E, (PSW & CY) );
	1645	E = tmp;
	1646	}
	1647
	1648	/* 60 56: 0110 0000 0101 0110 */
	1649	void upd7810_device::ADC_H_A()
	1650	{
	1651	UINT8 tmp = H + A + (PSW & CY);
	1652	ZHC_ADD( tmp, H, (PSW & CY) );
	1653	H = tmp;
	1654	}
	1655
	1656	/* 60 57: 0110 0000 0101 0111 */
	1657	void upd7810_device::ADC_L_A()
	1658	{
	1659	UINT8 tmp = L + A + (PSW & CY);
	1660	ZHC_ADD( tmp, L, (PSW & CY) );
	1661	L = tmp;
	1662	}
	1663
	1664	/* 60 60: 0110 0000 0110 0000 */
	1665	void upd7810_device::SUB_V_A()
	1666	{
	1667	UINT8 tmp = V - A;
	1668	ZHC_SUB( tmp, V, 0 );
	1669	V = tmp;
	1670	}
	1671
	1672	/* 60 61: 0110 0000 0110 0001 */
	1673	void upd7810_device::SUB_A_A()
	1674	{
	1675	UINT8 tmp = A - A;
	1676	ZHC_SUB( tmp, A, 0 );
	1677	A = tmp;
	1678	}
	1679
	1680	/* 60 62: 0110 0000 0110 0010 */
	1681	void upd7810_device::SUB_B_A()
	1682	{
	1683	UINT8 tmp = B - A;
	1684	ZHC_SUB( tmp, B, 0 );
	1685	B = tmp;
	1686	}
	1687
	1688	/* 60 63: 0110 0000 0110 0011 */
	1689	void upd7810_device::SUB_C_A()
	1690	{
	1691	UINT8 tmp = C - A;
	1692	ZHC_SUB( tmp, C, 0 );
	1693	C = tmp;
	1694	}
	1695
	1696	/* 60 64: 0110 0000 0110 0100 */
	1697	void upd7810_device::SUB_D_A()
	1698	{
	1699	UINT8 tmp = D - A;
	1700	ZHC_SUB( tmp, D, 0 );
	1701	D = tmp;
	1702	}
	1703
	1704	/* 60 65: 0110 0000 0110 0101 */
	1705	void upd7810_device::SUB_E_A()
	1706	{
	1707	UINT8 tmp = E - A;
	1708	ZHC_SUB( tmp, E, 0 );
	1709	E = tmp;
	1710	}
	1711
	1712	/* 60 66: 0110 0000 0110 0110 */
	1713	void upd7810_device::SUB_H_A()
	1714	{
	1715	UINT8 tmp = H - A;
	1716	ZHC_SUB( tmp, H, 0 );
	1717	H = tmp;
	1718	}
	1719
	1720	/* 60 67: 0110 0000 0110 0111 */
	1721	void upd7810_device::SUB_L_A()
	1722	{
	1723	UINT8 tmp = L - A;
	1724	ZHC_SUB( tmp, L, 0 );
	1725	L = tmp;
	1726	}
	1727
	1728	/* 60 68: 0110 0000 0110 1000 */
	1729	void upd7810_device::NEA_V_A()
	1730	{
	1731	UINT8 tmp = V - A;
	1732	ZHC_SUB( tmp, V, 0 );
	1733	SKIP_NZ;
	1734	}
	1735
	1736	/* 60 69: 0110 0000 0110 1001 */
	1737	void upd7810_device::NEA_A_A()
	1738	{
	1739	UINT8 tmp = A - A;
	1740	ZHC_SUB( tmp, A, 0 );
	1741	SKIP_NZ;
	1742	}
	1743
	1744	/* 60 6a: 0110 0000 0110 1010 */
	1745	void upd7810_device::NEA_B_A()
	1746	{
	1747	UINT8 tmp = B - A;
	1748	ZHC_SUB( tmp, B, 0 );
	1749	SKIP_NZ;
	1750	}
	1751
	1752	/* 60 6b: 0110 0000 0110 1011 */
	1753	void upd7810_device::NEA_C_A()
	1754	{
	1755	UINT8 tmp = C - A;
	1756	ZHC_SUB( tmp, C, 0 );
	1757	SKIP_NZ;
	1758	}
	1759
	1760	/* 60 6c: 0110 0000 0110 1100 */
	1761	void upd7810_device::NEA_D_A()
	1762	{
	1763	UINT8 tmp = D - A;
	1764	ZHC_SUB( tmp, D, 0 );
	1765	SKIP_NZ;
	1766	}
	1767
	1768	/* 60 6d: 0110 0000 0110 1101 */
	1769	void upd7810_device::NEA_E_A()
	1770	{
	1771	UINT8 tmp = E - A;
	1772	ZHC_SUB( tmp, E, 0 );
	1773	SKIP_NZ;
	1774	}
	1775
	1776	/* 60 6e: 0110 0000 0110 1110 */
	1777	void upd7810_device::NEA_H_A()
	1778	{
	1779	UINT8 tmp = H - A;
	1780	ZHC_SUB( tmp, H, 0 );
	1781	SKIP_NZ;
	1782	}
	1783
	1784	/* 60 6f: 0110 0000 0110 1111 */
	1785	void upd7810_device::NEA_L_A()
	1786	{
	1787	UINT8 tmp = L - A;
	1788	ZHC_SUB( tmp, L, 0 );
	1789	SKIP_NZ;
	1790	}
	1791
	1792	/* 60 70: 0110 0000 0111 0000 */
	1793	void upd7810_device::SBB_V_A()
	1794	{
	1795	UINT8 tmp = V - A - (PSW & CY);
	1796	ZHC_SUB( tmp, V, (PSW & CY) );
	1797	V = tmp;
	1798	}
	1799
	1800	/* 60 71: 0110 0000 0111 0001 */
	1801	void upd7810_device::SBB_A_A()
	1802	{
	1803	UINT8 tmp = A - A - (PSW & CY);
	1804	ZHC_SUB( tmp, A, (PSW & CY) );
	1805	A = tmp;
	1806	}
	1807
	1808	/* 60 72: 0110 0000 0111 0010 */
	1809	void upd7810_device::SBB_B_A()
	1810	{
	1811	UINT8 tmp = B - A - (PSW & CY);
	1812	ZHC_SUB( tmp, B, (PSW & CY) );
	1813	B = tmp;
	1814	}
	1815
	1816	/* 60 73: 0110 0000 0111 0011 */
	1817	void upd7810_device::SBB_C_A()
	1818	{
	1819	UINT8 tmp = C - A - (PSW & CY);
	1820	ZHC_SUB( tmp, C, (PSW & CY) );
	1821	C = tmp;
	1822	}
	1823
	1824	/* 60 74: 0110 0000 0111 0100 */
	1825	void upd7810_device::SBB_D_A()
	1826	{
	1827	UINT8 tmp = D - A - (PSW & CY);
	1828	ZHC_SUB( tmp, D, (PSW & CY) );
	1829	D = tmp;
	1830	}
	1831
	1832	/* 60 75: 0110 0000 0111 0101 */
	1833	void upd7810_device::SBB_E_A()
	1834	{
	1835	UINT8 tmp = E - A - (PSW & CY);
	1836	ZHC_SUB( tmp, E, (PSW & CY) );
	1837	E = tmp;
	1838	}
	1839
	1840	/* 60 76: 0110 0000 0111 0110 */
	1841	void upd7810_device::SBB_H_A()
	1842	{
	1843	UINT8 tmp = H - A - (PSW & CY);
	1844	ZHC_SUB( tmp, H, (PSW & CY) );
	1845	H = tmp;
	1846	}
	1847
	1848	/* 60 77: 0110 0000 0111 0111 */
	1849	void upd7810_device::SBB_L_A()
	1850	{
	1851	UINT8 tmp = L - A - (PSW & CY);
	1852	ZHC_SUB( tmp, L, (PSW & CY) );
	1853	L = tmp;
	1854	}
	1855
	1856	/* 60 78: 0110 0000 0111 1000 */
	1857	void upd7810_device::EQA_V_A()
	1858	{
	1859	UINT8 tmp = V - A;
	1860	ZHC_SUB( tmp, V, 0 );
	1861	SKIP_Z;
	1862	}
	1863
	1864	/* 60 79: 0110 0000 0111 1001 */
	1865	void upd7810_device::EQA_A_A()
	1866	{
	1867	UINT8 tmp = A - A;
	1868	ZHC_SUB( tmp, A, 0 );
	1869	SKIP_Z;
	1870	}
	1871
	1872	/* 60 7a: 0110 0000 0111 1010 */
	1873	void upd7810_device::EQA_B_A()
	1874	{
	1875	UINT8 tmp = B - A;
	1876	ZHC_SUB( tmp, B, 0 );
	1877	SKIP_Z;
	1878	}
	1879
	1880	/* 60 7b: 0110 0000 0111 1011 */
	1881	void upd7810_device::EQA_C_A()
	1882	{
	1883	UINT8 tmp = C - A;
	1884	ZHC_SUB( tmp, C, 0 );
	1885	SKIP_Z;
	1886	}
	1887
	1888	/* 60 7c: 0110 0000 0111 1100 */
	1889	void upd7810_device::EQA_D_A()
	1890	{
	1891	UINT8 tmp = D - A;
	1892	ZHC_SUB( tmp, D, 0 );
	1893	SKIP_Z;
	1894	}
	1895
	1896	/* 60 7d: 0110 0000 0111 1101 */
	1897	void upd7810_device::EQA_E_A()
	1898	{
	1899	UINT8 tmp = E - A;
	1900	ZHC_SUB( tmp, E, 0 );
	1901	SKIP_Z;
	1902	}
	1903
	1904	/* 60 7e: 0110 0000 0111 1110 */
	1905	void upd7810_device::EQA_H_A()
	1906	{
	1907	UINT8 tmp = H - A;
	1908	ZHC_SUB( tmp, H, 0 );
	1909	SKIP_Z;
	1910	}
	1911
	1912	/* 60 7f: 0110 0000 0111 1111 */
	1913	void upd7810_device::EQA_L_A()
	1914	{
	1915	UINT8 tmp = L - A;
	1916	ZHC_SUB( tmp, L, 0 );
	1917	SKIP_Z;
	1918	}
	1919
	1920	/* 60 88: 0110 0000 1000 1000 */
	1921	void upd7810_device::ANA_A_V()
	1922	{
	1923	A &= V;
	1924	SET_Z(A);
	1925	}
	1926
	1927	/* 60 89: 0110 0000 1000 1001 */
	1928	/* ANA_A_A already defined */
	1929
	1930	/* 60 8a: 0110 0000 1000 1010 */
	1931	void upd7810_device::ANA_A_B()
	1932	{
	1933	A &= B;
	1934	SET_Z(A);
	1935	}
	1936
	1937	/* 60 8b: 0110 0000 1000 1011 */
	1938	void upd7810_device::ANA_A_C()
	1939	{
	1940	A &= C;
	1941	SET_Z(A);
	1942	}
	1943
	1944	/* 60 8c: 0110 0000 1000 1100 */
	1945	void upd7810_device::ANA_A_D()
	1946	{
	1947	A &= D;
	1948	SET_Z(A);
	1949	}
	1950
	1951	/* 60 8d: 0110 0000 1000 1101 */
	1952	void upd7810_device::ANA_A_E()
	1953	{
	1954	A &= E;
	1955	SET_Z(A);
	1956	}
	1957
	1958	/* 60 8e: 0110 0000 1000 1110 */
	1959	void upd7810_device::ANA_A_H()
	1960	{
	1961	A &= H;
	1962	SET_Z(A);
	1963	}
	1964
	1965	/* 60 8f: 0110 0000 1000 1111 */
	1966	void upd7810_device::ANA_A_L()
	1967	{
	1968	A &= L;
	1969	SET_Z(A);
	1970	}
	1971
	1972	/* 60 90: 0110 0000 1001 0000 */
	1973	void upd7810_device::XRA_A_V()
	1974	{
	1975	A ^= V;
	1976	SET_Z(A);
	1977	}
	1978
	1979	/* 60 91: 0110 0000 1001 0001 */
	1980	/* XRA_A_A already defined */
	1981
	1982	/* 60 92: 0110 0000 1001 0010 */
	1983	void upd7810_device::XRA_A_B()
	1984	{
	1985	A ^= B;
	1986	SET_Z(A);
	1987	}
	1988
	1989	/* 60 93: 0110 0000 1001 0011 */
	1990	void upd7810_device::XRA_A_C()
	1991	{
	1992	A ^= C;
	1993	SET_Z(A);
	1994	}
	1995
	1996	/* 60 94: 0110 0000 1001 0100 */
	1997	void upd7810_device::XRA_A_D()
	1998	{
	1999	A ^= D;
	2000	SET_Z(A);
	2001	}
	2002
	2003	/* 60 95: 0110 0000 1001 0101 */
	2004	void upd7810_device::XRA_A_E()
	2005	{
	2006	A ^= E;
	2007	SET_Z(A);
	2008	}
	2009
	2010	/* 60 96: 0110 0000 1001 0110 */
	2011	void upd7810_device::XRA_A_H()
	2012	{
	2013	A ^= H;
	2014	SET_Z(A);
	2015	}
	2016
	2017	/* 60 97: 0110 0000 1001 0111 */
	2018	void upd7810_device::XRA_A_L()
	2019	{
	2020	A ^= L;
	2021	SET_Z(A);
	2022	}
	2023
	2024	/* 60 98: 0110 0000 1001 1000 */
	2025	void upd7810_device::ORA_A_V()
	2026	{
	2027	A \|= V;
	2028	SET_Z(A);
	2029	}
	2030
	2031	/* 60 99: 0110 0000 1001 1001 */
	2032	/* ORA_A_A already defined */
	2033
	2034	/* 60 9a: 0110 0000 1001 1010 */
	2035	void upd7810_device::ORA_A_B()
	2036	{
	2037	A \|= B;
	2038	SET_Z(A);
	2039	}
	2040
	2041	/* 60 9b: 0110 0000 1001 1011 */
	2042	void upd7810_device::ORA_A_C()
	2043	{
	2044	A \|= C;
	2045	SET_Z(A);
	2046	}
	2047
	2048	/* 60 9c: 0110 0000 1001 1100 */
	2049	void upd7810_device::ORA_A_D()
	2050	{
	2051	A \|= D;
	2052	SET_Z(A);
	2053	}
	2054
	2055	/* 60 9d: 0110 0000 1001 1101 */
	2056	void upd7810_device::ORA_A_E()
	2057	{
	2058	A \|= E;
	2059	SET_Z(A);
	2060	}
	2061
	2062	/* 60 9e: 0110 0000 1001 1110 */
	2063	void upd7810_device::ORA_A_H()
	2064	{
	2065	A \|= H;
	2066	SET_Z(A);
	2067	}
	2068
	2069	/* 60 9f: 0110 0000 1001 1111 */
	2070	void upd7810_device::ORA_A_L()
	2071	{
	2072	A \|= L;
	2073	SET_Z(A);
	2074	}
	2075
	2076	/* 60 a0: 0110 0000 1010 0000 */
	2077	void upd7810_device::ADDNC_A_V()
	2078	{
	2079	UINT8 tmp = A + V;
	2080	ZHC_ADD( tmp, A, 0 );
	2081	A = tmp;
	2082	SKIP_NC;
	2083	}
	2084
	2085	/* 60 a1: 0110 0000 1010 0001 */
	2086	/* ADDNC_A_A already defined */
	2087
	2088	/* 60 a2: 0110 0000 1010 0010 */
	2089	void upd7810_device::ADDNC_A_B()
	2090	{
	2091	UINT8 tmp = A + B;
	2092	ZHC_ADD( tmp, A, 0 );
	2093	A = tmp;
	2094	SKIP_NC;
	2095	}
	2096
	2097	/* 60 a3: 0110 0000 1010 0011 */
	2098	void upd7810_device::ADDNC_A_C()
	2099	{
	2100	UINT8 tmp = A + C;
	2101	ZHC_ADD( tmp, A, 0 );
	2102	A = tmp;
	2103	SKIP_NC;
	2104	}
	2105
	2106	/* 60 a4: 0110 0000 1010 0100 */
	2107	void upd7810_device::ADDNC_A_D()
	2108	{
	2109	UINT8 tmp = A + D;
	2110	ZHC_ADD( tmp, A, 0 );
	2111	A = tmp;
	2112	SKIP_NC;
	2113	}
	2114
	2115	/* 60 a5: 0110 0000 1010 0101 */
	2116	void upd7810_device::ADDNC_A_E()
	2117	{
	2118	UINT8 tmp = A + E;
	2119	ZHC_ADD( tmp, A, 0 );
	2120	A = tmp;
	2121	SKIP_NC;
	2122	}
	2123
	2124	/* 60 a6: 0110 0000 1010 0110 */
	2125	void upd7810_device::ADDNC_A_H()
	2126	{
	2127	UINT8 tmp = A + H;
	2128	ZHC_ADD( tmp, A, 0 );
	2129	A = tmp;
	2130	SKIP_NC;
	2131	}
	2132
	2133	/* 60 a7: 0110 0000 1010 0111 */
	2134	void upd7810_device::ADDNC_A_L()
	2135	{
	2136	UINT8 tmp = A + L;
	2137	ZHC_ADD( tmp, A, 0 );
	2138	A = tmp;
	2139	SKIP_NC;
	2140	}
	2141
	2142	/* 60 a8: 0110 0000 1010 1000 */
	2143	void upd7810_device::GTA_A_V()
	2144	{
	2145	UINT16 tmp = A - V - 1;
	2146	ZHC_SUB( tmp, A, 0 );
	2147	SKIP_NC;
	2148	}
	2149
	2150	/* 60 a9: 0110 0000 1010 1001 */
	2151	/* GTA_A_A already defined */
	2152
	2153	/* 60 aa: 0110 0000 1010 1010 */
	2154	void upd7810_device::GTA_A_B()
	2155	{
	2156	UINT16 tmp = A - B - 1;
	2157	ZHC_SUB( tmp, A, 0 );
	2158	SKIP_NC;
	2159	}
	2160
	2161	/* 60 ab: 0110 0000 1010 1011 */
	2162	void upd7810_device::GTA_A_C()
	2163	{
	2164	UINT16 tmp = A - C - 1;
	2165	ZHC_SUB( tmp, A, 0 );
	2166	SKIP_NC;
	2167	}
	2168
	2169	/* 60 ac: 0110 0000 1010 1100 */
	2170	void upd7810_device::GTA_A_D()
	2171	{
	2172	UINT16 tmp = A - D - 1;
	2173	ZHC_SUB( tmp, A, 0 );
	2174	SKIP_NC;
	2175	}
	2176
	2177	/* 60 ad: 0110 0000 1010 1101 */
	2178	void upd7810_device::GTA_A_E()
	2179	{
	2180	UINT16 tmp = A - E - 1;
	2181	ZHC_SUB( tmp, A, 0 );
	2182	SKIP_NC;
	2183	}
	2184
	2185	/* 60 ae: 0110 0000 1010 1110 */
	2186	void upd7810_device::GTA_A_H()
	2187	{
	2188	UINT16 tmp = A - H - 1;
	2189	ZHC_SUB( tmp, A, 0 );
	2190	SKIP_NC;
	2191	}
	2192
	2193	/* 60 af: 0110 0000 1010 1111 */
	2194	void upd7810_device::GTA_A_L()
	2195	{
	2196	UINT16 tmp = A - L - 1;
	2197	ZHC_SUB( tmp, A, 0 );
	2198	SKIP_NC;
	2199	}
	2200
	2201	/* 60 b0: 0110 0000 1011 0000 */
	2202	void upd7810_device::SUBNB_A_V()
	2203	{
	2204	UINT8 tmp = A - V;
	2205	ZHC_SUB( tmp, A, 0 );
	2206	A = tmp;
	2207	SKIP_NC;
	2208	}
	2209
	2210	/* 60 b1: 0110 0000 1011 0001 */
	2211	/* SUBNB_A_A already defined */
	2212
	2213	/* 60 b2: 0110 0000 1011 0010 */
	2214	void upd7810_device::SUBNB_A_B()
	2215	{
	2216	UINT8 tmp = A - B;
	2217	ZHC_SUB( tmp, A, 0 );
	2218	A = tmp;
	2219	SKIP_NC;
	2220	}
	2221
	2222	/* 60 b3: 0110 0000 1011 0011 */
	2223	void upd7810_device::SUBNB_A_C()
	2224	{
	2225	UINT8 tmp = A - C;
	2226	ZHC_SUB( tmp, A, 0 );
	2227	A = tmp;
	2228	SKIP_NC;
	2229	}
	2230
	2231	/* 60 b4: 0110 0000 1011 0100 */
	2232	void upd7810_device::SUBNB_A_D()
	2233	{
	2234	UINT8 tmp = A - D;
	2235	ZHC_SUB( tmp, A, 0 );
	2236	A = tmp;
	2237	SKIP_NC;
	2238	}
	2239
	2240	/* 60 b5: 0110 0000 1011 0101 */
	2241	void upd7810_device::SUBNB_A_E()
	2242	{
	2243	UINT8 tmp = A - E;
	2244	ZHC_SUB( tmp, A, 0 );
	2245	A = tmp;
	2246	SKIP_NC;
	2247	}
	2248
	2249	/* 60 b6: 0110 0000 1011 0110 */
	2250	void upd7810_device::SUBNB_A_H()
	2251	{
	2252	UINT8 tmp = A - H;
	2253	ZHC_SUB( tmp, A, 0 );
	2254	A = tmp;
	2255	SKIP_NC;
	2256	}
	2257
	2258	/* 60 b7: 0110 0000 1011 0111 */
	2259	void upd7810_device::SUBNB_A_L()
	2260	{
	2261	UINT8 tmp = A - L;
	2262	ZHC_SUB( tmp, A, 0 );
	2263	A = tmp;
	2264	SKIP_NC;
	2265	}
	2266
	2267	/* 60 b8: 0110 0000 1011 1000 */
	2268	void upd7810_device::LTA_A_V()
	2269	{
	2270	UINT8 tmp = A - V;
	2271	ZHC_SUB( tmp, A, 0 );
	2272	SKIP_CY;
	2273	}
	2274
	2275	/* 60 b9: 0110 0000 1011 1001 */
	2276	/* LTA_A_A already defined */
	2277
	2278	/* 60 ba: 0110 0000 1011 1010 */
	2279	void upd7810_device::LTA_A_B()
	2280	{
	2281	UINT8 tmp = A - B;
	2282	ZHC_SUB( tmp, A, 0 );
	2283	SKIP_CY;
	2284	}
	2285
	2286	/* 60 bb: 0110 0000 1011 1011 */
	2287	void upd7810_device::LTA_A_C()
	2288	{
	2289	UINT8 tmp = A - C;
	2290	ZHC_SUB( tmp, A, 0 );
	2291	SKIP_CY;
	2292	}
	2293
	2294	/* 60 bc: 0110 0000 1011 1100 */
	2295	void upd7810_device::LTA_A_D()
	2296	{
	2297	UINT8 tmp = A - D;
	2298	ZHC_SUB( tmp, A, 0 );
	2299	SKIP_CY;
	2300	}
	2301
	2302	/* 60 bd: 0110 0000 1011 1101 */
	2303	void upd7810_device::LTA_A_E()
	2304	{
	2305	UINT8 tmp = A - E;
	2306	ZHC_SUB( tmp, A, 0 );
	2307	SKIP_CY;
	2308	}
	2309
	2310	/* 60 be: 0110 0000 1011 1110 */
	2311	void upd7810_device::LTA_A_H()
	2312	{
	2313	UINT8 tmp = A - H;
	2314	ZHC_SUB( tmp, A, 0 );
	2315	SKIP_CY;
	2316	}
	2317
	2318	/* 60 bf: 0110 0000 1011 1111 */
	2319	void upd7810_device::LTA_A_L()
	2320	{
	2321	UINT8 tmp = A - L;
	2322	ZHC_SUB( tmp, A, 0 );
	2323	SKIP_CY;
	2324	}
	2325
	2326	/* 60 c0: 0110 0000 1100 0000 */
	2327	void upd7810_device::ADD_A_V()
	2328	{
	2329	UINT8 tmp = A + V;
	2330	ZHC_ADD( tmp, A, 0 );
	2331	A = tmp;
	2332	}
	2333
	2334	/* 60 c1: 0110 0000 1100 0001 */
	2335	/* ADD_A_A already defined */
	2336
	2337	/* 60 c2: 0110 0000 1100 0010 */
	2338	void upd7810_device::ADD_A_B()
	2339	{
	2340	UINT8 tmp = A + B;
	2341	ZHC_ADD( tmp, A, 0 );
	2342	A = tmp;
	2343	}
	2344
	2345	/* 60 c3: 0110 0000 1100 0011 */
	2346	void upd7810_device::ADD_A_C()
	2347	{
	2348	UINT8 tmp = A + C;
	2349	ZHC_ADD( tmp, A, 0 );
	2350	A = tmp;
	2351	}
	2352
	2353	/* 60 c4: 0110 0000 1100 0100 */
	2354	void upd7810_device::ADD_A_D()
	2355	{
	2356	UINT8 tmp = A + D;
	2357	ZHC_ADD( tmp, A, 0 );
	2358	A = tmp;
	2359	}
	2360
	2361	/* 60 c5: 0110 0000 1100 0101 */
	2362	void upd7810_device::ADD_A_E()
	2363	{
	2364	UINT8 tmp = A + E;
	2365	ZHC_ADD( tmp, A, 0 );
	2366	A = tmp;
	2367	}
	2368
	2369	/* 60 c6: 0110 0000 1100 0110 */
	2370	void upd7810_device::ADD_A_H()
	2371	{
	2372	UINT8 tmp = A + H;
	2373	ZHC_ADD( tmp, A, 0 );
	2374	A = tmp;
	2375	}
	2376
	2377	/* 60 c7: 0110 0000 1100 0111 */
	2378	void upd7810_device::ADD_A_L()
	2379	{
	2380	UINT8 tmp = A + L;
	2381	ZHC_ADD( tmp, A, 0 );
	2382	A = tmp;
	2383	}
	2384
	2385	/* 60 c8: 0110 0000 1100 1000 */
	2386	void upd7810_device::ONA_A_V()
	2387	{
	2388	if (A & V)
	2389	PSW = (PSW & ~Z) \| SK;
	2390	else
	2391	PSW \|= Z;
	2392	}
	2393
	2394	/* 60 c9: 0110 0000 1100 1001 */
	2395	void upd7810_device::ONA_A_A()
	2396	{
	2397	if (A & A)
	2398	PSW = (PSW & ~Z) \| SK;
	2399	else
	2400	PSW \|= Z;
	2401	}
	2402
	2403	/* 60 ca: 0110 0000 1100 1010 */
	2404	void upd7810_device::ONA_A_B()
	2405	{
	2406	if (A & B)
	2407	PSW = (PSW & ~Z) \| SK;
	2408	else
	2409	PSW \|= Z;
	2410	}
	2411
	2412	/* 60 cb: 0110 0000 1100 1011 */
	2413	void upd7810_device::ONA_A_C()
	2414	{
	2415	if (A & C)
	2416	PSW = (PSW & ~Z) \| SK;
	2417	else
	2418	PSW \|= Z;
	2419	}
	2420
	2421	/* 60 cc: 0110 0000 1100 1100 */
	2422	void upd7810_device::ONA_A_D()
	2423	{
	2424	if (A & D)
	2425	PSW = (PSW & ~Z) \| SK;
	2426	else
	2427	PSW \|= Z;
	2428	}
	2429
	2430	/* 60 cd: 0110 0000 1100 1101 */
	2431	void upd7810_device::ONA_A_E()
	2432	{
	2433	if (A & E)
	2434	PSW = (PSW & ~Z) \| SK;
	2435	else
	2436	PSW \|= Z;
	2437	}
	2438
	2439	/* 60 ce: 0110 0000 1100 1110 */
	2440	void upd7810_device::ONA_A_H()
	2441	{
	2442	if (A & H)
	2443	PSW = (PSW & ~Z) \| SK;
	2444	else
	2445	PSW \|= Z;
	2446	}
	2447
	2448	/* 60 cf: 0110 0000 1100 1111 */
	2449	void upd7810_device::ONA_A_L()
	2450	{
	2451	if (A & L)
	2452	PSW = (PSW & ~Z) \| SK;
	2453	else
	2454	PSW \|= Z;
	2455	}
	2456
	2457	/* 60 d0: 0110 0000 1101 0000 */
	2458	void upd7810_device::ADC_A_V()
	2459	{
	2460	UINT8 tmp = A + V + (PSW & CY);
	2461	ZHC_ADD( tmp, A, (PSW & CY) );
	2462	A = tmp;
	2463	}
	2464
	2465	/* 60 d1: 0110 0000 1101 0001 */
	2466	/* ADC_A_A already defined */
	2467
	2468	/* 60 d2: 0110 0000 1101 0010 */
	2469	void upd7810_device::ADC_A_B()
	2470	{
	2471	UINT8 tmp = A + B + (PSW & CY);
	2472	ZHC_ADD( tmp, A, (PSW & CY) );
	2473	A = tmp;
	2474	}
	2475
	2476	/* 60 d3: 0110 0000 1101 0011 */
	2477	void upd7810_device::ADC_A_C()
	2478	{
	2479	UINT8 tmp = A + C + (PSW & CY);
	2480	ZHC_ADD( tmp, A, (PSW & CY) );
	2481	A = tmp;
	2482	}
	2483
	2484	/* 60 d4: 0110 0000 1101 0100 */
	2485	void upd7810_device::ADC_A_D()
	2486	{
	2487	UINT8 tmp = A + D + (PSW & CY);
	2488	ZHC_ADD( tmp, A, (PSW & CY) );
	2489	A = tmp;
	2490	}
	2491
	2492	/* 60 d5: 0110 0000 1101 0101 */
	2493	void upd7810_device::ADC_A_E()
	2494	{
	2495	UINT8 tmp = A + E + (PSW & CY);
	2496	ZHC_ADD( tmp, A, (PSW & CY) );
	2497	A = tmp;
	2498	}
	2499
	2500	/* 60 d6: 0110 0000 1101 0110 */
	2501	void upd7810_device::ADC_A_H()
	2502	{
	2503	UINT8 tmp = A + H + (PSW & CY);
	2504	ZHC_ADD( tmp, A, (PSW & CY) );
	2505	A = tmp;
	2506	}
	2507
	2508	/* 60 d7: 0110 0000 1101 0111 */
	2509	void upd7810_device::ADC_A_L()
	2510	{
	2511	UINT8 tmp = A + L + (PSW & CY);
	2512	ZHC_ADD( tmp, A, (PSW & CY) );
	2513	A = tmp;
	2514	}
	2515
	2516	/* 60 d8: 0110 0000 1101 1000 */
	2517	void upd7810_device::OFFA_A_V()
	2518	{
	2519	if ( A & V )
	2520	PSW &= ~Z;
	2521	else
	2522	PSW = PSW \| Z \| SK;
	2523	}
	2524
	2525	/* 60 d9: 0110 0000 1101 1001 */
	2526	void upd7810_device::OFFA_A_A()
	2527	{
	2528	if ( A & A )
	2529	PSW &= ~Z;
	2530	else
	2531	PSW = PSW \| Z \| SK;
	2532	}
	2533
	2534	/* 60 da: 0110 0000 1101 1010 */
	2535	void upd7810_device::OFFA_A_B()
	2536	{
	2537	if ( A & B )
	2538	PSW &= ~Z;
	2539	else
	2540	PSW = PSW \| Z \| SK;
	2541	}
	2542
	2543	/* 60 db: 0110 0000 1101 1011 */
	2544	void upd7810_device::OFFA_A_C()
	2545	{
	2546	if ( A & C )
	2547	PSW &= ~Z;
	2548	else
	2549	PSW = PSW \| Z \| SK;
	2550	}
	2551
	2552	/* 60 dc: 0110 0000 1101 1100 */
	2553	void upd7810_device::OFFA_A_D()
	2554	{
	2555	if ( A & D )
	2556	PSW &= ~Z;
	2557	else
	2558	PSW = PSW \| Z \| SK;
	2559	}
	2560
	2561	/* 60 dd: 0110 0000 1101 1101 */
	2562	void upd7810_device::OFFA_A_E()
	2563	{
	2564	if ( A & E )
	2565	PSW &= ~Z;
	2566	else
	2567	PSW = PSW \| Z \| SK;
	2568	}
	2569
	2570	/* 60 de: 0110 0000 1101 1110 */
	2571	void upd7810_device::OFFA_A_H()
	2572	{
	2573	if ( A & H )
	2574	PSW &= ~Z;
	2575	else
	2576	PSW = PSW \| Z \| SK;
	2577	}
	2578
	2579	/* 60 df: 0110 0000 1101 1111 */
	2580	void upd7810_device::OFFA_A_L()
	2581	{
	2582	if ( A & L )
	2583	PSW &= ~Z;
	2584	else
	2585	PSW = PSW \| Z \| SK;
	2586	}
	2587
	2588	/* 60 e0: 0110 0000 1110 0000 */
	2589	void upd7810_device::SUB_A_V()
	2590	{
	2591	UINT8 tmp = A - V;
	2592	ZHC_SUB( tmp, A, 0 );
	2593	A = tmp;
	2594	}
	2595
	2596	/* 60 e1: 0110 0000 1110 0001 */
	2597	/* SUB_A_A already defined */
	2598
	2599	/* 60 e2: 0110 0000 1110 0010 */
	2600	void upd7810_device::SUB_A_B()
	2601	{
	2602	UINT8 tmp = A - B;
	2603	ZHC_SUB( tmp, A, 0 );
	2604	A = tmp;
	2605	}
	2606
	2607	/* 60 e3: 0110 0000 1110 0011 */
	2608	void upd7810_device::SUB_A_C()
	2609	{
	2610	UINT8 tmp = A - C;
	2611	ZHC_SUB( tmp, A, 0 );
	2612	A = tmp;
	2613	}
	2614
	2615	/* 60 e4: 0110 0000 1110 0100 */
	2616	void upd7810_device::SUB_A_D()
	2617	{
	2618	UINT8 tmp = A - D;
	2619	ZHC_SUB( tmp, A, 0 );
	2620	A = tmp;
	2621	}
	2622
	2623	/* 60 e5: 0110 0000 1110 0101 */
	2624	void upd7810_device::SUB_A_E()
	2625	{
	2626	UINT8 tmp = A - E;
	2627	ZHC_SUB( tmp, A, 0 );
	2628	A = tmp;
	2629	}
	2630
	2631	/* 60 e6: 0110 0000 1110 0110 */
	2632	void upd7810_device::SUB_A_H()
	2633	{
	2634	UINT8 tmp = A - H;
	2635	ZHC_SUB( tmp, A, 0 );
	2636	A = tmp;
	2637	}
	2638
	2639	/* 60 e7: 0110 0000 1110 0111 */
	2640	void upd7810_device::SUB_A_L()
	2641	{
	2642	UINT8 tmp = A - L;
	2643	ZHC_SUB( tmp, A, 0 );
	2644	A = tmp;
	2645	}
	2646
	2647	/* 60 e8: 0110 0000 1110 1000 */
	2648	void upd7810_device::NEA_A_V()
	2649	{
	2650	UINT8 tmp = A - V;
	2651	ZHC_SUB( tmp, A, 0 );
	2652	SKIP_NZ;
	2653	}
	2654
	2655	/* 60 e9: 0110 0000 1110 1001 */
	2656	/* NEA_A_A already defined */
	2657
	2658	/* 60 ea: 0110 0000 1110 1010 */
	2659	void upd7810_device::NEA_A_B()
	2660	{
	2661	UINT8 tmp = A - B;
	2662	ZHC_SUB( tmp, A, 0 );
	2663	SKIP_NZ;
	2664	}
	2665
	2666	/* 60 eb: 0110 0000 1110 1011 */
	2667	void upd7810_device::NEA_A_C()
	2668	{
	2669	UINT8 tmp = A - C;
	2670	ZHC_SUB( tmp, A, 0 );
	2671	SKIP_NZ;
	2672	}
	2673
	2674	/* 60 ec: 0110 0000 1110 1100 */
	2675	void upd7810_device::NEA_A_D()
	2676	{
	2677	UINT8 tmp = A - D;
	2678	ZHC_SUB( tmp, A, 0 );
	2679	SKIP_NZ;
	2680	}
	2681
	2682	/* 60 ed: 0110 0000 1110 1101 */
	2683	void upd7810_device::NEA_A_E()
	2684	{
	2685	UINT8 tmp = A - E;
	2686	ZHC_SUB( tmp, A, 0 );
	2687	SKIP_NZ;
	2688	}
	2689
	2690	/* 60 ee: 0110 0000 1110 1110 */
	2691	void upd7810_device::NEA_A_H()
	2692	{
	2693	UINT8 tmp = A - H;
	2694	ZHC_SUB( tmp, A, 0 );
	2695	SKIP_NZ;
	2696	}
	2697
	2698	/* 60 ef: 0110 0000 1110 1111 */
	2699	void upd7810_device::NEA_A_L()
	2700	{
	2701	UINT8 tmp = A - L;
	2702	ZHC_SUB( tmp, A, 0 );
	2703	SKIP_NZ;
	2704	}
	2705
	2706	/* 60 f0: 0110 0000 1111 0000 */
	2707	void upd7810_device::SBB_A_V()
	2708	{
	2709	UINT8 tmp = A - V - (PSW & CY);
	2710	ZHC_SUB( tmp, A, (PSW & CY) );
	2711	A = tmp;
	2712	}
	2713
	2714	/* 60 f1: 0110 0000 1111 0001 */
	2715	/* SBB_A_A already defined */
	2716
	2717	/* 60 f2: 0110 0000 1111 0010 */
	2718	void upd7810_device::SBB_A_B()
	2719	{
	2720	UINT8 tmp = A - B - (PSW & CY);
	2721	ZHC_SUB( tmp, A, (PSW & CY) );
	2722	A = tmp;
	2723	}
	2724
	2725	/* 60 f3: 0110 0000 1111 0011 */
	2726	void upd7810_device::SBB_A_C()
	2727	{
	2728	UINT8 tmp = A - C - (PSW & CY);
	2729	ZHC_SUB( tmp, A, (PSW & CY) );
	2730	A = tmp;
	2731	}
	2732
	2733	/* 60 f4: 0110 0000 1111 0100 */
	2734	void upd7810_device::SBB_A_D()
	2735	{
	2736	UINT8 tmp = A - D - (PSW & CY);
	2737	ZHC_SUB( tmp, A, (PSW & CY) );
	2738	A = tmp;
	2739	}
	2740
	2741	/* 60 f5: 0110 0000 1111 0101 */
	2742	void upd7810_device::SBB_A_E()
	2743	{
	2744	UINT8 tmp = A - E - (PSW & CY);
	2745	ZHC_SUB( tmp, A, (PSW & CY) );
	2746	A = tmp;
	2747	}
	2748
	2749	/* 60 f6: 0110 0000 1111 0110 */
	2750	void upd7810_device::SBB_A_H()
	2751	{
	2752	UINT8 tmp = A - H - (PSW & CY);
	2753	ZHC_SUB( tmp, A, (PSW & CY) );
	2754	A = tmp;
	2755	}
	2756
	2757	/* 60 f7: 0110 0000 1111 0111 */
	2758	void upd7810_device::SBB_A_L()
	2759	{
	2760	UINT8 tmp = A - L - (PSW & CY);
	2761	ZHC_SUB( tmp, A, (PSW & CY) );
	2762	A = tmp;
	2763	}
	2764
	2765	/* 60 f8: 0110 0000 1111 1000 */
	2766	void upd7810_device::EQA_A_V()
	2767	{
	2768	UINT8 tmp = A - V;
	2769	ZHC_SUB( tmp, A, 0 );
	2770	SKIP_Z;
	2771	}
	2772
	2773	/* 60 f9: 0110 0000 1111 1001 */
	2774	/* EQA_A_A already defined */
	2775
	2776	/* 60 fa: 0110 0000 1111 1010 */
	2777	void upd7810_device::EQA_A_B()
	2778	{
	2779	UINT8 tmp = A - B;
	2780	ZHC_SUB( tmp, A, 0 );
	2781	SKIP_Z;
	2782	}
	2783
	2784	/* 60 fb: 0110 0000 1111 1011 */
	2785	void upd7810_device::EQA_A_C()
	2786	{
	2787	UINT8 tmp = A - C;
	2788	ZHC_SUB( tmp, A, 0 );
	2789	SKIP_Z;
	2790	}
	2791
	2792	/* 60 fc: 0110 0000 1111 1100 */
	2793	void upd7810_device::EQA_A_D()
	2794	{
	2795	UINT8 tmp = A - D;
	2796	ZHC_SUB( tmp, A, 0 );
	2797	SKIP_Z;
	2798	}
	2799
	2800	/* 60 fd: 0110 0000 1111 1101 */
	2801	void upd7810_device::EQA_A_E()
	2802	{
	2803	UINT8 tmp = A - E;
	2804	ZHC_SUB( tmp, A, 0 );
	2805	SKIP_Z;
	2806	}
	2807
	2808	/* 60 fe: 0110 0000 1111 1110 */
	2809	void upd7810_device::EQA_A_H()
	2810	{
	2811	UINT8 tmp = A - H;
	2812	ZHC_SUB( tmp, A, 0 );
	2813	SKIP_Z;
	2814	}
	2815
	2816	/* 60 ff: 0110 0000 1111 1111 */
	2817	void upd7810_device::EQA_A_L()
	2818	{
	2819	UINT8 tmp = A - L;
	2820	ZHC_SUB( tmp, A, 0 );
	2821	SKIP_Z;
	2822	}
	2823
	2824	/* prefix 64 */
	2825	/* 64 00: 0110 0100 0000 0000 xxxx xxxx */
	2826	void upd7810_device::MVI_PA_xx()
	2827	{
	2828	UINT8 imm;
	2829	RDOPARG( imm );
	2830	WP( UPD7810_PORTA, imm );
	2831	}
	2832
	2833	/* 64 01: 0110 0100 0000 0001 xxxx xxxx */
	2834	void upd7810_device::MVI_PB_xx()
	2835	{
	2836	UINT8 imm;
	2837	RDOPARG( imm );
	2838	WP( UPD7810_PORTB, imm );
	2839	}
	2840
	2841	/* 64 02: 0110 0100 0000 0010 xxxx xxxx */
	2842	void upd7810_device::MVI_PC_xx()
	2843	{
	2844	UINT8 imm;
	2845	RDOPARG( imm );
	2846	WP( UPD7810_PORTC, imm );
	2847	}
	2848
	2849	/* 64 03: 0110 0100 0000 0011 xxxx xxxx */
	2850	void upd7810_device::MVI_PD_xx()
	2851	{
	2852	UINT8 imm;
	2853	RDOPARG( imm );
	2854	WP( UPD7810_PORTD, imm );
	2855	}
	2856
	2857	/* 64 05: 0110 0100 0000 0101 xxxx xxxx */
	2858	void upd7810_device::MVI_PF_xx()
	2859	{
	2860	UINT8 imm;
	2861	RDOPARG( imm );
	2862	WP( UPD7810_PORTF, imm );
	2863	}
	2864
	2865	/* 64 06: 0110 0100 0000 0110 xxxx xxxx */
	2866	void upd7810_device::MVI_MKH_xx()
	2867	{
	2868	RDOPARG( MKH );
	2869	}
	2870
	2871	/* 64 07: 0110 0100 0000 0111 xxxx xxxx */
	2872	void upd7810_device::MVI_MKL_xx()
	2873	{
	2874	RDOPARG( MKL );
	2875	}
	2876
	2877	/* 64 08: 0110 0100 0000 1000 xxxx xxxx */
	2878	void upd7810_device::ANI_PA_xx()
	2879	{
	2880	UINT8 pa = RP( UPD7810_PORTA), imm;
	2881	RDOPARG( imm );
	2882	pa &= imm;
	2883	WP( UPD7810_PORTA, pa );
	2884	SET_Z(pa);
	2885	}
	2886
	2887	/* 64 09: 0110 0100 0000 1001 xxxx xxxx */
	2888	void upd7810_device::ANI_PB_xx()
	2889	{
	2890	UINT8 pb = RP( UPD7810_PORTB), imm;
	2891	RDOPARG( imm );
	2892	pb &= imm;
	2893	WP( UPD7810_PORTB, pb );
	2894	SET_Z(pb);
	2895	}
	2896
	2897	/* 64 0a: 0110 0100 0000 1010 xxxx xxxx */
	2898	void upd7810_device::ANI_PC_xx()
	2899	{
	2900	UINT8 pc = RP( UPD7810_PORTC), imm;
	2901	RDOPARG( imm );
	2902	pc &= imm;
	2903	WP( UPD7810_PORTC, pc );
	2904	SET_Z(pc);
	2905	}
	2906
	2907	/* 64 0b: 0110 0100 0000 1011 xxxx xxxx */
	2908	void upd7810_device::ANI_PD_xx()
	2909	{
	2910	UINT8 pd = RP( UPD7810_PORTD ), imm;
	2911	RDOPARG( imm );
	2912	pd &= imm;
	2913	WP( UPD7810_PORTD, pd );
	2914	SET_Z(pd);
	2915	}
	2916
	2917	/* 64 0d: 0110 0100 0000 1101 xxxx xxxx */
	2918	void upd7810_device::ANI_PF_xx()
	2919	{
	2920	UINT8 pf = RP( UPD7810_PORTF ), imm;
	2921	RDOPARG( imm );
	2922	pf &= imm;
	2923	WP( UPD7810_PORTF, pf );
	2924	SET_Z(pf);
	2925	}
	2926
	2927	/* 64 0e: 0110 0100 0000 1110 xxxx xxxx */
	2928	void upd7810_device::ANI_MKH_xx()
	2929	{
	2930	UINT8 imm;
	2931	RDOPARG( imm );
	2932	MKH &= imm;
	2933	SET_Z(MKH);
	2934	}
	2935
	2936	/* 64 0f: 0110 0100 0000 1111 xxxx xxxx */
	2937	void upd7810_device::ANI_MKL_xx()
	2938	{
	2939	UINT8 imm;
	2940	RDOPARG( imm );
	2941	MKL &= imm;
	2942	SET_Z(MKL);
	2943	}
	2944
	2945	/* 64 10: 0110 0100 0001 0000 xxxx xxxx */
	2946	void upd7810_device::XRI_PA_xx()
	2947	{
	2948	UINT8 pa = RP( UPD7810_PORTA ), imm;
	2949	RDOPARG( imm );
	2950	pa ^= imm;
	2951	WP( UPD7810_PORTA, pa );
	2952	SET_Z(pa);
	2953	}
	2954
	2955	/* 64 11: 0110 0100 0001 0001 xxxx xxxx */
	2956	void upd7810_device::XRI_PB_xx()
	2957	{
	2958	UINT8 pb = RP( UPD7810_PORTB ), imm;
	2959	RDOPARG( imm );
	2960	pb ^= imm;
	2961	WP( UPD7810_PORTB, pb );
	2962	SET_Z(pb);
	2963	}
	2964
	2965	/* 64 12: 0110 0100 0001 0010 xxxx xxxx */
	2966	void upd7810_device::XRI_PC_xx()
	2967	{
	2968	UINT8 pc = RP( UPD7810_PORTC ), imm;
	2969	RDOPARG( imm );
	2970	pc ^= imm;
	2971	WP( UPD7810_PORTC, pc );
	2972	SET_Z(pc);
	2973	}
	2974
	2975	/* 64 13: 0110 0100 0001 0011 xxxx xxxx */
	2976	void upd7810_device::XRI_PD_xx()
	2977	{
	2978	UINT8 pd = RP( UPD7810_PORTD ), imm;
	2979	RDOPARG( imm );
	2980	pd ^= imm;
	2981	WP( UPD7810_PORTD, pd );
	2982	SET_Z(pd);
	2983	}
	2984
	2985	/* 64 15: 0110 0100 0001 0101 xxxx xxxx */
	2986	void upd7810_device::XRI_PF_xx()
	2987	{
	2988	UINT8 pf = RP( UPD7810_PORTF ), imm;
	2989	RDOPARG( imm );
	2990	pf ^= imm;
	2991	WP( UPD7810_PORTF, pf );
	2992	SET_Z(pf);
	2993	}
	2994
	2995	/* 64 16: 0110 0100 0001 0110 xxxx xxxx */
	2996	void upd7810_device::XRI_MKH_xx()
	2997	{
	2998	UINT8 imm;
	2999	RDOPARG( imm );
	3000	MKH ^= imm;
	3001	SET_Z(MKH);
	3002	}
	3003
	3004	/* 64 17: 0110 0100 0001 0111 xxxx xxxx */
	3005	void upd7810_device::XRI_MKL_xx()
	3006	{
	3007	UINT8 imm;
	3008	RDOPARG( imm );
	3009	MKL ^= imm;
	3010	SET_Z(MKL);
	3011	}
	3012
	3013	/* 64 18: 0110 0100 0001 1000 xxxx xxxx */
	3014	void upd7810_device::ORI_PA_xx()
	3015	{
	3016	UINT8 pa = RP( UPD7810_PORTA ), imm;
	3017	RDOPARG( imm );
	3018	pa \|= imm;
	3019	WP( UPD7810_PORTA, pa );
	3020	SET_Z(pa);
	3021	}
	3022
	3023	/* 64 19: 0110 0100 0001 1001 xxxx xxxx */
	3024	void upd7810_device::ORI_PB_xx()
	3025	{
	3026	UINT8 pb = RP( UPD7810_PORTB ), imm;
	3027	RDOPARG( imm );
	3028	pb \|= imm;
	3029	WP( UPD7810_PORTB, pb );
	3030	SET_Z(pb);
	3031	}
	3032
	3033	/* 64 1a: 0110 0100 0001 1010 xxxx xxxx */
	3034	void upd7810_device::ORI_PC_xx()
	3035	{
	3036	UINT8 pc = RP( UPD7810_PORTC ), imm;
	3037	RDOPARG( imm );
	3038	pc \|= imm;
	3039	WP( UPD7810_PORTC, pc );
	3040	SET_Z(pc);
	3041	}
	3042
	3043	/* 64 1b: 0110 0100 0001 1011 xxxx xxxx */
	3044	void upd7810_device::ORI_PD_xx()
	3045	{
	3046	UINT8 pd = RP( UPD7810_PORTD ), imm;
	3047	RDOPARG( imm );
	3048	pd \|= imm;
	3049	WP( UPD7810_PORTD, pd );
	3050	SET_Z(pd);
	3051	}
	3052
	3053	/* 64 1d: 0110 0100 0001 1101 xxxx xxxx */
	3054	void upd7810_device::ORI_PF_xx()
	3055	{
	3056	UINT8 pf = RP( UPD7810_PORTF ), imm;
	3057	RDOPARG( imm );
	3058	pf \|= imm;
	3059	WP( UPD7810_PORTF, pf );
	3060	SET_Z(pf);
	3061	}
	3062
	3063	/* 64 1e: 0110 0100 0001 1110 xxxx xxxx */
	3064	void upd7810_device::ORI_MKH_xx()
	3065	{
	3066	UINT8 imm;
	3067	RDOPARG( imm );
	3068	MKH \|= imm;
	3069	SET_Z(MKH);
	3070	}
	3071
	3072	/* 64 1f: 0110 0100 0001 1111 xxxx xxxx */
	3073	void upd7810_device::ORI_MKL_xx()
	3074	{
	3075	UINT8 imm;
	3076	RDOPARG( imm );
	3077	MKL \|= imm;
	3078	SET_Z(MKL);
	3079	}
	3080
	3081	/* 64 20: 0110 0100 0010 0000 xxxx xxxx */
	3082	void upd7810_device::ADINC_PA_xx()
	3083	{
	3084	UINT8 pa = RP( UPD7810_PORTA );
	3085	UINT8 tmp, imm;
	3086
	3087	RDOPARG( imm );
	3088	tmp = pa + imm;
	3089
	3090	ZHC_ADD( tmp, pa, 0 );
	3091	WP( UPD7810_PORTA , tmp );
	3092	SKIP_NC;
	3093	}
	3094
	3095	/* 64 21: 0110 0100 0010 0001 xxxx xxxx */
	3096	void upd7810_device::ADINC_PB_xx()
	3097	{
	3098	UINT8 pb = RP( UPD7810_PORTB );
	3099	UINT8 tmp, imm;
	3100
	3101	RDOPARG( imm );
	3102	tmp = pb + imm;
	3103
	3104	ZHC_ADD( tmp, pb, 0 );
	3105	WP( UPD7810_PORTB, tmp );
	3106	SKIP_NC;
	3107	}
	3108
	3109	/* 64 22: 0110 0100 0010 0010 xxxx xxxx */
	3110	void upd7810_device::ADINC_PC_xx()
	3111	{
	3112	UINT8 pc = RP( UPD7810_PORTC );
	3113	UINT8 tmp, imm;
	3114
	3115	RDOPARG( imm );
	3116	tmp = pc + imm;
	3117
	3118	ZHC_ADD( tmp, pc, 0 );
	3119	WP( UPD7810_PORTC, tmp );
	3120	SKIP_NC;
	3121	}
	3122
	3123	/* 64 23: 0110 0100 0010 0011 xxxx xxxx */
	3124	void upd7810_device::ADINC_PD_xx()
	3125	{
	3126	UINT8 pd = RP( UPD7810_PORTD );
	3127	UINT8 tmp, imm;
	3128
	3129	RDOPARG( imm );
	3130	tmp = pd + imm;
	3131
	3132	ZHC_ADD( tmp, pd, 0 );
	3133	WP( UPD7810_PORTD, tmp );
	3134	SKIP_NC;
	3135	}
	3136
	3137	/* 64 25: 0110 0100 0010 0101 xxxx xxxx */
	3138	void upd7810_device::ADINC_PF_xx()
	3139	{
	3140	UINT8 pf = RP( UPD7810_PORTF );
	3141	UINT8 tmp, imm;
	3142
	3143	RDOPARG( imm );
	3144	tmp = pf + imm;
	3145
	3146	ZHC_ADD( tmp, pf, 0 );
	3147	WP( UPD7810_PORTF, tmp );
	3148	SKIP_NC;
	3149	}
	3150
	3151	/* 64 26: 0110 0100 0010 0110 xxxx xxxx */
	3152	void upd7810_device::ADINC_MKH_xx()
	3153	{
	3154	UINT8 tmp, imm;
	3155
	3156	RDOPARG( imm );
	3157	tmp = MKH + imm;
	3158
	3159	ZHC_ADD( tmp, MKH, 0 );
	3160	MKH = tmp;
	3161	SKIP_NC;
	3162	}
	3163
	3164	/* 64 27: 0110 0100 0010 0111 xxxx xxxx */
	3165	void upd7810_device::ADINC_MKL_xx()
	3166	{
	3167	UINT8 tmp, imm;
	3168
	3169	RDOPARG( imm );
	3170	tmp = MKL + imm;
	3171
	3172	ZHC_ADD( tmp, MKL, 0 );
	3173	MKL = tmp;
	3174	SKIP_NC;
	3175	}
	3176
	3177	/* 64 28: 0110 0100 0010 1000 xxxx xxxx */
	3178	void upd7810_device::GTI_PA_xx()
	3179	{
	3180	UINT8 pa = RP( UPD7810_PORTA ), imm;
	3181	UINT16 tmp;
	3182
	3183	RDOPARG( imm );
	3184	tmp = pa - imm - 1;
	3185	ZHC_SUB( tmp, pa, 0 );
	3186
	3187	SKIP_NC;
	3188	}
	3189
	3190	/* 64 29: 0110 0100 0010 1001 xxxx xxxx */
	3191	void upd7810_device::GTI_PB_xx()
	3192	{
	3193	UINT8 pb = RP( UPD7810_PORTB ), imm;
	3194	UINT16 tmp;
	3195
	3196	RDOPARG( imm );
	3197	tmp = pb - imm - 1;
	3198	ZHC_SUB( tmp, pb, 0 );
	3199
	3200	SKIP_NC;
	3201	}
	3202
	3203	/* 64 2a: 0110 0100 0010 1010 xxxx xxxx */
	3204	void upd7810_device::GTI_PC_xx()
	3205	{
	3206	UINT8 pc = RP( UPD7810_PORTC ), imm;
	3207	UINT16 tmp;
	3208
	3209	RDOPARG( imm );
	3210	tmp = pc - imm - 1;
	3211	ZHC_SUB( tmp, pc, 0 );
	3212
	3213	SKIP_NC;
	3214	}
	3215
	3216	/* 64 2b: 0110 0100 0010 1011 xxxx xxxx */
	3217	void upd7810_device::GTI_PD_xx()
	3218	{
	3219	UINT8 pd = RP( UPD7810_PORTD ), imm;
	3220	UINT16 tmp;
	3221
	3222	RDOPARG( imm );
	3223	tmp = pd - imm - 1;
	3224	ZHC_SUB( tmp, pd, 0 );
	3225
	3226	SKIP_NC;
	3227	}
	3228
	3229	/* 64 2d: 0110 0100 0010 1101 xxxx xxxx */
	3230	void upd7810_device::GTI_PF_xx()
	3231	{
	3232	UINT8 pf = RP( UPD7810_PORTF ), imm;
	3233	UINT16 tmp;
	3234
	3235	RDOPARG( imm );
	3236	tmp = pf - imm - 1;
	3237	ZHC_SUB( tmp, pf, 0 );
	3238
	3239	SKIP_NC;
	3240	}
	3241
	3242	/* 64 2e: 0110 0100 0010 1110 xxxx xxxx */
	3243	void upd7810_device::GTI_MKH_xx()
	3244	{
	3245	UINT8 imm;
	3246	UINT16 tmp;
	3247
	3248	RDOPARG( imm );
	3249	tmp = MKH - imm - 1;
	3250	ZHC_SUB( tmp, MKH, 0 );
	3251
	3252	SKIP_NC;
	3253	}
	3254
	3255	/* 64 2f: 0110 0100 0010 1111 xxxx xxxx */
	3256	void upd7810_device::GTI_MKL_xx()
	3257	{
	3258	UINT8 imm;
	3259	UINT16 tmp;
	3260
	3261	RDOPARG( imm );
	3262	tmp = MKL - imm - 1;
	3263	ZHC_SUB( tmp, MKL, 0 );
	3264
	3265	SKIP_NC;
	3266	}
	3267
	3268	/* 64 30: 0110 0100 0011 0000 xxxx xxxx */
	3269	void upd7810_device::SUINB_PA_xx()
	3270	{
	3271	UINT8 pa = RP( UPD7810_PORTA ), tmp, imm;
	3272
	3273	RDOPARG( imm );
	3274	tmp = pa - imm;
	3275	ZHC_SUB( tmp, pa, 0 );
	3276	pa = tmp;
	3277	WP( UPD7810_PORTA, pa );
	3278	SKIP_NC;
	3279	}
	3280
	3281	/* 64 31: 0110 0100 0011 0001 xxxx xxxx */
	3282	void upd7810_device::SUINB_PB_xx()
	3283	{
	3284	UINT8 pb = RP( UPD7810_PORTB ), tmp, imm;
	3285
	3286	RDOPARG( imm );
	3287	tmp = pb - imm;
	3288	ZHC_SUB( tmp, pb, 0 );
	3289	pb = tmp;
	3290	WP( UPD7810_PORTB, pb );
	3291	SKIP_NC;
	3292	}
	3293
	3294	/* 64 32: 0110 0100 0011 0010 xxxx xxxx */
	3295	void upd7810_device::SUINB_PC_xx()
	3296	{
	3297	UINT8 pc = RP( UPD7810_PORTC ), tmp, imm;
	3298
	3299	RDOPARG( imm );
	3300	tmp = pc - imm;
	3301	ZHC_SUB( tmp, pc, 0 );
	3302	pc = tmp;
	3303	WP( UPD7810_PORTC, pc );
	3304	SKIP_NC;
	3305	}
	3306
	3307	/* 64 33: 0110 0100 0011 0011 xxxx xxxx */
	3308	void upd7810_device::SUINB_PD_xx()
	3309	{
	3310	UINT8 pd = RP( UPD7810_PORTD ), tmp, imm;
	3311
	3312	RDOPARG( imm );
	3313	tmp = pd - imm;
	3314	ZHC_SUB( tmp, pd, 0 );
	3315	pd = tmp;
	3316	WP( UPD7810_PORTD, pd );
	3317	SKIP_NC;
	3318	}
	3319
	3320	/* 64 35: 0110 0100 0011 0101 xxxx xxxx */
	3321	void upd7810_device::SUINB_PF_xx()
	3322	{
	3323	UINT8 pf = RP( UPD7810_PORTF ), tmp, imm;
	3324
	3325	RDOPARG( imm );
	3326	tmp = pf - imm;
	3327	ZHC_SUB( tmp, pf, 0 );
	3328	pf = tmp;
	3329	WP( UPD7810_PORTF, pf );
	3330	SKIP_NC;
	3331	}
	3332
	3333	/* 64 36: 0110 0100 0011 0110 xxxx xxxx */
	3334	void upd7810_device::SUINB_MKH_xx()
	3335	{
	3336	UINT8 tmp, imm;
	3337
	3338	RDOPARG( imm );
	3339	tmp = MKH - imm;
	3340	ZHC_SUB( tmp, MKH, 0 );
	3341	MKH = tmp;
	3342	SKIP_NC;
	3343	}
	3344
	3345	/* 64 37: 0110 0100 0011 0111 xxxx xxxx */
	3346	void upd7810_device::SUINB_MKL_xx()
	3347	{
	3348	UINT8 tmp, imm;
	3349
	3350	RDOPARG( imm );
	3351	tmp = MKL - imm;
	3352	ZHC_SUB( tmp, MKL, 0 );
	3353	MKL = tmp;
	3354	SKIP_NC;
	3355	}
	3356
	3357	/* 64 38: 0110 0100 0011 1000 xxxx xxxx */
	3358	void upd7810_device::LTI_PA_xx()
	3359	{
	3360	UINT8 pa = RP( UPD7810_PORTA ), tmp, imm;
	3361	RDOPARG( imm );
	3362	tmp = pa - imm;
	3363	ZHC_SUB( tmp, pa, 0 );
	3364	SKIP_CY;
	3365	}
	3366
	3367	/* 64 39: 0110 0100 0011 1001 xxxx xxxx */
	3368	void upd7810_device::LTI_PB_xx()
	3369	{
	3370	UINT8 pb = RP( UPD7810_PORTB ), tmp, imm;
	3371	RDOPARG( imm );
	3372	tmp = pb - imm;
	3373	ZHC_SUB( tmp, pb, 0 );
	3374	SKIP_CY;
	3375	}
	3376
	3377	/* 64 3a: 0110 0100 0011 1010 xxxx xxxx */
	3378	void upd7810_device::LTI_PC_xx()
	3379	{
	3380	UINT8 pc = RP( UPD7810_PORTC ), tmp, imm;
	3381	RDOPARG( imm );
	3382	tmp = pc - imm;
	3383	ZHC_SUB( tmp, pc, 0 );
	3384	SKIP_CY;
	3385	}
	3386
	3387	/* 64 3b: 0110 0100 0011 1011 xxxx xxxx */
	3388	void upd7810_device::LTI_PD_xx()
	3389	{
	3390	UINT8 pd = RP( UPD7810_PORTD ), tmp, imm;
	3391	RDOPARG( imm );
	3392	tmp = pd - imm;
	3393	ZHC_SUB( tmp, pd, 0 );
	3394	SKIP_CY;
	3395	}
	3396
	3397	/* 64 3d: 0110 0100 0011 1101 xxxx xxxx */
	3398	void upd7810_device::LTI_PF_xx()
	3399	{
	3400	UINT8 pf = RP( UPD7810_PORTF ), tmp, imm;
	3401	RDOPARG( imm );
	3402	tmp = pf - imm;
	3403	ZHC_SUB( tmp, pf, 0 );
	3404	SKIP_CY;
	3405	}
	3406
	3407	/* 64 3e: 0110 0100 0011 1110 xxxx xxxx */
	3408	void upd7810_device::LTI_MKH_xx()
	3409	{
	3410	UINT8 tmp, imm;
	3411
	3412	RDOPARG( imm );
	3413	tmp = MKH - imm;
	3414	ZHC_SUB( tmp, MKH, 0 );
	3415	SKIP_CY;
	3416	}
	3417
	3418	/* 64 3f: 0110 0100 0011 1111 xxxx xxxx */
	3419	void upd7810_device::LTI_MKL_xx()
	3420	{
	3421	UINT8 tmp, imm;
	3422
	3423	RDOPARG( imm );
	3424	tmp = MKL - imm;
	3425	ZHC_SUB( tmp, MKL, 0 );
	3426	SKIP_CY;
	3427	}
	3428
	3429	/* 64 40: 0110 0100 0100 0000 xxxx xxxx */
	3430	void upd7810_device::ADI_PA_xx()
	3431	{
	3432	UINT8 pa = RP( UPD7810_PORTA ), tmp, imm;
	3433
	3434	RDOPARG( imm );
	3435	tmp = pa + imm;
	3436	ZHC_ADD( tmp, pa, 0 );
	3437	pa = tmp;
	3438	WP( UPD7810_PORTA, pa );
	3439	}
	3440
	3441	/* 64 41: 0110 0100 0100 0001 xxxx xxxx */
	3442	void upd7810_device::ADI_PB_xx()
	3443	{
	3444	UINT8 pb = RP( UPD7810_PORTB ), tmp, imm;
	3445
	3446	RDOPARG( imm );
	3447	tmp = pb + imm;
	3448	ZHC_ADD( tmp, pb, 0 );
	3449	pb = tmp;
	3450	WP( UPD7810_PORTB, pb );
	3451	}
	3452
	3453	/* 64 42: 0110 0100 0100 0010 xxxx xxxx */
	3454	void upd7810_device::ADI_PC_xx()
	3455	{
	3456	UINT8 pc = RP( UPD7810_PORTC ), tmp, imm;
	3457
	3458	RDOPARG( imm );
	3459	tmp = pc + imm;
	3460	ZHC_ADD( tmp, pc, 0 );
	3461	pc = tmp;
	3462	WP( UPD7810_PORTC, pc );
	3463	}
	3464
	3465	/* 64 43: 0110 0100 0100 0011 xxxx xxxx */
	3466	void upd7810_device::ADI_PD_xx()
	3467	{
	3468	UINT8 pd = RP( UPD7810_PORTD ), tmp, imm;
	3469
	3470	RDOPARG( imm );
	3471	tmp = pd + imm;
	3472	ZHC_ADD( tmp, pd, 0 );
	3473	pd = tmp;
	3474	WP( UPD7810_PORTD, pd );
	3475	}
	3476
	3477	/* 64 45: 0110 0100 0100 0101 xxxx xxxx */
	3478	void upd7810_device::ADI_PF_xx()
	3479	{
	3480	UINT8 pf = RP( UPD7810_PORTF ), tmp, imm;
	3481
	3482	RDOPARG( imm );
	3483	tmp = pf + imm;
	3484	ZHC_ADD( tmp, pf, 0 );
	3485	pf = tmp;
	3486	WP( UPD7810_PORTF, pf );
	3487	}
	3488
	3489	/* 64 46: 0110 0100 0100 0110 xxxx xxxx */
	3490	void upd7810_device::ADI_MKH_xx()
	3491	{
	3492	UINT8 tmp, imm;
	3493
	3494	RDOPARG( imm );
	3495	tmp = MKH + imm;
	3496	ZHC_ADD( tmp, MKH, 0 );
	3497	MKH = tmp;
	3498	}
	3499
	3500	/* 64 47: 0110 0100 0100 0111 xxxx xxxx */
	3501	void upd7810_device::ADI_MKL_xx()
	3502	{
	3503	UINT8 tmp, imm;
	3504
	3505	RDOPARG( imm );
	3506	tmp = MKL + imm;
	3507	ZHC_ADD( tmp, MKL, 0 );
	3508	MKL = tmp;
	3509	}
	3510
	3511	/* 64 48: 0110 0100 0100 1000 xxxx xxxx */
	3512	void upd7810_device::ONI_PA_xx()
	3513	{
	3514	UINT8 pa = RP( UPD7810_PORTA ), imm;
	3515
	3516	RDOPARG( imm );
	3517	if (pa & imm)
	3518	PSW \|= SK;
	3519	}
	3520
	3521	/* 64 49: 0110 0100 0100 1001 xxxx xxxx */
	3522	void upd7810_device::ONI_PB_xx()
	3523	{
	3524	UINT8 pb = RP( UPD7810_PORTB ), imm;
	3525
	3526	RDOPARG( imm );
	3527	if (pb & imm)
	3528	PSW \|= SK;
	3529	}
	3530
	3531	/* 64 4a: 0110 0100 0100 1010 xxxx xxxx */
	3532	void upd7810_device::ONI_PC_xx()
	3533	{
	3534	UINT8 pc = RP( UPD7810_PORTC ), imm;
	3535
	3536	RDOPARG( imm );
	3537	if (pc & imm)
	3538	PSW \|= SK;
	3539	}
	3540
	3541	/* 64 4b: 0110 0100 0100 1011 xxxx xxxx */
	3542	void upd7810_device::ONI_PD_xx()
	3543	{
	3544	UINT8 pd = RP( UPD7810_PORTD ), imm;
	3545
	3546	RDOPARG( imm );
	3547	if (pd & imm)
	3548	PSW \|= SK;
	3549	}
	3550
	3551	/* 64 4d: 0110 0100 0100 1101 xxxx xxxx */
	3552	void upd7810_device::ONI_PF_xx()
	3553	{
	3554	UINT8 pf = RP( UPD7810_PORTF ), imm;
	3555
	3556	RDOPARG( imm );
	3557	if (pf & imm)
	3558	PSW \|= SK;
	3559	}
	3560
	3561	/* 64 4e: 0110 0100 0100 1110 xxxx xxxx */
	3562	void upd7810_device::ONI_MKH_xx()
	3563	{
	3564	UINT8 imm;
	3565
	3566	RDOPARG( imm );
	3567	if (MKH & imm)
	3568	PSW \|= SK;
	3569	}
	3570
	3571	/* 64 4f: 0110 0100 0100 1111 xxxx xxxx */
	3572	void upd7810_device::ONI_MKL_xx()
	3573	{
	3574	UINT8 imm;
	3575
	3576	RDOPARG( imm );
	3577	if (MKL & imm)
	3578	PSW \|= SK;
	3579	}
	3580
	3581	/* 64 50: 0110 0100 0101 0000 xxxx xxxx */
	3582	void upd7810_device::ACI_PA_xx()
	3583	{
	3584	UINT8 pa = RP( UPD7810_PORTA ), tmp, imm;
	3585
	3586	RDOPARG( imm );
	3587	tmp = pa + imm + (PSW & CY);
	3588	ZHC_ADD( tmp, pa, (PSW & CY) );
	3589	pa = tmp;
	3590	WP( UPD7810_PORTA, pa );
	3591	}
	3592
	3593	/* 64 51: 0110 0100 0101 0001 xxxx xxxx */
	3594	void upd7810_device::ACI_PB_xx()
	3595	{
	3596	UINT8 pb = RP( UPD7810_PORTB ), tmp, imm;
	3597
	3598	RDOPARG( imm );
	3599	tmp = pb + imm + (PSW & CY);
	3600	ZHC_ADD( tmp, pb, (PSW & CY) );
	3601	pb = tmp;
	3602	WP( UPD7810_PORTB, pb );
	3603	}
	3604
	3605	/* 64 52: 0110 0100 0101 0010 xxxx xxxx */
	3606	void upd7810_device::ACI_PC_xx()
	3607	{
	3608	UINT8 pc = RP( UPD7810_PORTC ), tmp, imm;
	3609
	3610	RDOPARG( imm );
	3611	tmp = pc + imm + (PSW & CY);
	3612	ZHC_ADD( tmp, pc, (PSW & CY) );
	3613	pc = tmp;
	3614	WP( UPD7810_PORTC, pc );
	3615	}
	3616
	3617	/* 64 53: 0110 0100 0101 0011 xxxx xxxx */
	3618	void upd7810_device::ACI_PD_xx()
	3619	{
	3620	UINT8 pd = RP( UPD7810_PORTD ), tmp, imm;
	3621
	3622	RDOPARG( imm );
	3623	tmp = pd + imm + (PSW & CY);
	3624	ZHC_ADD( tmp, pd, (PSW & CY) );
	3625	pd = tmp;
	3626	WP( UPD7810_PORTD, pd );
	3627	}
	3628
	3629	/* 64 55: 0110 0100 0101 0101 xxxx xxxx */
	3630	void upd7810_device::ACI_PF_xx()
	3631	{
	3632	UINT8 pf = RP( UPD7810_PORTF ), tmp, imm;
	3633
	3634	RDOPARG( imm );
	3635	tmp = pf + imm + (PSW & CY);
	3636	ZHC_ADD( tmp, pf, (PSW & CY) );
	3637	pf = tmp;
	3638	WP( UPD7810_PORTF, pf );
	3639	}
	3640
	3641	/* 64 56: 0110 0100 0101 0110 xxxx xxxx */
	3642	void upd7810_device::ACI_MKH_xx()
	3643	{
	3644	UINT8 imm, tmp;
	3645
	3646	RDOPARG( imm );
	3647	tmp = MKH + imm + (PSW & CY);
	3648	ZHC_ADD( tmp, MKH, (PSW & CY) );
	3649	MKH = tmp;
	3650	}
	3651
	3652	/* 64 57: 0110 0100 0101 0111 xxxx xxxx */
	3653	void upd7810_device::ACI_MKL_xx()
	3654	{
	3655	UINT8 imm, tmp;
	3656
	3657	RDOPARG( imm );
	3658	tmp = MKL + imm + (PSW & CY);
	3659	ZHC_ADD( tmp, MKL, (PSW & CY) );
	3660	MKL = tmp;
	3661	}
	3662
	3663	/* 64 58: 0110 0100 0101 1000 xxxx xxxx */
	3664	void upd7810_device::OFFI_PA_xx()
	3665	{
	3666	UINT8 pa = RP( UPD7810_PORTA ), imm;
	3667
	3668	RDOPARG( imm );
	3669	if (0 == (pa & imm))
	3670	PSW \|= SK;
	3671	}
	3672
	3673	/* 64 59: 0110 0100 0101 1001 xxxx xxxx */
	3674	void upd7810_device::OFFI_PB_xx()
	3675	{
	3676	UINT8 pb = RP( UPD7810_PORTB ), imm;
	3677
	3678	RDOPARG( imm );
	3679	if (0 == (pb & imm))
	3680	PSW \|= SK;
	3681	}
	3682
	3683	/* 64 5a: 0110 0100 0101 1010 xxxx xxxx */
	3684	void upd7810_device::OFFI_PC_xx()
	3685	{
	3686	UINT8 pc = RP( UPD7810_PORTC ), imm;
	3687
	3688	RDOPARG( imm );
	3689	if (0 == (pc & imm))
	3690	PSW \|= SK;
	3691	}
	3692
	3693	/* 64 5b: 0110 0100 0101 1011 xxxx xxxx */
	3694	void upd7810_device::OFFI_PD_xx()
	3695	{
	3696	UINT8 pd = RP( UPD7810_PORTD ), imm;
	3697
	3698	RDOPARG( imm );
	3699	if (0 == (pd & imm))
	3700	PSW \|= SK;
	3701	}
	3702
	3703	/* 64 5d: 0110 0100 0101 1101 xxxx xxxx */
	3704	void upd7810_device::OFFI_PF_xx()
	3705	{
	3706	UINT8 pf = RP( UPD7810_PORTF ), imm;
	3707
	3708	RDOPARG( imm );
	3709	if (0 == (pf & imm))
	3710	PSW \|= SK;
	3711	}
	3712
	3713	/* 64 5e: 0110 0100 0101 1110 xxxx xxxx */
	3714	void upd7810_device::OFFI_MKH_xx()
	3715	{
	3716	UINT8 imm;
	3717
	3718	RDOPARG( imm );
	3719	if (0 == (MKH & imm))
	3720	PSW \|= SK;
	3721	}
	3722
	3723	/* 64 5f: 0110 0100 0101 1111 xxxx xxxx */
	3724	void upd7810_device::OFFI_MKL_xx()
	3725	{
	3726	UINT8 imm;
	3727
	3728	RDOPARG( imm );
	3729	if (0 == (MKL & imm))
	3730	PSW \|= SK;
	3731	}
	3732
	3733	/* 64 60: 0110 0100 0110 0000 xxxx xxxx */
	3734	void upd7810_device::SUI_PA_xx()
	3735	{
	3736	UINT8 pa = RP( UPD7810_PORTA ), tmp, imm;
	3737
	3738	RDOPARG( imm );
	3739	tmp = pa - imm;
	3740	ZHC_SUB( tmp, pa, 0 );
	3741	pa = tmp;
	3742	WP( UPD7810_PORTA, pa );
	3743	}
	3744
	3745	/* 64 61: 0110 0100 0110 0001 xxxx xxxx */
	3746	void upd7810_device::SUI_PB_xx()
	3747	{
	3748	UINT8 pb = RP( UPD7810_PORTB ), tmp, imm;
	3749
	3750	RDOPARG( imm );
	3751	tmp = pb - imm;
	3752	ZHC_SUB( tmp, pb, 0 );
	3753	pb = tmp;
	3754	WP( UPD7810_PORTB, pb );
	3755	}
	3756
	3757	/* 64 62: 0110 0100 0110 0010 xxxx xxxx */
	3758	void upd7810_device::SUI_PC_xx()
	3759	{
	3760	UINT8 pc = RP( UPD7810_PORTC ), tmp, imm;
	3761
	3762	RDOPARG( imm );
	3763	tmp = pc - imm;
	3764	ZHC_SUB( tmp, pc, 0 );
	3765	pc = tmp;
	3766	WP( UPD7810_PORTC, pc );
	3767	}
	3768
	3769	/* 64 63: 0110 0100 0110 0011 xxxx xxxx */
	3770	void upd7810_device::SUI_PD_xx()
	3771	{
	3772	UINT8 pd = RP( UPD7810_PORTD ), tmp, imm;
	3773
	3774	RDOPARG( imm );
	3775	tmp = pd - imm;
	3776	ZHC_SUB( tmp, pd, 0 );
	3777	pd = tmp;
	3778	WP( UPD7810_PORTD, pd );
	3779	}
	3780
	3781	/* 64 65: 0110 0100 0110 0101 xxxx xxxx */
	3782	void upd7810_device::SUI_PF_xx()
	3783	{
	3784	UINT8 pf = RP( UPD7810_PORTF ), tmp, imm;
	3785
	3786	RDOPARG( imm );
	3787	tmp = pf - imm;
	3788	ZHC_SUB( tmp, pf, 0 );
	3789	pf = tmp;
	3790	WP( UPD7810_PORTF, pf );
	3791	}
	3792
	3793	/* 64 66: 0110 0100 0110 0110 xxxx xxxx */
	3794	void upd7810_device::SUI_MKH_xx()
	3795	{
	3796	UINT8 tmp, imm;
	3797
	3798	RDOPARG( imm );
	3799	tmp = MKH - imm;
	3800	ZHC_SUB( tmp, MKH, 0 );
	3801	MKH = tmp;
	3802	}
	3803
	3804	/* 64 67: 0110 0100 0110 0111 xxxx xxxx */
	3805	void upd7810_device::SUI_MKL_xx()
	3806	{
	3807	UINT8 tmp, imm;
	3808
	3809	RDOPARG( imm );
	3810	tmp = MKL - imm;
	3811	ZHC_SUB( tmp, MKL, 0 );
	3812	MKL = tmp;
	3813	}
	3814
	3815	/* 64 68: 0110 0100 0110 1000 xxxx xxxx */
	3816	void upd7810_device::NEI_PA_xx()
	3817	{
	3818	UINT8 pa = RP( UPD7810_PORTA ), tmp, imm;
	3819
	3820	RDOPARG( imm );
	3821	tmp = pa - imm;
	3822	ZHC_SUB( tmp, pa, 0 );
	3823	SKIP_NZ;
	3824	}
	3825
	3826	/* 64 69: 0110 0100 0110 1001 xxxx xxxx */
	3827	void upd7810_device::NEI_PB_xx()
	3828	{
	3829	UINT8 pb = RP( UPD7810_PORTB ), tmp, imm;
	3830
	3831	RDOPARG( imm );
	3832	tmp = pb - imm;
	3833	ZHC_SUB( tmp, pb, 0 );
	3834	SKIP_NZ;
	3835	}
	3836
	3837	/* 64 6a: 0110 0100 0110 1010 xxxx xxxx */
	3838	void upd7810_device::NEI_PC_xx()
	3839	{
	3840	UINT8 pc = RP( UPD7810_PORTC ), tmp, imm;
	3841
	3842	RDOPARG( imm );
	3843	tmp = pc - imm;
	3844	ZHC_SUB( tmp, pc, 0 );
	3845	SKIP_NZ;
	3846	}
	3847
	3848	/* 64 6b: 0110 0100 0110 1011 xxxx xxxx */
	3849	void upd7810_device::NEI_PD_xx()
	3850	{
	3851	UINT8 pd = RP( UPD7810_PORTD ), tmp, imm;
	3852
	3853	RDOPARG( imm );
	3854	tmp = pd - imm;
	3855	ZHC_SUB( tmp, pd, 0 );
	3856	SKIP_NZ;
	3857	}
	3858
	3859	/* 64 6d: 0110 0100 0110 1101 xxxx xxxx */
	3860	void upd7810_device::NEI_PF_xx()
	3861	{
	3862	UINT8 pf = RP( UPD7810_PORTF ), tmp, imm;
	3863
	3864	RDOPARG( imm );
	3865	tmp = pf - imm;
	3866	ZHC_SUB( tmp, pf, 0 );
	3867	SKIP_NZ;
	3868	}
	3869
	3870	/* 64 6e: 0110 0100 0110 1110 xxxx xxxx */
	3871	void upd7810_device::NEI_MKH_xx()
	3872	{
	3873	UINT8 tmp, imm;
	3874
	3875	RDOPARG( imm );
	3876	tmp = MKH - imm;
	3877	ZHC_SUB( tmp, MKH, 0 );
	3878	SKIP_NZ;
	3879	}
	3880
	3881	/* 64 6f: 0110 0100 0110 1111 xxxx xxxx */
	3882	void upd7810_device::NEI_MKL_xx()
	3883	{
	3884	UINT8 tmp, imm;
	3885
	3886	RDOPARG( imm );
	3887	tmp = MKL - imm;
	3888	ZHC_SUB( tmp, MKL, 0 );
	3889	SKIP_NZ;
	3890	}
	3891
	3892	/* 64 70: 0110 0100 0111 0000 xxxx xxxx */
	3893	void upd7810_device::SBI_PA_xx()
	3894	{
	3895	UINT8 pa = RP( UPD7810_PORTA ), tmp, imm;
	3896
	3897	RDOPARG( imm );
	3898	tmp = pa - imm - (PSW & CY);
	3899	ZHC_SUB( tmp, pa, (PSW & CY) );
	3900	pa = tmp;
	3901	WP( UPD7810_PORTA, pa );
	3902	}
	3903
	3904	/* 64 71: 0110 0100 0111 0001 xxxx xxxx */
	3905	void upd7810_device::SBI_PB_xx()
	3906	{
	3907	UINT8 pb = RP( UPD7810_PORTB ), tmp, imm;
	3908
	3909	RDOPARG( imm );
	3910	tmp = pb - imm - (PSW & CY);
	3911	ZHC_SUB( tmp, pb, (PSW & CY) );
	3912	pb = tmp;
	3913	WP( UPD7810_PORTB, pb );
	3914	}
	3915
	3916	/* 64 72: 0110 0100 0111 0010 xxxx xxxx */
	3917	void upd7810_device::SBI_PC_xx()
	3918	{
	3919	UINT8 pc = RP( UPD7810_PORTC ), tmp, imm;
	3920
	3921	RDOPARG( imm );
	3922	tmp = pc - imm - (PSW & CY);
	3923	ZHC_SUB( tmp, pc, (PSW & CY) );
	3924	pc = tmp;
	3925	WP( UPD7810_PORTC, pc );
	3926	}
	3927
	3928	/* 64 73: 0110 0100 0111 0011 xxxx xxxx */
	3929	void upd7810_device::SBI_PD_xx()
	3930	{
	3931	UINT8 pd = RP( UPD7810_PORTD ), tmp, imm;
	3932
	3933	RDOPARG( imm );
	3934	tmp = pd - imm - (PSW & CY);
	3935	ZHC_SUB( tmp, pd, (PSW & CY) );
	3936	pd = tmp;
	3937	WP( UPD7810_PORTD, pd );
	3938	}
	3939
	3940	/* 64 75: 0110 0100 0111 0101 xxxx xxxx */
	3941	void upd7810_device::SBI_PF_xx()
	3942	{
	3943	UINT8 pf = RP( UPD7810_PORTF ), tmp, imm;
	3944
	3945	RDOPARG( imm );
	3946	tmp = pf - imm - (PSW & CY);
	3947	ZHC_SUB( tmp, pf, (PSW & CY) );
	3948	pf = tmp;
	3949	WP( UPD7810_PORTF, pf );
	3950	}
	3951
	3952	/* 64 76: 0110 0100 0111 0110 xxxx xxxx */
	3953	void upd7810_device::SBI_MKH_xx()
	3954	{
	3955	UINT8 tmp, imm;
	3956
	3957	RDOPARG( imm );
	3958	tmp = MKH - imm - (PSW & CY);
	3959	ZHC_SUB( tmp, MKH, (PSW & CY) );
	3960	MKH = tmp;
	3961	}
	3962
	3963	/* 64 77: 0110 0100 0111 0111 xxxx xxxx */
	3964	void upd7810_device::SBI_MKL_xx()
	3965	{
	3966	UINT8 tmp, imm;
	3967
	3968	RDOPARG( imm );
	3969	tmp = MKL - imm - (PSW & CY);
	3970	ZHC_SUB( tmp, MKL, (PSW & CY) );
	3971	MKL = tmp;
	3972	}
	3973
	3974	/* 64 78: 0110 0100 0111 1000 xxxx xxxx */
	3975	void upd7810_device::EQI_PA_xx()
	3976	{
	3977	UINT8 pa = RP( UPD7810_PORTA ), tmp, imm;
	3978
	3979	RDOPARG( imm );
	3980	tmp = pa - imm;
	3981	ZHC_SUB( tmp, pa, 0 );
	3982	SKIP_Z;
	3983	}
	3984
	3985	/* 64 79: 0110 0100 0111 1001 xxxx xxxx */
	3986	void upd7810_device::EQI_PB_xx()
	3987	{
	3988	UINT8 pb = RP( UPD7810_PORTB ), tmp, imm;
	3989
	3990	RDOPARG( imm );
	3991	tmp = pb - imm;
	3992	ZHC_SUB( tmp, pb, 0 );
	3993	SKIP_Z;
	3994	}
	3995
	3996	/* 64 7a: 0110 0100 0111 1010 xxxx xxxx */
	3997	void upd7810_device::EQI_PC_xx()
	3998	{
	3999	UINT8 pc = RP( UPD7810_PORTC ), tmp, imm;
	4000
	4001	RDOPARG( imm );
	4002	tmp = pc - imm;
	4003	ZHC_SUB( tmp, pc, 0 );
	4004	SKIP_Z;
	4005	}
	4006
	4007	/* 64 7b: 0110 0100 0111 1011 xxxx xxxx */
	4008	void upd7810_device::EQI_PD_xx()
	4009	{
	4010	UINT8 pd = RP( UPD7810_PORTD ), tmp, imm;
	4011
	4012	RDOPARG( imm );
	4013	tmp = pd - imm;
	4014	ZHC_SUB( tmp, pd, 0 );
	4015	SKIP_Z;
	4016	}
	4017
	4018	/* 64 7d: 0110 0100 0111 1101 xxxx xxxx */
	4019	void upd7810_device::EQI_PF_xx()
	4020	{
	4021	UINT8 pf = RP( UPD7810_PORTF ), tmp, imm;
	4022
	4023	RDOPARG( imm );
	4024	tmp = pf - imm;
	4025	ZHC_SUB( tmp, pf, 0 );
	4026	SKIP_Z;
	4027	}
	4028
	4029	/* 64 7e: 0110 0100 0111 1110 xxxx xxxx */
	4030	void upd7810_device::EQI_MKH_xx()
	4031	{
	4032	UINT8 tmp, imm;
	4033
	4034	RDOPARG( imm );
	4035	tmp = MKH - imm;
	4036	ZHC_SUB( tmp, MKH, 0 );
	4037	SKIP_Z;
	4038	}
	4039
	4040	/* 64 7f: 0110 0100 0111 1111 xxxx xxxx */
	4041	void upd7810_device::EQI_MKL_xx()
	4042	{
	4043	UINT8 tmp, imm;
	4044
	4045	RDOPARG( imm );
	4046	tmp = MKL - imm;
	4047	ZHC_SUB( tmp, MKL, 0 );
	4048	SKIP_Z;
	4049	}
	4050
	4051	/* 64 80: 0110 0100 1000 0000 xxxx xxxx */
	4052	void upd7810_device::MVI_ANM_xx()
	4053	{
	4054	RDOPARG( ANM );
	4055	}
	4056
	4057	/* 64 81: 0110 0100 1000 0001 xxxx xxxx */
	4058	void upd7810_device::MVI_SMH_xx()
	4059	{
	4060	RDOPARG( SMH );
	4061	}
	4062
	4063	/* 64 83: 0110 0100 1000 0011 xxxx xxxx */
	4064	void upd7810_device::MVI_EOM_xx()
	4065	{
	4066	RDOPARG( EOM );
	4067	upd7810_write_EOM();
	4068	}
	4069
	4070	/* 64 85: 0110 0100 1000 0101 xxxx xxxx */
	4071	void upd7810_device::MVI_TMM_xx()
	4072	{
	4073	RDOPARG( TMM );
	4074	}
	4075
	4076	/* 64 88: 0110 0100 1000 1000 xxxx xxxx */
	4077	void upd7810_device::ANI_ANM_xx()
	4078	{
	4079	UINT8 imm;
	4080
	4081	RDOPARG( imm );
	4082	ANM &= imm;
	4083	SET_Z(ANM);
	4084	}
	4085
	4086	/* 64 89: 0110 0100 1000 1001 xxxx xxxx */
	4087	void upd7810_device::ANI_SMH_xx()
	4088	{
	4089	UINT8 imm;
	4090
	4091	RDOPARG( imm );
	4092	SMH &= imm;
	4093	SET_Z(SMH);
	4094	}
	4095
	4096	/* 64 8b: 0110 0100 1000 1011 xxxx xxxx */
	4097	void upd7810_device::ANI_EOM_xx()
	4098	{
	4099	/* only bits #1 and #5 can be read */
	4100	UINT8 eom = EOM & 0x22;
	4101	UINT8 imm;
	4102
	4103	RDOPARG( imm );
	4104	/* only bits #1 and #5 can be read */
	4105	EOM = eom & imm;
	4106	SET_Z(EOM);
	4107	upd7810_write_EOM();
	4108	}
	4109
	4110	/* 64 8d: 0110 0100 1000 1101 xxxx xxxx */
	4111	void upd7810_device::ANI_TMM_xx()
	4112	{
	4113	UINT8 imm;
	4114
	4115	RDOPARG( imm );
	4116	TMM &= imm;
	4117	SET_Z(TMM);
	4118	}
	4119
	4120	/* 64 90: 0110 0100 1001 0000 xxxx xxxx */
	4121	void upd7810_device::XRI_ANM_xx()
	4122	{
	4123	UINT8 imm;
	4124
	4125	RDOPARG( imm );
	4126	ANM ^= imm;
	4127	SET_Z(ANM);
	4128	}
	4129
	4130	/* 64 91: 0110 0100 1001 0001 xxxx xxxx */
	4131	void upd7810_device::XRI_SMH_xx()
	4132	{
	4133	UINT8 imm;
	4134
	4135	RDOPARG( imm );
	4136	SMH ^= imm;
	4137	SET_Z(SMH);
	4138	}
	4139
	4140	/* 64 93: 0110 0100 1001 0011 xxxx xxxx */
	4141	void upd7810_device::XRI_EOM_xx()
	4142	{
	4143	/* only bits #1 and #5 can be read */
	4144	UINT8 eom = EOM & 0x22;
	4145	UINT8 imm;
	4146
	4147	RDOPARG( imm );
	4148	/* only bits #1 and #5 can be read */
	4149	EOM = eom ^ imm;
	4150	SET_Z(EOM);
	4151	upd7810_write_EOM();
	4152	}
	4153
	4154	/* 64 95: 0110 0100 1001 0101 xxxx xxxx */
	4155	void upd7810_device::XRI_TMM_xx()
	4156	{
	4157	UINT8 imm;
	4158
	4159	RDOPARG( imm );
	4160	TMM ^= imm;
	4161	SET_Z(TMM);
	4162	}
	4163
	4164	/* 64 98: 0110 0100 1001 1000 xxxx xxxx */
	4165	void upd7810_device::ORI_ANM_xx()
	4166	{
	4167	UINT8 imm;
	4168
	4169	RDOPARG( imm );
	4170	ANM \|= imm;
	4171	SET_Z(ANM);
	4172	}
	4173
	4174	/* 64 99: 0110 0100 1001 1001 xxxx xxxx */
	4175	void upd7810_device::ORI_SMH_xx()
	4176	{
	4177	UINT8 imm;
	4178
	4179	RDOPARG( imm );
	4180	SMH \|= imm;
	4181	SET_Z(SMH);
	4182	}
	4183
	4184	/* 64 9b: 0110 0100 1001 1011 xxxx xxxx */
	4185	void upd7810_device::ORI_EOM_xx()
	4186	{
	4187	/* only bits #1 and #5 can be read */
	4188	UINT8 eom = EOM & 0x22;
	4189	UINT8 imm;
	4190
	4191	RDOPARG( imm );
	4192	/* only bits #1 and #5 can be read */
	4193	EOM = eom \| imm;
	4194	SET_Z(EOM);
	4195	upd7810_write_EOM();
	4196	}
	4197
	4198	/* 64 9d: 0110 0100 1001 1101 xxxx xxxx */
	4199	void upd7810_device::ORI_TMM_xx()
	4200	{
	4201	UINT8 imm;
	4202
	4203	RDOPARG( imm );
	4204	TMM \|= imm;
	4205	SET_Z(TMM);
	4206	}
	4207
	4208	/* 64 a0: 0110 0100 1010 0000 xxxx xxxx */
	4209	void upd7810_device::ADINC_ANM_xx()
	4210	{
	4211	UINT8 tmp, imm;
	4212
	4213	RDOPARG( imm );
	4214	tmp = ANM + imm;
	4215
	4216	ZHC_ADD( tmp, ANM, 0 );
	4217	ANM = tmp;
	4218	SKIP_NC;
	4219	}
	4220
	4221	/* 64 a1: 0110 0100 1010 0001 xxxx xxxx */
	4222	void upd7810_device::ADINC_SMH_xx()
	4223	{
	4224	UINT8 tmp, imm;
	4225
	4226	RDOPARG( imm );
	4227	tmp = SMH + imm;
	4228
	4229	ZHC_ADD( tmp, SMH, 0 );
	4230	SMH = tmp;
	4231	SKIP_NC;
	4232	}
	4233
	4234	/* 64 a3: 0110 0100 1010 0011 xxxx xxxx */
	4235	void upd7810_device::ADINC_EOM_xx()
	4236	{
	4237	/* only bits #1 and #5 can be read */
	4238	UINT8 eom = EOM & 0x22;
	4239	UINT8 tmp, imm;
	4240
	4241	RDOPARG( imm );
	4242	/* only bits #1 and #5 can be read */
	4243	tmp = eom + imm;
	4244
	4245	ZHC_ADD( tmp, eom, 0 );
	4246	EOM = tmp;
	4247	SKIP_NC;
	4248	upd7810_write_EOM();
	4249	}
	4250
	4251	/* 64 a5: 0110 0100 1010 0101 xxxx xxxx */
	4252	void upd7810_device::ADINC_TMM_xx()
	4253	{
	4254	UINT8 tmp, imm;
	4255
	4256	RDOPARG( imm );
	4257	tmp = TMM + imm;
	4258
	4259	ZHC_ADD( tmp, TMM, 0 );
	4260	TMM = tmp;
	4261	SKIP_NC;
	4262	}
	4263
	4264	/* 64 a8: 0110 0100 1010 1000 xxxx xxxx */
	4265	void upd7810_device::GTI_ANM_xx()
	4266	{
	4267	UINT8 imm;
	4268	UINT16 tmp;
	4269
	4270	RDOPARG( imm );
	4271	tmp = ANM - imm - 1;
	4272	ZHC_SUB( tmp, ANM, 0 );
	4273
	4274	SKIP_NC;
	4275	}
	4276
	4277	/* 64 a9: 0110 0100 1010 1001 xxxx xxxx */
	4278	void upd7810_device::GTI_SMH_xx()
	4279	{
	4280	UINT8 imm;
	4281	UINT16 tmp;
	4282
	4283	RDOPARG( imm );
	4284	tmp = SMH - imm - 1;
	4285	ZHC_SUB( tmp, SMH, 0 );
	4286
	4287	SKIP_NC;
	4288	}
	4289
	4290	/* 64 ab: 0110 0100 1010 1011 xxxx xxxx */
	4291	void upd7810_device::GTI_EOM_xx()
	4292	{
	4293	/* only bits #1 and #5 can be read */
	4294	UINT8 eom = EOM & 0x22;
	4295	UINT8 imm;
	4296	UINT16 tmp;
	4297
	4298	RDOPARG( imm );
	4299	tmp = eom - imm - 1;
	4300	ZHC_SUB( tmp, eom, 0 );
	4301
	4302	SKIP_NC;
	4303	}
	4304
	4305	/* 64 ad: 0110 0100 1010 1101 xxxx xxxx */
	4306	void upd7810_device::GTI_TMM_xx()
	4307	{
	4308	UINT8 imm;
	4309	UINT16 tmp;
	4310
	4311	RDOPARG( imm );
	4312	tmp = TMM - imm - 1;
	4313	ZHC_SUB( tmp, TMM, 0 );
	4314
	4315	SKIP_NC;
	4316	}
	4317
	4318	/* 64 b0: 0110 0100 1011 0000 xxxx xxxx */
	4319	void upd7810_device::SUINB_ANM_xx()
	4320	{
	4321	UINT8 tmp, imm;
	4322
	4323	RDOPARG( imm );
	4324	tmp = ANM - imm;
	4325	ZHC_SUB( tmp, ANM, 0 );
	4326	ANM = tmp;
	4327	SKIP_NC;
	4328	}
	4329
	4330	/* 64 b1: 0110 0100 1011 0001 xxxx xxxx */
	4331	void upd7810_device::SUINB_SMH_xx()
	4332	{
	4333	UINT8 tmp, imm;
	4334
	4335	RDOPARG( imm );
	4336	tmp = SMH - imm;
	4337	ZHC_SUB( tmp, SMH, 0 );
	4338	SMH = tmp;
	4339	SKIP_NC;
	4340	}
	4341
	4342	/* 64 b3: 0110 0100 1011 0011 xxxx xxxx */
	4343	void upd7810_device::SUINB_EOM_xx()
	4344	{
	4345	/* only bits #1 and #5 can be read */
	4346	UINT8 eom = EOM & 0x22;
	4347	UINT8 tmp, imm;
	4348
	4349	RDOPARG( imm );
	4350	tmp = eom - imm;
	4351	ZHC_SUB( tmp, eom, 0 );
	4352	EOM = tmp;
	4353	SKIP_NC;
	4354	upd7810_write_EOM();
	4355	}
	4356
	4357	/* 64 b5: 0110 0100 1011 0101 xxxx xxxx */
	4358	void upd7810_device::SUINB_TMM_xx()
	4359	{
	4360	UINT8 tmp, imm;
	4361
	4362	RDOPARG( imm );
	4363	tmp = TMM - imm;
	4364	ZHC_SUB( tmp, TMM, 0 );
	4365	TMM = tmp;
	4366	SKIP_NC;
	4367	}
	4368
	4369	/* 64 b8: 0110 0100 1011 1000 xxxx xxxx */
	4370	void upd7810_device::LTI_ANM_xx()
	4371	{
	4372	UINT8 tmp, imm;
	4373
	4374	RDOPARG( imm );
	4375	tmp = ANM - imm;
	4376	ZHC_SUB( tmp, ANM, 0 );
	4377	SKIP_CY;
	4378	}
	4379
	4380	/* 64 b9: 0110 0100 1011 1001 xxxx xxxx */
	4381	void upd7810_device::LTI_SMH_xx()
	4382	{
	4383	UINT8 tmp, imm;
	4384
	4385	RDOPARG( imm );
	4386	tmp = SMH - imm;
	4387	ZHC_SUB( tmp, SMH, 0 );
	4388	SKIP_CY;
	4389	}
	4390
	4391	/* 64 bb: 0110 0100 1011 1011 xxxx xxxx */
	4392	void upd7810_device::LTI_EOM_xx()
	4393	{
	4394	/* only bits #1 and #5 can be read */
	4395	UINT8 eom = EOM & 0x22;
	4396	UINT8 tmp, imm;
	4397
	4398	RDOPARG( imm );
	4399	tmp = eom - imm;
	4400	ZHC_SUB( tmp, eom, 0 );
	4401	SKIP_CY;
	4402	}
	4403
	4404	/* 64 bd: 0110 0100 1011 1101 xxxx xxxx */
	4405	void upd7810_device::LTI_TMM_xx()
	4406	{
	4407	UINT8 tmp, imm;
	4408
	4409	RDOPARG( imm );
	4410	tmp = TMM - imm;
	4411	ZHC_SUB( tmp, TMM, 0 );
	4412	SKIP_CY;
	4413	}
	4414
	4415	/* 64 c0: 0110 0100 1100 0000 xxxx xxxx */
	4416	void upd7810_device::ADI_ANM_xx()
	4417	{
	4418	UINT8 tmp, imm;
	4419
	4420	RDOPARG( imm );
	4421	tmp = ANM + imm;
	4422
	4423	ZHC_ADD( tmp, ANM, 0 );
	4424	ANM = tmp;
	4425	}
	4426
	4427	/* 64 c1: 0110 0100 1100 0001 xxxx xxxx */
	4428	void upd7810_device::ADI_SMH_xx()
	4429	{
	4430	UINT8 tmp, imm;
	4431
	4432	RDOPARG( imm );
	4433	tmp = SMH + imm;
	4434
	4435	ZHC_ADD( tmp, SMH, 0 );
	4436	SMH = tmp;
	4437	}
	4438
	4439	/* 64 c3: 0110 0100 1100 0011 xxxx xxxx */
	4440	void upd7810_device::ADI_EOM_xx()
	4441	{
	4442	/* only bits #1 and #5 can be read */
	4443	UINT8 eom = EOM & 0x22;
	4444	UINT8 tmp, imm;
	4445
	4446	RDOPARG( imm );
	4447	tmp = eom + imm;
	4448
	4449	ZHC_ADD( tmp, eom, 0 );
	4450	EOM = tmp;
	4451	upd7810_write_EOM();
	4452	}
	4453
	4454	/* 64 c5: 0110 0100 1100 0101 xxxx xxxx */
	4455	void upd7810_device::ADI_TMM_xx()
	4456	{
	4457	UINT8 tmp, imm;
	4458
	4459	RDOPARG( imm );
	4460	tmp = TMM + imm;
	4461
	4462	ZHC_ADD( tmp, TMM, 0 );
	4463	TMM = tmp;
	4464	}
	4465
	4466	/* 64 c8: 0110 0100 1100 1000 xxxx xxxx */
	4467	void upd7810_device::ONI_ANM_xx()
	4468	{
	4469	UINT8 imm;
	4470
	4471	RDOPARG( imm );
	4472	if (ANM & imm)
	4473	PSW \|= SK;
	4474	}
	4475
	4476	/* 64 c9: 0110 0100 1100 1001 xxxx xxxx */
	4477	void upd7810_device::ONI_SMH_xx()
	4478	{
	4479	UINT8 imm;
	4480
	4481	RDOPARG( imm );
	4482	if (SMH & imm)
	4483	PSW \|= SK;
	4484	}
	4485
	4486	/* 64 cb: 0110 0100 1100 1011 xxxx xxxx */
	4487	void upd7810_device::ONI_EOM_xx()
	4488	{
	4489	/* only bits #1 and #5 can be read */
	4490	UINT8 eom = EOM & 0x22;
	4491	UINT8 imm;
	4492
	4493	RDOPARG( imm );
	4494	if (eom & imm)
	4495	PSW \|= SK;
	4496	}
	4497
	4498	/* 64 cd: 0110 0100 1100 1101 xxxx xxxx */
	4499	void upd7810_device::ONI_TMM_xx()
	4500	{
	4501	UINT8 imm;
	4502
	4503	RDOPARG( imm );
	4504	if (TMM & imm)
	4505	PSW \|= SK;
	4506	}
	4507
	4508	/* 64 d0: 0110 0100 1101 0000 xxxx xxxx */
	4509	void upd7810_device::ACI_ANM_xx()
	4510	{
	4511	UINT8 tmp, imm;
	4512
	4513	RDOPARG( imm );
	4514	tmp = ANM + imm + (PSW & CY);
	4515
	4516	ZHC_ADD( tmp, ANM, (PSW & CY) );
	4517	ANM = tmp;
	4518	}
	4519
	4520	/* 64 d1: 0110 0100 1101 0001 xxxx xxxx */
	4521	void upd7810_device::ACI_SMH_xx()
	4522	{
	4523	UINT8 tmp, imm;
	4524
	4525	RDOPARG( imm );
	4526	tmp = SMH + imm + (PSW & CY);
	4527
	4528	ZHC_ADD( tmp, SMH, (PSW & CY) );
	4529	SMH = tmp;
	4530	}
	4531
	4532	/* 64 d3: 0110 0100 1101 0011 xxxx xxxx */
	4533	void upd7810_device::ACI_EOM_xx()
	4534	{
	4535	/* only bits #1 and #5 can be read */
	4536	UINT8 eom = EOM & 0x22;
	4537	UINT8 tmp, imm;
	4538
	4539	RDOPARG( imm );
	4540	tmp = eom + imm + (PSW & CY);
	4541
	4542	ZHC_ADD( tmp, eom, (PSW & CY) );
	4543	EOM = tmp;
	4544	upd7810_write_EOM();
	4545	}
	4546
	4547	/* 64 d5: 0110 0100 1101 0101 xxxx xxxx */
	4548	void upd7810_device::ACI_TMM_xx()
	4549	{
	4550	UINT8 tmp, imm;
	4551
	4552	RDOPARG( imm );
	4553	tmp = TMM + imm + (PSW & CY);
	4554
	4555	ZHC_ADD( tmp, TMM, (PSW & CY) );
	4556	TMM = tmp;
	4557	}
	4558
	4559	/* 64 d8: 0110 0100 1101 1000 xxxx xxxx */
	4560	void upd7810_device::OFFI_ANM_xx()
	4561	{
	4562	UINT8 imm;
	4563
	4564	RDOPARG( imm );
	4565	if (0 == (ANM & imm))
	4566	PSW \|= SK;
	4567	}
	4568
	4569	/* 64 d9: 0110 0100 1101 1001 xxxx xxxx */
	4570	void upd7810_device::OFFI_SMH_xx()
	4571	{
	4572	UINT8 imm;
	4573
	4574	RDOPARG( imm );
	4575	if (0 == (SMH & imm))
	4576	PSW \|= SK;
	4577	}
	4578
	4579	/* 64 db: 0110 0100 1101 1011 xxxx xxxx */
	4580	void upd7810_device::OFFI_EOM_xx()
	4581	{
	4582	/* only bits #1 and #5 can be read */
	4583	UINT8 eom = EOM & 0x22;
	4584	UINT8 imm;
	4585
	4586	RDOPARG( imm );
	4587	if (0 == (eom & imm))
	4588	PSW \|= SK;
	4589	}
	4590
	4591	/* 64 dd: 0110 0100 1101 1101 xxxx xxxx */
	4592	void upd7810_device::OFFI_TMM_xx()
	4593	{
	4594	UINT8 imm;
	4595
	4596	RDOPARG( imm );
	4597	if (0 == (TMM & imm))
	4598	PSW \|= SK;
	4599	}
	4600
	4601	/* 64 e0: 0110 0100 1110 0000 xxxx xxxx */
	4602	void upd7810_device::SUI_ANM_xx()
	4603	{
	4604	UINT8 tmp, imm;
	4605
	4606	RDOPARG( imm );
	4607	tmp = ANM - imm;
	4608	ZHC_SUB( tmp, ANM, 0 );
	4609	ANM = tmp;
	4610	}
	4611
	4612	/* 64 e1: 0110 0100 1110 0001 xxxx xxxx */
	4613	void upd7810_device::SUI_SMH_xx()
	4614	{
	4615	UINT8 tmp, imm;
	4616
	4617	RDOPARG( imm );
	4618	tmp = SMH - imm;
	4619	ZHC_SUB( tmp, SMH, 0 );
	4620	SMH = tmp;
	4621	}
	4622
	4623	/* 64 e3: 0110 0100 1110 0011 xxxx xxxx */
	4624	void upd7810_device::SUI_EOM_xx()
	4625	{
	4626	/* only bits #1 and #5 can be read */
	4627	UINT8 eom = EOM & 0x22;
	4628	UINT8 tmp, imm;
	4629
	4630	RDOPARG( imm );
	4631	tmp = eom - imm;
	4632	ZHC_SUB( tmp, eom, 0 );
	4633	EOM = tmp;
	4634	upd7810_write_EOM();
	4635	}
	4636
	4637	/* 64 e5: 0110 0100 1110 0101 xxxx xxxx */
	4638	void upd7810_device::SUI_TMM_xx()
	4639	{
	4640	UINT8 tmp, imm;
	4641
	4642	RDOPARG( imm );
	4643	tmp = TMM - imm;
	4644	ZHC_SUB( tmp, TMM, 0 );
	4645	TMM = tmp;
	4646	}
	4647
	4648	/* 64 e8: 0110 0100 1110 1000 xxxx xxxx */
	4649	void upd7810_device::NEI_ANM_xx()
	4650	{
	4651	UINT8 tmp, imm;
	4652
	4653	RDOPARG( imm );
	4654	tmp = ANM - imm;
	4655	ZHC_SUB( tmp, ANM, 0 );
	4656	SKIP_NZ;
	4657	}
	4658
	4659	/* 64 e9: 0110 0100 1110 1001 xxxx xxxx */
	4660	void upd7810_device::NEI_SMH_xx()
	4661	{
	4662	UINT8 tmp, imm;
	4663
	4664	RDOPARG( imm );
	4665	tmp = SMH - imm;
	4666	ZHC_SUB( tmp, SMH, 0 );
	4667	SKIP_NZ;
	4668	}
	4669
	4670	/* 64 eb: 0110 0100 1110 1011 xxxx xxxx */
	4671	void upd7810_device::NEI_EOM_xx()
	4672	{
	4673	/* only bits #1 and #5 can be read */
	4674	UINT8 eom = EOM & 0x22;
	4675	UINT8 tmp, imm;
	4676
	4677	RDOPARG( imm );
	4678	tmp = eom - imm;
	4679	ZHC_SUB( tmp, eom, 0 );
	4680	SKIP_NZ;
	4681	}
	4682
	4683	/* 64 ed: 0110 0100 1110 1101 xxxx xxxx */
	4684	void upd7810_device::NEI_TMM_xx()
	4685	{
	4686	UINT8 tmp, imm;
	4687
	4688	RDOPARG( imm );
	4689	tmp = TMM - imm;
	4690	ZHC_SUB( tmp, TMM, 0 );
	4691	SKIP_NZ;
	4692	}
	4693
	4694	/* 64 f0: 0110 0100 1111 0000 xxxx xxxx */
	4695	void upd7810_device::SBI_ANM_xx()
	4696	{
	4697	UINT8 tmp, imm;
	4698
	4699	RDOPARG( imm );
	4700	tmp = ANM - imm - (PSW & CY);
	4701	ZHC_SUB( tmp, ANM, (PSW & CY) );
	4702	ANM = tmp;
	4703	}
	4704
	4705	/* 64 f1: 0110 0100 1111 0001 xxxx xxxx */
	4706	void upd7810_device::SBI_SMH_xx()
	4707	{
	4708	UINT8 tmp, imm;
	4709
	4710	RDOPARG( imm );
	4711	tmp = SMH - imm - (PSW & CY);
	4712	ZHC_SUB( tmp, SMH, (PSW & CY) );
	4713	SMH = tmp;
	4714	}
	4715
	4716	/* 64 f3: 0110 0100 1111 0011 xxxx xxxx */
	4717	void upd7810_device::SBI_EOM_xx()
	4718	{
	4719	/* only bits #1 and #5 can be read */
	4720	UINT8 eom = EOM & 0x22;
	4721	UINT8 tmp, imm;
	4722
	4723	RDOPARG( imm );
	4724	tmp = eom - imm - (PSW & CY);
	4725	ZHC_SUB( tmp, eom, (PSW & CY) );
	4726	EOM = tmp;
	4727	upd7810_write_EOM();
	4728	}
	4729
	4730	/* 64 f5: 0110 0100 1111 0101 xxxx xxxx */
	4731	void upd7810_device::SBI_TMM_xx()
	4732	{
	4733	UINT8 tmp, imm;
	4734
	4735	RDOPARG( imm );
	4736	tmp = TMM - imm - (PSW & CY);
	4737	ZHC_SUB( tmp, TMM, (PSW & CY) );
	4738	TMM = tmp;
	4739	}
	4740
	4741	/* 64 f8: 0110 0100 1111 1000 xxxx xxxx */
	4742	void upd7810_device::EQI_ANM_xx()
	4743	{
	4744	UINT8 tmp, imm;
	4745
	4746	RDOPARG( imm );
	4747	tmp = ANM - imm;
	4748	ZHC_SUB( tmp, ANM, 0 );
	4749	SKIP_Z;
	4750	}
	4751
	4752	/* 64 f9: 0110 0100 1111 1001 xxxx xxxx */
	4753	void upd7810_device::EQI_SMH_xx()
	4754	{
	4755	UINT8 tmp, imm;
	4756
	4757	RDOPARG( imm );
	4758	tmp = SMH - imm;
	4759	ZHC_SUB( tmp, SMH, 0 );
	4760	SKIP_Z;
	4761	}
	4762
	4763	/* 64 fb: 0110 0100 1111 1011 xxxx xxxx */
	4764	void upd7810_device::EQI_EOM_xx()
	4765	{
	4766	/* only bits #1 and #5 can be read */
	4767	UINT8 eom = EOM & 0x22;
	4768	UINT8 tmp, imm;
	4769
	4770	RDOPARG( imm );
	4771	tmp = eom - imm;
	4772	ZHC_SUB( tmp, eom, 0 );
	4773	SKIP_Z;
	4774	}
	4775
	4776	/* 64 fd: 0110 0100 1111 1101 xxxx xxxx */
	4777	void upd7810_device::EQI_TMM_xx()
	4778	{
	4779	UINT8 tmp, imm;
	4780
	4781	RDOPARG( imm );
	4782	tmp = TMM - imm;
	4783	ZHC_SUB( tmp, TMM, 0 );
	4784	SKIP_Z;
	4785	}
	4786
	4787	/* prefix 70 */
	4788	/* 70 0e: 0111 0000 0000 1110 llll llll hhhh hhhh */
	4789	void upd7810_device::SSPD_w()
	4790	{
	4791	PAIR ea;
	4792	ea.d = 0;
	4793
	4794	RDOPARG( ea.b.l );
	4795	RDOPARG( ea.b.h );
	4796	WM( ea.d, SPL );
	4797	WM( ea.d + 1, SPH );
	4798	}
	4799
	4800	/* 70 0f: 0111 0000 0000 1111 llll llll hhhh hhhh */
	4801	void upd7810_device::LSPD_w()
	4802	{
	4803	PAIR ea;
	4804	ea.d = 0;
	4805
	4806	RDOPARG( ea.b.l );
	4807	RDOPARG( ea.b.h );
	4808	SPL = RM( ea.d );
	4809	SPH = RM( ea.d + 1 );
	4810	}
	4811
	4812	/* 70 1e: 0111 0000 0001 1110 llll llll hhhh hhhh */
	4813	void upd7810_device::SBCD_w()
	4814	{
	4815	PAIR ea;
	4816	ea.d = 0;
	4817
	4818	RDOPARG( ea.b.l );
	4819	RDOPARG( ea.b.h );
	4820	WM( ea.d, C );
	4821	WM( ea.d + 1, B );
	4822	}
	4823
	4824	/* 70 1f: 0111 0000 0001 1111 llll llll hhhh hhhh */
	4825	void upd7810_device::LBCD_w()
	4826	{
	4827	PAIR ea;
	4828	ea.d = 0;
	4829
	4830	RDOPARG( ea.b.l );
	4831	RDOPARG( ea.b.h );
	4832	C = RM( ea.d );
	4833	B = RM( ea.d + 1 );
	4834	}
	4835
	4836	/* 70 2e: 0111 0000 0010 1110 llll llll hhhh hhhh */
	4837	void upd7810_device::SDED_w()
	4838	{
	4839	PAIR ea;
	4840	ea.d = 0;
	4841
	4842	RDOPARG( ea.b.l );
	4843	RDOPARG( ea.b.h );
	4844	WM( ea.d, E );
	4845	WM( ea.d + 1, D );
	4846	}
	4847
	4848	/* 70 2f: 0111 0000 0010 1111 llll llll hhhh hhhh */
	4849	void upd7810_device::LDED_w()
	4850	{
	4851	PAIR ea;
	4852	ea.d = 0;
	4853
	4854	RDOPARG( ea.b.l );
	4855	RDOPARG( ea.b.h );
	4856	E = RM( ea.d );
	4857	D = RM( ea.d + 1 );
	4858	}
	4859
	4860	/* 70 3e: 0111 0000 0011 1110 llll llll hhhh hhhh */
	4861	void upd7810_device::SHLD_w()
	4862	{
	4863	PAIR ea;
	4864	ea.d = 0;
	4865
	4866	RDOPARG( ea.b.l );
	4867	RDOPARG( ea.b.h );
	4868	WM( ea.d, L );
	4869	WM( ea.d + 1, H );
	4870	}
	4871
	4872	/* 70 3f: 0111 0000 0011 1111 llll llll hhhh hhhh */
	4873	void upd7810_device::LHLD_w()
	4874	{
	4875	PAIR ea;
	4876	ea.d = 0;
	4877
	4878	RDOPARG( ea.b.l );
	4879	RDOPARG( ea.b.h );
	4880	L = RM( ea.d );
	4881	H = RM( ea.d + 1 );
	4882	}
	4883
	4884	/* 70 41: 0111 0000 0100 0001 */
	4885	void upd7810_device::EADD_EA_A()
	4886	{
	4887	UINT16 tmp;
	4888	tmp = EA + A;
	4889	ZHC_ADD( tmp, EA, 0 );
	4890	EA = tmp;
	4891	}
	4892
	4893	/* 70 42: 0111 0000 0100 0010 */
	4894	void upd7810_device::EADD_EA_B()
	4895	{
	4896	UINT16 tmp;
	4897	tmp = EA + B;
	4898	ZHC_ADD( tmp, EA, 0 );
	4899	EA = tmp;
	4900	}
	4901
	4902	/* 70 43: 0111 0000 0100 0011 */
	4903	void upd7810_device::EADD_EA_C()
	4904	{
	4905	UINT16 tmp;
	4906	tmp = EA + C;
	4907	ZHC_ADD( tmp, EA, 0 );
	4908	EA = tmp;
	4909	}
	4910
	4911	/* 70 61: 0111 0000 0110 0001 */
	4912	void upd7810_device::ESUB_EA_A()
	4913	{
	4914	UINT16 tmp;
	4915	tmp = EA - A;
	4916	ZHC_SUB( tmp, EA, 0 );
	4917	EA = tmp;
	4918	}
	4919
	4920	/* 70 62: 0111 0000 0110 0010 */
	4921	void upd7810_device::ESUB_EA_B()
	4922	{
	4923	UINT16 tmp;
	4924	tmp = EA - B;
	4925	ZHC_SUB( tmp, EA, 0 );
	4926	EA = tmp;
	4927	}
	4928
	4929	/* 70 63: 0111 0000 0110 0011 */
	4930	void upd7810_device::ESUB_EA_C()
	4931	{
	4932	UINT16 tmp;
	4933	tmp = EA - C;
	4934	ZHC_SUB( tmp, EA, 0 );
	4935	EA = tmp;
	4936	}
	4937
	4938	/* 70 68: 0111 0000 0110 1000 llll llll hhhh hhhh */
	4939	void upd7810_device::MOV_V_w()
	4940	{
	4941	PAIR ea;
	4942	ea.d = 0;
	4943
	4944	RDOPARG( ea.b.l );
	4945	RDOPARG( ea.b.h );
	4946	V = RM( ea.d );
	4947	}
	4948
	4949	/* 70 69: 0111 0000 0110 1001 llll llll hhhh hhhh */
	4950	void upd7810_device::MOV_A_w()
	4951	{
	4952	PAIR ea;
	4953	ea.d = 0;
	4954
	4955	RDOPARG( ea.b.l );
	4956	RDOPARG( ea.b.h );
	4957	A = RM( ea.d );
	4958	}
	4959
	4960	/* 70 6a: 0111 0000 0110 1010 llll llll hhhh hhhh */
	4961	void upd7810_device::MOV_B_w()
	4962	{
	4963	PAIR ea;
	4964	ea.d = 0;
	4965
	4966	RDOPARG( ea.b.l );
	4967	RDOPARG( ea.b.h );
	4968	B = RM( ea.d );
	4969	}
	4970
	4971	/* 70 6b: 0111 0000 0110 1011 llll llll hhhh hhhh */
	4972	void upd7810_device::MOV_C_w()
	4973	{
	4974	PAIR ea;
	4975	ea.d = 0;
	4976
	4977	RDOPARG( ea.b.l );
	4978	RDOPARG( ea.b.h );
	4979	C = RM( ea.d );
	4980	}
	4981
	4982	/* 70 6c: 0111 0000 0110 1100 llll llll hhhh hhhh */
	4983	void upd7810_device::MOV_D_w()
	4984	{
	4985	PAIR ea;
	4986	ea.d = 0;
	4987
	4988	RDOPARG( ea.b.l );
	4989	RDOPARG( ea.b.h );
	4990	D = RM( ea.d );
	4991	}
	4992
	4993	/* 70 6d: 0111 0000 0110 1101 llll llll hhhh hhhh */
	4994	void upd7810_device::MOV_E_w()
	4995	{
	4996	PAIR ea;
	4997	ea.d = 0;
	4998
	4999	RDOPARG( ea.b.l );
	5000	RDOPARG( ea.b.h );
	5001	E = RM( ea.d );
	5002	}
	5003
	5004	/* 70 6e: 0111 0000 0110 1110 llll llll hhhh hhhh */
	5005	void upd7810_device::MOV_H_w()
	5006	{
	5007	PAIR ea;
	5008	ea.d = 0;
	5009
	5010	RDOPARG( ea.b.l );
	5011	RDOPARG( ea.b.h );
	5012	H = RM( ea.d );
	5013	}
	5014
	5015	/* 70 6f: 0111 0000 0110 1111 llll llll hhhh hhhh */
	5016	void upd7810_device::MOV_L_w()
	5017	{
	5018	PAIR ea;
	5019	ea.d = 0;
	5020
	5021	RDOPARG( ea.b.l );
	5022	RDOPARG( ea.b.h );
	5023	L = RM( ea.d );
	5024	}
	5025
	5026	/* 70 78: 0111 0000 0111 1000 llll llll hhhh hhhh */
	5027	void upd7810_device::MOV_w_V()
	5028	{
	5029	PAIR ea;
	5030	ea.d = 0;
	5031
	5032	RDOPARG( ea.b.l );
	5033	RDOPARG( ea.b.h );
	5034	WM( ea.d, V );
	5035	}
	5036
	5037	/* 70 79: 0111 0000 0111 1001 llll llll hhhh hhhh */
	5038	void upd7810_device::MOV_w_A()
	5039	{
	5040	PAIR ea;
	5041	ea.d = 0;
	5042
	5043	RDOPARG( ea.b.l );
	5044	RDOPARG( ea.b.h );
	5045	WM( ea.d, A );
	5046	}
	5047
	5048	/* 70 7a: 0111 0000 0111 1010 llll llll hhhh hhhh */
	5049	void upd7810_device::MOV_w_B()
	5050	{
	5051	PAIR ea;
	5052	ea.d = 0;
	5053
	5054	RDOPARG( ea.b.l );
	5055	RDOPARG( ea.b.h );
	5056	WM( ea.d, B );
	5057	}
	5058
	5059	/* 70 7b: 0111 0000 0111 1011 llll llll hhhh hhhh */
	5060	void upd7810_device::MOV_w_C()
	5061	{
	5062	PAIR ea;
	5063	ea.d = 0;
	5064
	5065	RDOPARG( ea.b.l );
	5066	RDOPARG( ea.b.h );
	5067	WM( ea.d, C );
	5068	}
	5069
	5070	/* 70 7c: 0111 0000 0111 1100 llll llll hhhh hhhh */
	5071	void upd7810_device::MOV_w_D()
	5072	{
	5073	PAIR ea;
	5074	ea.d = 0;
	5075
	5076	RDOPARG( ea.b.l );
	5077	RDOPARG( ea.b.h );
	5078	WM( ea.d, D );
	5079	}
	5080
	5081	/* 70 7d: 0111 0000 0111 1101 llll llll hhhh hhhh */
	5082	void upd7810_device::MOV_w_E()
	5083	{
	5084	PAIR ea;
	5085	ea.d = 0;
	5086
	5087	RDOPARG( ea.b.l );
	5088	RDOPARG( ea.b.h );
	5089	WM( ea.d, E );
	5090	}
	5091
	5092	/* 70 7e: 0111 0000 0111 1110 llll llll hhhh hhhh */
	5093	void upd7810_device::MOV_w_H()
	5094	{
	5095	PAIR ea;
	5096	ea.d = 0;
	5097
	5098	RDOPARG( ea.b.l );
	5099	RDOPARG( ea.b.h );
	5100	WM( ea.d, H );
	5101	}
	5102
	5103	/* 70 7f: 0111 0000 0111 1111 llll llll hhhh hhhh */
	5104	void upd7810_device::MOV_w_L()
	5105	{
	5106	PAIR ea;
	5107	ea.d = 0;
	5108
	5109	RDOPARG( ea.b.l );
	5110	RDOPARG( ea.b.h );
	5111	WM( ea.d, L );
	5112	}
	5113
	5114	/* 70 89: 0111 0000 1000 1001 */
	5115	void upd7810_device::ANAX_B()
	5116	{
	5117	A &= RM( BC );
	5118	SET_Z(A);
	5119	}
	5120
	5121	/* 70 8a: 0111 0000 1000 1010 */
	5122	void upd7810_device::ANAX_D()
	5123	{
	5124	A &= RM( DE );
	5125	SET_Z(A);
	5126	}
	5127
	5128	/* 70 8b: 0111 0000 1000 1011 */
	5129	void upd7810_device::ANAX_H()
	5130	{
	5131	A &= RM( HL );
	5132	SET_Z(A);
	5133	}
	5134
	5135	/* 70 8c: 0111 0000 1000 1100 */
	5136	void upd7810_device::ANAX_Dp()
	5137	{
	5138	A &= RM( DE );
	5139	DE++;
	5140	SET_Z(A);
	5141	}
	5142
	5143	/* 70 8d: 0111 0000 1000 1101 */
	5144	void upd7810_device::ANAX_Hp()
	5145	{
	5146	A &= RM( HL );
	5147	HL++;
	5148	SET_Z(A);
	5149	}
	5150
	5151	/* 70 8e: 0111 0000 1000 1110 */
	5152	void upd7810_device::ANAX_Dm()
	5153	{
	5154	A &= RM( DE );
	5155	DE--;
	5156	SET_Z(A);
	5157	}
	5158
	5159	/* 70 8f: 0111 0000 1000 1111 */
	5160	void upd7810_device::ANAX_Hm()
	5161	{
	5162	A &= RM( HL );
	5163	HL--;
	5164	SET_Z(A);
	5165	}
	5166
	5167	/* 70 91: 0111 0000 1001 0001 */
	5168	void upd7810_device::XRAX_B()
	5169	{
	5170	A ^= RM( BC );
	5171	SET_Z(A);
	5172	}
	5173
	5174	/* 70 92: 0111 0000 1001 0010 */
	5175	void upd7810_device::XRAX_D()
	5176	{
	5177	A ^= RM( DE );
	5178	SET_Z(A);
	5179	}
	5180
	5181	/* 70 93: 0111 0000 1001 0011 */
	5182	void upd7810_device::XRAX_H()
	5183	{
	5184	A ^= RM( HL );
	5185	SET_Z(A);
	5186	}
	5187
	5188	/* 70 94: 0111 0000 1001 0100 */
	5189	void upd7810_device::XRAX_Dp()
	5190	{
	5191	A ^= RM( DE );
	5192	DE++;
	5193	SET_Z(A);
	5194	}
	5195
	5196	/* 70 95: 0111 0000 1001 0101 */
	5197	void upd7810_device::XRAX_Hp()
	5198	{
	5199	A ^= RM( HL );
	5200	HL++;
	5201	SET_Z(A);
	5202	}
	5203
	5204	/* 70 96: 0111 0000 1001 0110 */
	5205	void upd7810_device::XRAX_Dm()
	5206	{
	5207	A ^= RM( DE );
	5208	DE--;
	5209	SET_Z(A);
	5210	}
	5211
	5212	/* 70 97: 0111 0000 1001 0111 */
	5213	void upd7810_device::XRAX_Hm()
	5214	{
	5215	A ^= RM( HL );
	5216	HL--;
	5217	SET_Z(A);
	5218	}
	5219
	5220	/* 70 99: 0111 0000 1001 1001 */
	5221	void upd7810_device::ORAX_B()
	5222	{
	5223	A \|= RM( BC );
	5224	SET_Z(A);
	5225	}
	5226
	5227	/* 70 9a: 0111 0000 1001 1010 */
	5228	void upd7810_device::ORAX_D()
	5229	{
	5230	A \|= RM( DE );
	5231	SET_Z(A);
	5232	}
	5233
	5234	/* 70 9b: 0111 0000 1001 1011 */
	5235	void upd7810_device::ORAX_H()
	5236	{
	5237	A \|= RM( HL );
	5238	SET_Z(A);
	5239	}
	5240
	5241	/* 70 9c: 0111 0000 1001 0100 */
	5242	void upd7810_device::ORAX_Dp()
	5243	{
	5244	A \|= RM( DE );
	5245	DE++;
	5246	SET_Z(A);
	5247	}
	5248
	5249	/* 70 9d: 0111 0000 1001 1101 */
	5250	void upd7810_device::ORAX_Hp()
	5251	{
	5252	A \|= RM( HL );
	5253	HL++;
	5254	SET_Z(A);
	5255	}
	5256
	5257	/* 70 9e: 0111 0000 1001 1110 */
	5258	void upd7810_device::ORAX_Dm()
	5259	{
	5260	A \|= RM( DE );
	5261	DE--;
	5262	SET_Z(A);
	5263	}
	5264
	5265	/* 70 9f: 0111 0000 1001 1111 */
	5266	void upd7810_device::ORAX_Hm()
	5267	{
	5268	A \|= RM( HL );
	5269	HL--;
	5270	SET_Z(A);
	5271	}
	5272
	5273	/* 70 a1: 0111 0000 1010 0001 */
	5274	void upd7810_device::ADDNCX_B()
	5275	{
	5276	UINT8 tmp = A + RM( BC );
	5277	ZHC_ADD( tmp, A, 0 );
	5278	A = tmp;
	5279	SKIP_NC;
	5280	}
	5281
	5282	/* 70 a2: 0111 0000 1010 0010 */
	5283	void upd7810_device::ADDNCX_D()
	5284	{
	5285	UINT8 tmp = A + RM( DE );
	5286	ZHC_ADD( tmp, A, 0 );
	5287	A = tmp;
	5288	SKIP_NC;
	5289	}
	5290
	5291	/* 70 a3: 0111 0000 1010 0011 */
	5292	void upd7810_device::ADDNCX_H()
	5293	{
	5294	UINT8 tmp = A + RM( HL );
	5295	ZHC_ADD( tmp, A, 0 );
	5296	A = tmp;
	5297	SKIP_NC;
	5298	}
	5299
	5300	/* 70 a4: 0111 0000 1010 0100 */
	5301	void upd7810_device::ADDNCX_Dp()
	5302	{
	5303	UINT8 tmp = A + RM( DE );
	5304	DE++;
	5305	ZHC_ADD( tmp, A, 0 );
	5306	A = tmp;
	5307	SKIP_NC;
	5308	}
	5309
	5310	/* 70 a5: 0111 0000 1010 0101 */
	5311	void upd7810_device::ADDNCX_Hp()
	5312	{
	5313	UINT8 tmp = A + RM( HL );
	5314	HL++;
	5315	ZHC_ADD( tmp, A, 0 );
	5316	A = tmp;
	5317	SKIP_NC;
	5318	}
	5319
	5320	/* 70 a6: 0111 0000 1010 0110 */
	5321	void upd7810_device::ADDNCX_Dm()
	5322	{
	5323	UINT8 tmp = A + RM( DE );
	5324	DE--;
	5325	ZHC_ADD( tmp, A, 0 );
	5326	A = tmp;
	5327	SKIP_NC;
	5328	}
	5329
	5330	/* 70 a7: 0111 0000 1010 0111 */
	5331	void upd7810_device::ADDNCX_Hm()
	5332	{
	5333	UINT8 tmp = A + RM( HL );
	5334	HL--;
	5335	ZHC_ADD( tmp, A, 0 );
	5336	A = tmp;
	5337	SKIP_NC;
	5338	}
	5339
	5340	/* 70 a9: 0111 0000 1010 1001 */
	5341	void upd7810_device::GTAX_B()
	5342	{
	5343	UINT16 tmp = A - RM( BC ) - 1;
	5344	ZHC_SUB( tmp, A, 0 );
	5345	SKIP_NC;
	5346	}
	5347
	5348	/* 70 aa: 0111 0000 1010 1010 */
	5349	void upd7810_device::GTAX_D()
	5350	{
	5351	UINT16 tmp = A - RM( DE ) - 1;
	5352	ZHC_SUB( tmp, A, 0 );
	5353	SKIP_NC;
	5354	}
	5355
	5356	/* 70 ab: 0111 0000 1010 1011 */
	5357	void upd7810_device::GTAX_H()
	5358	{
	5359	UINT16 tmp = A - RM( HL ) - 1;
	5360	ZHC_SUB( tmp, A, 0 );
	5361	SKIP_NC;
	5362	}
	5363
	5364	/* 70 ac: 0111 0000 1010 1100 */
	5365	void upd7810_device::GTAX_Dp()
	5366	{
	5367	UINT16 tmp = A - RM( DE ) - 1;
	5368	DE++;
	5369	ZHC_SUB( tmp, A, 0 );
	5370	SKIP_NC;
	5371	}
	5372
	5373	/* 70 ad: 0111 0000 1010 1101 */
	5374	void upd7810_device::GTAX_Hp()
	5375	{
	5376	UINT16 tmp = A - RM( HL ) - 1;
	5377	HL++;
	5378	ZHC_SUB( tmp, A, 0 );
	5379	SKIP_NC;
	5380	}
	5381
	5382	/* 70 ae: 0111 0000 1010 1110 */
	5383	void upd7810_device::GTAX_Dm()
	5384	{
	5385	UINT16 tmp = A - RM( DE ) - 1;
	5386	DE--;
	5387	ZHC_SUB( tmp, A, 0 );
	5388	SKIP_NC;
	5389	}
	5390
	5391	/* 70 af: 0111 0000 1010 1111 */
	5392	void upd7810_device::GTAX_Hm()
	5393	{
	5394	UINT16 tmp = A - RM( HL ) - 1;
	5395	HL--;
	5396	ZHC_SUB( tmp, A, 0 );
	5397	SKIP_NC;
	5398	}
	5399
	5400	/* 70 b1: 0111 0000 1011 0001 */
	5401	void upd7810_device::SUBNBX_B()
	5402	{
	5403	UINT8 tmp = A - RM( BC );
	5404	ZHC_SUB( tmp, A, 0 );
	5405	A = tmp;
	5406	SKIP_NC;
	5407	}
	5408
	5409	/* 70 b2: 0111 0000 1011 0010 */
	5410	void upd7810_device::SUBNBX_D()
	5411	{
	5412	UINT8 tmp = A - RM( DE );
	5413	ZHC_SUB( tmp, A, 0 );
	5414	A = tmp;
	5415	SKIP_NC;
	5416	}
	5417
	5418	/* 70 b3: 0111 0000 1011 0011 */
	5419	void upd7810_device::SUBNBX_H()
	5420	{
	5421	UINT8 tmp = A - RM( HL );
	5422	ZHC_SUB( tmp, A, 0 );
	5423	A = tmp;
	5424	SKIP_NC;
	5425	}
	5426
	5427	/* 70 b4: 0111 0000 1011 0100 */
	5428	void upd7810_device::SUBNBX_Dp()
	5429	{
	5430	UINT8 tmp = A - RM( DE );
	5431	DE++;
	5432	ZHC_SUB( tmp, A, 0 );
	5433	A = tmp;
	5434	SKIP_NC;
	5435	}
	5436
	5437	/* 70 b5: 0111 0000 1011 0101 */
	5438	void upd7810_device::SUBNBX_Hp()
	5439	{
	5440	UINT8 tmp = A - RM( HL );
	5441	HL++;
	5442	ZHC_SUB( tmp, A, 0 );
	5443	A = tmp;
	5444	SKIP_NC;
	5445	}
	5446
	5447	/* 70 b6: 0111 0000 1011 0110 */
	5448	void upd7810_device::SUBNBX_Dm()
	5449	{
	5450	UINT8 tmp = A - RM( DE );
	5451	DE--;
	5452	ZHC_SUB( tmp, A, 0 );
	5453	A = tmp;
	5454	SKIP_NC;
	5455	}
	5456
	5457	/* 70 b7: 0111 0000 1011 0111 */
	5458	void upd7810_device::SUBNBX_Hm()
	5459	{
	5460	UINT8 tmp = A - RM( HL );
	5461	HL--;
	5462	ZHC_SUB( tmp, A, 0 );
	5463	A = tmp;
	5464	SKIP_NC;
	5465	}
	5466
	5467	/* 70 b9: 0111 0000 1011 1001 */
	5468	void upd7810_device::LTAX_B()
	5469	{
	5470	UINT8 tmp = A - RM( BC );
	5471	ZHC_SUB( tmp, A, 0 );
	5472	SKIP_CY;
	5473	}
	5474
	5475	/* 70 ba: 0111 0000 1011 1010 */
	5476	void upd7810_device::LTAX_D()
	5477	{
	5478	UINT8 tmp = A - RM( DE );
	5479	ZHC_SUB( tmp, A, 0 );
	5480	SKIP_CY;
	5481	}
	5482
	5483	/* 70 bb: 0111 0000 1011 1011 */
	5484	void upd7810_device::LTAX_H()
	5485	{
	5486	UINT8 tmp = A - RM( HL );
	5487	ZHC_SUB( tmp, A, 0 );
	5488	SKIP_CY;
	5489	}
	5490
	5491	/* 70 bc: 0111 0000 1011 1100 */
	5492	void upd7810_device::LTAX_Dp()
	5493	{
	5494	UINT8 tmp = A - RM( DE );
	5495	DE++;
	5496	ZHC_SUB( tmp, A, 0 );
	5497	SKIP_CY;
	5498	}
	5499
	5500	/* 70 bd: 0111 0000 1011 1101 */
	5501	void upd7810_device::LTAX_Hp()
	5502	{
	5503	UINT8 tmp = A - RM( HL );
	5504	HL++;
	5505	ZHC_SUB( tmp, A, 0 );
	5506	SKIP_CY;
	5507	}
	5508
	5509	/* 70 be: 0111 0000 1011 1110 */
	5510	void upd7810_device::LTAX_Dm()
	5511	{
	5512	UINT8 tmp = A - RM( DE );
	5513	DE--;
	5514	ZHC_SUB( tmp, A, 0 );
	5515	SKIP_CY;
	5516	}
	5517
	5518	/* 70 bf: 0111 0000 1011 1111 */
	5519	void upd7810_device::LTAX_Hm()
	5520	{
	5521	UINT8 tmp = A - RM( HL );
	5522	HL--;
	5523	ZHC_SUB( tmp, A, 0 );
	5524	SKIP_CY;
	5525	}
	5526
	5527	/* 70 c1: 0111 0000 1100 0001 */
	5528	void upd7810_device::ADDX_B()
	5529	{
	5530	UINT8 tmp = A + RM( BC );
	5531	ZHC_ADD( tmp, A, 0 );
	5532	A = tmp;
	5533	}
	5534
	5535	/* 70 c2: 0111 0000 1100 0010 */
	5536	void upd7810_device::ADDX_D()
	5537	{
	5538	UINT8 tmp = A + RM( DE );
	5539	ZHC_ADD( tmp, A, 0 );
	5540	A = tmp;
	5541	}
	5542
	5543	/* 70 c3: 0111 0000 1100 0011 */
	5544	void upd7810_device::ADDX_H()
	5545	{
	5546	UINT8 tmp = A + RM( HL );
	5547	ZHC_ADD( tmp, A, 0 );
	5548	A = tmp;
	5549	}
	5550
	5551	/* 70 c4: 0111 0000 1100 0100 */
	5552	void upd7810_device::ADDX_Dp()
	5553	{
	5554	UINT8 tmp = A + RM( DE );
	5555	DE++;
	5556	ZHC_ADD( tmp, A, 0 );
	5557	A = tmp;
	5558	}
	5559
	5560	/* 70 c5: 0111 0000 1100 0101 */
	5561	void upd7810_device::ADDX_Hp()
	5562	{
	5563	UINT8 tmp = A + RM( HL );
	5564	HL++;
	5565	ZHC_ADD( tmp, A, 0 );
	5566	A = tmp;
	5567	}
	5568
	5569	/* 70 c6: 0111 0000 1100 0110 */
	5570	void upd7810_device::ADDX_Dm()
	5571	{
	5572	UINT8 tmp = A + RM( DE );
	5573	DE--;
	5574	ZHC_ADD( tmp, A, 0 );
	5575	A = tmp;
	5576	}
	5577
	5578	/* 70 c7: 0111 0000 1100 0111 */
	5579	void upd7810_device::ADDX_Hm()
	5580	{
	5581	UINT8 tmp = A + RM( HL );
	5582	HL--;
	5583	ZHC_ADD( tmp, A, 0 );
	5584	A = tmp;
	5585	}
	5586
	5587	/* 70 c9: 0111 0000 1100 1001 */
	5588	void upd7810_device::ONAX_B()
	5589	{
	5590	if (A & RM( BC ))
	5591	PSW = (PSW & ~Z) \| SK;
	5592	else
	5593	PSW \|= Z;
	5594	}
	5595
	5596	/* 70 ca: 0111 0000 1100 1010 */
	5597	void upd7810_device::ONAX_D()
	5598	{
	5599	if (A & RM( DE ))
	5600	PSW = (PSW & ~Z) \| SK;
	5601	else
	5602	PSW \|= Z;
	5603	}
	5604
	5605	/* 70 cb: 0111 0000 1100 1011 */
	5606	void upd7810_device::ONAX_H()
	5607	{
	5608	if (A & RM( HL ))
	5609	PSW = (PSW & ~Z) \| SK;
	5610	else
	5611	PSW \|= Z;
	5612	}
	5613
	5614	/* 70 cc: 0111 0000 1100 1100 */
	5615	void upd7810_device::ONAX_Dp()
	5616	{
	5617	if (A & RM( DE ))
	5618	PSW = (PSW & ~Z) \| SK;
	5619	else
	5620	PSW \|= Z;
	5621	DE++;
	5622	}
	5623
	5624	/* 70 cd: 0111 0000 1100 1101 */
	5625	void upd7810_device::ONAX_Hp()
	5626	{
	5627	if (A & RM( HL ))
	5628	PSW = (PSW & ~Z) \| SK;
	5629	else
	5630	PSW \|= Z;
	5631	HL++;
	5632	}
	5633
	5634	/* 70 ce: 0111 0000 1100 1110 */
	5635	void upd7810_device::ONAX_Dm()
	5636	{
	5637	if (A & RM( DE ))
	5638	PSW = (PSW & ~Z) \| SK;
	5639	else
	5640	PSW \|= Z;
	5641	DE--;
	5642	}
	5643
	5644	/* 70 cf: 0111 0000 1100 1111 */
	5645	void upd7810_device::ONAX_Hm()
	5646	{
	5647	if (A & RM( HL ))
	5648	PSW = (PSW & ~Z) \| SK;
	5649	else
	5650	PSW \|= Z;
	5651	HL--;
	5652	}
	5653
	5654	/* 70 d1: 0111 0000 1101 0001 */
	5655	void upd7810_device::ADCX_B()
	5656	{
	5657	UINT8 tmp = A + RM( BC ) + (PSW & CY);
	5658	ZHC_ADD( tmp, A, 0 );
	5659	A = tmp;
	5660	}
	5661
	5662	/* 70 d2: 0111 0000 1101 0010 */
	5663	void upd7810_device::ADCX_D()
	5664	{
	5665	UINT8 tmp = A + RM( DE ) + (PSW & CY);
	5666	ZHC_ADD( tmp, A, 0 );
	5667	A = tmp;
	5668	}
	5669
	5670	/* 70 d3: 0111 0000 1101 0011 */
	5671	void upd7810_device::ADCX_H()
	5672	{
	5673	UINT8 tmp = A + RM( HL ) + (PSW & CY);
	5674	ZHC_ADD( tmp, A, 0 );
	5675	A = tmp;
	5676	}
	5677
	5678	/* 70 d4: 0111 0000 1101 0100 */
	5679	void upd7810_device::ADCX_Dp()
	5680	{
	5681	UINT8 tmp = A + RM( DE ) + (PSW & CY);
	5682	DE++;
	5683	ZHC_ADD( tmp, A, 0 );
	5684	A = tmp;
	5685	}
	5686
	5687	/* 70 d5: 0111 0000 1101 0101 */
	5688	void upd7810_device::ADCX_Hp()
	5689	{
	5690	UINT8 tmp = A + RM( HL ) + (PSW & CY);
	5691	HL++;
	5692	ZHC_ADD( tmp, A, 0 );
	5693	A = tmp;
	5694	}
	5695
	5696	/* 70 d6: 0111 0000 1101 0110 */
	5697	void upd7810_device::ADCX_Dm()
	5698	{
	5699	UINT8 tmp = A + RM( DE ) + (PSW & CY);
	5700	DE--;
	5701	ZHC_ADD( tmp, A, 0 );
	5702	A = tmp;
	5703	}
	5704
	5705	/* 70 d7: 0111 0000 1101 0111 */
	5706	void upd7810_device::ADCX_Hm()
	5707	{
	5708	UINT8 tmp = A + RM( HL ) + (PSW & CY);
	5709	HL--;
	5710	ZHC_ADD( tmp, A, 0 );
	5711	A = tmp;
	5712	}
	5713
	5714	/* 70 d9: 0111 0000 1101 1001 */
	5715	void upd7810_device::OFFAX_B()
	5716	{
	5717	if ( A & RM( BC ) )
	5718	PSW &= ~Z;
	5719	else
	5720	PSW = PSW \| Z \| SK;
	5721	}
	5722
	5723	/* 70 da: 0111 0000 1101 1010 */
	5724	void upd7810_device::OFFAX_D()
	5725	{
	5726	if ( A & RM( DE ) )
	5727	PSW &= ~Z;
	5728	else
	5729	PSW = PSW \| Z \| SK;
	5730	}
	5731
	5732	/* 70 db: 0111 0000 1101 1011 */
	5733	void upd7810_device::OFFAX_H()
	5734	{
	5735	if ( A & RM( HL ) )
	5736	PSW &= ~Z;
	5737	else
	5738	PSW = PSW \| Z \| SK;
	5739	}
	5740
	5741	/* 70 dc: 0111 0000 1101 1100 */
	5742	void upd7810_device::OFFAX_Dp()
	5743	{
	5744	if ( A & RM( DE ) )
	5745	PSW &= ~Z;
	5746	else
	5747	PSW = PSW \| Z \| SK;
	5748	DE++;
	5749	}
	5750
	5751	/* 70 dd: 0111 0000 1101 1101 */
	5752	void upd7810_device::OFFAX_Hp()
	5753	{
	5754	if ( A & RM( HL ) )
	5755	PSW &= ~Z;
	5756	else
	5757	PSW = PSW \| Z \| SK;
	5758	HL++;
	5759	}
	5760
	5761	/* 70 de: 0111 0000 1101 1110 */
	5762	void upd7810_device::OFFAX_Dm()
	5763	{
	5764	if ( A & RM( DE ) )
	5765	PSW &= ~Z;
	5766	else
	5767	PSW = PSW \| Z \| SK;
	5768	DE--;
	5769	}
	5770
	5771	/* 70 df: 0111 0000 1101 1111 */
	5772	void upd7810_device::OFFAX_Hm()
	5773	{
	5774	if ( A & RM( HL ) )
	5775	PSW &= ~Z;
	5776	else
	5777	PSW = PSW \| Z \| SK;
	5778	HL--;
	5779	}
	5780
	5781	/* 70 e1: 0111 0000 1110 0001 */
	5782	void upd7810_device::SUBX_B()
	5783	{
	5784	UINT8 tmp = A - RM( BC );
	5785	ZHC_SUB( tmp, A, 0 );
	5786	A = tmp;
	5787	}
	5788
	5789	/* 70 e2: 0111 0000 1110 0010 */
	5790	void upd7810_device::SUBX_D()
	5791	{
	5792	UINT8 tmp = A - RM( DE );
	5793	ZHC_SUB( tmp, A, 0 );
	5794	A = tmp;
	5795	}
	5796
	5797	/* 70 e3: 0111 0000 1110 0011 */
	5798	void upd7810_device::SUBX_H()
	5799	{
	5800	UINT8 tmp = A - RM( HL );
	5801	ZHC_SUB( tmp, A, 0 );
	5802	A = tmp;
	5803	}
	5804
	5805	/* 70 e4: 0111 0000 1110 0100 */
	5806	void upd7810_device::SUBX_Dp()
	5807	{
	5808	UINT8 tmp = A - RM( DE );
	5809	ZHC_SUB( tmp, A, 0 );
	5810	A = tmp;
	5811	DE++;
	5812	}
	5813
	5814	/* 70 e5: 0111 0000 1110 0101 */
	5815	void upd7810_device::SUBX_Hp()
	5816	{
	5817	UINT8 tmp = A - RM( HL );
	5818	ZHC_SUB( tmp, A, 0 );
	5819	A = tmp;
	5820	HL++;
	5821	}
	5822
	5823	/* 70 e6: 0111 0000 1110 0110 */
	5824	void upd7810_device::SUBX_Dm()
	5825	{
	5826	UINT8 tmp = A - RM( DE );
	5827	ZHC_SUB( tmp, A, 0 );
	5828	A = tmp;
	5829	DE--;
	5830	}
	5831
	5832	/* 70 e7: 0111 0000 1110 0111 */
	5833	void upd7810_device::SUBX_Hm()
	5834	{
	5835	UINT8 tmp = A - RM( HL );
	5836	ZHC_SUB( tmp, A, 0 );
	5837	A = tmp;
	5838	HL--;
	5839	}
	5840
	5841	/* 70 e9: 0111 0000 1110 1001 */
	5842	void upd7810_device::NEAX_B()
	5843	{
	5844	UINT8 tmp = A - RM( BC );
	5845	ZHC_SUB( tmp, A, 0 );
	5846	SKIP_NZ;
	5847	}
	5848
	5849	/* 70 ea: 0111 0000 1110 1010 */
	5850	void upd7810_device::NEAX_D()
	5851	{
	5852	UINT8 tmp = A - RM( DE );
	5853	ZHC_SUB( tmp, A, 0 );
	5854	SKIP_NZ;
	5855	}
	5856
	5857	/* 70 eb: 0111 0000 1110 1011 */
	5858	void upd7810_device::NEAX_H()
	5859	{
	5860	UINT8 tmp = A - RM( HL );
	5861	ZHC_SUB( tmp, A, 0 );
	5862	SKIP_NZ;
	5863	}
	5864
	5865	/* 70 ec: 0111 0000 1110 1100 */
	5866	void upd7810_device::NEAX_Dp()
	5867	{
	5868	UINT8 tmp = A - RM( DE );
	5869	DE++;
	5870	ZHC_SUB( tmp, A, 0 );
	5871	SKIP_NZ;
	5872	}
	5873
	5874	/* 70 ed: 0111 0000 1110 1101 */
	5875	void upd7810_device::NEAX_Hp()
	5876	{
	5877	UINT8 tmp = A - RM( HL );
	5878	HL++;
	5879	ZHC_SUB( tmp, A, 0 );
	5880	SKIP_NZ;
	5881	}
	5882
	5883	/* 70 ee: 0111 0000 1110 1110 */
	5884	void upd7810_device::NEAX_Dm()
	5885	{
	5886	UINT8 tmp = A - RM( DE );
	5887	DE--;
	5888	ZHC_SUB( tmp, A, 0 );
	5889	SKIP_NZ;
	5890	}
	5891
	5892	/* 70 ef: 0111 0000 1110 1111 */
	5893	void upd7810_device::NEAX_Hm()
	5894	{
	5895	UINT8 tmp = A - RM( HL );
	5896	HL--;
	5897	ZHC_SUB( tmp, A, 0 );
	5898	SKIP_NZ;
	5899	}
	5900
	5901	/* 70 f1: 0111 0000 1111 0001 */
	5902	void upd7810_device::SBBX_B()
	5903	{
	5904	UINT8 tmp = A - RM( BC ) - (PSW & CY);
	5905	ZHC_SUB( tmp, A, (PSW & CY) );
	5906	A = tmp;
	5907	}
	5908
	5909	/* 70 f2: 0111 0000 1111 0010 */
	5910	void upd7810_device::SBBX_D()
	5911	{
	5912	UINT8 tmp = A - RM( DE ) - (PSW & CY);
	5913	ZHC_SUB( tmp, A, (PSW & CY) );
	5914	A = tmp;
	5915	}
	5916
	5917	/* 70 f3: 0111 0000 1111 0011 */
	5918	void upd7810_device::SBBX_H()
	5919	{
	5920	UINT8 tmp = A - RM( HL ) - (PSW & CY);
	5921	ZHC_SUB( tmp, A, (PSW & CY) );
	5922	A = tmp;
	5923	}
	5924
	5925	/* 70 f4: 0111 0000 1111 0100 */
	5926	void upd7810_device::SBBX_Dp()
	5927	{
	5928	UINT8 tmp = A - RM( DE ) - (PSW & CY);
	5929	DE++;
	5930	ZHC_SUB( tmp, A, (PSW & CY) );
	5931	A = tmp;
	5932	}
	5933
	5934	/* 70 f5: 0111 0000 1111 0101 */
	5935	void upd7810_device::SBBX_Hp()
	5936	{
	5937	UINT8 tmp = A - RM( HL ) - (PSW & CY);
	5938	HL++;
	5939	ZHC_SUB( tmp, A, (PSW & CY) );
	5940	A = tmp;
	5941	}
	5942
	5943	/* 70 f6: 0111 0000 1111 0110 */
	5944	void upd7810_device::SBBX_Dm()
	5945	{
	5946	UINT8 tmp = A - RM( DE ) - (PSW & CY);
	5947	DE--;
	5948	ZHC_SUB( tmp, A, (PSW & CY) );
	5949	A = tmp;
	5950	}
	5951
	5952	/* 70 f7: 0111 0000 1111 0111 */
	5953	void upd7810_device::SBBX_Hm()
	5954	{
	5955	UINT8 tmp = A - RM( HL ) - (PSW & CY);
	5956	HL--;
	5957	ZHC_SUB( tmp, A, (PSW & CY) );
	5958	A = tmp;
	5959	}
	5960
	5961	/* 70 f9: 0111 0000 1111 1001 */
	5962	void upd7810_device::EQAX_B()
	5963	{
	5964	UINT8 tmp = A - RM( BC );
	5965	ZHC_SUB( tmp, A, 0 );
	5966	SKIP_Z;
	5967	}
	5968
	5969	/* 70 fa: 0111 0000 1111 1010 */
	5970	void upd7810_device::EQAX_D()
	5971	{
	5972	UINT8 tmp = A - RM( DE );
	5973	ZHC_SUB( tmp, A, 0 );
	5974	SKIP_Z;
	5975	}
	5976
	5977	/* 70 fb: 0111 0000 1111 1011 */
	5978	void upd7810_device::EQAX_H()
	5979	{
	5980	UINT8 tmp = A - RM( HL );
	5981	ZHC_SUB( tmp, A, 0 );
	5982	SKIP_Z;
	5983	}
	5984
	5985	/* 70 fc: 0111 0000 1111 1100 */
	5986	void upd7810_device::EQAX_Dp()
	5987	{
	5988	UINT8 tmp = A - RM( DE );
	5989	DE++;
	5990	ZHC_SUB( tmp, A, 0 );
	5991	SKIP_Z;
	5992	}
	5993
	5994	/* 70 fd: 0111 0000 1111 1101 */
	5995	void upd7810_device::EQAX_Hp()
	5996	{
	5997	UINT8 tmp = A - RM( HL );
	5998	HL++;
	5999	ZHC_SUB( tmp, A, 0 );
	6000	SKIP_Z;
	6001	}
	6002
	6003	/* 70 fe: 0111 0000 1111 1110 */
	6004	void upd7810_device::EQAX_Dm()
	6005	{
	6006	UINT8 tmp = A - RM( DE );
	6007	DE--;
	6008	ZHC_SUB( tmp, A, 0 );
	6009	SKIP_Z;
	6010	}
	6011
	6012	/* 70 ff: 0111 0000 1111 1111 */
	6013	void upd7810_device::EQAX_Hm()
	6014	{
	6015	UINT8 tmp = A - RM( HL );
	6016	HL--;
	6017	ZHC_SUB( tmp, A, 0 );
	6018	SKIP_Z;
	6019	}
	6020
	6021	/* prefix 74 */
	6022	/* 74 08: 0111 0100 0000 1000 xxxx xxxx */
	6023	void upd7810_device::ANI_V_xx()
	6024	{
	6025	UINT8 imm;
	6026	RDOPARG( imm );
	6027	V &= imm;
	6028	SET_Z(V);
	6029	}
	6030
	6031	/* 74 09: 0111 0100 0000 1001 xxxx xxxx */
	6032	void upd7810_device::ANI_A_xx()
	6033	{
	6034	UINT8 imm;
	6035	RDOPARG( imm );
	6036	A &= imm;
	6037	SET_Z(A);
	6038	}
	6039
	6040	/* 74 0a: 0111 0100 0000 1010 xxxx xxxx */
	6041	void upd7810_device::ANI_B_xx()
	6042	{
	6043	UINT8 imm;
	6044	RDOPARG( imm );
	6045	B &= imm;
	6046	SET_Z(B);
	6047	}
	6048
	6049	/* 74 0b: 0111 0100 0000 1011 xxxx xxxx */
	6050	void upd7810_device::ANI_C_xx()
	6051	{
	6052	UINT8 imm;
	6053	RDOPARG( imm );
	6054	C &= imm;
	6055	SET_Z(C);
	6056	}
	6057
	6058	/* 74 0c: 0111 0100 0000 1100 xxxx xxxx */
	6059	void upd7810_device::ANI_D_xx()
	6060	{
	6061	UINT8 imm;
	6062	RDOPARG( imm );
	6063	D &= imm;
	6064	SET_Z(D);
	6065	}
	6066
	6067	/* 74 0d: 0111 0100 0000 1101 xxxx xxxx */
	6068	void upd7810_device::ANI_E_xx()
	6069	{
	6070	UINT8 imm;
	6071	RDOPARG( imm );
	6072	E &= imm;
	6073	SET_Z(E);
	6074	}
	6075
	6076	/* 74 0e: 0111 0100 0000 1110 xxxx xxxx */
	6077	void upd7810_device::ANI_H_xx()
	6078	{
	6079	UINT8 imm;
	6080	RDOPARG( imm );
	6081	H &= imm;
	6082	SET_Z(H);
	6083	}
	6084
	6085	/* 74 0f: 0111 0100 0000 1111 xxxx xxxx */
	6086	void upd7810_device::ANI_L_xx()
	6087	{
	6088	UINT8 imm;
	6089	RDOPARG( imm );
	6090	L &= imm;
	6091	SET_Z(L);
	6092	}
	6093
	6094	/* 74 10: 0111 0100 0001 0000 xxxx xxxx */
	6095	void upd7810_device::XRI_V_xx()
	6096	{
	6097	UINT8 imm;
	6098	RDOPARG( imm );
	6099	V ^= imm;
	6100	SET_Z(V);
	6101	}
	6102
	6103	/* 74 11: 0111 0100 0001 0001 xxxx xxxx */
	6104	void upd7810_device::XRI_A_xx()
	6105	{
	6106	UINT8 imm;
	6107	RDOPARG( imm );
	6108	A ^= imm;
	6109	SET_Z(A);
	6110	}
	6111
	6112	/* 74 12: 0111 0100 0001 0010 xxxx xxxx */
	6113	void upd7810_device::XRI_B_xx()
	6114	{
	6115	UINT8 imm;
	6116	RDOPARG( imm );
	6117	B ^= imm;
	6118	SET_Z(B);
	6119	}
	6120
	6121	/* 74 13: 0111 0100 0001 0011 xxxx xxxx */
	6122	void upd7810_device::XRI_C_xx()
	6123	{
	6124	UINT8 imm;
	6125	RDOPARG( imm );
	6126	C ^= imm;
	6127	SET_Z(C);
	6128	}
	6129
	6130	/* 74 14: 0111 0100 0001 0100 xxxx xxxx */
	6131	void upd7810_device::XRI_D_xx()
	6132	{
	6133	UINT8 imm;
	6134	RDOPARG( imm );
	6135	D ^= imm;
	6136	SET_Z(D);
	6137	}
	6138
	6139	/* 74 15: 0111 0100 0001 0101 xxxx xxxx */
	6140	void upd7810_device::XRI_E_xx()
	6141	{
	6142	UINT8 imm;
	6143	RDOPARG( imm );
	6144	E ^= imm;
	6145	SET_Z(E);
	6146	}
	6147
	6148	/* 74 16: 0111 0100 0001 0110 xxxx xxxx */
	6149	void upd7810_device::XRI_H_xx()
	6150	{
	6151	UINT8 imm;
	6152	RDOPARG( imm );
	6153	H ^= imm;
	6154	SET_Z(H);
	6155	}
	6156
	6157	/* 74 17: 0111 0100 0001 0111 xxxx xxxx */
	6158	void upd7810_device::XRI_L_xx()
	6159	{
	6160	UINT8 imm;
	6161	RDOPARG( imm );
	6162	L ^= imm;
	6163	SET_Z(L);
	6164	}
	6165
	6166	/* 74 18: 0111 0100 0001 1000 xxxx xxxx */
	6167	void upd7810_device::ORI_V_xx()
	6168	{
	6169	UINT8 imm;
	6170	RDOPARG( imm );
	6171	V \|= imm;
	6172	SET_Z(V);
	6173	}
	6174
	6175	/* 74 19: 0111 0100 0001 1001 xxxx xxxx */
	6176	void upd7810_device::ORI_A_xx()
	6177	{
	6178	UINT8 imm;
	6179	RDOPARG( imm );
	6180	A \|= imm;
	6181	SET_Z(A);
	6182	}
	6183
	6184	/* 74 1a: 0111 0100 0001 1010 xxxx xxxx */
	6185	void upd7810_device::ORI_B_xx()
	6186	{
	6187	UINT8 imm;
	6188	RDOPARG( imm );
	6189	B \|= imm;
	6190	SET_Z(B);
	6191	}
	6192
	6193	/* 74 1b: 0111 0100 0001 1011 xxxx xxxx */
	6194	void upd7810_device::ORI_C_xx()
	6195	{
	6196	UINT8 imm;
	6197	RDOPARG( imm );
	6198	C \|= imm;
	6199	SET_Z(C);
	6200	}
	6201
	6202	/* 74 1c: 0111 0100 0001 1100 xxxx xxxx */
	6203	void upd7810_device::ORI_D_xx()
	6204	{
	6205	UINT8 imm;
	6206	RDOPARG( imm );
	6207	D \|= imm;
	6208	SET_Z(D);
	6209	}
	6210
	6211	/* 74 1d: 0111 0100 0001 1101 xxxx xxxx */
	6212	void upd7810_device::ORI_E_xx()
	6213	{
	6214	UINT8 imm;
	6215	RDOPARG( imm );
	6216	E \|= imm;
	6217	SET_Z(E);
	6218	}
	6219
	6220	/* 74 1e: 0111 0100 0001 1110 xxxx xxxx */
	6221	void upd7810_device::ORI_H_xx()
	6222	{
	6223	UINT8 imm;
	6224	RDOPARG( imm );
	6225	H \|= imm;
	6226	SET_Z(H);
	6227	}
	6228
	6229	/* 74 1f: 0111 0100 0001 1111 xxxx xxxx */
	6230	void upd7810_device::ORI_L_xx()
	6231	{
	6232	UINT8 imm;
	6233	RDOPARG( imm );
	6234	L \|= imm;
	6235	SET_Z(L);
	6236	}
	6237
	6238	/* 74 20: 0111 0100 0010 0000 xxxx xxxx */
	6239	void upd7810_device::ADINC_V_xx()
	6240	{
	6241	UINT8 tmp, imm;
	6242
	6243	RDOPARG( imm );
	6244	tmp = V + imm;
	6245
	6246	ZHC_ADD( tmp, V, 0 );
	6247	V = tmp;
	6248	SKIP_NC;
	6249	}
	6250
	6251	/* 74 21: 0111 0100 0010 0001 xxxx xxxx */
	6252	void upd7810_device::ADINC_A_xx()
	6253	{
	6254	UINT8 tmp, imm;
	6255
	6256	RDOPARG( imm );
	6257	tmp = A + imm;
	6258
	6259	ZHC_ADD( tmp, A, 0 );
	6260	A = tmp;
	6261	SKIP_NC;
	6262	}
	6263
	6264	/* 74 22: 0111 0100 0010 0010 xxxx xxxx */
	6265	void upd7810_device::ADINC_B_xx()
	6266	{
	6267	UINT8 tmp, imm;
	6268
	6269	RDOPARG( imm );
	6270	tmp = B + imm;
	6271
	6272	ZHC_ADD( tmp, B, 0 );
	6273	B = tmp;
	6274	SKIP_NC;
	6275	}
	6276
	6277	/* 74 23: 0111 0100 0010 0011 xxxx xxxx */
	6278	void upd7810_device::ADINC_C_xx()
	6279	{
	6280	UINT8 tmp, imm;
	6281
	6282	RDOPARG( imm );
	6283	tmp = C + imm;
	6284
	6285	ZHC_ADD( tmp, C, 0 );
	6286	C = tmp;
	6287	SKIP_NC;
	6288	}
	6289
	6290	/* 74 24: 0111 0100 0010 0100 xxxx xxxx */
	6291	void upd7810_device::ADINC_D_xx()
	6292	{
	6293	UINT8 tmp, imm;
	6294
	6295	RDOPARG( imm );
	6296	tmp = D + imm;
	6297
	6298	ZHC_ADD( tmp, D, 0 );
	6299	D = tmp;
	6300	SKIP_NC;
	6301	}
	6302
	6303	/* 74 25: 0111 0100 0010 0101 xxxx xxxx */
	6304	void upd7810_device::ADINC_E_xx()
	6305	{
	6306	UINT8 tmp, imm;
	6307
	6308	RDOPARG( imm );
	6309	tmp = E + imm;
	6310
	6311	ZHC_ADD( tmp, E, 0 );
	6312	E = tmp;
	6313	SKIP_NC;
	6314	}
	6315
	6316	/* 74 26: 0111 0100 0010 0110 xxxx xxxx */
	6317	void upd7810_device::ADINC_H_xx()
	6318	{
	6319	UINT8 tmp, imm;
	6320
	6321	RDOPARG( imm );
	6322	tmp = H + imm;
	6323
	6324	ZHC_ADD( tmp, H, 0 );
	6325	H = tmp;
	6326	SKIP_NC;
	6327	}
	6328
	6329	/* 74 27: 0111 0100 0010 0111 xxxx xxxx */
	6330	void upd7810_device::ADINC_L_xx()
	6331	{
	6332	UINT8 tmp, imm;
	6333
	6334	RDOPARG( imm );
	6335	tmp = L + imm;
	6336
	6337	ZHC_ADD( tmp, L, 0 );
	6338	L = tmp;
	6339	SKIP_NC;
	6340	}
	6341
	6342	/* 74 28: 0111 0100 0010 1000 xxxx xxxx */
	6343	void upd7810_device::GTI_V_xx()
	6344	{
	6345	UINT8 imm;
	6346	UINT16 tmp;
	6347
	6348	RDOPARG( imm );
	6349	tmp = V - imm - 1;
	6350	ZHC_SUB( tmp, V, 0 );
	6351
	6352	SKIP_NC;
	6353	}
	6354
	6355	/* 74 29: 0111 0100 0010 1001 xxxx xxxx */
	6356	void upd7810_device::GTI_A_xx()
	6357	{
	6358	UINT8 imm;
	6359	UINT16 tmp;
	6360
	6361	RDOPARG( imm );
	6362	tmp = A - imm - 1;
	6363	ZHC_SUB( tmp, A, 0 );
	6364
	6365	SKIP_NC;
	6366	}
	6367
	6368	/* 74 2a: 0111 0100 0010 1010 xxxx xxxx */
	6369	void upd7810_device::GTI_B_xx()
	6370	{
	6371	UINT8 imm;
	6372	UINT16 tmp;
	6373
	6374	RDOPARG( imm );
	6375	tmp = B - imm - 1;
	6376	ZHC_SUB( tmp, B, 0 );
	6377
	6378	SKIP_NC;
	6379	}
	6380
	6381	/* 74 2b: 0111 0100 0010 1011 xxxx xxxx */
	6382	void upd7810_device::GTI_C_xx()
	6383	{
	6384	UINT8 imm;
	6385	UINT16 tmp;
	6386
	6387	RDOPARG( imm );
	6388	tmp = C - imm - 1;
	6389	ZHC_SUB( tmp, C, 0 );
	6390
	6391	SKIP_NC;
	6392	}
	6393
	6394	/* 74 2c: 0111 0100 0010 1100 xxxx xxxx */
	6395	void upd7810_device::GTI_D_xx()
	6396	{
	6397	UINT8 imm;
	6398	UINT16 tmp;
	6399
	6400	RDOPARG( imm );
	6401	tmp = D - imm - 1;
	6402	ZHC_SUB( tmp, D, 0 );
	6403
	6404	SKIP_NC;
	6405	}
	6406
	6407	/* 74 2d: 0111 0100 0010 1101 xxxx xxxx */
	6408	void upd7810_device::GTI_E_xx()
	6409	{
	6410	UINT8 imm;
	6411	UINT16 tmp;
	6412
	6413	RDOPARG( imm );
	6414	tmp = E - imm - 1;
	6415	ZHC_SUB( tmp, E, 0 );
	6416
	6417	SKIP_NC;
	6418	}
	6419
	6420	/* 74 2e: 0111 0100 0010 1110 xxxx xxxx */
	6421	void upd7810_device::GTI_H_xx()
	6422	{
	6423	UINT8 imm;
	6424	UINT16 tmp;
	6425
	6426	RDOPARG( imm );
	6427	tmp = H - imm - 1;
	6428	ZHC_SUB( tmp, H, 0 );
	6429
	6430	SKIP_NC;
	6431	}
	6432
	6433	/* 74 2f: 0111 0100 0010 1111 xxxx xxxx */
	6434	void upd7810_device::GTI_L_xx()
	6435	{
	6436	UINT8 imm;
	6437	UINT16 tmp;
	6438
	6439	RDOPARG( imm );
	6440	tmp = L - imm - 1;
	6441	ZHC_SUB( tmp, L, 0 );
	6442
	6443	SKIP_NC;
	6444	}
	6445
	6446	/* 74 30: 0111 0100 0011 0000 xxxx xxxx */
	6447	void upd7810_device::SUINB_V_xx()
	6448	{
	6449	UINT8 tmp, imm;
	6450
	6451	RDOPARG( imm );
	6452	tmp = V - imm;
	6453	ZHC_SUB( tmp, V, 0 );
	6454	V = tmp;
	6455	SKIP_NC;
	6456	}
	6457
	6458	/* 74 31: 0111 0100 0011 0001 xxxx xxxx */
	6459	void upd7810_device::SUINB_A_xx()
	6460	{
	6461	UINT8 tmp, imm;
	6462
	6463	RDOPARG( imm );
	6464	tmp = A - imm;
	6465	ZHC_SUB( tmp, A, 0 );
	6466	A = tmp;
	6467	SKIP_NC;
	6468	}
	6469
	6470	/* 74 32: 0111 0100 0011 0010 xxxx xxxx */
	6471	void upd7810_device::SUINB_B_xx()
	6472	{
	6473	UINT8 tmp, imm;
	6474
	6475	RDOPARG( imm );
	6476	tmp = B - imm;
	6477	ZHC_SUB( tmp, B, 0 );
	6478	B = tmp;
	6479	SKIP_NC;
	6480	}
	6481
	6482	/* 74 33: 0111 0100 0011 0011 xxxx xxxx */
	6483	void upd7810_device::SUINB_C_xx()
	6484	{
	6485	UINT8 tmp, imm;
	6486
	6487	RDOPARG( imm );
	6488	tmp = C - imm;
	6489	ZHC_SUB( tmp, C, 0 );
	6490	C = tmp;
	6491	SKIP_NC;
	6492	}
	6493
	6494	/* 74 34: 0111 0100 0011 0100 xxxx xxxx */
	6495	void upd7810_device::SUINB_D_xx()
	6496	{
	6497	UINT8 tmp, imm;
	6498
	6499	RDOPARG( imm );
	6500	tmp = D - imm;
	6501	ZHC_SUB( tmp, D, 0 );
	6502	D = tmp;
	6503	SKIP_NC;
	6504	}
	6505
	6506	/* 74 35: 0111 0100 0011 0101 xxxx xxxx */
	6507	void upd7810_device::SUINB_E_xx()
	6508	{
	6509	UINT8 tmp, imm;
	6510
	6511	RDOPARG( imm );
	6512	tmp = E - imm;
	6513	ZHC_SUB( tmp, E, 0 );
	6514	E = tmp;
	6515	SKIP_NC;
	6516	}
	6517
	6518	/* 74 36: 0111 0100 0011 0110 xxxx xxxx */
	6519	void upd7810_device::SUINB_H_xx()
	6520	{
	6521	UINT8 tmp, imm;
	6522
	6523	RDOPARG( imm );
	6524	tmp = H - imm;
	6525	ZHC_SUB( tmp, H, 0 );
	6526	H = tmp;
	6527	SKIP_NC;
	6528	}
	6529
	6530	/* 74 37: 0111 0100 0011 0111 xxxx xxxx */
	6531	void upd7810_device::SUINB_L_xx()
	6532	{
	6533	UINT8 tmp, imm;
	6534
	6535	RDOPARG( imm );
	6536	tmp = L - imm;
	6537	ZHC_SUB( tmp, L, 0 );
	6538	L = tmp;
	6539	SKIP_NC;
	6540	}
	6541
	6542	/* 74 38: 0111 0100 0011 1000 xxxx xxxx */
	6543	void upd7810_device::LTI_V_xx()
	6544	{
	6545	UINT8 tmp, imm;
	6546
	6547	RDOPARG( imm );
	6548	tmp = V - imm;
	6549	ZHC_SUB( tmp, V, 0 );
	6550	SKIP_CY;
	6551	}
	6552
	6553	/* 74 39: 0111 0100 0011 1001 xxxx xxxx */
	6554	void upd7810_device::LTI_A_xx()
	6555	{
	6556	UINT8 tmp, imm;
	6557
	6558	RDOPARG( imm );
	6559	tmp = A - imm;
	6560	ZHC_SUB( tmp, A, 0 );
	6561	SKIP_CY;
	6562	}
	6563
	6564	/* 74 3a: 0111 0100 0011 1010 xxxx xxxx */
	6565	void upd7810_device::LTI_B_xx()
	6566	{
	6567	UINT8 tmp, imm;
	6568
	6569	RDOPARG( imm );
	6570	tmp = B - imm;
	6571	ZHC_SUB( tmp, B, 0 );
	6572	SKIP_CY;
	6573	}
	6574
	6575	/* 74 3b: 0111 0100 0011 1011 xxxx xxxx */
	6576	void upd7810_device::LTI_C_xx()
	6577	{
	6578	UINT8 tmp, imm;
	6579
	6580	RDOPARG( imm );
	6581	tmp = C - imm;
	6582	ZHC_SUB( tmp, C, 0 );
	6583	SKIP_CY;
	6584	}
	6585
	6586	/* 74 3c: 0111 0100 0011 1100 xxxx xxxx */
	6587	void upd7810_device::LTI_D_xx()
	6588	{
	6589	UINT8 tmp, imm;
	6590
	6591	RDOPARG( imm );
	6592	tmp = D - imm;
	6593	ZHC_SUB( tmp, D, 0 );
	6594	SKIP_CY;
	6595	}
	6596
	6597	/* 74 3d: 0111 0100 0011 1101 xxxx xxxx */
	6598	void upd7810_device::LTI_E_xx()
	6599	{
	6600	UINT8 tmp, imm;
	6601
	6602	RDOPARG( imm );
	6603	tmp = E - imm;
	6604	ZHC_SUB( tmp, E, 0 );
	6605	SKIP_CY;
	6606	}
	6607
	6608	/* 74 3e: 0111 0100 0011 1110 xxxx xxxx */
	6609	void upd7810_device::LTI_H_xx()
	6610	{
	6611	UINT8 tmp, imm;
	6612
	6613	RDOPARG( imm );
	6614	tmp = H - imm;
	6615	ZHC_SUB( tmp, H, 0 );
	6616	SKIP_CY;
	6617	}
	6618
	6619	/* 74 3f: 0111 0100 0011 1111 xxxx xxxx */
	6620	void upd7810_device::LTI_L_xx()
	6621	{
	6622	UINT8 tmp, imm;
	6623
	6624	RDOPARG( imm );
	6625	tmp = L - imm;
	6626	ZHC_SUB( tmp, L, 0 );
	6627	SKIP_CY;
	6628	}
	6629
	6630	/* 74 40: 0111 0100 0100 0000 xxxx xxxx */
	6631	void upd7810_device::ADI_V_xx()
	6632	{
	6633	UINT8 tmp, imm;
	6634
	6635	RDOPARG( imm );
	6636	tmp = V + imm;
	6637
	6638	ZHC_ADD( tmp, V, 0 );
	6639	V = tmp;
	6640	}
	6641
	6642	/* 74 41: 0111 0100 0100 0001 xxxx xxxx */
	6643	void upd7810_device::ADI_A_xx()
	6644	{
	6645	UINT8 tmp, imm;
	6646
	6647	RDOPARG( imm );
	6648	tmp = A + imm;
	6649
	6650	ZHC_ADD( tmp, A, 0 );
	6651	A = tmp;
	6652	}
	6653
	6654	/* 74 42: 0111 0100 0100 0010 xxxx xxxx */
	6655	void upd7810_device::ADI_B_xx()
	6656	{
	6657	UINT8 tmp, imm;
	6658
	6659	RDOPARG( imm );
	6660	tmp = B + imm;
	6661
	6662	ZHC_ADD( tmp, B, 0 );
	6663	B = tmp;
	6664	}
	6665
	6666	/* 74 43: 0111 0100 0100 0011 xxxx xxxx */
	6667	void upd7810_device::ADI_C_xx()
	6668	{
	6669	UINT8 tmp, imm;
	6670
	6671	RDOPARG( imm );
	6672	tmp = C + imm;
	6673
	6674	ZHC_ADD( tmp, C, 0 );
	6675	C = tmp;
	6676	}
	6677
	6678	/* 74 44: 0111 0100 0100 0100 xxxx xxxx */
	6679	void upd7810_device::ADI_D_xx()
	6680	{
	6681	UINT8 tmp, imm;
	6682
	6683	RDOPARG( imm );
	6684	tmp = D + imm;
	6685
	6686	ZHC_ADD( tmp, D, 0 );
	6687	D = tmp;
	6688	}
	6689
	6690	/* 74 45: 0111 0100 0100 0101 xxxx xxxx */
	6691	void upd7810_device::ADI_E_xx()
	6692	{
	6693	UINT8 tmp, imm;
	6694
	6695	RDOPARG( imm );
	6696	tmp = E + imm;
	6697
	6698	ZHC_ADD( tmp, E, 0 );
	6699	E = tmp;
	6700	}
	6701
	6702	/* 74 46: 0111 0100 0100 0110 xxxx xxxx */
	6703	void upd7810_device::ADI_H_xx()
	6704	{
	6705	UINT8 tmp, imm;
	6706
	6707	RDOPARG( imm );
	6708	tmp = H + imm;
	6709
	6710	ZHC_ADD( tmp, H, 0 );
	6711	H = tmp;
	6712	}
	6713
	6714	/* 74 47: 0111 0100 0100 0111 xxxx xxxx */
	6715	void upd7810_device::ADI_L_xx()
	6716	{
	6717	UINT8 tmp, imm;
	6718
	6719	RDOPARG( imm );
	6720	tmp = L + imm;
	6721
	6722	ZHC_ADD( tmp, L, 0 );
	6723	L = tmp;
	6724	}
	6725
	6726	/* 74 48: 0111 0100 0100 1000 xxxx xxxx */
	6727	void upd7810_device::ONI_V_xx()
	6728	{
	6729	UINT8 imm;
	6730
	6731	RDOPARG( imm );
	6732	if (V & imm)
	6733	PSW \|= SK;
	6734	}
	6735
	6736	/* 74 49: 0111 0100 0100 1001 xxxx xxxx */
	6737	void upd7810_device::ONI_A_xx()
	6738	{
	6739	UINT8 imm;
	6740
	6741	RDOPARG( imm );
	6742	if (A & imm)
	6743	PSW \|= SK;
	6744	}
	6745
	6746	/* 74 4a: 0111 0100 0100 1010 xxxx xxxx */
	6747	void upd7810_device::ONI_B_xx()
	6748	{
	6749	UINT8 imm;
	6750
	6751	RDOPARG( imm );
	6752	if (B & imm)
	6753	PSW \|= SK;
	6754	}
	6755
	6756	/* 74 4b: 0111 0100 0100 1011 xxxx xxxx */
	6757	void upd7810_device::ONI_C_xx()
	6758	{
	6759	UINT8 imm;
	6760
	6761	RDOPARG( imm );
	6762	if (C & imm)
	6763	PSW \|= SK;
	6764	}
	6765
	6766	/* 74 4c: 0111 0100 0100 1100 xxxx xxxx */
	6767	void upd7810_device::ONI_D_xx()
	6768	{
	6769	UINT8 imm;
	6770
	6771	RDOPARG( imm );
	6772	if (D & imm)
	6773	PSW \|= SK;
	6774	}
	6775
	6776	/* 74 4d: 0111 0100 0100 1101 xxxx xxxx */
	6777	void upd7810_device::ONI_E_xx()
	6778	{
	6779	UINT8 imm;
	6780
	6781	RDOPARG( imm );
	6782	if (E & imm)
	6783	PSW \|= SK;
	6784	}
	6785
	6786	/* 74 4e: 0111 0100 0100 1110 xxxx xxxx */
	6787	void upd7810_device::ONI_H_xx()
	6788	{
	6789	UINT8 imm;
	6790
	6791	RDOPARG( imm );
	6792	if (H & imm)
	6793	PSW \|= SK;
	6794	}
	6795
	6796	/* 74 4f: 0111 0100 0100 1111 xxxx xxxx */
	6797	void upd7810_device::ONI_L_xx()
	6798	{
	6799	UINT8 imm;
	6800
	6801	RDOPARG( imm );
	6802	if (L & imm)
	6803	PSW \|= SK;
	6804	}
	6805
	6806	/* 74 50: 0111 0100 0101 0000 xxxx xxxx */
	6807	void upd7810_device::ACI_V_xx()
	6808	{
	6809	UINT8 tmp, imm;
	6810
	6811	RDOPARG( imm );
	6812	tmp = V + imm + (PSW & CY);
	6813	ZHC_ADD( tmp, V, (PSW & CY) );
	6814	V = tmp;
	6815	}
	6816
	6817	/* 74 51: 0111 0100 0101 0001 xxxx xxxx */
	6818	void upd7810_device::ACI_A_xx()
	6819	{
	6820	UINT8 tmp, imm;
	6821
	6822	RDOPARG( imm );
	6823	tmp = A + imm + (PSW & CY);
	6824	ZHC_ADD( tmp, A, (PSW & CY) );
	6825	A = tmp;
	6826	}
	6827
	6828	/* 74 52: 0111 0100 0101 0010 xxxx xxxx */
	6829	void upd7810_device::ACI_B_xx()
	6830	{
	6831	UINT8 tmp, imm;
	6832
	6833	RDOPARG( imm );
	6834	tmp = B + imm + (PSW & CY);
	6835	ZHC_ADD( tmp, B, (PSW & CY) );
	6836	B = tmp;
	6837	}
	6838
	6839	/* 74 53: 0111 0100 0101 0011 xxxx xxxx */
	6840	void upd7810_device::ACI_C_xx()
	6841	{
	6842	UINT8 tmp, imm;
	6843
	6844	RDOPARG( imm );
	6845	tmp = C + imm + (PSW & CY);
	6846	ZHC_ADD( tmp, C, (PSW & CY) );
	6847	C = tmp;
	6848	}
	6849
	6850	/* 74 54: 0111 0100 0101 0100 xxxx xxxx */
	6851	void upd7810_device::ACI_D_xx()
	6852	{
	6853	UINT8 tmp, imm;
	6854
	6855	RDOPARG( imm );
	6856	tmp = D + imm + (PSW & CY);
	6857	ZHC_ADD( tmp, D, (PSW & CY) );
	6858	D = tmp;
	6859	}
	6860
	6861	/* 74 55: 0111 0100 0101 0101 xxxx xxxx */
	6862	void upd7810_device::ACI_E_xx()
	6863	{
	6864	UINT8 tmp, imm;
	6865
	6866	RDOPARG( imm );
	6867	tmp = E + imm + (PSW & CY);
	6868	ZHC_ADD( tmp, E, (PSW & CY) );
	6869	E = tmp;
	6870	}
	6871
	6872	/* 74 56: 0111 0100 0101 0110 xxxx xxxx */
	6873	void upd7810_device::ACI_H_xx()
	6874	{
	6875	UINT8 tmp, imm;
	6876
	6877	RDOPARG( imm );
	6878	tmp = H + imm + (PSW & CY);
	6879	ZHC_ADD( tmp, H, (PSW & CY) );
	6880	H = tmp;
	6881	}
	6882
	6883	/* 74 57: 0111 0100 0101 0111 xxxx xxxx */
	6884	void upd7810_device::ACI_L_xx()
	6885	{
	6886	UINT8 tmp, imm;
	6887
	6888	RDOPARG( imm );
	6889	tmp = L + imm + (PSW & CY);
	6890	ZHC_ADD( tmp, L, (PSW & CY) );
	6891	L = tmp;
	6892	}
	6893
	6894	/* 74 58: 0111 0100 0101 1000 xxxx xxxx */
	6895	void upd7810_device::OFFI_V_xx()
	6896	{
	6897	UINT8 imm;
	6898
	6899	RDOPARG( imm );
	6900	if (0 == (V & imm))
	6901	PSW \|= SK;
	6902	}
	6903
	6904	/* 74 59: 0111 0100 0101 1001 xxxx xxxx */
	6905	void upd7810_device::OFFI_A_xx()
	6906	{
	6907	UINT8 imm;
	6908
	6909	RDOPARG( imm );
	6910	if (0 == (A & imm))
	6911	PSW \|= SK;
	6912	}
	6913
	6914	/* 74 5a: 0111 0100 0101 1010 xxxx xxxx */
	6915	void upd7810_device::OFFI_B_xx()
	6916	{
	6917	UINT8 imm;
	6918
	6919	RDOPARG( imm );
	6920	if (0 == (B & imm))
	6921	PSW \|= SK;
	6922	}
	6923
	6924	/* 74 5b: 0111 0100 0101 1011 xxxx xxxx */
	6925	void upd7810_device::OFFI_C_xx()
	6926	{
	6927	UINT8 imm;
	6928
	6929	RDOPARG( imm );
	6930	if (0 == (C & imm))
	6931	PSW \|= SK;
	6932	}
	6933
	6934	/* 74 5c: 0111 0100 0101 1100 xxxx xxxx */
	6935	void upd7810_device::OFFI_D_xx()
	6936	{
	6937	UINT8 imm;
	6938
	6939	RDOPARG( imm );
	6940	if (0 == (D & imm))
	6941	PSW \|= SK;
	6942	}
	6943
	6944	/* 74 5d: 0111 0100 0101 1101 xxxx xxxx */
	6945	void upd7810_device::OFFI_E_xx()
	6946	{
	6947	UINT8 imm;
	6948
	6949	RDOPARG( imm );
	6950	if (0 == (E & imm))
	6951	PSW \|= SK;
	6952	}
	6953
	6954	/* 74 5e: 0111 0100 0101 1110 xxxx xxxx */
	6955	void upd7810_device::OFFI_H_xx()
	6956	{
	6957	UINT8 imm;
	6958
	6959	RDOPARG( imm );
	6960	if (0 == (H & imm))
	6961	PSW \|= SK;
	6962	}
	6963
	6964	/* 74 5f: 0111 0100 0101 1111 xxxx xxxx */
	6965	void upd7810_device::OFFI_L_xx()
	6966	{
	6967	UINT8 imm;
	6968
	6969	RDOPARG( imm );
	6970	if (0 == (L & imm))
	6971	PSW \|= SK;
	6972	}
	6973
	6974	/* 74 60: 0111 0100 0110 0000 xxxx xxxx */
	6975	void upd7810_device::SUI_V_xx()
	6976	{
	6977	UINT8 tmp, imm;
	6978
	6979	RDOPARG( imm );
	6980	tmp = V - imm;
	6981	ZHC_SUB( tmp, V, 0 );
	6982	V = tmp;
	6983	}
	6984
	6985	/* 74 61: 0111 0100 0110 0001 xxxx xxxx */
	6986	void upd7810_device::SUI_A_xx()
	6987	{
	6988	UINT8 tmp, imm;
	6989
	6990	RDOPARG( imm );
	6991	tmp = A - imm;
	6992	ZHC_SUB( tmp, A, 0 );
	6993	A = tmp;
	6994	}
	6995
	6996	/* 74 62: 0111 0100 0110 0010 xxxx xxxx */
	6997	void upd7810_device::SUI_B_xx()
	6998	{
	6999	UINT8 tmp, imm;
	7000
	7001	RDOPARG( imm );
	7002	tmp = B - imm;
	7003	ZHC_SUB( tmp, B, 0 );
	7004	B = tmp;
	7005	}
	7006
	7007	/* 74 63: 0111 0100 0110 0011 xxxx xxxx */
	7008	void upd7810_device::SUI_C_xx()
	7009	{
	7010	UINT8 tmp, imm;
	7011
	7012	RDOPARG( imm );
	7013	tmp = C - imm;
	7014	ZHC_SUB( tmp, C, 0 );
	7015	C = tmp;
	7016	}
	7017
	7018	/* 74 64: 0111 0100 0110 0100 xxxx xxxx */
	7019	void upd7810_device::SUI_D_xx()
	7020	{
	7021	UINT8 tmp, imm;
	7022
	7023	RDOPARG( imm );
	7024	tmp = D - imm;
	7025	ZHC_SUB( tmp, D, 0 );
	7026	D = tmp;
	7027	}
	7028
	7029	/* 74 65: 0111 0100 0110 0101 xxxx xxxx */
	7030	void upd7810_device::SUI_E_xx()
	7031	{
	7032	UINT8 tmp, imm;
	7033
	7034	RDOPARG( imm );
	7035	tmp = E - imm;
	7036	ZHC_SUB( tmp, E, 0 );
	7037	E = tmp;
	7038	}
	7039
	7040	/* 74 66: 0111 0100 0110 0110 xxxx xxxx */
	7041	void upd7810_device::SUI_H_xx()
	7042	{
	7043	UINT8 tmp, imm;
	7044
	7045	RDOPARG( imm );
	7046	tmp = H - imm;
	7047	ZHC_SUB( tmp, H, 0 );
	7048	H = tmp;
	7049	}
	7050
	7051	/* 74 67: 0111 0100 0110 0111 xxxx xxxx */
	7052	void upd7810_device::SUI_L_xx()
	7053	{
	7054	UINT8 tmp, imm;
	7055
	7056	RDOPARG( imm );
	7057	tmp = L - imm;
	7058	ZHC_SUB( tmp, L, 0 );
	7059	L = tmp;
	7060	}
	7061
	7062	/* 74 68: 0111 0100 0110 1000 xxxx xxxx */
	7063	void upd7810_device::NEI_V_xx()
	7064	{
	7065	UINT8 tmp, imm;
	7066
	7067	RDOPARG( imm );
	7068	tmp = V - imm;
	7069	ZHC_SUB( tmp, V, 0 );
	7070	SKIP_NZ;
	7071	}
	7072
	7073	/* 74 69: 0111 0100 0110 1001 xxxx xxxx */
	7074	void upd7810_device::NEI_A_xx()
	7075	{
	7076	UINT8 tmp, imm;
	7077
	7078	RDOPARG( imm );
	7079	tmp = A - imm;
	7080	ZHC_SUB( tmp, A, 0 );
	7081	SKIP_NZ;
	7082	}
	7083
	7084	/* 74 6a: 0111 0100 0110 1010 xxxx xxxx */
	7085	void upd7810_device::NEI_B_xx()
	7086	{
	7087	UINT8 tmp, imm;
	7088
	7089	RDOPARG( imm );
	7090	tmp = B - imm;
	7091	ZHC_SUB( tmp, B, 0 );
	7092	SKIP_NZ;
	7093	}
	7094
	7095	/* 74 6b: 0111 0100 0110 1011 xxxx xxxx */
	7096	void upd7810_device::NEI_C_xx()
	7097	{
	7098	UINT8 tmp, imm;
	7099
	7100	RDOPARG( imm );
	7101	tmp = C - imm;
	7102	ZHC_SUB( tmp, C, 0 );
	7103	SKIP_NZ;
	7104	}
	7105
	7106	/* 74 6c: 0111 0100 0110 1100 xxxx xxxx */
	7107	void upd7810_device::NEI_D_xx()
	7108	{
	7109	UINT8 tmp, imm;
	7110
	7111	RDOPARG( imm );
	7112	tmp = D - imm;
	7113	ZHC_SUB( tmp, D, 0 );
	7114	SKIP_NZ;
	7115	}
	7116
	7117	/* 74 6d: 0111 0100 0110 1101 xxxx xxxx */
	7118	void upd7810_device::NEI_E_xx()
	7119	{
	7120	UINT8 tmp, imm;
	7121
	7122	RDOPARG( imm );
	7123	tmp = E - imm;
	7124	ZHC_SUB( tmp, E, 0 );
	7125	SKIP_NZ;
	7126	}
	7127
	7128	/* 74 6e: 0111 0100 0110 1110 xxxx xxxx */
	7129	void upd7810_device::NEI_H_xx()
	7130	{
	7131	UINT8 tmp, imm;
	7132
	7133	RDOPARG( imm );
	7134	tmp = H - imm;
	7135	ZHC_SUB( tmp, H, 0 );
	7136	SKIP_NZ;
	7137	}
	7138
	7139	/* 74 6f: 0111 0100 0110 1111 xxxx xxxx */
	7140	void upd7810_device::NEI_L_xx()
	7141	{
	7142	UINT8 tmp, imm;
	7143
	7144	RDOPARG( imm );
	7145	tmp = L - imm;
	7146	ZHC_SUB( tmp, L, 0 );
	7147	SKIP_NZ;
	7148	}
	7149
	7150	/* 74 70: 0111 0100 0111 0000 xxxx xxxx */
	7151	void upd7810_device::SBI_V_xx()
	7152	{
	7153	UINT8 tmp, imm;
	7154
	7155	RDOPARG( imm );
	7156	tmp = V - imm - (PSW & CY);
	7157	ZHC_SUB( tmp, V, (PSW & CY) );
	7158	V = tmp;
	7159	}
	7160
	7161	/* 74 71: 0111 0100 0111 0001 xxxx xxxx */
	7162	void upd7810_device::SBI_A_xx()
	7163	{
	7164	UINT8 tmp, imm;
	7165
	7166	RDOPARG( imm );
	7167	tmp = A - imm - (PSW & CY);
	7168	ZHC_SUB( tmp, A, (PSW & CY) );
	7169	A = tmp;
	7170	}
	7171
	7172	/* 74 72: 0111 0100 0111 0010 xxxx xxxx */
	7173	void upd7810_device::SBI_B_xx()
	7174	{
	7175	UINT8 tmp, imm;
	7176
	7177	RDOPARG( imm );
	7178	tmp = B - imm - (PSW & CY);
	7179	ZHC_SUB( tmp, B, (PSW & CY) );
	7180	B = tmp;
	7181	}
	7182
	7183	/* 74 73: 0111 0100 0111 0011 xxxx xxxx */
	7184	void upd7810_device::SBI_C_xx()
	7185	{
	7186	UINT8 tmp, imm;
	7187
	7188	RDOPARG( imm );
	7189	tmp = C - imm - (PSW & CY);
	7190	ZHC_SUB( tmp, C, (PSW & CY) );
	7191	C = tmp;
	7192	}
	7193
	7194	/* 74 74: 0111 0100 0111 0100 xxxx xxxx */
	7195	void upd7810_device::SBI_D_xx()
	7196	{
	7197	UINT8 tmp, imm;
	7198
	7199	RDOPARG( imm );
	7200	tmp = D - imm - (PSW & CY);
	7201	ZHC_SUB( tmp, D, (PSW & CY) );
	7202	D = tmp;
	7203	}
	7204
	7205	/* 74 75: 0111 0100 0111 0101 xxxx xxxx */
	7206	void upd7810_device::SBI_E_xx()
	7207	{
	7208	UINT8 tmp, imm;
	7209
	7210	RDOPARG( imm );
	7211	tmp = E - imm - (PSW & CY);
	7212	ZHC_SUB( tmp, E, (PSW & CY) );
	7213	E = tmp;
	7214	}
	7215
	7216	/* 74 76: 0111 0100 0111 0110 xxxx xxxx */
	7217	void upd7810_device::SBI_H_xx()
	7218	{
	7219	UINT8 tmp, imm;
	7220
	7221	RDOPARG( imm );
	7222	tmp = H - imm - (PSW & CY);
	7223	ZHC_SUB( tmp, H, (PSW & CY) );
	7224	H = tmp;
	7225	}
	7226
	7227	/* 74 77: 0111 0100 0111 0111 xxxx xxxx */
	7228	void upd7810_device::SBI_L_xx()
	7229	{
	7230	UINT8 tmp, imm;
	7231
	7232	RDOPARG( imm );
	7233	tmp = L - imm - (PSW & CY);
	7234	ZHC_SUB( tmp, L, (PSW & CY) );
	7235	L = tmp;
	7236	}
	7237
	7238	/* 74 78: 0111 0100 0111 1000 xxxx xxxx */
	7239	void upd7810_device::EQI_V_xx()
	7240	{
	7241	UINT8 tmp, imm;
	7242
	7243	RDOPARG( imm );
	7244	tmp = V - imm;
	7245	ZHC_SUB( tmp, V, 0 );
	7246	SKIP_Z;
	7247	}
	7248
	7249	/* 74 79: 0111 0100 0111 1001 xxxx xxxx */
	7250	void upd7810_device::EQI_A_xx()
	7251	{
	7252	UINT8 tmp, imm;
	7253
	7254	RDOPARG( imm );
	7255	tmp = A - imm;
	7256	ZHC_SUB( tmp, A, 0 );
	7257	SKIP_Z;
	7258	}
	7259
	7260	/* 74 7a: 0111 0100 0111 1010 xxxx xxxx */
	7261	void upd7810_device::EQI_B_xx()
	7262	{
	7263	UINT8 tmp, imm;
	7264
	7265	RDOPARG( imm );
	7266	tmp = B - imm;
	7267	ZHC_SUB( tmp, B, 0 );
	7268	SKIP_Z;
	7269	}
	7270
	7271	/* 74 7b: 0111 0100 0111 1011 xxxx xxxx */
	7272	void upd7810_device::EQI_C_xx()
	7273	{
	7274	UINT8 tmp, imm;
	7275
	7276	RDOPARG( imm );
	7277	tmp = C - imm;
	7278	ZHC_SUB( tmp, C, 0 );
	7279	SKIP_Z;
	7280	}
	7281
	7282	/* 74 7c: 0111 0100 0111 1100 xxxx xxxx */
	7283	void upd7810_device::EQI_D_xx()
	7284	{
	7285	UINT8 tmp, imm;
	7286
	7287	RDOPARG( imm );
	7288	tmp = D - imm;
	7289	ZHC_SUB( tmp, D, 0 );
	7290	SKIP_Z;
	7291	}
	7292
	7293	/* 74 7d: 0111 0100 0111 1101 xxxx xxxx */
	7294	void upd7810_device::EQI_E_xx()
	7295	{
	7296	UINT8 tmp, imm;
	7297
	7298	RDOPARG( imm );
	7299	tmp = E - imm;
	7300	ZHC_SUB( tmp, E, 0 );
	7301	SKIP_Z;
	7302	}
	7303
	7304	/* 74 7e: 0111 0100 0111 1110 xxxx xxxx */
	7305	void upd7810_device::EQI_H_xx()
	7306	{
	7307	UINT8 tmp, imm;
	7308
	7309	RDOPARG( imm );
	7310	tmp = H - imm;
	7311	ZHC_SUB( tmp, H, 0 );
	7312	SKIP_Z;
	7313	}
	7314
	7315	/* 74 7f: 0111 0100 0111 1111 xxxx xxxx */
	7316	void upd7810_device::EQI_L_xx()
	7317	{
	7318	UINT8 tmp, imm;
	7319
	7320	RDOPARG( imm );
	7321	tmp = L - imm;
	7322	ZHC_SUB( tmp, L, 0 );
	7323	SKIP_Z;
	7324	}
	7325
	7326	/* 74 88: 0111 0100 1000 1000 oooo oooo */
	7327	void upd7810_device::ANAW_wa()
	7328	{
	7329	PAIR ea = m_va;
	7330	RDOPARG( ea.b.l );
	7331
	7332	A &= RM( ea.d );
	7333	SET_Z(A);
	7334	}
	7335
	7336	/* 74 8d: 0111 0100 1000 1101 */
	7337	void upd7810_device::DAN_EA_BC()
	7338	{
	7339	EA &= BC;
	7340	SET_Z(EA);
	7341	}
	7342
	7343	/* 74 8e: 0111 0100 1000 1110 */
	7344	void upd7810_device::DAN_EA_DE()
	7345	{
	7346	EA &= DE;
	7347	SET_Z(EA);
	7348	}
	7349
	7350	/* 74 8f: 0111 0100 1000 1111 */
	7351	void upd7810_device::DAN_EA_HL()
	7352	{
	7353	EA &= HL;
	7354	SET_Z(EA);
	7355	}
	7356
	7357	/* 74 90: 0111 0100 1001 0000 oooo oooo */
	7358	void upd7810_device::XRAW_wa()
	7359	{
	7360	PAIR ea = m_va;
	7361	RDOPARG( ea.b.l );
	7362
	7363	A ^= RM( ea.d );
	7364	SET_Z(A);
	7365	}
	7366
	7367	/* 74 95: 0111 0100 1001 0101 */
	7368	void upd7810_device::DXR_EA_BC()
	7369	{
	7370	EA ^= BC;
	7371	SET_Z(EA);
	7372	}
	7373
	7374	/* 74 96: 0111 0100 1001 0110 */
	7375	void upd7810_device::DXR_EA_DE()
	7376	{
	7377	EA ^= DE;
	7378	SET_Z(EA);
	7379	}
	7380
	7381	/* 74 97: 0111 0100 1001 0111 */
	7382	void upd7810_device::DXR_EA_HL()
	7383	{
	7384	EA ^= HL;
	7385	SET_Z(EA);
	7386	}
	7387
	7388	/* 74 98: 0111 0100 1001 1000 oooo oooo */
	7389	void upd7810_device::ORAW_wa()
	7390	{
	7391	PAIR ea = m_va;
	7392	RDOPARG( ea.b.l );
	7393
	7394	A \|= RM( ea.d );
	7395	SET_Z(A);
	7396	}
	7397
	7398	/* 74 9d: 0111 0100 1001 1101 */
	7399	void upd7810_device::DOR_EA_BC()
	7400	{
	7401	EA \|= BC;
	7402	SET_Z(EA);
	7403	}
	7404
	7405	/* 74 9e: 0111 0100 1001 1110 */
	7406	void upd7810_device::DOR_EA_DE()
	7407	{
	7408	EA \|= DE;
	7409	SET_Z(EA);
	7410	}
	7411
	7412	/* 74 9f: 0111 0100 1001 1111 */
	7413	void upd7810_device::DOR_EA_HL()
	7414	{
	7415	EA \|= HL;
	7416	SET_Z(EA);
	7417	}
	7418
	7419	/* 74 a0: 0111 0100 1010 0000 oooo oooo */
	7420	void upd7810_device::ADDNCW_wa()
	7421	{
	7422	PAIR ea = m_va;
	7423	UINT8 tmp;
	7424
	7425	RDOPARG( ea.b.l );
	7426
	7427	tmp = A + RM( ea.d );
	7428	ZHC_ADD( tmp, A, 0 );
	7429	A = tmp;
	7430	SKIP_NC;
	7431	}
	7432
	7433	/* 74 a5: 0111 0100 1010 0101 */
	7434	void upd7810_device::DADDNC_EA_BC()
	7435	{
	7436	UINT16 tmp = EA + BC;
	7437
	7438	ZHC_ADD( tmp, EA, 0 );
	7439	EA = tmp;
	7440	SKIP_NC;
	7441	}
	7442
	7443	/* 74 a6: 0111 0100 1010 0110 */
	7444	void upd7810_device::DADDNC_EA_DE()
	7445	{
	7446	UINT16 tmp = EA + DE;
	7447
	7448	ZHC_ADD( tmp, EA, 0 );
	7449	EA = tmp;
	7450	SKIP_NC;
	7451	}
	7452
	7453	/* 74 a7: 0111 0100 1010 0111 */
	7454	void upd7810_device::DADDNC_EA_HL()
	7455	{
	7456	UINT16 tmp = EA + HL;
	7457
	7458	ZHC_ADD( tmp, EA, 0 );
	7459	EA = tmp;
	7460	SKIP_NC;
	7461	}
	7462
	7463	/* 74 a8: 0111 0100 1010 1000 oooo oooo */
	7464	void upd7810_device::GTAW_wa()
	7465	{
	7466	PAIR ea = m_va;
	7467	UINT16 tmp;
	7468
	7469	RDOPARG( ea.b.l );
	7470	tmp = A - RM( ea.d ) - 1;
	7471	ZHC_SUB( tmp, A, 0 );
	7472	SKIP_NC;
	7473	}
	7474
	7475	/* 74 ad: 0111 0100 1010 1101 */
	7476	void upd7810_device::DGT_EA_BC()
	7477	{
	7478	UINT32 tmp = EA - BC - 1;
	7479	ZHC_SUB( tmp, EA, 0 );
	7480	SKIP_NC;
	7481	}
	7482
	7483	/* 74 ae: 0111 0100 1010 1110 */
	7484	void upd7810_device::DGT_EA_DE()
	7485	{
	7486	UINT32 tmp = EA - DE - 1;
	7487	ZHC_SUB( tmp, EA, 0 );
	7488	SKIP_NC;
	7489	}
	7490
	7491	/* 74 af: 0111 0100 1010 1111 */
	7492	void upd7810_device::DGT_EA_HL()
	7493	{
	7494	UINT32 tmp = EA - HL - 1;
	7495	ZHC_SUB( tmp, EA, 0 );
	7496	SKIP_NC;
	7497	}
	7498
	7499	/* 74 b0: 0111 0100 1011 0000 oooo oooo */
	7500	void upd7810_device::SUBNBW_wa()
	7501	{
	7502	PAIR ea = m_va;
	7503	UINT8 tmp;
	7504
	7505	RDOPARG( ea.b.l );
	7506	tmp = A - RM( ea.d );
	7507	ZHC_SUB( tmp, A, 0 );
	7508	A = tmp;
	7509	SKIP_NC;
	7510	}
	7511
	7512	/* 74 b5: 0111 0100 1011 0101 */
	7513	void upd7810_device::DSUBNB_EA_BC()
	7514	{
	7515	UINT16 tmp = EA - BC;
	7516	ZHC_SUB( tmp, EA, 0 );
	7517	EA = tmp;
	7518	SKIP_NC;
	7519	}
	7520
	7521	/* 74 b6: 0111 0100 1011 0110 */
	7522	void upd7810_device::DSUBNB_EA_DE()
	7523	{
	7524	UINT16 tmp = EA - DE;
	7525	ZHC_SUB( tmp, EA, 0 );
	7526	EA = tmp;
	7527	SKIP_NC;
	7528	}
	7529
	7530	/* 74 b7: 0111 0100 1011 0111 */
	7531	void upd7810_device::DSUBNB_EA_HL()
	7532	{
	7533	UINT16 tmp;
	7534
	7535	tmp = EA - HL;
	7536	ZHC_SUB( tmp, EA, 0 );
	7537	EA = tmp;
	7538	SKIP_NC;
	7539	}
	7540
	7541	/* 74 b8: 0111 0100 1011 1000 oooo oooo */
	7542	void upd7810_device::LTAW_wa()
	7543	{
	7544	PAIR ea = m_va;
	7545	UINT8 tmp;
	7546
	7547	RDOPARG( ea.b.l );
	7548	tmp = A - RM( ea.d );
	7549	ZHC_SUB( tmp, A, 0 );
	7550	SKIP_CY;
	7551	}
	7552
	7553	/* 74 bd: 0111 0100 1011 1101 */
	7554	void upd7810_device::DLT_EA_BC()
	7555	{
	7556	UINT16 tmp = EA - BC;
	7557	ZHC_SUB( tmp, EA, 0 );
	7558	SKIP_CY;
	7559	}
	7560
	7561	/* 74 be: 0111 0100 1011 1110 */
	7562	void upd7810_device::DLT_EA_DE()
	7563	{
	7564	UINT16 tmp = EA - DE;
	7565	ZHC_SUB( tmp, EA, 0 );
	7566	SKIP_CY;
	7567	}
	7568
	7569	/* 74 bf: 0111 0100 1011 1111 */
	7570	void upd7810_device::DLT_EA_HL()
	7571	{
	7572	UINT16 tmp = EA - HL;
	7573	ZHC_SUB( tmp, EA, 0 );
	7574	SKIP_CY;
	7575	}
	7576
	7577	/* 74 c0: 0111 0100 1100 0000 oooo oooo */
	7578	void upd7810_device::ADDW_wa()
	7579	{
	7580	PAIR ea = m_va;
	7581	UINT8 tmp;
	7582	RDOPARG( ea.b.l );
	7583	tmp = A + RM( ea.d );
	7584	ZHC_ADD( tmp, A, 0 );
	7585	A = tmp;
	7586	}
	7587
	7588	/* 74 c5: 0111 0100 1100 0101 */
	7589	void upd7810_device::DADD_EA_BC()
	7590	{
	7591	UINT16 tmp = EA + BC;
	7592	ZHC_ADD( tmp, EA, 0 );
	7593	EA = tmp;
	7594	}
	7595
	7596	/* 74 c6: 0111 0100 1100 0110 */
	7597	void upd7810_device::DADD_EA_DE()
	7598	{
	7599	UINT16 tmp = EA + DE;
	7600	ZHC_ADD( tmp, EA, 0 );
	7601	EA = tmp;
	7602	}
	7603
	7604	/* 74 c7: 0111 0100 1100 0111 */
	7605	void upd7810_device::DADD_EA_HL()
	7606	{
	7607	UINT16 tmp = EA + HL;
	7608	ZHC_ADD( tmp, EA, 0 );
	7609	EA = tmp;
	7610	}
	7611
	7612	/* 74 c8: 0111 0100 1100 1000 oooo oooo */
	7613	void upd7810_device::ONAW_wa()
	7614	{
	7615	PAIR ea = m_va;
	7616	RDOPARG( ea.b.l );
	7617
	7618	if (A & RM( ea.d ))
	7619	PSW = (PSW & ~Z) \| SK;
	7620	else
	7621	PSW \|= Z;
	7622	}
	7623
	7624	/* 74 cd: 0111 0100 1100 1101 */
	7625	void upd7810_device::DON_EA_BC()
	7626	{
	7627	if (EA & BC)
	7628	PSW = (PSW & ~Z) \| SK;
	7629	else
	7630	PSW \|= Z;
	7631	}
	7632
	7633	/* 74 ce: 0111 0100 1100 1110 */
	7634	void upd7810_device::DON_EA_DE()
	7635	{
	7636	if (EA & DE)
	7637	PSW = (PSW & ~Z) \| SK;
	7638	else
	7639	PSW \|= Z;
	7640	}
	7641
	7642	/* 74 cf: 0111 0100 1100 1111 */
	7643	void upd7810_device::DON_EA_HL()
	7644	{
	7645	if (EA & HL)
	7646	PSW = (PSW & ~Z) \| SK;
	7647	else
	7648	PSW \|= Z;
	7649	}
	7650
	7651	/* 74 d0: 0111 0100 1101 0000 oooo oooo */
	7652	void upd7810_device::ADCW_wa()
	7653	{
	7654	PAIR ea = m_va;
	7655	UINT8 tmp;
	7656
	7657	RDOPARG( ea.b.l );
	7658	tmp = A + RM( ea.d ) + (PSW & CY);
	7659	ZHC_ADD( tmp, A, (PSW & CY) );
	7660	A = tmp;
	7661	}
	7662
	7663	/* 74 d5: 0111 0100 1101 0101 */
	7664	void upd7810_device::DADC_EA_BC()
	7665	{
	7666	UINT16 tmp = EA + BC + (PSW & CY);
	7667	ZHC_ADD( tmp, EA, (PSW & CY) );
	7668	EA = tmp;
	7669	}
	7670
	7671	/* 74 d6: 0111 0100 1101 0110 */
	7672	void upd7810_device::DADC_EA_DE()
	7673	{
	7674	UINT16 tmp = EA + DE + (PSW & CY);
	7675	ZHC_ADD( tmp, EA, (PSW & CY) );
	7676	EA = tmp;
	7677	}
	7678
	7679	/* 74 d7: 0111 0100 1101 0111 */
	7680	void upd7810_device::DADC_EA_HL()
	7681	{
	7682	UINT16 tmp = EA + HL + (PSW & CY);
	7683	ZHC_ADD( tmp, EA, (PSW & CY) );
	7684	EA = tmp;
	7685	}
	7686
	7687	/* 74 d8: 0111 0100 1101 1000 oooo oooo */
	7688	void upd7810_device::OFFAW_wa()
	7689	{
	7690	PAIR ea = m_va;
	7691	RDOPARG( ea.b.l );
	7692
	7693	if ( A & RM( ea.d ) )
	7694	PSW &= ~Z;
	7695	else
	7696	PSW = PSW \| Z \| SK;
	7697	}
	7698
	7699	/* 74 dd: 0111 0100 1101 1101 */
	7700	void upd7810_device::DOFF_EA_BC()
	7701	{
	7702	if ( EA & BC )
	7703	PSW &= ~Z;
	7704	else
	7705	PSW = PSW \| Z \| SK;
	7706	}
	7707
	7708	/* 74 de: 0111 0100 1101 1110 */
	7709	void upd7810_device::DOFF_EA_DE()
	7710	{
	7711	if ( EA & DE )
	7712	PSW &= ~Z;
	7713	else
	7714	PSW = PSW \| Z \| SK;
	7715	}
	7716
	7717	/* 74 df: 0111 0100 1101 1111 */
	7718	void upd7810_device::DOFF_EA_HL()
	7719	{
	7720	if ( EA & HL )
	7721	PSW &= ~Z;
	7722	else
	7723	PSW = PSW \| Z \| SK;
	7724	}
	7725
	7726	/* 74 e0: 0111 0100 1110 0000 oooo oooo */
	7727	void upd7810_device::SUBW_wa()
	7728	{
	7729	PAIR ea = m_va;
	7730	UINT8 tmp;
	7731
	7732	RDOPARG( ea.b.l );
	7733	tmp = A - RM( ea.d );
	7734	ZHC_SUB( tmp, A, 0 );
	7735	A = tmp;
	7736	}
	7737
	7738	/* 74 e5: 0111 0100 1110 0101 */
	7739	void upd7810_device::DSUB_EA_BC()
	7740	{
	7741	UINT16 tmp = EA - BC;
	7742	ZHC_SUB( tmp, EA, 0 );
	7743	EA = tmp;
	7744	}
	7745
	7746	/* 74 e6: 0111 0100 1110 0110 */
	7747	void upd7810_device::DSUB_EA_DE()
	7748	{
	7749	UINT16 tmp = EA - DE;
	7750	ZHC_SUB( tmp, EA, 0 );
	7751	EA = tmp;
	7752	}
	7753
	7754	/* 74 e7: 0111 0100 1110 0111 */
	7755	void upd7810_device::DSUB_EA_HL()
	7756	{
	7757	UINT16 tmp = EA - HL;
	7758	ZHC_SUB( tmp, EA, 0 );
	7759	EA = tmp;
	7760	}
	7761
	7762	/* 74 e8: 0111 0100 1110 1000 oooo oooo */
	7763	void upd7810_device::NEAW_wa()
	7764	{
	7765	PAIR ea = m_va;
	7766	UINT8 tmp;
	7767
	7768	RDOPARG( ea.b.l );
	7769	tmp = A - RM( ea.d );
	7770	ZHC_SUB( tmp, A, 0 );
	7771	SKIP_NZ;
	7772	}
	7773
	7774	/* 74 ed: 0111 0100 1110 1101 */
	7775	void upd7810_device::DNE_EA_BC()
	7776	{
	7777	UINT16 tmp;
	7778
	7779	tmp = EA - BC;
	7780	ZHC_SUB( tmp, EA, 0 );
	7781	SKIP_NZ;
	7782	}
	7783
	7784	/* 74 ee: 0111 0100 1110 1110 */
	7785	void upd7810_device::DNE_EA_DE()
	7786	{
	7787	UINT16 tmp;
	7788
	7789	tmp = EA - DE;
	7790	ZHC_SUB( tmp, EA, 0 );
	7791	SKIP_NZ;
	7792	}
	7793
	7794	/* 74 ef: 0111 0100 1110 1111 */
	7795	void upd7810_device::DNE_EA_HL()
	7796	{
	7797	UINT16 tmp;
	7798
	7799	tmp = EA - HL;
	7800	ZHC_SUB( tmp, EA, 0 );
	7801	SKIP_NZ;
	7802	}
	7803
	7804	/* 74 f0: 0111 0100 1111 0000 oooo oooo */
	7805	void upd7810_device::SBBW_wa()
	7806	{
	7807	PAIR ea = m_va;
	7808	UINT8 tmp;
	7809
	7810	RDOPARG( ea.b.l );
	7811	tmp = A - RM( ea.d ) - (PSW & CY);
	7812	ZHC_SUB( tmp, A, (PSW & CY) );
	7813	A = tmp;
	7814	}
	7815
	7816	/* 74 f5: 0111 0100 1111 0101 */
	7817	void upd7810_device::DSBB_EA_BC()
	7818	{
	7819	UINT16 tmp = EA - BC - (PSW & CY);
	7820	ZHC_SUB( tmp, EA, (PSW & CY) );
	7821	EA = tmp;
	7822	}
	7823
	7824	/* 74 f6: 0111 0100 1111 0110 */
	7825	void upd7810_device::DSBB_EA_DE()
	7826	{
	7827	UINT16 tmp = EA - DE - (PSW & CY);
	7828	ZHC_SUB( tmp, EA, (PSW & CY) );
	7829	EA = tmp;
	7830	}
	7831
	7832	/* 74 f7: 0111 0100 1111 0111 */
	7833	void upd7810_device::DSBB_EA_HL()
	7834	{
	7835	UINT16 tmp = EA - HL - (PSW & CY);
	7836	ZHC_SUB( tmp, EA, (PSW & CY) );
	7837	EA = tmp;
	7838	}
	7839
	7840	/* 74 f8: 0111 0100 1111 1000 oooo oooo */
	7841	void upd7810_device::EQAW_wa()
	7842	{
	7843	PAIR ea = m_va;
	7844	UINT8 tmp;
	7845
	7846	RDOPARG( ea.b.l );
	7847	tmp = A - RM( ea.d );
	7848	ZHC_SUB( tmp, A, 0 );
	7849	SKIP_Z;
	7850	}
	7851
	7852	/* 74 fd: 0111 0100 1111 1101 */
	7853	void upd7810_device::DEQ_EA_BC()
	7854	{
	7855	UINT16 tmp;
	7856
	7857	tmp = EA - BC;
	7858	ZHC_SUB( tmp, EA, 0 );
	7859	SKIP_Z;
	7860	}
	7861
	7862	/* 74 fe: 0111 0100 1111 1110 */
	7863	void upd7810_device::DEQ_EA_DE()
	7864	{
	7865	UINT16 tmp;
	7866
	7867	tmp = EA - DE;
	7868	ZHC_SUB( tmp, EA, 0 );
	7869	SKIP_Z;
	7870	}
	7871
	7872	/* 74 ff: 0111 0100 1111 1111 */
	7873	void upd7810_device::DEQ_EA_HL()
	7874	{
	7875	UINT16 tmp;
	7876
	7877	tmp = EA - HL;
	7878	ZHC_SUB( tmp, EA, 0 );
	7879	SKIP_Z;
	7880	}
	7881
	7882	/************************************************
	7883	* main opcodes
	7884	************************************************/
	7885
	7886	/* 00: 0000 0000 */
	7887	void upd7810_device::NOP()
	7888	{
	7889	}
	7890
	7891	/* 01: 0000 0001 oooo oooo */
	7892	void upd7810_device::LDAW_wa()
	7893	{
	7894	PAIR ea = m_va;
	7895
	7896	RDOPARG( ea.b.l );
	7897
	7898	A = RM( ea.d );
	7899	}
	7900
	7901	/* 02: 0000 0010 */
	7902	void upd7810_device::INX_SP()
	7903	{
	7904	SP++;
	7905	}
	7906
	7907	/* 03: 0000 0011 */
	7908	void upd7810_device::DCX_SP()
	7909	{
	7910	SP--;
	7911	}
	7912
	7913	/* 04: 0000 0100 llll llll hhhh hhhh */
	7914	void upd7810_device::LXI_S_w()
	7915	{
	7916	RDOPARG( SPL );
	7917	RDOPARG( SPH );
	7918	}
	7919
	7920	/* 05: 0000 0101 oooo oooo xxxx xxxx */
	7921	void upd7810_device::ANIW_wa_xx()
	7922	{
	7923	PAIR ea = m_va;
	7924	UINT8 m, imm;
	7925
	7926	RDOPARG( ea.b.l );
	7927	RDOPARG( imm );
	7928	m = RM( ea.d );
	7929	m &= imm;
	7930	WM( ea.d, m );
	7931	SET_Z(m);
	7932	}
	7933
	7934	/* 07: 0000 0111 xxxx xxxx */
	7935	/* ANI_A_xx already defined (long form) */
	7936
	7937	/* 08: 0000 1000 */
	7938	void upd7810_device::MOV_A_EAH()
	7939	{
	7940	A = EAH;
	7941	}
	7942
	7943	/* 09: 0000 1001 */
	7944	void upd7810_device::MOV_A_EAL()
	7945	{
	7946	A = EAL;
	7947	}
	7948
	7949	/* 0a: 0000 1010 */
	7950	void upd7810_device::MOV_A_B()
	7951	{
	7952	A = B;
	7953	}
	7954
	7955	/* 0b: 0000 1011 */
	7956	void upd7810_device::MOV_A_C()
	7957	{
	7958	A = C;
	7959	}
	7960
	7961	/* 0c: 0000 1100 */
	7962	void upd7810_device::MOV_A_D()
	7963	{
	7964	A = D;
	7965	}
	7966
	7967	/* 0d: 0000 1101 */
	7968	void upd7810_device::MOV_A_E()
	7969	{
	7970	A = E;
	7971	}
	7972
	7973	/* 0e: 0000 1110 */
	7974	void upd7810_device::MOV_A_H()
	7975	{
	7976	A = H;
	7977	}
	7978
	7979	/* 0f: 0000 1111 */
	7980	void upd7810_device::MOV_A_L()
	7981	{
	7982	A = L;
	7983	}
	7984
	7985	/* 10: 0001 0000 */
	7986	void upd7810_device::EXA()
	7987	{
	7988	UINT16 tmp;
	7989	tmp = EA; EA = EA2; EA2 = tmp;
	7990	tmp = VA; VA = VA2; VA2 = tmp;
	7991	}
	7992
	7993	/* 11: 0001 0001 */
	7994	void upd7810_device::EXX()
	7995	{
	7996	UINT16 tmp;
	7997	tmp = BC; BC = BC2; BC2 = tmp;
	7998	tmp = DE; DE = DE2; DE2 = tmp;
	7999	tmp = HL; HL = HL2; HL2 = tmp;
	8000	}
	8001
	8002	/* 48 AD (7807 only) */
	8003	void upd7810_device::EXR()
	8004	{
	8005	UINT16 tmp;
	8006	tmp = BC; BC = BC2; BC2 = tmp;
	8007	tmp = DE; DE = DE2; DE2 = tmp;
	8008	tmp = HL; HL = HL2; HL2 = tmp;
	8009	tmp = EA; EA = EA2; EA2 = tmp;
	8010	tmp = VA; VA = VA2; VA2 = tmp;
	8011	}
	8012
	8013	/* 12: 0001 0010 */
	8014	void upd7810_device::INX_BC()
	8015	{
	8016	BC++;
	8017	}
	8018
	8019	/* 13: 0001 0011 */
	8020	void upd7810_device::DCX_BC()
	8021	{
	8022	BC--;
	8023	}
	8024
	8025	/* 14: 0001 0100 llll llll hhhh hhhh */
	8026	void upd7810_device::LXI_B_w()
	8027	{
	8028	RDOPARG( C );
	8029	RDOPARG( B );
	8030	}
	8031
	8032	/* 15: 0001 0101 oooo oooo xxxx xxxx */
	8033	void upd7810_device::ORIW_wa_xx()
	8034	{
	8035	PAIR ea = m_va;
	8036	UINT8 m, imm;
	8037
	8038	RDOPARG( ea.b.l );
	8039	RDOPARG( imm );
	8040	m = RM( ea.d );
	8041	m \|= imm;
	8042	WM( ea.d, m );
	8043	SET_Z(m);
	8044	}
	8045
	8046	/* 16: 0001 0110 xxxx xxxx */
	8047	/* XRI_A_xx already defined (long form) */
	8048
	8049	/* 17: 0001 0111 xxxx xxxx */
	8050	/* ORI_A_xx already defined (long form) */
	8051
	8052	/* 18: 0001 1000 */
	8053	void upd7810_device::MOV_EAH_A()
	8054	{
	8055	EAH = A;
	8056	}
	8057
	8058	/* 19: 0001 1001 */
	8059	void upd7810_device::MOV_EAL_A()
	8060	{
	8061	EAL = A;
	8062	}
	8063
	8064	/* 1a: 0001 1010 */
	8065	void upd7810_device::MOV_B_A()
	8066	{
	8067	B = A;
	8068	}
	8069
	8070	/* 1b: 0001 1011 */
	8071	void upd7810_device::MOV_C_A()
	8072	{
	8073	C = A;
	8074	}
	8075
	8076	/* 1c: 0001 1100 */
	8077	void upd7810_device::MOV_D_A()
	8078	{
	8079	D = A;
	8080	}
	8081
	8082	/* 1d: 0001 1101 */
	8083	void upd7810_device::MOV_E_A()
	8084	{
	8085	E = A;
	8086	}
	8087
	8088	/* 1e: 0001 1110 */
	8089	void upd7810_device::MOV_H_A()
	8090	{
	8091	H = A;
	8092	}
	8093
	8094	/* 1f: 0001 1111 */
	8095	void upd7810_device::MOV_L_A()
	8096	{
	8097	L = A;
	8098	}
	8099
	8100	/* 20: 0010 0000 oooo oooo */
	8101	void upd7810_device::INRW_wa()
	8102	{
	8103	PAIR ea = m_va;
	8104	UINT8 tmp, m;
	8105
	8106	RDOPARG( ea.b.l );
	8107	m = RM( ea.d );
	8108	tmp = m + 1;
	8109	ZHC_ADD( tmp, m, 0 );
	8110	WM( ea.d, tmp );
	8111	SKIP_CY;
	8112	}
	8113
	8114	/* 21: 0010 0001 */
	8115	void upd7810_device::JB()
	8116	{
	8117	PC = BC;
	8118	}
	8119
	8120	/* 22: 0010 0010 */
	8121	void upd7810_device::INX_DE()
	8122	{
	8123	DE++;
	8124	}
	8125
	8126	/* 23: 0010 0011 */
	8127	void upd7810_device::DCX_DE()
	8128	{
	8129	DE--;
	8130	}
	8131
	8132	/* 24: 0010 0100 llll llll hhhh hhhh */
	8133	void upd7810_device::LXI_D_w()
	8134	{
	8135	RDOPARG( E );
	8136	RDOPARG( D );
	8137	}
	8138
	8139	/* 25: 0010 0101 oooo oooo xxxx xxxx */
	8140	void upd7810_device::GTIW_wa_xx()
	8141	{
	8142	PAIR ea = m_va;
	8143	UINT8 m, imm;
	8144	UINT16 tmp;
	8145
	8146	RDOPARG( ea.b.l );
	8147	RDOPARG( imm );
	8148	m = RM( ea.d );
	8149	tmp = m - imm - 1;
	8150	ZHC_SUB( tmp, m, 0 );
	8151	SKIP_NC;
	8152	}
	8153
	8154	/* 26: 0010 0110 xxxx xxxx */
	8155	/* ADINC_A_xx already defined (long form) */
	8156
	8157	/* 27: 0010 0111 xxxx xxxx */
	8158	/* GTI_A_xx already defined (long form) */
	8159
	8160	/* 29: 0010 1001 */
	8161	void upd7810_device::LDAX_B()
	8162	{
	8163	A = RM( BC );
	8164	}
	8165
	8166	/* 2a: 0010 1010 */
	8167	void upd7810_device::LDAX_D()
	8168	{
	8169	A = RM( DE );
	8170	}
	8171
	8172	/* 2b: 0010 1011 */
	8173	void upd7810_device::LDAX_H()
	8174	{
	8175	A = RM( HL );
	8176	}
	8177
	8178	/* 2c: 0010 1100 */
	8179	void upd7810_device::LDAX_Dp()
	8180	{
	8181	A = RM( DE );
	8182	DE++;
	8183	}
	8184
	8185	/* 2d: 0010 1101 dddd dddd */
	8186	void upd7810_device::LDAX_Hp()
	8187	{
	8188	A = RM( HL );
	8189	HL++;
	8190	}
	8191
	8192	/* 2e: 0010 1110 dddd dddd */
	8193	void upd7810_device::LDAX_Dm()
	8194	{
	8195	A = RM( DE );
	8196	DE--;
	8197	}
	8198
	8199	/* 2f: 0010 1111 dddd dddd */
	8200	void upd7810_device::LDAX_Hm()
	8201	{
	8202	A = RM( HL );
	8203	HL--;
	8204	}
	8205
	8206	/* 30: 0011 0000 oooo oooo */
	8207	void upd7810_device::DCRW_wa()
	8208	{
	8209	PAIR ea = m_va;
	8210	UINT8 tmp, m;
	8211
	8212	RDOPARG( ea.b.l );
	8213	m = RM( ea.d );
	8214	tmp = m - 1;
	8215	ZHC_SUB( tmp, m, 0 );
	8216	WM( ea.d, tmp );
	8217	SKIP_CY;
	8218	}
	8219
	8220	/* 31: 0011 0001 */
	8221	void upd7810_device::BLOCK()
	8222	{
	8223	WM( DE, RM( HL ) );
	8224	DE++;
	8225	HL++;
	8226	C--;
	8227	if (C == 0xff)
	8228	PSW \|= CY;
	8229	else
	8230	{
	8231	PSW &= ~CY;
	8232	PC--;
	8233	}
	8234	}
	8235
	8236	/* 32: 0011 0010 */
	8237	void upd7810_device::INX_HL()
	8238	{
	8239	HL++;
	8240	}
	8241
	8242	/* 33: 0011 0011 */
	8243	void upd7810_device::DCX_HL()
	8244	{
	8245	HL--;
	8246	}
	8247
	8248	/* 34: 0011 0100 llll llll hhhh hhhh */
	8249	void upd7810_device::LXI_H_w()
	8250	{
	8251	if (PSW & L0) { /* overlay active? */
	8252	PC+=2;
	8253	return;
	8254	}
	8255	RDOPARG( L );
	8256	RDOPARG( H );
	8257	PSW \|= L0;
	8258	}
	8259
	8260	/* 35: 0011 0101 oooo oooo xxxx xxxx */
	8261	void upd7810_device::LTIW_wa_xx()
	8262	{
	8263	PAIR ea = m_va;
	8264	UINT8 tmp, m, imm;
	8265
	8266	RDOPARG( ea.b.l );
	8267	RDOPARG( imm );
	8268	m = RM( ea.d );
	8269	tmp = m - imm;
	8270	ZHC_SUB( tmp, m, 0 );
	8271	SKIP_CY;
	8272	}
	8273
	8274	/* 36: 0011 0110 xxxx xxxx */
	8275	/* SUINB_A_xx already defined (long form) */
	8276
	8277	/* 37: 0011 0111 xxxx xxxx */
	8278	/* LTI_A_xx already defined (long form) */
	8279
	8280	/* 39: 0011 1001 */
	8281	void upd7810_device::STAX_B()
	8282	{
	8283	WM( BC, A );
	8284	}
	8285
	8286	/* 3a: 0011 1010 */
	8287	void upd7810_device::STAX_D()
	8288	{
	8289	WM( DE, A );
	8290	}
	8291
	8292	/* 3b: 0011 1011 */
	8293	void upd7810_device::STAX_H()
	8294	{
	8295	WM( HL, A );
	8296	}
	8297
	8298	/* 3c: 0011 1100 */
	8299	void upd7810_device::STAX_Dp()
	8300	{
	8301	WM( DE, A );
	8302	DE++;
	8303	}
	8304
	8305	/* 3d: 0011 1101 */
	8306	void upd7810_device::STAX_Hp()
	8307	{
	8308	WM( HL, A );
	8309	HL++;
	8310	}
	8311
	8312	/* 3e: 0011 1110 */
	8313	void upd7810_device::STAX_Dm()
	8314	{
	8315	WM( DE, A );
	8316	DE--;
	8317	}
	8318
	8319	/* 3f: 0011 1111 */
	8320	void upd7810_device::STAX_Hm()
	8321	{
	8322	WM( HL, A );
	8323	HL--;
	8324	}
	8325
	8326	/* 40: 0100 0000 llll llll hhhh hhhh */
	8327	void upd7810_device::CALL_w()
	8328	{
	8329	PAIR w;
	8330	w.d = 0;
	8331
	8332	RDOPARG( w.b.l );
	8333	RDOPARG( w.b.h );
	8334
	8335	SP--;
	8336	WM( SPD, PCH );
	8337	SP--;
	8338	WM( SPD, PCL );
	8339
	8340	PC = w.w.l;
	8341	}
	8342
	8343	/* 41: 0100 0001 */
	8344	void upd7810_device::INR_A()
	8345	{
	8346	UINT8 tmp = A + 1;
	8347	ZHC_ADD( tmp, A, 0 );
	8348	A = tmp;
	8349	SKIP_CY;
	8350	}
	8351
	8352	/* 42: 0100 0010 */
	8353	void upd7810_device::INR_B()
	8354	{
	8355	UINT8 tmp = B + 1;
	8356	ZHC_ADD( tmp, B, 0 );
	8357	B = tmp;
	8358	SKIP_CY;
	8359	}
	8360
	8361	/* 43: 0100 0011 */
	8362	void upd7810_device::INR_C()
	8363	{
	8364	UINT8 tmp = C + 1;
	8365	ZHC_ADD( tmp, C, 0 );
	8366	C = tmp;
	8367	SKIP_CY;
	8368	}
	8369
	8370	/* 44: 0100 0100 llll llll hhhh hhhh */
	8371	void upd7810_device::LXI_EA_s()
	8372	{
	8373	RDOPARG( EAL );
	8374	RDOPARG( EAH );
	8375	}
	8376
	8377	/* 45: 0100 0101 oooo oooo xxxx xxxx */
	8378	void upd7810_device::ONIW_wa_xx()
	8379	{
	8380	PAIR ea = m_va;
	8381	UINT8 imm;
	8382
	8383	RDOPARG( ea.b.l );
	8384	RDOPARG( imm );
	8385
	8386	if (RM( ea.d ) & imm)
	8387	PSW \|= SK;
	8388	}
	8389
	8390	/* 46: 0100 0110 xxxx xxxx */
	8391	/* ADI_A_xx already defined (long form) */
	8392
	8393	/* 47: 0100 0111 xxxx xxxx */
	8394	/* ONI_A_xx already defined (long form) */
	8395
	8396	/* 48: prefix */
	8397	void upd7810_device::PRE_48()
	8398	{
	8399	RDOP(OP2);
	8400	m_icount -= m_op48[OP2].cycles;
	8401	handle_timers(m_op48[OP2].cycles);
	8402	(this->*m_op48[OP2].opfunc)();
	8403	}
	8404
	8405	/* 49: 0100 1001 xxxx xxxx */
	8406	void upd7810_device::MVIX_BC_xx()
	8407	{
	8408	UINT8 imm;
	8409	RDOPARG( imm );
	8410	WM( BC, imm );
	8411	}
	8412
	8413	/* 4a: 0100 1010 xxxx xxxx */
	8414	void upd7810_device::MVIX_DE_xx()
	8415	{
	8416	UINT8 imm;
	8417	RDOPARG( imm );
	8418	WM( DE, imm );
	8419	}
	8420
	8421	/* 4b: 0100 1011 xxxx xxxx */
	8422	void upd7810_device::MVIX_HL_xx()
	8423	{
	8424	UINT8 imm;
	8425	RDOPARG( imm );
	8426	WM( HL, imm );
	8427	}
	8428
	8429	/* 4c: prefix */
	8430	void upd7810_device::PRE_4C()
	8431	{
	8432	RDOP(OP2);
	8433	m_icount -= m_op4C[OP2].cycles;
	8434	handle_timers(m_op4C[OP2].cycles);
	8435	(this->*m_op4C[OP2].opfunc)();
	8436	}
	8437
	8438	/* 4d: prefix */
	8439	void upd7810_device::PRE_4D()
	8440	{
	8441	RDOP(OP2);
	8442	m_icount -= m_op4D[OP2].cycles;
	8443	handle_timers(m_op4D[OP2].cycles);
	8444	(this->*m_op4D[OP2].opfunc)();
	8445	}
	8446
	8447	/* 4e: 0100 111d dddd dddd */
	8448	void upd7810_device::JRE()
	8449	{
	8450	UINT8 offs;
	8451	RDOPARG( offs );
	8452	if (OP & 0x01)
	8453	PC -= 256 - offs;
	8454	else
	8455	PC += offs;
	8456	}
	8457
	8458	/* 50: 0101 0000 */
	8459	void upd7810_device::EXH()
	8460	{
	8461	UINT16 tmp;
	8462	tmp = HL; HL = HL2; HL2 = tmp;
	8463	}
	8464
	8465	/* 51: 0101 0001 */
	8466	void upd7810_device::DCR_A()
	8467	{
	8468	UINT8 tmp = A - 1;
	8469	ZHC_SUB( tmp, A, 0 );
	8470	A = tmp;
	8471	SKIP_CY;
	8472	}
	8473
	8474	/* 52: 0101 0010 */
	8475	void upd7810_device::DCR_B()
	8476	{
	8477	UINT8 tmp = B - 1;
	8478	ZHC_SUB( tmp, B, 0 );
	8479	B = tmp;
	8480	SKIP_CY;
	8481	}
	8482
	8483	/* 53: 0101 0011 */
	8484	void upd7810_device::DCR_C()
	8485	{
	8486	UINT8 tmp = C - 1;
	8487	ZHC_SUB( tmp, C, 0 );
	8488	C = tmp;
	8489	SKIP_CY;
	8490	}
	8491
	8492	/* 54: 0101 0100 llll llll hhhh hhhh */
	8493	void upd7810_device::JMP_w()
	8494	{
	8495	PAIR w;
	8496	w.d = 0;
	8497
	8498	RDOPARG( w.b.l );
	8499	RDOPARG( w.b.h );
	8500
	8501	PCD = w.d;
	8502	}
	8503
	8504	/* 55: 0101 0101 oooo oooo xxxx xxxx */
	8505	void upd7810_device::OFFIW_wa_xx()
	8506	{
	8507	PAIR ea = m_va;
	8508	UINT8 imm;
	8509
	8510	RDOPARG( ea.b.l );
	8511	RDOPARG( imm );
	8512
	8513	if (0 == (RM( ea.d ) & imm))
	8514	PSW \|= SK;
	8515	}
	8516
	8517	/* 56: 0101 0110 xxxx xxxx */
	8518	/* ACI_A_xx already defined (long form) */
	8519
	8520	/* 57: 0101 0111 xxxx xxxx */
	8521	/* OFFI_A_xx already defined (long form) */
	8522
	8523	/* 58: 0101 1000 oooo oooo (7810 only) */
	8524	void upd7810_device::BIT_0_wa()
	8525	{
	8526	PAIR ea = m_va;
	8527
	8528	RDOPARG( ea.b.l );
	8529
	8530	if (RM( ea.d ) & 0x01)
	8531	PSW \|= SK;
	8532	}
	8533
	8534	/* 59: 0101 1001 oooo oooo (7810 only) */
	8535	void upd7810_device::BIT_1_wa()
	8536	{
	8537	PAIR ea = m_va;
	8538
	8539	RDOPARG( ea.b.l );
	8540
	8541	if (RM( ea.d ) & 0x02)
	8542	PSW \|= SK;
	8543	}
	8544
	8545	/* 5a: 0101 1010 oooo oooo (7810 only) */
	8546	void upd7810_device::BIT_2_wa()
	8547	{
	8548	PAIR ea = m_va;
	8549
	8550	RDOPARG( ea.b.l );
	8551
	8552	if (RM( ea.d ) & 0x04)
	8553	PSW \|= SK;
	8554	}
	8555
	8556	/* 5b: 0101 1011 oooo oooo (7810 only) */
	8557	void upd7810_device::BIT_3_wa()
	8558	{
	8559	PAIR ea = m_va;
	8560
	8561	RDOPARG( ea.b.l );
	8562
	8563	if (RM( ea.d ) & 0x08)
	8564	PSW \|= SK;
	8565	}
	8566
	8567	/* 5c: 0101 1100 oooo oooo (7810 only) */
	8568	void upd7810_device::BIT_4_wa()
	8569	{
	8570	PAIR ea = m_va;
	8571
	8572	RDOPARG( ea.b.l );
	8573
	8574	if (RM( ea.d ) & 0x10)
	8575	PSW \|= SK;
	8576	}
	8577
	8578	/* 5d: 0101 1101 oooo oooo (7810 only) */
	8579	void upd7810_device::BIT_5_wa()
	8580	{
	8581	PAIR ea = m_va;
	8582
	8583	RDOPARG( ea.b.l );
	8584
	8585	if (RM( ea.d ) & 0x20)
	8586	PSW \|= SK;
	8587	}
	8588
	8589	/* 5e: 0101 1110 oooo oooo (7810 only) */
	8590	void upd7810_device::BIT_6_wa()
	8591	{
	8592	PAIR ea = m_va;
	8593
	8594	RDOPARG( ea.b.l );
	8595
	8596	if (RM( ea.d ) & 0x40)
	8597	PSW \|= SK;
	8598	}
	8599
	8600	/* 5f: 0101 1111 oooo oooo (7810 only) */
	8601	void upd7810_device::BIT_7_wa()
	8602	{
	8603	PAIR ea = m_va;
	8604
	8605	RDOPARG( ea.b.l );
	8606
	8607	if (RM( ea.d ) & 0x80)
	8608	PSW \|= SK;
	8609	}
	8610
	8611	/* 5d: 0101 1111 bbbb bbbb (7807 only) */
	8612	void upd7810_device::SKN_bit()
	8613	{
	8614	UINT8 imm;
	8615	int val;
	8616
	8617	RDOPARG( imm );
	8618
	8619	switch( imm & 0x1f )
	8620	{
	8621	case 0x10: /* PA */
	8622	val = RP( UPD7810_PORTA );
	8623	break;
	8624	case 0x11: /* PB */
	8625	val = RP( UPD7810_PORTB );
	8626	break;
	8627	case 0x12: /* PC */
	8628	val = RP( UPD7810_PORTC );
	8629	break;
	8630	case 0x13: /* PD */
	8631	val = RP( UPD7810_PORTD );
	8632	break;
	8633	case 0x15: /* PF */
	8634	val = RP( UPD7810_PORTF );
	8635	break;
	8636	case 0x16: /* MKH */
	8637	val = MKH;
	8638	break;
	8639	case 0x17: /* MKL */
	8640	val = MKL;
	8641	break;
	8642	case 0x19: /* SMH */
	8643	val = SMH;
	8644	break;
	8645	case 0x1b: /* EOM */
	8646	val = EOM;
	8647	break;
	8648	case 0x1d: /* TMM */
	8649	val = TMM;
	8650	break;
	8651	case 0x1e: /* PT */
	8652	val = RP( UPD7807_PORTT );
	8653	break;
	8654	default:
	8655	logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", tag(), OP, imm, PC);
	8656	val = 0;
	8657	break;
	8658	}
	8659
	8660	if (~val & (1 << (imm >> 5)))
	8661	PSW \|= SK;
	8662	}
	8663
	8664	/* 58: 0101 1000 bbbb bbbb (7807 only) */
	8665	void upd7810_device::SETB()
	8666	{
	8667	UINT8 imm;
	8668	int bit;
	8669
	8670	RDOPARG( imm );
	8671	bit = imm >> 5;
	8672
	8673	switch( imm & 0x1f )
	8674	{
	8675	case 0x10: /* PA */
	8676	WP( UPD7810_PORTA, RP( UPD7810_PORTA ) \| (1 << bit));
	8677	break;
	8678	case 0x11: /* PB */
	8679	WP( UPD7810_PORTB, RP( UPD7810_PORTB ) \| (1 << bit));
	8680	break;
	8681	case 0x12: /* PC */
	8682	WP( UPD7810_PORTC, RP( UPD7810_PORTC ) \| (1 << bit));
	8683	break;
	8684	case 0x13: /* PD */
	8685	WP( UPD7810_PORTD, RP( UPD7810_PORTD ) \| (1 << bit));
	8686	break;
	8687	case 0x15: /* PF */
	8688	WP( UPD7810_PORTF, RP( UPD7810_PORTF ) \| (1 << bit));
	8689	break;
	8690	case 0x16: /* MKH */
	8691	MKH \|= (1 << bit);
	8692	break;
	8693	case 0x17: /* MKL */
	8694	MKL \|= (1 << bit);
	8695	break;
	8696	case 0x19: /* SMH */
	8697	SMH \|= (1 << bit);
	8698	break;
	8699	case 0x1b: /* EOM */
	8700	EOM \|= (1 << bit);
	8701	break;
	8702	case 0x1d: /* TMM */
	8703	TMM \|= (1 << bit);
	8704	break;
	8705	// case 0x1e: /* PT */
	8706	// PT is input only
	8707	// break;
	8708	default:
	8709	logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", tag(), OP, imm, PC);
	8710	break;
	8711	}
	8712	}
	8713
	8714	/* 5b: 0101 1011 bbbb bbbb (7807 only) */
	8715	void upd7810_device::CLR()
	8716	{
	8717	UINT8 imm;
	8718	int bit;
	8719
	8720	RDOPARG( imm );
	8721	bit = imm >> 5;
	8722
	8723	switch( imm & 0x1f )
	8724	{
	8725	case 0x10: /* PA */
	8726	WP( UPD7810_PORTA, RP( UPD7810_PORTA ) & ~(1 << bit));
	8727	break;
	8728	case 0x11: /* PB */
	8729	WP( UPD7810_PORTB, RP( UPD7810_PORTB ) & ~(1 << bit));
	8730	break;
	8731	case 0x12: /* PC */
	8732	WP( UPD7810_PORTC, RP( UPD7810_PORTC ) & ~(1 << bit));
	8733	break;
	8734	case 0x13: /* PD */
	8735	WP( UPD7810_PORTD, RP( UPD7810_PORTD ) & ~(1 << bit));
	8736	break;
	8737	case 0x15: /* PF */
	8738	WP( UPD7810_PORTF, RP( UPD7810_PORTF ) & ~(1 << bit));
	8739	break;
	8740	case 0x16: /* MKH */
	8741	MKH &= ~(1 << bit);
	8742	break;
	8743	case 0x17: /* MKL */
	8744	MKL &= ~(1 << bit);
	8745	break;
	8746	case 0x19: /* SMH */
	8747	SMH &= ~(1 << bit);
	8748	break;
	8749	case 0x1b: /* EOM */
	8750	EOM &= ~(1 << bit);
	8751	break;
	8752	case 0x1d: /* TMM */
	8753	TMM &= ~(1 << bit);
	8754	break;
	8755	// case 0x1e: /* PT */
	8756	// PT is input only
	8757	// break;
	8758	default:
	8759	logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", tag(), OP, imm, PC);
	8760	break;
	8761	}
	8762	}
	8763
	8764	/* 5d: 0101 1111 bbbb bbbb (7807 only) */
	8765	void upd7810_device::SK_bit()
	8766	{
	8767	UINT8 imm;
	8768	int val;
	8769
	8770	RDOPARG( imm );
	8771
	8772	switch( imm & 0x1f )
	8773	{
	8774	case 0x10: /* PA */
	8775	val = RP( UPD7810_PORTA );
	8776	break;
	8777	case 0x11: /* PB */
	8778	val = RP( UPD7810_PORTB );
	8779	break;
	8780	case 0x12: /* PC */
	8781	val = RP( UPD7810_PORTC );
	8782	break;
	8783	case 0x13: /* PD */
	8784	val = RP( UPD7810_PORTD );
	8785	break;
	8786	case 0x15: /* PF */
	8787	val = RP( UPD7810_PORTF );
	8788	break;
	8789	case 0x16: /* MKH */
	8790	val = MKH;
	8791	break;
	8792	case 0x17: /* MKL */
	8793	val = MKL;
	8794	break;
	8795	case 0x19: /* SMH */
	8796	val = SMH;
	8797	break;
	8798	case 0x1b: /* EOM */
	8799	val = EOM;
	8800	break;
	8801	case 0x1d: /* TMM */
	8802	val = TMM;
	8803	break;
	8804	case 0x1e: /* PT */
	8805	val = RP( UPD7807_PORTT );
	8806	break;
	8807	default:
	8808	logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", tag(), OP, imm, PC);
	8809	val = 0;
	8810	break;
	8811	}
	8812
	8813	if (val & (1 << (imm >> 5)))
	8814	PSW \|= SK;
	8815	}
	8816
	8817	/* 60:*/
	8818	void upd7810_device::PRE_60()
	8819	{
	8820	RDOP(OP2);
	8821	m_icount -= m_op60[OP2].cycles;
	8822	handle_timers(m_op60[OP2].cycles);
	8823	(this->*m_op60[OP2].opfunc)();
	8824	}
	8825
	8826	/* 61: 0110 0001 */
	8827	void upd7810_device::DAA()
	8828	{
	8829	UINT8 l = A & 0x0f, h = A >> 4, tmp, adj = 0x00, old_cy = PSW & CY;
	8830
	8831	if (0 == (PSW & HC))
	8832	{
	8833	if (l < 10)
	8834	{
	8835	if (!(h < 10 && 0 == (PSW & CY)))
	8836	adj = 0x60;
	8837	}
	8838	else
	8839	{
	8840	if (h < 9 && 0 == (PSW & CY))
	8841	adj = 0x06;
	8842	else
	8843	adj = 0x66;
	8844	}
	8845	}
	8846	else
	8847	if (l < 3)
	8848	{
	8849	if (h < 10 && 0 == (PSW & CY))
	8850	adj = 0x06;
	8851	else
	8852	adj = 0x66;
	8853	}
	8854	tmp = A + adj;
	8855	ZHC_ADD( tmp, A, PSW & CY );
	8856	PSW \|= old_cy;
	8857	A = tmp;
	8858	}
	8859
	8860	/* 62: 0110 0010 */
	8861	void upd7810_device::RETI()
	8862	{
	8863	PCL = RM( SPD );
	8864	SP++;
	8865	PCH = RM( SPD );
	8866	SP++;
	8867	PSW = RM( SPD );
	8868	SP++;
	8869	}
	8870
	8871	/* 63: 0110 0011 oooo oooo */
	8872	void upd7810_device::STAW_wa()
	8873	{
	8874	PAIR ea = m_va;
	8875
	8876	RDOPARG( ea.b.l );
	8877
	8878	WM( ea.d, A );
	8879	}
	8880
	8881	/* 64: prefix */
	8882	void upd7810_device::PRE_64()
	8883	{
	8884	RDOP(OP2);
	8885	m_icount -= m_op64[OP2].cycles;
	8886	handle_timers(m_op64[OP2].cycles);
	8887	(this->*m_op64[OP2].opfunc)();
	8888	}
	8889
	8890	/* 65: 0110 0101 oooo oooo xxxx xxxx */
	8891	void upd7810_device::NEIW_wa_xx()
	8892	{
	8893	PAIR ea = m_va;
	8894	UINT8 tmp, m, imm;
	8895
	8896	RDOPARG( ea.b.l );
	8897	RDOPARG( imm );
	8898	m = RM( ea.d );
	8899	tmp = m - imm;
	8900	ZHC_SUB( tmp, m, 0 );
	8901	SKIP_NZ;
	8902	}
	8903
	8904	/* 66: 0110 0110 xxxx xxxx */
	8905	/* SUI_A_xx already defined (long form) */
	8906
	8907	/* 67: 0110 0111 xxxx xxxx */
	8908	/* NEI_A_xx already defined (long form) */
	8909
	8910	/* 68: 0110 1000 xxxx xxxx */
	8911	void upd7810_device::MVI_V_xx()
	8912	{
	8913	RDOPARG( V );
	8914	}
	8915
	8916	/* 69: 0110 1001 xxxx xxxx */
	8917	void upd7810_device::MVI_A_xx()
	8918	{
	8919	if (PSW & L1) { /* overlay active? */
	8920	PC++;
	8921	return; /* NOP */
	8922	}
	8923	RDOPARG( A );
	8924	PSW \|= L1;
	8925	}
	8926
	8927	/* 6a: 0110 1010 xxxx xxxx */
	8928	void upd7810_device::MVI_B_xx()
	8929	{
	8930	RDOPARG( B );
	8931	}
	8932
	8933	/* 6b: 0110 1011 xxxx xxxx */
	8934	void upd7810_device::MVI_C_xx()
	8935	{
	8936	RDOPARG( C );
	8937	}
	8938
	8939	/* 6c: 0110 1100 xxxx xxxx */
	8940	void upd7810_device::MVI_D_xx()
	8941	{
	8942	RDOPARG( D );
	8943	}
	8944
	8945	/* 6d: 0110 1101 xxxx xxxx */
	8946	void upd7810_device::MVI_E_xx()
	8947	{
	8948	RDOPARG( E );
	8949	}
	8950
	8951	/* 6e: 0110 1110 xxxx xxxx */
	8952	void upd7810_device::MVI_H_xx()
	8953	{
	8954	RDOPARG( H );
	8955	}
	8956
	8957	/* 6f: 0110 1111 xxxx xxxx */
	8958	void upd7810_device::MVI_L_xx()
	8959	{
	8960	if (PSW & L0) { /* overlay active? */
	8961	PC++;
	8962	return; /* NOP */
	8963	}
	8964	RDOPARG( L );
	8965	PSW \|= L0;
	8966	}
	8967
	8968	/* 70: prefix */
	8969	void upd7810_device::PRE_70()
	8970	{
	8971	RDOP(OP2);
	8972	m_icount -= m_op70[OP2].cycles;
	8973	handle_timers(m_op70[OP2].cycles);
	8974	(this->*m_op70[OP2].opfunc)();
	8975	}
	8976
	8977	/* 71: 0111 0001 oooo oooo xxxx xxxx */
	8978	void upd7810_device::MVIW_wa_xx()
	8979	{
	8980	PAIR ea = m_va;
	8981	UINT8 imm;
	8982
	8983	RDOPARG( ea.b.l );
	8984	RDOPARG( imm );
	8985
	8986	WM( ea.d, imm );
	8987	}
	8988
	8989	/* 72: 0111 0010 */
	8990	void upd7810_device::SOFTI()
	8991	{
	8992	SP--;
	8993	WM( SPD, PSW );
	8994	SP--;
	8995	WM( SPD, PCH );
	8996	SP--;
	8997	WM( SPD, PCL );
	8998
	8999	PC = 0x0060;
	9000	}
	9001
	9002	/* 74: prefix */
	9003	void upd7810_device::PRE_74()
	9004	{
	9005	RDOP(OP2);
	9006	m_icount -= m_op74[OP2].cycles;
	9007	handle_timers(m_op74[OP2].cycles);
	9008	(this->*m_op74[OP2].opfunc)();
	9009	}
	9010
	9011	/* 75: 0111 0101 oooo oooo xxxx xxxx */
	9012	void upd7810_device::EQIW_wa_xx()
	9013	{
	9014	PAIR ea = m_va;
	9015	UINT8 tmp, m, imm;
	9016
	9017	RDOPARG( ea.b.l );
	9018	RDOPARG( imm );
	9019	m = RM( ea.d );
	9020	tmp = m - imm;
	9021	ZHC_SUB( tmp, m, 0 );
	9022	SKIP_Z;
	9023	}
	9024
	9025	/* 76: 0111 0110 xxxx xxxx */
	9026	/* SBI_A_xx already defined (long form) */
	9027
	9028	/* 77: 0111 0111 xxxx xxxx */
	9029	/* EQI_A_xx already defined (long form) */
	9030
	9031	/* 78: 0111 1ddd dddd dddd */
	9032	void upd7810_device::CALF()
	9033	{
	9034	PAIR w;
	9035	w.d = 0;
	9036
	9037	RDOPARG( w.b.l );
	9038	w.b.h = 0x08 + (OP & 0x07);
	9039
	9040	SP--;
	9041	WM( SPD, PCH );
	9042	SP--;
	9043	WM( SPD, PCL );
	9044
	9045	PCD = w.d;
	9046	}
	9047
	9048	/* 80: 100t tttt */
	9049	void upd7810_device::CALT()
	9050	{
	9051	PAIR w;
	9052	w.d = 0;
	9053
	9054	w.w.l = 0x80 + 2 * (OP & 0x1f);
	9055
	9056	SP--;
	9057	WM( SPD, PCH );
	9058	SP--;
	9059	WM( SPD, PCL );
	9060
	9061	PCL=RM(w.w.l);
	9062	PCH=RM(w.w.l+1);
	9063	}
	9064
	9065	/* a0: 1010 0000 */
	9066	void upd7810_device::POP_VA()
	9067	{
	9068	A = RM( SPD );
	9069	SP++;
	9070	V = RM( SPD );
	9071	SP++;
	9072	}
	9073
	9074	/* a1: 1010 0001 */
	9075	void upd7810_device::POP_BC()
	9076	{
	9077	C = RM( SPD );
	9078	SP++;
	9079	B = RM( SPD );
	9080	SP++;
	9081	}
	9082
	9083	/* a2: 1010 0010 */
	9084	void upd7810_device::POP_DE()
	9085	{
	9086	E = RM( SPD );
	9087	SP++;
	9088	D = RM( SPD );
	9089	SP++;
	9090	}
	9091
	9092	/* a3: 1010 0011 */
	9093	void upd7810_device::POP_HL()
	9094	{
	9095	L = RM( SPD );
	9096	SP++;
	9097	H = RM( SPD );
	9098	SP++;
	9099	}
	9100
	9101	/* a4: 1010 0100 */
	9102	void upd7810_device::POP_EA()
	9103	{
	9104	EAL = RM( SPD );
	9105	SP++;
	9106	EAH = RM( SPD );
	9107	SP++;
	9108	}
	9109
	9110	/* a5: 1010 0101 */
	9111	void upd7810_device::DMOV_EA_BC()
	9112	{
	9113	EA = BC;
	9114	}
	9115
	9116	/* a6: 1010 0110 */
	9117	void upd7810_device::DMOV_EA_DE()
	9118	{
	9119	EA = DE;
	9120	}
	9121
	9122	/* a7: 1010 0111 */
	9123	void upd7810_device::DMOV_EA_HL()
	9124	{
	9125	EA = HL;
	9126	}
	9127
	9128	/* a8: 1010 1000 */
	9129	void upd7810_device::INX_EA()
	9130	{
	9131	EA++;
	9132	}
	9133
	9134	/* a9: 1010 1001 */
	9135	void upd7810_device::DCX_EA()
	9136	{
	9137	EA--;
	9138	}
	9139
	9140	/* aa: 1010 1010 */
	9141	void upd7810_device::EI()
	9142	{
	9143	IFF = 1;
	9144	}
	9145
	9146	/* ab: 1010 1011 dddd dddd */
	9147	void upd7810_device::LDAX_D_xx()
	9148	{
	9149	UINT16 ea;
	9150	RDOPARG( ea );
	9151	ea += DE;
	9152	A = RM( ea );
	9153	}
	9154
	9155	/* ac: 1010 1100 */
	9156	void upd7810_device::LDAX_H_A()
	9157	{
	9158	UINT16 ea;
	9159	ea = HL + A;
	9160	A = RM( ea );
	9161	}
	9162
	9163	/* ad: 1010 1101 */
	9164	void upd7810_device::LDAX_H_B()
	9165	{
	9166	UINT16 ea;
	9167	ea = HL + B;
	9168	A = RM( ea );
	9169	}
	9170
	9171	/* ae: 1010 1110 */
	9172	void upd7810_device::LDAX_H_EA()
	9173	{
	9174	UINT16 ea;
	9175	ea = HL + EA;
	9176	A = RM( ea );
	9177	}
	9178
	9179	/* af: 1010 1111 dddd dddd */
	9180	void upd7810_device::LDAX_H_xx()
	9181	{
	9182	UINT16 ea;
	9183	RDOPARG( ea );
	9184	ea += HL;
	9185	A = RM( ea );
	9186	}
	9187
	9188	/* b0: 1011 0000 */
	9189	void upd7810_device::PUSH_VA()
	9190	{
	9191	SP--;
	9192	WM( SPD, V );
	9193	SP--;
	9194	WM( SPD, A );
	9195	}
	9196
	9197	/* b1: 1011 0001 */
	9198	void upd7810_device::PUSH_BC()
	9199	{
	9200	SP--;
	9201	WM( SPD, B );
	9202	SP--;
	9203	WM( SPD, C );
	9204	}
	9205
	9206	/* b2: 1011 0010 */
	9207	void upd7810_device::PUSH_DE()
	9208	{
	9209	SP--;
	9210	WM( SPD, D );
	9211	SP--;
	9212	WM( SPD, E );
	9213	}
	9214
	9215	/* b3: 1011 0011 */
	9216	void upd7810_device::PUSH_HL()
	9217	{
	9218	SP--;
	9219	WM( SPD, H );
	9220	SP--;
	9221	WM( SPD, L );
	9222	}
	9223
	9224	/* b4: 1011 0100 */
	9225	void upd7810_device::PUSH_EA()
	9226	{
	9227	SP--;
	9228	WM( SPD, EAH );
	9229	SP--;
	9230	WM( SPD, EAL );
	9231	}
	9232
	9233	/* b5: 1011 0101 */
	9234	void upd7810_device::DMOV_BC_EA()
	9235	{
	9236	BC = EA;
	9237	}
	9238
	9239	/* b6: 1011 0110 */
	9240	void upd7810_device::DMOV_DE_EA()
	9241	{
	9242	DE = EA;
	9243	}
	9244
	9245	/* b7: 1011 0111 */
	9246	void upd7810_device::DMOV_HL_EA()
	9247	{
	9248	HL = EA;
	9249	}
	9250
	9251	/* b8: 1011 1000 */
	9252	void upd7810_device::RET()
	9253	{
	9254	PCL = RM( SPD );
	9255	SP++;
	9256	PCH = RM( SPD );
	9257	SP++;
	9258	}
	9259
	9260	/* b9: 1011 1001 */
	9261	void upd7810_device::RETS()
	9262	{
	9263	PCL = RM( SPD );
	9264	SP++;
	9265	PCH = RM( SPD );
	9266	SP++;
	9267	PSW\|=SK; /* skip one instruction */
	9268	}
	9269
	9270	/* ba: 1011 1010 */
	9271	void upd7810_device::DI()
	9272	{
	9273	IFF = 0;
	9274	}
	9275
	9276	/* bb: 1011 1011 dddd dddd */
	9277	void upd7810_device::STAX_D_xx()
	9278	{
	9279	UINT16 ea;
	9280	RDOPARG(ea);
	9281	ea += DE;
	9282	WM( ea, A );
	9283	}
	9284
	9285	/* bc: 1011 1100 */
	9286	void upd7810_device::STAX_H_A()
	9287	{
	9288	UINT16 ea = A;
	9289	ea += HL;
	9290	WM( ea, A );
	9291	}
	9292
	9293	/* bd: 1011 1101 */
	9294	void upd7810_device::STAX_H_B()
	9295	{
	9296	UINT16 ea = B;
	9297	ea += HL;
	9298	WM( ea, A );
	9299	}
	9300
	9301	/* be: 1011 1110 */
	9302	void upd7810_device::STAX_H_EA()
	9303	{
	9304	UINT16 ea = EA;
	9305	ea += HL;
	9306	WM( ea, A );
	9307	}
	9308
	9309	/* bf: 1011 1111 dddd dddd */
	9310	void upd7810_device::STAX_H_xx()
	9311	{
	9312	UINT16 ea;
	9313	RDOPARG( ea );
	9314	ea += HL;
	9315	WM( ea, A );
	9316	}
	9317
	9318	/* c0: 11dd dddd */
	9319	void upd7810_device::JR()
	9320	{
	9321	INT8 offs = (INT8)(OP << 2) >> 2;
	9322	PC += offs;
	9323	}
	9324
	9325	/*********************/
	9326	/* */
	9327	/* 7801 instructions */
	9328	/* */
	9329	/*********************/
	9330
	9331	void upd7810_device::CALT_7801()
	9332	{
	9333	PAIR w;
	9334	w.d = 0;
	9335
	9336	w.w.l = 0x80 + 2 * (OP & 0x3f);
	9337
	9338	SP--;
	9339	WM( SPD, PCH );
	9340	SP--;
	9341	WM( SPD, PCL );
	9342
	9343	PCL=RM(w.w.l);
	9344	PCH=RM(w.w.l+1);
	9345	}
	9346
	9347	/* DCR(W) and INR(W) instructions do not modify the CY register on at least 78c05 and 78c06 */
	9348	void upd7810_device::DCR_A_7801()
	9349	{
	9350	UINT32 old_CY = PSW & CY;
	9351	DCR_A();
	9352	PSW = ( PSW & ~CY ) \| old_CY;
	9353	}
	9354
	9355	void upd7810_device::DCR_B_7801()
	9356	{
	9357	UINT32 old_CY = PSW & CY;
	9358	DCR_B();
	9359	PSW = ( PSW & ~CY ) \| old_CY;
	9360	}
	9361
	9362	void upd7810_device::DCR_C_7801()
	9363	{
	9364	UINT32 old_CY = PSW & CY;
	9365	DCR_C();
	9366	PSW = ( PSW & ~CY ) \| old_CY;
	9367	}
	9368
	9369	void upd7810_device::DCRW_wa_7801()
	9370	{
	9371	UINT32 old_CY = PSW & CY;
	9372	DCRW_wa();
	9373	PSW = ( PSW & ~CY ) \| old_CY;
	9374	}
	9375
	9376	void upd7810_device::INR_A_7801()
	9377	{
	9378	UINT32 old_CY = PSW & CY;
	9379	INR_A();
	9380	PSW = ( PSW & ~CY ) \| old_CY;
	9381	}
	9382
	9383	void upd7810_device::INR_B_7801()
	9384	{
	9385	UINT32 old_CY = PSW & CY;
	9386	INR_B();
	9387	PSW = ( PSW & ~CY ) \| old_CY;
	9388	}
	9389
	9390	void upd7810_device::INR_C_7801()
	9391	{
	9392	UINT32 old_CY = PSW & CY;
	9393	INR_C();
	9394	PSW = ( PSW & ~CY ) \| old_CY;
	9395	}
	9396
	9397	void upd7810_device::INRW_wa_7801()
	9398	{
	9399	UINT32 old_CY = PSW & CY;
	9400	INRW_wa();
	9401	PSW = ( PSW & ~CY ) \| old_CY;
	9402	}
	9403
	9404	void upd7810_device::IN()
	9405	{
	9406	logerror("unimplemented instruction: IN\n");
	9407	}
	9408
	9409	void upd7810_device::OUT()
	9410	{
	9411	logerror("unimplemented instruction: OUT\n");
	9412	}
	9413
	9414	void upd7810_device::MOV_A_S()
	9415	{
	9416	logerror("unimplemented instruction: MOV_A_S\n");
	9417	}
	9418
	9419	void upd7810_device::MOV_S_A()
	9420	{
	9421	logerror("unimplemented instruction: MOV_A_S\n");
	9422	}
	9423
	9424	void upd7810_device::PEN()
	9425	{
	9426	logerror("unimplemented instruction: PEN\n");
	9427	}
	9428
	9429	void upd7810_device::PER()
	9430	{
	9431	logerror("unimplemented instruction: PER\n");
	9432	}
	9433
	9434	void upd7810_device::PEX()
	9435	{
	9436	logerror("unimplemented instruction: PEX\n");
	9437	}
	9438
	9439	void upd7810_device::SIO()
	9440	{
	9441	logerror("unimplemented instruction: SIO\n");
	9442	}
	9443
	9444	void upd7810_device::SKIT_F0()
	9445	{
	9446	if (IRR & INTF0)
	9447	PSW \|= SK;
	9448	IRR &= ~INTF0;
	9449	}
	9450
	9451	void upd7810_device::SKNIT_F0()
	9452	{
	9453	logerror("unimplemented instruction: SKNIT_F0\n");
	9454	}
	9455
	9456	void upd7810_device::STM()
	9457	{
	9458	m_ovc0 = ( ( TMM & 0x04 ) ? 16 * 8 : 8 ) * TM0;
	9459	}
	9460
	9461	void upd7810_device::STM_7801()
	9462	{
	9463	/* Set the timer flip/fliop */
	9464	TO = 1;
	9465	m_to_func(TO);
	9466
	9467	/* Reload the timer */
	9468	m_ovc0 = 16 * ( TM0 + ( ( TM1 & 0x0f ) << 8 ) );
	9469	}
	9470
	9471	void upd7810_device::MOV_MC_A_7801()
	9472	{
	9473	/* On the 7801 the mode C bits function as follows: */
	9474	/* Cn=1 Cn=0 */
	9475	/* PC0 Input Output */
	9476	/* PC1 Input Output */
	9477	/* PC2 Input -SCS Input */
	9478	/* PC3 Output SAK Output */
	9479	/* PC4 Output To Output */
	9480	/* PC5 Output IO/-M Output */
	9481	/* PC6 Output HLDA Output */
	9482	/* PC7 Input HOLD Input */
	9483	MC = 0x84 \| ( ( A & 0x02 ) ? 0x02 : 0x00 ) \| ( ( A & 0x01 ) ? 0x01 : 0x00 );
	9484	}

Property changes on: trunk/src/emu/cpu/upd7810/upd7810_opcodes.c
Added: svn:mime-type + text/plain Added: svn:eol-style + native

trunk/src/emu/cpu/upd7810/upd7810.c
r30937	r30938
407	407	#include "emu.h"
408	408	#include "debugger.h"
409	409	#include "upd7810.h"
	410	#include "upd7810_macros.h"
410	411
411	412
412	413	const device_type UPD7810 = &device_creator<upd7810_device>;
r30937	r30938
541	542	return CPU_DISASSEMBLE_NAME(upd78c05)(this, buffer, pc, oprom, opram, options);
542	543	}
543	544
544
545		#define CY 0x01
546		#define F1 0x02
547		#define L0 0x04
548		#define L1 0x08
549		#define HC 0x10
550		#define SK 0x20
551		#define Z 0x40
552		#define F7 0x80
553
554		/* IRR flags */
555		#define INTNMI 0x0001
556		#define INTFT0 0x0002
557		#define INTFT1 0x0004
558		#define INTF1 0x0008
559		#define INTF2 0x0010
560		#define INTFE0 0x0020
561		#define INTFE1 0x0040
562		#define INTFEIN 0x0080
563		#define INTFAD 0x0100
564		#define INTFSR 0x0200
565		#define INTFST 0x0400
566		#define INTER 0x0800
567		#define INTOV 0x1000
568		#define INTF0 0x2000
569
570		/* ITF flags */
571		#define INTAN4 0x0001
572		#define INTAN5 0x0002
573		#define INTAN6 0x0004
574		#define INTAN7 0x0008
575		#define INTSB 0x0010
576
577		#define PPC m_ppc.w.l
578		#define PC m_pc.w.l
579		#define PCL m_pc.b.l
580		#define PCH m_pc.b.h
581		#define PCD m_pc.d
582		#define SP m_sp.w.l
583		#define SPL m_sp.b.l
584		#define SPH m_sp.b.h
585		#define SPD m_sp.d
586		#define PSW m_psw
587		#define OP m_op
588		#define OP2 m_op2
589		#define IFF m_iff
590		#define EA m_ea.w.l
591		#define EAL m_ea.b.l
592		#define EAH m_ea.b.h
593		#define VA m_va.w.l
594		#define V m_va.b.h
595		#define A m_va.b.l
596		#define VAD m_va.d
597		#define BC m_bc.w.l
598		#define B m_bc.b.h
599		#define C m_bc.b.l
600		#define DE m_de.w.l
601		#define D m_de.b.h
602		#define E m_de.b.l
603		#define HL m_hl.w.l
604		#define H m_hl.b.h
605		#define L m_hl.b.l
606		#define EA2 m_ea2.w.l
607		#define VA2 m_va2.w.l
608		#define BC2 m_bc2.w.l
609		#define DE2 m_de2.w.l
610		#define HL2 m_hl2.w.l
611
612		#define OVC0 m_ovc0
613		#define OVC1 m_ovc1
614		#define OVCE m_ovce
615		#define OVCF m_ovcf
616		#define OVCS m_ovcs
617		#define EDGES m_edges
618
619		#define CNT0 m_cnt.b.l
620		#define CNT1 m_cnt.b.h
621		#define TM0 m_tm.b.l
622		#define TM1 m_tm.b.h
623		#define ECNT m_ecnt.w.l
624		#define ECPT m_ecnt.w.h
625		#define ETM0 m_etm.w.l
626		#define ETM1 m_etm.w.h
627
628		#define MA m_ma
629		#define MB m_mb
630		#define MCC m_mcc
631		#define MC m_mc
632		#define MM m_mm
633		#define MF m_mf
634		#define TMM m_tmm
635		#define ETMM m_etmm
636		#define EOM m_eom
637		#define SML m_sml
638		#define SMH m_smh
639		#define PANM m_panm
640		#define ANM m_anm
641		#define MKL m_mkl
642		#define MKH m_mkh
643		#define ZCM m_zcm
644
645		#define CR0 m_cr0
646		#define CR1 m_cr1
647		#define CR2 m_cr2
648		#define CR3 m_cr3
649		#define RXB m_rxb
650		#define TXB m_txb
651
652		#define RXD m_rxd
653		#define TXD m_txd
654		#define SCK m_sck
655		#define TI m_ti
656		#define TO m_to
657		#define CI m_ci
658		#define CO0 m_co0
659		#define CO1 m_co1
660
661		#define IRR m_irr
662		#define ITF m_itf
663
664
665		#define RDOP(O) O = m_direct->read_decrypted_byte(PCD); PC++
666		#define RDOPARG(A) A = m_direct->read_raw_byte(PCD); PC++
667		#define RM(A) m_program->read_byte(A)
668		#define WM(A,V) m_program->write_byte(A,V)
669
670		#define ZHC_ADD(after,before,carry) \
671		if (after == 0) PSW \|= Z; else PSW &= ~Z; \
672		if (after == before) \
673		PSW = (PSW&~CY) \| (carry); \
674		else if (after < before) \
675		PSW \|= CY; \
676		else \
677		PSW &= ~CY; \
678		if ((after & 15) < (before & 15)) \
679		PSW \|= HC; \
680		else \
681		PSW &= ~HC;
682		#define ZHC_SUB(after,before,carry) \
683		if (after == 0) PSW \|= Z; else PSW &= ~Z; \
684		if (before == after) \
685		PSW = (PSW & ~CY) \| (carry); \
686		else if (after > before) \
687		PSW \|= CY; \
688		else \
689		PSW &= ~CY; \
690		if ((after & 15) > (before & 15)) \
691		PSW \|= HC; \
692		else \
693		PSW &= ~HC;
694		#define SKIP_CY if (CY == (PSW & CY)) PSW \|= SK
695		#define SKIP_NC if (0 == (PSW & CY)) PSW \|= SK
696		#define SKIP_Z if (Z == (PSW & Z)) PSW \|= SK
697		#define SKIP_NZ if (0 == (PSW & Z)) PSW \|= SK
698		#define SET_Z(n) if (n) PSW &= ~Z; else PSW \|= Z
699
700	545	UINT8 upd7810_device::RP(offs_t port)
701	546	{
702	547	UINT8 data = 0xff;
r30937	r30938
1977	1822	}
1978	1823	}
1979	1824
1980		#include "7810tbl.inc"
1981		#include "7810ops.inc"
1982
1983	1825	void upd7810_device::device_reset()
1984	1826	{
1985	1827	m_ppc.d = 0;
r30937	r30938
2092	1934	m_ovc0 = ( ( TMM & 0x04 ) ? 16 * 8 : 8 ) * TM0;
2093	1935	}
2094	1936
2095
2096	1937	void upd7810_device::execute_run()
2097	1938	{
2098	1939	do

trunk/src/emu/cpu/cpu.mak
r30937	r30938
1774	1774	ifneq ($(filter UPD7810,$(CPUS)),)
1775	1775	OBJDIRS += $(CPUOBJ)/upd7810
1776	1776	CPUOBJS += $(CPUOBJ)/upd7810/upd7810.o
1777		DASMOBJS += $(CPUOBJ)/upd7810/7810dasm.o
	1777	CPUOBJS += $(CPUOBJ)/upd7810/upd7810_opcodes.o
	1778	CPUOBJS += $(CPUOBJ)/upd7810/upd7810_table.o
	1779	DASMOBJS += $(CPUOBJ)/upd7810/upd7810_dasm.o
1778	1780	endif
1779	1781
	1782	$(CPUOBJ)/upd7810/upd7810_opcodes.o: $(CPUSRC)/upd7810/upd7810_opcodes.c \
	1783	$(CPUSRC)/upd7810/upd7810_macros.h
	1784
1780	1785	$(CPUOBJ)/upd7810/upd7810.o: $(CPUSRC)/upd7810/upd7810.c \
1781		$(CPUSRC)/upd7810/7810tbl.inc \
1782		$(CPUSRC)/upd7810/7810ops.inc \
1783		$(CPUSRC)/upd7810/upd7810.h
	1786	$(CPUSRC)/upd7810/upd7810.h \
	1787	$(CPUSRC)/upd7810/upd7810_macros.h
1784	1788
1785	1789
1786
1787	1790	#-------------------------------------------------
1788	1791	# Nintendo Minx
1789	1792	#@src/emu/cpu/minx/minx.h,CPUS += MINX

199869 Revisions