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r30937 Wednesday 11th June, 2014 at 09:17:41 UTC by Alex Jackson

namcos1.c: Completely rewrote the emulation of the CUS117 MMU. The MMU is no longer emulated by modifying address maps at runtime, an operation which has become excessively slow as the core memory system has accumulated features and complexity over the years. Instead, the MMU is now a device which works on similar principles to the address_map_bank_device. The recent multisession regression is fixed, all games in the driver should now run substantially faster, and most importantly the driver code is now much cleaner and easier to understand. [Alex Jackson]

[src/mame]	mame.mak
[src/mame/drivers]	namcos1.c
[src/mame/includes]	namcos1.h
[src/mame/machine]	c117.c* c117.h* namcos1.c
[src/mame/video]	namcos1.c

trunk/src/mame/drivers/namcos1.c

r30936	r30937
60	60	Memory map
61	61	----------
62	62	Main, Sub CPU:
63		Address decoding is entirely handled by CUS117, which is a simple MMU providing a
64		virtual address space 23 bits wide. The chip outputs the various enable lines for
65		RAM, ROM, etc., and bits 12-21 of the virtual address (therefore bit 22 is handled
66		only internally). There are 8 banks in the 6809 address space, each one redirectable
67		to a portion of the virtual address space. The main and sub CPUs are independent,
68		each one can set up its own banks.
	63	Address decoding is entirely handled by CUS117; see machine/c117.c.
69	64
70	65	Main & sub CPU memory map:
71	66
r30936	r30937
179	174	ernesto@imagina.com
180	175
181	176	Updates by:
182		Vernon C. Brooks, Acho A. Tang, Nicola Salmoria
	177	Vernon C. Brooks, Acho A. Tang, Nicola Salmoria, Alex W. Jackson
183	178
184	179
185	180	Notes:
r30936	r30937
220	215
221	216
222	217	TODO:
223		- There is still a big mistery about the first location of tri port ram, which is
	218	- There is still a big mystery about the first location of tri port ram, which is
224	219	shared among all four CPUs. See namcos1_mcu_patch_w() for the kludge: essentially,
225	220	this location has to be 0xA6 for the games to work. However, the MCU first sets it
226	221	to 0xA6, then zeroes it - and there doesn't seem to be any code anywhere for any CPU
r30936	r30937
290	285	Sound:
291	286
292	287	Namco custom 8 channel 16-bit stereo PSG for sound effects
293		registor array based 2 channel 8-bit DAC for voice
	288	resistor array based 2 channel 8-bit DAC for voice
294	289	Yamaha YM2151+YM3012 FM chip for background music
295	290
296	291	Controls:
r30936	r30937
342	337	#include "cpu/m6809/m6809.h"
343	338	#include "cpu/m6800/m6800.h"
344	339	#include "sound/2151intf.h"
345		#include "sound/dac.h"
346	340	#include "machine/nvram.h"
347	341	#include "includes/namcos1.h"
348	342
349	343
350	344	/**********************************************************************/
351	345
352		WRITE8_MEMBER(namcos1_state::namcos1_sub_firq_w)
353		{
354		m_subcpu->set_input_line(M6809_FIRQ_LINE, ASSERT_LINE);
355		}
356
357	346	WRITE8_MEMBER(namcos1_state::irq_ack_w)
358	347	{
359	348	space.device().execute().set_input_line(0, CLEAR_LINE);
360	349	}
361	350
362		WRITE8_MEMBER(namcos1_state::firq_ack_w)
363		{
364		space.device().execute().set_input_line(M6809_FIRQ_LINE, CLEAR_LINE);
365		}
366	351
367
368
369	352	READ8_MEMBER(namcos1_state::dsw_r)
370	353	{
371	354	int ret = ioport("DIPSW")->read();
r30936	r30937
423	406
424	407
425	408	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, namcos1_state )
426		AM_RANGE(0x0000, 0x1fff) AM_RAMBANK("bank1")
427		AM_RANGE(0x2000, 0x3fff) AM_RAMBANK("bank2")
428		AM_RANGE(0x4000, 0x5fff) AM_RAMBANK("bank3")
429		AM_RANGE(0x6000, 0x7fff) AM_RAMBANK("bank4")
430		AM_RANGE(0x8000, 0x9fff) AM_RAMBANK("bank5")
431		AM_RANGE(0xa000, 0xbfff) AM_RAMBANK("bank6")
432		AM_RANGE(0xc000, 0xdfff) AM_RAMBANK("bank7")
433		AM_RANGE(0xe000, 0xefff) AM_WRITE(namcos1_bankswitch_w)
434		AM_RANGE(0xf000, 0xf000) AM_WRITE(namcos1_cpu_control_w)
435		AM_RANGE(0xf200, 0xf200) AM_WRITE(namcos1_watchdog_w)
436		//  AM_RANGE(0xf400, 0xf400) AM_WRITENOP // unknown
437		AM_RANGE(0xf600, 0xf600) AM_WRITE(irq_ack_w)
438		AM_RANGE(0xf800, 0xf800) AM_WRITE(firq_ack_w)
439		AM_RANGE(0xfa00, 0xfa00) AM_WRITE(namcos1_sub_firq_w) // asserts FIRQ on CPU1
440		AM_RANGE(0xfc00, 0xfc01) AM_WRITE(namcos1_subcpu_bank_w)
441		AM_RANGE(0xe000, 0xffff) AM_ROMBANK("bank8")
	409	AM_RANGE(0x0000, 0xffff) AM_DEVREADWRITE("c117", namco_c117_device, main_r, main_w)
442	410	ADDRESS_MAP_END
443	411
444
445	412	static ADDRESS_MAP_START( sub_map, AS_PROGRAM, 8, namcos1_state )
446		AM_RANGE(0x0000, 0x1fff) AM_RAMBANK("bank9")
447		AM_RANGE(0x2000, 0x3fff) AM_RAMBANK("bank10")
448		AM_RANGE(0x4000, 0x5fff) AM_RAMBANK("bank11")
449		AM_RANGE(0x6000, 0x7fff) AM_RAMBANK("bank12")
450		AM_RANGE(0x8000, 0x9fff) AM_RAMBANK("bank13")
451		AM_RANGE(0xa000, 0xbfff) AM_RAMBANK("bank14")
452		AM_RANGE(0xc000, 0xdfff) AM_RAMBANK("bank15")
453		AM_RANGE(0xe000, 0xefff) AM_WRITE(namcos1_bankswitch_w)
454		//  AM_RANGE(0xf000, 0xf000) AM_WRITENOP // IO Chip
455		AM_RANGE(0xf200, 0xf200) AM_WRITE(namcos1_watchdog_w)
456		//  AM_RANGE(0xf400, 0xf400) AM_WRITENOP // ?
457		AM_RANGE(0xf600, 0xf600) AM_WRITE(irq_ack_w)
458		AM_RANGE(0xf800, 0xf800) AM_WRITE(firq_ack_w)
459		AM_RANGE(0xe000, 0xffff) AM_ROMBANK("bank16")
	413	AM_RANGE(0x0000, 0xffff) AM_DEVREADWRITE("c117", namco_c117_device, sub_r, sub_w)
460	414	ADDRESS_MAP_END
461	415
	416	static ADDRESS_MAP_START( virtual_map, AS_PROGRAM, 8, namcos1_state )
	417	AM_RANGE(0x2c0000, 0x2c1fff) AM_WRITE(namcos1_3dcs_w)
	418	AM_RANGE(0x2e0000, 0x2e7fff) AM_RAM_WRITE(namcos1_paletteram_w) AM_SHARE("paletteram")
	419	AM_RANGE(0x2f0000, 0x2f7fff) AM_RAM_WRITE(namcos1_videoram_w) AM_SHARE("videoram")
	420	AM_RANGE(0x2f8000, 0x2f9fff) AM_READWRITE(no_key_r, no_key_w)
	421	AM_RANGE(0x2fc000, 0x2fcfff) AM_RAM_WRITE(namcos1_spriteram_w) AM_SHARE("spriteram")
	422	AM_RANGE(0x2fd000, 0x2fd01f) AM_RAM AM_SHARE("pfcontrol") AM_MIRROR(0xfe0)
	423	AM_RANGE(0x2fe000, 0x2fe3ff) AM_DEVREADWRITE("namco", namco_cus30_device, namcos1_cus30_r, namcos1_cus30_w) AM_MIRROR(0xc00) /* PSG ( Shared ) */
	424	AM_RANGE(0x2ff000, 0x2ff7ff) AM_RAM AM_SHARE("triram") AM_MIRROR(0x800)
	425	AM_RANGE(0x300000, 0x307fff) AM_RAM
	426	AM_RANGE(0x400000, 0x7fffff) AM_ROM AM_REGION("user1", 0)
	427	ADDRESS_MAP_END
462	428
	429
463	430	static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, namcos1_state )
464		AM_RANGE(0x0000, 0x3fff) AM_ROMBANK("bank17")   /* Banked ROMs */
	431	AM_RANGE(0x0000, 0x3fff) AM_ROMBANK("soundbank")   /* Banked ROMs */
465	432	AM_RANGE(0x4000, 0x4001) AM_DEVREAD("ymsnd", ym2151_device, status_r)
466	433	AM_RANGE(0x4000, 0x4001) AM_DEVREADWRITE("ymsnd", ym2151_device, read, write)
467	434	AM_RANGE(0x5000, 0x53ff) AM_DEVREADWRITE("namco", namco_cus30_device, namcos1_cus30_r, namcos1_cus30_w) AM_MIRROR(0x400) /* PSG ( Shared ) */
468		AM_RANGE(0x7000, 0x77ff) AM_RAMBANK("bank18")   /* TRIRAM (shared) */
	435	AM_RANGE(0x7000, 0x77ff) AM_RAM AM_SHARE("triram")
469	436	AM_RANGE(0x8000, 0x9fff) AM_RAM /* Sound RAM 3 */
470	437	AM_RANGE(0xc000, 0xc001) AM_WRITE(namcos1_sound_bankswitch_w) /* ROM bank selector */
471		AM_RANGE(0xd001, 0xd001) AM_WRITE(namcos1_watchdog_w)
	438	AM_RANGE(0xd001, 0xd001) AM_DEVWRITE("c117", namco_c117_device, sound_watchdog_w)
472	439	AM_RANGE(0xe000, 0xe000) AM_WRITE(irq_ack_w)
473	440	AM_RANGE(0xc000, 0xffff) AM_ROM
474	441	ADDRESS_MAP_END
r30936	r30937
480	447	AM_RANGE(0x1000, 0x1003) AM_READ(dsw_r)
481	448	AM_RANGE(0x1400, 0x1400) AM_READ_PORT("CONTROL0")
482	449	AM_RANGE(0x1401, 0x1401) AM_READ_PORT("CONTROL1")
483		AM_RANGE(0x4000, 0xbfff) AM_ROMBANK("bank20") /* banked ROM */
484		AM_RANGE(0xc000, 0xc000) AM_WRITE(namcos1_mcu_patch_w)  /* kludge! see notes */
485		AM_RANGE(0xc000, 0xc7ff) AM_RAMBANK("bank19")   /* TRIRAM (shared) */
	450	AM_RANGE(0x4000, 0xbfff) AM_ROMBANK("mcubank") /* banked ROM */
	451	AM_RANGE(0xc000, 0xc7ff) AM_RAM AM_SHARE("triram")
486	452	AM_RANGE(0xc800, 0xcfff) AM_RAM AM_SHARE("nvram") /* EEPROM */
487	453	AM_RANGE(0xd000, 0xd000) AM_WRITE(namcos1_dac0_w)
488	454	AM_RANGE(0xd400, 0xd400) AM_WRITE(namcos1_dac1_w)
r30936	r30937
1082	1048	MCFG_CPU_IO_MAP(mcu_port_map)
1083	1049	MCFG_CPU_VBLANK_INT_DRIVER("screen", namcos1_state,  irq0_line_assert)
1084	1050
	1051	MCFG_DEVICE_ADD("c117", NAMCO_C117, 0)
	1052	MCFG_DEVICE_PROGRAM_MAP(virtual_map)
	1053	MCFG_CUS117_CPUS("maincpu", "subcpu")
	1054	MCFG_CUS117_SUBRES_CB(WRITELINE(namcos1_state, subres_w))
	1055
1085	1056	// heavy sync required to prevent CPUs from fighting for video RAM access and going into deadlocks
1086	1057	MCFG_QUANTUM_TIME(attotime::from_hz(38400))
1087	1058

trunk/src/mame/machine/namcos1.c

r30936	r30937
1	1	#include "emu.h"
2		#include "sound/ym2151.h"
3	2	#include "includes/namcos1.h"
4	3
5	4
r30936	r30937
9	8	*                                                                              *
10	9	*******************************************************************************/
11	10
12		/* hardware elements of 1Mbytes physical memory space */
13
14		UINT8 namcos1_state::bank_r(address_space &space, offs_t offset, int bank)
15		{
16		return m_active_bank[bank].bank_handler_r(space, offset + m_active_bank[bank].bank_offset, 0xff);
17		}
18
19		READ8_MEMBER( namcos1_state::bank1_r )  { return bank_r(space, offset, 0); }
20		READ8_MEMBER( namcos1_state::bank2_r )  { return bank_r(space, offset, 1); }
21		READ8_MEMBER( namcos1_state::bank3_r )  { return bank_r(space, offset, 2); }
22		READ8_MEMBER( namcos1_state::bank4_r )  { return bank_r(space, offset, 3); }
23		READ8_MEMBER( namcos1_state::bank5_r )  { return bank_r(space, offset, 4); }
24		READ8_MEMBER( namcos1_state::bank6_r )  { return bank_r(space, offset, 5); }
25		READ8_MEMBER( namcos1_state::bank7_r )  { return bank_r(space, offset, 6); }
26		READ8_MEMBER( namcos1_state::bank8_r )  { return bank_r(space, offset, 7); }
27		READ8_MEMBER( namcos1_state::bank9_r )  { return bank_r(space, offset, 8); }
28		READ8_MEMBER( namcos1_state::bank10_r ) { return bank_r(space, offset, 9); }
29		READ8_MEMBER( namcos1_state::bank11_r ) { return bank_r(space, offset, 10); }
30		READ8_MEMBER( namcos1_state::bank12_r ) { return bank_r(space, offset, 11); }
31		READ8_MEMBER( namcos1_state::bank13_r ) { return bank_r(space, offset, 12); }
32		READ8_MEMBER( namcos1_state::bank14_r ) { return bank_r(space, offset, 13); }
33		READ8_MEMBER( namcos1_state::bank15_r ) { return bank_r(space, offset, 14); }
34		READ8_MEMBER( namcos1_state::bank16_r ) { return bank_r(space, offset, 15); }
35
36		void namcos1_state::bank_w(address_space &space, offs_t offset, UINT8 data, int bank)
37		{
38		m_active_bank[bank].bank_handler_w(space, offset + m_active_bank[bank].bank_offset, data, 0xff);
39		}
40
41		WRITE8_MEMBER( namcos1_state::bank1_w )  { bank_w(space, offset, data, 0); }
42		WRITE8_MEMBER( namcos1_state::bank2_w )  { bank_w(space, offset, data, 1); }
43		WRITE8_MEMBER( namcos1_state::bank3_w )  { bank_w(space, offset, data, 2); }
44		WRITE8_MEMBER( namcos1_state::bank4_w )  { bank_w(space, offset, data, 3); }
45		WRITE8_MEMBER( namcos1_state::bank5_w )  { bank_w(space, offset, data, 4); }
46		WRITE8_MEMBER( namcos1_state::bank6_w )  { bank_w(space, offset, data, 5); }
47		WRITE8_MEMBER( namcos1_state::bank7_w )  { bank_w(space, offset, data, 6); }
48		WRITE8_MEMBER( namcos1_state::bank8_w )  { bank_w(space, offset, data, 7); }
49		WRITE8_MEMBER( namcos1_state::bank9_w )  { bank_w(space, offset, data, 8); }
50		WRITE8_MEMBER( namcos1_state::bank10_w ) { bank_w(space, offset, data, 9); }
51		WRITE8_MEMBER( namcos1_state::bank11_w ) { bank_w(space, offset, data, 10); }
52		WRITE8_MEMBER( namcos1_state::bank12_w ) { bank_w(space, offset, data, 11); }
53		WRITE8_MEMBER( namcos1_state::bank13_w ) { bank_w(space, offset, data, 12); }
54		WRITE8_MEMBER( namcos1_state::bank14_w ) { bank_w(space, offset, data, 13); }
55		WRITE8_MEMBER( namcos1_state::bank15_w ) { bank_w(space, offset, data, 14); }
56		WRITE8_MEMBER( namcos1_state::bank16_w ) { bank_w(space, offset, data, 15); }
57
58	11	WRITE8_MEMBER( namcos1_state::namcos1_3dcs_w )
59	12	{
60	13	if (offset & 1) popmessage("LEFT");
r30936	r30937
484	437
485	438	READ8_MEMBER( namcos1_state::key_type3_r )
486	439	{
487		int op;
488
489	440	//  logerror("CPU %s PC %04x: keychip read %04x\n", space.device().tag(), space.device().safe_pc(), offset);
490	441
491	442	/* I need to handle blastoff's read from 0858. The game previously writes to 0858,
r30936	r30937
494	445	The schematics don't show A11 being used, so I go for this handling.
495	446	*/
496	447
497		op = (offset & 0x70) >> 4;
	448	int op = (offset & 0x70) >> 4;
498	449
499	450	if (op == m_key_reg)     return m_key_id;
500	451	if (op == m_key_rng)     return machine().rand();
r30936	r30937
527	478	UINT8 *rom = memregion("audiocpu")->base() + 0xc000;
528	479
529	480	int bank = (data & 0x70) >> 4;
530		membank("bank17")->set_base(rom + 0x4000 * bank);
	481	membank("soundbank")->set_base(rom + 0x4000 * bank);
531	482	}
532	483
533	484
r30936	r30937
538	489	*                                                                              *
539	490	*******************************************************************************/
540	491
	492	// These direct handlers are merely for speed - taking two trips
	493	// through the memory system for every opcode fetch is rather slow
541	494
542		WRITE8_MEMBER(namcos1_state::namcos1_cpu_control_w)
	495	DIRECT_UPDATE_MEMBER(namcos1_state::direct_handler_main)
543	496	{
544		//  logerror("reset control pc=%04x %02x\n",space.device().safe_pc(),data);
545		if ((data & 1) ^ m_reset)
546		{
547		m_mcu_patch_data = 0;
548		m_reset = data & 1;
549		}
550
551		m_subcpu->set_input_line(INPUT_LINE_RESET, (data & 1) ? CLEAR_LINE : ASSERT_LINE);
552		m_audiocpu->set_input_line(INPUT_LINE_RESET, (data & 1) ? CLEAR_LINE : ASSERT_LINE);
553		m_mcu->set_input_line(INPUT_LINE_RESET, (data & 1) ? CLEAR_LINE : ASSERT_LINE);
	497	return direct_handler(0, direct, address);
554	498	}
555	499
556
557
558		WRITE8_MEMBER(namcos1_state::namcos1_watchdog_w)
	500	DIRECT_UPDATE_MEMBER(namcos1_state::direct_handler_sub)
559	501	{
560		if (&space.device() == m_maincpu)
561		m_wdog |= 1;
562		else if (&space.device() == m_subcpu)
563		m_wdog |= 2;
564		else if (&space.device() == m_audiocpu)
565		m_wdog |= 4;
566
567		if (m_wdog == 7 || !m_reset)
568		{
569		m_wdog = 0;
570		watchdog_reset_w(space,0,0);
571		}
	502	return direct_handler(1, direct, address);
572	503	}
573	504
574
575
576		READ8_MEMBER( namcos1_state::soundram_r )
	505	inline offs_t namcos1_state::direct_handler(int whichcpu, direct_read_data &direct, offs_t address)
577	506	{
578		if (offset < 0x1000)
579		{
580		offset &= 0x3ff;
	507	offs_t remapped_address = m_c117->remap(whichcpu, address);
581	508
582		/* CUS 30 */
	509	// if not in ROM, return
	510	if (remapped_address < 0x400000) return address;
583	511
584		return machine().device<namco_cus30_device>("namco")->namcos1_cus30_r(space,offset);
585		}
586		else
587		{
588		offset &= 0x7ff;
	512	// calculate the base of the 8KB ROM page
	513	remapped_address &= 0x3fe000;
589	514
590		/* shared ram */
591		return m_triram[offset];
592		}
	515	direct.explicit_configure(address & 0xe000, address | 0x1fff, 0x1fff, &m_rom->base()[remapped_address]);
	516	return ~0;
593	517	}
594	518
595		WRITE8_MEMBER( namcos1_state::soundram_w )
596		{
597		if (offset < 0x1000)
598		{
599		offset &= 0x3ff;
600	519
601		/* CUS 30 */
602
603		machine().device<namco_cus30_device>("namco")->namcos1_cus30_w(space,offset,data);
604		}
605		else
606		{
607		offset &= 0x7ff;
608
609		/* shared ram */
610		m_triram[offset] = data;
611		return;
612		}
613		}
614
615		/* ROM handlers */
616
617		WRITE8_MEMBER( namcos1_state::rom_w )
	520	WRITE_LINE_MEMBER(namcos1_state::subres_w)
618	521	{
619		logerror("CPU %s PC %04x: warning - write %02x to rom address %04x\n", space.device().tag(), space.device().safe_pc(), data, offset);
620		}
621
622		/* error handlers */
623		READ8_MEMBER( namcos1_state::unknown_r )
624		{
625		logerror("CPU %s PC %04x: warning - read from unknown chip\n", space.device().tag(), space.device().safe_pc() );
626		//  popmessage("CPU %s PC %04x: read from unknown chip", space.device().tag(), space.device().safe_pc() );
627		return 0;
628		}
629
630		WRITE8_MEMBER( namcos1_state::unknown_w )
631		{
632		logerror("CPU %s PC %04x: warning - wrote to unknown chip\n", space.device().tag(), space.device().safe_pc() );
633		//  popmessage("CPU %s PC %04x: wrote to unknown chip", space.device().tag(), space.device().safe_pc() );
634		}
635
636		/* Main bankswitching routine */
637		void namcos1_state::set_bank(int banknum, const bankhandler *handler)
638		{
639		static const char *const banktags[] = {
640		"bank1", "bank2", "bank3", "bank4", "bank5", "bank6", "bank7", "bank8",
641		"bank9", "bank10", "bank11", "bank12", "bank13", "bank14", "bank15", "bank16"
642		};
643
644		static const struct { read8_delegate func; } io_bank_handler_r[16] =
	522	//  logerror("reset control pc=%04x %02x\n",space.device().safe_pc(),data);
	523	if (state != m_reset)
645	524	{
646		{ read8_delegate(FUNC(namcos1_state::bank1_r),this) }, { read8_delegate(FUNC(namcos1_state::bank2_r),this) }, { read8_delegate(FUNC(namcos1_state::bank3_r),this) }, { read8_delegate(FUNC(namcos1_state::bank4_r),this) },
647		{ read8_delegate(FUNC(namcos1_state::bank5_r),this) }, { read8_delegate(FUNC(namcos1_state::bank6_r),this) }, { read8_delegate(FUNC(namcos1_state::bank7_r),this) }, { read8_delegate(FUNC(namcos1_state::bank8_r),this) },
648		{ read8_delegate(FUNC(namcos1_state::bank9_r),this) }, { read8_delegate(FUNC(namcos1_state::bank10_r),this) }, { read8_delegate(FUNC(namcos1_state::bank11_r),this) }, { read8_delegate(FUNC(namcos1_state::bank12_r),this) },
649		{ read8_delegate(FUNC(namcos1_state::bank13_r),this) }, { read8_delegate(FUNC(namcos1_state::bank14_r),this) }, { read8_delegate(FUNC(namcos1_state::bank15_r),this) }, { read8_delegate(FUNC(namcos1_state::bank16_r),this) }
650		};
651
652		static const struct { write8_delegate func; } io_bank_handler_w[16] =
653		{
654		{ write8_delegate(FUNC(namcos1_state::bank1_w),this) }, { write8_delegate(FUNC(namcos1_state::bank2_w),this) }, { write8_delegate(FUNC(namcos1_state::bank3_w),this) }, { write8_delegate(FUNC(namcos1_state::bank4_w),this) },
655		{ write8_delegate(FUNC(namcos1_state::bank5_w),this) }, { write8_delegate(FUNC(namcos1_state::bank6_w),this) }, { write8_delegate(FUNC(namcos1_state::bank7_w),this) }, { write8_delegate(FUNC(namcos1_state::bank8_w),this) },
656		{ write8_delegate(FUNC(namcos1_state::bank9_w),this) }, { write8_delegate(FUNC(namcos1_state::bank10_w),this) }, { write8_delegate(FUNC(namcos1_state::bank11_w),this) }, { write8_delegate(FUNC(namcos1_state::bank12_w),this) },
657		{ write8_delegate(FUNC(namcos1_state::bank13_w),this) }, { write8_delegate(FUNC(namcos1_state::bank14_w),this) }, { write8_delegate(FUNC(namcos1_state::bank15_w),this) }, { write8_delegate(FUNC(namcos1_state::bank16_w),this) }
658		};
659
660		address_space &space = (((banknum & 8) == 0) ? m_maincpu : m_subcpu)->space(AS_PROGRAM);
661		int bankstart = (banknum & 7) * 0x2000;
662
663		/* for BANK handlers , memory direct and OP-code base */
664		if (handler->bank_pointer)
665		membank(banktags[banknum])->set_base(handler->bank_pointer);
666
667		/* read handlers */
668		if (handler->bank_handler_r.isnull())
669		{
670		if (!m_active_bank[banknum].bank_handler_r.isnull())
671		space.install_read_bank(bankstart, bankstart + 0x1fff, banktags[banknum]);
	525	m_mcu_patch_data = 0;
	526	m_reset = state;
672	527	}
673		else
674		{
675		if (m_active_bank[banknum].bank_handler_r.isnull())
676		space.install_read_handler(bankstart, bankstart + 0x1fff, io_bank_handler_r[banknum].func);
677		}
678	528
679		/* write handlers (except for the 0xe000-0xffff range) */
680		if (bankstart != 0xe000)
681		{
682		if (handler->bank_handler_w.isnull())
683		{
684		if (!m_active_bank[banknum].bank_handler_w.isnull())
685		space.install_write_bank(bankstart, bankstart + 0x1fff, banktags[banknum]);
686		}
687		else
688		{
689		if (m_active_bank[banknum].bank_handler_r.isnull())
690		space.install_write_handler(bankstart, bankstart + 0x1fff, io_bank_handler_w[banknum].func);
691		}
692		}
693
694		/* Remember this bank handler */
695		m_active_bank[banknum] = *handler;
	529	m_subcpu->set_input_line(INPUT_LINE_RESET, state);
	530	m_audiocpu->set_input_line(INPUT_LINE_RESET, state);
	531	m_mcu->set_input_line(INPUT_LINE_RESET, state);
696	532	}
697	533
698		void namcos1_state::namcos1_bankswitch(int cpu, offs_t offset, UINT8 data)
699		{
700		int bank = (cpu*8) + (( offset >> 9) & 0x07);
701		int old = m_chip[bank];
702
703		if (offset & 1)
704		{
705		m_chip[bank] &= 0x0300;
706		m_chip[bank] |= (data & 0xff);
707		}
708		else
709		{
710		m_chip[bank] &= 0x00ff;
711		m_chip[bank] |= (data & 0x03) << 8;
712		}
713
714		/* set_bank is slow, so only call it if uninitialized(unmapped) or changed */
715		if (m_active_bank[bank].bank_handler_r == read8_delegate(FUNC(namcos1_state::unknown_r),this) || m_chip[bank] != old)
716		set_bank(bank, &m_bank_element[m_chip[bank]]);
717
718		/* unmapped bank warning */
719		if( m_active_bank[bank].bank_handler_r == read8_delegate(FUNC(namcos1_state::unknown_r),this))
720		{
721		logerror("%s:warning unknown chip selected bank %x=$%04x\n", machine().describe_context(), bank , m_chip[bank] );
722		//      if (m_chip) popmessage("%s:unknown chip selected bank %x=$%04x", cpu , machine.describe_context(), bank , m_chip[bank] );
723		}
724		}
725
726		WRITE8_MEMBER(namcos1_state::namcos1_bankswitch_w)
727		{
728		//  logerror("cpu %s: namcos1_bankswitch_w offset %04x data %02x\n", device().tag(), offset, data);
729
730		namcos1_bankswitch((&space.device() == m_maincpu) ? 0 : 1, offset, data);
731		}
732
733		/* Sub cpu set start bank port */
734		WRITE8_MEMBER(namcos1_state::namcos1_subcpu_bank_w)
735		{
736		//  logerror("namcos1_subcpu_bank_w offset %04x data %02x\n",offset,data);
737
738		/* Prepare code for CPU 1 */
739		namcos1_bankswitch( 1, 0x0e00, 0x03 );
740		namcos1_bankswitch( 1, 0x0e01, data );
741		}
742
743	534	/*******************************************************************************
744	535	*                                                                              *
745	536	*   Initialization                                                             *
746	537	*                                                                              *
747	538	*******************************************************************************/
748	539
749		void namcos1_state::namcos1_install_bank(int start, int end,read8_delegate hr, write8_delegate hw, int offset, UINT8 *pointer)
750		{
751		for (int i = start; i <= end; i++)
752		{
753		m_bank_element[i].bank_handler_r = hr;
754		m_bank_element[i].bank_handler_w = hw;
755		m_bank_element[i].bank_offset    = offset;
756		m_bank_element[i].bank_pointer   = pointer;
757
758		offset += 0x2000;
759
760		if (pointer)
761		pointer += 0x2000;
762		}
763		}
764
765
766
767		void namcos1_state::namcos1_build_banks(read8_delegate key_r, write8_delegate key_w)
768		{
769		int i;
770
771		/**** kludge alert ****/
772		m_dummyrom = auto_alloc_array(machine(), UINT8, 0x2000);
773
774		/* when the games want to reset because the test switch has been flipped (or
775		because the protection checks failed!) they just set the top bits of bank #7
776		to 0, effectively crashing and waiting for the watchdog to kick in.
777		To avoid crashes in MAME, I prepare a dummy ROM containing just BRA -2 so
778		the program doesn't start executing code in unmapped areas.
779		Conveniently, the opcode for BRA -2 is 20 FE, and FE 20 FE is LDU $20FE,
780		so misaligned entry points get immediatly corrected. */
781		for (i = 0;i < 0x2000;i+=2)
782		{
783		m_dummyrom[i]   = 0x20;
784		m_dummyrom[i+1] = 0xfe;
785		}
786		/* also provide a valid IRQ vector */
787		m_dummyrom[0x1ff8] = 0xff;
788		m_dummyrom[0x1ff9] = 0x00;
789
790		/* clear all banks to unknown area */
791		for(i = 0;i < NAMCOS1_MAX_BANK;i++)
792		namcos1_install_bank(i,i,read8_delegate(),write8_delegate(FUNC(namcos1_state::unknown_w),this),0,m_dummyrom);
793		/**** end of kludge alert ****/
794
795
796		/* 3D glasses */
797		namcos1_install_bank(0x160,0x160,read8_delegate(),write8_delegate(FUNC(namcos1_state::namcos1_3dcs_w),this),0,0);
798		/* RAM 6 banks - palette */
799		namcos1_install_bank(0x170,0x173,read8_delegate(),write8_delegate(FUNC(namcos1_state::namcos1_paletteram_w),this),0,m_paletteram);
800		/* RAM 5 banks - videoram */
801		namcos1_install_bank(0x178,0x17b,read8_delegate(FUNC(namcos1_state::namcos1_videoram_r),this),write8_delegate(FUNC(namcos1_state::namcos1_videoram_w),this),0,0);
802		/* key chip bank */
803		namcos1_install_bank(0x17c,0x17c,key_r,key_w,0,0);
804		/* RAM 7 banks - display control, playfields, sprites */
805		namcos1_install_bank(0x17e,0x17e,read8_delegate(FUNC(namcos1_state::namcos1_spriteram_r),this),write8_delegate(FUNC(namcos1_state::namcos1_spriteram_w),this),0,0);
806		/* RAM 1 shared ram, PSG device */
807		namcos1_install_bank(0x17f,0x17f,read8_delegate(FUNC(namcos1_state::soundram_r),this),write8_delegate(FUNC(namcos1_state::soundram_w),this),0,0);
808		/* RAM 3 banks */
809		namcos1_install_bank(0x180,0x183,read8_delegate(),write8_delegate(),0,m_s1ram);
810
811		/* PRG0-PRG7 */
812		UINT8 *rom = machine().root_device().memregion("user1")->base();
813
814		namcos1_install_bank(0x200,0x3ff,read8_delegate(),write8_delegate(FUNC(namcos1_state::rom_w),this),0,rom);
815
816		/* bit 16 of the address is inverted for PRG7 (and bits 17,18 just not connected) */
817		for (i = 0x380000;i < 0x400000;i++)
818		{
819		if ((i & 0x010000) == 0)
820		{
821		UINT8 t = rom[i];
822		rom[i] = rom[i + 0x010000];
823		rom[i + 0x010000] = t;
824		}
825		}
826		}
827
828	540	void namcos1_state::machine_reset()
829	541	{
830		memset(m_chip, 0, sizeof(m_chip));
831
832		/* Point all of our bankhandlers to the error handlers */
833		static const bankhandler unknown_handler = { read8_delegate(FUNC(namcos1_state::unknown_r),this), write8_delegate(FUNC(namcos1_state::unknown_w),this), 0, NULL };
834
835		for (int bank = 0; bank < 2*8 ; bank++)
836		set_bank(bank, &unknown_handler);
837
838		/* Default MMU setup for Cpu 0 */
839		namcos1_bankswitch(0, 0x0000, 0x01 ); /* bank0 = 0x180(RAM) - evidence: wldcourt */
840		namcos1_bankswitch(0, 0x0001, 0x80 );
841		namcos1_bankswitch(0, 0x0200, 0x01 ); /* bank1 = 0x180(RAM) - evidence: berabohm */
842		namcos1_bankswitch(0, 0x0201, 0x80 );
843
844		namcos1_bankswitch(0, 0x0e00, 0x03 ); /* bank7 = 0x3ff(PRG7) */
845		namcos1_bankswitch(0, 0x0e01, 0xff );
846
847		/* Default MMU setup for Cpu 1 */
848		namcos1_bankswitch(1, 0x0000, 0x01 ); /* bank0 = 0x180(RAM) - evidence: wldcourt */
849		namcos1_bankswitch(1, 0x0001, 0x80 );
850
851		namcos1_bankswitch(1, 0x0e00, 0x03); /* bank7 = 0x3ff(PRG7) */
852		namcos1_bankswitch(1, 0x0e01, 0xff);
853
854		/* reset Cpu 0 and stop all other CPUs */
855		m_maincpu->reset();
856		m_subcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
857		m_audiocpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
858		m_mcu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
859
860	542	/* mcu patch data clear */
861	543	m_mcu_patch_data = 0;
862		m_reset = 0;
863	544
864	545	namcos1_init_DACs();
865	546	memset(m_key, 0, sizeof(m_key));
866	547	m_key_quotient = 0;
867	548	m_key_reminder = 0;
868	549	m_key_numerator_high_word = 0;
869		m_wdog = 0;
870	550	}
871	551
872	552
r30936	r30937
903	583	/* bit 0-1 : address line A15-A16 */
904	584	addr += (data & 3) * 0x8000;
905	585
906		membank("bank20")->set_base(memregion("mcu")->base() + addr);
	586	membank("mcubank")->set_base(memregion("mcu")->base() + addr);
907	587	}
908	588
909	589
r30936	r30937
935	615	*   driver specific initialize routine                                         *
936	616	*                                                                              *
937	617	*******************************************************************************/
938		void namcos1_state::namcos1_driver_init(const struct namcos1_specific *specific )
	618	void namcos1_state::namcos1_driver_init()
939	619	{
940		static const struct namcos1_specific no_key =
	620	UINT8 *rom = m_rom->base();
	621
	622	// bit 16 of the address is inverted for PRG7 (and bits 17,18 just not connected)
	623	for (int i = 0x380000;i < 0x400000;i++)
941	624	{
942		read8_delegate(FUNC(namcos1_state::no_key_r),this), write8_delegate(FUNC(namcos1_state::no_key_w),this)
943		};
	625	if ((i & 0x010000) == 0)
	626	{
	627	UINT8 t = rom[i];
	628	rom[i] = rom[i + 0x010000];
	629	rom[i + 0x010000] = t;
	630	}
	631	}
944	632
945		if (!specific) specific = &no_key;
	633	m_maincpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(namcos1_state::direct_handler_main), this));
	634	m_subcpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(namcos1_state::direct_handler_sub), this));
946	635
947		/* keychip id */
948		m_key_id        = specific->key_id;
949		/* for key type 3 */
950		m_key_reg       = specific->key_reg1;
951		m_key_rng       = specific->key_reg2;
952		m_key_swap4_arg = specific->key_reg3;
953		m_key_swap4     = specific->key_reg4;
954		m_key_bottom4   = specific->key_reg5;
955		m_key_top4      = specific->key_reg6;
	636	// kludge! see notes
	637	m_mcu->space(AS_PROGRAM).install_write_handler(0xc000, 0xc000, write8_delegate(FUNC(namcos1_state::namcos1_mcu_patch_w), this));
956	638
957		/* S1 RAM pointer set */
958		m_s1ram = auto_alloc_array_clear(machine(), UINT8, 0x8000);
959		m_triram = auto_alloc_array_clear(machine(), UINT8, 0x800);
960		m_paletteram = auto_alloc_array_clear(machine(), UINT8, 0x8000);
961
962		/* Register volatile user memory for save state */
963		save_pointer(NAME(m_s1ram), 0x8000);
964		save_pointer(NAME(m_triram), 0x800);
965		save_pointer(NAME(m_paletteram), 0x8000);
966
967		/* Point mcu & sound shared RAM to destination */
968		membank("bank18")->set_base(m_triram);
969		membank("bank19")->set_base(m_triram);
970
971		/* build bank elements */
972		namcos1_build_banks(specific->key_r,specific->key_w);
973		memset(m_active_bank, 0, sizeof(m_active_bank));
	639	// these are overridden as needed in the specific DRIVER_INIT_MEMBERs
	640	m_key_id        = 0;
	641	m_key_reg       = 0;
	642	m_key_rng       = 0;
	643	m_key_swap4_arg = 0;
	644	m_key_swap4     = 0;
	645	m_key_bottom4   = 0;
	646	m_key_top4      = 0;
974	647	}
975	648
976	649
r30936	r30937
979	652	*******************************************************************************/
980	653	DRIVER_INIT_MEMBER(namcos1_state,shadowld)
981	654	{
982		namcos1_driver_init(NULL);
	655	namcos1_driver_init();
983	656	}
984	657
985	658	/*******************************************************************************
r30936	r30937
987	660	*******************************************************************************/
988	661	DRIVER_INIT_MEMBER(namcos1_state,dspirit)
989	662	{
990		static const struct namcos1_specific dspirit_specific=
991		{
992		read8_delegate(FUNC(namcos1_state::key_type1_r),this), write8_delegate(FUNC(namcos1_state::key_type1_w),this), 0x36
993		};
994		namcos1_driver_init(&dspirit_specific);
	663	namcos1_driver_init();
	664	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	665	read8_delegate(FUNC(namcos1_state::key_type1_r),this),
	666	write8_delegate(FUNC(namcos1_state::key_type1_w),this));
	667	m_key_id = 0x36;
995	668	}
996	669
997	670	/*******************************************************************************
r30936	r30937
999	672	*******************************************************************************/
1000	673	DRIVER_INIT_MEMBER(namcos1_state,wldcourt)
1001	674	{
1002		static const struct namcos1_specific worldcourt_specific=
1003		{
1004		read8_delegate(FUNC(namcos1_state::key_type1_r),this), write8_delegate(FUNC(namcos1_state::key_type1_w),this), 0x35
1005		};
1006		namcos1_driver_init(&worldcourt_specific);
	675	namcos1_driver_init();
	676	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	677	read8_delegate(FUNC(namcos1_state::key_type1_r),this),
	678	write8_delegate(FUNC(namcos1_state::key_type1_w),this));
	679	m_key_id = 0x35;
1007	680	}
1008	681
1009	682	/*******************************************************************************
r30936	r30937
1011	684	*******************************************************************************/
1012	685	DRIVER_INIT_MEMBER(namcos1_state,blazer)
1013	686	{
1014		static const struct namcos1_specific blazer_specific=
1015		{
1016		read8_delegate(FUNC(namcos1_state::key_type1_r),this), write8_delegate(FUNC(namcos1_state::key_type1_w),this), 0x13
1017		};
1018		namcos1_driver_init(&blazer_specific);
	687	namcos1_driver_init();
	688	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	689	read8_delegate(FUNC(namcos1_state::key_type1_r),this),
	690	write8_delegate(FUNC(namcos1_state::key_type1_w),this));
	691	m_key_id = 0x13;
1019	692	}
1020	693
1021	694	/*******************************************************************************
r30936	r30937
1023	696	*******************************************************************************/
1024	697	DRIVER_INIT_MEMBER(namcos1_state,puzlclub)
1025	698	{
1026		static const struct namcos1_specific puzlclub_specific=
1027		{
1028		read8_delegate(FUNC(namcos1_state::key_type1_r),this), write8_delegate(FUNC(namcos1_state::key_type1_w),this), 0x35
1029		};
1030		namcos1_driver_init(&puzlclub_specific);
	699	namcos1_driver_init();
	700	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	701	read8_delegate(FUNC(namcos1_state::key_type1_r),this),
	702	write8_delegate(FUNC(namcos1_state::key_type1_w),this));
	703	m_key_id = 0x35;
1031	704	}
1032	705
1033	706	/*******************************************************************************
r30936	r30937
1035	708	*******************************************************************************/
1036	709	DRIVER_INIT_MEMBER(namcos1_state,pacmania)
1037	710	{
1038		static const struct namcos1_specific pacmania_specific=
1039		{
1040		read8_delegate(FUNC(namcos1_state::key_type2_r),this), write8_delegate(FUNC(namcos1_state::key_type2_w),this), 0x12
1041		};
1042		namcos1_driver_init(&pacmania_specific);
	711	namcos1_driver_init();
	712	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	713	read8_delegate(FUNC(namcos1_state::key_type2_r),this),
	714	write8_delegate(FUNC(namcos1_state::key_type2_w),this));
	715	m_key_id = 0x12;
1043	716	}
1044	717
1045	718	/*******************************************************************************
r30936	r30937
1047	720	*******************************************************************************/
1048	721	DRIVER_INIT_MEMBER(namcos1_state,alice)
1049	722	{
1050		static const struct namcos1_specific alice_specific=
1051		{
1052		read8_delegate(FUNC(namcos1_state::key_type2_r),this), write8_delegate(FUNC(namcos1_state::key_type2_w),this), 0x25
1053		};
1054		namcos1_driver_init(&alice_specific);
	723	namcos1_driver_init();
	724	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	725	read8_delegate(FUNC(namcos1_state::key_type2_r),this),
	726	write8_delegate(FUNC(namcos1_state::key_type2_w),this));
	727	m_key_id = 0x25;
1055	728	}
1056	729
1057	730	/*******************************************************************************
r30936	r30937
1059	732	*******************************************************************************/
1060	733	DRIVER_INIT_MEMBER(namcos1_state,galaga88)
1061	734	{
1062		static const struct namcos1_specific galaga88_specific=
1063		{
1064		read8_delegate(FUNC(namcos1_state::key_type2_r),this), write8_delegate(FUNC(namcos1_state::key_type2_w),this), 0x31
1065		};
1066		namcos1_driver_init(&galaga88_specific);
	735	namcos1_driver_init();
	736	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	737	read8_delegate(FUNC(namcos1_state::key_type2_r),this),
	738	write8_delegate(FUNC(namcos1_state::key_type2_w),this));
	739	m_key_id = 0x31;
1067	740	}
1068	741
1069	742	/*******************************************************************************
r30936	r30937
1071	744	*******************************************************************************/
1072	745	DRIVER_INIT_MEMBER(namcos1_state,ws)
1073	746	{
1074		static const struct namcos1_specific ws_specific=
1075		{
1076		read8_delegate(FUNC(namcos1_state::key_type2_r),this), write8_delegate(FUNC(namcos1_state::key_type2_w),this), 0x07
1077		};
1078		namcos1_driver_init(&ws_specific);
	747	namcos1_driver_init();
	748	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	749	read8_delegate(FUNC(namcos1_state::key_type2_r),this),
	750	write8_delegate(FUNC(namcos1_state::key_type2_w),this));
	751	m_key_id = 0x07;
1079	752	}
1080	753
1081	754	/*******************************************************************************
r30936	r30937
1083	756	*******************************************************************************/
1084	757	DRIVER_INIT_MEMBER(namcos1_state,bakutotu)
1085	758	{
1086		static const struct namcos1_specific bakutotu_specific=
1087		{
1088		read8_delegate(FUNC(namcos1_state::key_type2_r),this), write8_delegate(FUNC(namcos1_state::key_type2_w),this), 0x22
1089		};
1090		namcos1_driver_init(&bakutotu_specific);
1091
1092		#if 0
1093		// resolves CPU deadlocks caused by sloppy coding(see driver\namcos1.c)
1094		{
1095		static const UINT8 target[8] = {0x34,0x37,0x35,0x37,0x96,0x00,0x2e,0xed};
1096		UINT8 *rombase, *srcptr, *endptr, *scanptr;
1097
1098		rombase = memregion("user1")->base();
1099		srcptr = rombase + 0x1e000;
1100		endptr = srcptr + 0xa000;
1101
1102		while ( (scanptr = memchr(srcptr, 0x34, endptr-srcptr)) )
1103		{
1104		if (!memcmp(scanptr, target, 8))
1105		{
1106		scanptr[7] = 0xfc;
1107		srcptr = scanptr + 8;
1108
1109		logerror ("faulty loop patched at %06x\n", scanptr-rombase+7);
1110		}
1111		else
1112		srcptr = scanptr + 1;
1113		}
1114		}
1115		#endif
	759	namcos1_driver_init();
	760	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	761	read8_delegate(FUNC(namcos1_state::key_type2_r),this),
	762	write8_delegate(FUNC(namcos1_state::key_type2_w),this));
	763	m_key_id = 0x22;
1116	764	}
1117	765
1118	766	/*******************************************************************************
r30936	r30937
1120	768	*******************************************************************************/
1121	769	DRIVER_INIT_MEMBER(namcos1_state,splatter)
1122	770	{
1123		static const struct namcos1_specific splatter_specific=
1124		{
1125		read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 181, 3, 4,-1,-1,-1,-1
1126		};
1127
1128		namcos1_driver_init(&splatter_specific);
	771	namcos1_driver_init();
	772	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	773	read8_delegate(FUNC(namcos1_state::key_type3_r),this),
	774	write8_delegate(FUNC(namcos1_state::key_type3_w),this));
	775	m_key_id        = 181;
	776	m_key_reg       = 3;
	777	m_key_rng       = 4;
	778	m_key_swap4_arg = -1;
	779	m_key_swap4     = -1;
	780	m_key_bottom4   = -1;
	781	m_key_top4      = -1;
1129	782	}
1130	783
1131	784	/*******************************************************************************
r30936	r30937
1133	786	*******************************************************************************/
1134	787	DRIVER_INIT_MEMBER(namcos1_state,rompers)
1135	788	{
1136		static const struct namcos1_specific rompers_specific=
1137		{
1138		read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 182, 7,-1,-1,-1,-1,-1
1139		};
1140		namcos1_driver_init(&rompers_specific);
	789	namcos1_driver_init();
	790	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	791	read8_delegate(FUNC(namcos1_state::key_type3_r),this),
	792	write8_delegate(FUNC(namcos1_state::key_type3_w),this));
	793	m_key_id        = 182;
	794	m_key_reg       = 7;
	795	m_key_rng       = -1;
	796	m_key_swap4_arg = -1;
	797	m_key_swap4     = -1;
	798	m_key_bottom4   = -1;
	799	m_key_top4      = -1;
1141	800	}
1142	801
1143	802	/*******************************************************************************
r30936	r30937
1145	804	*******************************************************************************/
1146	805	DRIVER_INIT_MEMBER(namcos1_state,blastoff)
1147	806	{
1148		static const struct namcos1_specific blastoff_specific=
1149		{
1150		read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 183, 0, 7, 3, 5,-1,-1
1151		};
1152		namcos1_driver_init(&blastoff_specific);
	807	namcos1_driver_init();
	808	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	809	read8_delegate(FUNC(namcos1_state::key_type3_r),this),
	810	write8_delegate(FUNC(namcos1_state::key_type3_w),this));
	811	m_key_id        = 183;
	812	m_key_reg       = 0;
	813	m_key_rng       = 7;
	814	m_key_swap4_arg = 3;
	815	m_key_swap4     = 5;
	816	m_key_bottom4   = -1;
	817	m_key_top4      = -1;
1153	818	}
1154	819
1155	820	/*******************************************************************************
r30936	r30937
1157	822	*******************************************************************************/
1158	823	DRIVER_INIT_MEMBER(namcos1_state,ws89)
1159	824	{
1160		static const struct namcos1_specific ws89_specific=
1161		{
1162		read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 184, 2,-1,-1,-1,-1,-1
1163		};
1164		namcos1_driver_init(&ws89_specific);
	825	namcos1_driver_init();
	826	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	827	read8_delegate(FUNC(namcos1_state::key_type3_r),this),
	828	write8_delegate(FUNC(namcos1_state::key_type3_w),this));
	829	m_key_id        = 184;
	830	m_key_reg       = 2;
	831	m_key_rng       = -1;
	832	m_key_swap4_arg = -1;
	833	m_key_swap4     = -1;
	834	m_key_bottom4   = -1;
	835	m_key_top4      = -1;
1165	836	}
1166	837
1167	838	/*******************************************************************************
r30936	r30937
1169	840	*******************************************************************************/
1170	841	DRIVER_INIT_MEMBER(namcos1_state,tankfrce)
1171	842	{
1172		static const struct namcos1_specific tankfrce_specific=
1173		{
1174		read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 185, 5,-1, 1,-1, 2,-1
1175		};
1176		namcos1_driver_init(&tankfrce_specific);
	843	namcos1_driver_init();
	844	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	845	read8_delegate(FUNC(namcos1_state::key_type3_r),this),
	846	write8_delegate(FUNC(namcos1_state::key_type3_w),this));
	847	m_key_id        = 185;
	848	m_key_reg       = 5;
	849	m_key_rng       = -1;
	850	m_key_swap4_arg = 1;
	851	m_key_swap4     = -1;
	852	m_key_bottom4   = 2;
	853	m_key_top4      = -1;
1177	854	}
1178	855
1179
1180
1181	856	DRIVER_INIT_MEMBER(namcos1_state,tankfrc4)
1182	857	{
	858	DRIVER_INIT_CALL(tankfrce);
	859
1183	860	m_input_count = 0;
1184	861	m_strobe_count = 0;
1185	862	m_stored_input[0] = 0;
1186	863	m_stored_input[1] = 0;
1187	864
1188		static const struct namcos1_specific tankfrce_specific=
1189		{
1190		read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 185, 5,-1, 1,-1, 2,-1
1191		};
1192		namcos1_driver_init(&tankfrce_specific);
1193
1194	865	m_mcu->space(AS_PROGRAM).install_read_handler(0x1400, 0x1401, read8_delegate(FUNC(namcos1_state::faceoff_inputs_r), this));
1195	866	}
1196	867
r30936	r30937
1199	870	*******************************************************************************/
1200	871	DRIVER_INIT_MEMBER(namcos1_state,dangseed)
1201	872	{
1202		static const struct namcos1_specific dangseed_specific=
1203		{
1204		read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 308, 6,-1, 5,-1, 0, 4
1205		};
1206		namcos1_driver_init(&dangseed_specific);
	873	namcos1_driver_init();
	874	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	875	read8_delegate(FUNC(namcos1_state::key_type3_r),this),
	876	write8_delegate(FUNC(namcos1_state::key_type3_w),this));
	877	m_key_id        = 308;
	878	m_key_reg       = 6;
	879	m_key_rng       = -1;
	880	m_key_swap4_arg = 5;
	881	m_key_swap4     = -1;
	882	m_key_bottom4   = 0;
	883	m_key_top4      = 4;
1207	884	}
1208	885
1209	886	/*******************************************************************************
r30936	r30937
1211	888	*******************************************************************************/
1212	889	DRIVER_INIT_MEMBER(namcos1_state,pistoldm)
1213	890	{
1214		static const struct namcos1_specific pistoldm_specific=
1215		{
1216		read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 309, 1, 2, 0,-1, 4,-1
1217		};
1218		namcos1_driver_init(&pistoldm_specific);
	891	namcos1_driver_init();
	892	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	893	read8_delegate(FUNC(namcos1_state::key_type3_r),this),
	894	write8_delegate(FUNC(namcos1_state::key_type3_w),this));
	895	m_key_id        = 309;
	896	m_key_reg       = 1;
	897	m_key_rng       = 2;
	898	m_key_swap4_arg = 0;
	899	m_key_swap4     = -1;
	900	m_key_bottom4   = 4;
	901	m_key_top4      = -1;
1219	902	}
1220	903
1221	904	/*******************************************************************************
r30936	r30937
1223	906	*******************************************************************************/
1224	907	DRIVER_INIT_MEMBER(namcos1_state,ws90)
1225	908	{
1226		static const struct namcos1_specific ws90_specific=
1227		{
1228		read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 310, 4,-1, 7,-1, 3,-1
1229		};
1230		namcos1_driver_init(&ws90_specific);
	909	namcos1_driver_init();
	910	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	911	read8_delegate(FUNC(namcos1_state::key_type3_r),this),
	912	write8_delegate(FUNC(namcos1_state::key_type3_w),this));
	913	m_key_id        = 310;
	914	m_key_reg       = 4;
	915	m_key_rng       = -1;
	916	m_key_swap4_arg = 7;
	917	m_key_swap4     = -1;
	918	m_key_bottom4   = 3;
	919	m_key_top4      = -1;
1231	920	}
1232	921
1233	922	/*******************************************************************************
r30936	r30937
1235	924	*******************************************************************************/
1236	925	DRIVER_INIT_MEMBER(namcos1_state,soukobdx)
1237	926	{
1238		static const struct namcos1_specific soukobdx_specific=
1239		{
1240		read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 311, 2, 3/*?*/, 0,-1, 4,-1
1241		};
1242		namcos1_driver_init(&soukobdx_specific);
	927	namcos1_driver_init();
	928	m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff,
	929	read8_delegate(FUNC(namcos1_state::key_type3_r),this),
	930	write8_delegate(FUNC(namcos1_state::key_type3_w),this));
	931	m_key_id        = 311;
	932	m_key_reg       = 2;
	933	m_key_rng       = 3; /*?*/
	934	m_key_swap4_arg = 0;
	935	m_key_swap4     = -1;
	936	m_key_bottom4   = 4;
	937	m_key_top4      = -1;
1243	938	}
1244	939
1245	940
r30936	r30937
1280	975	DRIVER_INIT_MEMBER(namcos1_state,quester)
1281	976	{
1282	977	m_strobe = 0;
1283		namcos1_driver_init(NULL);
	978	namcos1_driver_init();
1284	979	m_mcu->space(AS_PROGRAM).install_read_handler(0x1400, 0x1401, read8_delegate(FUNC(namcos1_state::quester_paddle_r), this));
1285	980	}
1286	981
r30936	r30937
1370	1065	m_input_count = 0;
1371	1066	m_strobe = 0;
1372	1067	m_strobe_count = 0;
1373		namcos1_driver_init(NULL);
	1068	namcos1_driver_init();
1374	1069	m_mcu->space(AS_PROGRAM).install_read_handler(0x1400, 0x1401, read8_delegate(FUNC(namcos1_state::berabohm_buttons_r), this));
1375	1070	}
1376	1071
r30936	r30937
1446	1141	m_stored_input[0] = 0;
1447	1142	m_stored_input[1] = 0;
1448	1143
1449		namcos1_driver_init(NULL);
	1144	namcos1_driver_init();
1450	1145	m_mcu->space(AS_PROGRAM).install_read_handler(0x1400, 0x1401, read8_delegate(FUNC(namcos1_state::faceoff_inputs_r), this));
1451	1146	}

trunk/src/mame/machine/c117.c

r0	r30937
	1	// license:BSD-3-Clause
	2	// copyright-holders:Alex W. Jackson
	3	/*
	4	Namco Custom 117, used in System 1
	5
	6	CUS117 is a simple MMU that provides a 23 bit virtual address space for a pair
	7	of M6809 CPUs. The chip outputs the various enable lines for RAM, ROM, video
	8	customs, etc., and bits 12-21 of the virtual address (bit 22 of the virtual
	9	address is handled internally: it selects between ROM and everything else)
	10
	11	Each CPU's address space is evenly divided into eight 8KB banks, and each of
	12	these banks can be directed to any portion of the virtual address space
	13	(however, the last bank for each CPU is effectively read only, since writes to
	14	E000-FFFF control CUS117 itself)
	15
	16	The main and sub CPUs share the same address and data bus, but each CPU can
	17	set up its own banks independently. The main CPU can also set the sub CPU's
	18	last bank (E000-FFFF, where the 6809 reset and interrupt vectors reside)
	19
	20	As well as being an MMU, CUS117 serves as the interrupt controller for the
	21	two 6809s and as the reset generator for the entire system.
	22	*/
	23
	24	#include "emu.h"
	25	#include "cpu/m6809/m6809.h"
	26	#include "machine/c117.h"
	27
	28
	29	const device_type NAMCO_C117 = &device_creator<namco_c117_device>;
	30
	31
	32	//-------------------------------------------------
	33	//  namco_c117_device - constructor
	34	//-------------------------------------------------
	35
	36	namco_c117_device::namco_c117_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	37	: device_t(mconfig, NAMCO_C117, "Namco CUS117", tag, owner, clock, "namco_c117", __FILE__),
	38	device_memory_interface(mconfig, *this),
	39	m_subres_cb(*this),
	40	m_program_config("program", ENDIANNESS_BIG, 8, 23),
	41	m_maincpu_tag(NULL),
	42	m_subcpu_tag(NULL)
	43	{
	44	}
	45
	46	//-------------------------------------------------
	47	//  set_cpu_tags - set the tags of the two CPUs
	48	//  connected to the device
	49	//-------------------------------------------------
	50
	51	void namco_c117_device::set_cpu_tags(device_t &device, const char *maintag, const char *subtag)
	52	{
	53	namco_c117_device &c117 = downcast<namco_c117_device &>(device);
	54	c117.m_maincpu_tag = maintag;
	55	c117.m_subcpu_tag = subtag;
	56	}
	57
	58
	59	//-------------------------------------------------
	60	//  device_start - device-specific startup
	61	//-------------------------------------------------
	62
	63	void namco_c117_device::device_start()
	64	{
	65	m_subres_cb.resolve_safe();
	66
	67	m_program = &space(AS_PROGRAM);
	68
	69	cpu_device *maincpu = siblingdevice<cpu_device>(m_maincpu_tag);
	70	cpu_device *subcpu = siblingdevice<cpu_device>(m_subcpu_tag);
	71
	72	m_cpuexec[0] = maincpu;
	73	m_cpuexec[1] = subcpu;
	74	m_cpudirect[0] = &maincpu->space(AS_PROGRAM).direct();
	75	m_cpudirect[1] = &subcpu->space(AS_PROGRAM).direct();
	76
	77	memset(&m_offsets, 0, sizeof(m_offsets));
	78	m_subres = m_wdog = 0;
	79	save_item(NAME(m_offsets));
	80	save_item(NAME(m_subres));
	81	save_item(NAME(m_wdog));
	82	}
	83
	84
	85	//-------------------------------------------------
	86	//  device_reset - device-specific reset
	87	//-------------------------------------------------
	88
	89	void namco_c117_device::device_reset()
	90	{
	91	// default MMU setup for main CPU
	92	m_offsets[0][0] = 0x0180 * 0x2000; // bank0 = 0x180(RAM) - evidence: wldcourt
	93	m_offsets[0][1] = 0x0180 * 0x2000; // bank1 = 0x180(RAM) - evidence: berabohm
	94	m_offsets[0][7] = 0x03ff * 0x2000; // bank7 = 0x3ff(PRG7)
	95
	96	// default MMU setup for sub CPU
	97	m_offsets[1][0] = 0x0180 * 0x2000; // bank0 = 0x180(RAM) - evidence: wldcourt
	98	m_offsets[1][7] = 0x03ff * 0x2000; // bank7 = 0x3ff(PRG7)
	99
	100	m_cpudirect[0]->force_update();
	101	m_cpudirect[1]->force_update();
	102
	103	m_subres = m_wdog = 0;
	104	m_subres_cb(ASSERT_LINE);
	105
	106	// reset the main CPU so it picks up the reset vector from the correct bank
	107	m_cpuexec[0]->set_input_line(INPUT_LINE_RESET, PULSE_LINE);
	108	}
	109
	110
	111	READ8_MEMBER(namco_c117_device::main_r)
	112	{
	113	return m_program->read_byte(remap(0, offset));
	114	}
	115
	116	READ8_MEMBER(namco_c117_device::sub_r)
	117	{
	118	return m_program->read_byte(remap(1, offset));
	119	}
	120
	121	WRITE8_MEMBER(namco_c117_device::main_w)
	122	{
	123	if (offset < 0xe000)
	124	m_program->write_byte(remap(0, offset), data);
	125	else
	126	register_w(0, offset, data);
	127	}
	128
	129	WRITE8_MEMBER(namco_c117_device::sub_w)
	130	{
	131	if (offset < 0xe000)
	132	m_program->write_byte(remap(1, offset), data);
	133	else
	134	register_w(1, offset, data);
	135	}
	136
	137	// FIXME: the sound CPU watchdog is probably in CUS121, and definitely isn't in CUS117
	138	// however, until the watchdog is a device and it's possible to have two independent
	139	// watchdogs in a machine, it's easiest to handle it here
	140	WRITE8_MEMBER(namco_c117_device::sound_watchdog_w)
	141	{
	142	kick_watchdog(2);
	143	}
	144
	145
	146	void namco_c117_device::register_w(int whichcpu, offs_t offset, UINT8 data)
	147	{
	148	int reg = (offset >> 9) & 0xf;
	149	bool unknown_reg = false;
	150
	151	switch (reg)
	152	{
	153	case 0:
	154	case 1:
	155	case 2:
	156	case 3:
	157	case 4:
	158	case 5:
	159	case 6:
	160	case 7:
	161	bankswitch(whichcpu, reg, offset & 1, data);
	162	break;
	163	case 8:  // F000 - SUBRES (halt/reset everything but main CPU)
	164	if (whichcpu == 0)
	165	{
	166	m_subres = data & 1;
	167	m_subres_cb(m_subres ? CLEAR_LINE : ASSERT_LINE);
	168	}
	169	else
	170	unknown_reg = true;
	171	break;
	172	case 9:  // F200 - kick watchdog
	173	kick_watchdog(whichcpu);
	174	break;
	175	//      case 10: // F400 - unknown but used
	176	//          break;
	177	case 11: // F600 - IRQ ack
	178	m_cpuexec[whichcpu]->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
	179	break;
	180	case 12: // F800 - FIRQ ack
	181	m_cpuexec[whichcpu]->set_input_line(M6809_FIRQ_LINE, CLEAR_LINE);
	182	break;
	183	case 13: // FA00 - assert FIRQ on sub CPU
	184	if (whichcpu == 0)
	185	m_cpuexec[1]->set_input_line(M6809_FIRQ_LINE, ASSERT_LINE);
	186	else
	187	unknown_reg = true;
	188	break;
	189	case 14: // FC00 - set initial ROM bank for sub CPU
	190	if (whichcpu == 0)
	191	{
	192	m_offsets[1][7] = 0x600000 | (data * 0x2000);
	193	m_cpudirect[1]->force_update();
	194	}
	195	else
	196	unknown_reg = true;
	197	break;
	198	default:
	199	unknown_reg = true;
	200	}
	201	if (unknown_reg)
	202	logerror("'%s' writing to unknown CUS117 register %04X = %02X\n", (whichcpu ? m_subcpu_tag : m_maincpu_tag), offset, data);
	203	}
	204
	205	void namco_c117_device::bankswitch(int whichcpu, int whichbank, int a0, UINT8 data)
	206	{
	207	UINT32 &bank = m_offsets[whichcpu][whichbank];
	208
	209	// even writes set a22-a21; odd writes set a20-a13
	210	if (a0 == 0)
	211	bank = (bank & 0x1fe000) | ((data & 0x03) * 0x200000);
	212	else
	213	bank = (bank & 0x600000) | (data * 0x2000);
	214
	215	m_cpudirect[whichcpu]->force_update();
	216	}
	217
	218	void namco_c117_device::kick_watchdog(int whichcpu)
	219	{
	220	// FIXME: change to 3 once sound CPU watchdog is separated from this device
	221	static const int ALL_CPU_MASK = 7;
	222
	223	m_wdog |= (1 << whichcpu);
	224
	225	if (m_wdog == ALL_CPU_MASK || !m_subres)
	226	{
	227	m_wdog = 0;
	228	machine().watchdog_reset();
	229	}
	230	}

Property changes on: trunk/src/mame/machine/c117.c

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trunk/src/mame/machine/c117.h

r0	r30937
	1	// license:BSD-3-Clause
	2	// copyright-holders:Alex W. Jackson
	3
	4	#pragma once
	5
	6	#ifndef __C117_H__
	7	#define __C117_H__
	8
	9
	10	//**************************************************************************
	11	//  INTERFACE CONFIGURATION MACROS
	12	//**************************************************************************
	13
	14	#define MCFG_CUS117_CPUS(_maincpu, _subcpu) \
	15	namco_c117_device::set_cpu_tags(*device, _maincpu, _subcpu);
	16
	17	#define MCFG_CUS117_SUBRES_CB(_devcb) \
	18	devcb = &namco_c117_device::set_subres_cb(*device, DEVCB_##_devcb);
	19
	20
	21	//***************************************************************************
	22	//  TYPE DEFINITIONS
	23	//***************************************************************************
	24
	25	class namco_c117_device :
	26	public device_t,
	27	public device_memory_interface
	28	{
	29	public:
	30	//construction/destruction
	31	namco_c117_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	32
	33	// static configuration
	34	static void set_cpu_tags(device_t &device, const char *maintag, const char *subtag);
	35	template<class _Object> static devcb_base &set_subres_cb(device_t &device, _Object object) { return downcast<namco_c117_device &>(device).m_subres_cb.set_callback(object); }
	36
	37	DECLARE_READ8_MEMBER(main_r);
	38	DECLARE_READ8_MEMBER(sub_r);
	39	DECLARE_WRITE8_MEMBER(main_w);
	40	DECLARE_WRITE8_MEMBER(sub_w);
	41
	42	// FIXME: this doesn't belong here
	43	DECLARE_WRITE8_MEMBER(sound_watchdog_w);
	44
	45	offs_t remap(int whichcpu, offs_t offset) { return m_offsets[whichcpu][offset>>13] | (offset & 0x1fff); }
	46
	47	protected:
	48	// device-level overrides
	49	virtual void device_start();
	50	virtual void device_reset();
	51
	52	// device_memory_interface overrides
	53	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
	54
	55	private:
	56	// internal helpers
	57	void register_w(int whichcpu, offs_t offset, UINT8 data);
	58	void bankswitch(int whichcpu, int whichbank, int a0, UINT8 data);
	59	void kick_watchdog(int whichcpu);
	60
	61	// internal state
	62	UINT32 m_offsets[2][8];
	63	UINT8 m_subres, m_wdog;
	64
	65	// callbacks
	66	devcb_write_line           m_subres_cb;
	67
	68	// address space
	69	const address_space_config m_program_config;
	70	address_space *            m_program;
	71
	72	// cpu interfaces
	73	device_execute_interface * m_cpuexec[2];
	74	direct_read_data *         m_cpudirect[2];
	75
	76	// configuration
	77	const char *               m_maincpu_tag;
	78	const char *               m_subcpu_tag;
	79	};
	80
	81	// device type definition
	82	extern const device_type NAMCO_C117;
	83
	84	#endif

Property changes on: trunk/src/mame/machine/c117.h

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trunk/src/mame/includes/namcos1.h

r30936	r30937
	1	#include "machine/c117.h"
1	2	#include "sound/dac.h"
2	3	#include "sound/namco.h"
3	4
4		#define NAMCOS1_MAX_BANK 0x400
5
6		/* Bank handler definitions */
7		struct bankhandler
8		{
9		read8_delegate bank_handler_r;
10		write8_delegate bank_handler_w;
11		int bank_offset;
12		UINT8 *bank_pointer;
13		};
14
15	5	class namcos1_state : public driver_device
16	6	{
17	7	public:
18	8	namcos1_state(const machine_config &mconfig, device_type type, const char *tag)
19		: driver_device(mconfig, type, tag) ,
	9	: driver_device(mconfig, type, tag),
20	10	m_maincpu(*this, "maincpu"),
21		m_audiocpu(*this, "audiocpu"),
22	11	m_subcpu(*this, "subcpu"),
	12	m_audiocpu(*this, "audiocpu"),
23	13	m_mcu(*this, "mcu"),
24		m_cus30(*this, "namco"),
	14	m_c117(*this, "c117"),
25	15	m_dac(*this, "dac"),
26	16	m_gfxdecode(*this, "gfxdecode"),
27		m_palette(*this, "palette") { }
	17	m_palette(*this, "palette"),
	18	m_paletteram(*this, "paletteram"),
	19	m_videoram(*this, "videoram"),
	20	m_spriteram(*this, "spriteram"),
	21	m_playfield_control(*this, "pfcontrol"),
	22	m_triram(*this, "triram"),
	23	m_rom(*this, "user1") { }
28	24
29	25	required_device<cpu_device> m_maincpu;
30		required_device<cpu_device> m_audiocpu;
31	26	required_device<cpu_device> m_subcpu;
	27	required_device<cpu_device> m_audiocpu;
32	28	required_device<cpu_device> m_mcu;
33		required_device<namco_cus30_device> m_cus30;
	29	required_device<namco_c117_device> m_c117;
34	30	required_device<dac_device> m_dac;
35	31	required_device<gfxdecode_device> m_gfxdecode;
36	32	required_device<palette_device> m_palette;
37	33
	34	required_shared_ptr<UINT8> m_paletteram;
	35	required_shared_ptr<UINT8> m_videoram;
	36	required_shared_ptr<UINT8> m_spriteram;
	37	required_shared_ptr<UINT8> m_playfield_control;
	38	required_shared_ptr<UINT8> m_triram;
	39
	40	required_memory_region m_rom;
	41
38	42	int m_dac0_value;
39	43	int m_dac1_value;
40	44	int m_dac0_gain;
41	45	int m_dac1_gain;
42		UINT8 *m_paletteram;
43		UINT8 *m_triram;
44		UINT8 *m_s1ram;
45		UINT8 *m_dummyrom;
46		bankhandler m_bank_element[NAMCOS1_MAX_BANK];
47		bankhandler m_active_bank[16];
48	46	int m_key_id;
49	47	int m_key_reg;
50	48	int m_key_rng;
r30936	r30937
58	56	UINT8 m_key[8];
59	57	int m_mcu_patch_data;
60	58	int m_reset;
61		int m_wdog;
62		int m_chip[16];
63	59	int m_input_count;
64	60	int m_strobe;
65	61	int m_strobe_count;
66	62	int m_stored_input[2];
67		UINT8 *m_videoram;
68	63	UINT8 m_cus116[0x10];
69		UINT8 *m_spriteram;
70		UINT8 m_playfield_control[0x20];
71	64	tilemap_t *m_bg_tilemap[6];
72	65	UINT8 *m_tilemap_maskdata;
73	66	int m_copy_sprites;
74	67	UINT8 m_drawmode_table[16];
75		DECLARE_WRITE8_MEMBER(namcos1_sub_firq_w);
	68	DECLARE_DIRECT_UPDATE_MEMBER(direct_handler_main);
	69	DECLARE_DIRECT_UPDATE_MEMBER(direct_handler_sub);
	70	DECLARE_WRITE_LINE_MEMBER(subres_w);
76	71	DECLARE_WRITE8_MEMBER(irq_ack_w);
77		DECLARE_WRITE8_MEMBER(firq_ack_w);
78	72	DECLARE_READ8_MEMBER(dsw_r);
79	73	DECLARE_WRITE8_MEMBER(namcos1_coin_w);
80	74	DECLARE_WRITE8_MEMBER(namcos1_dac_gain_w);
81	75	DECLARE_WRITE8_MEMBER(namcos1_dac0_w);
82	76	DECLARE_WRITE8_MEMBER(namcos1_dac1_w);
83	77	DECLARE_WRITE8_MEMBER(namcos1_sound_bankswitch_w);
84		DECLARE_WRITE8_MEMBER(namcos1_cpu_control_w);
85		DECLARE_WRITE8_MEMBER(namcos1_watchdog_w);
86		DECLARE_WRITE8_MEMBER(namcos1_bankswitch_w);
87		DECLARE_WRITE8_MEMBER(namcos1_subcpu_bank_w);
88	78	DECLARE_WRITE8_MEMBER(namcos1_mcu_bankswitch_w);
89	79	DECLARE_WRITE8_MEMBER(namcos1_mcu_patch_w);
90	80	DECLARE_READ8_MEMBER(quester_paddle_r);
r30936	r30937
126	116	void screen_eof_namcos1(screen_device &screen, bool state);
127	117	void namcos1_update_DACs();
128	118	void namcos1_init_DACs();
129		DECLARE_READ8_MEMBER( namcos1_videoram_r );
130	119	DECLARE_WRITE8_MEMBER( namcos1_videoram_w );
131	120	DECLARE_WRITE8_MEMBER( namcos1_paletteram_w );
132		DECLARE_READ8_MEMBER( namcos1_spriteram_r );
133	121	DECLARE_WRITE8_MEMBER( namcos1_spriteram_w );
134		inline UINT8 bank_r(address_space &space, offs_t offset, int bank);
135		READ8_MEMBER( bank1_r );
136		READ8_MEMBER( bank2_r );
137		READ8_MEMBER( bank3_r );
138		READ8_MEMBER( bank4_r );
139		READ8_MEMBER( bank5_r );
140		READ8_MEMBER( bank6_r );
141		READ8_MEMBER( bank7_r );
142		READ8_MEMBER( bank8_r );
143		READ8_MEMBER( bank9_r );
144		READ8_MEMBER( bank10_r );
145		READ8_MEMBER( bank11_r );
146		READ8_MEMBER( bank12_r );
147		READ8_MEMBER( bank13_r );
148		READ8_MEMBER( bank14_r );
149		READ8_MEMBER( bank15_r );
150		READ8_MEMBER( bank16_r );
151		inline void bank_w(address_space &space, offs_t offset, UINT8 data, int bank);
152		WRITE8_MEMBER( bank1_w );
153		WRITE8_MEMBER( bank2_w );
154		WRITE8_MEMBER( bank3_w );
155		WRITE8_MEMBER( bank4_w );
156		WRITE8_MEMBER( bank5_w );
157		WRITE8_MEMBER( bank6_w );
158		WRITE8_MEMBER( bank7_w );
159		WRITE8_MEMBER( bank8_w );
160		WRITE8_MEMBER( bank9_w );
161		WRITE8_MEMBER( bank10_w );
162		WRITE8_MEMBER( bank11_w );
163		WRITE8_MEMBER( bank12_w );
164		WRITE8_MEMBER( bank13_w );
165		WRITE8_MEMBER( bank14_w );
166		WRITE8_MEMBER( bank15_w );
167		WRITE8_MEMBER( bank16_w );
168	122	WRITE8_MEMBER( namcos1_3dcs_w );
169	123	READ8_MEMBER( no_key_r );
170	124	WRITE8_MEMBER( no_key_w );
r30936	r30937
174	128	WRITE8_MEMBER( key_type2_w );
175	129	READ8_MEMBER( key_type3_r );
176	130	WRITE8_MEMBER( key_type3_w );
177		READ8_MEMBER( soundram_r );
178		WRITE8_MEMBER( soundram_w );
179		WRITE8_MEMBER( rom_w );
180		READ8_MEMBER( unknown_r );
181		WRITE8_MEMBER( unknown_w );
182		void set_bank(int banknum, const bankhandler *handler);
183		void namcos1_bankswitch(int cpu, offs_t offset, UINT8 data);
184		void namcos1_install_bank(int start,int end,read8_delegate hr,write8_delegate hw,int offset,UINT8 *pointer);
185		void namcos1_build_banks(read8_delegate key_r,write8_delegate key_w);
186		struct namcos1_specific
187		{
188		/* keychip */
189		read8_delegate key_r;
190		write8_delegate key_w;
191		int key_id;
192		int key_reg1;
193		int key_reg2;
194		int key_reg3;
195		int key_reg4;
196		int key_reg5;
197		int key_reg6;
198		};
199
200		void namcos1_driver_init(const struct namcos1_specific *specific );
	131	void namcos1_driver_init();
201	132	private:
202		inline void bg_get_info(tile_data &tileinfo,int tile_index,UINT8 *info_vram);
203		inline void fg_get_info(tile_data &tileinfo,int tile_index,UINT8 *info_vram);
	133	inline offs_t direct_handler(int whichcpu, direct_read_data &direct, offs_t address);
	134	inline void get_tile_info(tile_data &tileinfo,int tile_index,UINT8 *info_vram);
204	135	};

trunk/src/mame/mame.mak

r30936	r30937
1507	1507	$(DRIVERS)/toypop.o $(VIDEO)/toypop.o \
1508	1508	$(DRIVERS)/turrett.o $(AUDIO)/turrett.o $(VIDEO)/turrett.o \
1509	1509	$(DRIVERS)/warpwarp.o $(AUDIO)/geebee.o $(AUDIO)/warpwarp.o $(VIDEO)/warpwarp.o \
	1510	$(MACHINE)/c117.o \
1510	1511	$(MACHINE)/namcoio.o \
1511	1512	$(MACHINE)/namco06.o \
1512	1513	$(MACHINE)/namco50.o \

trunk/src/mame/video/namcos1.c

r30936	r30937
50	50
51	51	***************************************************************************/
52	52
53		inline void namcos1_state::bg_get_info(tile_data &tileinfo,int tile_index,UINT8 *info_vram)
	53	inline void namcos1_state::get_tile_info(tile_data &tileinfo,int tile_index,UINT8 *info_vram)
54	54	{
55	55	int code;
56	56
r30936	r30937
60	60	tileinfo.mask_data = &m_tilemap_maskdata[code << 3];
61	61	}
62	62
63		inline void namcos1_state::fg_get_info(tile_data &tileinfo,int tile_index,UINT8 *info_vram)
64		{
65		int code;
66
67		tile_index <<= 1;
68		code = info_vram[tile_index + 1] + ((info_vram[tile_index] & 0x3f) << 8);
69		SET_TILE_INFO_MEMBER(0,code,0,0);
70		tileinfo.mask_data = &m_tilemap_maskdata[code << 3];
71		}
72
73	63	TILE_GET_INFO_MEMBER(namcos1_state::bg_get_info0)
74	64	{
75		bg_get_info(tileinfo,tile_index,&m_videoram[0x0000]);
	65	get_tile_info(tileinfo,tile_index,&m_videoram[0x0000]);
76	66	}
77	67
78	68	TILE_GET_INFO_MEMBER(namcos1_state::bg_get_info1)
79	69	{
80		bg_get_info(tileinfo,tile_index,&m_videoram[0x2000]);
	70	get_tile_info(tileinfo,tile_index,&m_videoram[0x2000]);
81	71	}
82	72
83	73	TILE_GET_INFO_MEMBER(namcos1_state::bg_get_info2)
84	74	{
85		bg_get_info(tileinfo,tile_index,&m_videoram[0x4000]);
	75	get_tile_info(tileinfo,tile_index,&m_videoram[0x4000]);
86	76	}
87	77
88	78	TILE_GET_INFO_MEMBER(namcos1_state::bg_get_info3)
89	79	{
90		bg_get_info(tileinfo,tile_index,&m_videoram[0x6000]);
	80	get_tile_info(tileinfo,tile_index,&m_videoram[0x6000]);
91	81	}
92	82
93	83	TILE_GET_INFO_MEMBER(namcos1_state::fg_get_info4)
94	84	{
95		fg_get_info(tileinfo,tile_index,&m_videoram[0x7010]);
	85	get_tile_info(tileinfo,tile_index,&m_videoram[0x7010]);
96	86	}
97	87
98	88	TILE_GET_INFO_MEMBER(namcos1_state::fg_get_info5)
99	89	{
100		fg_get_info(tileinfo,tile_index,&m_videoram[0x7810]);
	90	get_tile_info(tileinfo,tile_index,&m_videoram[0x7810]);
101	91	}
102	92
103	93
r30936	r30937
114	104
115	105	m_tilemap_maskdata = (UINT8 *)memregion("gfx1")->base();
116	106
117		/* allocate videoram */
118		m_videoram = auto_alloc_array_clear(machine(), UINT8, 0x8000);
119		m_spriteram = auto_alloc_array_clear(machine(), UINT8, 0x1000);
120
121	107	/* initialize playfields */
122	108	m_bg_tilemap[0] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcos1_state::bg_get_info0),this),TILEMAP_SCAN_ROWS,8,8,64,64);
123	109	m_bg_tilemap[1] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcos1_state::bg_get_info1),this),TILEMAP_SCAN_ROWS,8,8,64,64);
r30936	r30937
140	126	m_bg_tilemap[5]->set_scrolldy(16, 16);
141	127
142	128	/* register videoram to the save state system (post-allocation) */
143		save_pointer(NAME(m_videoram), 0x8000);
144	129	save_item(NAME(m_cus116));
145		save_pointer(NAME(m_spriteram), 0x1000);
146		save_item(NAME(m_playfield_control));
147	130
148	131	/* set table for sprite color == 0x7f */
149	132	for (i = 0;i < 15;i++)
r30936	r30937
175	158
176	159	***************************************************************************/
177	160
178		READ8_MEMBER( namcos1_state::namcos1_videoram_r )
179		{
180		return m_videoram[offset];
181		}
182
183	161	WRITE8_MEMBER( namcos1_state::namcos1_videoram_w )
184	162	{
185	163	m_videoram[offset] = data;
r30936	r30937
235	213
236	214
237	215
238
239		READ8_MEMBER( namcos1_state::namcos1_spriteram_r )
240		{
241		/* 0000-07ff work ram */
242		/* 0800-0fff sprite ram */
243		if (offset < 0x1000)
244		return m_spriteram[offset];
245		/* 1xxx playfield control ram */
246		else
247		return m_playfield_control[offset & 0x1f];
248		}
249
250	216	WRITE8_MEMBER( namcos1_state::namcos1_spriteram_w )
251	217	{
252	218	/* 0000-07ff work ram */
253	219	/* 0800-0fff sprite ram */
254		if (offset < 0x1000)
255		{
256		m_spriteram[offset] = data;
	220	m_spriteram[offset] = data;
257	221
258		/* a write to this offset tells the sprite chip to buffer the sprite list */
259		if (offset == 0x0ff2)
260		m_copy_sprites = 1;
261		}
262		/* 1xxx playfield control ram */
263		else
264		m_playfield_control[offset & 0x1f] = data;
	222	/* a write to this offset tells the sprite chip to buffer the sprite list */
	223	if (offset == 0x0ff2)
	224	m_copy_sprites = 1;
265	225	}
266	226
267	227

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