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r30889 Sunday 8th June, 2014 at 18:39:43 UTC by Michael Zapf
(MESS) Preparing new HFDC implementation with new HDC9234. (nw)
[src/emu/bus/ti99_peb]hfdc.c hfdc.h peribox.c peribox.h
[src/emu/machine]machine.mak
[src/mess]mess.mak

trunk/src/emu/bus/ti99_peb/peribox.c
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339339*/
340340void peribox_device::inta_join(int slot, int state)
341341{
342   if (TRACE_INT) logerror("Peribox propagating INTA from slot %d to console: %d\n", slot, state);
342   if (TRACE_INT) logerror("%s: propagating INTA from slot %d to console: %d\n", tag(), slot, state);
343343   if (state==ASSERT_LINE)
344344      m_inta_flag |= (1 << slot);
345345   else
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350350
351351void peribox_device::intb_join(int slot, int state)
352352{
353   if (TRACE_INT) logerror("Peribox propagating INTB from slot %d to console: %d\n", slot, state);
353   if (TRACE_INT) logerror("%s: propagating INTB from slot %d to console: %d\n", tag(), slot, state);
354354   if (state==ASSERT_LINE)
355355      m_intb_flag |= (1 << slot);
356356   else
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364364*/
365365void peribox_device::ready_join(int slot, int state)
366366{
367   if (TRACE_READY) logerror("peribox: Incoming READY=%d from slot %d\n", state, slot);
367   if (TRACE_READY) logerror("%s: Incoming READY=%d from slot %d\n", tag(), state, slot);
368368   // We store the inverse state
369369   if (state==CLEAR_LINE)
370370      m_ready_flag |= (1 << slot);
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376376
377377void peribox_device::set_slot_loaded(int slot, peribox_slot_device* slotdev)
378378{
379   if (TRACE_EMU)
380   {
381      if (slotdev!=NULL) logerror("Setting slot %d to device %s\n", slot, slotdev->tag());
382      else logerror("Setting slot %d to EMPTY\n", slot);
383   }
384379   m_slot[slot] = slotdev;
385380}
386381
387382void peribox_device::device_start(void)
388383{
389   if (TRACE_EMU) logerror("Peribox started\n");
384   if (TRACE_EMU) logerror("%s: started\n", tag());
390385
391386   subdevice<legacy_floppy_image_device>(FLOPPY_0)->floppy_drive_set_rpm(300.);
392387   subdevice<legacy_floppy_image_device>(FLOPPY_1)->floppy_drive_set_rpm(300.);
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398393   m_console_intb.resolve();
399394   m_datamux_ready.resolve();
400395
401   if (TRACE_EMU) logerror("AMA/B/C address prefix set to %05x\n", m_address_prefix);
396   if (TRACE_EMU)
397   {
398      logerror("%s: AMA/B/C address prefix set to %05x\n", tag(), m_address_prefix);
399      for (int i=2; i < 9; i++)
400      {
401         logerror("%s: Slot %d = %s\n", tag(), i, (m_slot[i] != NULL)? m_slot[i]->m_card->tag() : "EMPTY");
402      }
403   }
402404}
403405
404406void peribox_device::device_config_complete()
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431433   SLOT_INTERFACE("usbsm", TI99_USBSM)
432434   SLOT_INTERFACE("bwgleg", TI99_BWG_LEG)
433435   SLOT_INTERFACE("bwg", TI99_BWG)
434   SLOT_INTERFACE("hfdc", TI99_HFDC)
436   SLOT_INTERFACE("hfdc", TI99_HFDC_LEG)
437   SLOT_INTERFACE("hfdcnew", TI99_HFDC)
435438SLOT_INTERFACE_END
436439
437440SLOT_INTERFACE_START( peribox_slot8 )
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439442   SLOT_INTERFACE("tifdc", TI99_FDC)
440443   SLOT_INTERFACE("bwgleg", TI99_BWG_LEG)
441444   SLOT_INTERFACE("bwg", TI99_BWG)
442   SLOT_INTERFACE("hfdc", TI99_HFDC)
445   SLOT_INTERFACE("hfdc", TI99_HFDC_LEG)
446   SLOT_INTERFACE("hfdcnew", TI99_HFDC)
443447SLOT_INTERFACE_END
444448
445449MACHINE_CONFIG_FRAGMENT( peribox_device )
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463467   MCFG_DEVICE_ADD(FLOPPY_3, LEGACY_FLOPPY, 0)
464468   MCFG_DEVICE_CONFIG(ti99_4_floppy_interface)
465469   MCFG_LEGACY_FLOPPY_IDX_CB(WRITELINE(peribox_device, indexhole))
466   
470
467471   MCFG_MFMHD_3_DRIVES_ADD()
468472MACHINE_CONFIG_END
469473
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490494SLOT_INTERFACE_START( peribox_slot7nobwg )
491495   SLOT_INTERFACE("ide", TI99_IDE)
492496   SLOT_INTERFACE("usbsm", TI99_USBSM)
493   SLOT_INTERFACE("hfdc", TI99_HFDC)
497   SLOT_INTERFACE("hfdc", TI99_HFDC_LEG)
498   SLOT_INTERFACE("hfdcnew", TI99_HFDC)
494499SLOT_INTERFACE_END
495500
496501SLOT_INTERFACE_START( peribox_slot8nobwg )
497502   SLOT_INTERFACE("tifdcleg", TI99_FDC_LEG)
498503   SLOT_INTERFACE("tifdc", TI99_FDC)
499   SLOT_INTERFACE("hfdc", TI99_HFDC)
504   SLOT_INTERFACE("hfdc", TI99_HFDC_LEG)
505   SLOT_INTERFACE("hfdcnew", TI99_HFDC)
500506SLOT_INTERFACE_END
501507
502508SLOT_INTERFACE_START( peribox_slotg )
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527533   MCFG_DEVICE_ADD(FLOPPY_2, LEGACY_FLOPPY, 0)
528534   MCFG_DEVICE_CONFIG(ti99_4_floppy_interface)
529535   MCFG_LEGACY_FLOPPY_IDX_CB(WRITELINE(peribox_device, indexhole))
530   MCFG_DEVICE_ADD(FLOPPY_3, LEGACY_FLOPPY, 0)   
536   MCFG_DEVICE_ADD(FLOPPY_3, LEGACY_FLOPPY, 0)
531537   MCFG_DEVICE_CONFIG(ti99_4_floppy_interface)
532538   MCFG_LEGACY_FLOPPY_IDX_CB(WRITELINE(peribox_device, indexhole))
533539   MCFG_MFMHD_3_DRIVES_ADD()
trunk/src/emu/bus/ti99_peb/peribox.h
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149149
150150class peribox_slot_device : public bus8z_device, public device_slot_interface
151151{
152   friend class peribox_device;
152153public:
153154   peribox_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
154155
trunk/src/emu/bus/ti99_peb/hfdc.c
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1515
1616    February 2012: Rewritten as class
1717
18    June 2014: Rewritten for modern floppy implementation
19
20    WORK IN PROGRESS
21
1822*****************************************************************************/
1923
24#include "emu.h"
25#include "peribox.h"
2026#include "hfdc.h"
27#include "machine/ti99_hd.h"
2128#include "imagedev/flopdrv.h"
2229#include "formats/ti99_dsk.h"       // Format
2330
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2734
2835#define MOTOR_TIMER 1
2936
30#define HFDC_MAX_FLOPPY 4
31#define HFDC_MAX_HARD 4
32
3337#define TAPE_ADDR   0x0fc0
3438#define HDC_R_ADDR  0x0fd0
3539#define HDC_W_ADDR  0x0fd2
3640#define CLK_ADDR    0x0fe0
3741#define RAM_ADDR    0x1000
3842
39#define VERBOSE 1
40#define LOG logerror
43#define TRACE_EMU 1
44#define TRACE_CRU 1
4145
46// =========================================================================
47
48/*
49    Modern implementation.
50*/
4251myarc_hfdc_device::myarc_hfdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
4352   : ti_expansion_card_device(mconfig, TI99_HFDC, "Myarc Hard and Floppy Disk Controller", tag, owner, clock, "ti99_hfdc", __FILE__),
4453      m_hdc9234(*this, FDC_TAG),
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4756}
4857
4958/*
59    Read a byte from the memory address space of the HFDC
60
61    0x4000 - 0x4fbf one of four possible ROM pages
62    0x4fc0 - 0x4fcf Tape control (only available in prototype HFDC models)
63    0x4fd0 - 0x4fdf HDC 9234 ports
64    0x4fe0 - 0x4fff RTC chip ports
65
66    0x5000 - 0x53ff static RAM page 0x10
67    0x5400 - 0x57ff static RAM page any of 32 pages
68    0x5800 - 0x5bff static RAM page any of 32 pages
69    0x5c00 - 0x5fff static RAM page any of 32 pages
70
71    HFDC manual, p. 44
72*/
73READ8Z_MEMBER(myarc_hfdc_device::readz)
74{
75   if (m_selected && ((offset & m_select_mask)==m_select_value))
76   {
77      logerror("%s: Read access to %04x\n", tag(), offset & 0xffff);
78   }
79}
80
81/*
82    Write a byte to the memory address space of the HFDC
83
84    0x4fc0 - 0x4fcf Tape control (only available in prototype HFDC models)
85    0x4fd0 - 0x4fdf HDC 9234 ports
86    0x4fe0 - 0x4fff RTC chip ports
87
88    0x5000 - 0x53ff static RAM page 0x08
89    0x5400 - 0x57ff static RAM page any of 32 pages
90    0x5800 - 0x5bff static RAM page any of 32 pages
91    0x5c00 - 0x5fff static RAM page any of 32 pages
92*/
93WRITE8_MEMBER( myarc_hfdc_device::write )
94{
95   if (m_selected && ((offset & m_select_mask)==m_select_value))
96   {
97      logerror("%s: Write access to %04x: %02x\n", tag(), offset & 0xffff, data);
98   }
99}
100
101/*
102    Read a set of 8 bits in the CRU space of the HFDC
103    There are two banks, according to the state of m_see_switches
104
105    m_see_switches == true:
106
107       7     6     5     4     3     2     1     0
108    +-----+-----+-----+-----+-----+-----+-----+-----+
109    |DIP1*|DIP2*|DIP3*|DIP4*|DIP5*|DIP6*|DIP7*|DIP8*|
110    +-----+-----+-----+-----+-----+-----+-----+-----+
111
112    MZ: The setting 00 (all switches on) is a valid setting according to the
113        HFDC manual and indicates 36 sectors/track, 80 tracks; however, this
114        setting is intended "for possible future expansion" and cannot fall
115        back to lower formats, hence, single density disks cannot be read.
116    ---
117
118    m_see_switches == false:
119
120       7     6     5     4     3     2     1     0
121    +-----+-----+-----+-----+-----+-----+-----+-----+
122    |  0  |  0  |  0  |  0  |  0  | MON | DIP | IRQ |
123    +-----+-----+-----+-----+-----+-----+-----+-----+
124
125    MON = Motor on
126    DIP = DMA in progress
127    IRQ = Interrupt request
128    ---
129    0 on all other locations
130*/
131READ8Z_MEMBER(myarc_hfdc_device::crureadz)
132{
133   if ((offset & 0xff00)==m_cru_base)
134   {
135      if (TRACE_CRU) logerror("%s: CRU read access to %04x\n", tag(), offset & 0xffff);
136   }
137}
138
139/*
140    Set a bit in the CRU space of the HFDC
141
142       7     6     5     4     3     2     1     0
143    +-----+-----+-----+-----+-----+-----+-----+-----+
144    |  0  | MON | DIP | ROM1| ROM0| MON | RES | SEL |
145    |     |     |     | CSEL| CD1 | CD0 |     |     |
146    +-----+-----+-----+-----+-----+-----+-----+-----+
147
148       17    16    15    14    13    12    11    10    F     E     D     C     B     A     9     8
149    +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+
150    |    RAM page select @5C00    |    RAM page select @5800    |     RAM page select @5400   |  -  |
151    +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+
152
153    SEL = Select card (and map ROM into address space)
154    RES = Reset controller
155    MON = Motor on
156    ROM bank select: bank 0..3; bit 3 = MSB, 4 = LSB
157    RAM bank select: bank 0..31; bit 9 = LSB (accordingly for other two areas)
158    CD0 and CD1 are Clock Divider selections for the Floppy Data Separator (FDC9216)
159    CSEL = cru_select
160
161    HFDC manual p. 43
162*/
163WRITE8_MEMBER(myarc_hfdc_device::cruwrite)
164{
165   if ((offset & 0xff00)==m_cru_base)
166   {
167      if (TRACE_CRU) logerror("%s: CRU write access to %04x: %d\n", tag(), offset & 0xffff, data);
168
169      int bit = (offset >> 1) & 0x1f;
170
171      // Handle the page selects right here
172      if (bit >= 0x09 && bit < 0x18)
173      {
174         if (data)
175            // we leave index 0 unchanged; modify indices 1-3
176            m_ram_page[(bit-4)/5] |= 1 << ((bit-9)%5);
177         else
178            m_ram_page[(bit-4)/5] &= ~(1 << ((bit-9)%5));
179         return;
180      }
181
182      switch (bit)
183      {
184      case 0:
185         m_selected = (data!=0);
186         if (TRACE_CRU) logerror("%s: selected = %d\n", tag(), m_selected);
187         break;
188      }
189   }
190}
191
192/*
193    Called whenever the state of the HDC9234 interrupt pin changes.
194*/
195WRITE_LINE_MEMBER( myarc_hfdc_device::intrq_w )
196{
197   m_irq = state;
198
199   // Set INTA*
200   // Signal from SMC is active high, INTA* is active low; board inverts signal
201   // Anyway, we keep with ASSERT_LINE and CLEAR_LINE
202   m_slot->set_inta(state);
203}
204
205/*
206    Called whenever the state of the HDC9234 DMA in progress changes.
207*/
208WRITE_LINE_MEMBER( myarc_hfdc_device::dip_w )
209{
210   m_dip = state;
211}
212
213WRITE8_MEMBER( myarc_hfdc_device::auxbus_out )
214{
215   logerror("%s: Write access to auxbus at %04x: %02x\n", tag(), offset & 0xffff, data);
216}
217
218READ8_MEMBER( myarc_hfdc_device::auxbus_in )
219{
220   logerror("%s: Read access to auxbus at %04x\n", tag(), offset & 0xffff);
221   return 0;
222}
223
224/*
225    Read a byte from the onboard SRAM
226*/
227READ8_MEMBER( myarc_hfdc_device::read_buffer )
228{
229   logerror("%s: Read access to onboard SRAM at %04x\n", tag(), offset & 0xffff);
230   return 0;
231}
232
233/*
234    Write a byte to the onboard SRAM
235*/
236WRITE8_MEMBER( myarc_hfdc_device::write_buffer )
237{
238   logerror("%s: Write access to onboard SRAM at %04x: %02x\n", tag(), offset & 0xffff, data);
239}
240
241void myarc_hfdc_device::device_start()
242{
243   if (TRACE_EMU) logerror("%s: start\n", tag());
244   m_dsrrom = memregion(DSRROM)->base();
245   m_buffer_ram = memregion(BUFFER)->base();
246   m_motor_on_timer = timer_alloc(MOTOR_TIMER);
247   // The HFDC does not use READY; it has on-board RAM for DMA
248}
249
250void myarc_hfdc_device::device_reset()
251{
252   if (TRACE_EMU) logerror("%s: reset\n", tag());
253
254   // The GenMOD mod; our implementation automagically adapts all cards
255   if (m_genmod)
256   {
257      m_select_mask = 0x1fe000;
258      m_select_value = 0x174000;
259   }
260   else
261   {
262      m_select_mask = 0x7e000;
263      m_select_value = 0x74000;
264   }
265
266   m_cru_base = ioport("CRUHFDC")->read();
267
268   // Resetting values
269   m_rom_page = 0;
270
271   m_ram_page[0] = 0x08;   // static page 0x08
272   for (int i=1; i < 4; i++) m_ram_page[i] = 0;
273
274   m_output1_latch = m_output2_latch = 0;
275   m_dip = m_irq = false;
276   m_see_switches = false;
277   m_CD = 0;
278   m_motor_running = false;
279   m_selected = false;
280}
281
282INPUT_PORTS_START( ti99_hfdc )
283   PORT_START( "CRUHFDC" )
284   PORT_DIPNAME( 0x1f00, 0x1100, "HFDC CRU base" )
285      PORT_DIPSETTING( 0x1000, "1000" )
286      PORT_DIPSETTING( 0x1100, "1100" )
287      PORT_DIPSETTING( 0x1200, "1200" )
288      PORT_DIPSETTING( 0x1300, "1300" )
289      PORT_DIPSETTING( 0x1400, "1400" )
290      PORT_DIPSETTING( 0x1500, "1500" )
291      PORT_DIPSETTING( 0x1600, "1600" )
292      PORT_DIPSETTING( 0x1700, "1700" )
293      PORT_DIPSETTING( 0x1800, "1800" )
294      PORT_DIPSETTING( 0x1900, "1900" )
295      PORT_DIPSETTING( 0x1a00, "1A00" )
296      PORT_DIPSETTING( 0x1b00, "1B00" )
297      PORT_DIPSETTING( 0x1c00, "1C00" )
298      PORT_DIPSETTING( 0x1d00, "1D00" )
299      PORT_DIPSETTING( 0x1e00, "1E00" )
300      PORT_DIPSETTING( 0x1f00, "1F00" )
301
302   PORT_START( "HFDCDIP" )
303   PORT_DIPNAME( 0xff, 0x55, "HFDC drive config" )
304      PORT_DIPSETTING( 0x00, "40 track, 16 ms")
305      PORT_DIPSETTING( 0xaa, "40 track, 8 ms")
306      PORT_DIPSETTING( 0x55, "80 track, 2 ms")
307      PORT_DIPSETTING( 0xff, "80 track HD, 2 ms")
308INPUT_PORTS_END
309
310MACHINE_CONFIG_FRAGMENT( ti99_hfdc )
311   MCFG_DEVICE_ADD(FDC_TAG, HDC9234, 0)
312   MCFG_HDC9234_INTRQ_CALLBACK(WRITELINE(myarc_hfdc_device, intrq_w))
313   MCFG_HDC9234_DIP_CALLBACK(WRITELINE(myarc_hfdc_device, dip_w))
314   MCFG_HDC9234_AUXBUS_OUT_CALLBACK(WRITE8(myarc_hfdc_device, auxbus_out))
315   MCFG_HDC9234_AUXBUS_IN_CALLBACK(READ8(myarc_hfdc_device, auxbus_in))
316   MCFG_HDC9234_DMA_IN_CALLBACK(READ8(myarc_hfdc_device, read_buffer))
317   MCFG_HDC9234_DMA_OUT_CALLBACK(WRITE8(myarc_hfdc_device, write_buffer))
318
319   MCFG_DEVICE_ADD(CLOCK_TAG, MM58274C, 0)
320   MCFG_MM58274C_MODE24(1) // 24 hour
321   MCFG_MM58274C_DAY1(0)   // sunday
322MACHINE_CONFIG_END
323
324ROM_START( ti99_hfdc )
325   ROM_REGION(0x4000, DSRROM, 0)
326   ROM_LOAD("hfdc.bin", 0x0000, 0x4000, CRC(66fbe0ed) SHA1(11df2ecef51de6f543e4eaf8b2529d3e65d0bd59)) /* HFDC disk DSR ROM */
327   ROM_REGION(0x8000, BUFFER, 0)  /* HFDC RAM buffer 32 KiB */
328   ROM_FILL(0x0000, 0x8000, 0x00)
329ROM_END
330
331
332machine_config_constructor myarc_hfdc_device::device_mconfig_additions() const
333{
334   return MACHINE_CONFIG_NAME( ti99_hfdc );
335}
336
337const rom_entry *myarc_hfdc_device::device_rom_region() const
338{
339   return ROM_NAME( ti99_hfdc );
340}
341
342ioport_constructor myarc_hfdc_device::device_input_ports() const
343{
344   return INPUT_PORTS_NAME( ti99_hfdc );
345}
346
347const device_type TI99_HFDC = &device_creator<myarc_hfdc_device>;
348
349// =========================================================================
350
351/*
352    Legacy implementation.
353*/
354#define VERBOSE 1
355#define LOG logerror
356
357myarc_hfdc_legacy_device::myarc_hfdc_legacy_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
358   : ti_expansion_card_device(mconfig, TI99_HFDC_LEG, "Myarc Hard and Floppy Disk Controller LEGACY", tag, owner, clock, "ti99_hfdc", __FILE__),
359      m_hdc9234(*this, FDC_TAG),
360      m_clock(*this, CLOCK_TAG)
361{
362}
363
364/*
50365    read a byte in disk DSR space
51366    HFDC manual, p. 44
52367    Memory map as seen by the 99/4A PEB
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61376    0x5800 - 0x5bff static RAM page any of 32 pages
62377    0x5c00 - 0x5fff static RAM page any of 32 pages
63378*/
64READ8Z_MEMBER(myarc_hfdc_device::readz)
379READ8Z_MEMBER(myarc_hfdc_legacy_device::readz)
65380{
66381   if (m_selected && ((offset & m_select_mask)==m_select_value))
67382   {
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119434/*
120435    Write a byte to the controller.
121436*/
122WRITE8_MEMBER( myarc_hfdc_device::write )
437WRITE8_MEMBER( myarc_hfdc_legacy_device::write )
123438{
124439   if (m_selected && ((offset & m_select_mask)==m_select_value))
125440   {
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160475   }
161476}
162477
163READ8Z_MEMBER(myarc_hfdc_device::crureadz)
478READ8Z_MEMBER(myarc_hfdc_legacy_device::crureadz)
164479{
165480   UINT8 reply;
166481   if ((offset & 0xff00)==m_cru_base)
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213528    Bit number = (CRU_rel_address - base_address)/2
214529    CD0 and CD1 are Clock Divider selections for the Floppy Data Separator (FDC9216)
215530*/
216WRITE8_MEMBER(myarc_hfdc_device::cruwrite)
531WRITE8_MEMBER(myarc_hfdc_legacy_device::cruwrite)
217532{
218533   if ((offset & 0xff00)==m_cru_base)
219534   {
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273588}
274589
275590
276int myarc_hfdc_device::slog2(int value)
591int myarc_hfdc_legacy_device::slog2(int value)
277592{
278593   int i=-1;
279594   while (value!=0)
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284599   return i;
285600}
286601
287READ8_MEMBER( myarc_hfdc_device::auxbus_in )
602READ8_MEMBER( myarc_hfdc_legacy_device::auxbus_in )
288603{
289604   UINT8 reply = 0;
290605   int index = 0;
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335650   return reply;
336651}
337652
338WRITE8_MEMBER( myarc_hfdc_device::auxbus_out )
653WRITE8_MEMBER( myarc_hfdc_legacy_device::auxbus_out )
339654{
340655   int index;
341656   switch (offset)
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383698/*
384699    Read a byte from buffer in DMA mode
385700*/
386READ8_MEMBER( myarc_hfdc_device::read_buffer )
701READ8_MEMBER( myarc_hfdc_legacy_device::read_buffer )
387702{
388703   UINT8 value = m_buffer_ram[m_dma_address & 0x7fff];
389704   m_dma_address++;
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393708/*
394709    Write a byte to buffer in DMA mode
395710*/
396WRITE8_MEMBER( myarc_hfdc_device::write_buffer )
711WRITE8_MEMBER( myarc_hfdc_legacy_device::write_buffer )
397712{
398713   m_buffer_ram[m_dma_address & 0x7fff] = data;
399714   m_dma_address++;
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402717/*
403718    Called whenever the state of the sms9234 interrupt pin changes.
404719*/
405WRITE_LINE_MEMBER( myarc_hfdc_device::intrq_w )
720WRITE_LINE_MEMBER( myarc_hfdc_legacy_device::intrq_w )
406721{
407722   m_irq = state;
408723
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412727   m_slot->set_inta(state);
413728}
414729
415
416730/*
417731    Called whenever the state of the sms9234 DMA in progress changes.
418732*/
419WRITE_LINE_MEMBER( myarc_hfdc_device::dip_w )
733WRITE_LINE_MEMBER( myarc_hfdc_legacy_device::dip_w )
420734{
421735   m_dip = state;
422736}
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424738/*
425739    Callback called at the end of DVENA pulse
426740*/
427void myarc_hfdc_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
741void myarc_hfdc_legacy_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
428742{
429743   m_motor_running = false;
430744   if (VERBOSE>6) LOG("hfdc: motor off\n");
431745}
432746
433MACHINE_CONFIG_FRAGMENT( ti99_hfdc )
747MACHINE_CONFIG_FRAGMENT( ti99_hfdc_legacy )
434748   MCFG_DEVICE_ADD(FDC_TAG, SMC92X4, 0)
435   MCFG_SMC92X4_INTRQ_CALLBACK(WRITELINE(myarc_hfdc_device, intrq_w))
436   MCFG_SMC92X4_DIP_CALLBACK(WRITELINE(myarc_hfdc_device, dip_w))
437   MCFG_SMC92X4_AUXBUS_OUT_CALLBACK(WRITE8(myarc_hfdc_device, auxbus_out))
438   MCFG_SMC92X4_AUXBUS_IN_CALLBACK(READ8(myarc_hfdc_device, auxbus_in))
439   MCFG_SMC92X4_DMA_IN_CALLBACK(READ8(myarc_hfdc_device, read_buffer))
440   MCFG_SMC92X4_DMA_OUT_CALLBACK(WRITE8(myarc_hfdc_device, write_buffer))
749   MCFG_SMC92X4_INTRQ_CALLBACK(WRITELINE(myarc_hfdc_legacy_device, intrq_w))
750   MCFG_SMC92X4_DIP_CALLBACK(WRITELINE(myarc_hfdc_legacy_device, dip_w))
751   MCFG_SMC92X4_AUXBUS_OUT_CALLBACK(WRITE8(myarc_hfdc_legacy_device, auxbus_out))
752   MCFG_SMC92X4_AUXBUS_IN_CALLBACK(READ8(myarc_hfdc_legacy_device, auxbus_in))
753   MCFG_SMC92X4_DMA_IN_CALLBACK(READ8(myarc_hfdc_legacy_device, read_buffer))
754   MCFG_SMC92X4_DMA_OUT_CALLBACK(WRITE8(myarc_hfdc_legacy_device, write_buffer))
441755   MCFG_SMC92X4_FULL_TRACK_LAYOUT(FALSE)    /* do not use the full track layout */
442756
443757   MCFG_DEVICE_ADD(CLOCK_TAG, MM58274C, 0)
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445759   MCFG_MM58274C_DAY1(0)   // sunday
446760MACHINE_CONFIG_END
447761
448ROM_START( ti99_hfdc )
762ROM_START( ti99_hfdc_legacy )
449763   ROM_REGION(0x4000, DSRROM, 0)
450764   ROM_LOAD("hfdc.bin", 0x0000, 0x4000, CRC(66fbe0ed) SHA1(11df2ecef51de6f543e4eaf8b2529d3e65d0bd59)) /* HFDC disk DSR ROM */
451765   ROM_REGION(0x8000, BUFFER, 0)  /* HFDC RAM buffer 32 KiB */
452766   ROM_FILL(0x0000, 0x8000, 0x00)
453767ROM_END
454768
455INPUT_PORTS_START( ti99_hfdc )
769INPUT_PORTS_START( ti99_hfdc_legacy )
456770   PORT_START( "CRUHFDC" )
457771   PORT_DIPNAME( 0x1f00, 0x1100, "HFDC CRU base" )
458772      PORT_DIPSETTING( 0x1000, "1000" )
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485799      PORT_CONFSETTING( 0x01, "Realistic")
486800INPUT_PORTS_END
487801
488void myarc_hfdc_device::device_start()
802void myarc_hfdc_legacy_device::device_start()
489803{
490804   if (VERBOSE>5) LOG("hfdc: start\n");
491805   m_dsrrom = memregion(DSRROM)->base();
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496810   // The HFDC does not use READY; it has on-board RAM for DMA
497811}
498812
499void myarc_hfdc_device::device_reset()
813void myarc_hfdc_legacy_device::device_reset()
500814{
501815   if (VERBOSE>5) LOG("hfdc: reset\n");
502816   if (m_genmod)
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558872   // TODO: Check how to make use of   floppy_mon_w(w->drive, CLEAR_LINE);
559873}
560874
561machine_config_constructor myarc_hfdc_device::device_mconfig_additions() const
875machine_config_constructor myarc_hfdc_legacy_device::device_mconfig_additions() const
562876{
563   return MACHINE_CONFIG_NAME( ti99_hfdc );
877   return MACHINE_CONFIG_NAME( ti99_hfdc_legacy );
564878}
565879
566const rom_entry *myarc_hfdc_device::device_rom_region() const
880const rom_entry *myarc_hfdc_legacy_device::device_rom_region() const
567881{
568   return ROM_NAME( ti99_hfdc );
882   return ROM_NAME( ti99_hfdc_legacy );
569883}
570884
571ioport_constructor myarc_hfdc_device::device_input_ports() const
885ioport_constructor myarc_hfdc_legacy_device::device_input_ports() const
572886{
573   return INPUT_PORTS_NAME(ti99_hfdc);
887   return INPUT_PORTS_NAME(ti99_hfdc_legacy);
574888}
575889
576const device_type TI99_HFDC = &device_creator<myarc_hfdc_device>;
890const device_type TI99_HFDC_LEG = &device_creator<myarc_hfdc_legacy_device>;
trunk/src/emu/bus/ti99_peb/hfdc.h
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88    Michael Zapf, September 2010
99
1010    January 2012: rewritten as class
11    June 2014: rewritten for modern floppy implementation
1112
13    WORK IN PROGRESS
14
1215****************************************************************************/
1316
1417#ifndef __HFDC__
1518#define __HFDC__
1619
17#include "emu.h"
18#include "peribox.h"
19#include "machine/ti99_hd.h"
20#include "machine/smc92x4.h"
21#include "machine/mm58274c.h"
22
2320#define HFDC_MAX_FLOPPY 4
2421#define HFDC_MAX_HARD 4
2522
23#include "machine/mm58274c.h"
24#include "machine/hdc9234.h"
25
2626extern const device_type TI99_HFDC;
2727
28/*
29    Implementation for modern floppy system.
30*/
2831class myarc_hfdc_device : public ti_expansion_card_device
2932{
3033public:
3134   myarc_hfdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
35
3236   DECLARE_READ8Z_MEMBER(readz);
3337   DECLARE_WRITE8_MEMBER(write);
3438   DECLARE_READ8Z_MEMBER(crureadz);
3539   DECLARE_WRITE8_MEMBER(cruwrite);
3640
3741   DECLARE_WRITE_LINE_MEMBER( intrq_w );
42   DECLARE_WRITE_LINE_MEMBER( dip_w );
43   DECLARE_WRITE8_MEMBER( auxbus_out );
44   DECLARE_READ8_MEMBER( auxbus_in );
45   DECLARE_READ8_MEMBER( read_buffer );
46   DECLARE_WRITE8_MEMBER( write_buffer );
47
48private:
49   void device_start();
50   void device_reset();
51
52   const rom_entry *device_rom_region() const;
53   machine_config_constructor device_mconfig_additions() const;
54   ioport_constructor device_input_ports() const;
55
56   // Motor monoflop (4.23 sec)
57   emu_timer*      m_motor_on_timer;
58
59   // HDC9234 controller on the board
60   required_device<hdc9234_device> m_hdc9234;
61
62   // Clock chip on the board
63   required_device<mm58274c_device> m_clock;
64
65   // True: Access to DIP switch settings, false: access to line states
66   bool    m_see_switches;
67
68   // IRQ state
69   bool    m_irq;
70
71   // DMA in Progress state
72   bool    m_dip;
73
74   // When true, motor monoflop is high
75   bool    m_motor_running;
76
77   // Device Service Routine ROM (firmware)
78   UINT8*  m_dsrrom;
79
80   // ROM banks.
81   int     m_rom_page;
82
83   // HFDC on-board SRAM (32K)
84   UINT8*  m_buffer_ram;
85
86   // RAM page registers
87   int     m_ram_page[4];
88
89   // Output 1 latch
90   UINT8   m_output1_latch;
91
92   // Output 2 latch
93   UINT8   m_output2_latch;
94
95   // Clock divider bits 0 and 1. Unused in this emulation. */
96   int     m_CD;
97};
98
99// =========================================================================
100
101/*
102    Legacy implementation.
103*/
104extern const device_type TI99_HFDC_LEG;
105
106#include "machine/smc92x4.h"
107
108class myarc_hfdc_legacy_device : public ti_expansion_card_device
109{
110public:
111   myarc_hfdc_legacy_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
112   DECLARE_READ8Z_MEMBER(readz);
113   DECLARE_WRITE8_MEMBER(write);
114   DECLARE_READ8Z_MEMBER(crureadz);
115   DECLARE_WRITE8_MEMBER(cruwrite);
116
117   DECLARE_WRITE_LINE_MEMBER( intrq_w );
38118   DECLARE_WRITE_LINE_MEMBER( drq_w );
39119   DECLARE_WRITE_LINE_MEMBER( dip_w );
40120   DECLARE_READ8_MEMBER( auxbus_in );
trunk/src/emu/machine/machine.mak
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18481848
18491849#-------------------------------------------------
18501850#
1851#@src/emu/machine/hdc9234.h,MACHINES += HDC9234
1852#-------------------------------------------------
1853
1854ifneq ($(filter HDC9234,$(MACHINES)),)
1855MACHINEOBJS += $(MACHINEOBJ)/hdc9234.o
1856endif
1857
1858#-------------------------------------------------
1859#
18511860#@src/emu/machine/ti99_hd.h,MACHINES += TI99_HD
18521861#-------------------------------------------------
18531862
trunk/src/mess/mess.mak
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546546#MACHINES += SECFLASH
547547#MACHINES += PCCARD
548548MACHINES += SMC92X4
549MACHINES += HDC9234
549550MACHINES += TI99_HD
550551MACHINES += STRATA
551552MACHINES += CORVUSHD

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