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r29544 Friday 11th April, 2014 at 21:41:28 UTC by Nathan Woods
Merge branch 'master' of ssh://mess.org/mame into new_menus
[/branches/new_menus/src/emu/cpu/i386]x87ops.inc
[/branches/new_menus/src/emu/machine]74123.c 74148.c 74153.c 74181.c cdp1852.c er2055.c i8243.c i8251.c ins8154.c mc146818.c mc68681.c mc68901.c mos6551.c msm6242.c rtc9701.c s3520cf.c s3c2410.c smc91c9x.c timekpr.c upd4992.c v3021.c
[/branches/new_menus/src/emu/sound]c140.c c140.h c6280.c c6280.h cem3394.c cem3394.h k005289.c k007232.c k051649.c k053260.c k053260.h k054539.c namco.c namco.h nes_apu.c nes_apu.h okim6258.c okim6258.h rf5c68.c rf5c68.h segapcm.c segapcm.h vrender0.c vrender0.h x1_010.c x1_010.h
[/branches/new_menus/src/emu/video]crtc_ega.c dm9368.c epic12.c h63484.c huc6261.c huc6261.h m50458.c ramdac.c saa5050.c snes_ppu.c* snes_ppu.h* v9938.c video.mak
[/branches/new_menus/src/mame]mame.lst mame.mak
[/branches/new_menus/src/mame/audio]dkong.c
[/branches/new_menus/src/mame/drivers]20pacgal.c balsente.c baraduke.c battlera.c battlnts.c bladestl.c cham24.c champbwl.c chihiro.c cps1.c crystal.c ddz.c famibox.c gal3.c galaga.c gaplus.c ggconnie.c jrpacman.c mappy.c megaphx.c multigam.c namcona1.c namcos1.c namcos2.c namcos21.c namcos86.c nss.c overdriv.c pacland.c pacman.c paranoia.c pengo.c peplus.c playch10.c polepos.c psattack.c punchout.c rallyx.c rockrage.c segahang.c segaorun.c segaxbd.c segaybd.c seta.c seta2.c sfcbox.c skykid.c snesb.c tceptor.c tourvis.c toypop.c uapce.c vsnes.c
[/branches/new_menus/src/mame/includes]balsente.h battlnts.h bladestl.h namcona1.h rockrage.h snes.h
[/branches/new_menus/src/mame/machine]balsente.c snes.c
[/branches/new_menus/src/mame/video]cps1.c gp9001.c k037122.c k053250.c mcd212.c namcona1.c scn2674.c seta001.c snes.c tc0280grd.h
[/branches/new_menus/src/mess]mess.mak
[/branches/new_menus/src/mess/drivers]fmtowns.c nes.c pce.c pcfx.c pve500.c rainbow.c snes.c x1twin.c x68k.c
[/branches/new_menus/src/mess/includes]fmtowns.h
[/branches/new_menus/src/mess/machine]dec_lk201.c

branches/new_menus/src/emu/machine/ins8154.c
r29543r29544
4444//-------------------------------------------------
4545
4646ins8154_device::ins8154_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
47   : device_t(mconfig, INS8154, "INS8154", tag, owner, clock, "ins8154", __FILE__),
47   : device_t(mconfig, INS8154, "INS8154 RAM I/O", tag, owner, clock, "ins8154", __FILE__),
4848   m_in_a_cb(*this),
4949   m_out_a_cb(*this),
5050   m_in_b_cb(*this),
branches/new_menus/src/emu/machine/msm6242.c
r29543r29544
6464//-------------------------------------------------
6565
6666msm6242_device::msm6242_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
67   : device_t(mconfig, MSM6242, "msm6242", tag, owner, clock, "msm6242", __FILE__),
67   : device_t(mconfig, MSM6242, "MSM6242 RTC", tag, owner, clock, "msm6242", __FILE__),
6868      device_rtc_interface(mconfig, *this),
6969      m_out_int_handler(*this)
7070{
branches/new_menus/src/emu/machine/74153.c
r29543r29544
4040const device_type TTL74153 = &device_creator<ttl74153_device>;
4141
4242ttl74153_device::ttl74153_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
43   : device_t(mconfig, TTL74153, "TTL 74153", tag, owner, clock, "74153", __FILE__),
43   : device_t(mconfig, TTL74153, "74153 TTL", tag, owner, clock, "74153", __FILE__),
4444   m_a(0),
4545   m_b(0)
4646{
branches/new_menus/src/emu/machine/mc146818.c
r29543r29544
2929//-------------------------------------------------
3030
3131mc146818_device::mc146818_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
32   : device_t(mconfig, MC146818, "MC146818", tag, owner, clock, "mc146818", __FILE__),
32   : device_t(mconfig, MC146818, "MC146818 RTC", tag, owner, clock, "mc146818", __FILE__),
3333      device_nvram_interface(mconfig, *this),
3434      m_index(0),
3535      m_last_refresh(attotime::zero),
branches/new_menus/src/emu/machine/i8251.c
r29543r29544
2929//-------------------------------------------------
3030
3131i8251_device::i8251_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
32   : device_t(mconfig, I8251, "I8251", tag, owner, clock, "i8251", __FILE__),
32   : device_t(mconfig, I8251, "8251 USART", tag, owner, clock, "i8251", __FILE__),
3333   device_serial_interface(mconfig, *this),
3434   m_txd_handler(*this),
3535   m_dtr_handler(*this),
branches/new_menus/src/emu/machine/i8243.c
r29543r29544
2323//-------------------------------------------------
2424
2525i8243_device::i8243_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
26   : device_t(mconfig, I8243, "I8243", tag, owner, clock, "i8243", __FILE__),
26   : device_t(mconfig, I8243, "8243 I/O Expander", tag, owner, clock, "i8243", __FILE__),
2727      m_readhandler(*this),
2828      m_writehandler(*this)
2929{
branches/new_menus/src/emu/machine/smc91c9x.c
r29543r29544
184184const device_type SMC91C94 = &device_creator<smc91c94_device>;
185185
186186smc91c94_device::smc91c94_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
187   : smc91c9x_device(mconfig, SMC91C94, "SMC91C94", tag, owner, clock, "smc91c94", __FILE__)
187   : smc91c9x_device(mconfig, SMC91C94, "SMC91C94 Ethernet Controller", tag, owner, clock, "smc91c94", __FILE__)
188188{
189189}
190190
branches/new_menus/src/emu/machine/mos6551.c
r29543r29544
240240      m_tx_internal_clock = true;
241241
242242      m_divide = 16;
243      scale = (double) 1 / scale;
243
244      if (!m_dtr || m_rx_state != STATE_START)
245      {
246         scale = (double) 1 / scale;
247      }
248      else
249      {
250         scale = 0;
251      }
244252   }
245253   else
246254   {
r29543r29544
355363      m_tx_output = OUTPUT_MARK;
356364      output_txd(1);
357365   }
366
367   update_divider();
358368}
359369
360370READ8_MEMBER( mos6551_device::read )
r29543r29544
629639               }
630640
631641               m_rx_state = STATE_START;
642
643               if (m_dtr)
644               {
645                  update_divider();
646               }
632647            }
633648            break;
634649         }
branches/new_menus/src/emu/machine/upd4992.c
r29543r29544
3434//-------------------------------------------------
3535
3636upd4992_device::upd4992_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
37   : device_t(mconfig, UPD4992, "uPD4992", tag, owner, clock, "upd4992", __FILE__),
37   : device_t(mconfig, UPD4992, "uPD4992 RTC", tag, owner, clock, "upd4992", __FILE__),
3838      device_rtc_interface(mconfig, *this)
3939{
4040}
branches/new_menus/src/emu/machine/74181.c
r29543r29544
2525//-------------------------------------------------
2626
2727ttl74181_device::ttl74181_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
28   device_t(mconfig, TTL74181, "TTL 74181", tag, owner, clock, "ttl74181", __FILE__),
28   device_t(mconfig, TTL74181, "74181 TTL", tag, owner, clock, "ttl74181", __FILE__),
2929   m_a(0),
3030   m_b(0),
3131   m_s(0),
branches/new_menus/src/emu/machine/v3021.c
r29543r29544
3232//-------------------------------------------------
3333
3434v3021_device::v3021_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
35   : device_t(mconfig, v3021, "v3021", tag, owner, clock, "v3021", __FILE__)
35   : device_t(mconfig, v3021, "V3021 RTC", tag, owner, clock, "v3021", __FILE__)
3636{
3737}
3838
branches/new_menus/src/emu/machine/er2055.c
r29543r29544
3434//-------------------------------------------------
3535
3636er2055_device::er2055_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
37   : device_t(mconfig, ER2055, "ER2055", tag, owner, clock, "er2055", __FILE__),
37   : device_t(mconfig, ER2055, "ER2055 EAROM", tag, owner, clock, "er2055", __FILE__),
3838      device_memory_interface(mconfig, *this),
3939      device_nvram_interface(mconfig, *this),
4040      m_space_config("EAROM", ENDIANNESS_BIG, 8, 6, 0, *ADDRESS_MAP_NAME(er2055_map)),
branches/new_menus/src/emu/machine/rtc9701.c
r29543r29544
3333//-------------------------------------------------
3434
3535rtc9701_device::rtc9701_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
36   : device_t(mconfig, rtc9701, "rtc9701", tag, owner, clock, "rtc9701", __FILE__),
36   : device_t(mconfig, rtc9701, "RTC-9701", tag, owner, clock, "rtc9701", __FILE__),
3737      device_nvram_interface(mconfig, *this),
3838      m_latch(0),
3939      m_reset_line(CLEAR_LINE),
branches/new_menus/src/emu/machine/mc68681.c
r29543r29544
6363//**************************************************************************
6464
6565mc68681_device::mc68681_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
66   : device_t(mconfig, MC68681, "MC68681", tag, owner, clock, "mc68681", __FILE__),
66   : device_t(mconfig, MC68681, "MC68681 DUART", tag, owner, clock, "mc68681", __FILE__),
6767   m_chanA(*this, CHANA_TAG),
6868   m_chanB(*this, CHANB_TAG),
6969   write_irq(*this),
r29543r29544
615615// DUART channel class stuff
616616
617617mc68681_channel::mc68681_channel(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
618   : device_t(mconfig, MC68681_CHANNEL, "DUART 68681 channel", tag, owner, clock, "mc68681_channel", __FILE__),
618   : device_t(mconfig, MC68681_CHANNEL, "MC68681 DUART CHANNEL", tag, owner, clock, "mc68681_channel", __FILE__),
619619   device_serial_interface(mconfig, *this),
620620   MR1(0),
621621   MR2(0),
branches/new_menus/src/emu/machine/74123.c
r29543r29544
2727//-------------------------------------------------
2828
2929ttl74123_device::ttl74123_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
30   : device_t(mconfig, TTL74123, "TTL 74123", tag, owner, clock, "ttl74123", __FILE__)
30   : device_t(mconfig, TTL74123, "74123 TTL", tag, owner, clock, "ttl74123", __FILE__)
3131{
3232}
3333
branches/new_menus/src/emu/machine/s3520cf.c
r29543r29544
3636//-------------------------------------------------
3737
3838s3520cf_device::s3520cf_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
39   : device_t(mconfig, S3520CF, "s3520cf", tag, owner, clock, "s3520cf", __FILE__)
39   : device_t(mconfig, S3520CF, "S-3520CF RTC", tag, owner, clock, "s3520cf", __FILE__)
4040{
4141}
4242
branches/new_menus/src/emu/machine/74148.c
r29543r29544
4545const device_type TTL74148 = &device_creator<ttl74148_device>;
4646
4747ttl74148_device::ttl74148_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
48   : device_t(mconfig, TTL74148, "TTL 74148", tag, owner, clock, "74148", __FILE__),
48   : device_t(mconfig, TTL74148, "74148 TTL", tag, owner, clock, "74148", __FILE__),
4949   m_enable_input(0),
5050   m_output(0),
5151   m_output_valid(0),
branches/new_menus/src/emu/machine/s3c2410.c
r29543r29544
4040const device_type S3C2410 = &device_creator<s3c2410_device>;
4141
4242s3c2410_device::s3c2410_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
43      : device_t(mconfig, S3C2410, "Samsung S3C2410", tag, owner, clock, "s3c2410", __FILE__),
43      : device_t(mconfig, S3C2410, "S3C2410 MCU", tag, owner, clock, "s3c2410", __FILE__),
4444      m_palette(*this),
4545      m_cpu(*this, ":maincpu")
4646{
branches/new_menus/src/emu/machine/cdp1852.c
r29543r29544
4242//-------------------------------------------------
4343
4444cdp1852_device::cdp1852_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
45   device_t(mconfig, CDP1852, "CDP1852", tag, owner, clock, "cdp1852", __FILE__),
45   device_t(mconfig, CDP1852, "CDP1852 I/O", tag, owner, clock, "cdp1852", __FILE__),
4646   m_read_mode(*this),
4747   m_write_sr(*this),
4848   m_read_data(*this),
branches/new_menus/src/emu/machine/mc68901.c
r29543r29544
336336//-------------------------------------------------
337337
338338mc68901_device::mc68901_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
339   : device_t(mconfig, MC68901, "Motorola MC68901", tag, owner, clock, "mc68901", __FILE__),
339   : device_t(mconfig, MC68901, "MC68901 MFP", tag, owner, clock, "mc68901", __FILE__),
340340      device_serial_interface(mconfig, *this),
341341      m_timer_clock(0),
342342      m_rx_clock(0),
branches/new_menus/src/emu/machine/timekpr.c
r29543r29544
124124}
125125
126126m48t02_device::m48t02_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
127   : timekeeper_device(mconfig, M48T02, "M48T02", tag, owner, clock, "m48t02", __FILE__)
127   : timekeeper_device(mconfig, M48T02, "M48T02 TIMEKEEPER", tag, owner, clock, "m48t02", __FILE__)
128128{
129129   m_offset_control = 0x7f8;
130130   m_offset_seconds = 0x7f9;
r29543r29544
140140}
141141
142142m48t35_device::m48t35_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
143   : timekeeper_device(mconfig, M48T35, "M48T35", tag, owner, clock, "m48t35", __FILE__)
143   : timekeeper_device(mconfig, M48T35, "M48T35 TIMEKEEPER", tag, owner, clock, "m48t35", __FILE__)
144144{
145145   m_offset_control = 0x7ff8;
146146   m_offset_seconds = 0x7ff9;
r29543r29544
156156}
157157
158158m48t37_device::m48t37_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
159   : timekeeper_device(mconfig, M48T37, "M48T37", tag, owner, clock, "m48t37", __FILE__)
159   : timekeeper_device(mconfig, M48T37, "M48T37 TIMEKEEPER", tag, owner, clock, "m48t37", __FILE__)
160160{
161161   m_offset_control = 0x7ff8;
162162   m_offset_seconds = 0x7ff9;
r29543r29544
172172}
173173
174174m48t58_device::m48t58_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
175   : timekeeper_device(mconfig, M48T58, "M48T58", tag, owner, clock, "m48t58", __FILE__)
175   : timekeeper_device(mconfig, M48T58, "M48T58 TIMEKEEPER", tag, owner, clock, "m48t58", __FILE__)
176176{
177177   m_offset_control = 0x1ff8;
178178   m_offset_seconds = 0x1ff9;
r29543r29544
188188}
189189
190190mk48t08_device::mk48t08_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
191   : timekeeper_device(mconfig, MK48T08, "MK48T08", tag, owner, clock, "m48t08", __FILE__)
191   : timekeeper_device(mconfig, MK48T08, "MK48T08 TIMEKEEPER", tag, owner, clock, "m48t08", __FILE__)
192192{
193193   m_offset_control = 0x1ff8;
194194   m_offset_seconds = 0x1ff9;
branches/new_menus/src/emu/cpu/i386/x87ops.inc
r29543r29544
19761976      floatx80 a = ST(0);
19771977      floatx80 b = ST(1);
19781978
1979      m_x87_sw &= ~X87_SW_C0;
1979      m_x87_sw &= ~X87_SW_C2;
19801980
19811981      // TODO: Implement Cx bits
19821982      result = floatx80_rem(a, b);
r29543r29544
20022002      floatx80 a = ST(0);
20032003      floatx80 b = ST(1);
20042004
2005      m_x87_sw &= ~X87_SW_C0;
2005      m_x87_sw &= ~X87_SW_C2;
20062006
20072007      // TODO: Implement Cx bits
20082008      result = floatx80_rem(a, b);
branches/new_menus/src/emu/video/h63484.c
r29543r29544
2929//-------------------------------------------------
3030
3131h63484_device::h63484_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
32   : device_t(mconfig, H63484, "H63484", tag, owner, clock, "h63484", __FILE__),
32   : device_t(mconfig, H63484, "HD63484 CRTC (rewrite)", tag, owner, clock, "h63484", __FILE__),
3333   device_memory_interface(mconfig, *this),
3434   device_video_interface(mconfig, *this),
3535   m_ar(0),
branches/new_menus/src/emu/video/v9938.c
r29543r29544
9999}
100100
101101v9938_device::v9938_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
102: v99x8_device(mconfig, V9938, "V9938", "v9938", tag, owner, clock)
102: v99x8_device(mconfig, V9938, "V9938 VDP", "v9938", tag, owner, clock)
103103{
104104   m_model = MODEL_V9938;
105105}
branches/new_menus/src/emu/video/huc6261.c
r29543r29544
2323const device_type HUC6261 = &device_creator<huc6261_device>;
2424
2525
26void huc6261_device::device_config_complete()
27{
28   const huc6261_interface *intf = reinterpret_cast<const huc6261_interface *>(static_config());
29
30   if ( intf != NULL )
31   {
32      *static_cast<huc6261_interface *>(this) = *intf;
33   }
34   else
35   {
36   }
37}
38
39
4026huc6261_device::huc6261_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
4127   :   device_t(mconfig, HUC6261, "HuC6261", tag, owner, clock, "huc6261", __FILE__),
4228      device_video_interface(mconfig, *this)
r29543r29544
403389void huc6261_device::device_start()
404390{
405391   /* Make sure we are supplied all our mandatory tags */
406   assert( huc6270_a_tag != NULL );
407   assert( huc6270_b_tag != NULL );
392   assert( m_huc6270_a_tag != NULL );
393   assert( m_huc6270_b_tag != NULL );
408394
409395   m_timer = timer_alloc();
410   m_huc6270_a = machine().device<huc6270_device>( huc6270_a_tag );
411   m_huc6270_b = machine().device<huc6270_device>( huc6270_b_tag );
396   m_huc6270_a = machine().device<huc6270_device>(m_huc6270_a_tag);
397   m_huc6270_b = machine().device<huc6270_device>(m_huc6270_b_tag);
412398
413399   m_bmp = auto_bitmap_rgb32_alloc( machine(), HUC6261_WPF, HUC6261_LPF );
414400
branches/new_menus/src/emu/video/huc6261.h
r29543r29544
1717#define HUC6261_LPF         263     /* max number of lines in a single frame */
1818
1919
20#define MCFG_HUC6261_ADD( _tag, clock, _intrf ) \
21   MCFG_DEVICE_ADD( _tag, HUC6261, clock )     \
22   MCFG_DEVICE_CONFIG( _intrf )
20#define MCFG_HUC6261_VDC1(_tag) \
21   huc6261_device::set_vdc1_tag(*device, _tag);
2322
23#define MCFG_HUC6261_VDC2(_tag) \
24   huc6261_device::set_vdc2_tag(*device, _tag);
2425
25struct huc6261_interface
26{
27   /* Tags for the 2 HuC6270 devices */
28   const char *huc6270_a_tag;
29   const char *huc6270_b_tag;
30};
3126
32
3327class huc6261_device :  public device_t,
34                  public device_video_interface,
35                  public huc6261_interface
28                  public device_video_interface
3629{
3730public:
3831   // construction/destruction
3932   huc6261_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
4033
34   static void set_vdc1_tag(device_t &device, const char *tag) { downcast<huc6261_device &>(device).m_huc6270_a_tag = tag; }
35   static void set_vdc2_tag(device_t &device, const char *tag) { downcast<huc6261_device &>(device).m_huc6270_b_tag = tag; }
36
4137   void video_update(bitmap_rgb32 &bitmap, const rectangle &cliprect);
4238   DECLARE_READ16_MEMBER( read );
4339   DECLARE_WRITE16_MEMBER( write );
r29543r29544
4642
4743protected:
4844   // device-level overrides
49   virtual void device_config_complete();
5045   virtual void device_start();
5146   virtual void device_reset();
5247   virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
5348
5449private:
50   const char *m_huc6270_a_tag;
51   const char *m_huc6270_b_tag;
52
5553   huc6270_device *m_huc6270_a;
5654   huc6270_device *m_huc6270_b;
5755   int     m_last_h;
branches/new_menus/src/emu/video/ramdac.c
r29543r29544
4040//-------------------------------------------------
4141
4242ramdac_device::ramdac_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
43   : device_t(mconfig, RAMDAC, "ramdac", tag, owner, clock, "ramdac", __FILE__),
43   : device_t(mconfig, RAMDAC, "RAMDAC", tag, owner, clock, "ramdac", __FILE__),
4444      device_memory_interface(mconfig, *this),
4545      m_space_config("videoram", ENDIANNESS_LITTLE, 8, 10, 0, NULL, *ADDRESS_MAP_NAME(ramdac_palram)),
4646      m_palette(*this),
branches/new_menus/src/emu/video/dm9368.c
r29543r29544
4444//-------------------------------------------------
4545
4646dm9368_device::dm9368_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
47   device_t(mconfig, DM9368, "DM9368", tag, owner, clock, "dm9368", __FILE__),
47   device_t(mconfig, DM9368, "DM9368 7-Segment Decoder", tag, owner, clock, "dm9368", __FILE__),
4848   device_output_interface(mconfig, *this),
4949   m_write_rbo(*this),
5050   m_rbi(1),
branches/new_menus/src/emu/video/snes_ppu.c
r0r29544
1/***************************************************************************
2
3  snes.c
4
5  Video file to handle emulation of the Nintendo Super NES.
6
7  Anthony Kruize
8  Based on the original code by Lee Hammerton (aka Savoury Snax)
9
10  Some notes on the snes video hardware:
11
12  Object Attribute Memory(OAM) is made up of 128 blocks of 32 bits, followed
13  by 128 blocks of 2 bits. The format for each block is:
14  -First Block----------------------------------------------------------------
15  | x pos  | y pos  |char no.| v flip | h flip |priority|palette |char no msb|
16  +--------+--------+--------+--------+--------+--------+--------+-----------+
17  | 8 bits | 8 bits | 8 bits | 1 bit  | 1 bit  | 2 bits | 3 bits | 1 bit     |
18  -Second Block---------------------------------------------------------------
19  | size  | x pos msb |
20  +-------+-----------+
21  | 1 bit | 1 bit     |
22  ---------------------
23
24  Video RAM contains information for character data and screen maps.
25  Screen maps are made up of 32 x 32 blocks of 16 bits each.
26  The format for each block is:
27  ----------------------------------------------
28  | v flip | x flip |priority|palette |char no.|
29  +--------+--------+--------+--------+--------+
30  | 1 bit  | 1 bit  | 1 bit  | 3 bits |10 bits |
31  ----------------------------------------------
32  Mode 7 is stored differently. Character data and screen map are interleaved.
33  There are two formats:
34  -Normal-----------------  -EXTBG-----------------------------
35  | char data | char no. |  | priority | char data | char no. |
36  +-----------+----------+  +----------+-----------+----------+
37  | 8 bits    | 8 bits   |  | 1 bit    | 7 bits    | 8 bits   |
38  ------------------------  -----------------------------------
39
40  The screen layers are drawn with the following priorities (updated info courtesy of byuu):
41
42  |           |   1   |   2   |   3   |   4   |   5   |   6   |   7   |   8   |   9   |  10   |  11   |  12   |
43  -------------------------------------------------------------------------------------------------------------
44  | Mode 0    |  BG4B |  BG3B |  OAM0 |  BG4A |  BG3A |  OAM1 |  BG2B |  BG1B |  OAM2 |  BG2A |  BG1A |  OAM3 |
45  -------------------------------------------------------------------------------------------------------------
46  | Mode 1 (*)|  BG3B |  OAM0 |  OAM1 |  BG2B |  BG1B |  OAM2 |  BG2A |  BG1A |  OAM3 |  BG3A |       |       |
47  -------------------------------------------------------------------------------------------------------------
48  | Mode 1 (!)|  BG3B |  OAM0 |  BG3A |  OAM1 |  BG2B |  BG1B |  OAM2 |  BG2A |  BG1A |  OAM3 |       |       |
49  -------------------------------------------------------------------------------------------------------------
50  | Mode 2    |  BG2B |  OAM0 |  BG1B |  OAM1 |  BG2A |  OAM2 |  BG1A |  OAM3 |       |       |       |       |
51  -------------------------------------------------------------------------------------------------------------
52  | Mode 3    |  BG2B |  OAM0 |  BG1B |  OAM1 |  BG2A |  OAM2 |  BG1A |  OAM3 |       |       |       |       |
53  -------------------------------------------------------------------------------------------------------------
54  | Mode 4    |  BG2B |  OAM0 |  BG1B |  OAM1 |  BG2A |  OAM2 |  BG1A |  OAM3 |       |       |       |       |
55  -------------------------------------------------------------------------------------------------------------
56  | Mode 5    |  BG2B |  OAM0 |  BG1B |  OAM1 |  BG2A |  OAM2 |  BG1A |  OAM3 |       |       |       |       |
57  -------------------------------------------------------------------------------------------------------------
58  | Mode 6    |  OAM0 |  BG1B |  OAM1 |  OAM2 |  BG1A |  OAM3 |       |       |       |       |       |       |
59  -------------------------------------------------------------------------------------------------------------
60  | Mode 7 (+)|  OAM0 |  BG1n |  OAM1 |  OAM2 |  OAM3 |       |       |       |       |       |       |       |
61  -------------------------------------------------------------------------------------------------------------
62  | Mode 7 (-)|  BG2B |  OAM0 |  BG1n |  OAM1 |  BG2A |  OAM2 |  OAM3 |       |       |       |       |       |
63  -------------------------------------------------------------------------------------------------------------
64
65  Where:
66   - Mode 1 (*) is Mode 1 with bg3_pty = 1
67   - Mode 1 (!) is Mode 1 with bg3_pty = 0
68   - Mode 7 (+) is base Mode 7
69   - Mode 7 (-) is Mode 7 EXTBG
70
71***************************************************************************/
72
73#include "emu.h"
74#include "video/snes_ppu.h"
75
76#define SNES_MAINSCREEN    0
77#define SNES_SUBSCREEN     1
78#define SNES_CLIP_NEVER    0
79#define SNES_CLIP_IN       1
80#define SNES_CLIP_OUT      2
81#define SNES_CLIP_ALWAYS   3
82
83#define SNES_VRAM_SIZE        0x20000   /* 128kb of video ram */
84#define SNES_CGRAM_SIZE       0x202     /* 256 16-bit colours + 1 tacked on 16-bit colour for fixed colour */
85#define SNES_OAM_SIZE         0x440     /* 1088 bytes of Object Attribute Memory */
86#define FIXED_COLOUR          256       /* Position in cgram for fixed colour */
87
88
89/* Definitions for PPU Memory-Mapped registers */
90#define INIDISP        0x2100
91#define OBSEL          0x2101
92#define OAMADDL        0x2102
93#define OAMADDH        0x2103
94#define OAMDATA        0x2104
95#define BGMODE         0x2105   /* abcdefff = abcd: bg4-1 tile size | e: BG3 high priority | f: mode */
96#define MOSAIC         0x2106   /* xxxxabcd = x: pixel size | abcd: affects bg 1-4 */
97#define BG1SC          0x2107
98#define BG2SC          0x2108
99#define BG3SC          0x2109
100#define BG4SC          0x210A
101#define BG12NBA        0x210B
102#define BG34NBA        0x210C
103#define BG1HOFS        0x210D
104#define BG1VOFS        0x210E
105#define BG2HOFS        0x210F
106#define BG2VOFS        0x2110
107#define BG3HOFS        0x2111
108#define BG3VOFS        0x2112
109#define BG4HOFS        0x2113
110#define BG4VOFS        0x2114
111#define VMAIN          0x2115   /* i---ffrr = i: Increment timing | f: Full graphic | r: increment rate */
112#define VMADDL         0x2116   /* aaaaaaaa = a: LSB of vram address */
113#define VMADDH         0x2117   /* aaaaaaaa = a: MSB of vram address */
114#define VMDATAL        0x2118   /* dddddddd = d: data to be written */
115#define VMDATAH        0x2119   /* dddddddd = d: data to be written */
116#define M7SEL          0x211A   /* ab----yx = a: screen over | y: vertical flip | x: horizontal flip */
117#define M7A            0x211B   /* aaaaaaaa = a: COSINE rotate angle / X expansion */
118#define M7B            0x211C   /* aaaaaaaa = a: SINE rotate angle / X expansion */
119#define M7C            0x211D   /* aaaaaaaa = a: SINE rotate angle / Y expansion */
120#define M7D            0x211E   /* aaaaaaaa = a: COSINE rotate angle / Y expansion */
121#define M7X            0x211F
122#define M7Y            0x2120
123#define CGADD          0x2121
124#define CGDATA         0x2122
125#define W12SEL         0x2123
126#define W34SEL         0x2124
127#define WOBJSEL        0x2125
128#define WH0            0x2126   /* pppppppp = p: Left position of window 1 */
129#define WH1            0x2127   /* pppppppp = p: Right position of window 1 */
130#define WH2            0x2128   /* pppppppp = p: Left position of window 2 */
131#define WH3            0x2129   /* pppppppp = p: Right position of window 2 */
132#define WBGLOG         0x212A   /* aabbccdd = a: BG4 params | b: BG3 params | c: BG2 params | d: BG1 params */
133#define WOBJLOG        0x212B   /* ----ccoo = c: Colour window params | o: Object window params */
134#define TM             0x212C
135#define TS             0x212D
136#define TMW            0x212E
137#define TSW            0x212F
138#define CGWSEL         0x2130
139#define CGADSUB        0x2131
140#define COLDATA        0x2132
141#define SETINI         0x2133
142#define MPYL           0x2134
143#define MPYM           0x2135
144#define MPYH           0x2136
145#define SLHV           0x2137
146#define ROAMDATA       0x2138
147#define RVMDATAL       0x2139
148#define RVMDATAH       0x213A
149#define RCGDATA        0x213B
150#define OPHCT          0x213C
151#define OPVCT          0x213D
152#define STAT77         0x213E
153#define STAT78         0x213F
154
155
156#if SNES_LAYER_DEBUG
157/*                                    red   green  blue    purple  yellow cyan    grey    white */
158static const UINT16 dbg_mode_colours[8] = { 0x1f, 0x3e0, 0x7c00, 0x7c1f, 0x3ff, 0x7fe0, 0x4210, 0x7fff };
159#endif /* SNES_LAYER_DEBUG */
160
161static const UINT16 table_obj_offset[8][8] =
162{
163   { (0*32),   (0*32)+32,   (0*32)+64,   (0*32)+96,   (0*32)+128,   (0*32)+160,   (0*32)+192,   (0*32)+224 },
164   { (16*32),  (16*32)+32,  (16*32)+64,  (16*32)+96,  (16*32)+128,  (16*32)+160,  (16*32)+192,  (16*32)+224 },
165   { (32*32),  (32*32)+32,  (32*32)+64,  (32*32)+96,  (32*32)+128,  (32*32)+160,  (32*32)+192,  (32*32)+224 },
166   { (48*32),  (48*32)+32,  (48*32)+64,  (48*32)+96,  (48*32)+128,  (48*32)+160,  (48*32)+192,  (48*32)+224 },
167   { (64*32),  (64*32)+32,  (64*32)+64,  (64*32)+96,  (64*32)+128,  (64*32)+160,  (64*32)+192,  (64*32)+224 },
168   { (80*32),  (80*32)+32,  (80*32)+64,  (80*32)+96,  (80*32)+128,  (80*32)+160,  (80*32)+192,  (80*32)+224 },
169   { (96*32),  (96*32)+32,  (96*32)+64,  (96*32)+96,  (96*32)+128,  (96*32)+160,  (96*32)+192,  (96*32)+224 },
170   { (112*32), (112*32)+32, (112*32)+64, (112*32)+96, (112*32)+128, (112*32)+160, (112*32)+192, (112*32)+224 }
171};
172
173
174enum
175{
176   SNES_COLOR_DEPTH_2BPP = 0,
177   SNES_COLOR_DEPTH_4BPP,
178   SNES_COLOR_DEPTH_8BPP
179};
180
181
182#define PPU_REG(a) m_regs[a - 0x2100]
183
184
185
186//**************************************************************************
187//  DEVICE DEFINITIONS
188//**************************************************************************
189
190const device_type SNES_PPU = &device_creator<snes_ppu_device>;
191
192
193//**************************************************************************
194//  live device
195//**************************************************************************
196
197//-------------------------------------------------
198//  snes_ppu_device - constructor
199//-------------------------------------------------
200
201snes_ppu_device::snes_ppu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
202            : device_t(mconfig, SNES_PPU, "SNES PPU", tag, owner, clock, "snes_ppu", __FILE__),
203               device_video_interface(mconfig, *this),
204               m_openbus_cb(*this)
205{
206}
207
208
209//-------------------------------------------------
210//  device_start - device-specific startup
211//-------------------------------------------------
212
213void snes_ppu_device::device_start()
214{
215   m_openbus_cb.resolve_safe(0);
216
217#if SNES_LAYER_DEBUG
218   memset(&m_debug_options, 0, sizeof(m_debug_options));
219#endif
220   
221   m_vram = auto_alloc_array(machine(), UINT8, SNES_VRAM_SIZE);
222   m_cgram = auto_alloc_array(machine(), UINT16, SNES_CGRAM_SIZE/2);
223   m_oam_ram = auto_alloc_array(machine(), UINT16, SNES_OAM_SIZE/2);
224   
225   /* Inititialize registers/variables */
226   m_update_windows = 1;
227   m_beam.latch_vert = 0;
228   m_beam.latch_horz = 0;
229   m_beam.current_vert = 0;
230   m_beam.current_horz = 0;
231   m_beam.last_visible_line = 225; /* TODO: PAL setting */
232   m_mode = 0;
233   m_ppu1_version = 1;  // 5C77 chip version number, read by STAT77, only '1' is known
234   m_ppu2_version = 3;  // 5C78 chip version number, read by STAT78, only '2' & '3' encountered so far.
235   
236   m_cgram_address = 0;
237   m_read_ophct = 0;
238   m_read_opvct = 0;
239   
240   PPU_REG(VMAIN) = 0x80;
241   // what about other regs?
242   
243   /* Inititialize mosaic table */
244   for (int j = 0; j < 16; j++)
245   {
246      for (int i = 0; i < 4096; i++)
247         m_mosaic_table[j][i] = (i / (j + 1)) * (j + 1);
248   }
249   
250   /* Init VRAM */
251   memset(m_vram, 0, SNES_VRAM_SIZE);
252   
253   /* Init Palette RAM */
254   memset((UINT8 *)m_cgram, 0, SNES_CGRAM_SIZE);
255   
256   /* Init oam RAM */
257   memset((UINT8 *)m_oam_ram, 0xff, SNES_OAM_SIZE);
258
259   for (int i = 0; i < 2; i++)
260   {
261      save_item(NAME(m_scanlines[i].enable), i);
262      save_item(NAME(m_scanlines[i].clip), i);
263      save_item(NAME(m_scanlines[i].buffer), i);
264      save_item(NAME(m_scanlines[i].priority), i);
265      save_item(NAME(m_scanlines[i].layer), i);
266      save_item(NAME(m_scanlines[i].blend_exception), i);
267   }
268   
269   for (int i = 0; i < 6; i++)
270   {
271      save_item(NAME(m_layer[i].window1_enabled), i);
272      save_item(NAME(m_layer[i].window1_invert), i);
273      save_item(NAME(m_layer[i].window2_enabled), i);
274      save_item(NAME(m_layer[i].window2_invert), i);
275      save_item(NAME(m_layer[i].wlog_mask), i);
276      save_item(NAME(m_layer[i].color_math), i);
277      save_item(NAME(m_layer[i].charmap), i);
278      save_item(NAME(m_layer[i].tilemap), i);
279      save_item(NAME(m_layer[i].tilemap_size), i);
280      save_item(NAME(m_layer[i].tile_size), i);
281      save_item(NAME(m_layer[i].mosaic_enabled), i);
282      save_item(NAME(m_layer[i].main_window_enabled), i);
283      save_item(NAME(m_layer[i].sub_window_enabled), i);
284      save_item(NAME(m_layer[i].main_bg_enabled), i);
285      save_item(NAME(m_layer[i].sub_bg_enabled), i);
286      save_item(NAME(m_layer[i].hoffs), i);
287      save_item(NAME(m_layer[i].voffs), i);
288     
289      save_item(NAME(m_clipmasks[i]), i);
290   }
291   
292   save_item(NAME(m_oam.address_low));
293   save_item(NAME(m_oam.address_high));
294   save_item(NAME(m_oam.saved_address_low));
295   save_item(NAME(m_oam.saved_address_high));
296   save_item(NAME(m_oam.address));
297   save_item(NAME(m_oam.priority_rotation));
298   save_item(NAME(m_oam.next_charmap));
299   save_item(NAME(m_oam.next_size));
300   save_item(NAME(m_oam.size));
301   save_item(NAME(m_oam.next_name_select));
302   save_item(NAME(m_oam.name_select));
303   save_item(NAME(m_oam.first_sprite));
304   save_item(NAME(m_oam.flip));
305   save_item(NAME(m_oam.write_latch));
306   
307   save_item(NAME(m_beam.latch_horz));
308   save_item(NAME(m_beam.latch_vert));
309   save_item(NAME(m_beam.current_horz));
310   save_item(NAME(m_beam.current_vert));
311   save_item(NAME(m_beam.last_visible_line));
312   save_item(NAME(m_beam.interlace_count));
313   
314   save_item(NAME(m_mode7.repeat));
315   save_item(NAME(m_mode7.hflip));
316   save_item(NAME(m_mode7.vflip));
317   save_item(NAME(m_mode7.matrix_a));
318   save_item(NAME(m_mode7.matrix_b));
319   save_item(NAME(m_mode7.matrix_c));
320   save_item(NAME(m_mode7.matrix_d));
321   save_item(NAME(m_mode7.origin_x));
322   save_item(NAME(m_mode7.origin_y));
323   save_item(NAME(m_mode7.hor_offset));
324   save_item(NAME(m_mode7.ver_offset));
325   save_item(NAME(m_mode7.extbg));
326   
327   save_item(NAME(m_mosaic_size));
328   save_item(NAME(m_clip_to_black));
329   save_item(NAME(m_prevent_color_math));
330   save_item(NAME(m_sub_add_mode));
331   save_item(NAME(m_bg3_priority_bit));
332   save_item(NAME(m_direct_color));
333   save_item(NAME(m_ppu_last_scroll));
334   save_item(NAME(m_mode7_last_scroll));
335   
336   save_item(NAME(m_ppu1_open_bus));
337   save_item(NAME(m_ppu2_open_bus));
338   save_item(NAME(m_ppu1_version));
339   save_item(NAME(m_ppu2_version));
340   save_item(NAME(m_window1_left));
341   save_item(NAME(m_window1_right));
342   save_item(NAME(m_window2_left));
343   save_item(NAME(m_window2_right));
344   
345   save_item(NAME(m_update_windows));
346   save_item(NAME(m_update_offsets));
347   save_item(NAME(m_update_oam_list));
348   save_item(NAME(m_mode));
349   save_item(NAME(m_interlace));
350   save_item(NAME(m_obj_interlace));
351   save_item(NAME(m_screen_brightness));
352   save_item(NAME(m_screen_disabled));
353   save_item(NAME(m_pseudo_hires));
354   save_item(NAME(m_color_modes));
355   save_item(NAME(m_stat77));
356   save_item(NAME(m_stat78));
357   
358   save_item(NAME(m_htmult));
359   save_item(NAME(m_cgram_address));
360   save_item(NAME(m_read_ophct));
361   save_item(NAME(m_read_opvct));
362   save_item(NAME(m_vram_fgr_high));
363   save_item(NAME(m_vram_fgr_increment));
364   save_item(NAME(m_vram_fgr_count));
365   save_item(NAME(m_vram_fgr_mask));
366   save_item(NAME(m_vram_fgr_shift));
367   save_item(NAME(m_vram_read_buffer));
368   save_item(NAME(m_vmadd));
369   
370   save_item(NAME(m_regs));
371   
372   save_pointer(NAME(m_vram), SNES_VRAM_SIZE);
373   save_pointer(NAME(m_cgram), SNES_CGRAM_SIZE/2);
374   save_pointer(NAME(m_oam_ram), SNES_OAM_SIZE/2);
375}
376
377
378
379/*****************************************
380 * get_bgcolor()
381 *
382 * Get the proper color (direct or from cgram)
383 *****************************************/
384
385inline UINT16 snes_ppu_device::get_bgcolor( UINT8 direct_colors, UINT16 palette, UINT8 color )
386{
387   UINT16 c = 0;
388
389   if (direct_colors)
390   {
391      /* format is  0 | BBb00 | GGGg0 | RRRr0, HW confirms that the data is zero padded. */
392      c = ((color & 0x07) << 2) | ((color & 0x38) << 4) | ((color & 0xc0) << 7);
393      c |= ((palette & 0x04) >> 1) | ((palette & 0x08) << 3) | ((palette & 0x10) << 8);
394   }
395   else
396      c = m_cgram[(palette + color) % FIXED_COLOUR];
397
398   return c;
399}
400
401/*****************************************
402 * set_scanline_pixel()
403 *
404 * Store pixel color, priority, layer and
405 * color math exception (for OAM) in the
406 * proper scanline
407 *****************************************/
408
409inline void snes_ppu_device::set_scanline_pixel( int screen, INT16 x, UINT16 color, UINT8 priority, UINT8 layer, int blend )
410{
411   m_scanlines[screen].buffer[x] = color;
412   m_scanlines[screen].priority[x] = priority;
413   m_scanlines[screen].layer[x] = layer;
414   m_scanlines[screen].blend_exception[x] = blend;
415}
416
417/*************************************************************************************************
418 * SNES tiles
419 *
420 * The way vram is accessed to draw tiles is basically the same for both BG and OAM tiles. Main
421 * differences are bit planes (variable for BG and fixed for OAM) and a few details of the scanline
422 * output (since OAM has neither mosaic, nor hires, nor direct colors).
423 * Hence, we use a common function to take data from VRAM and then we call specific routines for
424 * OAM vs BG vs Hi-Res BG tiles.
425 *************************************************************************************************/
426
427/*****************************************
428 * draw_bgtile_lores()
429 * draw_bgtile_hires()
430 * draw_oamtile_()
431 *
432 * Check if a pixel is clipped or not, and
433 * copy it to the scanline buffer when
434 * appropriate. The actual way to perform
435 * such operations depends on the source
436 * (BG or OAM) and on the resolution (hires
437 * or lores)
438 *****************************************/
439
440inline void snes_ppu_device::draw_bgtile_lores( UINT8 layer, INT16 ii, UINT8 colour, UINT16 pal, UINT8 direct_colors, UINT8 priority )
441{
442   int screen;
443   UINT16 c;
444
445   for (screen = SNES_MAINSCREEN; screen <= SNES_SUBSCREEN; screen++)
446   {
447      if (ii >= 0 && ii < SNES_SCR_WIDTH && m_scanlines[screen].enable)
448      {
449         if (m_scanlines[screen].priority[ii] <= priority)
450         {
451            UINT8 clr = colour;
452            UINT8 clipmask = m_clipmasks[layer][ii];
453
454#if SNES_LAYER_DEBUG
455            if (m_debug_options.windows_disabled)
456               clipmask = 0xff;
457#endif /* SNES_LAYER_DEBUG */
458
459            /* Clip to windows */
460            if (m_scanlines[screen].clip)
461               clr &= clipmask;
462
463            /* Only draw if we have a colour (0 == transparent) */
464            if (clr)
465            {
466               c = get_bgcolor(direct_colors, pal, clr);
467               set_scanline_pixel(screen, ii, c, priority, layer, 0);
468            }
469         }
470      }
471   }
472}
473
474inline void snes_ppu_device::draw_bgtile_hires( UINT8 layer, INT16 ii, UINT8 colour, UINT16 pal, UINT8 direct_colors, UINT8 priority )
475{
476   int screen;
477   UINT16 c;
478
479   for (screen = SNES_MAINSCREEN; screen <= SNES_SUBSCREEN; screen++)
480   {
481      // odd pixels to main screen, even pixels to sub screen
482      if (ii >= 0 && ii < (SNES_SCR_WIDTH << 1) && ((ii & 1) ^ screen) && m_scanlines[screen].enable)
483      {
484         if (m_scanlines[screen].priority[ii >> 1] <= priority)
485         {
486            UINT8 clr = colour;
487            UINT8 clipmask = m_clipmasks[layer][ii >> 1];
488
489#if SNES_LAYER_DEBUG
490            if (m_debug_options.windows_disabled)
491               clipmask = 0xff;
492#endif /* SNES_LAYER_DEBUG */
493
494            /* Clip to windows */
495            if (m_scanlines[screen].clip)
496               clr &= clipmask;
497
498            /* Only draw if we have a colour (0 == transparent) */
499            if (clr)
500            {
501               c = get_bgcolor(direct_colors, pal, clr);
502               set_scanline_pixel(screen, ii >> 1, c, priority, layer, 0);
503            }
504         }
505      }
506   }
507}
508
509inline void snes_ppu_device::draw_oamtile( INT16 ii, UINT8 colour, UINT16 pal, UINT8 priority )
510{
511   int screen;
512   int blend;
513   UINT16 c;
514   INT16 pos = ii & 0x1ff;
515
516   for (screen = SNES_MAINSCREEN; screen <= SNES_SUBSCREEN; screen++)
517   {
518      if (pos >= 0 && pos < SNES_SCR_WIDTH && m_scanlines[screen].enable)
519      {
520         UINT8 clr = colour;
521         UINT8 clipmask = m_clipmasks[SNES_OAM][pos];
522
523#if SNES_LAYER_DEBUG
524         if (m_debug_options.windows_disabled)
525            clipmask = 0xff;
526#endif /* SNES_LAYER_DEBUG */
527
528         /* Clip to windows */
529         if (m_scanlines[screen].clip)
530            clr &= clipmask;
531
532         /* Only draw if we have a colour (0 == transparent) */
533         if (clr)
534         {
535            c = m_cgram[(pal + clr) % FIXED_COLOUR];
536            blend = (pal + clr < 192) ? 1 : 0;
537            set_scanline_pixel(screen, pos, c, priority, SNES_OAM, blend);
538         }
539      }
540   }
541}
542
543/*****************************************
544 * draw_tile()
545 *
546 * Draw 8 pixels from the expected tile
547 * by reading the color planes from vram
548 * and by calling the appropriate routine
549 * (depending on layer and resolution)
550 *****************************************/
551
552inline void snes_ppu_device::draw_tile( UINT8 planes, UINT8 layer, UINT32 tileaddr, INT16 x, UINT8 priority, UINT8 flip, UINT8 direct_colors, UINT16 pal, UINT8 hires )
553{
554   UINT8 plane[8];
555   INT16 ii, jj;
556   int x_mos;
557
558   for (ii = 0; ii < planes / 2; ii++)
559   {
560      plane[2 * ii + 0] = m_vram[(tileaddr + 16 * ii + 0) % SNES_VRAM_SIZE];
561      plane[2 * ii + 1] = m_vram[(tileaddr + 16 * ii + 1) % SNES_VRAM_SIZE];
562   }
563
564   for (ii = x; ii < (x + 8); ii++)
565   {
566      UINT8 colour = 0;
567      UINT8 mosaic = m_layer[layer].mosaic_enabled;
568
569#if SNES_LAYER_DEBUG
570      if (m_debug_options.mosaic_disabled)
571         mosaic = 0;
572#endif /* SNES_LAYER_DEBUG */
573
574      if (flip)
575      {
576         for (jj = 0; jj < planes; jj++)
577            colour |= BIT(plane[jj], ii - x) ? (1 << jj) : 0;
578      }
579      else
580      {
581         for (jj = 0; jj < planes; jj++)
582            colour |= BIT(plane[jj], 7 - (ii - x)) ? (1 << jj) : 0;
583      }
584
585      if (layer == SNES_OAM)
586         draw_oamtile(ii, colour, pal, priority);
587      else if (!hires)
588      {
589         if (mosaic)
590         {
591            for (x_mos = 0; x_mos < (m_mosaic_size + 1); x_mos++)
592               draw_bgtile_lores(layer, ii + x_mos, colour, pal, direct_colors, priority);
593            ii += x_mos - 1;
594         }
595         else
596            draw_bgtile_lores(layer, ii, colour, pal, direct_colors, priority);
597      }
598      else /* hires */
599      {
600         if (mosaic)
601         {
602            for (x_mos = 0; x_mos < (m_mosaic_size + 1); x_mos++)
603               draw_bgtile_hires(layer, ii + x_mos, colour, pal, direct_colors, priority);
604            ii += x_mos - 1;
605         }
606         else
607            draw_bgtile_hires(layer, ii, colour, pal, direct_colors, priority);
608      }
609   }
610}
611
612/*************************************************************************************************
613 * SNES BG layers
614 *
615 * BG drawing theory of each scanline is quite easy: depending on the graphics Mode (0-7), there
616 * are up to 4 background layers. Pixels for each BG layer can have two different priorities.
617 * Depending on the line and on the BGHOFS and BGVOFS PPU registers, we first determine the tile
618 * address in m_vram (by determining x,y coord and tile size and by calling get_tmap_addr).
619 * Then, we load the correspondent data and we determine the tile properties: which priority to
620 * use, which palette etc. Finally, for each pixel of the tile appearing on screen, we check if
621 * the tile priority is higher than the BG/OAM already stored in that pixel for that line. If so
622 * we store the pixel in the buffer, otherwise we discard it.
623 *
624 * Of course, depending on the graphics Mode, it might be easier or harder to determine the proper
625 * tile address in vram (Mode 7 uses different registers, Mode 2, 4 and 6 uses OPT effect, etc.),
626 * but in general it works as described.
627 *************************************************************************************************/
628
629/*********************************************
630 * get_tmap_addr()
631 *
632 * Find the address in VRAM of the tile (x,y)
633 *********************************************/
634
635inline UINT32 snes_ppu_device::get_tmap_addr( UINT8 layer, UINT8 tile_size, UINT32 base, UINT32 x, UINT32 y )
636{
637   UINT32 res = base;
638   x  >>= (3 + tile_size);
639   y  >>= (3 + tile_size);
640
641   res += (m_layer[layer].tilemap_size & 2) ? ((y & 0x20) << ((m_layer[layer].tilemap_size & 1) ? 7 : 6)) : 0;
642   /* Scroll vertically */
643   res += (y & 0x1f) << 6;
644   /* Offset horizontally */
645   res += (m_layer[layer].tilemap_size & 1) ? ((x & 0x20) << 6) : 0;
646   /* Scroll horizontally */
647   res += (x & 0x1f) << 1;
648
649   return res;
650}
651
652/*********************************************
653 * update_line()
654 *
655 * Update an entire line of tiles.
656 *********************************************/
657
658inline void snes_ppu_device::update_line( UINT16 curline, UINT8 layer, UINT8 priority_b, UINT8 priority_a, UINT8 color_depth, UINT8 hires, UINT8 offset_per_tile, UINT8 direct_colors )
659{
660   UINT32 tmap, tile, xoff, yoff, charaddr, addr;
661   UINT16 ii = 0, vflip, hflip, pal, pal_direct, tilemap;
662   UINT8 xscroll, priority;
663   INT8 yscroll;
664   int tile_incr = 0;
665   UINT16 opt_bit = (layer == SNES_BG1) ? 13 : (layer == SNES_BG2) ? 14 : 0;
666   UINT8 tile_size;
667   /* variables depending on color_depth */
668   UINT8 color_planes = 2 << color_depth;
669   /* below we cheat to simplify the code: 8BPP should have 0 pal offset, not 0x100 (but we take care of this by later using pal % FIXED_COLOUR) */
670   UINT8 color_shift = 2 << color_depth;
671
672#if SNES_LAYER_DEBUG
673   if (m_debug_options.bg_disabled[layer])
674      return;
675#endif /* SNES_LAYER_DEBUG */
676
677   m_scanlines[SNES_MAINSCREEN].enable = m_layer[layer].main_bg_enabled;
678   m_scanlines[SNES_SUBSCREEN].enable = m_layer[layer].sub_bg_enabled;
679   m_scanlines[SNES_MAINSCREEN].clip = m_layer[layer].main_window_enabled;
680   m_scanlines[SNES_SUBSCREEN].clip = m_layer[layer].sub_window_enabled;
681
682   if (!m_scanlines[SNES_MAINSCREEN].enable && !m_scanlines[SNES_SUBSCREEN].enable)
683      return;
684
685   /* Handle Mosaic effects */
686   if (m_layer[layer].mosaic_enabled)
687      curline -= (curline % (m_mosaic_size + 1));
688
689   if ((m_interlace == 2) && !hires && !m_pseudo_hires)
690      curline /= 2;
691
692   /* Find the size of the tiles (8x8 or 16x16) */
693   tile_size = m_layer[layer].tile_size;
694
695   /* Find scroll info */
696   xoff = m_layer[layer].hoffs;
697   yoff = m_layer[layer].voffs;
698
699   xscroll = xoff & ((1 << (3 + tile_size)) - 1);
700
701   /* Jump to base map address */
702   tmap = m_layer[layer].tilemap << 9;
703   charaddr = m_layer[layer].charmap << 13;
704
705   while (ii < 256 + (8 << tile_size))
706   {
707      // determine the horizontal position (Bishojo Janshi Suchi Pai & Desert Figther have tile_size & hires == 1)
708      UINT32 xpos = xoff + (ii << (tile_size * hires));
709      UINT32 ypos = yoff + curline;
710
711      if (offset_per_tile != SNES_OPT_NONE)
712      {
713         int opt_x = ii + (xoff & 7);
714         UINT32 haddr = 0, vaddr = 0;
715         UINT16 hval = 0, vval = 0;
716
717         if (opt_x >= 8)
718         {
719            switch (offset_per_tile)
720            {
721            case SNES_OPT_MODE2:
722            case SNES_OPT_MODE6:
723               haddr = get_tmap_addr(SNES_BG3, m_layer[SNES_BG3].tile_size, m_layer[SNES_BG3].tilemap << 9, (opt_x - 8) + ((m_layer[SNES_BG3].hoffs & 0x3ff) & ~7), (m_layer[SNES_BG3].voffs & 0x3ff));
724               vaddr = get_tmap_addr(SNES_BG3, m_layer[SNES_BG3].tile_size, m_layer[SNES_BG3].tilemap << 9, (opt_x - 8) + ((m_layer[SNES_BG3].hoffs & 0x3ff) & ~7), (m_layer[SNES_BG3].voffs & 0x3ff) + 8);
725               hval = m_vram[haddr % SNES_VRAM_SIZE] | (m_vram[(haddr + 1) % SNES_VRAM_SIZE] << 8);
726               vval = m_vram[vaddr % SNES_VRAM_SIZE] | (m_vram[(vaddr + 1) % SNES_VRAM_SIZE] << 8);
727               if (BIT(hval, opt_bit))
728                  xpos = opt_x + (hval & ~7);
729               if (BIT(vval, opt_bit))
730                  ypos = curline + vval;
731               break;
732            case SNES_OPT_MODE4:
733               haddr = get_tmap_addr(SNES_BG3, m_layer[SNES_BG3].tile_size, m_layer[SNES_BG3].tilemap << 9, (opt_x - 8) + ((m_layer[SNES_BG3].hoffs & 0x3ff) & ~7), (m_layer[SNES_BG3].voffs & 0x3ff));
734               hval = m_vram[haddr % SNES_VRAM_SIZE] | (m_vram[(haddr + 1) % SNES_VRAM_SIZE] << 8);
735               if (BIT(hval, opt_bit))
736               {
737                  if (!BIT(hval, 15))
738                     xpos = opt_x + (hval & ~7);
739                  else
740                     ypos = curline + hval;
741               }
742               break;
743            }
744         }
745      }
746
747      addr = get_tmap_addr(layer, tile_size, tmap, xpos, ypos);
748
749      /*
750      Tilemap format
751        vhopppcc cccccccc
752
753        v/h  = Vertical/Horizontal flip this tile.
754        o    = Tile priority.
755        ppp  = Tile palette. The number of entries in the palette depends on the Mode and the BG.
756        cccccccccc = Tile number.
757      */
758      tilemap = m_vram[addr % SNES_VRAM_SIZE] | (m_vram[(addr + 1) % SNES_VRAM_SIZE] << 8);
759      vflip = BIT(tilemap, 15);
760      hflip = BIT(tilemap, 14);
761      priority = BIT(tilemap, 13) ? priority_a : priority_b;
762      pal_direct = ((tilemap & 0x1c00) >> 8);
763      tile = tilemap & 0x03ff;
764
765      pal = ((pal_direct >> 2) << color_shift);
766
767      /* Mode 0 palettes are layer specific */
768      if (m_mode == 0)
769      {
770         pal += (layer << 5);
771      }
772
773#if SNES_LAYER_DEBUG
774      /* if we want to draw only one of the priorities of this layer */
775      if (((m_debug_options.select_pri[layer] & 0x01) && (priority == priority_a)) ||
776         ((m_debug_options.select_pri[layer] & 0x02) && (priority == priority_b)))
777      {
778         if (!hires && tile_size)
779            ii += 16;
780         else
781            ii += 8;
782         continue;
783      }
784#endif /* SNES_LAYER_DEBUG */
785
786      /* figure out which line to draw */
787      yscroll = ypos & ((8 << tile_size) - 1);
788
789      if (tile_size)
790         if (BIT(yscroll, 3) != vflip)
791            tile += 16;
792
793      if (yscroll > 7)
794         yscroll &= 7;
795
796      if (vflip)
797         yscroll = 7 - yscroll;
798
799      yscroll <<= 1;
800
801      /* if we have to draw 16 pixels, set tile_incr and adjust tile for horizontal flip */
802      if (tile_size || hires)
803      {
804         if (hflip)
805         {
806            tile += 1;
807            tile_incr = -1; // next 8 pixels from previous tile (because of hflip)
808         }
809         else
810            tile_incr = 1;  // next 8 pixels from next tile
811      }
812
813      if (hires)
814      {
815         /* draw 16 pixels (the routine will automatically send half of them to the mainscreen scanline and half to the subscreen one) */
816         draw_tile(color_planes, layer, charaddr + (((tile + 0)         & 0x3ff) * 8 * color_planes) + yscroll, (ii - xscroll) * 2,     priority, hflip, direct_colors, direct_colors ? pal_direct : pal, hires);
817         draw_tile(color_planes, layer, charaddr + (((tile + tile_incr) & 0x3ff) * 8 * color_planes) + yscroll, (ii - xscroll) * 2 + 8, priority, hflip, direct_colors, direct_colors ? pal_direct : pal, hires);
818         ii += 8;
819      }
820      else
821      {
822         draw_tile(color_planes, layer, charaddr + ((tile & 0x3ff) * 8 * color_planes) + yscroll, ii - xscroll, priority, hflip, direct_colors, direct_colors ? pal_direct : pal, hires);
823         ii += 8;
824
825         if (tile_size)
826         {
827            draw_tile(color_planes, layer, charaddr + (((tile + tile_incr) & 0x3ff) * 8 * color_planes) + yscroll, ii - xscroll, priority, hflip, direct_colors, direct_colors ? pal_direct : pal, hires);
828            ii += 8;
829         }
830      }
831   }
832}
833
834
835/*********************************************
836 * update_line_mode7()
837 *
838 * Update an entire line of mode7 tiles.
839 *********************************************/
840
841#define MODE7_CLIP(x) (((x) & 0x2000) ? ((x) | ~0x03ff) : ((x) & 0x03ff))
842
843void snes_ppu_device::update_line_mode7( UINT16 curline, UINT8 layer, UINT8 priority_b, UINT8 priority_a )
844{
845   UINT32 tiled;
846   INT16 ma, mb, mc, md;
847   INT32 xc, yc, tx, ty, sx, sy, hs, vs, xpos, xdir, x0, y0;
848   UINT8 priority = priority_b;
849   UINT8 colour = 0;
850   UINT16 *mosaic_x, *mosaic_y;
851   UINT16 c;
852   int screen;
853
854#if SNES_LAYER_DEBUG
855   if (m_debug_options.bg_disabled[layer])
856      return;
857#endif /* SNES_LAYER_DEBUG */
858
859   m_scanlines[SNES_MAINSCREEN].enable = m_layer[layer].main_bg_enabled;
860   m_scanlines[SNES_SUBSCREEN].enable = m_layer[layer].sub_bg_enabled;
861   m_scanlines[SNES_MAINSCREEN].clip = m_layer[layer].main_window_enabled;
862   m_scanlines[SNES_SUBSCREEN].clip = m_layer[layer].sub_window_enabled;
863
864   if (!m_scanlines[SNES_MAINSCREEN].enable && !m_scanlines[SNES_SUBSCREEN].enable)
865      return;
866
867   ma = m_mode7.matrix_a;
868   mb = m_mode7.matrix_b;
869   mc = m_mode7.matrix_c;
870   md = m_mode7.matrix_d;
871   xc = m_mode7.origin_x;
872   yc = m_mode7.origin_y;
873   hs = m_mode7.hor_offset;
874   vs = m_mode7.ver_offset;
875
876   /* Sign extend */
877   xc <<= 19;
878   xc >>= 19;
879   yc <<= 19;
880   yc >>= 19;
881   hs <<= 19;
882   hs >>= 19;
883   vs <<= 19;
884   vs >>= 19;
885
886   /* Vertical flip */
887   if (m_mode7.vflip)
888      sy = 255 - curline;
889   else
890      sy = curline;
891
892   /* Horizontal flip */
893   if (m_mode7.hflip)
894   {
895      xpos = 255;
896      xdir = -1;
897   }
898   else
899   {
900      xpos = 0;
901      xdir = 1;
902   }
903
904   /* MOSAIC - to be verified */
905   if (layer == SNES_BG2)  // BG2 use two different bits for horizontal and vertical mosaic
906   {
907      mosaic_x = m_mosaic_table[m_layer[SNES_BG2].mosaic_enabled ? m_mosaic_size : 0];
908      mosaic_y = m_mosaic_table[m_layer[SNES_BG1].mosaic_enabled ? m_mosaic_size : 0];
909   }
910   else    // BG1 works as usual
911   {
912      mosaic_x =  m_mosaic_table[m_layer[SNES_BG1].mosaic_enabled ? m_mosaic_size : 0];
913      mosaic_y =  m_mosaic_table[m_layer[SNES_BG1].mosaic_enabled ? m_mosaic_size : 0];
914   }
915
916#if SNES_LAYER_DEBUG
917   if (m_debug_options.mosaic_disabled)
918   {
919      mosaic_x =  m_mosaic_table[0];
920      mosaic_y =  m_mosaic_table[0];
921   }
922#endif /* SNES_LAYER_DEBUG */
923
924   /* Let's do some mode7 drawing huh? */
925   /* These can be computed only once, since they do not depend on sx */
926   x0 = ((ma * MODE7_CLIP(hs - xc)) & ~0x3f) + ((mb * mosaic_y[sy]) & ~0x3f) + ((mb * MODE7_CLIP(vs - yc)) & ~0x3f) + (xc << 8);
927   y0 = ((mc * MODE7_CLIP(hs - xc)) & ~0x3f) + ((md * mosaic_y[sy]) & ~0x3f) + ((md * MODE7_CLIP(vs - yc)) & ~0x3f) + (yc << 8);
928
929   for (sx = 0; sx < 256; sx++, xpos += xdir)
930   {
931      tx = (x0 + (ma * mosaic_x[sx])) >> 8;
932      ty = (y0 + (mc * mosaic_x[sx])) >> 8;
933
934      switch (m_mode7.repeat)
935      {
936         case 0x00:  /* Repeat if outside screen area */
937         case 0x01:  /* Repeat if outside screen area */
938            tx &= 0x3ff;
939            ty &= 0x3ff;
940            tiled = m_vram[((((tx >> 3) & 0x7f) + (((ty >> 3) & 0x7f) * 128)) * 2) % SNES_VRAM_SIZE] << 7;
941            colour = m_vram[(tiled + ((tx & 0x07) * 2) + ((ty & 0x07) * 16) + 1) % SNES_VRAM_SIZE];
942            break;
943         case 0x02:  /* Single colour backdrop screen if outside screen area */
944            if ((tx >= 0) && (tx < 1024) && (ty >= 0) && (ty < 1024))
945            {
946               tiled = m_vram[((((tx >> 3) & 0x7f) + (((ty >> 3) & 0x7f) * 128)) * 2) % SNES_VRAM_SIZE] << 7;
947               colour = m_vram[(tiled + ((tx & 0x07) * 2) + ((ty & 0x07) * 16) + 1) % SNES_VRAM_SIZE];
948            }
949            else
950               colour = 0;
951            break;
952         case 0x03:  /* Character 0x00 repeat if outside screen area */
953            if ((tx >= 0) && (tx < 1024) && (ty >= 0) && (ty < 1024))
954               tiled = m_vram[((((tx >> 3) & 0x7f) + (((ty >> 3) & 0x7f) * 128)) * 2) % SNES_VRAM_SIZE] << 7;
955            else
956               tiled = 0;
957
958            colour = m_vram[(tiled + ((tx & 0x07) * 2) + ((ty & 0x07) * 16) + 1) % SNES_VRAM_SIZE];
959            break;
960      }
961
962      /* The last bit is for priority in EXTBG mode (used only for BG2) */
963      if (layer == SNES_BG2)
964      {
965         priority = ((colour & 0x80) >> 7) ? priority_a : priority_b;
966         colour &= 0x7f;
967
968#if SNES_LAYER_DEBUG
969      /* if we want to draw only one of the priorities of this layer */
970      if (((m_debug_options.select_pri[layer] & 0x01) && (priority == priority_a)) ||
971         ((m_debug_options.select_pri[layer] & 0x02) && (priority == priority_b)))
972         continue;
973#endif /* SNES_LAYER_DEBUG */
974      }
975
976      for (screen = SNES_MAINSCREEN; screen <= SNES_SUBSCREEN; screen++)
977      {
978         if (m_scanlines[screen].enable)
979         {
980            UINT8 clr = colour;
981            UINT8 clipmask = m_clipmasks[layer][xpos];
982
983#if SNES_LAYER_DEBUG
984            if (m_debug_options.windows_disabled)
985               clipmask = 0xff;
986#endif /* SNES_LAYER_DEBUG */
987
988            /* Clip to windows */
989            if (m_scanlines[screen].clip)
990               clr &= clipmask;
991
992            /* Draw pixel if appropriate */
993            if (m_scanlines[screen].priority[xpos] <= priority && clr > 0)
994            {
995               /* Direct select, but only outside EXTBG! */
996               // Direct color format is: 0 | BB000 | GGG00 | RRR00, HW confirms that the data is zero padded.
997               // In other words, like normal direct color, with pal = 0
998               c = get_bgcolor(m_direct_color && layer == SNES_BG1, 0, clr);
999               set_scanline_pixel(screen, xpos, c, priority, layer, 0);
1000            }
1001         }
1002      }
1003   }
1004}
1005
1006/*************************************************************************************************
1007 * SNES Sprites
1008 *
1009 * 1. First of all: sprites are drawn one line in advance. We emulate this by caching the
1010 * starting vram address, the sprite size and the "name select" at each line, and by using
1011 * them the next line to output the proper sprites - see update_obsel.
1012 *
1013 * 2. Each line can select its sprites among 128 available ones in oam_ram, hence we start
1014 * by creating a list of the available objects (each one with its x,y coordinate, its size,
1015 * its tile address, etc.) - see oam_list_build.
1016 *
1017 * 3. Next, we start finding out which sprites will appear in the line: starting from
1018 * FirstSprite, we count 32 OBJs which intersect our line and we store their indexes in the
1019 * oam_itemlist array (if more than 32 sprites intersect our line, we set the Range Over
1020 * flag); then, selecting among these sprites, we count 34 8x8 tiles which are visible
1021 * in our line (i.e. whose x coord is between -size and 256) and we store the corresponding
1022 * coordinates/priorities/palettes/etc. in the oam_tilelist array (if more than 34 tiles would
1023 * appear on screen, we set the Time Over flag).
1024 * Notice that when we populate oam_tilelist, we proceed from oam_itemlist[31] (or from the last
1025 * item which intersects the scanline), towards oam_itemlist[0], i.e. the higher tiles (say
1026 * oam_tilelist[34], or the last tile which appear on screen) will contain FirstSprite object,
1027 * or the sprites with closer index to FirstSprite which get displayed. This will play an
1028 * important role for sprite priority - see update_objects_rto.
1029 *
1030 * 4. All the above happens at the beginning of each VIDEO_UPDATE. When we finally draw the
1031 * scanline, we pass through the oam_tilelist and we store the displayed pixels in our scanline
1032 * buffer. Notice that, for each pixel of a SNES sprite, only the priority of the topmost sprite
1033 * is tested against the priority of the BG pixel (because FirstSprite is on top of FirstSprite+1,
1034 * which is on top of FirstSprite+2, etc., and therefore other sprites are already covered by the
1035 * topmost one). To emulate this, we draw each tile over the previous ones no matter what
1036 * priorities are (differently from what we did with BGs): in the end, we will have in each pixel z
1037 * its topmost sprite and scanline.priority[z] will be the topmost sprite priority as expected.
1038 * Of course, sprite drawing must happen before BG drawing, so that afterwords BG pixels properly
1039 * test their priority with the one of the correct sprite - see update_objects.
1040 *************************************************************************************************/
1041
1042
1043/*********************************************
1044 * update_obsel()
1045 *
1046 * Update sprite settings for next line.
1047 *********************************************/
1048
1049void snes_ppu_device::update_obsel( void )
1050{
1051   m_layer[SNES_OAM].charmap = m_oam.next_charmap;
1052   m_oam.name_select = m_oam.next_name_select;
1053
1054   if (m_oam.size != m_oam.next_size)
1055   {
1056      m_oam.size = m_oam.next_size;
1057      m_update_oam_list = 1;
1058   }
1059}
1060
1061/*********************************************
1062 * oam_list_build()
1063 *
1064 * Build a list of the available obj in OAM ram.
1065 *********************************************/
1066
1067void snes_ppu_device::oam_list_build( void )
1068{
1069   UINT8 *oamram = (UINT8 *)m_oam_ram;
1070   INT16 oam = 0x1ff;
1071   UINT16 oam_extra = oam + 0x20;
1072   UINT16 extra = 0;
1073   int ii;
1074
1075   m_update_oam_list = 0;       // eventually, we can optimize the code by only calling this function when there is a change in size
1076
1077   for (ii = 127; ii >= 0; ii--)
1078   {
1079      if (((ii + 1) % 4) == 0)
1080         extra = oamram[oam_extra--];
1081
1082      m_oam_spritelist[ii].vflip = (oamram[oam] & 0x80) >> 7;
1083      m_oam_spritelist[ii].hflip = (oamram[oam] & 0x40) >> 6;
1084      m_oam_spritelist[ii].priority_bits = (oamram[oam] & 0x30) >> 4;
1085      m_oam_spritelist[ii].pal = 128 + ((oamram[oam] & 0x0e) << 3);
1086      m_oam_spritelist[ii].tile = (oamram[oam--] & 0x1) << 8;
1087      m_oam_spritelist[ii].tile |= oamram[oam--];
1088      m_oam_spritelist[ii].y = oamram[oam--] + 1;
1089      m_oam_spritelist[ii].x = oamram[oam--];
1090      m_oam_spritelist[ii].size = (extra & 0x80) >> 7;
1091      extra <<= 1;
1092      m_oam_spritelist[ii].x |= ((extra & 0x80) << 1);
1093      extra <<= 1;
1094
1095      m_oam_spritelist[ii].y *= m_obj_interlace;
1096      m_oam_spritelist[ii].y &= 0x1ff;
1097
1098      m_oam_spritelist[ii].x &= 0x1ff;
1099
1100      /* Determine object size */
1101      switch (m_oam.size)
1102      {
1103      case 0:         /* 8x8 or 16x16 */
1104         m_oam_spritelist[ii].width  = m_oam_spritelist[ii].size ? 2 : 1;
1105         m_oam_spritelist[ii].height = m_oam_spritelist[ii].size ? 2 : 1;
1106         break;
1107      case 1:         /* 8x8 or 32x32 */
1108         m_oam_spritelist[ii].width  = m_oam_spritelist[ii].size ? 4 : 1;
1109         m_oam_spritelist[ii].height = m_oam_spritelist[ii].size ? 4 : 1;
1110         break;
1111      case 2:         /* 8x8 or 64x64 */
1112         m_oam_spritelist[ii].width  = m_oam_spritelist[ii].size ? 8 : 1;
1113         m_oam_spritelist[ii].height = m_oam_spritelist[ii].size ? 8 : 1;
1114         break;
1115      case 3:         /* 16x16 or 32x32 */
1116         m_oam_spritelist[ii].width  = m_oam_spritelist[ii].size ? 4 : 2;
1117         m_oam_spritelist[ii].height = m_oam_spritelist[ii].size ? 4 : 2;
1118         break;
1119      case 4:         /* 16x16 or 64x64 */
1120         m_oam_spritelist[ii].width  = m_oam_spritelist[ii].size ? 8 : 2;
1121         m_oam_spritelist[ii].height = m_oam_spritelist[ii].size ? 8 : 2;
1122         break;
1123      case 5:         /* 32x32 or 64x64 */
1124         m_oam_spritelist[ii].width  = m_oam_spritelist[ii].size ? 8 : 4;
1125         m_oam_spritelist[ii].height = m_oam_spritelist[ii].size ? 8 : 4;
1126         break;
1127      case 6:         /* undocumented: 16x32 or 32x64 */
1128         m_oam_spritelist[ii].width  = m_oam_spritelist[ii].size ? 4 : 2;
1129         m_oam_spritelist[ii].height = m_oam_spritelist[ii].size ? 8 : 4;
1130         if (m_obj_interlace && !m_oam_spritelist[ii].size)
1131            m_oam_spritelist[ii].height = 2;
1132         break;
1133      case 7:         /* undocumented: 16x32 or 32x32 */
1134         m_oam_spritelist[ii].width  = m_oam_spritelist[ii].size ? 4 : 2;
1135         m_oam_spritelist[ii].height = m_oam_spritelist[ii].size ? 4 : 4;
1136         if (m_obj_interlace && !m_oam_spritelist[ii].size)
1137            m_oam_spritelist[ii].height = 2;
1138         break;
1139      default:
1140         /* we should never enter here... */
1141         logerror("Object size unsupported: %d\n", m_oam.size);
1142         break;
1143      }
1144   }
1145}
1146
1147/*********************************************
1148 * is_sprite_on_scanline()
1149 *
1150 * Check if a given sprites intersect current
1151 * scanline
1152 *********************************************/
1153
1154int snes_ppu_device::is_sprite_on_scanline( UINT16 curline, UINT8 sprite )
1155{
1156   //if sprite is entirely offscreen and doesn't wrap around to the left side of the screen,
1157   //then it is not counted. this *should* be 256, and not 255, even though dot 256 is offscreen.
1158   int spr_height = (m_oam_spritelist[sprite].height << 3);
1159
1160   if (m_oam_spritelist[sprite].x > 256 && (m_oam_spritelist[sprite].x + (m_oam_spritelist[sprite].width << 3) - 1) < 512)
1161      return 0;
1162
1163   if (curline >= m_oam_spritelist[sprite].y && curline < (m_oam_spritelist[sprite].y + spr_height))
1164      return 1;
1165
1166   if ((m_oam_spritelist[sprite].y + spr_height) >= 256 && curline < ((m_oam_spritelist[sprite].y + spr_height) & 255))
1167      return 1;
1168
1169   return 0;
1170}
1171
1172/*********************************************
1173 * update_objects_rto()
1174 *
1175 * Determine which OBJs will be drawn on this
1176 * scanline.
1177 *********************************************/
1178
1179void snes_ppu_device::update_objects_rto( UINT16 curline )
1180{
1181   int ii, jj, active_sprite;
1182   UINT8 range_over, time_over;
1183   INT8 xs, ys;
1184   UINT8 line;
1185   UINT8 height, width, vflip, hflip, priority, pal;
1186   UINT16 tile;
1187   INT16 x, y;
1188   UINT32 name_sel = 0;
1189
1190   oam_list_build();
1191
1192   /* initialize counters */
1193   range_over = 0;
1194   time_over = 0;
1195
1196   /* setup the proper line */
1197   curline /= m_interlace;
1198   curline *= m_obj_interlace;
1199
1200   /* reset the list of first 32 objects which intersect current scanline */
1201   memset(m_oam_itemlist, 0xff, 32);
1202
1203   /* populate the list of 32 objects */
1204   for (ii = 0; ii < 128; ii++)
1205   {
1206      active_sprite = (ii + m_oam.first_sprite) & 0x7f;
1207
1208      if (!is_sprite_on_scanline(curline, active_sprite))
1209         continue;
1210
1211      if (range_over++ >= 32)
1212         break;
1213
1214      m_oam_itemlist[range_over - 1] = active_sprite;
1215   }
1216
1217   /* reset the list of first 34 tiles to be drawn */
1218   for (ii = 0; ii < 34; ii++)
1219      m_oam_tilelist[ii].tileaddr = 0xffff;
1220
1221   /* populate the list of 34 tiles */
1222   for (ii = 31; ii >= 0; ii--)
1223   {
1224      if (m_oam_itemlist[ii] == 0xff)
1225         continue;
1226
1227      active_sprite = m_oam_itemlist[ii];
1228
1229      tile = m_oam_spritelist[active_sprite].tile;
1230      x = m_oam_spritelist[active_sprite].x;
1231      y = m_oam_spritelist[active_sprite].y;
1232      height = m_oam_spritelist[active_sprite].height;
1233      width = m_oam_spritelist[active_sprite].width;
1234      vflip = m_oam_spritelist[active_sprite].vflip;
1235      hflip = m_oam_spritelist[active_sprite].hflip;
1236      priority = m_oam_spritelist[active_sprite].priority_bits;
1237      pal = m_oam_spritelist[active_sprite].pal;
1238
1239      /* Adjust y, if past maximum position (for sprites which overlap between top & bottom) */
1240      if (y >= (0x100 - 16) * m_interlace)
1241         y -= (0x100) * m_interlace;
1242
1243      if (curline >= y && curline < (y + (height << 3)))
1244      {
1245         /* Only objects using tiles over 255 use name select */
1246         name_sel = (tile < 256) ? 0 : m_oam.name_select;
1247
1248         ys = (curline - y) >> 3;
1249         line = (curline - y) % 8;
1250         if (vflip)
1251         {
1252            ys = height - ys - 1;
1253            line = 7 - line;
1254         }
1255         line <<= 1;
1256         tile <<= 5;
1257
1258         for (jj = 0; jj < width; jj++)
1259         {
1260            INT16 xx = (x + (jj << 3)) & 0x1ff;
1261
1262            if (x != 256 && xx >= 256 && (xx + 7) < 512)
1263               continue;
1264
1265            if (time_over++ >= 34)
1266               break;
1267
1268            xs = (hflip) ? (width - 1 - jj) : jj;
1269            m_oam_tilelist[time_over - 1].tileaddr = name_sel + tile + table_obj_offset[ys][xs] + line;
1270            m_oam_tilelist[time_over - 1].hflip = hflip;
1271            m_oam_tilelist[time_over - 1].x = xx;
1272            m_oam_tilelist[time_over - 1].pal = pal;
1273            m_oam_tilelist[time_over - 1].priority = priority;
1274         }
1275      }
1276   }
1277
1278   /* set Range Over flag if necessary */
1279   if (range_over > 32)
1280      m_stat77 |= 0x40;
1281
1282   /* set Time Over flag if necessary */
1283   if (time_over > 34)
1284      m_stat77 |= 0x80;
1285}
1286
1287/*********************************************
1288 * update_objects()
1289 *
1290 * Update an entire line of sprites.
1291 *********************************************/
1292
1293void snes_ppu_device::update_objects( UINT8 priority_oam0, UINT8 priority_oam1, UINT8 priority_oam2, UINT8 priority_oam3 )
1294{
1295   UINT8 pri, priority[4];
1296   UINT32 charaddr;
1297   int ii;
1298
1299#if SNES_LAYER_DEBUG
1300   if (m_debug_options.bg_disabled[SNES_OAM])
1301      return;
1302#endif /* SNES_LAYER_DEBUG */
1303
1304   m_scanlines[SNES_MAINSCREEN].enable = m_layer[SNES_OAM].main_bg_enabled;
1305   m_scanlines[SNES_SUBSCREEN].enable = m_layer[SNES_OAM].sub_bg_enabled;
1306   m_scanlines[SNES_MAINSCREEN].clip = m_layer[SNES_OAM].main_window_enabled;
1307   m_scanlines[SNES_SUBSCREEN].clip = m_layer[SNES_OAM].sub_window_enabled;
1308
1309   if (!m_scanlines[SNES_MAINSCREEN].enable && !m_scanlines[SNES_SUBSCREEN].enable)
1310      return;
1311
1312   charaddr = m_layer[SNES_OAM].charmap << 13;
1313
1314   priority[0] = priority_oam0;
1315   priority[1] = priority_oam1;
1316   priority[2] = priority_oam2;
1317   priority[3] = priority_oam3;
1318
1319   /* finally draw the tiles from the tilelist */
1320   for (ii = 0; ii < 34; ii++)
1321   {
1322      int tile = ii;
1323#if SNES_LAYER_DEBUG
1324      if (m_debug_options.sprite_reversed)
1325         tile = 33 - ii;
1326#endif /* SNES_LAYER_DEBUG */
1327
1328      if (m_oam_tilelist[tile].tileaddr == 0xffff)
1329         continue;
1330
1331      pri = priority[m_oam_tilelist[tile].priority];
1332
1333#if SNES_LAYER_DEBUG
1334      if (m_debug_options.select_pri[SNES_OAM])
1335      {
1336         int oam_draw = m_debug_options.select_pri[SNES_OAM] - 1;
1337         if (oam_draw != m_oam_tilelist[tile].priority)
1338            continue;
1339      }
1340#endif /* SNES_LAYER_DEBUG */
1341
1342      /* OAM tiles have fixed planes (4), no direct color and no hires, but otherwise work the same as BG ones */
1343      draw_tile(4, SNES_OAM, charaddr + m_oam_tilelist[tile].tileaddr, m_oam_tilelist[tile].x, pri, m_oam_tilelist[tile].hflip, 0, m_oam_tilelist[tile].pal, 0);
1344   }
1345}
1346
1347
1348/*********************************************
1349 * snes_update_mode_X()
1350 *
1351 * Update Mode X line.
1352 *********************************************/
1353
1354void snes_ppu_device::update_mode_0( UINT16 curline )
1355{
1356#if SNES_LAYER_DEBUG
1357   if (m_debug_options.mode_disabled[0])
1358      return;
1359#endif /* SNES_LAYER_DEBUG */
1360
1361   update_objects(3, 6, 9, 12);
1362   update_line(curline, SNES_BG1, 8, 11, SNES_COLOR_DEPTH_2BPP, 0, SNES_OPT_NONE, 0);
1363   update_line(curline, SNES_BG2, 7, 10, SNES_COLOR_DEPTH_2BPP, 0, SNES_OPT_NONE, 0);
1364   update_line(curline, SNES_BG3, 2, 5,  SNES_COLOR_DEPTH_2BPP, 0, SNES_OPT_NONE, 0);
1365   update_line(curline, SNES_BG4, 1, 4,  SNES_COLOR_DEPTH_2BPP, 0, SNES_OPT_NONE, 0);
1366}
1367
1368void snes_ppu_device::update_mode_1( UINT16 curline )
1369{
1370#if SNES_LAYER_DEBUG
1371   if (m_debug_options.mode_disabled[1])
1372      return;
1373#endif /* SNES_LAYER_DEBUG */
1374
1375   if (!m_bg3_priority_bit)
1376   {
1377      update_objects(2, 4, 7, 10);
1378      update_line(curline, SNES_BG1, 6, 9, SNES_COLOR_DEPTH_4BPP, 0, SNES_OPT_NONE, 0);
1379      update_line(curline, SNES_BG2, 5, 8, SNES_COLOR_DEPTH_4BPP, 0, SNES_OPT_NONE, 0);
1380      update_line(curline, SNES_BG3, 1, 3, SNES_COLOR_DEPTH_2BPP, 0, SNES_OPT_NONE, 0);
1381   }
1382   else
1383   {
1384      update_objects(2, 3, 6, 9);
1385      update_line(curline, SNES_BG1, 5, 8,  SNES_COLOR_DEPTH_4BPP, 0, SNES_OPT_NONE, 0);
1386      update_line(curline, SNES_BG2, 4, 7,  SNES_COLOR_DEPTH_4BPP, 0, SNES_OPT_NONE, 0);
1387      update_line(curline, SNES_BG3, 1, 10, SNES_COLOR_DEPTH_2BPP, 0, SNES_OPT_NONE, 0);
1388   }
1389}
1390
1391void snes_ppu_device::update_mode_2( UINT16 curline )
1392{
1393#if SNES_LAYER_DEBUG
1394   if (m_debug_options.mode_disabled[2])
1395      return;
1396#endif /* SNES_LAYER_DEBUG */
1397
1398   update_objects(2, 4, 6, 8);
1399   update_line(curline, SNES_BG1, 3, 7, SNES_COLOR_DEPTH_4BPP, 0, SNES_OPT_MODE2, 0);
1400   update_line(curline, SNES_BG2, 1, 5, SNES_COLOR_DEPTH_4BPP, 0, SNES_OPT_MODE2, 0);
1401}
1402
1403void snes_ppu_device::update_mode_3( UINT16 curline )
1404{
1405#if SNES_LAYER_DEBUG
1406   if (m_debug_options.mode_disabled[3])
1407      return;
1408#endif /* SNES_LAYER_DEBUG */
1409
1410   update_objects(2, 4, 6, 8);
1411   update_line(curline, SNES_BG1, 3, 7, SNES_COLOR_DEPTH_8BPP, 0, SNES_OPT_NONE, m_direct_color);
1412   update_line(curline, SNES_BG2, 1, 5, SNES_COLOR_DEPTH_4BPP, 0, SNES_OPT_NONE, 0);
1413}
1414
1415void snes_ppu_device::update_mode_4( UINT16 curline )
1416{
1417#if SNES_LAYER_DEBUG
1418   if (m_debug_options.mode_disabled[4])
1419      return;
1420#endif /* SNES_LAYER_DEBUG */
1421
1422   update_objects(2, 4, 6, 8);
1423   update_line(curline, SNES_BG1, 3, 7, SNES_COLOR_DEPTH_8BPP, 0, SNES_OPT_MODE4, m_direct_color);
1424   update_line(curline, SNES_BG2, 1, 5, SNES_COLOR_DEPTH_2BPP, 0, SNES_OPT_MODE4, 0);
1425}
1426
1427void snes_ppu_device::update_mode_5( UINT16 curline )
1428{
1429#if SNES_LAYER_DEBUG
1430   if (m_debug_options.mode_disabled[5])
1431      return;
1432#endif /* SNES_LAYER_DEBUG */
1433
1434   update_objects(2, 4, 6, 8);
1435   update_line(curline, SNES_BG1, 3, 7, SNES_COLOR_DEPTH_4BPP, 1, SNES_OPT_NONE, 0);
1436   update_line(curline, SNES_BG2, 1, 5, SNES_COLOR_DEPTH_2BPP, 1, SNES_OPT_NONE, 0);
1437}
1438
1439void snes_ppu_device::update_mode_6( UINT16 curline )
1440{
1441#if SNES_LAYER_DEBUG
1442   if (m_debug_options.mode_disabled[6])
1443      return;
1444#endif /* SNES_LAYER_DEBUG */
1445
1446   update_objects(1, 3, 4, 6);
1447   update_line(curline, SNES_BG1, 2, 5, SNES_COLOR_DEPTH_4BPP, 1, SNES_OPT_MODE6, 0);
1448}
1449
1450void snes_ppu_device::update_mode_7( UINT16 curline )
1451{
1452#if SNES_LAYER_DEBUG
1453   if (m_debug_options.mode_disabled[7])
1454      return;
1455#endif /* SNES_LAYER_DEBUG */
1456
1457   if (!m_mode7.extbg)
1458   {
1459      update_objects(1, 3, 4, 5);
1460      update_line_mode7(curline, SNES_BG1, 2, 2);
1461   }
1462   else
1463   {
1464      update_objects(2, 4, 6, 7);
1465      update_line_mode7(curline, SNES_BG1, 3, 3);
1466      update_line_mode7(curline, SNES_BG2, 1, 5);
1467   }
1468}
1469
1470/*********************************************
1471 * snes_draw_screens()
1472 *
1473 * Draw the whole screen (Mode 0 -> 7).
1474 *********************************************/
1475
1476void snes_ppu_device::draw_screens( UINT16 curline )
1477{
1478   switch (m_mode)
1479   {
1480      case 0: update_mode_0(curline); break;     /* Mode 0 */
1481      case 1: update_mode_1(curline); break;     /* Mode 1 */
1482      case 2: update_mode_2(curline); break;     /* Mode 2 - Supports offset per tile */
1483      case 3: update_mode_3(curline); break;     /* Mode 3 - Supports direct colour */
1484      case 4: update_mode_4(curline); break;     /* Mode 4 - Supports offset per tile and direct colour */
1485      case 5: update_mode_5(curline); break;     /* Mode 5 - Supports hires */
1486      case 6: update_mode_6(curline); break;     /* Mode 6 - Supports offset per tile and hires */
1487      case 7: update_mode_7(curline); break;     /* Mode 7 - Supports direct colour */
1488   }
1489}
1490
1491/*********************************************
1492 * update_windowmasks()
1493 *
1494 * An example of how windows work:
1495 * Win1: ...#####......
1496 * Win2: ......#####...
1497 *             IN                 OUT
1498 * OR:   ...########...     ###........###
1499 * AND:  ......##......     ######..######
1500 * XOR:  ...###..###...     ###...##...###
1501 * XNOR: ###...##...###     ...###..###...
1502 *********************************************/
1503
1504void snes_ppu_device::update_windowmasks( void )
1505{
1506   UINT16 ii, jj;
1507   INT8 w1, w2;
1508
1509   m_update_windows = 0;        /* reset the flag */
1510
1511   for (ii = 0; ii < SNES_SCR_WIDTH; ii++)
1512   {
1513      /* update bg 1, 2, 3, 4, obj & color windows */
1514      /* jj = layer */
1515      for (jj = 0; jj < 6; jj++)
1516      {
1517         m_clipmasks[jj][ii] = 0xff;  /* let's start from un-masked */
1518         w1 = w2 = -1;
1519
1520         if (m_layer[jj].window1_enabled)
1521         {
1522            /* Default to mask area inside */
1523            if ((ii < m_window1_left) || (ii > m_window1_right))
1524               w1 = 0;
1525            else
1526               w1 = 1;
1527
1528            /* If mask area is outside then swap */
1529            if (m_layer[jj].window1_invert)
1530               w1 = !w1;
1531         }
1532
1533         if (m_layer[jj].window2_enabled)
1534         {
1535            if ((ii < m_window2_left) || (ii > m_window2_right))
1536               w2 = 0;
1537            else
1538               w2 = 1;
1539            if (m_layer[jj].window2_invert)
1540               w2 = !w2;
1541         }
1542
1543         /* mask if the appropriate expression is true */
1544         if (w1 >= 0 && w2 >= 0)
1545         {
1546            switch (m_layer[jj].wlog_mask)
1547            {
1548               case 0x00:  /* OR */
1549                  m_clipmasks[jj][ii] = (w1 | w2) ? 0x00 : 0xff;
1550                  break;
1551               case 0x01:  /* AND */
1552                  m_clipmasks[jj][ii] = (w1 & w2) ? 0x00 : 0xff;
1553                  break;
1554               case 0x02:  /* XOR */
1555                  m_clipmasks[jj][ii] = (w1 ^ w2) ? 0x00 : 0xff;
1556                  break;
1557               case 0x03:  /* XNOR */
1558                  m_clipmasks[jj][ii] = !(w1 ^ w2) ? 0x00 : 0xff;
1559                  break;
1560            }
1561         }
1562         else if (w1 >= 0)
1563            m_clipmasks[jj][ii] = w1 ? 0x00 : 0xff;
1564         else if (w2 >= 0)
1565            m_clipmasks[jj][ii] = w2 ? 0x00 : 0xff;
1566      }
1567   }
1568}
1569
1570/*********************************************
1571 * update_offsets()
1572 *
1573 * Update the offsets with the latest changes.
1574 * This is currently unused, but it could
1575 * possibly be handy for some minor optimization
1576 *********************************************/
1577
1578void snes_ppu_device::update_offsets( void )
1579{
1580   int ii;
1581   for (ii = 0; ii < 4; ii++)
1582   {
1583   }
1584   m_update_offsets = 0;
1585}
1586
1587/*****************************************
1588 * draw_blend()
1589 *
1590 * Routine for additive/subtractive blending
1591 * between the main and sub screens, i.e.
1592 * color math.
1593 *****************************************/
1594
1595inline void snes_ppu_device::draw_blend( UINT16 offset, UINT16 *colour, UINT8 prevent_color_math, UINT8 black_pen_clip, int switch_screens )
1596{
1597#if SNES_LAYER_DEBUG
1598   if (m_debug_options.colormath_disabled)
1599      return;
1600#endif /* SNES_LAYER_DEBUG */
1601
1602   /* when color math is applied to subscreen pixels, the blending depends on the blending used by the previous mainscreen
1603   pixel, except for subscreen pixel 0 which has no previous mainscreen pixel, see comments in refresh_scanline */
1604   if (switch_screens && offset > 0)
1605      offset -= 1;
1606
1607   if ((black_pen_clip == SNES_CLIP_ALWAYS) ||
1608      (black_pen_clip == SNES_CLIP_IN && m_clipmasks[SNES_COLOR][offset]) ||
1609      (black_pen_clip == SNES_CLIP_OUT && !m_clipmasks[SNES_COLOR][offset]))
1610      *colour = 0; //clip to black before color math
1611
1612   if (prevent_color_math == SNES_CLIP_ALWAYS) // blending mode 3 == always OFF
1613      return;
1614
1615   if ((prevent_color_math == SNES_CLIP_NEVER) ||
1616      (prevent_color_math == SNES_CLIP_IN  && !m_clipmasks[SNES_COLOR][offset]) ||
1617      (prevent_color_math == SNES_CLIP_OUT && m_clipmasks[SNES_COLOR][offset]))
1618   {
1619      UINT16 r, g, b;
1620      struct SNES_SCANLINE *subscreen;
1621      int clip_max = 0;   // if add then clip to 0x1f, if sub then clip to 0
1622
1623#if SNES_LAYER_DEBUG
1624      /* Toggle drawing of SNES_SUBSCREEN or SNES_MAINSCREEN */
1625      if (m_debug_options.draw_subscreen)
1626      {
1627         subscreen = switch_screens ? &m_scanlines[SNES_SUBSCREEN] : &m_scanlines[SNES_MAINSCREEN];
1628      }
1629      else
1630#endif /* SNES_LAYER_DEBUG */
1631      {
1632         subscreen = switch_screens ? &m_scanlines[SNES_MAINSCREEN] : &m_scanlines[SNES_SUBSCREEN];
1633      }
1634
1635      if (m_sub_add_mode) /* SNES_SUBSCREEN*/
1636      {
1637         if (!BIT(m_color_modes, 7))
1638         {
1639            /* 0x00 add */
1640            r = (*colour & 0x1f) + (subscreen->buffer[offset] & 0x1f);
1641            g = ((*colour & 0x3e0) >> 5) + ((subscreen->buffer[offset] & 0x3e0) >> 5);
1642            b = ((*colour & 0x7c00) >> 10) + ((subscreen->buffer[offset] & 0x7c00) >> 10);
1643            clip_max = 1;
1644         }
1645         else
1646         {
1647            /* 0x80 sub */
1648            r = (*colour & 0x1f) - (subscreen->buffer[offset] & 0x1f);
1649            g = ((*colour & 0x3e0) >> 5) - ((subscreen->buffer[offset] & 0x3e0) >> 5);
1650            b = ((*colour & 0x7c00) >> 10) - ((subscreen->buffer[offset] & 0x7c00) >> 10);
1651            if (r > 0x1f) r = 0;
1652            if (g > 0x1f) g = 0;
1653            if (b > 0x1f) b = 0;
1654         }
1655         /* only halve if the color is not the back colour */
1656         if (BIT(m_color_modes, 6) && (subscreen->buffer[offset] != m_cgram[FIXED_COLOUR]))
1657         {
1658            r >>= 1;
1659            g >>= 1;
1660            b >>= 1;
1661         }
1662      }
1663      else /* Fixed colour */
1664      {
1665         if (!BIT(m_color_modes, 7))
1666         {
1667            /* 0x00 add */
1668            r = (*colour & 0x1f) + (m_cgram[FIXED_COLOUR] & 0x1f);
1669            g = ((*colour & 0x3e0) >> 5) + ((m_cgram[FIXED_COLOUR] & 0x3e0) >> 5);
1670            b = ((*colour & 0x7c00) >> 10) + ((m_cgram[FIXED_COLOUR] & 0x7c00) >> 10);
1671            clip_max = 1;
1672         }
1673         else
1674         {
1675            /* 0x80: sub */
1676            r = (*colour & 0x1f) - (m_cgram[FIXED_COLOUR] & 0x1f);
1677            g = ((*colour & 0x3e0) >> 5) - ((m_cgram[FIXED_COLOUR] & 0x3e0) >> 5);
1678            b = ((*colour & 0x7c00) >> 10) - ((m_cgram[FIXED_COLOUR] & 0x7c00) >> 10);
1679            if (r > 0x1f) r = 0;
1680            if (g > 0x1f) g = 0;
1681            if (b > 0x1f) b = 0;
1682         }
1683         /* halve if necessary */
1684         if (BIT(m_color_modes, 6))
1685         {
1686            r >>= 1;
1687            g >>= 1;
1688            b >>= 1;
1689         }
1690      }
1691
1692      /* according to anomie's docs, after addition has been performed, division by 2 happens *before* clipping to max, hence we clip now */
1693      if (clip_max)
1694      {
1695         if (r > 0x1f) r = 0x1f;
1696         if (g > 0x1f) g = 0x1f;
1697         if (b > 0x1f) b = 0x1f;
1698      }
1699
1700      *colour = ((r & 0x1f) | ((g & 0x1f) << 5) | ((b & 0x1f) << 10));
1701   }
1702}
1703
1704/*********************************************
1705 * refresh_scanline()
1706 *
1707 * Redraw the current line.
1708 *********************************************/
1709/*********************************************
1710 * Notice that in hires and pseudo hires modes,
1711 * i.e. when 512 different pixels are present
1712 * in a scanline, a crt TV monitor would end
1713 * up blending adjacent pixels. To mimic this,
1714 * we add a small (optional) hack which enters
1715 * only in the very last stage of the scanline
1716 * drawing and which simulates the TV by
1717 * replacing the exact pixel color with an
1718 * average of the current and next pixel colors.
1719 * Credits (and thanks) to Blargg and Byuu for
1720 * the optimized averaging algorithm.
1721 *********************************************/
1722
1723void snes_ppu_device::refresh_scanline( running_machine &machine, bitmap_rgb32 &bitmap, UINT16 curline )
1724{
1725   UINT16 ii;
1726   int x;
1727   int fade;
1728   struct SNES_SCANLINE *scanline1, *scanline2;
1729   UINT16 c;
1730   UINT16 prev_colour = 0;
1731   int blurring = machine.root_device().ioport("OPTIONS")->read_safe(0) & 0x01;
1732
1733   g_profiler.start(PROFILER_VIDEO);
1734
1735   if (m_screen_disabled) /* screen is forced blank */
1736      for (x = 0; x < SNES_SCR_WIDTH * 2; x++)
1737         bitmap.pix32(curline, x) = rgb_t::black;
1738   else
1739   {
1740      /* Update clip window masks if necessary */
1741      if (m_update_windows)
1742         update_windowmasks();
1743      /* Update the offsets if necessary */
1744      if (m_update_offsets)
1745         update_offsets();
1746
1747      /* Clear priority */
1748      memset(m_scanlines[SNES_MAINSCREEN].priority, 0, SNES_SCR_WIDTH);
1749      memset(m_scanlines[SNES_SUBSCREEN].priority, 0, SNES_SCR_WIDTH);
1750
1751      /* Clear layers */
1752      memset(m_scanlines[SNES_MAINSCREEN].layer, SNES_COLOR, SNES_SCR_WIDTH);
1753      memset(m_scanlines[SNES_SUBSCREEN].layer, SNES_COLOR, SNES_SCR_WIDTH);
1754
1755      /* Clear blend_exception (only used for OAM) */
1756      memset(m_scanlines[SNES_MAINSCREEN].blend_exception, 0, SNES_SCR_WIDTH);
1757      memset(m_scanlines[SNES_SUBSCREEN].blend_exception, 0, SNES_SCR_WIDTH);
1758
1759      /* Draw back colour */
1760      for (ii = 0; ii < SNES_SCR_WIDTH; ii++)
1761      {
1762         if (m_mode == 5 || m_mode == 6 || m_pseudo_hires)
1763            m_scanlines[SNES_SUBSCREEN].buffer[ii] = m_cgram[0];
1764         else
1765            m_scanlines[SNES_SUBSCREEN].buffer[ii] = m_cgram[FIXED_COLOUR];
1766
1767         m_scanlines[SNES_MAINSCREEN].buffer[ii] = m_cgram[0];
1768      }
1769
1770      /* Prepare OAM for this scanline */
1771      update_objects_rto(curline);
1772
1773      /* Draw scanline */
1774      draw_screens(curline);
1775
1776      update_obsel();
1777
1778#if SNES_LAYER_DEBUG
1779      if (dbg_video(machine, curline))
1780      {
1781         g_profiler.stop();
1782         return;
1783      }
1784
1785      /* Toggle drawing of SNES_SUBSCREEN or SNES_MAINSCREEN */
1786      if (m_debug_options.draw_subscreen)
1787      {
1788         scanline1 = &m_scanlines[SNES_SUBSCREEN];
1789         scanline2 = &m_scanlines[SNES_MAINSCREEN];
1790      }
1791      else
1792#endif /* SNES_LAYER_DEBUG */
1793      {
1794         scanline1 = &m_scanlines[SNES_MAINSCREEN];
1795         scanline2 = &m_scanlines[SNES_SUBSCREEN];
1796      }
1797
1798      /* Draw the scanline to screen */
1799
1800      fade = m_screen_brightness;
1801
1802      for (x = 0; x < SNES_SCR_WIDTH; x++)
1803      {
1804         int r, g, b, hires;
1805         UINT16 tmp_col[2];
1806         hires = (m_mode != 5 && m_mode != 6 && !m_pseudo_hires) ? 0 : 1;
1807
1808         /* in hires, the first pixel (of 512) is subscreen pixel, then the first mainscreen pixel follows, and so on... */
1809         if (!hires)
1810         {
1811            c = scanline1->buffer[x];
1812
1813            /* perform color math if the layer wants it (except if it's an object > 192) */
1814            if (!scanline1->blend_exception[x] && m_layer[scanline1->layer[x]].color_math)
1815               draw_blend(x, &c, m_prevent_color_math, m_clip_to_black, 0);
1816
1817            r = ((c & 0x1f) * fade) >> 4;
1818            g = (((c & 0x3e0) >> 5) * fade) >> 4;
1819            b = (((c & 0x7c00) >> 10) * fade) >> 4;
1820
1821            bitmap.pix32(curline, x * 2 + 0) = rgb_t(pal5bit(r), pal5bit(g), pal5bit(b));
1822            bitmap.pix32(curline, x * 2 + 1) = rgb_t(pal5bit(r), pal5bit(g), pal5bit(b));
1823         }
1824         else
1825         {
1826            /* prepare the pixel from main screen */
1827            c = scanline1->buffer[x];
1828
1829            /* perform color math if the layer wants it (except if it's an object > 192) */
1830            if (!scanline1->blend_exception[x] && m_layer[scanline1->layer[x]].color_math)
1831               draw_blend(x, &c, m_prevent_color_math, m_clip_to_black, 0);
1832
1833            tmp_col[1] = c;
1834
1835            /* prepare the pixel from sub screen */
1836            c = scanline2->buffer[x];
1837
1838            /* in hires/pseudo-hires, subscreen pixels are blended as well: for each subscreen pixel, color math
1839            is applied if it had been applied to the previous mainscreen pixel. What happens at subscreen pixel 0
1840            (which has no previous mainscreen pixel) is undocumented. Until more info are discovered, we (arbitrarily)
1841            apply to it the same color math as the *next* mainscreen pixel (i.e. mainscreen pixel 0), which seems as good as
1842            any other choice */
1843            if (x == 0 && !scanline1->blend_exception[0] && m_layer[scanline1->layer[0]].color_math)
1844               draw_blend(0, &c, m_prevent_color_math, m_clip_to_black, 1);
1845            else if (x > 0  && !scanline1->blend_exception[x - 1] && m_layer[scanline1->layer[x - 1]].color_math)
1846               draw_blend(x, &c, m_prevent_color_math, m_clip_to_black, 1);
1847
1848            tmp_col[0] = c;
1849
1850            /* average the first pixel if required, or draw it directly*/
1851            if (blurring)
1852               c = (prev_colour + tmp_col[0] - ((prev_colour ^ tmp_col[0]) & 0x0421)) >> 1;    // Hack code to mimic TV pixel blurring
1853            else
1854               c = tmp_col[0];
1855
1856            r = ((c & 0x1f) * fade) >> 4;
1857            g = (((c & 0x3e0) >> 5) * fade) >> 4;
1858            b = (((c & 0x7c00) >> 10) * fade) >> 4;
1859
1860            bitmap.pix32(curline, x * 2 + 0) = rgb_t(pal5bit(r), pal5bit(g), pal5bit(b));
1861            prev_colour = tmp_col[0];
1862
1863            /* average the second pixel if required, or draw it directly*/
1864            if (blurring)
1865               c = (prev_colour + tmp_col[1] - ((prev_colour ^ tmp_col[1]) & 0x0421)) >> 1;    // Hack code to mimic TV pixel blurring
1866            else
1867               c = tmp_col[1];
1868
1869            r = ((c & 0x1f) * fade) >> 4;
1870            g = (((c & 0x3e0) >> 5) * fade) >> 4;
1871            b = (((c & 0x7c00) >> 10) * fade) >> 4;
1872
1873            bitmap.pix32(curline, x * 2 + 1) = rgb_t(pal5bit(r), pal5bit(g), pal5bit(b));
1874            prev_colour = tmp_col[1];
1875         }
1876      }
1877   }
1878
1879   g_profiler.stop();
1880}
1881
1882
1883/* CPU <-> PPU comms */
1884
1885// full graphic variables
1886static const UINT16 vram_fgr_inctab[4] = { 1, 32, 128, 128 };
1887static const UINT16 vram_fgr_inccnts[4] = { 0, 32, 64, 128 };
1888static const UINT16 vram_fgr_shiftab[4] = { 0, 5, 6, 7 };
1889
1890// utility function - latches the H/V counters.  Used by IRQ, writes to WRIO, etc.
1891void snes_ppu_device::latch_counters( running_machine &machine )
1892{
1893   m_beam.current_horz = machine.first_screen()->hpos() / m_htmult;
1894   m_beam.latch_vert = machine.first_screen()->vpos();
1895   m_beam.latch_horz = m_beam.current_horz;
1896   m_stat78 |= 0x40;   // indicate we latched
1897//  m_read_ophct = m_read_opvct = 0;    // clear read flags - 2009-08: I think we must clear these when STAT78 is read...
1898
1899//  printf("latched @ H %d V %d\n", m_beam.latch_horz, m_beam.latch_vert);
1900}
1901
1902void snes_ppu_device::dynamic_res_change( running_machine &machine )
1903{
1904   rectangle visarea = machine.first_screen()->visible_area();
1905   attoseconds_t refresh;
1906
1907   visarea.min_x = visarea.min_y = 0;
1908   visarea.max_y = m_beam.last_visible_line * m_interlace - 1;
1909   visarea.max_x = (SNES_SCR_WIDTH * 2) - 1;
1910
1911   // fixme: should compensate for SNES_DBG_VIDEO
1912   if (m_mode == 5 || m_mode == 6 || m_pseudo_hires)
1913      m_htmult = 2;
1914   else
1915      m_htmult = 1;
1916
1917   /* FIXME: does the timing changes when the gfx mode is equal to 5 or 6? */
1918   if ((m_stat78 & 0x10) == SNES_NTSC)
1919   {
1920      refresh = HZ_TO_ATTOSECONDS(DOTCLK_NTSC) * SNES_HTOTAL * SNES_VTOTAL_NTSC;
1921      machine.first_screen()->configure(SNES_HTOTAL * 2, SNES_VTOTAL_NTSC * m_interlace, visarea, refresh);
1922   }
1923   else
1924   {
1925      refresh = HZ_TO_ATTOSECONDS(DOTCLK_PAL) * SNES_HTOTAL * SNES_VTOTAL_PAL;
1926      machine.first_screen()->configure(SNES_HTOTAL * 2, SNES_VTOTAL_PAL * m_interlace, visarea, refresh);
1927   }
1928}
1929
1930/*************************************************
1931
1932 SNES VRAM accesses:
1933
1934 VRAM accesses during active display are invalid.
1935 Unlike OAM and CGRAM, they will not be written
1936 anywhere at all. Thanks to byuu's researches,
1937 the ranges where writes are invalid have been
1938 validated on hardware, as has the edge case where
1939 the S-CPU open bus can be written if the write
1940 occurs during the very last clock cycle of
1941 vblank.
1942 Our implementation could be not 100% accurate
1943 when interlace is active.
1944*************************************************/
1945
1946inline UINT32 snes_ppu_device::get_vram_address( running_machine &machine )
1947{
1948   UINT32 addr = m_vmadd;
1949
1950   if (m_vram_fgr_count)
1951   {
1952      UINT32 rem = addr & m_vram_fgr_mask;
1953      UINT32 faddr = (addr & ~m_vram_fgr_mask) + (rem >> m_vram_fgr_shift) + ((rem & (m_vram_fgr_count - 1)) << 3);
1954      return faddr << 1;
1955   }
1956
1957   return addr << 1;
1958}
1959
1960READ8_MEMBER( snes_ppu_device::vram_read )
1961{
1962   UINT8 res = 0;
1963   offset &= 0xffff; // only 64KB are present on SNES
1964
1965   if (m_screen_disabled)
1966      res = m_vram[offset];
1967   else
1968   {
1969      UINT16 v = m_screen->vpos();
1970      UINT16 h = m_screen->hpos();
1971      UINT16 ls = (((m_stat78 & 0x10) == SNES_NTSC ? 525 : 625) >> 1) - 1;
1972
1973      if (m_interlace == 2)
1974         ls++;
1975
1976      if (v == ls && h == 1362)
1977         res = 0;
1978      else if (v < m_beam.last_visible_line - 1)
1979         res = 0;
1980      else if (v == m_beam.last_visible_line - 1)
1981      {
1982         if (h == 1362)
1983            res = m_vram[offset];
1984         else
1985         {
1986            //printf("%d %d VRAM read, CHECK!\n",h,v);
1987            res = 0;
1988         }
1989      }
1990      else
1991         res = m_vram[offset];
1992   }
1993   return res;
1994}
1995
1996WRITE8_MEMBER( snes_ppu_device::vram_write )
1997{
1998   offset &= 0xffff; // only 64KB are present on SNES, Robocop 3 relies on this
1999
2000   if (m_screen_disabled)
2001      m_vram[offset] = data;
2002   else
2003   {
2004      UINT16 v = m_screen->vpos();
2005      UINT16 h = m_screen->hpos();
2006      if (v == 0)
2007      {
2008         if (h <= 4)
2009            m_vram[offset] = data;
2010         else if (h == 6)
2011            m_vram[offset] = m_openbus_cb(space, 0);
2012         else
2013         {
2014            //printf("%d %d VRAM write, CHECK!\n",h,v);
2015            //no write
2016         }
2017      }
2018      else if (v < m_beam.last_visible_line)
2019      {
2020         //printf("%d %d VRAM write, CHECK!\n",h,v);
2021         //no write
2022      }
2023      else if (v == m_beam.last_visible_line)
2024      {
2025         if (h <= 4)
2026         {
2027            //printf("%d %d VRAM write, CHECK!\n",h,v);
2028            //no write
2029         }
2030         else
2031            m_vram[offset] = data;
2032      }
2033      else
2034         m_vram[offset] = data;
2035   }
2036}
2037
2038/*************************************************
2039
2040 SNES OAM accesses:
2041
2042 OAM accesses during active display are allowed.
2043 The actual address varies during rendering, as the
2044 PPU reads in data itself for processing.
2045 Unfortunately, no one has been able (yet) to
2046 determine how this works. The only known game to
2047 actually access OAM during active display is
2048 Uniracers and it expects accesses to map to
2049 offset 0x0218. Hence, following byuu's choice
2050 we rerouted OAM accesses during active display
2051 to 0x0218 (0x010c in our snes_oam).
2052 This is a hack, but it is more accurate than
2053 writing to the 'expected' address set by
2054 $2102,$2103.
2055
2056 Notice that, since PPU_REG(OAMDATA) is never
2057 read/written directly, we use it as an index
2058 to choose the high/low byte of the snes_oam word.
2059*************************************************/
2060
2061READ8_MEMBER( snes_ppu_device::oam_read )
2062{
2063   offset &= 0x1ff;
2064
2065   if (offset & 0x100)
2066      offset &= 0x10f;
2067
2068   if (!m_screen_disabled)
2069   {
2070      UINT16 v = m_screen->vpos();
2071
2072      if (v < m_beam.last_visible_line)
2073         offset = 0x010c;
2074   }
2075
2076   return (m_oam_ram[offset] >> (PPU_REG(OAMDATA) << 3)) & 0xff;
2077}
2078
2079WRITE8_MEMBER( snes_ppu_device::oam_write )
2080{
2081   offset &= 0x1ff;
2082
2083   if (offset & 0x100)
2084      offset &= 0x10f;
2085
2086   if (!m_screen_disabled)
2087   {
2088      UINT16 v = m_screen->vpos();
2089
2090      if (v < m_beam.last_visible_line)
2091         offset = 0x010c;
2092   }
2093
2094   if (!(PPU_REG(OAMDATA)))
2095      m_oam_ram[offset] = (m_oam_ram[offset] & 0xff00) | (data << 0);
2096   else
2097      m_oam_ram[offset] = (m_oam_ram[offset] & 0x00ff) | (data << 8);
2098}
2099
2100/*************************************************
2101
2102 SNES CGRAM accesses:
2103
2104 CGRAM writes during hblank are valid. During
2105 active display, the actual address the data
2106 is written to varies, as the PPU itself changes
2107 the address. Like OAM, it is not known the exact
2108 algorithm used, but no commercial software seems
2109 to attempt this. While byuu, in his emu, maps
2110 those accesses to 0x01ff, because it is more
2111 accurate to invalidate the 'expected' address
2112 than not, MESS has issues if we don't write to
2113 the expected address (see e.g. Tokimeki Memorial).
2114 This is because writes should work during hblank
2115 (so that the game can produce color fading), but
2116 ends up not working with the conditions below.
2117 Hence, for the moment, we only document the
2118 solution adopted by BSNES without enabling it.
2119*************************************************/
2120
2121READ8_MEMBER( snes_ppu_device::cgram_read )
2122{
2123   UINT8 res = 0;
2124   offset &= 0x1ff;
2125
2126#if 0
2127   if (!m_screen_disabled)
2128   {
2129      UINT16 v = m_screen->vpos();
2130      UINT16 h = m_screen->hpos();
2131
2132      if (v < m_beam.last_visible_line && h >= 128 && h < 1096)
2133         offset = 0x1ff;
2134   }
2135#endif
2136
2137   res = ((UINT8 *)m_cgram)[offset];
2138
2139   // CGRAM palette data format is 15-bits (0,bbbbb,ggggg,rrrrr).
2140   // Highest bit is simply ignored.
2141   if (offset & 0x01)
2142      res &= 0x7f;
2143
2144   return res;
2145}
2146
2147WRITE8_MEMBER( snes_ppu_device::cgram_write )
2148{
2149   offset &= 0x1ff;
2150
2151#if 0
2152   // FIXME: this currently breaks some games (e.g. Tokimeki Memorial),
2153   // even if it's expected to be more accurate than allowing for
2154   // writes to the cgram address
2155   if (!m_screen_disabled)
2156   {
2157      UINT16 v = m_screen->vpos();
2158      UINT16 h = m_screen->hpos();
2159
2160      if (v < m_beam.last_visible_line && h >= 128 && h < 1096)
2161         offset = 0x1ff;
2162   }
2163#endif
2164
2165   // CGRAM palette data format is 15-bits (0,bbbbb,ggggg,rrrrr).
2166   // Highest bit is simply ignored.
2167   if (offset & 0x01)
2168      data &= 0x7f;
2169
2170   ((UINT8 *)m_cgram)[offset] = data;
2171}
2172
2173UINT8 snes_ppu_device::read(address_space &space, UINT32 offset, UINT8 wrio_bit7)
2174{
2175   UINT8 value;
2176
2177   switch (offset)
2178   {
2179      case OAMDATA:   /* 21xy for x=0,1,2 and y=4,5,6,8,9,a returns PPU1 open bus*/
2180      case BGMODE:
2181      case MOSAIC:
2182      case BG2SC:
2183      case BG3SC:
2184      case BG4SC:
2185      case BG4VOFS:
2186      case VMAIN:
2187      case VMADDL:
2188      case VMDATAL:
2189      case VMDATAH:
2190      case M7SEL:
2191      case W34SEL:
2192      case WOBJSEL:
2193      case WH0:
2194      case WH2:
2195      case WH3:
2196      case WBGLOG:
2197         return m_ppu1_open_bus;
2198
2199      case MPYL:      /* Multiplication result (low) */
2200         {
2201            /* Perform 16bit * 8bit multiply */
2202            UINT32 c = (INT16)m_mode7.matrix_a * (INT8)(m_mode7.matrix_b >> 8);
2203            m_ppu1_open_bus = c & 0xff;
2204            return m_ppu1_open_bus;
2205         }
2206      case MPYM:      /* Multiplication result (mid) */
2207         {
2208            /* Perform 16bit * 8bit multiply */
2209            UINT32 c = (INT16)m_mode7.matrix_a * (INT8)(m_mode7.matrix_b >> 8);
2210            m_ppu1_open_bus = (c >> 8) & 0xff;
2211            return m_ppu1_open_bus;
2212         }
2213      case MPYH:      /* Multiplication result (high) */
2214         {
2215            /* Perform 16bit * 8bit multiply */
2216            UINT32 c = (INT16)m_mode7.matrix_a * (INT8)(m_mode7.matrix_b >> 8);
2217            m_ppu1_open_bus = (c >> 16) & 0xff;
2218            return m_ppu1_open_bus;
2219         }
2220      case SLHV:      /* Software latch for H/V counter */
2221         latch_counters(space.machine());
2222         return m_openbus_cb(space, 0);       /* Return value is meaningless */
2223
2224      case ROAMDATA:  /* Read data from OAM (DR) */
2225         m_ppu1_open_bus = oam_read(space, m_oam.address);
2226         PPU_REG(OAMDATA) = (PPU_REG(OAMDATA) + 1) % 2;
2227         if (!PPU_REG(OAMDATA))
2228         {
2229            m_oam.address++;
2230            m_oam.address &= 0x1ff;
2231            m_oam.first_sprite = m_oam.priority_rotation ? (m_oam.address >> 1) & 127 : 0;
2232         }
2233         return m_ppu1_open_bus;
2234      case RVMDATAL:  /* Read data from VRAM (low) */
2235         {
2236            UINT32 addr = get_vram_address(space.machine());
2237            m_ppu1_open_bus = m_vram_read_buffer & 0xff;
2238
2239            if (!m_vram_fgr_high)
2240            {
2241               m_vram_read_buffer = vram_read(space, addr);
2242               m_vram_read_buffer |= (vram_read(space, addr + 1) << 8);
2243
2244               m_vmadd = (m_vmadd + m_vram_fgr_increment) & 0xffff;
2245            }
2246
2247            return m_ppu1_open_bus;
2248         }
2249      case RVMDATAH:  /* Read data from VRAM (high) */
2250         {
2251            UINT32 addr = get_vram_address(space.machine());
2252            m_ppu1_open_bus = (m_vram_read_buffer >> 8) & 0xff;
2253
2254            if (m_vram_fgr_high)
2255            {
2256               m_vram_read_buffer = vram_read(space, addr);
2257               m_vram_read_buffer |= (vram_read(space, addr + 1) << 8);
2258
2259               m_vmadd = (m_vmadd + m_vram_fgr_increment) & 0xffff;
2260            }
2261
2262            return m_ppu1_open_bus;
2263         }
2264      case RCGDATA:   /* Read data from CGRAM */
2265         if (!(m_cgram_address & 0x01))
2266            m_ppu2_open_bus = cgram_read(space, m_cgram_address);
2267         else
2268         {
2269            m_ppu2_open_bus &= 0x80;
2270            m_ppu2_open_bus |= cgram_read(space, m_cgram_address) & 0x7f;
2271         }
2272
2273         m_cgram_address = (m_cgram_address + 1) % (SNES_CGRAM_SIZE - 2);
2274         return m_ppu2_open_bus;
2275      case OPHCT:     /* Horizontal counter data by ext/soft latch */
2276         if (m_read_ophct)
2277         {
2278            m_ppu2_open_bus &= 0xfe;
2279            m_ppu2_open_bus |= (m_beam.latch_horz >> 8) & 0x01;
2280         }
2281         else
2282         {
2283            m_ppu2_open_bus = m_beam.latch_horz & 0xff;
2284         }
2285         m_read_ophct ^= 1;
2286         return m_ppu2_open_bus;
2287      case OPVCT:     /* Vertical counter data by ext/soft latch */
2288         if (m_read_opvct)
2289         {
2290            m_ppu2_open_bus &= 0xfe;
2291            m_ppu2_open_bus |= (m_beam.latch_vert >> 8) & 0x01;
2292         }
2293         else
2294         {
2295            m_ppu2_open_bus = m_beam.latch_vert & 0xff;
2296         }
2297         m_read_opvct ^= 1;
2298         return m_ppu2_open_bus;
2299      case STAT77:    /* PPU status flag and version number */
2300         value = m_stat77 & 0xc0; // 0x80 & 0x40 are Time Over / Range Over Sprite flags, set by the video code
2301         // 0x20 - Master/slave mode select. Little is known about this bit. We always seem to read back 0 here.
2302         value |= (m_ppu1_open_bus & 0x10);
2303         value |= (m_ppu1_version & 0x0f);
2304         m_stat77 = value;  // not sure if this is needed...
2305         m_ppu1_open_bus = value;
2306         return m_ppu1_open_bus;
2307      case STAT78:    /* PPU status flag and version number */
2308         m_read_ophct = 0;
2309         m_read_opvct = 0;
2310         if (wrio_bit7)
2311            m_stat78 &= ~0x40; //clear ext latch if bit 7 of WRIO is set
2312         m_stat78 = (m_stat78 & ~0x2f) | (m_ppu2_open_bus & 0x20) | (m_ppu2_version & 0x0f);
2313         m_ppu2_open_bus = m_stat78;
2314         return m_ppu2_open_bus;
2315   }
2316
2317   /* note: remaining registers (Namely TM in Super Kick Boxing) returns MDR open bus, not PPU Open Bus! */
2318   return m_openbus_cb(space, 0);
2319}
2320
2321
2322void snes_ppu_device::write(address_space &space, UINT32 offset, UINT8 data)
2323{
2324   switch (offset)
2325   {
2326      case INIDISP:   /* Initial settings for screen */
2327         if ((m_screen_disabled & 0x80) && (!(data & 0x80))) //a 1->0 force blank transition causes a reset OAM address
2328         {
2329            space.write_byte(OAMADDL, m_oam.saved_address_low);
2330            space.write_byte(OAMADDH, m_oam.saved_address_high);
2331            m_oam.first_sprite = m_oam.priority_rotation ? (m_oam.address >> 1) & 127 : 0;
2332         }
2333         m_screen_disabled = data & 0x80;
2334         m_screen_brightness = (data & 0x0f) + 1;
2335         break;
2336      case OBSEL:     /* Object size and data area designation */
2337         m_oam.next_charmap = (data & 0x03) << 1;
2338         m_oam.next_name_select = (((data & 0x18) >> 3) * 0x1000) << 1;
2339         m_oam.next_size = (data & 0xe0) >> 5;
2340         break;
2341      case OAMADDL:   /* Address for accessing OAM (low) */
2342         m_oam.saved_address_low = data;
2343         m_oam.address = (m_oam.address & 0xff00) + data;
2344         m_oam.first_sprite = m_oam.priority_rotation ? (m_oam.address >> 1) & 127 : 0;
2345         PPU_REG(OAMDATA) = 0;
2346         break;
2347      case OAMADDH:   /* Address for accessing OAM (high) */
2348         m_oam.saved_address_high = data;
2349         m_oam.address = (m_oam.address & 0x00ff) | ((data & 0x01) << 8);
2350         m_oam.priority_rotation = BIT(data, 7);
2351         m_oam.first_sprite = m_oam.priority_rotation ? (m_oam.address >> 1) & 127 : 0;
2352         PPU_REG(OAMDATA) = 0;
2353         break;
2354      case OAMDATA:   /* Data for OAM write (DW) */
2355         if (m_oam.address >= 0x100)
2356            oam_write(space, m_oam.address, data);
2357         else
2358         {
2359            if (!PPU_REG(OAMDATA))
2360               m_oam.write_latch = data;
2361            else
2362            {
2363               // in this case, we not only write data to the upper byte of the word,
2364               // but also m_oam.write_latch to the lower byte (recall that
2365               // PPU_REG(OAMDATA) is used to select high/low byte)
2366               oam_write(space, m_oam.address, data);
2367               PPU_REG(OAMDATA) = 0;
2368               oam_write(space, m_oam.address, m_oam.write_latch);
2369               PPU_REG(OAMDATA) = 1;
2370            }
2371         }
2372         PPU_REG(OAMDATA) = (PPU_REG(OAMDATA) + 1) % 2;
2373         if (!PPU_REG(OAMDATA))
2374         {
2375            m_oam.address++;
2376            m_oam.address &= 0x1ff;
2377            m_oam.first_sprite = m_oam.priority_rotation ? (m_oam.address >> 1) & 127 : 0;
2378         }
2379         return;
2380      case BGMODE:    /* BG mode and character size settings */
2381         m_mode = data & 0x07;
2382         dynamic_res_change(space.machine());
2383         m_bg3_priority_bit = BIT(data, 3);
2384         m_layer[SNES_BG1].tile_size = BIT(data, 4);
2385         m_layer[SNES_BG2].tile_size = BIT(data, 5);
2386         m_layer[SNES_BG3].tile_size = BIT(data, 6);
2387         m_layer[SNES_BG4].tile_size = BIT(data, 7);
2388         m_update_offsets = 1;
2389         break;
2390      case MOSAIC:    /* Size and screen designation for mosaic */
2391         m_mosaic_size = (data & 0xf0) >> 4;
2392         m_layer[SNES_BG1].mosaic_enabled = BIT(data, 0);
2393         m_layer[SNES_BG2].mosaic_enabled = BIT(data, 1);
2394         m_layer[SNES_BG3].mosaic_enabled = BIT(data, 2);
2395         m_layer[SNES_BG4].mosaic_enabled = BIT(data, 3);
2396         break;
2397      case BG1SC:     /* Address for storing SC data BG1 SC size designation */
2398      case BG2SC:     /* Address for storing SC data BG2 SC size designation  */
2399      case BG3SC:     /* Address for storing SC data BG3 SC size designation  */
2400      case BG4SC:     /* Address for storing SC data BG4 SC size designation  */
2401         m_layer[offset - BG1SC].tilemap = data & 0xfc;
2402         m_layer[offset - BG1SC].tilemap_size = data & 0x3;
2403         break;
2404      case BG12NBA:   /* Address for BG 1 and 2 character data */
2405         m_layer[SNES_BG1].charmap = (data & 0x0f);
2406         m_layer[SNES_BG2].charmap = (data & 0xf0) >> 4;
2407         break;
2408      case BG34NBA:   /* Address for BG 3 and 4 character data */
2409         m_layer[SNES_BG3].charmap = (data & 0x0f);
2410         m_layer[SNES_BG4].charmap = (data & 0xf0) >> 4;
2411         break;
2412
2413      // Anomie says "H Current = (Byte<<8) | (Prev&~7) | ((Current>>8)&7); V Current = (Current<<8) | Prev;" and Prev is shared by all scrolls but in Mode 7!
2414      case BG1HOFS:   /* BG1 - horizontal scroll (DW) */
2415         /* In Mode 0->6 we use ppu_last_scroll as Prev */
2416         m_layer[SNES_BG1].hoffs = (data << 8) | (m_ppu_last_scroll & ~7) | ((m_layer[SNES_BG1].hoffs >> 8) & 7);
2417         m_ppu_last_scroll = data;
2418         /* In Mode 7 we use mode7_last_scroll as Prev */
2419         m_mode7.hor_offset = (data << 8) | (m_mode7_last_scroll & ~7) | ((m_mode7.hor_offset >> 8) & 7);
2420         m_mode7_last_scroll = data;
2421         m_update_offsets = 1;
2422         return;
2423      case BG1VOFS:   /* BG1 - vertical scroll (DW) */
2424         /* In Mode 0->6 we use ppu_last_scroll as Prev */
2425         m_layer[SNES_BG1].voffs = (data << 8) | m_ppu_last_scroll;
2426         m_ppu_last_scroll = data;
2427         /* In Mode 7 we use mode7_last_scroll as Prev */
2428         m_mode7.ver_offset = (data << 8) | m_mode7_last_scroll;
2429         m_mode7_last_scroll = data;
2430         m_update_offsets = 1;
2431         return;
2432      case BG2HOFS:   /* BG2 - horizontal scroll (DW) */
2433         m_layer[SNES_BG2].hoffs = (data << 8) | (m_ppu_last_scroll & ~7) | ((m_layer[SNES_BG2].hoffs >> 8) & 7);
2434         m_ppu_last_scroll = data;
2435         m_update_offsets = 1;
2436         return;
2437      case BG2VOFS:   /* BG2 - vertical scroll (DW) */
2438         m_layer[SNES_BG2].voffs = (data << 8) | (m_ppu_last_scroll);
2439         m_ppu_last_scroll = data;
2440         m_update_offsets = 1;
2441         return;
2442      case BG3HOFS:   /* BG3 - horizontal scroll (DW) */
2443         m_layer[SNES_BG3].hoffs = (data << 8) | (m_ppu_last_scroll & ~7) | ((m_layer[SNES_BG3].hoffs >> 8) & 7);
2444         m_ppu_last_scroll = data;
2445         m_update_offsets = 1;
2446         return;
2447      case BG3VOFS:   /* BG3 - vertical scroll (DW) */
2448         m_layer[SNES_BG3].voffs = (data << 8) | (m_ppu_last_scroll);
2449         m_ppu_last_scroll = data;
2450         m_update_offsets = 1;
2451         return;
2452      case BG4HOFS:   /* BG4 - horizontal scroll (DW) */
2453         m_layer[SNES_BG4].hoffs = (data << 8) | (m_ppu_last_scroll & ~7) | ((m_layer[SNES_BG4].hoffs >> 8) & 7);
2454         m_ppu_last_scroll = data;
2455         m_update_offsets = 1;
2456         return;
2457      case BG4VOFS:   /* BG4 - vertical scroll (DW) */
2458         m_layer[SNES_BG4].voffs = (data << 8) | (m_ppu_last_scroll);
2459         m_ppu_last_scroll = data;
2460         m_update_offsets = 1;
2461         return;
2462      case VMAIN:     /* VRAM address increment value designation */
2463         m_vram_fgr_high = (data & 0x80);
2464         m_vram_fgr_increment = vram_fgr_inctab[data & 3];
2465
2466         if (data & 0xc)
2467         {
2468            int md = (data & 0xc) >> 2;
2469
2470            m_vram_fgr_count = vram_fgr_inccnts[md];         // 0x20, 0x40, 0x80
2471            m_vram_fgr_mask = (m_vram_fgr_count * 8) - 1; // 0xff, 0x1ff, 0x2ff
2472            m_vram_fgr_shift = vram_fgr_shiftab[md];         // 5, 6, 7
2473         }
2474         else
2475         {
2476            m_vram_fgr_count = 0;
2477         }
2478//          printf("VMAIN: high %x inc %x count %x mask %x shift %x\n", m_vram_fgr_high, m_vram_fgr_increment, m_vram_fgr_count, m_vram_fgr_mask, m_vram_fgr_shift);
2479         break;
2480      case VMADDL:    /* Address for VRAM read/write (low) */
2481         {
2482            UINT32 addr;
2483            m_vmadd = (m_vmadd & 0xff00) | (data << 0);
2484            addr = get_vram_address(space.machine());
2485            m_vram_read_buffer = vram_read(space, addr);
2486            m_vram_read_buffer |= (vram_read(space, addr + 1) << 8);
2487         }
2488         break;
2489      case VMADDH:    /* Address for VRAM read/write (high) */
2490         {
2491            UINT32 addr;
2492            m_vmadd = (m_vmadd & 0x00ff) | (data << 8);
2493            addr = get_vram_address(space.machine());
2494            m_vram_read_buffer = vram_read(space, addr);
2495            m_vram_read_buffer |= (vram_read(space, addr + 1) << 8);
2496         }
2497         break;
2498      case VMDATAL:   /* 2118: Data for VRAM write (low) */
2499         {
2500            UINT32 addr = get_vram_address(space.machine());
2501            vram_write(space, addr, data);
2502
2503            if (!m_vram_fgr_high)
2504               m_vmadd = (m_vmadd + m_vram_fgr_increment) & 0xffff;
2505         }
2506         return;
2507      case VMDATAH:   /* 2119: Data for VRAM write (high) */
2508         {
2509            UINT32 addr = get_vram_address(space.machine());
2510            vram_write(space, addr + 1, data);
2511
2512            if (m_vram_fgr_high)
2513               m_vmadd = (m_vmadd + m_vram_fgr_increment) & 0xffff;
2514         }
2515         return;
2516      case M7SEL:     /* Mode 7 initial settings */
2517         m_mode7.repeat = (data >> 6) & 3;
2518         m_mode7.vflip  = BIT(data, 1);
2519         m_mode7.hflip  = BIT(data, 0);
2520         break;
2521      /* As per Anomie's doc: Reg = (Current<<8) | Prev; and there is only one Prev, shared by these matrix regs and Mode 7 scroll regs */
2522      case M7A:       /* Mode 7 COS angle/x expansion (DW) */
2523         m_mode7.matrix_a = m_mode7_last_scroll + (data << 8);
2524         m_mode7_last_scroll = data;
2525         break;
2526      case M7B:       /* Mode 7 SIN angle/ x expansion (DW) */
2527         m_mode7.matrix_b = m_mode7_last_scroll + (data << 8);
2528         m_mode7_last_scroll = data;
2529         break;
2530      case M7C:       /* Mode 7 SIN angle/y expansion (DW) */
2531         m_mode7.matrix_c = m_mode7_last_scroll + (data << 8);
2532         m_mode7_last_scroll = data;
2533         break;
2534      case M7D:       /* Mode 7 COS angle/y expansion (DW) */
2535         m_mode7.matrix_d = m_mode7_last_scroll + (data << 8);
2536         m_mode7_last_scroll = data;
2537         break;
2538      case M7X:       /* Mode 7 x center position (DW) */
2539         m_mode7.origin_x = m_mode7_last_scroll + (data << 8);
2540         m_mode7_last_scroll = data;
2541         break;
2542      case M7Y:       /* Mode 7 y center position (DW) */
2543         m_mode7.origin_y = m_mode7_last_scroll + (data << 8);
2544         m_mode7_last_scroll = data;
2545         break;
2546      case CGADD:     /* Initial address for colour RAM writing */
2547         /* CGRAM is 16-bit, but when reading/writing we treat it as 8-bit, so we need to double the address */
2548         m_cgram_address = data << 1;
2549         break;
2550      case CGDATA:    /* Data for colour RAM */
2551         cgram_write(space, m_cgram_address, data);
2552         m_cgram_address = (m_cgram_address + 1) % (SNES_CGRAM_SIZE - 2);
2553         break;
2554      case W12SEL:    /* Window mask settings for BG1-2 */
2555         if (data != PPU_REG(W12SEL))
2556         {
2557            m_layer[SNES_BG1].window1_invert  = BIT(data, 0);
2558            m_layer[SNES_BG1].window1_enabled = BIT(data, 1);
2559            m_layer[SNES_BG1].window2_invert  = BIT(data, 2);
2560            m_layer[SNES_BG1].window2_enabled = BIT(data, 3);
2561            m_layer[SNES_BG2].window1_invert  = BIT(data, 4);
2562            m_layer[SNES_BG2].window1_enabled = BIT(data, 5);
2563            m_layer[SNES_BG2].window2_invert  = BIT(data, 6);
2564            m_layer[SNES_BG2].window2_enabled = BIT(data, 7);
2565            m_update_windows = 1;
2566         }
2567         break;
2568      case W34SEL:    /* Window mask settings for BG3-4 */
2569         if (data != PPU_REG(W34SEL))
2570         {
2571            m_layer[SNES_BG3].window1_invert  = BIT(data, 0);
2572            m_layer[SNES_BG3].window1_enabled = BIT(data, 1);
2573            m_layer[SNES_BG3].window2_invert  = BIT(data, 2);
2574            m_layer[SNES_BG3].window2_enabled = BIT(data, 3);
2575            m_layer[SNES_BG4].window1_invert  = BIT(data, 4);
2576            m_layer[SNES_BG4].window1_enabled = BIT(data, 5);
2577            m_layer[SNES_BG4].window2_invert  = BIT(data, 6);
2578            m_layer[SNES_BG4].window2_enabled = BIT(data, 7);
2579            m_update_windows = 1;
2580         }
2581         break;
2582      case WOBJSEL:   /* Window mask settings for objects */
2583         if (data != PPU_REG(WOBJSEL))
2584         {
2585            m_layer[SNES_OAM].window1_invert  = BIT(data, 0);
2586            m_layer[SNES_OAM].window1_enabled = BIT(data, 1);
2587            m_layer[SNES_OAM].window2_invert  = BIT(data, 2);
2588            m_layer[SNES_OAM].window2_enabled = BIT(data, 3);
2589            m_layer[SNES_COLOR].window1_invert  = BIT(data, 4);
2590            m_layer[SNES_COLOR].window1_enabled = BIT(data, 5);
2591            m_layer[SNES_COLOR].window2_invert  = BIT(data, 6);
2592            m_layer[SNES_COLOR].window2_enabled = BIT(data, 7);
2593            m_update_windows = 1;
2594         }
2595         break;
2596      case WH0:       /* Window 1 left position */
2597         if (data != PPU_REG(WH0))
2598         {
2599            m_window1_left = data;
2600            m_update_windows = 1;
2601         }
2602         break;
2603      case WH1:       /* Window 1 right position */
2604         if (data != PPU_REG(WH1))
2605         {
2606            m_window1_right = data;
2607            m_update_windows = 1;
2608         }
2609         break;
2610      case WH2:       /* Window 2 left position */
2611         if (data != PPU_REG(WH2))
2612         {
2613            m_window2_left = data;
2614            m_update_windows = 1;
2615         }
2616         break;
2617      case WH3:       /* Window 2 right position */
2618         if (data != PPU_REG(WH3))
2619         {
2620            m_window2_right = data;
2621            m_update_windows = 1;
2622         }
2623         break;
2624      case WBGLOG:    /* Window mask logic for BG's */
2625         if (data != PPU_REG(WBGLOG))
2626         {
2627            m_layer[SNES_BG1].wlog_mask = data & 0x03;
2628            m_layer[SNES_BG2].wlog_mask = (data & 0x0c) >> 2;
2629            m_layer[SNES_BG3].wlog_mask = (data & 0x30) >> 4;
2630            m_layer[SNES_BG4].wlog_mask = (data & 0xc0) >> 6;
2631            m_update_windows = 1;
2632         }
2633         break;
2634      case WOBJLOG:   /* Window mask logic for objects */
2635         if (data != PPU_REG(WOBJLOG))
2636         {
2637            m_layer[SNES_OAM].wlog_mask = data & 0x03;
2638            m_layer[SNES_COLOR].wlog_mask = (data & 0x0c) >> 2;
2639            m_update_windows = 1;
2640         }
2641         break;
2642      case TM:        /* Main screen designation */
2643         m_layer[SNES_BG1].main_bg_enabled = BIT(data, 0);
2644         m_layer[SNES_BG2].main_bg_enabled = BIT(data, 1);
2645         m_layer[SNES_BG3].main_bg_enabled = BIT(data, 2);
2646         m_layer[SNES_BG4].main_bg_enabled = BIT(data, 3);
2647         m_layer[SNES_OAM].main_bg_enabled = BIT(data, 4);
2648         break;
2649      case TS:        /* Subscreen designation */
2650         m_layer[SNES_BG1].sub_bg_enabled = BIT(data, 0);
2651         m_layer[SNES_BG2].sub_bg_enabled = BIT(data, 1);
2652         m_layer[SNES_BG3].sub_bg_enabled = BIT(data, 2);
2653         m_layer[SNES_BG4].sub_bg_enabled = BIT(data, 3);
2654         m_layer[SNES_OAM].sub_bg_enabled = BIT(data, 4);
2655         break;
2656      case TMW:       /* Window mask for main screen designation */
2657         m_layer[SNES_BG1].main_window_enabled = BIT(data, 0);
2658         m_layer[SNES_BG2].main_window_enabled = BIT(data, 1);
2659         m_layer[SNES_BG3].main_window_enabled = BIT(data, 2);
2660         m_layer[SNES_BG4].main_window_enabled = BIT(data, 3);
2661         m_layer[SNES_OAM].main_window_enabled = BIT(data, 4);
2662         break;
2663      case TSW:       /* Window mask for subscreen designation */
2664         m_layer[SNES_BG1].sub_window_enabled = BIT(data, 0);
2665         m_layer[SNES_BG2].sub_window_enabled = BIT(data, 1);
2666         m_layer[SNES_BG3].sub_window_enabled = BIT(data, 2);
2667         m_layer[SNES_BG4].sub_window_enabled = BIT(data, 3);
2668         m_layer[SNES_OAM].sub_window_enabled = BIT(data, 4);
2669         break;
2670      case CGWSEL:    /* Initial settings for Fixed colour addition or screen addition */
2671         m_clip_to_black = (data >> 6) & 0x03;
2672         m_prevent_color_math = (data >> 4) & 0x03;
2673         m_sub_add_mode = BIT(data, 1);
2674         m_direct_color = BIT(data, 0);
2675#ifdef SNES_DBG_REG_W
2676         if ((data & 0x2) != (PPU_REG(CGWSEL) & 0x2))
2677            mame_printf_debug("Add/Sub Layer: %s\n", ((data & 0x2) >> 1) ? "Subscreen" : "Fixed colour");
2678#endif
2679         break;
2680      case CGADSUB:   /* Addition/Subtraction designation for each screen */
2681         m_color_modes = data & 0xc0;
2682         m_layer[SNES_BG1].color_math = BIT(data, 0);
2683         m_layer[SNES_BG2].color_math = BIT(data, 1);
2684         m_layer[SNES_BG3].color_math = BIT(data, 2);
2685         m_layer[SNES_BG4].color_math = BIT(data, 3);
2686         m_layer[SNES_OAM].color_math = BIT(data, 4);
2687         m_layer[SNES_COLOR].color_math = BIT(data, 5);
2688         break;
2689      case COLDATA:   /* Fixed colour data for fixed colour addition/subtraction */
2690         {
2691            /* Store it in the extra space we made in the CGRAM. It doesn't really go there, but it's as good a place as any. */
2692            UINT8 r, g, b;
2693
2694            /* Get existing value. */
2695            r = m_cgram[FIXED_COLOUR] & 0x1f;
2696            g = (m_cgram[FIXED_COLOUR] & 0x3e0) >> 5;
2697            b = (m_cgram[FIXED_COLOUR] & 0x7c00) >> 10;
2698            /* Set new value */
2699            if (data & 0x20)
2700               r = data & 0x1f;
2701            if (data & 0x40)
2702               g = data & 0x1f;
2703            if (data & 0x80)
2704               b = data & 0x1f;
2705            m_cgram[FIXED_COLOUR] = (r | (g << 5) | (b << 10));
2706         } break;
2707      case SETINI:    /* Screen mode/video select */
2708         m_interlace = (data & 0x01) ? 2 : 1;
2709         m_obj_interlace = (data & 0x02) ? 2 : 1;
2710         m_beam.last_visible_line = (data & 0x04) ? 240 : 225;
2711         m_pseudo_hires = BIT(data, 3);
2712         m_mode7.extbg = BIT(data, 6);
2713         dynamic_res_change(space.machine());
2714#ifdef SNES_DBG_REG_W
2715         if ((data & 0x8) != (PPU_REG(SETINI) & 0x8))
2716            mame_printf_debug("Pseudo 512 mode: %s\n", (data & 0x8) ? "on" : "off");
2717#endif
2718         break;
2719      }
2720
2721   PPU_REG(offset) = data;
2722}
2723
2724/***** Debug Functions *****/
2725
2726#if SNES_LAYER_DEBUG
2727
2728#define DEBUG_TOGGLE(bit, debug_settings, MSG1, MSG2) \
2729   if (BIT(toggles, bit) && !debug_settings)       \
2730   {                                               \
2731      debug_settings = 1;                       \
2732      popmessage MSG1;                          \
2733   }                                               \
2734   else if (!BIT(toggles, bit) && debug_settings)  \
2735   {                                               \
2736      debug_settings = 0;                       \
2737      popmessage MSG2;                          \
2738   }
2739
2740UINT8 snes_ppu_device::dbg_video( running_machine &machine, UINT16 curline )
2741{
2742   int i;
2743   UINT8 toggles = machine.root_device().ioport("DEBUG1")->read_safe(0);
2744   m_debug_options.select_pri[SNES_BG1] = (toggles & 0x03);
2745   m_debug_options.select_pri[SNES_BG2] = (toggles & 0x0c) >> 2;
2746   m_debug_options.select_pri[SNES_BG3] = (toggles & 0x30) >> 4;
2747   m_debug_options.select_pri[SNES_BG4] = (toggles & 0xc0) >> 6;
2748
2749   toggles = machine.root_device().ioport("DEBUG2")->read_safe(0);
2750   for (i = 0; i < 4; i++)
2751      DEBUG_TOGGLE(i, m_debug_options.bg_disabled[i], ("Debug: Disabled BG%d.\n", i + 1), ("Debug: Enabled BG%d.\n", i + 1))
2752   DEBUG_TOGGLE(4, m_debug_options.bg_disabled[SNES_OAM], ("Debug: Disabled OAM.\n"), ("Debug: Enabled OAM.\n"))
2753   DEBUG_TOGGLE(5, m_debug_options.draw_subscreen, ("Debug: Switched screens.\n"), ("Debug: Switched screens.\n"))
2754   DEBUG_TOGGLE(6, m_debug_options.colormath_disabled, ("Debug: Disabled Color Math.\n"), ("Debug: Enabled Color Math.\n"))
2755   DEBUG_TOGGLE(7, m_debug_options.windows_disabled, ("Debug: Disabled Window Masks.\n"), ("Debug: Enabled Window Masks.\n"))
2756
2757   toggles = machine.root_device().ioport("DEBUG4")->read_safe(0);
2758   for (i = 0; i < 8; i++)
2759      DEBUG_TOGGLE(i, m_debug_options.mode_disabled[i], ("Debug: Disabled Mode %d drawing.\n", i), ("Debug: Enabled Mode %d drawing.\n", i))
2760
2761   toggles = machine.root_device().ioport("DEBUG3")->read_safe(0);
2762   DEBUG_TOGGLE(2, m_debug_options.mosaic_disabled, ("Debug: Disabled Mosaic.\n"), ("Debug: Enabled Mosaic.\n"))
2763   m_debug_options.sprite_reversed = BIT(toggles, 7);
2764   m_debug_options.select_pri[SNES_OAM] = (toggles & 0x70) >> 4;
2765
2766#ifdef MAME_DEBUG
2767   /* Once per frame, log video properties */
2768   if (curline == 1)
2769   {
2770      static const char WINLOGIC[4] = { '|', '&', '^', '!' };
2771
2772      logerror("%s", m_debug_options.windows_disabled?" ":"W");
2773      logerror("%s1 %s%s%s%s%s%c%s%s%d%s %d %4X %4X",
2774            m_debug_options.bg_disabled[0]?" ":"*",
2775            (PPU_REG(TM) & 0x1)?"M":" ",
2776            (PPU_REG(TS) & 0x1)?"S":" ",
2777            (PPU_REG(CGADSUB) & 0x1)?"B":" ",
2778            (PPU_REG(TMW) & 0x1)?"m":" ",
2779            (PPU_REG(TSW) & 0x1)?"s":" ",
2780            WINLOGIC[(PPU_REG(WBGLOG) & 0x3)],
2781            (PPU_REG(W12SEL) & 0x2)?((PPU_REG(W12SEL) & 0x1)?"o":"i"):" ",
2782            (PPU_REG(W12SEL) & 0x8)?((PPU_REG(W12SEL) & 0x4)?"o":"i"):" ",
2783            m_layer[SNES_BG1].tile_size + 1,
2784            (PPU_REG(MOSAIC) & 0x1)?"m":" ",
2785            PPU_REG(BG1SC) & 0x3,
2786            (PPU_REG(BG1SC) & 0xfc) << 9,
2787            m_layer[SNES_BG1].charmap << 13);
2788      logerror("%s2 %s%s%s%s%s%c%s%s%d%s %d %4X %4X",
2789            m_debug_options.bg_disabled[1]?" ":"*",
2790            (PPU_REG(TM) & 0x2)?"M":" ",
2791            (PPU_REG(TS) & 0x2)?"S":" ",
2792            (PPU_REG(CGADSUB) & 0x2)?"B":" ",
2793            (PPU_REG(TMW) & 0x2)?"m":" ",
2794            (PPU_REG(TSW) & 0x2)?"s":" ",
2795            WINLOGIC[(PPU_REG(WBGLOG) & 0xc) >> 2],
2796            (PPU_REG(W12SEL) & 0x20)?((PPU_REG(W12SEL) & 0x10)?"o":"i"):" ",
2797            (PPU_REG(W12SEL) & 0x80)?((PPU_REG(W12SEL) & 0x40)?"o":"i"):" ",
2798            m_layer[SNES_BG2].tile_size + 1,
2799            (PPU_REG(MOSAIC) & 0x2)?"m":" ",
2800            PPU_REG(BG2SC) & 0x3,
2801            (PPU_REG(BG2SC) & 0xfc) << 9,
2802            m_layer[SNES_BG2].charmap << 13);
2803      logerror("%s3 %s%s%s%s%s%c%s%s%d%s%s%d %4X %4X",
2804            m_debug_options.bg_disabled[2]?" ":"*",
2805            (PPU_REG(TM) & 0x4)?"M":" ",
2806            (PPU_REG(TS) & 0x4)?"S":" ",
2807            (PPU_REG(CGADSUB) & 0x4)?"B":" ",
2808            (PPU_REG(TMW) & 0x4)?"m":" ",
2809            (PPU_REG(TSW) & 0x4)?"s":" ",
2810            WINLOGIC[(PPU_REG(WBGLOG) & 0x30)>>4],
2811            (PPU_REG(W34SEL) & 0x2)?((PPU_REG(W34SEL) & 0x1)?"o":"i"):" ",
2812            (PPU_REG(W34SEL) & 0x8)?((PPU_REG(W34SEL) & 0x4)?"o":"i"):" ",
2813            m_layer[SNES_BG3].tile_size + 1,
2814            (PPU_REG(MOSAIC) & 0x4)?"m":" ",
2815            (PPU_REG(BGMODE) & 0x8)?"P":" ",
2816            PPU_REG(BG3SC) & 0x3,
2817            (PPU_REG(BG3SC) & 0xfc) << 9,
2818            m_layer[SNES_BG3].charmap << 13);
2819      logerror("%s4 %s%s%s%s%s%c%s%s%d%s %d %4X %4X",
2820            m_debug_options.bg_disabled[3]?" ":"*",
2821            (PPU_REG(TM) & 0x8)?"M":" ",
2822            (PPU_REG(TS) & 0x8)?"S":" ",
2823            (PPU_REG(CGADSUB) & 0x8)?"B":" ",
2824            (PPU_REG(TMW) & 0x8)?"m":" ",
2825            (PPU_REG(TSW) & 0x8)?"s":" ",
2826            WINLOGIC[(PPU_REG(WBGLOG) & 0xc0)>>6],
2827            (PPU_REG(W34SEL) & 0x20)?((PPU_REG(W34SEL) & 0x10)?"o":"i"):" ",
2828            (PPU_REG(W34SEL) & 0x80)?((PPU_REG(W34SEL) & 0x40)?"o":"i"):" ",
2829            m_layer[SNES_BG4].tile_size + 1,
2830            (PPU_REG(MOSAIC) & 0x8)?"m":" ",
2831            PPU_REG(BG4SC) & 0x3,
2832            (PPU_REG(BG4SC) & 0xfc) << 9,
2833            m_layer[SNES_BG4].charmap << 13 );
2834      logerror("%sO %s%s%s%s%s%c%s%s       %4X",
2835            m_debug_options.bg_disabled[4]?" ":"*",
2836            (PPU_REG(TM) & 0x10)?"M":" ",
2837            (PPU_REG(TS) & 0x10)?"S":" ",
2838            (PPU_REG(CGADSUB) & 0x10)?"B":" ",
2839            (PPU_REG(TMW) & 0x10)?"m":" ",
2840            (PPU_REG(TSW) & 0x10)?"s":" ",
2841            WINLOGIC[(PPU_REG(WOBJLOG) & 0x3)],
2842            (PPU_REG(WOBJSEL) & 0x2)?((PPU_REG(WOBJSEL) & 0x1)?"o":"i"):" ",
2843            (PPU_REG(WOBJSEL) & 0x8)?((PPU_REG(WOBJSEL) & 0x4)?"o":"i"):" ",
2844            m_layer[SNES_OAM].charmap << 13 );
2845      logerror("%sB   %s  %c%s%s",
2846            m_debug_options.colormath_disabled?" ":"*",
2847            (PPU_REG(CGADSUB) & 0x20)?"B":" ",
2848            WINLOGIC[(PPU_REG(WOBJLOG) & 0xc)>>2],
2849            (PPU_REG(WOBJSEL) & 0x20)?((PPU_REG(WOBJSEL) & 0x10)?"o":"i"):" ",
2850            (PPU_REG(WOBJSEL) & 0x80)?((PPU_REG(WOBJSEL) & 0x40)?"o":"i"):" " );
2851      logerror("Flags: %s%s%s %s %2d", (PPU_REG(CGWSEL) & 0x2)?"S":"F", (PPU_REG(CGADSUB) & 0x80)?"-":"+", (PPU_REG(CGADSUB) & 0x40)?" 50%":"100%",(PPU_REG(CGWSEL) & 0x1)?"D":"P", (PPU_REG(MOSAIC) & 0xf0) >> 4 );
2852      logerror("SetINI: %s %s %s %s %s %s", (PPU_REG(SETINI) & 0x1)?" I":"NI", (PPU_REG(SETINI) & 0x2)?"P":"R", (PPU_REG(SETINI) & 0x4)?"240":"225",(PPU_REG(SETINI) & 0x8)?"512":"256",(PPU_REG(SETINI) & 0x40)?"E":"N",(PPU_REG(SETINI) & 0x80)?"ES":"NS" );
2853      logerror("Mode7: A %5d B %5d", m_mode7.matrix_a, m_mode7.matrix_b );
2854      logerror(" %s%s%s   C %5d D %5d", (PPU_REG(M7SEL) & 0xc0)?((PPU_REG(M7SEL) & 0x40)?"0":"C"):"R", (PPU_REG(M7SEL) & 0x1)?"H":" ", (PPU_REG(M7SEL) & 0x2)?"V":" ", m_mode7.matrix_c, m_mode7.matrix_d );
2855      logerror("       X %5d Y %5d", m_mode7.origin_x, m_mode7.origin_y );
2856   }
2857#endif
2858
2859   return 0;
2860}
2861#endif /* SNES_LAYER_DEBUG */
Property changes on: branches/new_menus/src/emu/video/snes_ppu.c
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branches/new_menus/src/emu/video/snes_ppu.h
r0r29544
1/***************************************************************************
2
3        SNES PPU
4
5***************************************************************************/
6
7#pragma once
8
9#ifndef __SNES_PPU_H__
10#define __SNES_PPU_H__
11
12
13#define MCLK_NTSC   (21477272)  /* verified */
14#define MCLK_PAL    (21218370)  /* verified */
15
16#define DOTCLK_NTSC (MCLK_NTSC/4)
17#define DOTCLK_PAL  (MCLK_PAL/4)
18
19#define SNES_SCR_WIDTH        256       /* 32 characters 8 pixels wide */
20#define SNES_SCR_HEIGHT_NTSC  225       /* Can be 224 or 240 height */
21#define SNES_SCR_HEIGHT_PAL   240       /* ??? */
22#define SNES_VTOTAL_NTSC      262       /* Maximum number of lines for NTSC systems */
23#define SNES_VTOTAL_PAL       312       /* Maximum number of lines for PAL systems */
24#define SNES_HTOTAL           341       /* Maximum number pixels per line (incl. hblank) */
25
26#define SNES_NTSC             0x00
27#define SNES_PAL              0x10
28
29
30#define SNES_LAYER_DEBUG  0
31
32
33/* offset-per-tile modes */
34enum
35{
36   SNES_OPT_NONE = 0,
37   SNES_OPT_MODE2,
38   SNES_OPT_MODE4,
39   SNES_OPT_MODE6
40};
41
42/* layers */
43enum
44{
45   SNES_BG1 = 0,
46   SNES_BG2,
47   SNES_BG3,
48   SNES_BG4,
49   SNES_OAM,
50   SNES_COLOR
51};
52
53
54struct SNES_SCANLINE
55{
56   int enable, clip;
57   
58   UINT16 buffer[SNES_SCR_WIDTH];
59   UINT8  priority[SNES_SCR_WIDTH];
60   UINT8  layer[SNES_SCR_WIDTH];
61   UINT8  blend_exception[SNES_SCR_WIDTH];
62};
63
64// ======================> snes_ppu_device
65
66class snes_ppu_device :  public device_t,
67                     public device_video_interface
68{
69public:
70   // construction/destruction
71   snes_ppu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
72
73   // inline configuration helpers
74   template<class _Object> static devcb2_base &static_set_open_bus_callback(device_t &device, _Object object) { return downcast<snes_ppu_device &>(device).m_openbus_cb.set_callback(object); }
75
76   UINT8 m_regs[0x40];
77   
78   SNES_SCANLINE m_scanlines[2];
79   
80   struct
81   {
82      /* clipmasks */
83      UINT8 window1_enabled, window1_invert;
84      UINT8 window2_enabled, window2_invert;
85      UINT8 wlog_mask;
86      /* color math enabled */
87      UINT8 color_math;
88     
89      UINT8 charmap;
90      UINT8 tilemap;
91      UINT8 tilemap_size;
92     
93      UINT8 tile_size;
94      UINT8 mosaic_enabled;   // actually used only for layers 0->3!
95     
96      UINT8 main_window_enabled;
97      UINT8 sub_window_enabled;
98      UINT8 main_bg_enabled;
99      UINT8 sub_bg_enabled;
100     
101      UINT16 hoffs;
102      UINT16 voffs;
103   } m_layer[6]; // this is for the BG1 - BG2 - BG3 - BG4 - OBJ - color layers
104   
105   struct
106   {
107      UINT8 address_low;
108      UINT8 address_high;
109      UINT8 saved_address_low;
110      UINT8 saved_address_high;
111      UINT16 address;
112      UINT16 priority_rotation;
113      UINT8 next_charmap;
114      UINT8 next_size;
115      UINT8 size;
116      UINT32 next_name_select;
117      UINT32 name_select;
118      UINT8 first_sprite;
119      UINT8 flip;
120      UINT16 write_latch;
121   } m_oam;
122   
123   struct
124   {
125      UINT16 latch_horz;
126      UINT16 latch_vert;
127      UINT16 current_horz;
128      UINT16 current_vert;
129      UINT8 last_visible_line;
130      UINT8 interlace_count;
131   } m_beam;
132   
133   struct
134   {
135      UINT8 repeat;
136      UINT8 hflip;
137      UINT8 vflip;
138      INT16 matrix_a;
139      INT16 matrix_b;
140      INT16 matrix_c;
141      INT16 matrix_d;
142      INT16 origin_x;
143      INT16 origin_y;
144      UINT16 hor_offset;
145      UINT16 ver_offset;
146      UINT8 extbg;
147   } m_mode7;
148   
149   struct OAM
150   {
151      UINT16 tile;
152      INT16 x, y;
153      UINT8 size, vflip, hflip, priority_bits, pal;
154      int height, width;
155   };
156   
157   struct OAM m_oam_spritelist[SNES_SCR_WIDTH / 2];
158   
159   UINT8 m_oam_itemlist[32];
160   
161   struct TILELIST {
162      INT16 x;
163      UINT16 priority, pal, tileaddr;
164      int hflip;
165   };
166   
167   struct TILELIST m_oam_tilelist[34];
168   
169#if SNES_LAYER_DEBUG
170   struct DEBUGOPTS
171   {
172      UINT8 bg_disabled[5];
173      UINT8 mode_disabled[8];
174      UINT8 draw_subscreen;
175      UINT8 windows_disabled;
176      UINT8 mosaic_disabled;
177      UINT8 colormath_disabled;
178      UINT8 sprite_reversed;
179      UINT8 select_pri[5];
180   };
181   struct DEBUGOPTS m_debug_options;
182#endif
183   
184   UINT8 m_mosaic_size;
185   UINT8 m_clip_to_black;
186   UINT8 m_prevent_color_math;
187   UINT8 m_sub_add_mode;
188   UINT8 m_bg3_priority_bit;
189   UINT8 m_direct_color;
190   UINT8 m_ppu_last_scroll;      /* as per Anomie's doc and Theme Park, all scroll regs shares (but mode 7 ones) the same
191                           'previous' scroll value */
192   UINT8 m_mode7_last_scroll;    /* as per Anomie's doc mode 7 scroll regs use a different value, shared with mode 7 matrix! */
193   
194   UINT8 m_ppu1_open_bus, m_ppu2_open_bus;
195   UINT8 m_ppu1_version, m_ppu2_version;
196   UINT8 m_window1_left, m_window1_right, m_window2_left, m_window2_right;
197   
198   UINT16 m_mosaic_table[16][4096];
199   UINT8 m_clipmasks[6][SNES_SCR_WIDTH];
200   UINT8 m_update_windows;
201   UINT8 m_update_offsets;
202   UINT8 m_update_oam_list;
203   UINT8 m_mode;
204   UINT8 m_interlace; //doubles the visible resolution
205   UINT8 m_obj_interlace;
206   UINT8 m_screen_brightness;
207   UINT8 m_screen_disabled;
208   UINT8 m_pseudo_hires;
209   UINT8 m_color_modes;
210   UINT8 m_stat77;
211   UINT8 m_stat78;
212   
213   UINT16                m_htmult;     /* in 512 wide, we run HTOTAL double and halve it on latching */
214   UINT16                m_cgram_address;  /* CGRAM address */
215   UINT8                 m_read_ophct;
216   UINT8                 m_read_opvct;
217   UINT16                m_vram_fgr_high;
218   UINT16                m_vram_fgr_increment;
219   UINT16                m_vram_fgr_count;
220   UINT16                m_vram_fgr_mask;
221   UINT16                m_vram_fgr_shift;
222   UINT16                m_vram_read_buffer;
223   UINT16                m_vmadd;
224   
225   inline UINT16 get_bgcolor(UINT8 direct_colors, UINT16 palette, UINT8 color);
226   inline void set_scanline_pixel(int screen, INT16 x, UINT16 color, UINT8 priority, UINT8 layer, int blend);
227   inline void draw_bgtile_lores(UINT8 layer, INT16 ii, UINT8 colour, UINT16 pal, UINT8 direct_colors, UINT8 priority);
228   inline void draw_bgtile_hires(UINT8 layer, INT16 ii, UINT8 colour, UINT16 pal, UINT8 direct_colors, UINT8 priority);
229   inline void draw_oamtile(INT16 ii, UINT8 colour, UINT16 pal, UINT8 priority);
230   inline void draw_tile(UINT8 planes, UINT8 layer, UINT32 tileaddr, INT16 x, UINT8 priority, UINT8 flip, UINT8 direct_colors, UINT16 pal, UINT8 hires);
231   inline UINT32 get_tmap_addr(UINT8 layer, UINT8 tile_size, UINT32 base, UINT32 x, UINT32 y);
232   inline void update_line(UINT16 curline, UINT8 layer, UINT8 priority_b, UINT8 priority_a, UINT8 color_depth, UINT8 hires, UINT8 offset_per_tile, UINT8 direct_colors);
233   void update_line_mode7(UINT16 curline, UINT8 layer, UINT8 priority_b, UINT8 priority_a);
234   void update_obsel(void);
235   void oam_list_build(void);
236   int is_sprite_on_scanline(UINT16 curline, UINT8 sprite);
237   void update_objects_rto(UINT16 curline);
238   void update_objects(UINT8 priority_oam0, UINT8 priority_oam1, UINT8 priority_oam2, UINT8 priority_oam3);
239   void update_mode_0(UINT16 curline);
240   void update_mode_1(UINT16 curline);
241   void update_mode_2(UINT16 curline);
242   void update_mode_3(UINT16 curline);
243   void update_mode_4(UINT16 curline);
244   void update_mode_5(UINT16 curline);
245   void update_mode_6(UINT16 curline);
246   void update_mode_7(UINT16 curline);
247   void draw_screens(UINT16 curline);
248   void update_windowmasks(void);
249   void update_offsets(void);
250   inline void draw_blend(UINT16 offset, UINT16 *colour, UINT8 prevent_color_math, UINT8 black_pen_clip, int switch_screens);
251   void refresh_scanline(running_machine &machine, bitmap_rgb32 &bitmap, UINT16 curline);
252   
253   void latch_counters(running_machine &machine);
254   void dynamic_res_change(running_machine &machine);
255   inline UINT32 get_vram_address(running_machine &machine);
256   UINT8 dbg_video(running_machine &machine, UINT16 curline);
257   
258   UINT8 read(address_space &space, UINT32 offset, UINT8 wrio_bit7);
259   void write(address_space &space, UINT32 offset, UINT8 data);
260   
261   DECLARE_READ8_MEMBER( oam_read );
262   DECLARE_WRITE8_MEMBER( oam_write );
263   DECLARE_READ8_MEMBER( cgram_read );
264   DECLARE_WRITE8_MEMBER( cgram_write );
265   DECLARE_READ8_MEMBER( vram_read );
266   DECLARE_WRITE8_MEMBER( vram_write );
267   UINT16 *m_oam_ram;     /* Object Attribute Memory */
268   UINT16 *m_cgram;   /* Palette RAM */
269   UINT8  *m_vram;    /* Video RAM (TODO: Should be 16-bit, but it's easier this way) */
270
271protected:
272   // device-level overrides
273   virtual void device_start();
274   virtual void device_reset() {};   
275
276private:
277   devcb2_read16  m_openbus_cb;
278};
279
280
281// device type definition
282extern const device_type SNES_PPU;
283
284
285/***************************************************************************
286 INTERFACE CONFIGURATION MACROS
287 ***************************************************************************/
288
289#define MCFG_SNES_PPU_OPENBUS_CB(_read) \
290   devcb = &snes_ppu_device::static_set_open_bus_callback(*device, DEVCB2_##_read);
291
292#endif
Property changes on: branches/new_menus/src/emu/video/snes_ppu.h
Added: svn:mime-type
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Added: svn:eol-style
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branches/new_menus/src/emu/video/crtc_ega.c
r29543r29544
521521   {
522522      UINT16 y;
523523
524      assert(!m_row_update_cb.isnull() != NULL);
524      assert(!m_row_update_cb.isnull());
525525
526526      /* call the set up function if any */
527527      if (!m_begin_update_cb.isnull())
branches/new_menus/src/emu/video/epic12.c
r29543r29544
88const device_type EPIC12 = &device_creator<epic12_device>;
99
1010epic12_device::epic12_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
11   : device_t(mconfig, EPIC12, "epic12_device", tag, owner, clock, "epic12", __FILE__),
11   : device_t(mconfig, EPIC12, "EP1C12 BLITTER", tag, owner, clock, "epic12", __FILE__),
1212      device_video_interface(mconfig, *this)
1313{
1414   m_is_unsafe = 0;
branches/new_menus/src/emu/video/video.mak
r29543r29544
447447
448448#-------------------------------------------------
449449#
450#@src/emu/video/snes_ppu.h,VIDEOS += SNES_PPU
451#-------------------------------------------------
452ifneq ($(filter SNES_PPU,$(VIDEOS)),)
453VIDEOOBJS+= $(VIDEOOBJ)/snes_ppu.o
454endif
455
456#-------------------------------------------------
457#
450458#@src/emu/video/stvvdp1.h,VIDEOS += STVVDP
451459#@src/emu/video/stvvdp2.h,VIDEOS += STVVDP
452460#-------------------------------------------------
branches/new_menus/src/emu/video/m50458.c
r29543r29544
173173//-------------------------------------------------
174174
175175m50458_device::m50458_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
176   : device_t(mconfig, M50458, "m50458", tag, owner, clock, "m50458", __FILE__),
176   : device_t(mconfig, M50458, "M50458 OSD", tag, owner, clock, "m50458", __FILE__),
177177      device_memory_interface(mconfig, *this),
178178      device_video_interface(mconfig, *this),
179179      m_space_config("videoram", ENDIANNESS_LITTLE, 16, 16, 0, NULL, *ADDRESS_MAP_NAME(m50458_vram))
branches/new_menus/src/emu/video/saa5050.c
r29543r29544
184184}
185185
186186saa5050_device::saa5050_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
187   device_t(mconfig, SAA5050, "SAA5050", tag, owner, clock, "saa5050", __FILE__),
187   device_t(mconfig, SAA5050, "SAA5050 video", tag, owner, clock, "saa5050", __FILE__),
188188   m_char_rom(*this, "chargen"),
189189   m_read_d(*this),
190190   m_frame_count(0),
branches/new_menus/src/emu/sound/nes_apu.c
r29543r29544
108108      m_samps_per_sync(0),
109109      m_buffer_size(0),
110110      m_real_rate(0),
111      m_stream(NULL)
111      m_stream(NULL),
112      m_cpu_tag("")
112113{
113114   for (int i = 0; i < NOISE_LONG; i++)
114115   {
r29543r29544
132133}
133134
134135//-------------------------------------------------
135//  device_config_complete - perform any
136//  operations now that the configuration is
137//  complete
138//-------------------------------------------------
139
140void nesapu_device::device_config_complete()
141{
142   // inherit a copy of the static data
143   const nesapu_interface *intf = reinterpret_cast<const nesapu_interface *>(static_config());
144   if (intf != NULL)
145   *static_cast<nesapu_interface *>(this) = *intf;
146
147   // or initialize to defaults if none provided
148   else
149   {
150      m_cpu_tag = "";
151   }
152}
153
154//-------------------------------------------------
155136//  device_start - device-specific startup
156137//-------------------------------------------------
157138
158139void nesapu_device::device_start()
159140{
160141   int rate = clock() / 4;
161   int i;
162142
163143   /* Initialize global variables */
164144   m_samps_per_sync = rate / ATTOSECONDS_TO_HZ(machine().first_screen()->frame_period().attoseconds);
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180160   m_stream = machine().sound().stream_alloc(*this, 0, 1, rate, this);
181161
182162   /* register for save */
183   for (i = 0; i < 2; i++)
163   for (int i = 0; i < 2; i++)
184164   {
185165      save_item(NAME(m_APU.squ[i].regs), i);
186166      save_item(NAME(m_APU.squ[i].vbl_length), i);
branches/new_menus/src/emu/sound/nes_apu.h
r29543r29544
4141#define  SYNCS_MAX1     0x20
4242#define  SYNCS_MAX2     0x80
4343
44struct nesapu_interface
45{
46   const char *m_cpu_tag;  /* CPU tag */
47};
48
4944class nesapu_device : public device_t,
50                           public device_sound_interface,
51                           public nesapu_interface
45                  public device_sound_interface
5246{
5347public:
5448   nesapu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
5549   ~nesapu_device() {}
50   
51   static void set_cpu_tag(device_t &device, const char *tag) { downcast<nesapu_device &>(device).m_cpu_tag = tag; }
5652
5753   DECLARE_READ8_MEMBER( read );
5854   DECLARE_WRITE8_MEMBER( write );
5955
6056protected:
6157   // device-level overrides
62   virtual void device_config_complete();
6358   virtual void device_start();
6459
6560   // sound stream update overrides
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7873   uint32  m_sync_times2[SYNCS_MAX2]; /* Samples per sync table */
7974   sound_stream *m_stream;
8075
76   const char *m_cpu_tag;
77
8178   void create_syncs(unsigned long sps);
8279   int8 apu_square(square_t *chan);
8380   int8 apu_triangle(triangle_t *chan);
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9087
9188extern const device_type NES_APU;
9289
90#define MCFG_NES_APU_CPU(_tag) \
91   nesapu_device::set_cpu_tag(*device, _tag);
9392
93
9494#endif /* __NES_APU_H__ */
branches/new_menus/src/emu/sound/k054539.c
r29543r29544
1616#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
1717
1818k054539_device::k054539_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
19   : device_t(mconfig, K054539, "K054539", tag, owner, clock, "k054539", __FILE__),
19   : device_t(mconfig, K054539, "Konami 054539", tag, owner, clock, "k054539", __FILE__),
2020      device_sound_interface(mconfig, *this),
2121      m_timer_handler(*this)
2222{
branches/new_menus/src/emu/sound/cem3394.c
r29543r29544
116116cem3394_device::cem3394_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
117117   : device_t(mconfig, CEM3394, "CEM3394", tag, owner, clock, "cem3394", __FILE__),
118118      device_sound_interface(mconfig, *this),
119      m_external(NULL),
120119      m_stream(NULL),
121120      m_vco_zero_freq(0.0),
122121      m_filter_zero_freq(0.0),
r29543r29544
154153   int i;
155154
156155   /* external volume is effectively 0 if no external function */
157   if (!m_external || !ENABLE_EXTERNAL)
156   if (m_ext_cb.isnull() || !ENABLE_EXTERNAL)
158157      ext_volume = 0;
159158
160159   /* adjust the volume for the filter */
r29543r29544
175174      INT16 last_ext = m_last_ext;
176175
177176      /* fetch the external data */
178      (*m_external)(this, samples, m_external_buffer);
177      m_ext_cb(samples, m_external_buffer);
179178
180179      /* compute the modulation depth, and adjust fstep to the maximum frequency */
181180      /* we lop off 13 bits of depth so that we can multiply by stepadjust, below, */
r29543r29544
325324
326325void cem3394_device::device_start()
327326{
328   const cem3394_interface *intf = (const cem3394_interface *)static_config();
329
330327   /* copy global parameters */
331328   m_sample_rate = CEM3394_SAMPLE_RATE;
332329   m_inv_sample_rate = 1.0 / (double)m_sample_rate;
333330
334331   /* allocate stream channels, 1 per chip */
335332   m_stream = stream_alloc(0, 1, m_sample_rate);
336   m_external = intf->external;
337   m_vco_zero_freq = intf->vco_zero_freq;
338   m_filter_zero_freq = intf->filter_zero_freq;
339333
334   m_ext_cb.bind_relative_to(*owner());
335
340336   /* allocate memory for a mixer buffer and external buffer (1 second should do it!) */
341337   m_mixer_buffer = auto_alloc_array(machine(), INT16, m_sample_rate);
342338   m_external_buffer = auto_alloc_array(machine(), INT16, m_sample_rate);
branches/new_menus/src/emu/sound/cem3394.h
r29543r29544
55
66#define CEM3394_SAMPLE_RATE     (44100*4)
77
8
9// interface
10struct cem3394_interface
11{
12   double vco_zero_freq;                    /* frequency at 0V for VCO */
13   double filter_zero_freq;                 /* frequency at 0V for filter */
14   void (*external)(device_t*, int, short*);/* external input source */
15};
16
178// inputs
189enum
1910{
r29543r29544
2718   CEM3394_FINAL_GAIN
2819};
2920
21typedef device_delegate<void (int count, short *buffer)> cem3394_ext_input_delegate;
3022
23#define CEM3394_EXT_INPUT(_name) void _name(int count, short *buffer)
24
3125//**************************************************************************
3226//  INTERFACE CONFIGURATION MACROS
3327//**************************************************************************
r29543r29544
3731#define MCFG_CEM3394_REPLACE(_tag, _clock) \
3832   MCFG_DEVICE_REPLACE(_tag, CEM3394, _clock)
3933
34#define MCFG_CEM3394_EXT_INPUT_CB(_class, _method) \
35   cem3394_device::set_ext_input_callback(*device, cem3394_ext_input_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
4036
37#define MCFG_CEM3394_VCO_ZERO(_freq) \
38   cem3394_device::set_vco_zero_freq(*device, _freq);
4139
40#define MCFG_CEM3394_FILTER_ZERO(_freq) \
41   cem3394_device::set_filter_zero_freq(*device, _freq);
42
43
4244class cem3394_device : public device_t,
4345                  public device_sound_interface
4446{
r29543r29544
4648   cem3394_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
4749   ~cem3394_device() { }
4850
51   static void set_ext_input_callback(device_t &device, cem3394_ext_input_delegate callback) { downcast<cem3394_device &>(device).m_ext_cb = callback; }
52   static void set_vco_zero_freq(device_t &device, double freq) { downcast<cem3394_device &>(device).m_vco_zero_freq = freq; }
53   static void set_filter_zero_freq(device_t &device, double freq) { downcast<cem3394_device &>(device).m_filter_zero_freq = freq; }
54
4955protected:
5056   // device-level overrides
5157   virtual void device_start();
r29543r29544
7379   UINT32 compute_db_volume(double voltage);
7480
7581private:
76   void (*m_external)(device_t*, int, short*);/* callback to generate external samples */
82   cem3394_ext_input_delegate m_ext_cb; /* callback to generate external samples */
7783
7884   sound_stream *m_stream;           /* our stream */
7985   double m_vco_zero_freq;           /* frequency of VCO at 0.0V */
branches/new_menus/src/emu/sound/k053260.c
r29543r29544
2727//-------------------------------------------------
2828
2929k053260_device::k053260_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
30   : device_t(mconfig, K053260, "K053260", tag, owner, clock, "k053260", __FILE__),
30   : device_t(mconfig, K053260, "Konami 053260", tag, owner, clock, "k053260", __FILE__),
3131      device_sound_interface(mconfig, *this),
3232      m_channel(NULL),
3333      m_mode(0),
3434      m_rom(NULL),
3535      m_rom_size(0),
3636      m_delta_table(NULL),
37      m_intf(NULL)
37      m_rgnoverride(NULL)
3838{
3939   memset(m_regs, 0, sizeof(int)*0x30);
4040}
r29543r29544
4646
4747void k053260_device::device_start()
4848{
49   static const k053260_interface defintrf = { 0 };
5049   int rate = clock() / 32;
51   int i;
5250
53   /* Initialize our chip structure */
54   m_intf = (static_config() != NULL) ? (const k053260_interface *)static_config() : &defintrf;
55
5651   m_mode = 0;
5752
58   memory_region *region = (m_intf->rgnoverride != NULL) ? memregion(m_intf->rgnoverride) : this->region();
59
53   memory_region *region = (m_rgnoverride) ? memregion(m_rgnoverride) : this->region();
6054   m_rom = *region;
6155   m_rom_size = region->bytes();
6256
6357   device_reset();
6458
65   for ( i = 0; i < 0x30; i++ )
59   for (int i = 0; i < 0x30; i++)
6660      m_regs[i] = 0;
6761
6862   m_delta_table = auto_alloc_array( machine(), UINT32, 0x1000 );
r29543r29544
7569   save_item(NAME(m_mode));
7670   save_item(NAME(m_regs));
7771
78   for ( i = 0; i < 4; i++ )
72   for (int i = 0; i < 4; i++)
7973   {
8074      save_item(NAME(m_channels[i].rate), i);
8175      save_item(NAME(m_channels[i].size), i);
r29543r29544
9892
9993void k053260_device::device_reset()
10094{
101   int i;
10295
103   for( i = 0; i < 4; i++ ) {
96   for (int i = 0; i < 4; i++)
97   {
10498      m_channels[i].rate = 0;
10599      m_channels[i].size = 0;
106100      m_channels[i].start = 0;
branches/new_menus/src/emu/sound/rf5c68.c
r29543r29544
2424      m_stream(NULL),
2525      m_cbank(0),
2626      m_wbank(0),
27      m_enable(0),
28      m_sample_callback(NULL)
27      m_enable(0)
2928{
3029   memset(m_data, 0, sizeof(UINT8)*0x10000);
3130}
r29543r29544
3736
3837void rf5c68_device::device_start()
3938{
40   const rf5c68_interface* intf = (const rf5c68_interface*)static_config();
41
39   m_sample_end_cb.bind_relative_to(*owner());
40   
4241   /* allocate memory for the chip */
4342   memset(m_data, 0xff, sizeof(m_data));
4443
4544   /* allocate the stream */
4645   m_stream = stream_alloc(0, 2, clock() / 384);
47
48   /* set up callback */
49   if(intf != NULL)
50      m_sample_callback = intf->sample_end_callback;
51   else
52      m_sample_callback = NULL;
5346}
5447
5548
r29543r29544
8881            int sample;
8982
9083            /* trigger sample callback */
91            if(m_sample_callback)
84            if(!m_sample_end_cb.isnull())
9285            {
9386               if(((chan->addr >> 11) & 0xfff) == 0xfff)
94                  m_sample_callback(this, ((chan->addr >> 11)/0x2000));
87                  m_sample_end_cb((chan->addr >> 11)/0x2000);
9588            }
9689
9790            /* fetch the sample and handle looping */
branches/new_menus/src/emu/sound/k053260.h
r29543r29544
1919#define MCFG_K053260_REPLACE(_tag, _clock) \
2020   MCFG_DEVICE_REPLACE(_tag, K053260, _clock)
2121
22#define MCFG_K053260_REGION(_tag) \
23   k053260_device::set_region_tag(*device, _tag);
2224
25
2326//**************************************************************************
2427//  TYPE DEFINITIONS
2528//**************************************************************************
2629
27struct k053260_interface
28{
29   const char *rgnoverride;
30};
31
32
3330struct k053260_channel
3431{
3532   k053260_channel() :
r29543r29544
6865   k053260_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
6966   ~k053260_device() { }
7067
68   static void set_region_tag(device_t &device, const char *tag) { downcast<k053260_device &>(device).m_rgnoverride = tag; }
69
7170protected:
7271   // device-level overrides
7372   virtual void device_start();
r29543r29544
8483   void InitDeltaTable( int rate, int clock );
8584   void check_bounds( int channel );
8685
87private:
8886   sound_stream *              m_channel;
8987   int                         m_mode;
9088   int                         m_regs[0x30];
r29543r29544
9290   int                         m_rom_size;
9391   UINT32                      *m_delta_table;
9492   k053260_channel             m_channels[4];
95   const k053260_interface     *m_intf;
93   const char                  *m_rgnoverride;
9694};
9795
9896extern const device_type K053260;
9997
100
10198#endif /* __K053260_H__ */
branches/new_menus/src/emu/sound/rf5c68.h
r29543r29544
1919#define MCFG_RF5C68_REPLACE(_tag, _clock) \
2020   MCFG_DEVICE_REPLACE(_tag, RF5C68, _clock)
2121
22#define MCFG_RF5C68_SAMPLE_END_CB(_class, _method) \
23   rf5c68_device::set_end_callback(*device, rf5c68_sample_end_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
2224
2325//**************************************************************************
2426//  TYPE DEFINITIONS
2527//**************************************************************************
2628
27struct rf5c68_interface
28{
29   void (*sample_end_callback)(device_t* device, int channel);
30};
29typedef device_delegate<void (int channel)> rf5c68_sample_end_cb_delegate;
3130
31#define RF5C68_SAMPLE_END_CB_MEMBER(_name)   void _name(int channel)
3232
33
3334struct rf5c68_pcm_channel
3435{
3536   rf5c68_pcm_channel() :
r29543r29544
5152};
5253
5354
54
5555// ======================> rf5c68_device
5656
5757class rf5c68_device : public device_t,
r29543r29544
6161   rf5c68_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
6262   ~rf5c68_device() { }
6363
64   static void set_end_callback(device_t &device, rf5c68_sample_end_cb_delegate callback) { downcast<rf5c68_device &>(device).m_sample_end_cb = callback; }
65   
6466protected:
6567   // device-level overrides
6668   virtual void device_start();
r29543r29544
8284   UINT8                m_wbank;
8385   UINT8                m_enable;
8486   UINT8                m_data[0x10000];
85   void                (*m_sample_callback)(device_t* device,int channel);
87
88   rf5c68_sample_end_cb_delegate m_sample_end_cb;
8689};
8790
8891extern const device_type RF5C68;
branches/new_menus/src/emu/sound/namco.c
r29543r29544
4444      m_stream(NULL),
4545      m_namco_clock(0),
4646      m_sample_rate(0),
47      m_f_fracbits(0)
47      m_f_fracbits(0),
48      m_voices(0),
49      m_stereo(0)
4850{
4951}
5052
r29543r29544
6567
6668
6769//-------------------------------------------------
68//  device_config_complete - perform any
69//  operations now that the configuration is
70//  complete
71//-------------------------------------------------
72
73void namco_audio_device::device_config_complete()
74{
75   // inherit a copy of the static data
76   const namco_interface *intf = reinterpret_cast<const namco_interface *>(static_config());
77   if (intf != NULL)
78   *static_cast<namco_interface *>(this) = *intf;
79
80   // or initialize to defaults if none provided
81   else
82   {
83      m_voices = 0;
84      m_stereo = 0;
85   }
86}
87
88//-------------------------------------------------
8970//  device_start - device-specific startup
9071//-------------------------------------------------
9172
branches/new_menus/src/emu/sound/namco.h
r29543r29544
88
99#define MAX_VOLUME 16
1010
11struct namco_interface
12{
13   int m_voices;     /* number of voices */
14   int m_stereo;     /* set to 1 to indicate stereo (e.g., System 1) */
15};
1611
12#define MCFG_NAMCO_AUDIO_VOICES(_voices) \
13   namco_audio_device::set_voices(*device, _voices);
14
15#define MCFG_NAMCO_AUDIO_STEREO(_stereo) \
16   namco_audio_device::set_stereo(*device, _stereo);
17
18
1719/* this structure defines the parameters for a channel */
1820struct sound_channel
1921{
r29543r29544
2931};
3032
3133class namco_audio_device : public device_t,
32                           public device_sound_interface,
33                           public namco_interface
34                     public device_sound_interface
3435{
3536public:
3637   namco_audio_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
3738   ~namco_audio_device() {}
3839
39   protected:
40   // static configuration
41   static void set_voices(device_t &device, int voices) { downcast<namco_audio_device &>(device).m_voices = voices; }
42   static void set_stereo(device_t &device, int stereo) { downcast<namco_audio_device &>(device).m_stereo = stereo; }
43   
44protected:
4045   // device-level overrides
41   virtual void device_config_complete();
4246   virtual void device_start();
4347
4448   // internal state
r29543r29544
6165   int m_sample_rate;
6266   int m_f_fracbits;
6367
68   int m_voices;     /* number of voices */
69   int m_stereo;     /* set to 1 to indicate stereo (e.g., System 1) */
70
6471   /* decoded waveform table */
6572   INT16 *m_waveform[MAX_VOLUME];
6673
branches/new_menus/src/emu/sound/k007232.c
r29543r29544
146146const device_type K007232 = &device_creator<k007232_device>;
147147
148148k007232_device::k007232_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
149   : device_t(mconfig, K007232, "K007232", tag, owner, clock, "k007232", __FILE__),
149   : device_t(mconfig, K007232, "Konami 007232", tag, owner, clock, "k007232", __FILE__),
150150      device_sound_interface(mconfig, *this),
151151      m_port_write_handler(*this)
152152{
branches/new_menus/src/emu/sound/x1_010.c
r29543r29544
8686   : device_t(mconfig, X1_010, "X1-010", tag, owner, clock, "x1_010", __FILE__),
8787      device_sound_interface(mconfig, *this),
8888      m_rate(0),
89      m_adr(0),
8990      m_stream(NULL),
9091      m_region(NULL),
9192      m_sound_enable(0),
r29543r29544
9899}
99100
100101//-------------------------------------------------
101//  device_config_complete - perform any
102//  operations now that the configuration is
103//  complete
104//-------------------------------------------------
105
106void x1_010_device::device_config_complete()
107{
108   // inherit a copy of the static data
109   const x1_010_interface *intf = reinterpret_cast<const x1_010_interface *>(static_config());
110   if (intf != NULL)
111   *static_cast<x1_010_interface *>(this) = *intf;
112
113   // or initialize to defaults if none provided
114   else
115   {
116   m_adr = 0;
117   }
118}
119
120//-------------------------------------------------
121102//  device_start - device-specific startup
122103//-------------------------------------------------
123104
branches/new_menus/src/emu/sound/x1_010.h
r29543r29544
55
66#define SETA_NUM_CHANNELS 16
77
8struct x1_010_interface
9{
10   int m_adr;    /* address */
11};
12
13
148class x1_010_device : public device_t,
15                           public device_sound_interface,
16                           public x1_010_interface
9                  public device_sound_interface
1710{
1811public:
1912   x1_010_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
2013   ~x1_010_device() {}
2114
15   // static configuration
16   static void set_address(device_t &device, int addr) { downcast<x1_010_device &>(device).m_adr = addr; }
17
2218   DECLARE_READ8_MEMBER ( read );
2319   DECLARE_WRITE8_MEMBER( write );
2420
r29543r29544
2925
3026protected:
3127   // device-level overrides
32   virtual void device_config_complete();
3328   virtual void device_start();
3429
3530   // sound stream update overrides
r29543r29544
3934
4035   /* Variables only used here */
4136   int m_rate;                               // Output sampling rate (Hz)
37   int m_adr;                                // address
4238   sound_stream *  m_stream;                 // Stream handle
4339   const UINT8 *m_region;                    // region name
4440   int m_sound_enable;                       // sound output enable/disable
r29543r29544
5349extern const device_type X1_010;
5450
5551
52#define MCFG_X1_010_ADDRESS(_addr) \
53   x1_010_device::set_address(*device, _addr);
54
55
5656#endif /* __X1_010_H__ */
branches/new_menus/src/emu/sound/k051649.c
r29543r29544
4242//-------------------------------------------------
4343
4444k051649_device::k051649_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
45   : device_t(mconfig, K051649, "K051649", tag, owner, clock, "k051649", __FILE__),
45   : device_t(mconfig, K051649, "Konami 051649", tag, owner, clock, "k051649", __FILE__),
4646      device_sound_interface(mconfig, *this),
4747      m_stream(NULL),
4848      m_mclock(0),
branches/new_menus/src/emu/sound/k005289.c
r29543r29544
5252//-------------------------------------------------
5353
5454k005289_device::k005289_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
55   : device_t(mconfig, K005289, "K005289", tag, owner, clock, "k005289", __FILE__),
55   : device_t(mconfig, K005289, "Konami 005289", tag, owner, clock, "k005289", __FILE__),
5656      device_sound_interface(mconfig, *this),
5757   m_sound_prom(NULL),
5858   m_stream(NULL),
branches/new_menus/src/emu/sound/vrender0.c
r29543r29544
5959#define ENVVOL(chan)    (m_SOUNDREGS[(0x20/4)*chan+0x04/4]&0xffffff)
6060
6161/*
62#define GETSOUNDREG16(Chan,Offs) space.read_word(m_Intf.reg_base+0x20*Chan+Offs)
63#define GETSOUNDREG32(Chan,Offs) space.read_dword(m_Intf.reg_base+0x20*Chan+Offs)
62#define GETSOUNDREG16(Chan,Offs) space.read_word(m_reg_base+0x20*Chan+Offs)
63#define GETSOUNDREG32(Chan,Offs) space.read_dword(m_reg_base+0x20*Chan+Offs)
6464
6565#define CURSADDR(chan)  GETSOUNDREG32(chan,0x00)
6666#define DSADDR(chan)    GETSOUNDREG16(chan,0x08)
r29543r29544
8686      device_sound_interface(mconfig, *this),
8787      m_TexBase(NULL),
8888      m_FBBase(NULL),
89      m_stream(NULL)
89      m_stream(NULL),
90      m_reg_base(0)
9091{
9192}
9293
r29543r29544
9798
9899void vrender0_device::device_start()
99100{
100   const vr0_interface *intf = (const vr0_interface *)static_config();
101
102   memcpy(&(m_Intf),intf,sizeof(vr0_interface));
103101   memset(m_SOUNDREGS,0,sizeof(m_SOUNDREGS));
104102
105103   m_stream = stream_alloc(0, 2, 44100);
branches/new_menus/src/emu/sound/vrender0.h
r29543r29544
1313#define MCFG_SOUND_VRENDER0_REPLACE(_tag, _clock) \
1414   MCFG_DEVICE_REPLACE(_tag, VRENDER0, _clock)
1515
16#define MCFG_VR0_REGBASE(_base) \
17   vrender0_device::set_reg_base(*device, _base);
1618
1719//**************************************************************************
1820//  TYPE DEFINITIONS
r29543r29544
2123
2224// ======================> vrender0_device
2325
24struct vr0_interface
25{
26   UINT32 RegBase;
27};
28
29void vr0_snd_set_areas(device_t *device, UINT32 *texture, UINT32 *frame);
30
3126class vrender0_device : public device_t,
3227                  public device_sound_interface
3328{
r29543r29544
3530   vrender0_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
3631   ~vrender0_device() { }
3732
38protected:
39   // device-level overrides
40   virtual void device_start();
33   // static configuration
34   static void set_reg_base(device_t &device, int base) { downcast<vrender0_device &>(device).m_reg_base = base; }
4135
42   // sound stream update overrides
43   virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples);
44
45public:
4636   DECLARE_READ32_MEMBER( vr0_snd_read );
4737   DECLARE_WRITE32_MEMBER( vr0_snd_write );
4838
4939   void set_areas(UINT32 *texture, UINT32 *frame);
5040
41protected:
42   // device-level overrides
43   virtual void device_start();
44   
45   // sound stream update overrides
46   virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples);
47
5148private:
5249   UINT32 *m_TexBase;
5350   UINT32 *m_FBBase;
5451   UINT32 m_SOUNDREGS[0x10000/4];
5552   sound_stream *m_stream;
56   vr0_interface m_Intf;
53   UINT32 m_reg_base;
5754
5855   void VR0_RenderAudio(int nsamples, stream_sample_t *l, stream_sample_t *r);
5956};
branches/new_menus/src/emu/sound/okim6258.c
r29543r29544
108108
109109void okim6258_device::device_start()
110110{
111   const okim6258_interface *intf = (const okim6258_interface *)static_config();
112
113111   compute_tables();
114112
115113   m_master_clock = clock();
116   m_adpcm_type = intf->adpcm_type;
117114
118   /* D/A precision is 10-bits but 12-bit data can be output serially to an external DAC */
119   m_output_bits = intf->output_12bits ? 12 : 10;
120   m_divider = dividers[intf->divider];
115   m_divider = dividers[m_start_divider];
121116
122117   m_stream = stream_alloc(0, 1, clock()/m_divider);
123118
branches/new_menus/src/emu/sound/okim6258.h
r29543r29544
1010#define TYPE_3BITS          0
1111#define TYPE_4BITS          1
1212
13#define OUTPUT_10BITS       0
14#define OUTPUT_12BITS       1
13#define OUTPUT_10BITS       10
14#define OUTPUT_12BITS       12
1515
1616
1717//**************************************************************************
r29543r29544
2323#define MCFG_OKIM6258_REPLACE(_tag, _clock) \
2424   MCFG_DEVICE_REPLACE(_tag, OKIM6258, _clock)
2525
26#define MCFG_OKIM6258_DIVIDER(_div) \
27   okim6258_device::set_start_div(*device, _div);
2628
29#define MCFG_OKIM6258_ADPCM_TYPE(_type) \
30   okim6258_device::set_type(*device, _type);
31
32#define MCFG_OKIM6258_OUT_BITS(_bits) \
33   okim6258_device::set_outbits(*device, _bits);
34
35
2736//**************************************************************************
2837//  TYPE DEFINITIONS
2938//**************************************************************************
3039
31struct okim6258_interface
32{
33   int divider;
34   int adpcm_type;
35   int output_12bits;
36};
37
38
3940// ======================> okim6258_device
4041
4142class okim6258_device : public device_t,
r29543r29544
4546   okim6258_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
4647   ~okim6258_device() { }
4748
49   // static configuration
50   static void set_start_div(device_t &device, int div) { downcast<okim6258_device &>(device).m_start_divider = div; }
51   static void set_type(device_t &device, int type) { downcast<okim6258_device &>(device).m_adpcm_type = type; }
52   static void set_outbits(device_t &device, int outbit) { downcast<okim6258_device &>(device).m_output_bits = outbit; }
53
4854protected:
4955   // device-level overrides
5056   virtual void device_start();
r29543r29544
7177   UINT8  m_status;
7278
7379   UINT32 m_master_clock;    /* master clock frequency */
80   UINT32 m_start_divider;
7481   UINT32 m_divider;         /* master clock divider */
7582   UINT8 m_adpcm_type;       /* 3/4 bit ADPCM select */
7683   UINT8 m_data_in;          /* ADPCM data-in register */
7784   UINT8 m_nibble_shift;     /* nibble select */
7885   sound_stream *m_stream;   /* which stream are we playing on? */
7986
80   UINT8 m_output_bits;
87   UINT8 m_output_bits;      /* D/A precision is 10-bits but 12-bit data can be
88                        output serially to an external DAC */
8189
8290   INT32 m_signal;
8391   INT32 m_step;
branches/new_menus/src/emu/sound/c6280.c
r29543r29544
248248
249249c6280_device::c6280_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
250250   : device_t(mconfig, C6280, "HuC6280", tag, owner, clock, "c6280", __FILE__),
251      device_sound_interface(mconfig, *this)
251      device_sound_interface(mconfig, *this),
252      m_cpudevice(*this)
252253{
253254}
254255
255256//-------------------------------------------------
256//  device_config_complete - perform any
257//  operations now that the configuration is
258//  complete
259//-------------------------------------------------
260
261void c6280_device::device_config_complete()
262{
263}
264
265//-------------------------------------------------
266257//  device_start - device-specific startup
267258//-------------------------------------------------
268259
r29543r29544
273264   /* Create stereo stream */
274265   m_stream = machine().sound().stream_alloc(*this, 0, 2, rate, this);
275266
276   const c6280_interface *intf = (const c6280_interface *)static_config();
277
278267   /* Loudest volume level for table */
279268   double level = 65535.0 / 6.0 / 32.0;
280269
r29543r29544
285274   m_lfo_control = 0;
286275   memset(m_channel, 0, sizeof(channel) * 8);
287276
288   m_cpudevice = machine().device<h6280_device>(intf->cpu);
289   if (m_cpudevice == NULL)
290   {
291      fatalerror("c6280_init: no CPU found with tag of '%s'\n", tag());
292   }
293
294277   /* Make waveform frequency table */
295278   for (int i = 0; i < 4096; i += 1)
296279   {
r29543r29544
321304   save_item(NAME(m_lfo_control));
322305   for (int chan = 0; chan < 8; chan++)
323306   {
324      state_save_register_item(machine(), "c6280", NULL, chan, m_channel[chan].m_frequency);
325      state_save_register_item(machine(), "c6280", NULL, chan, m_channel[chan].m_control);
326      state_save_register_item(machine(), "c6280", NULL, chan, m_channel[chan].m_balance);
327      state_save_register_item(machine(), "c6280", NULL, chan, m_channel[chan].m_waveform);
328      state_save_register_item(machine(), "c6280", NULL, chan, m_channel[chan].m_index);
329      state_save_register_item(machine(), "c6280", NULL, chan, m_channel[chan].m_dda);
330      state_save_register_item(machine(), "c6280", NULL, chan, m_channel[chan].m_noise_control);
331      state_save_register_item(machine(), "c6280", NULL, chan, m_channel[chan].m_noise_counter);
332      state_save_register_item(machine(), "c6280", NULL, chan, m_channel[chan].m_counter);
307      save_item(NAME(m_channel[chan].m_frequency), chan);
308      save_item(NAME(m_channel[chan].m_control), chan);
309      save_item(NAME(m_channel[chan].m_balance), chan);
310      save_item(NAME(m_channel[chan].m_waveform), chan);
311      save_item(NAME(m_channel[chan].m_index), chan);
312      save_item(NAME(m_channel[chan].m_dda), chan);
313      save_item(NAME(m_channel[chan].m_noise_control), chan);
314      save_item(NAME(m_channel[chan].m_noise_counter), chan);
315      save_item(NAME(m_channel[chan].m_counter), chan);
333316   }
334317}
branches/new_menus/src/emu/sound/c6280.h
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55
66#include "cpu/h6280/h6280.h"
77
8struct c6280_interface
9{
10   const char *    cpu;
11};
12
138class c6280_device : public device_t,
149                  public device_sound_interface
1510{
1611public:
1712   c6280_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
1813
14   static void set_devicecpu_tag(device_t &device, const char *tag) { downcast<c6280_device &>(device).m_cpudevice.set_tag(tag); }
15
1916   // read/write
2017   DECLARE_READ8_MEMBER( c6280_r );
2118   DECLARE_WRITE8_MEMBER( c6280_w );
2219
2320protected:
2421   // device-level overrides
25   virtual void device_config_complete();
2622   virtual void device_start();
2723
2824   // sound stream update overrides
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4339
4440   // internal state
4541   sound_stream *m_stream;
46   h6280_device *m_cpudevice;
42   required_device<h6280_device> m_cpudevice;
4743   UINT8 m_select;
4844   UINT8 m_balance;
4945   UINT8 m_lfo_frequency;
r29543r29544
5652
5753extern const device_type C6280;
5854
55#define MCFG_C6280_CPU(_tag) \
56   c6280_device::set_devicecpu_tag(*device, "^"_tag);
5957
58
6059#endif /* __C6280_H__ */
branches/new_menus/src/emu/sound/c140.c
r29543r29544
106106
107107void c140_device::device_start()
108108{
109   const c140_interface *intf = (const c140_interface *)static_config();
110
111109   m_sample_rate=m_baserate=clock();
112110
113   m_banking_type = intf->banking_type;
114
115111   m_stream = stream_alloc(0, 2, m_sample_rate);
116112
117113   m_pRom=*region();
branches/new_menus/src/emu/sound/c140.h
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2323#define MCFG_C140_REPLACE(_tag, _clock) \
2424   MCFG_DEVICE_REPLACE(_tag, C140, _clock)
2525
26#define MCFG_C140_BANK_TYPE(_type) \
27   c140_device::set_bank_type(*device, _type);
2628
29
2730//**************************************************************************
2831//  TYPE DEFINITIONS
2932//**************************************************************************
3033
31struct c140_interface
32{
33   int banking_type;
34};
35
36
3734struct C140_VOICE
3835{
3936   C140_VOICE() :
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8178   c140_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
8279   ~c140_device() { }
8380
81   // static configuration
82   static void set_bank_type(device_t &device, int bank) { downcast<c140_device &>(device).m_banking_type = bank; }
83
8484protected:
8585   // device-level overrides
8686   virtual void device_start();
branches/new_menus/src/emu/sound/segapcm.c
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1919      device_sound_interface(mconfig, *this),
2020      m_ram(NULL),
2121      m_rom(NULL),
22      m_bank(0),
2223      m_bankshift(0),
2324      m_bankmask(0),
2425      m_rgnmask(0),
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3435void segapcm_device::device_start()
3536{
3637   int mask, rom_mask, len;
37   const sega_pcm_interface *intf = (const sega_pcm_interface *)static_config();
3838
3939   m_rom = *region();
4040   m_ram = auto_alloc_array(machine(), UINT8, 0x800);
4141
4242   memset(m_ram, 0xff, 0x800);
4343
44   m_bankshift = (UINT8)(intf->bank);
45   mask = intf->bank >> 16;
46   if(!mask)
47      mask = BANK_MASK7>>16;
44   m_bankshift = (UINT8) m_bank;
45   mask = m_bank >> 16;
46   if (!mask)
47      mask = BANK_MASK7 >> 16;
4848
4949   len = region()->bytes();
5050   m_rgnmask = len - 1;
branches/new_menus/src/emu/sound/segapcm.h
r29543r29544
2424#define MCFG_SEGAPCM_REPLACE(_tag, _clock) \
2525   MCFG_DEVICE_REPLACE(_tag, SEGAPCM, _clock)
2626
27#define MCFG_SEGAPCM_BANK(_bank) \
28   segapcm_device::set_bank(*device, _bank);
29
30
2731//**************************************************************************
2832//  TYPE DEFINITIONS
2933//**************************************************************************
3034
31struct sega_pcm_interface
32{
33   int  bank;
34};
35
3635class segapcm_device : public device_t,
3736                  public device_sound_interface
3837{
3938public:
4039   segapcm_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
4140   ~segapcm_device() { }
42
41   
42   // static configuration
43   static void set_bank(device_t &device, int bank) { downcast<segapcm_device &>(device).m_bank = bank; }
44   
45   DECLARE_WRITE8_MEMBER( sega_pcm_w );
46   DECLARE_READ8_MEMBER( sega_pcm_r );
47   
4348protected:
4449   // device-level overrides
4550   virtual void device_start();
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4752   // sound stream update overrides
4853   virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples);
4954
50public:
51   DECLARE_WRITE8_MEMBER( sega_pcm_w );
52   DECLARE_READ8_MEMBER( sega_pcm_r );
53
5455private:
5556   UINT8* m_ram;
5657   UINT8 m_low[16];
5758   const UINT8* m_rom;
59   int m_bank;
5860   int m_bankshift;
5961   int m_bankmask;
6062   int m_rgnmask;
branches/new_menus/src/mess/drivers/fmtowns.c
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20782078}
20792079
20802080// PCM interrupt (IRQ 13)
2081static void towns_pcm_irq(device_t* device, int channel)
2081RF5C68_SAMPLE_END_CB_MEMBER(towns_state::towns_pcm_irq)
20822082{
2083   towns_state* state = device->machine().driver_data<towns_state>();
2084   pic8259_device* pic = state->m_pic_slave;
2085
2086   if(state->m_towns_pcm_channel_mask & (1 << channel))
2083   if (m_towns_pcm_channel_mask & (1 << channel))
20872084   {
2088      state->m_towns_pcm_irq_flag = 1;
2089      state->m_towns_pcm_channel_flag |= (1 << channel);
2090      pic->ir5_w(1);
2085      m_towns_pcm_irq_flag = 1;
2086      m_towns_pcm_channel_flag |= (1 << channel);
2087      m_pic_slave->ir5_w(1);
20912088      if(IRQ_LOG) logerror("PIC: IRQ13 (PCM) set high (channel %i)\n",channel);
20922089   }
20932090}
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26702667   { DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
26712668};
26722669
2673static const rf5c68_interface rf5c68_intf =
2674{
2675   towns_pcm_irq
2676};
2677
26782670static const gfx_layout fnt_chars_16x16 =
26792671{
26802672   16,16,
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27332725   MCFG_SOUND_ADD("fm", YM3438, 53693100 / 7) // actual clock speed unknown
27342726   MCFG_YM2612_IRQ_HANDLER(WRITELINE(towns_state, towns_fm_irq))
27352727   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
2728
27362729   MCFG_RF5C68_ADD("pcm", 53693100 / 7)  // actual clock speed unknown
2737   MCFG_SOUND_CONFIG(rf5c68_intf)
2730   MCFG_RF5C68_SAMPLE_END_CB(towns_state, towns_pcm_irq)
27382731   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.50)
27392732   MCFG_SOUND_ADD("cdda",CDDA,0)
27402733   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
branches/new_menus/src/mess/drivers/pcfx.c
r29543r29544
457457}
458458
459459
460static const huc6261_interface pcfx_huc6261_config =
461{
462   "huc6270_a",
463   "huc6270_b"
464};
465
466
467460void pcfx_state::machine_reset()
468461{
469462   membank( "bank1" )->set_base( memregion("user1")->base() );
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492485   MCFG_DEVICE_ADD( "huc6270_a", HUC6270, 0 )
493486   MCFG_HUC6270_VRAM_SIZE(0x20000)
494487   MCFG_HUC6270_IRQ_CHANGED_CB(WRITELINE(pcfx_state, irq12_w))
488
495489   MCFG_DEVICE_ADD( "huc6270_b", HUC6270, 0 )
496490   MCFG_HUC6270_VRAM_SIZE(0x20000)
497491   MCFG_HUC6270_IRQ_CHANGED_CB(WRITELINE(pcfx_state, irq14_w))
498   MCFG_HUC6261_ADD( "huc6261", XTAL_21_4772MHz, pcfx_huc6261_config )
499   MCFG_HUC6272_ADD( "huc6272", XTAL_21_4772MHz )
500492
493   MCFG_DEVICE_ADD("huc6261", HUC6261, XTAL_21_4772MHz)
494   MCFG_HUC6261_VDC1("huc6270_a")
495   MCFG_HUC6261_VDC2("huc6270_b")
496
497   MCFG_HUC6272_ADD( "huc6272", XTAL_21_4772MHz )
501498MACHINE_CONFIG_END
502499
503500
branches/new_menus/src/mess/drivers/x1twin.c
r29543r29544
514514};
515515
516516
517#if 0
518static const c6280_interface c6280_config =
519{
520   "pce_cpu"
521};
522#endif
523517
524518static MACHINE_CONFIG_START( x1twin, x1twin_state )
525519   /* basic machine hardware */
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599593
600594#if 0
601595   MCFG_SOUND_ADD("c6280", C6280, PCE_MAIN_CLOCK/6)
602//  MCFG_SOUND_CONFIG(c6280_config)
596   MCFG_C6280_CPU("pce_cpu")
603597   MCFG_SOUND_ROUTE(0, "pce_l", 0.5)
604598   MCFG_SOUND_ROUTE(1, "pce_r", 0.5)
605599#endif
branches/new_menus/src/mess/drivers/x68k.c
r29543r29544
13591359   {attotime::from_usec(32),attotime::from_nsec(450),attotime::from_nsec(50),attotime::from_nsec(50)}, // Burst mode timing (guesstimate)
13601360};
13611361
1362static const okim6258_interface x68k_okim6258_interface =
1363{
1364   FOSC_DIV_BY_512,
1365   TYPE_4BITS,
1366   OUTPUT_10BITS,
1367};
1368
13691362static INPUT_PORTS_START( x68000 )
13701363   PORT_START("ctrltype")
13711364   PORT_CONFNAME(0x0f, 0x00, "Joystick Port 1")
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18701863   MCFG_YM2151_PORT_WRITE_HANDLER(WRITE8(x68k_state,x68k_ct_w))  // CT1, CT2 from YM2151 port 0x1b
18711864   MCFG_SOUND_ROUTE(0, "lspeaker", 0.50)
18721865   MCFG_SOUND_ROUTE(1, "rspeaker", 0.50)
1866
18731867   MCFG_OKIM6258_ADD("okim6258", 4000000)
1874   MCFG_SOUND_CONFIG(x68k_okim6258_interface)
1868   MCFG_OKIM6258_DIVIDER(FOSC_DIV_BY_512)
1869   MCFG_OKIM6258_ADPCM_TYPE(TYPE_4BITS)
1870   MCFG_OKIM6258_OUT_BITS(OUTPUT_10BITS)
18751871   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.50)
18761872   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.50)
18771873
branches/new_menus/src/mess/drivers/snes.c
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14611461   INT16 y = ioport(portnames[port][2])->read();
14621462
14631463   /* these are the theoretical boundaries, but we currently are always onscreen... */
1464   if (x < 0 || x >= SNES_SCR_WIDTH || y < 0 || y >= m_ppu.m_beam.last_visible_line)
1464   if (x < 0 || x >= SNES_SCR_WIDTH || y < 0 || y >= m_ppu->m_beam.last_visible_line)
14651465      m_scope[port].offscreen = 1;
14661466   else
14671467      m_scope[port].offscreen = 0;
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14801480
14811481   if (y < 0)
14821482      y = 0;
1483   if (y > (m_ppu.m_beam.last_visible_line - 1))
1484      y = m_ppu.m_beam.last_visible_line - 1;
1483   if (y > (m_ppu->m_beam.last_visible_line - 1))
1484      y = m_ppu->m_beam.last_visible_line - 1;
14851485
1486   m_ppu.m_beam.latch_horz = x;
1487   m_ppu.m_beam.latch_vert = y;
1488   m_ppu.m_stat78 |= 0x40;
1486   m_ppu->m_beam.latch_horz = x;
1487   m_ppu->m_beam.latch_vert = y;
1488   m_ppu->m_stat78 |= 0x40;
14891489}
14901490
14911491void snes_console_state::input_read_sscope(int port)
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19571957   MCFG_SCREEN_RAW_PARAMS(DOTCLK_NTSC * 2, SNES_HTOTAL * 2, 0, SNES_SCR_WIDTH * 2, SNES_VTOTAL_NTSC, 0, SNES_SCR_HEIGHT_NTSC)
19581958   MCFG_SCREEN_UPDATE_DRIVER( snes_state, screen_update )
19591959
1960   MCFG_DEVICE_ADD("ppu", SNES_PPU, 0)
1961   MCFG_SNES_PPU_OPENBUS_CB(READ8(snes_state, snes_open_bus_r))
1962   MCFG_VIDEO_SET_SCREEN("screen")
1963
19601964   /* sound hardware */
19611965   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
19621966   MCFG_SOUND_ADD("spc700", SNES, 0)
branches/new_menus/src/mess/drivers/pve500.c
r29543r29544
6464
6565static Z80CTC_INTERFACE( external_ctc_intf )
6666{
67   DEVCB_NULL, /* interrupt handler */
67   DEVCB_CPU_INPUT_LINE("maincpu", INPUT_LINE_IRQ0), /* interrupt handler */
6868   DEVCB_NULL, /* ZC/TO0 callback */
6969   DEVCB_NULL, /* ZC/TO1 callback */
7070   DEVCB_NULL  /* ZC/TO2 callback */
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7272
7373static const z80sio_interface external_sio_intf =
7474{
75   DEVCB_NULL, /* interrupt handler */
76   DEVCB_NULL, /* DTR changed handler */
75   DEVCB_CPU_INPUT_LINE("maincpu", INPUT_LINE_IRQ0), /* interrupt handler */
76  DEVCB_NULL, /* DTR changed handler */
7777   DEVCB_NULL, /* RTS changed handler */
7878   DEVCB_NULL, /* BREAK changed handler */
7979   DEVCB_NULL, /* transmit handler */
8080   DEVCB_NULL  /* receive handler */
8181};
8282
83static const z80_daisy_config maincpu_daisy_chain[] =
84{
85   { "external_ctc" },
86   { "external_sio" },
87   { NULL }
88};
89
90
8391static ADDRESS_MAP_START(maincpu_io, AS_IO, 8, pve500_state)
8492   AM_RANGE(0x00, 0x03) AM_DEVREADWRITE("external_sio", z80sio_device, read, write)
8593   AM_RANGE(0x08, 0x0B) AM_DEVREADWRITE("external_ctc", z80ctc_device, read, write)
r29543r29544
106114}
107115
108116static INPUT_PORTS_START( pve500 )
109   PORT_START("keyboard")
110   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED ) PORT_NAME("TODO") PORT_CODE(KEYCODE_A)
117   PORT_START("SCAN0")
118   PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("TRANS")       PORT_CODE(KEYCODE_5)
119   PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("A/B")         PORT_CODE(KEYCODE_4)
120   PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("FROM TO")     PORT_CODE(KEYCODE_3)
121   PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("P2")          PORT_CODE(KEYCODE_2)
122   PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("P1")          PORT_CODE(KEYCODE_1)
123   PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_UNUSED)
124   PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_UNUSED)
125   PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ENTRY")       PORT_CODE(KEYCODE_SPACE)
126
127   PORT_START("SCAN1")
128   PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ALL STOP")    PORT_CODE(KEYCODE_M)
129   PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("LAST EDIT")   PORT_CODE(KEYCODE_I)
130   PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("AUDIO SPLIT") PORT_CODE(KEYCODE_T)
131   PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("A2")          PORT_CODE(KEYCODE_9)
132   PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ASMBL")       PORT_CODE(KEYCODE_6)
133   PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("V")           PORT_CODE(KEYCODE_7)
134   PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("A1")          PORT_CODE(KEYCODE_8)
135   PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ENTRY")       PORT_CODE(KEYCODE_SPACE)
136
137   PORT_START("SCAN2")
138   PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("RVW/JUMP")    PORT_CODE(KEYCODE_N)
139   PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("AUTO EDIT")   PORT_CODE(KEYCODE_B)
140   PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("PREVIEW")     PORT_CODE(KEYCODE_V)
141   PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("P-FF")        PORT_CODE(KEYCODE_R)
142   PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("P-REW")       PORT_CODE(KEYCODE_E)
143   PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("P-STILL")     PORT_CODE(KEYCODE_W)
144   PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("P-PLAY")      PORT_CODE(KEYCODE_Q)
145   PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ENTRY")       PORT_CODE(KEYCODE_SPACE)
146
147   PORT_START("SCAN3")
148   PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("R-OUT")       PORT_CODE(KEYCODE_K)
149   PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("R-IN")        PORT_CODE(KEYCODE_J)
150   PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("GO TO")       PORT_CODE(KEYCODE_H)
151   PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("P-OUT")       PORT_CODE(KEYCODE_G)
152   PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("P-IN")        PORT_CODE(KEYCODE_F)
153   PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("TRIM+")       PORT_CODE(KEYCODE_U)
154   PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("TRIM-")       PORT_CODE(KEYCODE_Y)
155   PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ENTRY")       PORT_CODE(KEYCODE_SPACE)
156
157   PORT_START("SCAN4")
158   PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("R-FF")        PORT_CODE(KEYCODE_OPENBRACE)
159   PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("R-REW")       PORT_CODE(KEYCODE_QUOTE)
160   PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("R-STILL")     PORT_CODE(KEYCODE_P)
161   PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("R-PLAY")      PORT_CODE(KEYCODE_O)
162   PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("EDIT")        PORT_CODE(KEYCODE_EQUALS)
163   PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("REC")         PORT_CODE(KEYCODE_MINUS)
164   PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_UNUSED)
165   PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ENTRY")       PORT_CODE(KEYCODE_SPACE)
166
167   PORT_START("SCAN5")
168      PORT_DIPNAME( 0x03, 0x02, "R-EDIT REF" )
169      PORT_DIPSETTING(    0x02, "TC" )
170      PORT_DIPSETTING(    0x00, "RTC" )
171      PORT_DIPSETTING(    0x01, "CTL" )
172
173      PORT_DIPNAME( 0x0C, 0x08, "P2-EDIT REF" )
174      PORT_DIPSETTING(    0x08, "TC" )
175      PORT_DIPSETTING(    0x00, "RTC" )
176      PORT_DIPSETTING(    0x04, "CTL" )
177
178      PORT_DIPNAME( 0x30, 0x20, "P1-EDIT REF" )
179      PORT_DIPSETTING(    0x20, "TC" )
180      PORT_DIPSETTING(    0x00, "RTC" )
181      PORT_DIPSETTING(    0x10, "CTL" )
182
183   PORT_START("SCAN6")
184      PORT_DIPNAME( 0x03, 0x02, "SYNCHRO" )
185      PORT_DIPSETTING(    0x02, "ON/CF" )
186      PORT_DIPSETTING(    0x00, "ON" )
187      PORT_DIPSETTING(    0x01, "OFF" )
188
189      PORT_DIPNAME( 0x0C, 0x08, "PREROLL" )
190      PORT_DIPSETTING(    0x08, "7" )
191      PORT_DIPSETTING(    0x00, "5" )
192      PORT_DIPSETTING(    0x04, "3" )
193
194   PORT_START("SCAN7")
195   PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("TOTAL")       PORT_CODE(KEYCODE_CLOSEBRACE)
196   PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("LEARN")       PORT_CODE(KEYCODE_L)
197   PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("TRANS-1F")    PORT_CODE(KEYCODE_Z)
198   PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("TRANS-10F")   PORT_CODE(KEYCODE_X)
199   PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("TRANS-100F")  PORT_CODE(KEYCODE_C)
200   PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("R-RESET")     PORT_CODE(KEYCODE_A)
201   PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("P2-RESET")    PORT_CODE(KEYCODE_S)
202   PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("P1-RESET")    PORT_CODE(KEYCODE_D)
111203INPUT_PORTS_END
112204
113205void pve500_state::machine_start()
r29543r29544
119211   io_KY = 0;
120212
121213   for (int i=0; i<27; i++)
122      output_set_digit_value(i, 0xff);
214      output_set_digit_value(i, 0x00);
123215}
124216
125217void pve500_state::machine_reset()
r29543r29544
162254      case IO_EXPANDER_PORTB:
163255         return io_LE;
164256      case IO_EXPANDER_PORTC:
257         io_KY = 0x00;
258         if (io_SC & 0x01) io_KY |= ioport("SCAN0")->read();
259         if (io_SC & 0x02) io_KY |= ioport("SCAN1")->read();
260         if (io_SC & 0x04) io_KY |= ioport("SCAN2")->read();
261         if (io_SC & 0x08) io_KY |= ioport("SCAN3")->read();
262         if (io_SC & 0x10) io_KY |= ioport("SCAN4")->read();
263         if (io_SC & 0x20) io_KY |= ioport("SCAN5")->read();
264         if (io_SC & 0x40) io_KY |= ioport("SCAN6")->read();
265         if (io_SC & 0x80) io_KY |= ioport("SCAN7")->read();
165266         return io_KY;
166267      case IO_EXPANDER_PORTD:
167268         return io_LD;
r29543r29544
192293         io_SEL = data;
193294         for (int i=0; i<4; i++){
194295            if (io_SEL & (1 << i)){
195               switch (io_SC){
196                  case 1:   output_set_digit_value(8*i + 0, io_LD & 0x7F); break;
197                  case 2:   output_set_digit_value(8*i + 1, io_LD & 0x7F); break;
198                  case 4:   output_set_digit_value(8*i + 2, io_LD & 0x7F); break;
199                  case 8:   output_set_digit_value(8*i + 3, io_LD & 0x7F); break;
200                  case 16:  output_set_digit_value(8*i + 4, io_LD & 0x7F); break;
201                  case 32:  output_set_digit_value(8*i + 5, io_LD & 0x7F); break;
202                  case 64:  output_set_digit_value(8*i + 6, io_LD & 0x7F); break;
203                  case 128: output_set_digit_value(8*i + 7, io_LD & 0x7F); break;
204                  default:
205                     /*software should not do it.
206               any idea how to emulate that in case it does? */ break;
296               for (int j=0; j<8; j++){
297                  if (io_SC & (1<<j)){
298                     output_set_digit_value(8*i + j, BITSWAP8(io_LD & 0x7F, 7, 0, 1, 2, 3, 4, 5, 6));
299                     printf("io_expander_w PORTE data=%02X\n", data);
300                  }
207301               }
208302            }
209303         }
r29543r29544
217311   MCFG_CPU_ADD("maincpu", TLCS_Z80, XTAL_12MHz / 2) /* TMPZ84C015BF-6 (TOSHIBA TLCS-Z80) */
218312   MCFG_CPU_PROGRAM_MAP(maincpu_prg)
219313   MCFG_CPU_IO_MAP(maincpu_io)
314   MCFG_CPU_CONFIG(maincpu_daisy_chain)
220315   MCFG_Z80CTC_ADD("external_ctc", XTAL_12MHz / 2, external_ctc_intf)
221316   MCFG_Z80SIO_ADD("external_sio", XTAL_12MHz / 2, external_sio_intf)
222317
branches/new_menus/src/mess/drivers/nes.c
r29543r29544
640640INPUT_PORTS_END
641641
642642
643static const nesapu_interface nes_apu_interface =
644{
645   "maincpu"
646};
647
648
649643void nes_state::ppu_nmi(int *ppu_regs)
650644{
651645   m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
r29543r29544
693687   MCFG_SCREEN_UPDATE_DRIVER(nes_state, screen_update_nes)
694688   MCFG_SCREEN_PALETTE("palette")
695689
696
697690   MCFG_PALETTE_ADD("palette", 4*16*8)
698691   MCFG_PALETTE_INIT_OWNER(nes_state, nes)
699692
r29543r29544
704697   /* sound hardware */
705698   MCFG_SPEAKER_STANDARD_MONO("mono")
706699   MCFG_SOUND_ADD("nessound", NES_APU, NTSC_CLOCK)
707   MCFG_SOUND_CONFIG(nes_apu_interface)
700   MCFG_NES_APU_CPU("maincpu")
708701   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90)
709702
710703   MCFG_NES_CARTRIDGE_ADD("nes_slot", nes_cart, NULL)
r29543r29544
735728
736729   /* sound hardware */
737730   MCFG_SOUND_REPLACE("nessound", NES_APU, PAL_CLOCK)
738   MCFG_SOUND_CONFIG(nes_apu_interface)
731   MCFG_NES_APU_CPU("maincpu")
739732   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90)
740733MACHINE_CONFIG_END
741734
r29543r29544
757750
758751   /* sound hardware */
759752   MCFG_SOUND_REPLACE("nessound", NES_APU, 26601712/15) /* 26.601712MHz / 15 == 1.77344746666... MHz */
760   MCFG_SOUND_CONFIG(nes_apu_interface)
753   MCFG_NES_APU_CPU("maincpu")
761754   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90)
762755MACHINE_CONFIG_END
763756
branches/new_menus/src/mess/drivers/pce.c
r29543r29544
284284ADDRESS_MAP_END
285285
286286
287static const c6280_interface c6280_config =
288{
289   "maincpu"
290};
291
292287UINT32 pce_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
293288{
294289   m_huc6260->video_update( bitmap, cliprect );
r29543r29544
337332
338333   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
339334   MCFG_SOUND_ADD(C6280_TAG, C6280, MAIN_CLOCK/6)
340   MCFG_SOUND_CONFIG(c6280_config)
335   MCFG_C6280_CPU("maincpu")
341336   MCFG_SOUND_ROUTE( 0, "lspeaker", 1.00 )
342337   MCFG_SOUND_ROUTE( 1, "rspeaker", 1.00 )
343338
r29543r29544
402397
403398   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
404399   MCFG_SOUND_ADD(C6280_TAG, C6280, MAIN_CLOCK/6)
405   MCFG_SOUND_CONFIG(c6280_config)
400   MCFG_C6280_CPU("maincpu")
406401   MCFG_SOUND_ROUTE(0, "lspeaker", 1.00)
407402   MCFG_SOUND_ROUTE(1, "rspeaker", 1.00)
408403
branches/new_menus/src/mess/drivers/rainbow.c
r29543r29544
168168W17 pulls J1 serial  port pin 1 to GND when set (chassis to logical GND).
169169****************************************************************************/
170170
171// Define standard and maximum RAM sizes (A, then B model):
172//#define BOARD_RAM 0x10000  // 64 K base RAM  (100-A)
173//#define END_OF_RAM 0xcffff // very last byte (100-A) DO NOT CHANGE.
174
175// DEC-100-B probes until a 'flaky' area is found (BOOT ROM around F400:0E04).
176// It is no longer possible to key in the RAM size from within the 100-B BIOS.
177#define BOARD_RAM 0x20000  // 128 K base RAM (100-B)
178#define END_OF_RAM 0xdffff // very last byte (100-B) DO NOT CHANGE.
179
180// TROUBLESHOOTING RAM
181// Unexpected low RAM sizes are an indication of option RAM (at worst: 128 K on board) failure.
182// While motherboard errors often render the system unbootable, bad option RAM (> 128 K)
183// can be narrowed down with the Diagnostic Disk and codes from the 'Pocket Service Guide'
184// EK-PC100-PS-002 (APPENDIX B.2.2); pc100ps2.pdf
185
186
171187// Workaround DOES NOT APPLY to the 190-B ROM. Only enable when compiling the 'rainbow' driver -
172188//#define FORCE_RAINBOW_100_LOGO
173189
r29543r29544
203219      m_inp7(*this, "GRAPHICS OPTION"),
204220      m_inp8(*this, "MEMORY PRESENT"),
205221      m_inp9(*this, "MONITOR TYPE"),
222      m_inp10(*this, "J17"),
206223
207224      m_crtc(*this, "vt100_video"),
208225      m_i8088(*this, "maincpu"),
r29543r29544
232249   DECLARE_READ8_MEMBER(share_z80_r);
233250   DECLARE_WRITE8_MEMBER(share_z80_w);
234251
235   DECLARE_READ8_MEMBER(floating_bus_r);
236   DECLARE_WRITE8_MEMBER(floating_bus_w);
237
238252   DECLARE_READ8_MEMBER(hd_status_68_r);
239253
240254   DECLARE_READ8_MEMBER(i8088_latch_r);
r29543r29544
285299   required_ioport m_inp7;
286300   required_ioport m_inp8;
287301   required_ioport m_inp9;
302   required_ioport m_inp10;
288303
289304   required_device<rainbow_video_device> m_crtc;
290305   required_device<cpu_device> m_i8088;
r29543r29544
368383static ADDRESS_MAP_START( rainbow8088_map, AS_PROGRAM, 8, rainbow_state)
369384   ADDRESS_MAP_UNMAP_HIGH
370385   AM_RANGE(0x00000, 0x0ffff) AM_RAM AM_SHARE("sh_ram")
371   AM_RANGE(0x10000, 0x1ffff) AM_RAM
386   AM_RANGE(0x10000, END_OF_RAM) AM_RAM
372387
373   // test at f4e00 - f4e1c
374   AM_RANGE(0x20000, 0xdffff) AM_READWRITE(floating_bus_r,floating_bus_w)
375   AM_RANGE(0x20000, 0xdffff) AM_RAM
376
377388   // Documentation claims there is a 256 x 4 bit NVRAM from 0xed000 to 0xed040 (*)
378389   //   shadowed at $ec000 - $ecfff and from $ed040 - $edfff.
379390
r29543r29544
475486      PORT_DIPSETTING(    0x02, "GREEN" )
476487      PORT_DIPSETTING(    0x03, "AMBER" )
477488
489   // MEMORY, FLOPPY, BUNDLE, GRAPHICS affect 'system_parameter_r':
478490      PORT_START("MEMORY PRESENT")
479      PORT_DIPNAME( 0xF000, 0x2000, "MEMORY PRESENT")
480      PORT_DIPSETTING(    0x2000, "128 K (BOARD DEFAULT)" ) // NOTE: 0x2000 hard coded in 'system_parameter_r'
481      PORT_DIPSETTING(    0x3000, "192 K (MEMORY OPTION)" )
482      PORT_DIPSETTING(    0x4000, "256 K (MEMORY OPTION)" )
483      PORT_DIPSETTING(    0x5000, "320 K (MEMORY OPTION)" )
484      PORT_DIPSETTING(    0x6000, "384 K (MEMORY OPTION)" )
485      PORT_DIPSETTING(    0x7000, "448 K (MEMORY OPTION)" )
486      PORT_DIPSETTING(    0x8000, "512 K (MEMORY OPTION)" )
487      PORT_DIPSETTING(    0x9000, "576 K (MEMORY OPTION)" )
488      PORT_DIPSETTING(    0xA000, "640 K (MEMORY OPTION)" )
489      PORT_DIPSETTING(    0xB000, "704 K (MEMORY OPTION)" )
490      PORT_DIPSETTING(    0xC000, "768 K (MEMORY OPTION)" )
491      PORT_DIPSETTING(    0xD000, "832 K (MEMORY OPTION)" )
492      PORT_DIPSETTING(    0xE000, "896 K (MEMORY OPTION)" )
491      PORT_DIPNAME( 0xF0000, 0x20000, "MEMORY PRESENT")
492      PORT_DIPSETTING(    0x10000, "64  K (MINIMUM ON 100-A)" ) // see BOARD_RAM
493      PORT_DIPSETTING(    0x20000, "128 K (MINIMUM ON 100-B)" )
494      PORT_DIPSETTING(    0x30000, "192 K (MEMORY OPTION)" )
495      PORT_DIPSETTING(    0x40000, "256 K (MEMORY OPTION)" )
496      PORT_DIPSETTING(    0x50000, "320 K (MEMORY OPTION)" )
497      PORT_DIPSETTING(    0x60000, "384 K (MEMORY OPTION)" )
498      PORT_DIPSETTING(    0x70000, "448 K (MEMORY OPTION)" )
499      PORT_DIPSETTING(    0x80000, "512 K (MEMORY OPTION)" )
500      PORT_DIPSETTING(    0x90000, "576 K (MEMORY OPTION)" )
501      PORT_DIPSETTING(    0xA0000, "640 K (MEMORY OPTION)" )
502      PORT_DIPSETTING(    0xB0000, "704 K (MEMORY OPTION)" )
503      PORT_DIPSETTING(    0xC0000, "768 K (MEMORY OPTION)" )
504      PORT_DIPSETTING(    0xD0000, "832 K (MAX.MEM.ON -A)" ) // see END_OF_RAM
505      PORT_DIPSETTING(    0xE0000, "896 K (MAX.MEM.ON -B)" )
493506
494      PORT_START("GRAPHICS OPTION")
495      PORT_DIPNAME( 0x00, 0x00, "GRAPHICS OPTION") PORT_TOGGLE
496      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
497      PORT_DIPSETTING(    0x04, DEF_STR( On ) )
507   // Floppy is always 'on', BUNDLE + GRAPHICS are not implemented yet:
508      PORT_START("FLOPPY CONTROLLER")
509      PORT_DIPNAME( 0x01, 0x01, "FLOPPY CONTROLLER") PORT_TOGGLE
510      PORT_DIPSETTING(    0x01, DEF_STR( On ) )
498511
499512      PORT_START("BUNDLE OPTION")
500513      PORT_DIPNAME( 0x00, 0x00, "BUNDLE OPTION") PORT_TOGGLE
501514      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
502515      PORT_DIPSETTING(    0x01, DEF_STR( On ) )
503516
504   PORT_START("W13") // W13 - W18 affect 'system_parameter_r'
517      PORT_START("GRAPHICS OPTION")
518      PORT_DIPNAME( 0x00, 0x00, "GRAPHICS OPTION") PORT_TOGGLE
519      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
520      PORT_DIPSETTING(    0x01, DEF_STR( On ) )
521     
522   // W13 - W18 are used for factory tests   and affect the boot process -
523   PORT_START("W13")
505524      PORT_DIPNAME( 0x02, 0x02, "W13 (FACTORY TEST A, LEAVE OFF)") PORT_TOGGLE
506525      PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
507526      PORT_DIPSETTING(    0x00, DEF_STR( On ) )
r29543r29544
522541      PORT_WRITE_LINE_DEVICE_MEMBER("kbdser", i8251_device, write_dsr)
523542
524543   // J17 jumper on FDC controller board shifts drive select (experimental) -
525   PORT_START("FLOPPY CONTROLLER")
544   PORT_START("J17")
526545      PORT_DIPNAME( 0x02, 0x00, "J17 DRIVE SELECT (A => C and B => D)") PORT_TOGGLE
527546      PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
528547      PORT_DIPSETTING(    0x02, DEF_STR( On ) )
r29543r29544
548567
549568void rainbow_state::machine_reset()
550569{
570   /* configure RAM */
571   address_space &program = m_maincpu->space(AS_PROGRAM);
572   if (m_inp8->read() < END_OF_RAM)
573   {   program.unmap_readwrite(m_inp8->read(), END_OF_RAM);
574   }
575
551576   if (COLD_BOOT == 1)
552577   {
553578      COLD_BOOT = 2;
r29543r29544
603628   return 0;
604629}
605630
606// It is no longer possible to key in the RAM size on the 100-B.
607// The DEC-100-B boot ROM probes until a 'flaky' area is found (around F400:0E04).
608
609// Unexpected low RAM sizes are an indication of option RAM (at worst: 128 K on board) failure.
610// While motherboard errors often render the system unbootable, bad option RAM (> 128 K)
611// can be narrowed down with the Diagnostic Disk and codes from the 'Pocket Service Guide'
612// EK-PC100-PS-002 (APPENDIX B.2.2); pc100ps2.pdf
613// ================================================================
614// - Simulate floating bus for initial RAM detection -
615// FIXME: code valid ONLY within ROM section F4Exxx.
616//
617// NOTE: MS-DOS 2.x unfortunately probes RAM in a similar way.
618// => SET OPTION RAM to 896 K for unknown applications (and DOS) <=
619// ================================================================
620READ8_MEMBER(rainbow_state::floating_bus_r)
621{
622   int pc = space.device().safe_pc();
623
624   if ( ((pc & 0xFFF00) == 0xF4E00) &&
625         ( m_maincpu->state_int(I8086_DS) >= m_inp8->read() )
626      )
627   {
628      return (offset>>16) + 2;
629   }
630   else
631      return space.read_byte(offset);
632}
633
634WRITE8_MEMBER(rainbow_state::floating_bus_w)
635{
636      space.write_byte(offset,data);
637}
638
639631// interrupt handling and arbitration.  priorities currently unknown.
640632void rainbow_state::update_8088_irqs()
641633{
r29543r29544
746738    B F G M
747739   ( 1 means NOT present )
748740*/
749   // Hard coded value 0x2000 - see DIP switch setup!
750   return 0x0f - m_inp5->read()
751            - 0                 // floppy is hard coded in emulator.
752            - m_inp7->read()
753            - ((m_inp8->read() > 0x2000) ? 8 : 0);
741   return   (((m_inp5->read() == 1)      ? 0 : 1)  |
742       ((m_inp6->read() == 1)      ? 0 : 2)  |
743       ((m_inp7->read() == 1)      ? 0 : 4)  |
744       ((m_inp8->read() > BOARD_RAM)   ? 0 : 8)
745      );
754746}
755747
756748READ8_MEMBER(rainbow_state::comm_control_r)
r29543r29544
951943   int force_ready = ( (data & 4) != 0 ) ? 0 : 1;
952944
953945   int drive;
954   if ( m_inp6->read() && ((data & 3) < 2) )
946   if ( m_inp10->read() && ((data & 3) < 2) )
955947      drive = (data & 1) + 2;
956948   else
957949      drive = data & 3;
r29543r29544
12361228// 'Rainbow 100-A' (introduced May 1982) is first-generation hardware with ROM 04.03.11
12371229// - 64 K base RAM on board (instead of 128 K on 'B' model).  832 K RAM max.
12381230// - inability to boot from hard disc (mind the inadequate PSU)
1239// - cannot control bit 7 of IRQ vector (prevents DOS 2.0x from booting on unmodified hardware)
1231// - cannot control bit 7 of IRQ vector (prevents DOS >= 2.05 from booting on unmodified hardware)
12401232// - limited palette with color graphics option (4 instead of 16 colors)
12411233// - smaller ROMs (3 x 2764) with fewer routines (no documented way to beep...)
12421234
branches/new_menus/src/mess/mess.mak
r29543r29544
301301VIDEOS += SED1200
302302VIDEOS += SED1330
303303VIDEOS += SED1520
304VIDEOS += SNES_PPU
304305VIDEOS += STVVDP
305306VIDEOS += T6A04
306307#VIDEOS += TLC34076
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795796   $(MAME_VIDEO)/ppu2c0x.o     \
796797   $(MAME_AUDIO)/snes_snd.o    \
797798   $(MAME_MACHINE)/snes.o      \
798   $(MAME_VIDEO)/snes.o        \
799799   $(MAME_MACHINE)/n64.o       \
800800   $(MAME_VIDEO)/n64.o         \
801801   $(MAME_VIDEO)/rdpblend.o    \
branches/new_menus/src/mess/machine/dec_lk201.c
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226226//  INPUT_PORTS( lk201 )
227227//-------------------------------------------------
228228
229/* [Foreign language caps] are referenced in software titles. Please leave them in.
230
231   DEC omitted terms like 'Interrupt', 'Break' and 'Data / Talk' on some keyboards,
232   so Fn numbers are definitely important for end users.
233 
234   === CURRENT SPECIAL KEYS ===
235   [PC-AT] ......=> [DEC]
236   LEFT CONTROL..=> Control
237   LEFT ALT .....=> Compose
238   
239   RIGHT ALT ....=> Help
240   RIGHT CONTROL => Do
241   ==============================================================================================
242   === (PC - AT ) keys above cursor block ===
243   * KEYCODE_INSERT * KEYCODE_HOME * KEYCODE_PGUP
244   * KEYCODE_DEL... * KEYCODE_END  * KEYCODE_PGDN
245
246   === (DEC LK 201 layout above cursor) ===
247   * Find   ........| Insert Here  | Remove
248   * Select.........| Prev   ..... | Next
249   ==============================================================================================
250   === CURRENT NUM PAD ASSIGNMENTS ===
251   [PF1] to [PF4] are mapped to NUM LOCK, SLASH etc. (=> 4 keys on top on num pad).
252   Num pad '+' gives         ',' on the DEC. 
253           ',' translates to '.' (=> more or less the layout of model 'LK-201-AG')
254         
255   Switch between 'full' and 'partial keyboard emulation' with Scroll Lock.
256*/
257
229258INPUT_PORTS_START( lk201 )
230259   PORT_START("KBD0")
231260   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED )
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245274   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNUSED )
246275   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Compose") PORT_CODE(KEYCODE_LALT)
247276   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Caps Lock") PORT_CODE(KEYCODE_CAPSLOCK)
248   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Ctrl") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL)
277   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Ctrl") PORT_CODE(KEYCODE_LCONTROL)
249278
250279   PORT_START("KBD2")
251280   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Z") PORT_CODE(KEYCODE_Z)
252281   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("A") PORT_CODE(KEYCODE_A)
253282   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Q") PORT_CODE(KEYCODE_Q)
254283   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("1") PORT_CODE(KEYCODE_1)
255   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Esc") PORT_CODE(KEYCODE_TILDE)
284   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Tilde") PORT_CODE(KEYCODE_TILDE) // E00
256285   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNUSED )
257286   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNUSED )
258287   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
259288
260289   PORT_START("KBD3")
261   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("<")
290   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("<") PORT_CODE(KEYCODE_BACKSLASH2) // B00
262291   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("X") PORT_CODE(KEYCODE_X)
263292   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("S") PORT_CODE(KEYCODE_S)
264293   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("W") PORT_CODE(KEYCODE_W)
265294   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Tab") PORT_CODE(KEYCODE_TAB)
266295   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNUSED )
267   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Z") PORT_CODE(KEYCODE_2)
268   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Hold Screen") PORT_CODE(KEYCODE_F1)
296   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("2") PORT_CODE(KEYCODE_2)
297   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Hold Screen (F1)") PORT_CODE(KEYCODE_F1)
269298
270299   PORT_START("KBD4")
271300   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("C") PORT_CODE(KEYCODE_C)
272301   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("D") PORT_CODE(KEYCODE_D)
273302   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("E") PORT_CODE(KEYCODE_E)
274303   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("3") PORT_CODE(KEYCODE_3)
275   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Setup") PORT_CODE(KEYCODE_F3)
304   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Setup (F3)") PORT_CODE(KEYCODE_F3)
276305   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNUSED )
277   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Print Screen") PORT_CODE(KEYCODE_F2)
306   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Print Screen (F2)") PORT_CODE(KEYCODE_F2)
278307   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
279308
280309   PORT_START("KBD5")
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284313   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("R") PORT_CODE(KEYCODE_R)
285314   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("4") PORT_CODE(KEYCODE_4)
286315   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNUSED )
287   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Break") PORT_CODE(KEYCODE_F5)
288   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("F4") PORT_CODE(KEYCODE_F4)
316   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Break (F5)") PORT_CODE(KEYCODE_F5)
317   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Data / Talk (F4)") PORT_CODE(KEYCODE_F4)
289318
290319   PORT_START("KBD6")
291320   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("B") PORT_CODE(KEYCODE_B)
292321   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("G") PORT_CODE(KEYCODE_G)
293322   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("T") PORT_CODE(KEYCODE_T)
294323   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("5") PORT_CODE(KEYCODE_5)
295   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Interrupt") PORT_CODE(KEYCODE_F6)
324   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Interrupt (F6) [X]") PORT_CODE(KEYCODE_F6)
296325   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNUSED )
297326   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNUSED )
298327   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
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302331   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("H") PORT_CODE(KEYCODE_H)
303332   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Y") PORT_CODE(KEYCODE_Y)
304333   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("6") PORT_CODE(KEYCODE_6)
305   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Resume") PORT_CODE(KEYCODE_F7)
334   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Resume (F7) [Fortsetzen]") PORT_CODE(KEYCODE_F7)
306335   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNUSED )
307   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Cancel") PORT_CODE(KEYCODE_F8)
336   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Cancel (F8) [Zuruecknehmen]") PORT_CODE(KEYCODE_F8)
308337   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
309338
310339   PORT_START("KBD8")
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312341   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("J") PORT_CODE(KEYCODE_J)
313342   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("U") PORT_CODE(KEYCODE_U)
314343   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("7") PORT_CODE(KEYCODE_7)
315   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Exit") PORT_CODE(KEYCODE_F10)
344   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Exit (F10) [Fertig]") PORT_CODE(KEYCODE_F10)
316345   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNUSED )
317   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Main Screen") PORT_CODE(KEYCODE_F9)
346   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Main Screen (F9) [Hauptbild]") PORT_CODE(KEYCODE_F9)
318347   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
319348
320349   PORT_START("KBD9")
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324353   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("8") PORT_CODE(KEYCODE_8)
325354   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNUSED )
326355   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNUSED )
327   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("F11") PORT_CODE(KEYCODE_F11)
356   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("ESC (F11)") PORT_CODE(KEYCODE_F11)
328357   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
329358
330359   PORT_START("KBD10")
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332361   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("L") PORT_CODE(KEYCODE_L)
333362   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("O") PORT_CODE(KEYCODE_O)
334363   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("9") PORT_CODE(KEYCODE_9)
335   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("F13") PORT_CODE(KEYCODE_PRTSCR)
364   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("LF (F13)") PORT_CODE(KEYCODE_PRTSCR)
336365   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNUSED )
337   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("F12") PORT_CODE(KEYCODE_F12)
366   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("BS (F12)") PORT_CODE(KEYCODE_F12)
338367   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
339368
340369   PORT_START("KBD11")
341   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("/") PORT_CODE(KEYCODE_SLASH)
342   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME(";") PORT_CODE(KEYCODE_COLON)
370   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("/") PORT_CODE(KEYCODE_SLASH) 
371   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME(";") PORT_CODE(KEYCODE_COLON)     
343372   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED ) // FIXME - duplicate "Return"
344373   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("P") PORT_CODE(KEYCODE_P)
345374   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("0") PORT_CODE(KEYCODE_0)
346375   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNUSED )
347   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Delete") PORT_CODE(KEYCODE_BACKSPACE)
348   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Additional Options (F14)") PORT_CODE(KEYCODE_SCRLOCK)
376   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Delete <X") PORT_CODE(KEYCODE_BACKSPACE)
377   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Additional Options (F14) [Zusaetze]") PORT_CODE(KEYCODE_PAUSE)
349378
350379   PORT_START("KBD12")
351380   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("\\") PORT_CODE(KEYCODE_BACKSLASH)
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362391   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_UNUSED )
363392   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("'") PORT_CODE(KEYCODE_QUOTE)
364393   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("[") PORT_CODE(KEYCODE_OPENBRACE)
365   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Previous") PORT_CODE(KEYCODE_END)
366   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Do (F16)")
394   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Previous [^]") PORT_CODE(KEYCODE_END)
395   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Do (F16) [Ausfuehren]") PORT_CODE(KEYCODE_RCONTROL)
367396   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("-") PORT_CODE(KEYCODE_MINUS)
368397   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Insert Here") PORT_CODE(KEYCODE_HOME)
369398
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374403   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Num 7") PORT_CODE(KEYCODE_7_PAD)
375404   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Up") PORT_CODE(KEYCODE_UP)
376405   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Remove") PORT_CODE(KEYCODE_PGUP)
377   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Next") PORT_CODE(KEYCODE_PGDN)
406   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Next [v]") PORT_CODE(KEYCODE_PGDN)
378407   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("PF1") PORT_CODE(KEYCODE_NUMLOCK)
379408
380409   PORT_START("KBD15")
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400429   PORT_START("KBD17")
401430   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Enter") PORT_CODE(KEYCODE_ENTER_PAD)
402431   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Num ,") PORT_CODE(KEYCODE_PLUS_PAD)
403   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Num -")
432   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Num -") // duplicate...see KBD13
404433   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("PF4") PORT_CODE(KEYCODE_MINUS_PAD)
405   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("F20") PORT_CODE(KEYCODE_PAUSE)
434   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("F20")
406435   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNUSED )
407436   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("F19")
408437   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
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720749
721750//  printf("SPI %02x to %x (PC=%x)\n", data, offset, m_maincpu->pc());
722751}
752
branches/new_menus/src/mess/includes/fmtowns.h
r29543r29544
272272   DECLARE_WRITE_LINE_MEMBER(mb8877a_drq_w);
273273   DECLARE_WRITE_LINE_MEMBER(pit_out2_changed);
274274
275   RF5C68_SAMPLE_END_CB_MEMBER(towns_pcm_irq);
276
275277   void towns_update_video_banks(address_space&);
276278   void init_serial_rom();
277279   void init_rtc();
branches/new_menus/src/mame/mame.lst
r29543r29544
30693069cawingbl        // bootleg
30703070cawingb2        // bootleg
30713071nemo            // 30/11/1990 (c) 1990 (World)
3072nemoa         // 09/11/1990 (c) 1990 (World)
30723073nemoj           // 20/11/1990 (c) 1990 (Japan)
30733074sf2             // 22/05/1991 (c) 1991 (World)
30743075sf2eb           // 14/02/1991 (c) 1991 (World)
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1086710868pepp0224        // (c) 1987 IGT - International Game Technology
1086810869pepp0224a       // (c) 1987 IGT - International Game Technology
1086910870pepp0230        // (c) 1987 IGT - International Game Technology
10871pepp0242        // (c) 1987 IGT - International Game Technology
1087010872pepp0249        // (c) 1987 IGT - International Game Technology
1087110873pepp0250        // (c) 1987 IGT - International Game Technology
1087210874pepp0265        // (c) 1987 IGT - International Game Technology
1087310875pepp0265a       // (c) 1987 IGT - International Game Technology
1087410876pepp0274        // (c) 1987 IGT - International Game Technology
10877pepp0288        // (c) 1987 IGT - International Game Technology
1087510878pepp0290        // (c) 1987 IGT - International Game Technology
1087610879pepp0291        // (c) 1987 IGT - International Game Technology
1087710880pepp0409        // (c) 1987 IGT - International Game Technology
r29543r29544
1088410887pepp0426        // (c) 1987 IGT - International Game Technology
1088510888pepp0428        // (c) 1987 IGT - International Game Technology
1088610889pepp0429        // (c) 1987 IGT - International Game Technology
10890pepp0431        // (c) 1987 IGT - International Game Technology
1088710891pepp0434        // (c) 1987 IGT - International Game Technology
1088810892pepp0447        // (c) 1987 IGT - International Game Technology
1088910893pepp0447a       // (c) 1987 IGT - International Game Technology
1089010894pepp0449        // (c) 1987 IGT - International Game Technology
10895pepp0449a       // (c) 1987 IGT - International Game Technology
1089110896pepp0452        // (c) 1987 IGT - International Game Technology
1089210897pepp0454        // (c) 1987 IGT - International Game Technology
1089310898pepp0455        // (c) 1987 IGT - International Game Technology
r29543r29544
1097010975pex0055pq       // (c) 1995 IGT - International Game Technology
1097110976pex0055pr       // (c) 1995 IGT - International Game Technology
1097210977pex0060p        // (c) 1995 IGT - International Game Technology
10978pex0150p        // (c) 1995 IGT - International Game Technology
1097310979pex0158p        // (c) 1995 IGT - International Game Technology
1097410980pex0171p        // (c) 1995 IGT - International Game Technology
1097510981pex0188p        // (c) 1995 IGT - International Game Technology
r29543r29544
1097810984pex0203p        // (c) 1995 IGT - International Game Technology
1097910985pex0224p        // (c) 1995 IGT - International Game Technology
1098010986pex0225p        // (c) 1995 IGT - International Game Technology
10987pex0242p        // (c) 1995 IGT - International Game Technology
1098110988pex0265p        // (c) 1995 IGT - International Game Technology
1098210989pex0291p        // (c) 1995 IGT - International Game Technology
1098310990pex0417p        // (c) 1995 IGT - International Game Technology
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1099411001pex0508p        // (c) 1995 IGT - International Game Technology
1099511002pex0514p        // (c) 1995 IGT - International Game Technology
1099611003pex0515p        // (c) 1995 IGT - International Game Technology
11004pex0516p        // (c) 1995 IGT - International Game Technology
1099711005pex0536p        // (c) 1995 IGT - International Game Technology
1099811006pex0537p        // (c) 1995 IGT - International Game Technology
1099911007pex0568p        // (c) 1995 IGT - International Game Technology
r29543r29544
1101011018pex2031p        // (c) 1995 IGT - International Game Technology
1101111019pex2035p        // (c) 1995 IGT - International Game Technology
1101211020pex2036p        // (c) 1995 IGT - International Game Technology
11021pex2038p        // (c) 1995 IGT - International Game Technology
1101311022pex2040p        // (c) 1995 IGT - International Game Technology
1101411023pex2042p        // (c) 1995 IGT - International Game Technology
1101511024pex2043p        // (c) 1995 IGT - International Game Technology
11025pex2044p        // (c) 1995 IGT - International Game Technology
1101611026pex2045p        // (c) 1995 IGT - International Game Technology
1101711027pex2066p        // (c) 1995 IGT - International Game Technology
1101811028pex2067p        // (c) 1995 IGT - International Game Technology
r29543r29544
1103011040pex2245pa       // (c) 1995 IGT - International Game Technology
1103111041pex2250p        // (c) 1995 IGT - International Game Technology
1103211042pex2251p        // (c) 1995 IGT - International Game Technology
11043pex2272p        // (c) 1995 IGT - International Game Technology
11044pex2275p        // (c) 1995 IGT - International Game Technology
1103311045pex2283p        // (c) 1995 IGT - International Game Technology
1103411046pex2284p        // (c) 1995 IGT - International Game Technology
1103511047pex2302p        // (c) 1995 IGT - International Game Technology
1103611048pex2303p        // (c) 1995 IGT - International Game Technology
11049pex2306p        // (c) 1995 IGT - International Game Technology
1103711050pex2307p        // (c) 1995 IGT - International Game Technology
11051pex2310p        // (c) 1995 IGT - International Game Technology
1103811052pex2314p        // (c) 1995 IGT - International Game Technology
1103911053pex2374p        // (c) 1995 IGT - International Game Technology
1104011054pex2377p        // (c) 1995 IGT - International Game Technology
r29543r29544
1105311067pexm006p        // (c) 1997 IGT - International Game Technology
1105411068pexm007p        // (c) 1997 IGT - International Game Technology
1105511069pexm008p        // (c) 1997 IGT - International Game Technology
11070pexmp013        // (c) 1997 IGT - International Game Technology
1105611071pexmp017        // (c) 1997 IGT - International Game Technology
1105711072pexmp017a       // (c) 1997 IGT - International Game Technology
1105811073pexmp017b       // (c) 1997 IGT - International Game Technology
11074pexmp026        // (c) 1997 IGT - International Game Technology
1105911075pexmp030        // (c) 1997 IGT - International Game Technology
1106011076
1106111077elgrande        // (c) 1982 Tuni Electro Service / E.T. Marketing
branches/new_menus/src/mame/audio/dkong.c
r29543r29544
13341334 *
13351335 *************************************/
13361336
1337static const nesapu_interface nes_interface_1 = { "n2a03a" };
1338static const nesapu_interface nes_interface_2 = { "n2a03b" };
1339
13401337const tms5110_interface tms_interface = {
13411338   NULL,
13421339   NULL,
r29543r29544
14691466
14701467   MCFG_SPEAKER_STANDARD_MONO("mono")
14711468   MCFG_SOUND_ADD("nesapu1", NES_APU, N2A03_DEFAULTCLOCK)
1472   MCFG_SOUND_CONFIG(nes_interface_1)
1469   MCFG_NES_APU_CPU("n2a03a")
14731470   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
14741471
14751472   MCFG_SOUND_ADD("nesapu2", NES_APU, N2A03_DEFAULTCLOCK)
1476   MCFG_SOUND_CONFIG(nes_interface_2)
1473   MCFG_NES_APU_CPU("n2a03b")
14771474   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
14781475
14791476MACHINE_CONFIG_END
branches/new_menus/src/mame/machine/snes.c
r29543r29544
2323#define __MACHINE_SNES_C
2424
2525#include "emu.h"
26#include "cpu/superfx/superfx.h"
27#include "cpu/g65816/g65816.h"
28#include "cpu/upd7725/upd7725.h"
2926#include "includes/snes.h"
30#include "audio/snes_snd.h"
3127
3228
3329#define DMA_REG(a) m_dma_regs[a - 0x4300]   // regs 0x4300-0x437f
3430
35void snes_state::video_start()
36{
37   m_ppu.ppu_start(m_screen,this);
38}
39
4031UINT32 snes_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
4132{
4233   /* NTSC SNES draw range is 1-225. */
4334   for (int y = cliprect.min_y; y <= cliprect.max_y; y++)
44      m_ppu.refresh_scanline(machine(), bitmap, y + 1);
35      m_ppu->refresh_scanline(machine(), bitmap, y + 1);
4536
4637   return 0;
4738}
r29543r29544
9687{
9788   // latch the counters and pull IRQ
9889   // (don't need to switch to the 65816 context, we don't do anything dependant on it)
99   m_ppu.latch_counters(machine());
90   m_ppu->latch_counters(machine());
10091   SNES_CPU_REG(TIMEUP) = 0x80;    /* Indicate that irq occurred */
10192   m_maincpu->set_input_line(G65816_LINE_IRQ, ASSERT_LINE);
10293
r29543r29544
114105   // make sure we're in the 65816's context since we're messing with the OAM and stuff
115106   address_space &space = m_maincpu->space(AS_PROGRAM);
116107
117   if (!(m_ppu.m_screen_disabled)) //Reset OAM address, byuu says it happens at H=10
108   if (!(m_ppu->m_screen_disabled)) //Reset OAM address, byuu says it happens at H=10
118109   {
119      space.write_byte(OAMADDL, m_ppu.m_oam.saved_address_low); /* Reset oam address */
120      space.write_byte(OAMADDH, m_ppu.m_oam.saved_address_high);
121      m_ppu.m_oam.first_sprite = m_ppu.m_oam.priority_rotation ? (m_ppu.m_oam.address >> 1) & 127 : 0;
110      space.write_byte(OAMADDL, m_ppu->m_oam.saved_address_low); /* Reset oam address */
111      space.write_byte(OAMADDH, m_ppu->m_oam.saved_address_high);
112      m_ppu->m_oam.first_sprite = m_ppu->m_oam.priority_rotation ? (m_ppu->m_oam.address >> 1) & 127 : 0;
122113   }
123114}
124115
r29543r29544
139130TIMER_CALLBACK_MEMBER(snes_state::snes_scanline_tick)
140131{
141132   /* Increase current line - we want to latch on this line during it, not after it */
142   m_ppu.m_beam.current_vert = m_screen->vpos();
133   m_ppu->m_beam.current_vert = m_screen->vpos();
143134
144135   // not in hblank
145136   SNES_CPU_REG(HVBJOY) &= ~0x40;
r29543r29544
147138   /* Vertical IRQ timer - only if horizontal isn't also enabled! */
148139   if ((SNES_CPU_REG(NMITIMEN) & 0x20) && !(SNES_CPU_REG(NMITIMEN) & 0x10))
149140   {
150      if (m_ppu.m_beam.current_vert == m_vtime)
141      if (m_ppu->m_beam.current_vert == m_vtime)
151142      {
152143         SNES_CPU_REG(TIMEUP) = 0x80;    /* Indicate that irq occurred */
153144         // IRQ latches the counters, do it now
154         m_ppu.latch_counters(machine());
145         m_ppu->latch_counters(machine());
155146         m_maincpu->set_input_line(G65816_LINE_IRQ, ASSERT_LINE );
156147      }
157148   }
r29543r29544
164155      // is the HIRQ on a specific scanline?
165156      if (SNES_CPU_REG(NMITIMEN) & 0x20)
166157      {
167         if (m_ppu.m_beam.current_vert != m_vtime)
158         if (m_ppu->m_beam.current_vert != m_vtime)
168159         {
169160            setirq = 0;
170161         }
r29543r29544
172163
173164      if (setirq)
174165      {
175//          printf("HIRQ @ %d, %d\n", pixel * m_ppu.m_htmult, m_ppu.m_beam.current_vert);
166//          printf("HIRQ @ %d, %d\n", pixel * m_ppu->m_htmult, m_ppu->m_beam.current_vert);
176167         if (pixel == 0)
177168         {
178169            hirq_tick();
179170         }
180171         else
181172         {
182            m_hirq_timer->adjust(m_screen->time_until_pos(m_ppu.m_beam.current_vert, pixel * m_ppu.m_htmult));
173            m_hirq_timer->adjust(m_screen->time_until_pos(m_ppu->m_beam.current_vert, pixel * m_ppu->m_htmult));
183174         }
184175      }
185176   }
186177
187178   /* Start of VBlank */
188   if (m_ppu.m_beam.current_vert == m_ppu.m_beam.last_visible_line)
179   if (m_ppu->m_beam.current_vert == m_ppu->m_beam.last_visible_line)
189180   {
190      timer_set(m_screen->time_until_pos(m_ppu.m_beam.current_vert, 10), TIMER_RESET_OAM_ADDRESS);
181      timer_set(m_screen->time_until_pos(m_ppu->m_beam.current_vert, 10), TIMER_RESET_OAM_ADDRESS);
191182
192183      SNES_CPU_REG(HVBJOY) |= 0x81;       /* Set vblank bit to on & indicate controllers being read */
193184      SNES_CPU_REG(RDNMI) |= 0x80;        /* Set NMI occurred bit */
r29543r29544
199190      }
200191
201192      /* three lines after start of vblank we update the controllers (value from snes9x) */
202      m_io_timer->adjust(m_screen->time_until_pos(m_ppu.m_beam.current_vert + 2, m_hblank_offset * m_ppu.m_htmult));
193      m_io_timer->adjust(m_screen->time_until_pos(m_ppu->m_beam.current_vert + 2, m_hblank_offset * m_ppu->m_htmult));
203194   }
204195
205196   // hdma reset happens at scanline 0, H=~6
206   if (m_ppu.m_beam.current_vert == 0)
197   if (m_ppu->m_beam.current_vert == 0)
207198   {
208199      address_space &cpu0space = m_maincpu->space(AS_PROGRAM);
209200      hdma_init(cpu0space);
210201   }
211202
212   if (m_ppu.m_beam.current_vert == 0)
203   if (m_ppu->m_beam.current_vert == 0)
213204   {   /* VBlank is over, time for a new frame */
214205      SNES_CPU_REG(HVBJOY) &= 0x7f;       /* Clear vblank bit */
215206      SNES_CPU_REG(RDNMI)  &= 0x7f;       /* Clear nmi occurred bit */
216      m_ppu.m_stat78 ^= 0x80;       /* Toggle field flag */
217      m_ppu.m_stat77 &= 0x3f;  /* Clear Time Over and Range Over bits */
207      m_ppu->m_stat78 ^= 0x80;       /* Toggle field flag */
208      m_ppu->m_stat77 &= 0x3f;  /* Clear Time Over and Range Over bits */
218209
219210      m_maincpu->set_input_line(G65816_LINE_NMI, CLEAR_LINE );
220211   }
221212
222213   m_scanline_timer->adjust(attotime::never);
223   m_hblank_timer->adjust(m_screen->time_until_pos(m_ppu.m_beam.current_vert, m_hblank_offset * m_ppu.m_htmult));
214   m_hblank_timer->adjust(m_screen->time_until_pos(m_ppu->m_beam.current_vert, m_hblank_offset * m_ppu->m_htmult));
224215
225//  printf("%02x %d\n",SNES_CPU_REG(HVBJOY),m_ppu.m_beam.current_vert);
216//  printf("%02x %d\n",SNES_CPU_REG(HVBJOY),m_ppu->m_beam.current_vert);
226217}
227218
228219/* This is called at the start of hblank *before* the scanline indicated in current_vert! */
r29543r29544
231222   address_space &cpu0space = m_maincpu->space(AS_PROGRAM);
232223   int nextscan;
233224
234   m_ppu.m_beam.current_vert = m_screen->vpos();
225   m_ppu->m_beam.current_vert = m_screen->vpos();
235226
236227   /* make sure we halt */
237228   m_hblank_timer->adjust(attotime::never);
238229
239230   /* draw a scanline */
240   if (m_ppu.m_beam.current_vert <= m_ppu.m_beam.last_visible_line)
231   if (m_ppu->m_beam.current_vert <= m_ppu->m_beam.last_visible_line)
241232   {
242233      if (m_screen->vpos() > 0)
243234      {
r29543r29544
245236         if (SNES_CPU_REG(HDMAEN))
246237            hdma(cpu0space);
247238
248         m_screen->update_partial((m_ppu.m_interlace == 2) ? (m_ppu.m_beam.current_vert * m_ppu.m_interlace) : m_ppu.m_beam.current_vert - 1);
239         m_screen->update_partial((m_ppu->m_interlace == 2) ? (m_ppu->m_beam.current_vert * m_ppu->m_interlace) : m_ppu->m_beam.current_vert - 1);
249240      }
250241   }
251242
r29543r29544
253244   SNES_CPU_REG(HVBJOY) |= 0x40;
254245
255246   /* kick off the start of scanline timer */
256   nextscan = m_ppu.m_beam.current_vert + 1;
257   if (nextscan >= (((m_ppu.m_stat78 & 0x10) == SNES_NTSC) ? SNES_VTOTAL_NTSC : SNES_VTOTAL_PAL))
247   nextscan = m_ppu->m_beam.current_vert + 1;
248   if (nextscan >= (((m_ppu->m_stat78 & 0x10) == SNES_NTSC) ? SNES_VTOTAL_NTSC : SNES_VTOTAL_PAL))
258249   {
259250      nextscan = 0;
260251   }
r29543r29544
402393   // PPU accesses are from 2100 to 213f
403394   if (offset >= INIDISP && offset < APU00)
404395   {
405      return m_ppu.read(space, offset, SNES_CPU_REG(WRIO) & 0x80);
396      return m_ppu->read(space, offset, SNES_CPU_REG(WRIO) & 0x80);
406397   }
407398
408399   // APU is mirrored from 2140 to 217f
r29543r29544
490481   // PPU accesses are from 2100 to 213f
491482   if (offset >= INIDISP && offset < APU00)
492483   {
493      m_ppu.write(space, offset, data);
484      m_ppu->write(space, offset, data);
494485      return;
495486   }
496487
r29543r29544
548539         if (!(SNES_CPU_REG(WRIO) & 0x80) && (data & 0x80))
549540         {
550541            // external latch
551            m_ppu.latch_counters(space.machine());
542            m_ppu->latch_counters(space.machine());
552543         }
553544         SNES_CPU_REG(WRIO) = data;
554545         return;
r29543r29544
574565         return;
575566      case HDMAEN:    /* HDMA channel designation */
576567         if (data) //if a HDMA is enabled, data is inited at the next scanline
577            timer_set(m_screen->time_until_pos(m_ppu.m_beam.current_vert + 1), TIMER_RESET_HDMA);
568            timer_set(m_screen->time_until_pos(m_ppu->m_beam.current_vert + 1), TIMER_RESET_HDMA);
578569         SNES_CPU_REG(HDMAEN) = data;
579570         return;
580571      case TIMEUP:    // IRQ Flag is cleared on both read and write
r29543r29544
10421033   // SNES hcounter has a 0-339 range.  hblank starts at counter 260.
10431034   // clayfighter sets an HIRQ at 260, apparently it wants it to be before hdma kicks off, so we'll delay 2 pixels.
10441035   m_hblank_offset = 274;
1045   m_hblank_timer->adjust(m_screen->time_until_pos(((m_ppu.m_stat78 & 0x10) == SNES_NTSC) ? SNES_VTOTAL_NTSC - 1 : SNES_VTOTAL_PAL - 1, m_hblank_offset));
1036   m_hblank_timer->adjust(m_screen->time_until_pos(((m_ppu->m_stat78 & 0x10) == SNES_NTSC) ? SNES_VTOTAL_NTSC - 1 : SNES_VTOTAL_PAL - 1, m_hblank_offset));
10461037}
10471038
10481039void snes_state::snes_init_ram()
r29543r29544
10691060
10701061   // init frame counter so first line is 0
10711062   if (ATTOSECONDS_TO_HZ(m_screen->frame_period().attoseconds) >= 59)
1072      m_ppu.m_beam.current_vert = SNES_VTOTAL_NTSC;
1063      m_ppu->m_beam.current_vert = SNES_VTOTAL_NTSC;
10731064   else
1074      m_ppu.m_beam.current_vert = SNES_VTOTAL_PAL;
1065      m_ppu->m_beam.current_vert = SNES_VTOTAL_PAL;
10751066}
10761067
10771068void snes_state::machine_start()
r29543r29544
11351126
11361127   /* Set STAT78 to NTSC or PAL */
11371128   if (ATTOSECONDS_TO_HZ(m_screen->frame_period().attoseconds) >= 59.0f)
1138      m_ppu.m_stat78 = SNES_NTSC;
1129      m_ppu->m_stat78 = SNES_NTSC;
11391130   else /* if (ATTOSECONDS_TO_HZ(m_screen->frame_period().attoseconds) == 50.0f) */
1140      m_ppu.m_stat78 = SNES_PAL;
1131      m_ppu->m_stat78 = SNES_PAL;
11411132
11421133   // reset does this to these registers
11431134   SNES_CPU_REG(NMITIMEN) = 0;
11441135   m_htime = 0x1ff;
11451136   m_vtime = 0x1ff;
11461137
1147   m_ppu.m_htmult = 1;
1148   m_ppu.m_interlace = 1;
1149   m_ppu.m_obj_interlace = 1;
1138   m_ppu->m_htmult = 1;
1139   m_ppu->m_interlace = 1;
1140   m_ppu->m_obj_interlace = 1;
11501141}
11511142
11521143
branches/new_menus/src/mame/machine/balsente.c
r29543r29544
206206}
207207
208208
209void balsente_noise_gen(device_t *device, int count, short *buffer)
209inline void balsente_state::noise_gen_chip(int chip, int count, short *buffer)
210210{
211   balsente_state *state = device->machine().driver_data<balsente_state>();
212   int chip;
213   UINT32 step, noise_counter;
214
215   /* find the chip we are referring to */
216   for (chip = 0; chip < ARRAY_LENGTH(state->m_cem_device); chip++)
217      if (device == state->m_cem_device[chip])
218         break;
219   assert(chip < ARRAY_LENGTH(state->m_cem_device));
220
221211   /* noise generator runs at 100kHz */
222   step = (100000 << 14) / CEM3394_SAMPLE_RATE;
223   noise_counter = state->m_noise_position[chip];
224
212   UINT32 step = (100000 << 14) / CEM3394_SAMPLE_RATE;
213   UINT32 noise_counter = m_noise_position[chip];
214   
225215   while (count--)
226216   {
227      *buffer++ = state->m_poly17[(noise_counter >> 14) & POLY17_SIZE] << 12;
217      *buffer++ = m_poly17[(noise_counter >> 14) & POLY17_SIZE] << 12;
228218      noise_counter += step;
229219   }
230
220   
231221   /* remember the noise position */
232   state->m_noise_position[chip] = noise_counter;
222   m_noise_position[chip] = noise_counter;
233223}
234224
225CEM3394_EXT_INPUT(balsente_state::noise_gen_0) { noise_gen_chip(0, count, buffer); }
226CEM3394_EXT_INPUT(balsente_state::noise_gen_1) { noise_gen_chip(1, count, buffer); }
227CEM3394_EXT_INPUT(balsente_state::noise_gen_2) { noise_gen_chip(2, count, buffer); }
228CEM3394_EXT_INPUT(balsente_state::noise_gen_3) { noise_gen_chip(3, count, buffer); }
229CEM3394_EXT_INPUT(balsente_state::noise_gen_4) { noise_gen_chip(4, count, buffer); }
230CEM3394_EXT_INPUT(balsente_state::noise_gen_5) { noise_gen_chip(5, count, buffer); }
235231
236232
237233/*************************************
r29543r29544
930926   /* bit D0 enables/disables audio */
931927   if (diff_counter_control & 0x01)
932928   {
933      int ch;
934      for (ch = 0; ch < 6; ch++)
929      for (int ch = 0; ch < 6; ch++)
935930         m_cem_device[ch]->set_output_gain(0, (data & 0x01) ? 1.0 : 0);
936931   }
937932
branches/new_menus/src/mame/includes/namcona1.h
r29543r29544
3030      : driver_device(mconfig, type, tag),
3131      m_maincpu(*this,"maincpu"),
3232      m_mcu(*this,"mcu"),
33      m_eeprom(*this, "eeprom"),
3433      m_gfxdecode(*this, "gfxdecode"),
3534      m_screen(*this, "screen"),
3635      m_palette(*this, "palette"),
r29543r29544
4645
4746   required_device<cpu_device> m_maincpu;
4847   required_device<cpu_device> m_mcu;
49   required_device<eeprom_parallel_28xx_device> m_eeprom;
5048   required_device<gfxdecode_device> m_gfxdecode;
5149   required_device<screen_device> m_screen;
5250   required_device<palette_device> m_palette;
r29543r29544
6260   // this has to be UINT8 to be in the right byte order for the tilemap system
6361   dynamic_array<UINT8> m_shaperam;
6462
65   UINT16 *m_mpBank0;
66   UINT16 *m_mpBank1;
63   UINT16 *m_prgrom;
64   UINT16 *m_maskrom;
6765   int m_mEnableInterrupts;
6866   int m_gametype;
6967   UINT16 m_count;
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7674   tilemap_t *m_bg_tilemap[4+1];
7775   int m_palette_is_dirty;
7876
79
8077   DECLARE_READ16_MEMBER(custom_key_r);
8178   DECLARE_WRITE16_MEMBER(custom_key_w);
8279   DECLARE_WRITE16_MEMBER(namcona1_vreg_w);
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10097   void write_version_info();
10198   int transfer_dword(UINT32 dest, UINT32 source);
10299   void namcona1_blit();
103   void init_namcona1(int gametype);
104100   void UpdatePalette(int offset);
105101   DECLARE_WRITE16_MEMBER(namcona1_videoram_w);
106102   DECLARE_WRITE16_MEMBER(namcona1_paletteram_w);
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134130   virtual void video_start();
135131   UINT32 screen_update_namcona1(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
136132   TIMER_DEVICE_CALLBACK_MEMBER(namcona1_interrupt);
137   TIMER_DEVICE_CALLBACK_MEMBER(mcu_interrupt);
138133
139134private:
140135   void tilemap_get_info(tile_data &tileinfo, int tile_index, const UINT16 *tilemap_videoram, bool use_4bpp_gfx);
branches/new_menus/src/mame/includes/snes.h
r29543r29544
33
44#include "cpu/spc700/spc700.h"
55#include "cpu/g65816/g65816.h"
6#include "cpu/upd7725/upd7725.h"
76#include "audio/snes_snd.h"
7#include "video/snes_ppu.h"
88
99/*
1010    SNES timing theory:
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1919    This is because 2 dots are "long" dots that last 6 MC ticks, resulting in 1 extra dot per line.
2020*/
2121
22#define MCLK_NTSC   (21477272)  /* verified */
23#define MCLK_PAL    (21218370)  /* verified */
24
25#define DOTCLK_NTSC (MCLK_NTSC/4)
26#define DOTCLK_PAL  (MCLK_PAL/4)
27
28#define SNES_LAYER_DEBUG  0
29
30/* Debug definitions */
31#ifdef MAME_DEBUG
32/* #define SNES_DBG_GENERAL*/       /* Display general debug info */
33/* #define SNES_DBG_VIDEO */        /* Display video debug info */
34/* #define SNES_DBG_DMA*/           /* Display DMA debug info */
35/* #define SNES_DBG_HDMA*/          /* Display HDMA debug info */
36/* #define SNES_DBG_REG_R*/         /* Display register read info */
37/* #define SNES_DBG_REG_W*/         /* Display register write info */
38#endif /* MAME_DEBUG */
39
40/* Useful definitions */
41#define SNES_SCR_WIDTH        256       /* 32 characters 8 pixels wide */
42#define SNES_SCR_HEIGHT_NTSC  225       /* Can be 224 or 240 height */
43#define SNES_SCR_HEIGHT_PAL   240       /* ??? */
44#define SNES_VTOTAL_NTSC      262       /* Maximum number of lines for NTSC systems */
45#define SNES_VTOTAL_PAL       312       /* Maximum number of lines for PAL systems */
46#define SNES_HTOTAL           341       /* Maximum number pixels per line (incl. hblank) */
22// Useful definitions
4723#define SNES_DMA_BASE         0x4300    /* Base DMA register address */
4824#define SNES_MODE_20          0x01      /* Lo-ROM cart */
4925#define SNES_MODE_21          0x02      /* Hi-ROM cart */
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5329#define SNES_MODE_BSLO        0x20
5430#define SNES_MODE_BSHI        0x40
5531#define SNES_MODE_ST          0x80
56#define SNES_NTSC             0x00
57#define SNES_PAL              0x10
58#define SNES_VRAM_SIZE        0x20000   /* 128kb of video ram */
59#define SNES_CGRAM_SIZE       0x202     /* 256 16-bit colours + 1 tacked on 16-bit colour for fixed colour */
60#define SNES_OAM_SIZE         0x440     /* 1088 bytes of Object Attribute Memory */
6132#define SNES_EXROM_START      0x1000000
62#define FIXED_COLOUR          256       /* Position in cgram for fixed colour */
63/* Definitions for PPU Memory-Mapped registers */
33
34// some PPU registers we still use in machine/snes.c
6435#define INIDISP        0x2100
65#define OBSEL          0x2101
6636#define OAMADDL        0x2102
6737#define OAMADDH        0x2103
68#define OAMDATA        0x2104
69#define BGMODE         0x2105   /* abcdefff = abcd: bg4-1 tile size | e: BG3 high priority | f: mode */
70#define MOSAIC         0x2106   /* xxxxabcd = x: pixel size | abcd: affects bg 1-4 */
71#define BG1SC          0x2107
72#define BG2SC          0x2108
73#define BG3SC          0x2109
74#define BG4SC          0x210A
75#define BG12NBA        0x210B
76#define BG34NBA        0x210C
77#define BG1HOFS        0x210D
78#define BG1VOFS        0x210E
79#define BG2HOFS        0x210F
80#define BG2VOFS        0x2110
81#define BG3HOFS        0x2111
82#define BG3VOFS        0x2112
83#define BG4HOFS        0x2113
84#define BG4VOFS        0x2114
85#define VMAIN          0x2115   /* i---ffrr = i: Increment timing | f: Full graphic | r: increment rate */
86#define VMADDL         0x2116   /* aaaaaaaa = a: LSB of vram address */
87#define VMADDH         0x2117   /* aaaaaaaa = a: MSB of vram address */
88#define VMDATAL        0x2118   /* dddddddd = d: data to be written */
89#define VMDATAH        0x2119   /* dddddddd = d: data to be written */
90#define M7SEL          0x211A   /* ab----yx = a: screen over | y: vertical flip | x: horizontal flip */
91#define M7A            0x211B   /* aaaaaaaa = a: COSINE rotate angle / X expansion */
92#define M7B            0x211C   /* aaaaaaaa = a: SINE rotate angle / X expansion */
93#define M7C            0x211D   /* aaaaaaaa = a: SINE rotate angle / Y expansion */
94#define M7D            0x211E   /* aaaaaaaa = a: COSINE rotate angle / Y expansion */
95#define M7X            0x211F
96#define M7Y            0x2120
97#define CGADD          0x2121
98#define CGDATA         0x2122
99#define W12SEL         0x2123
100#define W34SEL         0x2124
101#define WOBJSEL        0x2125
102#define WH0            0x2126   /* pppppppp = p: Left position of window 1 */
103#define WH1            0x2127   /* pppppppp = p: Right position of window 1 */
104#define WH2            0x2128   /* pppppppp = p: Left position of window 2 */
105#define WH3            0x2129   /* pppppppp = p: Right position of window 2 */
106#define WBGLOG         0x212A   /* aabbccdd = a: BG4 params | b: BG3 params | c: BG2 params | d: BG1 params */
107#define WOBJLOG        0x212B   /* ----ccoo = c: Colour window params | o: Object window params */
108#define TM             0x212C
109#define TS             0x212D
110#define TMW            0x212E
111#define TSW            0x212F
112#define CGWSEL         0x2130
113#define CGADSUB        0x2131
114#define COLDATA        0x2132
11538#define SETINI         0x2133
11639#define MPYL           0x2134
11740#define MPYM           0x2135
11841#define MPYH           0x2136
119#define SLHV           0x2137
120#define ROAMDATA       0x2138
121#define RVMDATAL       0x2139
122#define RVMDATAH       0x213A
123#define RCGDATA        0x213B
124#define OPHCT          0x213C
125#define OPVCT          0x213D
126#define STAT77         0x213E
127#define STAT78         0x213F
42
12843#define APU00          0x2140
12944#define APU01          0x2141
13045#define APU02          0x2142
13146#define APU03          0x2143
47
13248#define WMDATA         0x2180
13349#define WMADDL         0x2181
13450#define WMADDM         0x2182
13551#define WMADDH         0x2183
136/* Definitions for CPU Memory-Mapped registers */
52
53// Definitions for CPU Memory-Mapped registers
13754#define OLDJOY1        0x4016
13855#define OLDJOY2        0x4017
13956#define NMITIMEN       0x4200
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363280
364281#define SNES_CPU_REG(a) m_cpu_regs[a - 0x4200]  // regs 0x4200-0x421f
365282
366/* (PPU) Video related */
367
368struct SNES_SCANLINE
369{
370   int enable, clip;
371
372   UINT16 buffer[SNES_SCR_WIDTH];
373   UINT8  priority[SNES_SCR_WIDTH];
374   UINT8  layer[SNES_SCR_WIDTH];
375   UINT8  blend_exception[SNES_SCR_WIDTH];
376};
377
378class snes_state;
379
380class snes_ppu_class  /* once all the regs are saved in this structure, it would be better to reorganize it a bit... */
381{
382public:
383   UINT8 m_regs[0x40];
384
385   SNES_SCANLINE m_scanlines[2];
386
387   struct
388   {
389      /* clipmasks */
390      UINT8 window1_enabled, window1_invert;
391      UINT8 window2_enabled, window2_invert;
392      UINT8 wlog_mask;
393      /* color math enabled */
394      UINT8 color_math;
395
396      UINT8 charmap;
397      UINT8 tilemap;
398      UINT8 tilemap_size;
399
400      UINT8 tile_size;
401      UINT8 mosaic_enabled;   // actually used only for layers 0->3!
402
403      UINT8 main_window_enabled;
404      UINT8 sub_window_enabled;
405      UINT8 main_bg_enabled;
406      UINT8 sub_bg_enabled;
407
408      UINT16 hoffs;
409      UINT16 voffs;
410   } m_layer[6]; // this is for the BG1 - BG2 - BG3 - BG4 - OBJ - color layers
411
412   struct
413   {
414      UINT8 address_low;
415      UINT8 address_high;
416      UINT8 saved_address_low;
417      UINT8 saved_address_high;
418      UINT16 address;
419      UINT16 priority_rotation;
420      UINT8 next_charmap;
421      UINT8 next_size;
422      UINT8 size;
423      UINT32 next_name_select;
424      UINT32 name_select;
425      UINT8 first_sprite;
426      UINT8 flip;
427      UINT16 write_latch;
428   } m_oam;
429
430   struct
431   {
432      UINT16 latch_horz;
433      UINT16 latch_vert;
434      UINT16 current_horz;
435      UINT16 current_vert;
436      UINT8 last_visible_line;
437      UINT8 interlace_count;
438   } m_beam;
439
440   struct
441   {
442      UINT8 repeat;
443      UINT8 hflip;
444      UINT8 vflip;
445      INT16 matrix_a;
446      INT16 matrix_b;
447      INT16 matrix_c;
448      INT16 matrix_d;
449      INT16 origin_x;
450      INT16 origin_y;
451      UINT16 hor_offset;
452      UINT16 ver_offset;
453      UINT8 extbg;
454   } m_mode7;
455
456   struct OAM
457   {
458      UINT16 tile;
459      INT16 x, y;
460      UINT8 size, vflip, hflip, priority_bits, pal;
461      int height, width;
462   };
463
464   struct OAM m_oam_spritelist[SNES_SCR_WIDTH / 2];
465
466   UINT8 m_oam_itemlist[32];
467
468   struct TILELIST {
469      INT16 x;
470      UINT16 priority, pal, tileaddr;
471      int hflip;
472   };
473
474   struct TILELIST m_oam_tilelist[34];
475
476   #if SNES_LAYER_DEBUG
477   struct DEBUGOPTS
478   {
479      UINT8 bg_disabled[5];
480      UINT8 mode_disabled[8];
481      UINT8 draw_subscreen;
482      UINT8 windows_disabled;
483      UINT8 mosaic_disabled;
484      UINT8 colormath_disabled;
485      UINT8 sprite_reversed;
486      UINT8 select_pri[5];
487   };
488   struct DEBUGOPTS m_debug_options;
489   #endif
490
491   screen_device *m_screen;
492
493   UINT8 m_mosaic_size;
494   UINT8 m_clip_to_black;
495   UINT8 m_prevent_color_math;
496   UINT8 m_sub_add_mode;
497   UINT8 m_bg3_priority_bit;
498   UINT8 m_direct_color;
499   UINT8 m_ppu_last_scroll;      /* as per Anomie's doc and Theme Park, all scroll regs shares (but mode 7 ones) the same
500                                 'previous' scroll value */
501   UINT8 m_mode7_last_scroll;    /* as per Anomie's doc mode 7 scroll regs use a different value, shared with mode 7 matrix! */
502
503   UINT8 m_ppu1_open_bus, m_ppu2_open_bus;
504   UINT8 m_ppu1_version, m_ppu2_version;
505   UINT8 m_window1_left, m_window1_right, m_window2_left, m_window2_right;
506
507   UINT16 m_mosaic_table[16][4096];
508   UINT8 m_clipmasks[6][SNES_SCR_WIDTH];
509   UINT8 m_update_windows;
510   UINT8 m_update_offsets;
511   UINT8 m_update_oam_list;
512   UINT8 m_mode;
513   UINT8 m_interlace; //doubles the visible resolution
514   UINT8 m_obj_interlace;
515   UINT8 m_screen_brightness;
516   UINT8 m_screen_disabled;
517   UINT8 m_pseudo_hires;
518   UINT8 m_color_modes;
519   UINT8 m_stat77;
520   UINT8 m_stat78;
521
522   UINT16                m_htmult;     /* in 512 wide, we run HTOTAL double and halve it on latching */
523   UINT16                m_cgram_address;  /* CGRAM address */
524   UINT8                 m_read_ophct;
525   UINT8                 m_read_opvct;
526   UINT16                m_vram_fgr_high;
527   UINT16                m_vram_fgr_increment;
528   UINT16                m_vram_fgr_count;
529   UINT16                m_vram_fgr_mask;
530   UINT16                m_vram_fgr_shift;
531   UINT16                m_vram_read_buffer;
532   UINT16                m_vmadd;
533
534   inline UINT16 get_bgcolor(UINT8 direct_colors, UINT16 palette, UINT8 color);
535   inline void set_scanline_pixel(int screen, INT16 x, UINT16 color, UINT8 priority, UINT8 layer, int blend);
536   inline void draw_bgtile_lores(UINT8 layer, INT16 ii, UINT8 colour, UINT16 pal, UINT8 direct_colors, UINT8 priority);
537   inline void draw_bgtile_hires(UINT8 layer, INT16 ii, UINT8 colour, UINT16 pal, UINT8 direct_colors, UINT8 priority);
538   inline void draw_oamtile(INT16 ii, UINT8 colour, UINT16 pal, UINT8 priority);
539   inline void draw_tile(UINT8 planes, UINT8 layer, UINT32 tileaddr, INT16 x, UINT8 priority, UINT8 flip, UINT8 direct_colors, UINT16 pal, UINT8 hires);
540   inline UINT32 get_tmap_addr(UINT8 layer, UINT8 tile_size, UINT32 base, UINT32 x, UINT32 y);
541   inline void update_line(UINT16 curline, UINT8 layer, UINT8 priority_b, UINT8 priority_a, UINT8 color_depth, UINT8 hires, UINT8 offset_per_tile, UINT8 direct_colors);
542   void update_line_mode7(UINT16 curline, UINT8 layer, UINT8 priority_b, UINT8 priority_a);
543   void update_obsel(void);
544   void oam_list_build(void);
545   int is_sprite_on_scanline(UINT16 curline, UINT8 sprite);
546   void update_objects_rto(UINT16 curline);
547   void update_objects(UINT8 priority_oam0, UINT8 priority_oam1, UINT8 priority_oam2, UINT8 priority_oam3);
548   void update_mode_0(UINT16 curline);
549   void update_mode_1(UINT16 curline);
550   void update_mode_2(UINT16 curline);
551   void update_mode_3(UINT16 curline);
552   void update_mode_4(UINT16 curline);
553   void update_mode_5(UINT16 curline);
554   void update_mode_6(UINT16 curline);
555   void update_mode_7(UINT16 curline);
556   void draw_screens(UINT16 curline);
557   void update_windowmasks(void);
558   void update_offsets(void);
559   inline void draw_blend(UINT16 offset, UINT16 *colour, UINT8 prevent_color_math, UINT8 black_pen_clip, int switch_screens);
560   void refresh_scanline(running_machine &machine, bitmap_rgb32 &bitmap, UINT16 curline);
561
562   void latch_counters(running_machine &machine);
563   void dynamic_res_change(running_machine &machine);
564   inline UINT32 get_vram_address(running_machine &machine);
565   UINT8 dbg_video(running_machine &machine, UINT16 curline);
566
567   void ppu_start(screen_device &screen,snes_state *state);
568   UINT8 read(address_space &space, UINT32 offset, UINT8 wrio_bit7);
569   void write(address_space &space, UINT32 offset, UINT8 data);
570
571   DECLARE_READ8_MEMBER( oam_read );
572   DECLARE_WRITE8_MEMBER( oam_write );
573   DECLARE_READ8_MEMBER( cgram_read );
574   DECLARE_WRITE8_MEMBER( cgram_write );
575   DECLARE_READ8_MEMBER( vram_read );
576   DECLARE_WRITE8_MEMBER( vram_write );
577   UINT16 *m_oam_ram;     /* Object Attribute Memory */
578   UINT16 *m_cgram;   /* Palette RAM */
579   UINT8  *m_vram;    /* Video RAM (TODO: Should be 16-bit, but it's easier this way) */
580
581   snes_state *m_state;
582};
583
584283struct snes_cart_info
585284{
586285   UINT8 *m_rom;
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613312      m_maincpu(*this, "maincpu"),
614313      m_soundcpu(*this, "soundcpu"),
615314      m_spc700(*this, "spc700"),
616      m_superfx(*this, "superfx"),
315      m_ppu(*this, "ppu"),
617316      m_screen(*this, "screen") { }
618317
619318   /* misc */
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670369   snes_cart_info m_cart;   // used by NSS/SFCBox only! to be moved in a derived class!
671370   void rom_map_setup(UINT32 size);
672371
673   snes_ppu_class        m_ppu;
674372   UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
675373
676374   /* devices */
677375   required_device<_5a22_device> m_maincpu;
678376   required_device<spc700_device> m_soundcpu;
679377   required_device<snes_sound_device> m_spc700;
680   optional_device<cpu_device> m_superfx;
378   required_device<snes_ppu_device> m_ppu;
681379   required_device<screen_device> m_screen;
682380
683381
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728426   DECLARE_WRITE_LINE_MEMBER(snes_extern_irq_w);
729427   DECLARE_DEVICE_IMAGE_LOAD_MEMBER(snes_cart);
730428   DECLARE_DEVICE_IMAGE_LOAD_MEMBER(sufami_cart);
731   virtual void video_start();
732429   void snes_init_timers();
733430   virtual void machine_start();
734431   virtual void machine_reset();
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760457   HAS_UNK
761458};
762459
763/* offset-per-tile modes */
764enum
765{
766   SNES_OPT_NONE = 0,
767   SNES_OPT_MODE2,
768   SNES_OPT_MODE4,
769   SNES_OPT_MODE6
770};
771
772/* layers */
773enum
774{
775   SNES_BG1 = 0,
776   SNES_BG2,
777   SNES_BG3,
778   SNES_BG4,
779   SNES_OAM,
780   SNES_COLOR
781};
782
783460#endif /* _SNES_H_ */
branches/new_menus/src/mame/includes/bladestl.h
r29543r29544
1313public:
1414   bladestl_state(const machine_config &mconfig, device_type type, const char *tag)
1515      : driver_device(mconfig, type, tag),
16      m_paletteram(*this, "paletteram"),
16
17      m_maincpu(*this, "maincpu"),
1718      m_audiocpu(*this, "audiocpu"),
1819      m_k007342(*this, "k007342"),
1920      m_k007420(*this, "k007420"),
20      m_maincpu(*this, "maincpu"),
2121      m_upd7759(*this, "upd"),
2222      m_gfxdecode(*this, "gfxdecode"),
23      m_palette(*this, "palette") { }
23      m_palette(*this, "palette"),
24      m_rombank(*this, "rombank"),
25      m_paletteram(*this, "paletteram") { }
2426
27   required_device<cpu_device> m_maincpu;
28   required_device<cpu_device> m_audiocpu;
29   required_device<k007342_device> m_k007342;
30   required_device<k007420_device> m_k007420;
31   required_device<upd7759_device> m_upd7759;
32   required_device<gfxdecode_device> m_gfxdecode;
33   required_device<palette_device> m_palette;
34
2535   /* memory pointers */
36   required_memory_bank m_rombank;
2637   required_shared_ptr<UINT8> m_paletteram;
2738
2839   /* video-related */
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3344   int        m_last_track[4];
3445
3546   /* devices */
36   required_device<cpu_device> m_audiocpu;
37   required_device<k007342_device> m_k007342;
38   required_device<k007420_device> m_k007420;
3947   DECLARE_READ8_MEMBER(trackball_r);
4048   DECLARE_WRITE8_MEMBER(bladestl_bankswitch_w);
4149   DECLARE_WRITE8_MEMBER(bladestl_sh_irqtrigger_w);
r29543r29544
4755   DECLARE_PALETTE_INIT(bladestl);
4856   UINT32 screen_update_bladestl(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
4957   TIMER_DEVICE_CALLBACK_MEMBER(bladestl_scanline);
50   required_device<cpu_device> m_maincpu;
51   required_device<upd7759_device> m_upd7759;
52   required_device<gfxdecode_device> m_gfxdecode;
53   required_device<palette_device> m_palette;
5458   void set_pens();
5559   K007342_CALLBACK_MEMBER(bladestl_tile_callback);
5660   K007420_CALLBACK_MEMBER(bladestl_sprite_callback);
branches/new_menus/src/mame/includes/rockrage.h
r29543r29544
1313public:
1414   rockrage_state(const machine_config &mconfig, device_type type, const char *tag)
1515      : driver_device(mconfig, type, tag),
16      m_paletteram(*this, "paletteram"),
1716      m_maincpu(*this, "maincpu"),
1817      m_audiocpu(*this, "audiocpu"),
1918      m_k007342(*this, "k007342"),
2019      m_k007420(*this, "k007420"),
2120      m_vlm(*this, "vlm"),
2221      m_gfxdecode(*this, "gfxdecode"),
23      m_palette(*this, "palette") { }
22      m_palette(*this, "palette"),
23      m_rombank(*this, "rombank"),
24      m_paletteram(*this, "paletteram") { }
2425
25   /* memory pointers */
26   required_shared_ptr<UINT8> m_paletteram;
27
28   /* video-related */
29   int        m_layer_colorbase[2];
30   int        m_vreg;
31
3226   /* devices */
3327   required_device<cpu_device> m_maincpu;
3428   required_device<cpu_device> m_audiocpu;
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3832   required_device<gfxdecode_device> m_gfxdecode;
3933   required_device<palette_device> m_palette;
4034
35   /* memory pointers */
36   required_memory_bank m_rombank;
37   required_shared_ptr<UINT8> m_paletteram;
38
39   /* video-related */
40   int        m_layer_colorbase[2];
41   int        m_vreg;
42
4143   DECLARE_WRITE8_MEMBER(rockrage_bankswitch_w);
4244   DECLARE_WRITE8_MEMBER(rockrage_sh_irqtrigger_w);
4345   DECLARE_WRITE8_MEMBER(rockrage_vreg_w);
branches/new_menus/src/mame/includes/battlnts.h
r29543r29544
1212public:
1313   battlnts_state(const machine_config &mconfig, device_type type, const char *tag)
1414      : driver_device(mconfig, type, tag),
15      m_maincpu(*this, "maincpu"),
1516      m_audiocpu(*this, "audiocpu"),
1617      m_k007342(*this, "k007342"),
1718      m_k007420(*this, "k007420"),
18      m_maincpu(*this, "maincpu"),
19      m_gfxdecode(*this, "gfxdecode") { }
19      m_gfxdecode(*this, "gfxdecode"),
20      m_rombank(*this, "rombank") { }
2021
21   /* memory pointers */
22//  UINT8 *      paletteram;    // this currently uses generic palette handling
23
2422   /* video-related */
2523   int m_spritebank;
2624   int m_layer_colorbase[2];
2725
28
2926   /* devices */
27   required_device<cpu_device> m_maincpu;
3028   required_device<cpu_device> m_audiocpu;
3129   required_device<k007342_device> m_k007342;
3230   required_device<k007420_device> m_k007420;
31   required_device<gfxdecode_device> m_gfxdecode;
32   required_memory_bank m_rombank;
33
3334   DECLARE_WRITE8_MEMBER(battlnts_sh_irqtrigger_w);
3435   DECLARE_WRITE8_MEMBER(battlnts_bankswitch_w);
3536   DECLARE_WRITE8_MEMBER(battlnts_spritebank_w);
r29543r29544
3839   virtual void machine_reset();
3940   UINT32 screen_update_battlnts(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
4041   INTERRUPT_GEN_MEMBER(battlnts_interrupt);
41   required_device<cpu_device> m_maincpu;
42   required_device<gfxdecode_device> m_gfxdecode;
4342   K007342_CALLBACK_MEMBER(battlnts_tile_callback);
4443   K007420_CALLBACK_MEMBER(battlnts_sprite_callback);
4544};
branches/new_menus/src/mame/includes/balsente.h
r29543r29544
215215   void update_grudge_steering();
216216   void expand_roms(UINT8 cd_rom_mask);
217217   inline void config_shooter_adc(UINT8 shooter, UINT8 adc_shift);
218   inline void noise_gen_chip(int chip, int count, short *buffer);
219   CEM3394_EXT_INPUT(noise_gen_0);
220   CEM3394_EXT_INPUT(noise_gen_1);
221   CEM3394_EXT_INPUT(noise_gen_2);
222   CEM3394_EXT_INPUT(noise_gen_3);
223   CEM3394_EXT_INPUT(noise_gen_4);
224   CEM3394_EXT_INPUT(noise_gen_5);
218225   required_device<cpu_device> m_maincpu;
219226   required_device<cpu_device> m_audiocpu;
220227   optional_device<cpu_device> m_68k;
branches/new_menus/src/mame/mame.mak
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309309VIDEOS += RAMDAC
310310VIDEOS += SAA5050
311311#VIDEOS += SED1330
312VIDEOS += SNES_PPU
312313VIDEOS += STVVDP
313314VIDEOS += TLC34076
314315VIDEOS += TMS34061
r29543r29544
14261427   $(DRIVERS)/mario.o $(AUDIO)/mario.o $(VIDEO)/mario.o \
14271428   $(DRIVERS)/multigam.o \
14281429   $(DRIVERS)/n8080.o $(AUDIO)/n8080.o $(VIDEO)/n8080.o \
1429   $(DRIVERS)/nss.o $(MACHINE)/snes.o $(AUDIO)/snes_snd.o $(VIDEO)/snes.o \
1430   $(DRIVERS)/nss.o $(MACHINE)/snes.o $(AUDIO)/snes_snd.o \
14301431   $(DRIVERS)/playch10.o $(MACHINE)/playch10.o $(VIDEO)/playch10.o \
14311432   $(DRIVERS)/popeye.o $(VIDEO)/popeye.o \
14321433   $(DRIVERS)/punchout.o $(VIDEO)/punchout.o \
branches/new_menus/src/mame/video/snes.c
r29543r29544
1/***************************************************************************
2
3  snes.c
4
5  Video file to handle emulation of the Nintendo Super NES.
6
7  Anthony Kruize
8  Based on the original code by Lee Hammerton (aka Savoury Snax)
9
10  Some notes on the snes video hardware:
11
12  Object Attribute Memory(OAM) is made up of 128 blocks of 32 bits, followed
13  by 128 blocks of 2 bits. The format for each block is:
14  -First Block----------------------------------------------------------------
15  | x pos  | y pos  |char no.| v flip | h flip |priority|palette |char no msb|
16  +--------+--------+--------+--------+--------+--------+--------+-----------+
17  | 8 bits | 8 bits | 8 bits | 1 bit  | 1 bit  | 2 bits | 3 bits | 1 bit     |
18  -Second Block---------------------------------------------------------------
19  | size  | x pos msb |
20  +-------+-----------+
21  | 1 bit | 1 bit     |
22  ---------------------
23
24  Video RAM contains information for character data and screen maps.
25  Screen maps are made up of 32 x 32 blocks of 16 bits each.
26  The format for each block is:
27  ----------------------------------------------
28  | v flip | x flip |priority|palette |char no.|
29  +--------+--------+--------+--------+--------+
30  | 1 bit  | 1 bit  | 1 bit  | 3 bits |10 bits |
31  ----------------------------------------------
32  Mode 7 is stored differently. Character data and screen map are interleaved.
33  There are two formats:
34  -Normal-----------------  -EXTBG-----------------------------
35  | char data | char no. |  | priority | char data | char no. |
36  +-----------+----------+  +----------+-----------+----------+
37  | 8 bits    | 8 bits   |  | 1 bit    | 7 bits    | 8 bits   |
38  ------------------------  -----------------------------------
39
40  The screen layers are drawn with the following priorities (updated info courtesy of byuu):
41
42  |           |   1   |   2   |   3   |   4   |   5   |   6   |   7   |   8   |   9   |  10   |  11   |  12   |
43  -------------------------------------------------------------------------------------------------------------
44  | Mode 0    |  BG4B |  BG3B |  OAM0 |  BG4A |  BG3A |  OAM1 |  BG2B |  BG1B |  OAM2 |  BG2A |  BG1A |  OAM3 |
45  -------------------------------------------------------------------------------------------------------------
46  | Mode 1 (*)|  BG3B |  OAM0 |  OAM1 |  BG2B |  BG1B |  OAM2 |  BG2A |  BG1A |  OAM3 |  BG3A |       |       |
47  -------------------------------------------------------------------------------------------------------------
48  | Mode 1 (!)|  BG3B |  OAM0 |  BG3A |  OAM1 |  BG2B |  BG1B |  OAM2 |  BG2A |  BG1A |  OAM3 |       |       |
49  -------------------------------------------------------------------------------------------------------------
50  | Mode 2    |  BG2B |  OAM0 |  BG1B |  OAM1 |  BG2A |  OAM2 |  BG1A |  OAM3 |       |       |       |       |
51  -------------------------------------------------------------------------------------------------------------
52  | Mode 3    |  BG2B |  OAM0 |  BG1B |  OAM1 |  BG2A |  OAM2 |  BG1A |  OAM3 |       |       |       |       |
53  -------------------------------------------------------------------------------------------------------------
54  | Mode 4    |  BG2B |  OAM0 |  BG1B |  OAM1 |  BG2A |  OAM2 |  BG1A |  OAM3 |       |       |       |       |
55  -------------------------------------------------------------------------------------------------------------
56  | Mode 5    |  BG2B |  OAM0 |  BG1B |  OAM1 |  BG2A |  OAM2 |  BG1A |  OAM3 |       |       |       |       |
57  -------------------------------------------------------------------------------------------------------------
58  | Mode 6    |  OAM0 |  BG1B |  OAM1 |  OAM2 |  BG1A |  OAM3 |       |       |       |       |       |       |
59  -------------------------------------------------------------------------------------------------------------
60  | Mode 7 (+)|  OAM0 |  BG1n |  OAM1 |  OAM2 |  OAM3 |       |       |       |       |       |       |       |
61  -------------------------------------------------------------------------------------------------------------
62  | Mode 7 (-)|  BG2B |  OAM0 |  BG1n |  OAM1 |  BG2A |  OAM2 |  OAM3 |       |       |       |       |       |
63  -------------------------------------------------------------------------------------------------------------
64
65  Where:
66   - Mode 1 (*) is Mode 1 with bg3_pty = 1
67   - Mode 1 (!) is Mode 1 with bg3_pty = 0
68   - Mode 7 (+) is base Mode 7
69   - Mode 7 (-) is Mode 7 EXTBG
70
71***************************************************************************/
72
73#include "emu.h"
74#include "includes/snes.h"
75
76#define SNES_MAINSCREEN    0
77#define SNES_SUBSCREEN     1
78#define SNES_CLIP_NEVER    0
79#define SNES_CLIP_IN       1
80#define SNES_CLIP_OUT      2
81#define SNES_CLIP_ALWAYS   3
82
83#if SNES_LAYER_DEBUG
84/*                                    red   green  blue    purple  yellow cyan    grey    white */
85static const UINT16 dbg_mode_colours[8] = { 0x1f, 0x3e0, 0x7c00, 0x7c1f, 0x3ff, 0x7fe0, 0x4210, 0x7fff };
86#endif /* SNES_LAYER_DEBUG */
87
88static const UINT16 table_obj_offset[8][8] =
89{
90   { (0*32),   (0*32)+32,   (0*32)+64,   (0*32)+96,   (0*32)+128,   (0*32)+160,   (0*32)+192,   (0*32)+224 },
91   { (16*32),  (16*32)+32,  (16*32)+64,  (16*32)+96,  (16*32)+128,  (16*32)+160,  (16*32)+192,  (16*32)+224 },
92   { (32*32),  (32*32)+32,  (32*32)+64,  (32*32)+96,  (32*32)+128,  (32*32)+160,  (32*32)+192,  (32*32)+224 },
93   { (48*32),  (48*32)+32,  (48*32)+64,  (48*32)+96,  (48*32)+128,  (48*32)+160,  (48*32)+192,  (48*32)+224 },
94   { (64*32),  (64*32)+32,  (64*32)+64,  (64*32)+96,  (64*32)+128,  (64*32)+160,  (64*32)+192,  (64*32)+224 },
95   { (80*32),  (80*32)+32,  (80*32)+64,  (80*32)+96,  (80*32)+128,  (80*32)+160,  (80*32)+192,  (80*32)+224 },
96   { (96*32),  (96*32)+32,  (96*32)+64,  (96*32)+96,  (96*32)+128,  (96*32)+160,  (96*32)+192,  (96*32)+224 },
97   { (112*32), (112*32)+32, (112*32)+64, (112*32)+96, (112*32)+128, (112*32)+160, (112*32)+192, (112*32)+224 }
98};
99
100
101enum
102{
103   SNES_COLOR_DEPTH_2BPP = 0,
104   SNES_COLOR_DEPTH_4BPP,
105   SNES_COLOR_DEPTH_8BPP
106};
107
108
109#define PPU_REG(a) m_regs[a - 0x2100]
110
111
112/*****************************************
113 * get_bgcolor()
114 *
115 * Get the proper color (direct or from cgram)
116 *****************************************/
117
118inline UINT16 snes_ppu_class::get_bgcolor( UINT8 direct_colors, UINT16 palette, UINT8 color )
119{
120   UINT16 c = 0;
121
122   if (direct_colors)
123   {
124      /* format is  0 | BBb00 | GGGg0 | RRRr0, HW confirms that the data is zero padded. */
125      c = ((color & 0x07) << 2) | ((color & 0x38) << 4) | ((color & 0xc0) << 7);
126      c |= ((palette & 0x04) >> 1) | ((palette & 0x08) << 3) | ((palette & 0x10) << 8);
127   }
128   else
129      c = m_cgram[(palette + color) % FIXED_COLOUR];
130
131   return c;
132}
133
134/*****************************************
135 * set_scanline_pixel()
136 *
137 * Store pixel color, priority, layer and
138 * color math exception (for OAM) in the
139 * proper scanline
140 *****************************************/
141
142inline void snes_ppu_class::set_scanline_pixel( int screen, INT16 x, UINT16 color, UINT8 priority, UINT8 layer, int blend )
143{
144   m_scanlines[screen].buffer[x] = color;
145   m_scanlines[screen].priority[x] = priority;
146   m_scanlines[screen].layer[x] = layer;
147   m_scanlines[screen].blend_exception[x] = blend;
148}
149
150/*************************************************************************************************
151 * SNES tiles
152 *
153 * The way vram is accessed to draw tiles is basically the same for both BG and OAM tiles. Main
154 * differences are bit planes (variable for BG and fixed for OAM) and a few details of the scanline
155 * output (since OAM has neither mosaic, nor hires, nor direct colors).
156 * Hence, we use a common function to take data from VRAM and then we call specific routines for
157 * OAM vs BG vs Hi-Res BG tiles.
158 *************************************************************************************************/
159
160/*****************************************
161 * draw_bgtile_lores()
162 * draw_bgtile_hires()
163 * draw_oamtile_()
164 *
165 * Check if a pixel is clipped or not, and
166 * copy it to the scanline buffer when
167 * appropriate. The actual way to perform
168 * such operations depends on the source
169 * (BG or OAM) and on the resolution (hires
170 * or lores)
171 *****************************************/
172
173inline void snes_ppu_class::draw_bgtile_lores( UINT8 layer, INT16 ii, UINT8 colour, UINT16 pal, UINT8 direct_colors, UINT8 priority )
174{
175   int screen;
176   UINT16 c;
177
178   for (screen = SNES_MAINSCREEN; screen <= SNES_SUBSCREEN; screen++)
179   {
180      if (ii >= 0 && ii < SNES_SCR_WIDTH && m_scanlines[screen].enable)
181      {
182         if (m_scanlines[screen].priority[ii] <= priority)
183         {
184            UINT8 clr = colour;
185            UINT8 clipmask = m_clipmasks[layer][ii];
186
187#if SNES_LAYER_DEBUG
188            if (m_debug_options.windows_disabled)
189               clipmask = 0xff;
190#endif /* SNES_LAYER_DEBUG */
191
192            /* Clip to windows */
193            if (m_scanlines[screen].clip)
194               clr &= clipmask;
195
196            /* Only draw if we have a colour (0 == transparent) */
197            if (clr)
198            {
199               c = get_bgcolor(direct_colors, pal, clr);
200               set_scanline_pixel(screen, ii, c, priority, layer, 0);
201            }
202         }
203      }
204   }
205}
206
207inline void snes_ppu_class::draw_bgtile_hires( UINT8 layer, INT16 ii, UINT8 colour, UINT16 pal, UINT8 direct_colors, UINT8 priority )
208{
209   int screen;
210   UINT16 c;
211
212   for (screen = SNES_MAINSCREEN; screen <= SNES_SUBSCREEN; screen++)
213   {
214      // odd pixels to main screen, even pixels to sub screen
215      if (ii >= 0 && ii < (SNES_SCR_WIDTH << 1) && ((ii & 1) ^ screen) && m_scanlines[screen].enable)
216      {
217         if (m_scanlines[screen].priority[ii >> 1] <= priority)
218         {
219            UINT8 clr = colour;
220            UINT8 clipmask = m_clipmasks[layer][ii >> 1];
221
222#if SNES_LAYER_DEBUG
223            if (m_debug_options.windows_disabled)
224               clipmask = 0xff;
225#endif /* SNES_LAYER_DEBUG */
226
227            /* Clip to windows */
228            if (m_scanlines[screen].clip)
229               clr &= clipmask;
230
231            /* Only draw if we have a colour (0 == transparent) */
232            if (clr)
233            {
234               c = get_bgcolor(direct_colors, pal, clr);
235               set_scanline_pixel(screen, ii >> 1, c, priority, layer, 0);
236            }
237         }
238      }
239   }
240}
241
242inline void snes_ppu_class::draw_oamtile( INT16 ii, UINT8 colour, UINT16 pal, UINT8 priority )
243{
244   int screen;
245   int blend;
246   UINT16 c;
247   INT16 pos = ii & 0x1ff;
248
249   for (screen = SNES_MAINSCREEN; screen <= SNES_SUBSCREEN; screen++)
250   {
251      if (pos >= 0 && pos < SNES_SCR_WIDTH && m_scanlines[screen].enable)
252      {
253         UINT8 clr = colour;
254         UINT8 clipmask = m_clipmasks[SNES_OAM][pos];
255
256#if SNES_LAYER_DEBUG
257         if (m_debug_options.windows_disabled)
258            clipmask = 0xff;
259#endif /* SNES_LAYER_DEBUG */
260
261         /* Clip to windows */
262         if (m_scanlines[screen].clip)
263            clr &= clipmask;
264
265         /* Only draw if we have a colour (0 == transparent) */
266         if (clr)
267         {
268            c = m_cgram[(pal + clr) % FIXED_COLOUR];
269            blend = (pal + clr < 192) ? 1 : 0;
270            set_scanline_pixel(screen, pos, c, priority, SNES_OAM, blend);
271         }
272      }
273   }
274}
275
276/*****************************************
277 * draw_tile()
278 *
279 * Draw 8 pixels from the expected tile
280 * by reading the color planes from vram
281 * and by calling the appropriate routine
282 * (depending on layer and resolution)
283 *****************************************/
284
285inline void snes_ppu_class::draw_tile( UINT8 planes, UINT8 layer, UINT32 tileaddr, INT16 x, UINT8 priority, UINT8 flip, UINT8 direct_colors, UINT16 pal, UINT8 hires )
286{
287   UINT8 plane[8];
288   INT16 ii, jj;
289   int x_mos;
290
291   for (ii = 0; ii < planes / 2; ii++)
292   {
293      plane[2 * ii + 0] = m_vram[(tileaddr + 16 * ii + 0) % SNES_VRAM_SIZE];
294      plane[2 * ii + 1] = m_vram[(tileaddr + 16 * ii + 1) % SNES_VRAM_SIZE];
295   }
296
297   for (ii = x; ii < (x + 8); ii++)
298   {
299      UINT8 colour = 0;
300      UINT8 mosaic = m_layer[layer].mosaic_enabled;
301
302#if SNES_LAYER_DEBUG
303      if (m_debug_options.mosaic_disabled)
304         mosaic = 0;
305#endif /* SNES_LAYER_DEBUG */
306
307      if (flip)
308      {
309         for (jj = 0; jj < planes; jj++)
310            colour |= BIT(plane[jj], ii - x) ? (1 << jj) : 0;
311      }
312      else
313      {
314         for (jj = 0; jj < planes; jj++)
315            colour |= BIT(plane[jj], 7 - (ii - x)) ? (1 << jj) : 0;
316      }
317
318      if (layer == SNES_OAM)
319         draw_oamtile(ii, colour, pal, priority);
320      else if (!hires)
321      {
322         if (mosaic)
323         {
324            for (x_mos = 0; x_mos < (m_mosaic_size + 1); x_mos++)
325               draw_bgtile_lores(layer, ii + x_mos, colour, pal, direct_colors, priority);
326            ii += x_mos - 1;
327         }
328         else
329            draw_bgtile_lores(layer, ii, colour, pal, direct_colors, priority);
330      }
331      else /* hires */
332      {
333         if (mosaic)
334         {
335            for (x_mos = 0; x_mos < (m_mosaic_size + 1); x_mos++)
336               draw_bgtile_hires(layer, ii + x_mos, colour, pal, direct_colors, priority);
337            ii += x_mos - 1;
338         }
339         else
340            draw_bgtile_hires(layer, ii, colour, pal, direct_colors, priority);
341      }
342   }
343}
344
345/*************************************************************************************************
346 * SNES BG layers
347 *
348 * BG drawing theory of each scanline is quite easy: depending on the graphics Mode (0-7), there
349 * are up to 4 background layers. Pixels for each BG layer can have two different priorities.
350 * Depending on the line and on the BGHOFS and BGVOFS PPU registers, we first determine the tile
351 * address in m_vram (by determining x,y coord and tile size and by calling get_tmap_addr).
352 * Then, we load the correspondent data and we determine the tile properties: which priority to
353 * use, which palette etc. Finally, for each pixel of the tile appearing on screen, we check if
354 * the tile priority is higher than the BG/OAM already stored in that pixel for that line. If so
355 * we store the pixel in the buffer, otherwise we discard it.
356 *
357 * Of course, depending on the graphics Mode, it might be easier or harder to determine the proper
358 * tile address in vram (Mode 7 uses different registers, Mode 2, 4 and 6 uses OPT effect, etc.),
359 * but in general it works as described.
360 *************************************************************************************************/
361
362/*********************************************
363 * get_tmap_addr()
364 *
365 * Find the address in VRAM of the tile (x,y)
366 *********************************************/
367
368inline UINT32 snes_ppu_class::get_tmap_addr( UINT8 layer, UINT8 tile_size, UINT32 base, UINT32 x, UINT32 y )
369{
370   UINT32 res = base;
371   x  >>= (3 + tile_size);
372   y  >>= (3 + tile_size);
373
374   res += (m_layer[layer].tilemap_size & 2) ? ((y & 0x20) << ((m_layer[layer].tilemap_size & 1) ? 7 : 6)) : 0;
375   /* Scroll vertically */
376   res += (y & 0x1f) << 6;
377   /* Offset horizontally */
378   res += (m_layer[layer].tilemap_size & 1) ? ((x & 0x20) << 6) : 0;
379   /* Scroll horizontally */
380   res += (x & 0x1f) << 1;
381
382   return res;
383}
384
385/*********************************************
386 * update_line()
387 *
388 * Update an entire line of tiles.
389 *********************************************/
390
391inline void snes_ppu_class::update_line( UINT16 curline, UINT8 layer, UINT8 priority_b, UINT8 priority_a, UINT8 color_depth, UINT8 hires, UINT8 offset_per_tile, UINT8 direct_colors )
392{
393   UINT32 tmap, tile, xoff, yoff, charaddr, addr;
394   UINT16 ii = 0, vflip, hflip, pal, pal_direct, tilemap;
395   UINT8 xscroll, priority;
396   INT8 yscroll;
397   int tile_incr = 0;
398   UINT16 opt_bit = (layer == SNES_BG1) ? 13 : (layer == SNES_BG2) ? 14 : 0;
399   UINT8 tile_size;
400   /* variables depending on color_depth */
401   UINT8 color_planes = 2 << color_depth;
402   /* below we cheat to simplify the code: 8BPP should have 0 pal offset, not 0x100 (but we take care of this by later using pal % FIXED_COLOUR) */
403   UINT8 color_shift = 2 << color_depth;
404
405#if SNES_LAYER_DEBUG
406   if (m_debug_options.bg_disabled[layer])
407      return;
408#endif /* SNES_LAYER_DEBUG */
409
410   m_scanlines[SNES_MAINSCREEN].enable = m_layer[layer].main_bg_enabled;
411   m_scanlines[SNES_SUBSCREEN].enable = m_layer[layer].sub_bg_enabled;
412   m_scanlines[SNES_MAINSCREEN].clip = m_layer[layer].main_window_enabled;
413   m_scanlines[SNES_SUBSCREEN].clip = m_layer[layer].sub_window_enabled;
414
415   if (!m_scanlines[SNES_MAINSCREEN].enable && !m_scanlines[SNES_SUBSCREEN].enable)
416      return;
417
418   /* Handle Mosaic effects */
419   if (m_layer[layer].mosaic_enabled)
420      curline -= (curline % (m_mosaic_size + 1));
421
422   if ((m_interlace == 2) && !hires && !m_pseudo_hires)
423      curline /= 2;
424
425   /* Find the size of the tiles (8x8 or 16x16) */
426   tile_size = m_layer[layer].tile_size;
427
428   /* Find scroll info */
429   xoff = m_layer[layer].hoffs;
430   yoff = m_layer[layer].voffs;
431
432   xscroll = xoff & ((1 << (3 + tile_size)) - 1);
433
434   /* Jump to base map address */
435   tmap = m_layer[layer].tilemap << 9;
436   charaddr = m_layer[layer].charmap << 13;
437
438   while (ii < 256 + (8 << tile_size))
439   {
440      // determine the horizontal position (Bishojo Janshi Suchi Pai & Desert Figther have tile_size & hires == 1)
441      UINT32 xpos = xoff + (ii << (tile_size * hires));
442      UINT32 ypos = yoff + curline;
443
444      if (offset_per_tile != SNES_OPT_NONE)
445      {
446         int opt_x = ii + (xoff & 7);
447         UINT32 haddr = 0, vaddr = 0;
448         UINT16 hval = 0, vval = 0;
449
450         if (opt_x >= 8)
451         {
452            switch (offset_per_tile)
453            {
454            case SNES_OPT_MODE2:
455            case SNES_OPT_MODE6:
456               haddr = get_tmap_addr(SNES_BG3, m_layer[SNES_BG3].tile_size, m_layer[SNES_BG3].tilemap << 9, (opt_x - 8) + ((m_layer[SNES_BG3].hoffs & 0x3ff) & ~7), (m_layer[SNES_BG3].voffs & 0x3ff));
457               vaddr = get_tmap_addr(SNES_BG3, m_layer[SNES_BG3].tile_size, m_layer[SNES_BG3].tilemap << 9, (opt_x - 8) + ((m_layer[SNES_BG3].hoffs & 0x3ff) & ~7), (m_layer[SNES_BG3].voffs & 0x3ff) + 8);
458               hval = m_vram[haddr % SNES_VRAM_SIZE] | (m_vram[(haddr + 1) % SNES_VRAM_SIZE] << 8);
459               vval = m_vram[vaddr % SNES_VRAM_SIZE] | (m_vram[(vaddr + 1) % SNES_VRAM_SIZE] << 8);
460               if (BIT(hval, opt_bit))
461                  xpos = opt_x + (hval & ~7);
462               if (BIT(vval, opt_bit))
463                  ypos = curline + vval;
464               break;
465            case SNES_OPT_MODE4:
466               haddr = get_tmap_addr(SNES_BG3, m_layer[SNES_BG3].tile_size, m_layer[SNES_BG3].tilemap << 9, (opt_x - 8) + ((m_layer[SNES_BG3].hoffs & 0x3ff) & ~7), (m_layer[SNES_BG3].voffs & 0x3ff));
467               hval = m_vram[haddr % SNES_VRAM_SIZE] | (m_vram[(haddr + 1) % SNES_VRAM_SIZE] << 8);
468               if (BIT(hval, opt_bit))
469               {
470                  if (!BIT(hval, 15))
471                     xpos = opt_x + (hval & ~7);
472                  else
473                     ypos = curline + hval;
474               }
475               break;
476            }
477         }
478      }
479
480      addr = get_tmap_addr(layer, tile_size, tmap, xpos, ypos);
481
482      /*
483      Tilemap format
484        vhopppcc cccccccc
485
486        v/h  = Vertical/Horizontal flip this tile.
487        o    = Tile priority.
488        ppp  = Tile palette. The number of entries in the palette depends on the Mode and the BG.
489        cccccccccc = Tile number.
490      */
491      tilemap = m_vram[addr % SNES_VRAM_SIZE] | (m_vram[(addr + 1) % SNES_VRAM_SIZE] << 8);
492      vflip = BIT(tilemap, 15);
493      hflip = BIT(tilemap, 14);
494      priority = BIT(tilemap, 13) ? priority_a : priority_b;
495      pal_direct = ((tilemap & 0x1c00) >> 8);
496      tile = tilemap & 0x03ff;
497
498      pal = ((pal_direct >> 2) << color_shift);
499
500      /* Mode 0 palettes are layer specific */
501      if (m_mode == 0)
502      {
503         pal += (layer << 5);
504      }
505
506#if SNES_LAYER_DEBUG
507      /* if we want to draw only one of the priorities of this layer */
508      if (((m_debug_options.select_pri[layer] & 0x01) && (priority == priority_a)) ||
509         ((m_debug_options.select_pri[layer] & 0x02) && (priority == priority_b)))
510      {
511         if (!hires && tile_size)
512            ii += 16;
513         else
514            ii += 8;
515         continue;
516      }
517#endif /* SNES_LAYER_DEBUG */
518
519      /* figure out which line to draw */
520      yscroll = ypos & ((8 << tile_size) - 1);
521
522      if (tile_size)
523         if (BIT(yscroll, 3) != vflip)
524            tile += 16;
525
526      if (yscroll > 7)
527         yscroll &= 7;
528
529      if (vflip)
530         yscroll = 7 - yscroll;
531
532      yscroll <<= 1;
533
534      /* if we have to draw 16 pixels, set tile_incr and adjust tile for horizontal flip */
535      if (tile_size || hires)
536      {
537         if (hflip)
538         {
539            tile += 1;
540            tile_incr = -1; // next 8 pixels from previous tile (because of hflip)
541         }
542         else
543            tile_incr = 1;  // next 8 pixels from next tile
544      }
545
546      if (hires)
547      {
548         /* draw 16 pixels (the routine will automatically send half of them to the mainscreen scanline and half to the subscreen one) */
549         draw_tile(color_planes, layer, charaddr + (((tile + 0)         & 0x3ff) * 8 * color_planes) + yscroll, (ii - xscroll) * 2,     priority, hflip, direct_colors, direct_colors ? pal_direct : pal, hires);
550         draw_tile(color_planes, layer, charaddr + (((tile + tile_incr) & 0x3ff) * 8 * color_planes) + yscroll, (ii - xscroll) * 2 + 8, priority, hflip, direct_colors, direct_colors ? pal_direct : pal, hires);
551         ii += 8;
552      }
553      else
554      {
555         draw_tile(color_planes, layer, charaddr + ((tile & 0x3ff) * 8 * color_planes) + yscroll, ii - xscroll, priority, hflip, direct_colors, direct_colors ? pal_direct : pal, hires);
556         ii += 8;
557
558         if (tile_size)
559         {
560            draw_tile(color_planes, layer, charaddr + (((tile + tile_incr) & 0x3ff) * 8 * color_planes) + yscroll, ii - xscroll, priority, hflip, direct_colors, direct_colors ? pal_direct : pal, hires);
561            ii += 8;
562         }
563      }
564   }
565}
566
567
568/*********************************************
569 * update_line_mode7()
570 *
571 * Update an entire line of mode7 tiles.
572 *********************************************/
573
574#define MODE7_CLIP(x) (((x) & 0x2000) ? ((x) | ~0x03ff) : ((x) & 0x03ff))
575
576void snes_ppu_class::update_line_mode7( UINT16 curline, UINT8 layer, UINT8 priority_b, UINT8 priority_a )
577{
578   UINT32 tiled;
579   INT16 ma, mb, mc, md;
580   INT32 xc, yc, tx, ty, sx, sy, hs, vs, xpos, xdir, x0, y0;
581   UINT8 priority = priority_b;
582   UINT8 colour = 0;
583   UINT16 *mosaic_x, *mosaic_y;
584   UINT16 c;
585   int screen;
586
587#if SNES_LAYER_DEBUG
588   if (m_debug_options.bg_disabled[layer])
589      return;
590#endif /* SNES_LAYER_DEBUG */
591
592   m_scanlines[SNES_MAINSCREEN].enable = m_layer[layer].main_bg_enabled;
593   m_scanlines[SNES_SUBSCREEN].enable = m_layer[layer].sub_bg_enabled;
594   m_scanlines[SNES_MAINSCREEN].clip = m_layer[layer].main_window_enabled;
595   m_scanlines[SNES_SUBSCREEN].clip = m_layer[layer].sub_window_enabled;
596
597   if (!m_scanlines[SNES_MAINSCREEN].enable && !m_scanlines[SNES_SUBSCREEN].enable)
598      return;
599
600   ma = m_mode7.matrix_a;
601   mb = m_mode7.matrix_b;
602   mc = m_mode7.matrix_c;
603   md = m_mode7.matrix_d;
604   xc = m_mode7.origin_x;
605   yc = m_mode7.origin_y;
606   hs = m_mode7.hor_offset;
607   vs = m_mode7.ver_offset;
608
609   /* Sign extend */
610   xc <<= 19;
611   xc >>= 19;
612   yc <<= 19;
613   yc >>= 19;
614   hs <<= 19;
615   hs >>= 19;
616   vs <<= 19;
617   vs >>= 19;
618
619   /* Vertical flip */
620   if (m_mode7.vflip)
621      sy = 255 - curline;
622   else
623      sy = curline;
624
625   /* Horizontal flip */
626   if (m_mode7.hflip)
627   {
628      xpos = 255;
629      xdir = -1;
630   }
631   else
632   {
633      xpos = 0;
634      xdir = 1;
635   }
636
637   /* MOSAIC - to be verified */
638   if (layer == SNES_BG2)  // BG2 use two different bits for horizontal and vertical mosaic
639   {
640      mosaic_x = m_mosaic_table[m_layer[SNES_BG2].mosaic_enabled ? m_mosaic_size : 0];
641      mosaic_y = m_mosaic_table[m_layer[SNES_BG1].mosaic_enabled ? m_mosaic_size : 0];
642   }
643   else    // BG1 works as usual
644   {
645      mosaic_x =  m_mosaic_table[m_layer[SNES_BG1].mosaic_enabled ? m_mosaic_size : 0];
646      mosaic_y =  m_mosaic_table[m_layer[SNES_BG1].mosaic_enabled ? m_mosaic_size : 0];
647   }
648
649#if SNES_LAYER_DEBUG
650   if (m_debug_options.mosaic_disabled)
651   {
652      mosaic_x =  m_mosaic_table[0];
653      mosaic_y =  m_mosaic_table[0];
654   }
655#endif /* SNES_LAYER_DEBUG */
656
657   /* Let's do some mode7 drawing huh? */
658   /* These can be computed only once, since they do not depend on sx */
659   x0 = ((ma * MODE7_CLIP(hs - xc)) & ~0x3f) + ((mb * mosaic_y[sy]) & ~0x3f) + ((mb * MODE7_CLIP(vs - yc)) & ~0x3f) + (xc << 8);
660   y0 = ((mc * MODE7_CLIP(hs - xc)) & ~0x3f) + ((md * mosaic_y[sy]) & ~0x3f) + ((md * MODE7_CLIP(vs - yc)) & ~0x3f) + (yc << 8);
661
662   for (sx = 0; sx < 256; sx++, xpos += xdir)
663   {
664      tx = (x0 + (ma * mosaic_x[sx])) >> 8;
665      ty = (y0 + (mc * mosaic_x[sx])) >> 8;
666
667      switch (m_mode7.repeat)
668      {
669         case 0x00:  /* Repeat if outside screen area */
670         case 0x01:  /* Repeat if outside screen area */
671            tx &= 0x3ff;
672            ty &= 0x3ff;
673            tiled = m_vram[((((tx >> 3) & 0x7f) + (((ty >> 3) & 0x7f) * 128)) * 2) % SNES_VRAM_SIZE] << 7;
674            colour = m_vram[(tiled + ((tx & 0x07) * 2) + ((ty & 0x07) * 16) + 1) % SNES_VRAM_SIZE];
675            break;
676         case 0x02:  /* Single colour backdrop screen if outside screen area */
677            if ((tx >= 0) && (tx < 1024) && (ty >= 0) && (ty < 1024))
678            {
679               tiled = m_vram[((((tx >> 3) & 0x7f) + (((ty >> 3) & 0x7f) * 128)) * 2) % SNES_VRAM_SIZE] << 7;
680               colour = m_vram[(tiled + ((tx & 0x07) * 2) + ((ty & 0x07) * 16) + 1) % SNES_VRAM_SIZE];
681            }
682            else
683               colour = 0;
684            break;
685         case 0x03:  /* Character 0x00 repeat if outside screen area */
686            if ((tx >= 0) && (tx < 1024) && (ty >= 0) && (ty < 1024))
687               tiled = m_vram[((((tx >> 3) & 0x7f) + (((ty >> 3) & 0x7f) * 128)) * 2) % SNES_VRAM_SIZE] << 7;
688            else
689               tiled = 0;
690
691            colour = m_vram[(tiled + ((tx & 0x07) * 2) + ((ty & 0x07) * 16) + 1) % SNES_VRAM_SIZE];
692            break;
693      }
694
695      /* The last bit is for priority in EXTBG mode (used only for BG2) */
696      if (layer == SNES_BG2)
697      {
698         priority = ((colour & 0x80) >> 7) ? priority_a : priority_b;
699         colour &= 0x7f;
700
701#if SNES_LAYER_DEBUG
702      /* if we want to draw only one of the priorities of this layer */
703      if (((m_debug_options.select_pri[layer] & 0x01) && (priority == priority_a)) ||
704         ((m_debug_options.select_pri[layer] & 0x02) && (priority == priority_b)))
705         continue;
706#endif /* SNES_LAYER_DEBUG */
707      }
708
709      for (screen = SNES_MAINSCREEN; screen <= SNES_SUBSCREEN; screen++)
710      {
711         if (m_scanlines[screen].enable)
712         {
713            UINT8 clr = colour;
714            UINT8 clipmask = m_clipmasks[layer][xpos];
715
716#if SNES_LAYER_DEBUG
717            if (m_debug_options.windows_disabled)
718               clipmask = 0xff;
719#endif /* SNES_LAYER_DEBUG */
720
721            /* Clip to windows */
722            if (m_scanlines[screen].clip)
723               clr &= clipmask;
724
725            /* Draw pixel if appropriate */
726            if (m_scanlines[screen].priority[xpos] <= priority && clr > 0)
727            {
728               /* Direct select, but only outside EXTBG! */
729               // Direct color format is: 0 | BB000 | GGG00 | RRR00, HW confirms that the data is zero padded.
730               // In other words, like normal direct color, with pal = 0
731               c = get_bgcolor(m_direct_color && layer == SNES_BG1, 0, clr);
732               set_scanline_pixel(screen, xpos, c, priority, layer, 0);
733            }
734         }
735      }
736   }
737}
738
739/*************************************************************************************************
740 * SNES Sprites
741 *
742 * 1. First of all: sprites are drawn one line in advance. We emulate this by caching the
743 * starting vram address, the sprite size and the "name select" at each line, and by using
744 * them the next line to output the proper sprites - see update_obsel.
745 *
746 * 2. Each line can select its sprites among 128 available ones in oam_ram, hence we start
747 * by creating a list of the available objects (each one with its x,y coordinate, its size,
748 * its tile address, etc.) - see oam_list_build.
749 *
750 * 3. Next, we start finding out which sprites will appear in the line: starting from
751 * FirstSprite, we count 32 OBJs which intersect our line and we store their indexes in the
752 * oam_itemlist array (if more than 32 sprites intersect our line, we set the Range Over
753 * flag); then, selecting among these sprites, we count 34 8x8 tiles which are visible
754 * in our line (i.e. whose x coord is between -size and 256) and we store the corresponding
755 * coordinates/priorities/palettes/etc. in the oam_tilelist array (if more than 34 tiles would
756 * appear on screen, we set the Time Over flag).
757 * Notice that when we populate oam_tilelist, we proceed from oam_itemlist[31] (or from the last
758 * item which intersects the scanline), towards oam_itemlist[0], i.e. the higher tiles (say
759 * oam_tilelist[34], or the last tile which appear on screen) will contain FirstSprite object,
760 * or the sprites with closer index to FirstSprite which get displayed. This will play an
761 * important role for sprite priority - see update_objects_rto.
762 *
763 * 4. All the above happens at the beginning of each VIDEO_UPDATE. When we finally draw the
764 * scanline, we pass through the oam_tilelist and we store the displayed pixels in our scanline
765 * buffer. Notice that, for each pixel of a SNES sprite, only the priority of the topmost sprite
766 * is tested against the priority of the BG pixel (because FirstSprite is on top of FirstSprite+1,
767 * which is on top of FirstSprite+2, etc., and therefore other sprites are already covered by the
768 * topmost one). To emulate this, we draw each tile over the previous ones no matter what
769 * priorities are (differently from what we did with BGs): in the end, we will have in each pixel z
770 * its topmost sprite and scanline.priority[z] will be the topmost sprite priority as expected.
771 * Of course, sprite drawing must happen before BG drawing, so that afterwords BG pixels properly
772 * test their priority with the one of the correct sprite - see update_objects.
773 *************************************************************************************************/
774
775
776/*********************************************
777 * update_obsel()
778 *
779 * Update sprite settings for next line.
780 *********************************************/
781
782void snes_ppu_class::update_obsel( void )
783{
784   m_layer[SNES_OAM].charmap = m_oam.next_charmap;
785   m_oam.name_select = m_oam.next_name_select;
786
787   if (m_oam.size != m_oam.next_size)
788   {
789      m_oam.size = m_oam.next_size;
790      m_update_oam_list = 1;
791   }
792}
793
794/*********************************************
795 * oam_list_build()
796 *
797 * Build a list of the available obj in OAM ram.
798 *********************************************/
799
800void snes_ppu_class::oam_list_build( void )
801{
802   UINT8 *oamram = (UINT8 *)m_oam_ram;
803   INT16 oam = 0x1ff;
804   UINT16 oam_extra = oam + 0x20;
805   UINT16 extra = 0;
806   int ii;
807
808   m_update_oam_list = 0;       // eventually, we can optimize the code by only calling this function when there is a change in size
809
810   for (ii = 127; ii >= 0; ii--)
811   {
812      if (((ii + 1) % 4) == 0)
813         extra = oamram[oam_extra--];
814
815      m_oam_spritelist[ii].vflip = (oamram[oam] & 0x80) >> 7;
816      m_oam_spritelist[ii].hflip = (oamram[oam] & 0x40) >> 6;
817      m_oam_spritelist[ii].priority_bits = (oamram[oam] & 0x30) >> 4;
818      m_oam_spritelist[ii].pal = 128 + ((oamram[oam] & 0x0e) << 3);
819      m_oam_spritelist[ii].tile = (oamram[oam--] & 0x1) << 8;
820      m_oam_spritelist[ii].tile |= oamram[oam--];
821      m_oam_spritelist[ii].y = oamram[oam--] + 1;
822      m_oam_spritelist[ii].x = oamram[oam--];
823      m_oam_spritelist[ii].size = (extra & 0x80) >> 7;
824      extra <<= 1;
825      m_oam_spritelist[ii].x |= ((extra & 0x80) << 1);
826      extra <<= 1;
827
828      m_oam_spritelist[ii].y *= m_obj_interlace;
829      m_oam_spritelist[ii].y &= 0x1ff;
830
831      m_oam_spritelist[ii].x &= 0x1ff;
832
833      /* Determine object size */
834      switch (m_oam.size)
835      {
836      case 0:         /* 8x8 or 16x16 */
837         m_oam_spritelist[ii].width  = m_oam_spritelist[ii].size ? 2 : 1;
838         m_oam_spritelist[ii].height = m_oam_spritelist[ii].size ? 2 : 1;
839         break;
840      case 1:         /* 8x8 or 32x32 */
841         m_oam_spritelist[ii].width  = m_oam_spritelist[ii].size ? 4 : 1;
842         m_oam_spritelist[ii].height = m_oam_spritelist[ii].size ? 4 : 1;
843         break;
844      case 2:         /* 8x8 or 64x64 */
845         m_oam_spritelist[ii].width  = m_oam_spritelist[ii].size ? 8 : 1;
846         m_oam_spritelist[ii].height = m_oam_spritelist[ii].size ? 8 : 1;
847         break;
848      case 3:         /* 16x16 or 32x32 */
849         m_oam_spritelist[ii].width  = m_oam_spritelist[ii].size ? 4 : 2;
850         m_oam_spritelist[ii].height = m_oam_spritelist[ii].size ? 4 : 2;
851         break;
852      case 4:         /* 16x16 or 64x64 */
853         m_oam_spritelist[ii].width  = m_oam_spritelist[ii].size ? 8 : 2;
854         m_oam_spritelist[ii].height = m_oam_spritelist[ii].size ? 8 : 2;
855         break;
856      case 5:         /* 32x32 or 64x64 */
857         m_oam_spritelist[ii].width  = m_oam_spritelist[ii].size ? 8 : 4;
858         m_oam_spritelist[ii].height = m_oam_spritelist[ii].size ? 8 : 4;
859         break;
860      case 6:         /* undocumented: 16x32 or 32x64 */
861         m_oam_spritelist[ii].width  = m_oam_spritelist[ii].size ? 4 : 2;
862         m_oam_spritelist[ii].height = m_oam_spritelist[ii].size ? 8 : 4;
863         if (m_obj_interlace && !m_oam_spritelist[ii].size)
864            m_oam_spritelist[ii].height = 2;
865         break;
866      case 7:         /* undocumented: 16x32 or 32x32 */
867         m_oam_spritelist[ii].width  = m_oam_spritelist[ii].size ? 4 : 2;
868         m_oam_spritelist[ii].height = m_oam_spritelist[ii].size ? 4 : 4;
869         if (m_obj_interlace && !m_oam_spritelist[ii].size)
870            m_oam_spritelist[ii].height = 2;
871         break;
872      default:
873         /* we should never enter here... */
874         logerror("Object size unsupported: %d\n", m_oam.size);
875         break;
876      }
877   }
878}
879
880/*********************************************
881 * is_sprite_on_scanline()
882 *
883 * Check if a given sprites intersect current
884 * scanline
885 *********************************************/
886
887int snes_ppu_class::is_sprite_on_scanline( UINT16 curline, UINT8 sprite )
888{
889   //if sprite is entirely offscreen and doesn't wrap around to the left side of the screen,
890   //then it is not counted. this *should* be 256, and not 255, even though dot 256 is offscreen.
891   int spr_height = (m_oam_spritelist[sprite].height << 3);
892
893   if (m_oam_spritelist[sprite].x > 256 && (m_oam_spritelist[sprite].x + (m_oam_spritelist[sprite].width << 3) - 1) < 512)
894      return 0;
895
896   if (curline >= m_oam_spritelist[sprite].y && curline < (m_oam_spritelist[sprite].y + spr_height))
897      return 1;
898
899   if ((m_oam_spritelist[sprite].y + spr_height) >= 256 && curline < ((m_oam_spritelist[sprite].y + spr_height) & 255))
900      return 1;
901
902   return 0;
903}
904
905/*********************************************
906 * update_objects_rto()
907 *
908 * Determine which OBJs will be drawn on this
909 * scanline.
910 *********************************************/
911
912void snes_ppu_class::update_objects_rto( UINT16 curline )
913{
914   int ii, jj, active_sprite;
915   UINT8 range_over, time_over;
916   INT8 xs, ys;
917   UINT8 line;
918   UINT8 height, width, vflip, hflip, priority, pal;
919   UINT16 tile;
920   INT16 x, y;
921   UINT32 name_sel = 0;
922
923   oam_list_build();
924
925   /* initialize counters */
926   range_over = 0;
927   time_over = 0;
928
929   /* setup the proper line */
930   curline /= m_interlace;
931   curline *= m_obj_interlace;
932
933   /* reset the list of first 32 objects which intersect current scanline */
934   memset(m_oam_itemlist, 0xff, 32);
935
936   /* populate the list of 32 objects */
937   for (ii = 0; ii < 128; ii++)
938   {
939      active_sprite = (ii + m_oam.first_sprite) & 0x7f;
940
941      if (!is_sprite_on_scanline(curline, active_sprite))
942         continue;
943
944      if (range_over++ >= 32)
945         break;
946
947      m_oam_itemlist[range_over - 1] = active_sprite;
948   }
949
950   /* reset the list of first 34 tiles to be drawn */
951   for (ii = 0; ii < 34; ii++)
952      m_oam_tilelist[ii].tileaddr = 0xffff;
953
954   /* populate the list of 34 tiles */
955   for (ii = 31; ii >= 0; ii--)
956   {
957      if (m_oam_itemlist[ii] == 0xff)
958         continue;
959
960      active_sprite = m_oam_itemlist[ii];
961
962      tile = m_oam_spritelist[active_sprite].tile;
963      x = m_oam_spritelist[active_sprite].x;
964      y = m_oam_spritelist[active_sprite].y;
965      height = m_oam_spritelist[active_sprite].height;
966      width = m_oam_spritelist[active_sprite].width;
967      vflip = m_oam_spritelist[active_sprite].vflip;
968      hflip = m_oam_spritelist[active_sprite].hflip;
969      priority = m_oam_spritelist[active_sprite].priority_bits;
970      pal = m_oam_spritelist[active_sprite].pal;
971
972      /* Adjust y, if past maximum position (for sprites which overlap between top & bottom) */
973      if (y >= (0x100 - 16) * m_interlace)
974         y -= (0x100) * m_interlace;
975
976      if (curline >= y && curline < (y + (height << 3)))
977      {
978         /* Only objects using tiles over 255 use name select */
979         name_sel = (tile < 256) ? 0 : m_oam.name_select;
980
981         ys = (curline - y) >> 3;
982         line = (curline - y) % 8;
983         if (vflip)
984         {
985            ys = height - ys - 1;
986            line = 7 - line;
987         }
988         line <<= 1;
989         tile <<= 5;
990
991         for (jj = 0; jj < width; jj++)
992         {
993            INT16 xx = (x + (jj << 3)) & 0x1ff;
994
995            if (x != 256 && xx >= 256 && (xx + 7) < 512)
996               continue;
997
998            if (time_over++ >= 34)
999               break;
1000
1001            xs = (hflip) ? (width - 1 - jj) : jj;
1002            m_oam_tilelist[time_over - 1].tileaddr = name_sel + tile + table_obj_offset[ys][xs] + line;
1003            m_oam_tilelist[time_over - 1].hflip = hflip;
1004            m_oam_tilelist[time_over - 1].x = xx;
1005            m_oam_tilelist[time_over - 1].pal = pal;
1006            m_oam_tilelist[time_over - 1].priority = priority;
1007         }
1008      }
1009   }
1010
1011   /* set Range Over flag if necessary */
1012   if (range_over > 32)
1013      m_stat77 |= 0x40;
1014
1015   /* set Time Over flag if necessary */
1016   if (time_over > 34)
1017      m_stat77 |= 0x80;
1018}
1019
1020/*********************************************
1021 * update_objects()
1022 *
1023 * Update an entire line of sprites.
1024 *********************************************/
1025
1026void snes_ppu_class::update_objects( UINT8 priority_oam0, UINT8 priority_oam1, UINT8 priority_oam2, UINT8 priority_oam3 )
1027{
1028   UINT8 pri, priority[4];
1029   UINT32 charaddr;
1030   int ii;
1031
1032#if SNES_LAYER_DEBUG
1033   if (m_debug_options.bg_disabled[SNES_OAM])
1034      return;
1035#endif /* SNES_LAYER_DEBUG */
1036
1037   m_scanlines[SNES_MAINSCREEN].enable = m_layer[SNES_OAM].main_bg_enabled;
1038   m_scanlines[SNES_SUBSCREEN].enable = m_layer[SNES_OAM].sub_bg_enabled;
1039   m_scanlines[SNES_MAINSCREEN].clip = m_layer[SNES_OAM].main_window_enabled;
1040   m_scanlines[SNES_SUBSCREEN].clip = m_layer[SNES_OAM].sub_window_enabled;
1041
1042   if (!m_scanlines[SNES_MAINSCREEN].enable && !m_scanlines[SNES_SUBSCREEN].enable)
1043      return;
1044
1045   charaddr = m_layer[SNES_OAM].charmap << 13;
1046
1047   priority[0] = priority_oam0;
1048   priority[1] = priority_oam1;
1049   priority[2] = priority_oam2;
1050   priority[3] = priority_oam3;
1051
1052   /* finally draw the tiles from the tilelist */
1053   for (ii = 0; ii < 34; ii++)
1054   {
1055      int tile = ii;
1056#if SNES_LAYER_DEBUG
1057      if (m_debug_options.sprite_reversed)
1058         tile = 33 - ii;
1059#endif /* SNES_LAYER_DEBUG */
1060
1061      if (m_oam_tilelist[tile].tileaddr == 0xffff)
1062         continue;
1063
1064      pri = priority[m_oam_tilelist[tile].priority];
1065
1066#if SNES_LAYER_DEBUG
1067      if (m_debug_options.select_pri[SNES_OAM])
1068      {
1069         int oam_draw = m_debug_options.select_pri[SNES_OAM] - 1;
1070         if (oam_draw != m_oam_tilelist[tile].priority)
1071            continue;
1072      }
1073#endif /* SNES_LAYER_DEBUG */
1074
1075      /* OAM tiles have fixed planes (4), no direct color and no hires, but otherwise work the same as BG ones */
1076      draw_tile(4, SNES_OAM, charaddr + m_oam_tilelist[tile].tileaddr, m_oam_tilelist[tile].x, pri, m_oam_tilelist[tile].hflip, 0, m_oam_tilelist[tile].pal, 0);
1077   }
1078}
1079
1080
1081/*********************************************
1082 * snes_update_mode_X()
1083 *
1084 * Update Mode X line.
1085 *********************************************/
1086
1087void snes_ppu_class::update_mode_0( UINT16 curline )
1088{
1089#if SNES_LAYER_DEBUG
1090   if (m_debug_options.mode_disabled[0])
1091      return;
1092#endif /* SNES_LAYER_DEBUG */
1093
1094   update_objects(3, 6, 9, 12);
1095   update_line(curline, SNES_BG1, 8, 11, SNES_COLOR_DEPTH_2BPP, 0, SNES_OPT_NONE, 0);
1096   update_line(curline, SNES_BG2, 7, 10, SNES_COLOR_DEPTH_2BPP, 0, SNES_OPT_NONE, 0);
1097   update_line(curline, SNES_BG3, 2, 5,  SNES_COLOR_DEPTH_2BPP, 0, SNES_OPT_NONE, 0);
1098   update_line(curline, SNES_BG4, 1, 4,  SNES_COLOR_DEPTH_2BPP, 0, SNES_OPT_NONE, 0);
1099}
1100
1101void snes_ppu_class::update_mode_1( UINT16 curline )
1102{
1103#if SNES_LAYER_DEBUG
1104   if (m_debug_options.mode_disabled[1])
1105      return;
1106#endif /* SNES_LAYER_DEBUG */
1107
1108   if (!m_bg3_priority_bit)
1109   {
1110      update_objects(2, 4, 7, 10);
1111      update_line(curline, SNES_BG1, 6, 9, SNES_COLOR_DEPTH_4BPP, 0, SNES_OPT_NONE, 0);
1112      update_line(curline, SNES_BG2, 5, 8, SNES_COLOR_DEPTH_4BPP, 0, SNES_OPT_NONE, 0);
1113      update_line(curline, SNES_BG3, 1, 3, SNES_COLOR_DEPTH_2BPP, 0, SNES_OPT_NONE, 0);
1114   }
1115   else
1116   {
1117      update_objects(2, 3, 6, 9);
1118      update_line(curline, SNES_BG1, 5, 8,  SNES_COLOR_DEPTH_4BPP, 0, SNES_OPT_NONE, 0);
1119      update_line(curline, SNES_BG2, 4, 7,  SNES_COLOR_DEPTH_4BPP, 0, SNES_OPT_NONE, 0);
1120      update_line(curline, SNES_BG3, 1, 10, SNES_COLOR_DEPTH_2BPP, 0, SNES_OPT_NONE, 0);
1121   }
1122}
1123
1124void snes_ppu_class::update_mode_2( UINT16 curline )
1125{
1126#if SNES_LAYER_DEBUG
1127   if (m_debug_options.mode_disabled[2])
1128      return;
1129#endif /* SNES_LAYER_DEBUG */
1130
1131   update_objects(2, 4, 6, 8);
1132   update_line(curline, SNES_BG1, 3, 7, SNES_COLOR_DEPTH_4BPP, 0, SNES_OPT_MODE2, 0);
1133   update_line(curline, SNES_BG2, 1, 5, SNES_COLOR_DEPTH_4BPP, 0, SNES_OPT_MODE2, 0);
1134}
1135
1136void snes_ppu_class::update_mode_3( UINT16 curline )
1137{
1138#if SNES_LAYER_DEBUG
1139   if (m_debug_options.mode_disabled[3])
1140      return;
1141#endif /* SNES_LAYER_DEBUG */
1142
1143   update_objects(2, 4, 6, 8);
1144   update_line(curline, SNES_BG1, 3, 7, SNES_COLOR_DEPTH_8BPP, 0, SNES_OPT_NONE, m_direct_color);
1145   update_line(curline, SNES_BG2, 1, 5, SNES_COLOR_DEPTH_4BPP, 0, SNES_OPT_NONE, 0);
1146}
1147
1148void snes_ppu_class::update_mode_4( UINT16 curline )
1149{
1150#if SNES_LAYER_DEBUG
1151   if (m_debug_options.mode_disabled[4])
1152      return;
1153#endif /* SNES_LAYER_DEBUG */
1154
1155   update_objects(2, 4, 6, 8);
1156   update_line(curline, SNES_BG1, 3, 7, SNES_COLOR_DEPTH_8BPP, 0, SNES_OPT_MODE4, m_direct_color);
1157   update_line(curline, SNES_BG2, 1, 5, SNES_COLOR_DEPTH_2BPP, 0, SNES_OPT_MODE4, 0);
1158}
1159
1160void snes_ppu_class::update_mode_5( UINT16 curline )
1161{
1162#if SNES_LAYER_DEBUG
1163   if (m_debug_options.mode_disabled[5])
1164      return;
1165#endif /* SNES_LAYER_DEBUG */
1166
1167   update_objects(2, 4, 6, 8);
1168   update_line(curline, SNES_BG1, 3, 7, SNES_COLOR_DEPTH_4BPP, 1, SNES_OPT_NONE, 0);
1169   update_line(curline, SNES_BG2, 1, 5, SNES_COLOR_DEPTH_2BPP, 1, SNES_OPT_NONE, 0);
1170}
1171
1172void snes_ppu_class::update_mode_6( UINT16 curline )
1173{
1174#if SNES_LAYER_DEBUG
1175   if (m_debug_options.mode_disabled[6])
1176      return;
1177#endif /* SNES_LAYER_DEBUG */
1178
1179   update_objects(1, 3, 4, 6);
1180   update_line(curline, SNES_BG1, 2, 5, SNES_COLOR_DEPTH_4BPP, 1, SNES_OPT_MODE6, 0);
1181}
1182
1183void snes_ppu_class::update_mode_7( UINT16 curline )
1184{
1185#if SNES_LAYER_DEBUG
1186   if (m_debug_options.mode_disabled[7])
1187      return;
1188#endif /* SNES_LAYER_DEBUG */
1189
1190   if (!m_mode7.extbg)
1191   {
1192      update_objects(1, 3, 4, 5);
1193      update_line_mode7(curline, SNES_BG1, 2, 2);
1194   }
1195   else
1196   {
1197      update_objects(2, 4, 6, 7);
1198      update_line_mode7(curline, SNES_BG1, 3, 3);
1199      update_line_mode7(curline, SNES_BG2, 1, 5);
1200   }
1201}
1202
1203/*********************************************
1204 * snes_draw_screens()
1205 *
1206 * Draw the whole screen (Mode 0 -> 7).
1207 *********************************************/
1208
1209void snes_ppu_class::draw_screens( UINT16 curline )
1210{
1211   switch (m_mode)
1212   {
1213      case 0: update_mode_0(curline); break;     /* Mode 0 */
1214      case 1: update_mode_1(curline); break;     /* Mode 1 */
1215      case 2: update_mode_2(curline); break;     /* Mode 2 - Supports offset per tile */
1216      case 3: update_mode_3(curline); break;     /* Mode 3 - Supports direct colour */
1217      case 4: update_mode_4(curline); break;     /* Mode 4 - Supports offset per tile and direct colour */
1218      case 5: update_mode_5(curline); break;     /* Mode 5 - Supports hires */
1219      case 6: update_mode_6(curline); break;     /* Mode 6 - Supports offset per tile and hires */
1220      case 7: update_mode_7(curline); break;     /* Mode 7 - Supports direct colour */
1221   }
1222}
1223
1224/*********************************************
1225 * update_windowmasks()
1226 *
1227 * An example of how windows work:
1228 * Win1: ...#####......
1229 * Win2: ......#####...
1230 *             IN                 OUT
1231 * OR:   ...########...     ###........###
1232 * AND:  ......##......     ######..######
1233 * XOR:  ...###..###...     ###...##...###
1234 * XNOR: ###...##...###     ...###..###...
1235 *********************************************/
1236
1237void snes_ppu_class::update_windowmasks( void )
1238{
1239   UINT16 ii, jj;
1240   INT8 w1, w2;
1241
1242   m_update_windows = 0;        /* reset the flag */
1243
1244   for (ii = 0; ii < SNES_SCR_WIDTH; ii++)
1245   {
1246      /* update bg 1, 2, 3, 4, obj & color windows */
1247      /* jj = layer */
1248      for (jj = 0; jj < 6; jj++)
1249      {
1250         m_clipmasks[jj][ii] = 0xff;  /* let's start from un-masked */
1251         w1 = w2 = -1;
1252
1253         if (m_layer[jj].window1_enabled)
1254         {
1255            /* Default to mask area inside */
1256            if ((ii < m_window1_left) || (ii > m_window1_right))
1257               w1 = 0;
1258            else
1259               w1 = 1;
1260
1261            /* If mask area is outside then swap */
1262            if (m_layer[jj].window1_invert)
1263               w1 = !w1;
1264         }
1265
1266         if (m_layer[jj].window2_enabled)
1267         {
1268            if ((ii < m_window2_left) || (ii > m_window2_right))
1269               w2 = 0;
1270            else
1271               w2 = 1;
1272            if (m_layer[jj].window2_invert)
1273               w2 = !w2;
1274         }
1275
1276         /* mask if the appropriate expression is true */
1277         if (w1 >= 0 && w2 >= 0)
1278         {
1279            switch (m_layer[jj].wlog_mask)
1280            {
1281               case 0x00:  /* OR */
1282                  m_clipmasks[jj][ii] = (w1 | w2) ? 0x00 : 0xff;
1283                  break;
1284               case 0x01:  /* AND */
1285                  m_clipmasks[jj][ii] = (w1 & w2) ? 0x00 : 0xff;
1286                  break;
1287               case 0x02:  /* XOR */
1288                  m_clipmasks[jj][ii] = (w1 ^ w2) ? 0x00 : 0xff;
1289                  break;
1290               case 0x03:  /* XNOR */
1291                  m_clipmasks[jj][ii] = !(w1 ^ w2) ? 0x00 : 0xff;
1292                  break;
1293            }
1294         }
1295         else if (w1 >= 0)
1296            m_clipmasks[jj][ii] = w1 ? 0x00 : 0xff;
1297         else if (w2 >= 0)
1298            m_clipmasks[jj][ii] = w2 ? 0x00 : 0xff;
1299      }
1300   }
1301}
1302
1303/*********************************************
1304 * update_offsets()
1305 *
1306 * Update the offsets with the latest changes.
1307 * This is currently unused, but it could
1308 * possibly be handy for some minor optimization
1309 *********************************************/
1310
1311void snes_ppu_class::update_offsets( void )
1312{
1313   int ii;
1314   for (ii = 0; ii < 4; ii++)
1315   {
1316   }
1317   m_update_offsets = 0;
1318}
1319
1320/*****************************************
1321 * draw_blend()
1322 *
1323 * Routine for additive/subtractive blending
1324 * between the main and sub screens, i.e.
1325 * color math.
1326 *****************************************/
1327
1328inline void snes_ppu_class::draw_blend( UINT16 offset, UINT16 *colour, UINT8 prevent_color_math, UINT8 black_pen_clip, int switch_screens )
1329{
1330#if SNES_LAYER_DEBUG
1331   if (m_debug_options.colormath_disabled)
1332      return;
1333#endif /* SNES_LAYER_DEBUG */
1334
1335   /* when color math is applied to subscreen pixels, the blending depends on the blending used by the previous mainscreen
1336   pixel, except for subscreen pixel 0 which has no previous mainscreen pixel, see comments in refresh_scanline */
1337   if (switch_screens && offset > 0)
1338      offset -= 1;
1339
1340   if ((black_pen_clip == SNES_CLIP_ALWAYS) ||
1341      (black_pen_clip == SNES_CLIP_IN && m_clipmasks[SNES_COLOR][offset]) ||
1342      (black_pen_clip == SNES_CLIP_OUT && !m_clipmasks[SNES_COLOR][offset]))
1343      *colour = 0; //clip to black before color math
1344
1345   if (prevent_color_math == SNES_CLIP_ALWAYS) // blending mode 3 == always OFF
1346      return;
1347
1348   if ((prevent_color_math == SNES_CLIP_NEVER) ||
1349      (prevent_color_math == SNES_CLIP_IN  && !m_clipmasks[SNES_COLOR][offset]) ||
1350      (prevent_color_math == SNES_CLIP_OUT && m_clipmasks[SNES_COLOR][offset]))
1351   {
1352      UINT16 r, g, b;
1353      struct SNES_SCANLINE *subscreen;
1354      int clip_max = 0;   // if add then clip to 0x1f, if sub then clip to 0
1355
1356#if SNES_LAYER_DEBUG
1357      /* Toggle drawing of SNES_SUBSCREEN or SNES_MAINSCREEN */
1358      if (m_debug_options.draw_subscreen)
1359      {
1360         subscreen = switch_screens ? &m_scanlines[SNES_SUBSCREEN] : &m_scanlines[SNES_MAINSCREEN];
1361      }
1362      else
1363#endif /* SNES_LAYER_DEBUG */
1364      {
1365         subscreen = switch_screens ? &m_scanlines[SNES_MAINSCREEN] : &m_scanlines[SNES_SUBSCREEN];
1366      }
1367
1368      if (m_sub_add_mode) /* SNES_SUBSCREEN*/
1369      {
1370         if (!BIT(m_color_modes, 7))
1371         {
1372            /* 0x00 add */
1373            r = (*colour & 0x1f) + (subscreen->buffer[offset] & 0x1f);
1374            g = ((*colour & 0x3e0) >> 5) + ((subscreen->buffer[offset] & 0x3e0) >> 5);
1375            b = ((*colour & 0x7c00) >> 10) + ((subscreen->buffer[offset] & 0x7c00) >> 10);
1376            clip_max = 1;
1377         }
1378         else
1379         {
1380            /* 0x80 sub */
1381            r = (*colour & 0x1f) - (subscreen->buffer[offset] & 0x1f);
1382            g = ((*colour & 0x3e0) >> 5) - ((subscreen->buffer[offset] & 0x3e0) >> 5);
1383            b = ((*colour & 0x7c00) >> 10) - ((subscreen->buffer[offset] & 0x7c00) >> 10);
1384            if (r > 0x1f) r = 0;
1385            if (g > 0x1f) g = 0;
1386            if (b > 0x1f) b = 0;
1387         }
1388         /* only halve if the color is not the back colour */
1389         if (BIT(m_color_modes, 6) && (subscreen->buffer[offset] != m_cgram[FIXED_COLOUR]))
1390         {
1391            r >>= 1;
1392            g >>= 1;
1393            b >>= 1;
1394         }
1395      }
1396      else /* Fixed colour */
1397      {
1398         if (!BIT(m_color_modes, 7))
1399         {
1400            /* 0x00 add */
1401            r = (*colour & 0x1f) + (m_cgram[FIXED_COLOUR] & 0x1f);
1402            g = ((*colour & 0x3e0) >> 5) + ((m_cgram[FIXED_COLOUR] & 0x3e0) >> 5);
1403            b = ((*colour & 0x7c00) >> 10) + ((m_cgram[FIXED_COLOUR] & 0x7c00) >> 10);
1404            clip_max = 1;
1405         }
1406         else
1407         {
1408            /* 0x80: sub */
1409            r = (*colour & 0x1f) - (m_cgram[FIXED_COLOUR] & 0x1f);
1410            g = ((*colour & 0x3e0) >> 5) - ((m_cgram[FIXED_COLOUR] & 0x3e0) >> 5);
1411            b = ((*colour & 0x7c00) >> 10) - ((m_cgram[FIXED_COLOUR] & 0x7c00) >> 10);
1412            if (r > 0x1f) r = 0;
1413            if (g > 0x1f) g = 0;
1414            if (b > 0x1f) b = 0;
1415         }
1416         /* halve if necessary */
1417         if (BIT(m_color_modes, 6))
1418         {
1419            r >>= 1;
1420            g >>= 1;
1421            b >>= 1;
1422         }
1423      }
1424
1425      /* according to anomie's docs, after addition has been performed, division by 2 happens *before* clipping to max, hence we clip now */
1426      if (clip_max)
1427      {
1428         if (r > 0x1f) r = 0x1f;
1429         if (g > 0x1f) g = 0x1f;
1430         if (b > 0x1f) b = 0x1f;
1431      }
1432
1433      *colour = ((r & 0x1f) | ((g & 0x1f) << 5) | ((b & 0x1f) << 10));
1434   }
1435}
1436
1437/*********************************************
1438 * refresh_scanline()
1439 *
1440 * Redraw the current line.
1441 *********************************************/
1442/*********************************************
1443 * Notice that in hires and pseudo hires modes,
1444 * i.e. when 512 different pixels are present
1445 * in a scanline, a crt TV monitor would end
1446 * up blending adjacent pixels. To mimic this,
1447 * we add a small (optional) hack which enters
1448 * only in the very last stage of the scanline
1449 * drawing and which simulates the TV by
1450 * replacing the exact pixel color with an
1451 * average of the current and next pixel colors.
1452 * Credits (and thanks) to Blargg and Byuu for
1453 * the optimized averaging algorithm.
1454 *********************************************/
1455
1456void snes_ppu_class::refresh_scanline( running_machine &machine, bitmap_rgb32 &bitmap, UINT16 curline )
1457{
1458   UINT16 ii;
1459   int x;
1460   int fade;
1461   struct SNES_SCANLINE *scanline1, *scanline2;
1462   UINT16 c;
1463   UINT16 prev_colour = 0;
1464   int blurring = machine.root_device().ioport("OPTIONS")->read_safe(0) & 0x01;
1465
1466   g_profiler.start(PROFILER_VIDEO);
1467
1468   if (m_screen_disabled) /* screen is forced blank */
1469      for (x = 0; x < SNES_SCR_WIDTH * 2; x++)
1470         bitmap.pix32(curline, x) = rgb_t::black;
1471   else
1472   {
1473      /* Update clip window masks if necessary */
1474      if (m_update_windows)
1475         update_windowmasks();
1476      /* Update the offsets if necessary */
1477      if (m_update_offsets)
1478         update_offsets();
1479
1480      /* Clear priority */
1481      memset(m_scanlines[SNES_MAINSCREEN].priority, 0, SNES_SCR_WIDTH);
1482      memset(m_scanlines[SNES_SUBSCREEN].priority, 0, SNES_SCR_WIDTH);
1483
1484      /* Clear layers */
1485      memset(m_scanlines[SNES_MAINSCREEN].layer, SNES_COLOR, SNES_SCR_WIDTH);
1486      memset(m_scanlines[SNES_SUBSCREEN].layer, SNES_COLOR, SNES_SCR_WIDTH);
1487
1488      /* Clear blend_exception (only used for OAM) */
1489      memset(m_scanlines[SNES_MAINSCREEN].blend_exception, 0, SNES_SCR_WIDTH);
1490      memset(m_scanlines[SNES_SUBSCREEN].blend_exception, 0, SNES_SCR_WIDTH);
1491
1492      /* Draw back colour */
1493      for (ii = 0; ii < SNES_SCR_WIDTH; ii++)
1494      {
1495         if (m_mode == 5 || m_mode == 6 || m_pseudo_hires)
1496            m_scanlines[SNES_SUBSCREEN].buffer[ii] = m_cgram[0];
1497         else
1498            m_scanlines[SNES_SUBSCREEN].buffer[ii] = m_cgram[FIXED_COLOUR];
1499
1500         m_scanlines[SNES_MAINSCREEN].buffer[ii] = m_cgram[0];
1501      }
1502
1503      /* Prepare OAM for this scanline */
1504      update_objects_rto(curline);
1505
1506      /* Draw scanline */
1507      draw_screens(curline);
1508
1509      update_obsel();
1510
1511#if SNES_LAYER_DEBUG
1512      if (dbg_video(machine, curline))
1513      {
1514         g_profiler.stop();
1515         return;
1516      }
1517
1518      /* Toggle drawing of SNES_SUBSCREEN or SNES_MAINSCREEN */
1519      if (m_debug_options.draw_subscreen)
1520      {
1521         scanline1 = &m_scanlines[SNES_SUBSCREEN];
1522         scanline2 = &m_scanlines[SNES_MAINSCREEN];
1523      }
1524      else
1525#endif /* SNES_LAYER_DEBUG */
1526      {
1527         scanline1 = &m_scanlines[SNES_MAINSCREEN];
1528         scanline2 = &m_scanlines[SNES_SUBSCREEN];
1529      }
1530
1531      /* Draw the scanline to screen */
1532
1533      fade = m_screen_brightness;
1534
1535      for (x = 0; x < SNES_SCR_WIDTH; x++)
1536      {
1537         int r, g, b, hires;
1538         UINT16 tmp_col[2];
1539         hires = (m_mode != 5 && m_mode != 6 && !m_pseudo_hires) ? 0 : 1;
1540
1541         /* in hires, the first pixel (of 512) is subscreen pixel, then the first mainscreen pixel follows, and so on... */
1542         if (!hires)
1543         {
1544            c = scanline1->buffer[x];
1545
1546            /* perform color math if the layer wants it (except if it's an object > 192) */
1547            if (!scanline1->blend_exception[x] && m_layer[scanline1->layer[x]].color_math)
1548               draw_blend(x, &c, m_prevent_color_math, m_clip_to_black, 0);
1549
1550            r = ((c & 0x1f) * fade) >> 4;
1551            g = (((c & 0x3e0) >> 5) * fade) >> 4;
1552            b = (((c & 0x7c00) >> 10) * fade) >> 4;
1553
1554            bitmap.pix32(curline, x * 2 + 0) = rgb_t(pal5bit(r), pal5bit(g), pal5bit(b));
1555            bitmap.pix32(curline, x * 2 + 1) = rgb_t(pal5bit(r), pal5bit(g), pal5bit(b));
1556         }
1557         else
1558         {
1559            /* prepare the pixel from main screen */
1560            c = scanline1->buffer[x];
1561
1562            /* perform color math if the layer wants it (except if it's an object > 192) */
1563            if (!scanline1->blend_exception[x] && m_layer[scanline1->layer[x]].color_math)
1564               draw_blend(x, &c, m_prevent_color_math, m_clip_to_black, 0);
1565
1566            tmp_col[1] = c;
1567
1568            /* prepare the pixel from sub screen */
1569            c = scanline2->buffer[x];
1570
1571            /* in hires/pseudo-hires, subscreen pixels are blended as well: for each subscreen pixel, color math
1572            is applied if it had been applied to the previous mainscreen pixel. What happens at subscreen pixel 0
1573            (which has no previous mainscreen pixel) is undocumented. Until more info are discovered, we (arbitrarily)
1574            apply to it the same color math as the *next* mainscreen pixel (i.e. mainscreen pixel 0), which seems as good as
1575            any other choice */
1576            if (x == 0 && !scanline1->blend_exception[0] && m_layer[scanline1->layer[0]].color_math)
1577               draw_blend(0, &c, m_prevent_color_math, m_clip_to_black, 1);
1578            else if (x > 0  && !scanline1->blend_exception[x - 1] && m_layer[scanline1->layer[x - 1]].color_math)
1579               draw_blend(x, &c, m_prevent_color_math, m_clip_to_black, 1);
1580
1581            tmp_col[0] = c;
1582
1583            /* average the first pixel if required, or draw it directly*/
1584            if (blurring)
1585               c = (prev_colour + tmp_col[0] - ((prev_colour ^ tmp_col[0]) & 0x0421)) >> 1;    // Hack code to mimic TV pixel blurring
1586            else
1587               c = tmp_col[0];
1588
1589            r = ((c & 0x1f) * fade) >> 4;
1590            g = (((c & 0x3e0) >> 5) * fade) >> 4;
1591            b = (((c & 0x7c00) >> 10) * fade) >> 4;
1592
1593            bitmap.pix32(curline, x * 2 + 0) = rgb_t(pal5bit(r), pal5bit(g), pal5bit(b));
1594            prev_colour = tmp_col[0];
1595
1596            /* average the second pixel if required, or draw it directly*/
1597            if (blurring)
1598               c = (prev_colour + tmp_col[1] - ((prev_colour ^ tmp_col[1]) & 0x0421)) >> 1;    // Hack code to mimic TV pixel blurring
1599            else
1600               c = tmp_col[1];
1601
1602            r = ((c & 0x1f) * fade) >> 4;
1603            g = (((c & 0x3e0) >> 5) * fade) >> 4;
1604            b = (((c & 0x7c00) >> 10) * fade) >> 4;
1605
1606            bitmap.pix32(curline, x * 2 + 1) = rgb_t(pal5bit(r), pal5bit(g), pal5bit(b));
1607            prev_colour = tmp_col[1];
1608         }
1609      }
1610   }
1611
1612   g_profiler.stop();
1613}
1614
1615void snes_ppu_class::ppu_start(screen_device &screen,snes_state *state)
1616{
1617   m_screen = &screen;
1618   running_machine &machine = screen.machine();
1619   m_state = state;
1620#if SNES_LAYER_DEBUG
1621   memset(&m_debug_options, 0, sizeof(m_debug_options));
1622#endif
1623
1624   m_vram = auto_alloc_array(machine, UINT8, SNES_VRAM_SIZE);
1625   m_cgram = auto_alloc_array(machine, UINT16, SNES_CGRAM_SIZE/2);
1626   m_oam_ram = auto_alloc_array(machine, UINT16, SNES_OAM_SIZE/2);
1627
1628   /* Inititialize registers/variables */
1629   m_update_windows = 1;
1630   m_beam.latch_vert = 0;
1631   m_beam.latch_horz = 0;
1632   m_beam.current_vert = 0;
1633   m_beam.current_horz = 0;
1634   m_beam.last_visible_line = 225; /* TODO: PAL setting */
1635   m_mode = 0;
1636   m_ppu1_version = 1;  // 5C77 chip version number, read by STAT77, only '1' is known
1637   m_ppu2_version = 3;  // 5C78 chip version number, read by STAT78, only '2' & '3' encountered so far.
1638
1639   m_cgram_address = 0;
1640   m_read_ophct = 0;
1641   m_read_opvct = 0;
1642
1643   PPU_REG(VMAIN) = 0x80;
1644   // what about other regs?
1645
1646   /* Inititialize mosaic table */
1647   for (int j = 0; j < 16; j++)
1648   {
1649      for (int i = 0; i < 4096; i++)
1650         m_mosaic_table[j][i] = (i / (j + 1)) * (j + 1);
1651   }
1652
1653   /* Init VRAM */
1654   memset(m_vram, 0, SNES_VRAM_SIZE);
1655
1656   /* Init Palette RAM */
1657   memset((UINT8 *)m_cgram, 0, SNES_CGRAM_SIZE);
1658
1659   /* Init oam RAM */
1660   memset((UINT8 *)m_oam_ram, 0xff, SNES_OAM_SIZE);
1661
1662
1663   for (int i = 0; i < 2; i++)
1664   {
1665      state_save_register_item(machine, "snes_ppu", NULL, i, m_scanlines[i].enable);
1666      state_save_register_item(machine, "snes_ppu", NULL, i, m_scanlines[i].clip);
1667      state_save_register_item(machine, "snes_ppu", NULL, i, m_scanlines[i].buffer);
1668      state_save_register_item(machine, "snes_ppu", NULL, i, m_scanlines[i].priority);
1669      state_save_register_item(machine, "snes_ppu", NULL, i, m_scanlines[i].layer);
1670      state_save_register_item(machine, "snes_ppu", NULL, i, m_scanlines[i].blend_exception);
1671   }
1672
1673   for (int i = 0; i < 6; i++)
1674   {
1675      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].window1_enabled);
1676      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].window1_invert);
1677      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].window2_enabled);
1678      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].window2_invert);
1679      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].wlog_mask);
1680      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].color_math);
1681      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].charmap);
1682      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].tilemap);
1683      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].tilemap_size);
1684      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].tile_size);
1685      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].mosaic_enabled);
1686      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].main_window_enabled);
1687      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].sub_window_enabled);
1688      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].main_bg_enabled);
1689      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].sub_bg_enabled);
1690      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].hoffs);
1691      state_save_register_item(machine, "snes_ppu", NULL, i, m_layer[i].voffs);
1692
1693      state_save_register_item_array(machine, "snes_ppu", NULL, i, m_clipmasks[i]);
1694   }
1695
1696   machine.save().save_item(NAME(m_oam.address_low));
1697   machine.save().save_item(NAME(m_oam.address_high));
1698   machine.save().save_item(NAME(m_oam.saved_address_low));
1699   machine.save().save_item(NAME(m_oam.saved_address_high));
1700   machine.save().save_item(NAME(m_oam.address));
1701   machine.save().save_item(NAME(m_oam.priority_rotation));
1702   machine.save().save_item(NAME(m_oam.next_charmap));
1703   machine.save().save_item(NAME(m_oam.next_size));
1704   machine.save().save_item(NAME(m_oam.size));
1705   machine.save().save_item(NAME(m_oam.next_name_select));
1706   machine.save().save_item(NAME(m_oam.name_select));
1707   machine.save().save_item(NAME(m_oam.first_sprite));
1708   machine.save().save_item(NAME(m_oam.flip));
1709   machine.save().save_item(NAME(m_oam.write_latch));
1710
1711   machine.save().save_item(NAME(m_beam.latch_horz));
1712   machine.save().save_item(NAME(m_beam.latch_vert));
1713   machine.save().save_item(NAME(m_beam.current_horz));
1714   machine.save().save_item(NAME(m_beam.current_vert));
1715   machine.save().save_item(NAME(m_beam.last_visible_line));
1716   machine.save().save_item(NAME(m_beam.interlace_count));
1717
1718   machine.save().save_item(NAME(m_mode7.repeat));
1719   machine.save().save_item(NAME(m_mode7.hflip));
1720   machine.save().save_item(NAME(m_mode7.vflip));
1721   machine.save().save_item(NAME(m_mode7.matrix_a));
1722   machine.save().save_item(NAME(m_mode7.matrix_b));
1723   machine.save().save_item(NAME(m_mode7.matrix_c));
1724   machine.save().save_item(NAME(m_mode7.matrix_d));
1725   machine.save().save_item(NAME(m_mode7.origin_x));
1726   machine.save().save_item(NAME(m_mode7.origin_y));
1727   machine.save().save_item(NAME(m_mode7.hor_offset));
1728   machine.save().save_item(NAME(m_mode7.ver_offset));
1729   machine.save().save_item(NAME(m_mode7.extbg));
1730
1731   machine.save().save_item(NAME(m_mosaic_size));
1732   machine.save().save_item(NAME(m_clip_to_black));
1733   machine.save().save_item(NAME(m_prevent_color_math));
1734   machine.save().save_item(NAME(m_sub_add_mode));
1735   machine.save().save_item(NAME(m_bg3_priority_bit));
1736   machine.save().save_item(NAME(m_direct_color));
1737   machine.save().save_item(NAME(m_ppu_last_scroll));
1738   machine.save().save_item(NAME(m_mode7_last_scroll));
1739
1740   machine.save().save_item(NAME(m_ppu1_open_bus));
1741   machine.save().save_item(NAME(m_ppu2_open_bus));
1742   machine.save().save_item(NAME(m_ppu1_version));
1743   machine.save().save_item(NAME(m_ppu2_version));
1744   machine.save().save_item(NAME(m_window1_left));
1745   machine.save().save_item(NAME(m_window1_right));
1746   machine.save().save_item(NAME(m_window2_left));
1747   machine.save().save_item(NAME(m_window2_right));
1748
1749   machine.save().save_item(NAME(m_update_windows));
1750   machine.save().save_item(NAME(m_update_offsets));
1751   machine.save().save_item(NAME(m_update_oam_list));
1752   machine.save().save_item(NAME(m_mode));
1753   machine.save().save_item(NAME(m_interlace));
1754   machine.save().save_item(NAME(m_obj_interlace));
1755   machine.save().save_item(NAME(m_screen_brightness));
1756   machine.save().save_item(NAME(m_screen_disabled));
1757   machine.save().save_item(NAME(m_pseudo_hires));
1758   machine.save().save_item(NAME(m_color_modes));
1759   machine.save().save_item(NAME(m_stat77));
1760   machine.save().save_item(NAME(m_stat78));
1761
1762   machine.save().save_item(NAME(m_htmult));
1763   machine.save().save_item(NAME(m_cgram_address));
1764   machine.save().save_item(NAME(m_read_ophct));
1765   machine.save().save_item(NAME(m_read_opvct));
1766   machine.save().save_item(NAME(m_vram_fgr_high));
1767   machine.save().save_item(NAME(m_vram_fgr_increment));
1768   machine.save().save_item(NAME(m_vram_fgr_count));
1769   machine.save().save_item(NAME(m_vram_fgr_mask));
1770   machine.save().save_item(NAME(m_vram_fgr_shift));
1771   machine.save().save_item(NAME(m_vram_read_buffer));
1772   machine.save().save_item(NAME(m_vmadd));
1773
1774   machine.save().save_item(NAME(m_regs));
1775
1776   machine.save().save_pointer(NAME(m_vram), SNES_VRAM_SIZE);
1777   machine.save().save_pointer(NAME(m_cgram), SNES_CGRAM_SIZE/2);
1778   machine.save().save_pointer(NAME(m_oam_ram), SNES_OAM_SIZE/2);
1779}
1780
1781
1782/* CPU <-> PPU comms */
1783
1784// full graphic variables
1785static const UINT16 vram_fgr_inctab[4] = { 1, 32, 128, 128 };
1786static const UINT16 vram_fgr_inccnts[4] = { 0, 32, 64, 128 };
1787static const UINT16 vram_fgr_shiftab[4] = { 0, 5, 6, 7 };
1788
1789// utility function - latches the H/V counters.  Used by IRQ, writes to WRIO, etc.
1790void snes_ppu_class::latch_counters( running_machine &machine )
1791{
1792   m_beam.current_horz = machine.first_screen()->hpos() / m_htmult;
1793   m_beam.latch_vert = machine.first_screen()->vpos();
1794   m_beam.latch_horz = m_beam.current_horz;
1795   m_stat78 |= 0x40;   // indicate we latched
1796//  m_read_ophct = m_read_opvct = 0;    // clear read flags - 2009-08: I think we must clear these when STAT78 is read...
1797
1798//  printf("latched @ H %d V %d\n", m_beam.latch_horz, m_beam.latch_vert);
1799}
1800
1801void snes_ppu_class::dynamic_res_change( running_machine &machine )
1802{
1803   rectangle visarea = machine.first_screen()->visible_area();
1804   attoseconds_t refresh;
1805
1806   visarea.min_x = visarea.min_y = 0;
1807   visarea.max_y = m_beam.last_visible_line * m_interlace - 1;
1808   visarea.max_x = (SNES_SCR_WIDTH * 2) - 1;
1809
1810   // fixme: should compensate for SNES_DBG_VIDEO
1811   if (m_mode == 5 || m_mode == 6 || m_pseudo_hires)
1812      m_htmult = 2;
1813   else
1814      m_htmult = 1;
1815
1816   /* FIXME: does the timing changes when the gfx mode is equal to 5 or 6? */
1817   if ((m_stat78 & 0x10) == SNES_NTSC)
1818   {
1819      refresh = HZ_TO_ATTOSECONDS(DOTCLK_NTSC) * SNES_HTOTAL * SNES_VTOTAL_NTSC;
1820      machine.first_screen()->configure(SNES_HTOTAL * 2, SNES_VTOTAL_NTSC * m_interlace, visarea, refresh);
1821   }
1822   else
1823   {
1824      refresh = HZ_TO_ATTOSECONDS(DOTCLK_PAL) * SNES_HTOTAL * SNES_VTOTAL_PAL;
1825      machine.first_screen()->configure(SNES_HTOTAL * 2, SNES_VTOTAL_PAL * m_interlace, visarea, refresh);
1826   }
1827}
1828
1829/*************************************************
1830
1831 SNES VRAM accesses:
1832
1833 VRAM accesses during active display are invalid.
1834 Unlike OAM and CGRAM, they will not be written
1835 anywhere at all. Thanks to byuu's researches,
1836 the ranges where writes are invalid have been
1837 validated on hardware, as has the edge case where
1838 the S-CPU open bus can be written if the write
1839 occurs during the very last clock cycle of
1840 vblank.
1841 Our implementation could be not 100% accurate
1842 when interlace is active.
1843*************************************************/
1844
1845inline UINT32 snes_ppu_class::get_vram_address( running_machine &machine )
1846{
1847   UINT32 addr = m_vmadd;
1848
1849   if (m_vram_fgr_count)
1850   {
1851      UINT32 rem = addr & m_vram_fgr_mask;
1852      UINT32 faddr = (addr & ~m_vram_fgr_mask) + (rem >> m_vram_fgr_shift) + ((rem & (m_vram_fgr_count - 1)) << 3);
1853      return faddr << 1;
1854   }
1855
1856   return addr << 1;
1857}
1858
1859READ8_MEMBER( snes_ppu_class::vram_read )
1860{
1861   UINT8 res = 0;
1862   offset &= 0xffff; // only 64KB are present on SNES
1863
1864   if (m_screen_disabled)
1865      res = m_vram[offset];
1866   else
1867   {
1868      UINT16 v = m_screen->vpos();
1869      UINT16 h = m_screen->hpos();
1870      UINT16 ls = (((m_stat78 & 0x10) == SNES_NTSC ? 525 : 625) >> 1) - 1;
1871
1872      if (m_interlace == 2)
1873         ls++;
1874
1875      if (v == ls && h == 1362)
1876         res = 0;
1877      else if (v < m_beam.last_visible_line - 1)
1878         res = 0;
1879      else if (v == m_beam.last_visible_line - 1)
1880      {
1881         if (h == 1362)
1882            res = m_vram[offset];
1883         else
1884         {
1885            //printf("%d %d VRAM read, CHECK!\n",h,v);
1886            res = 0;
1887         }
1888      }
1889      else
1890         res = m_vram[offset];
1891   }
1892   return res;
1893}
1894
1895WRITE8_MEMBER( snes_ppu_class::vram_write )
1896{
1897   offset &= 0xffff; // only 64KB are present on SNES, Robocop 3 relies on this
1898
1899   if (m_screen_disabled)
1900      m_vram[offset] = data;
1901   else
1902   {
1903      UINT16 v = m_screen->vpos();
1904      UINT16 h = m_screen->hpos();
1905      if (v == 0)
1906      {
1907         if (h <= 4)
1908            m_vram[offset] = data;
1909         else if (h == 6)
1910            m_vram[offset] = m_state->snes_open_bus_r(space, 0);
1911         else
1912         {
1913            //printf("%d %d VRAM write, CHECK!\n",h,v);
1914            //no write
1915         }
1916      }
1917      else if (v < m_beam.last_visible_line)
1918      {
1919         //printf("%d %d VRAM write, CHECK!\n",h,v);
1920         //no write
1921      }
1922      else if (v == m_beam.last_visible_line)
1923      {
1924         if (h <= 4)
1925         {
1926            //printf("%d %d VRAM write, CHECK!\n",h,v);
1927            //no write
1928         }
1929         else
1930            m_vram[offset] = data;
1931      }
1932      else
1933         m_vram[offset] = data;
1934   }
1935}
1936
1937/*************************************************
1938
1939 SNES OAM accesses:
1940
1941 OAM accesses during active display are allowed.
1942 The actual address varies during rendering, as the
1943 PPU reads in data itself for processing.
1944 Unfortunately, no one has been able (yet) to
1945 determine how this works. The only known game to
1946 actually access OAM during active display is
1947 Uniracers and it expects accesses to map to
1948 offset 0x0218. Hence, following byuu's choice
1949 we rerouted OAM accesses during active display
1950 to 0x0218 (0x010c in our snes_oam).
1951 This is a hack, but it is more accurate than
1952 writing to the 'expected' address set by
1953 $2102,$2103.
1954
1955 Notice that, since PPU_REG(OAMDATA) is never
1956 read/written directly, we use it as an index
1957 to choose the high/low byte of the snes_oam word.
1958*************************************************/
1959
1960READ8_MEMBER( snes_ppu_class::oam_read )
1961{
1962   offset &= 0x1ff;
1963
1964   if (offset & 0x100)
1965      offset &= 0x10f;
1966
1967   if (!m_screen_disabled)
1968   {
1969      UINT16 v = m_screen->vpos();
1970
1971      if (v < m_beam.last_visible_line)
1972         offset = 0x010c;
1973   }
1974
1975   return (m_oam_ram[offset] >> (PPU_REG(OAMDATA) << 3)) & 0xff;
1976}
1977
1978WRITE8_MEMBER( snes_ppu_class::oam_write )
1979{
1980   offset &= 0x1ff;
1981
1982   if (offset & 0x100)
1983      offset &= 0x10f;
1984
1985   if (!m_screen_disabled)
1986   {
1987      UINT16 v = m_screen->vpos();
1988
1989      if (v < m_beam.last_visible_line)
1990         offset = 0x010c;
1991   }
1992
1993   if (!(PPU_REG(OAMDATA)))
1994      m_oam_ram[offset] = (m_oam_ram[offset] & 0xff00) | (data << 0);
1995   else
1996      m_oam_ram[offset] = (m_oam_ram[offset] & 0x00ff) | (data << 8);
1997}
1998
1999/*************************************************
2000
2001 SNES CGRAM accesses:
2002
2003 CGRAM writes during hblank are valid. During
2004 active display, the actual address the data
2005 is written to varies, as the PPU itself changes
2006 the address. Like OAM, it is not known the exact
2007 algorithm used, but no commercial software seems
2008 to attempt this. While byuu, in his emu, maps
2009 those accesses to 0x01ff, because it is more
2010 accurate to invalidate the 'expected' address
2011 than not, MESS has issues if we don't write to
2012 the expected address (see e.g. Tokimeki Memorial).
2013 This is because writes should work during hblank
2014 (so that the game can produce color fading), but
2015 ends up not working with the conditions below.
2016 Hence, for the moment, we only document the
2017 solution adopted by BSNES without enabling it.
2018*************************************************/
2019
2020READ8_MEMBER( snes_ppu_class::cgram_read )
2021{
2022   UINT8 res = 0;
2023   offset &= 0x1ff;
2024
2025#if 0
2026   if (!m_screen_disabled)
2027   {
2028      UINT16 v = m_screen->vpos();
2029      UINT16 h = m_screen->hpos();
2030
2031      if (v < m_beam.last_visible_line && h >= 128 && h < 1096)
2032         offset = 0x1ff;
2033   }
2034#endif
2035
2036   res = ((UINT8 *)m_cgram)[offset];
2037
2038   // CGRAM palette data format is 15-bits (0,bbbbb,ggggg,rrrrr).
2039   // Highest bit is simply ignored.
2040   if (offset & 0x01)
2041      res &= 0x7f;
2042
2043   return res;
2044}
2045
2046WRITE8_MEMBER( snes_ppu_class::cgram_write )
2047{
2048   offset &= 0x1ff;
2049
2050#if 0
2051   // FIXME: this currently breaks some games (e.g. Tokimeki Memorial),
2052   // even if it's expected to be more accurate than allowing for
2053   // writes to the cgram address
2054   if (!m_screen_disabled)
2055   {
2056      UINT16 v = m_screen->vpos();
2057      UINT16 h = m_screen->hpos();
2058
2059      if (v < m_beam.last_visible_line && h >= 128 && h < 1096)
2060         offset = 0x1ff;
2061   }
2062#endif
2063
2064   // CGRAM palette data format is 15-bits (0,bbbbb,ggggg,rrrrr).
2065   // Highest bit is simply ignored.
2066   if (offset & 0x01)
2067      data &= 0x7f;
2068
2069   ((UINT8 *)m_cgram)[offset] = data;
2070}
2071
2072UINT8 snes_ppu_class::read(address_space &space, UINT32 offset, UINT8 wrio_bit7)
2073{
2074   UINT8 value;
2075
2076   switch (offset)
2077   {
2078      case OAMDATA:   /* 21xy for x=0,1,2 and y=4,5,6,8,9,a returns PPU1 open bus*/
2079      case BGMODE:
2080      case MOSAIC:
2081      case BG2SC:
2082      case BG3SC:
2083      case BG4SC:
2084      case BG4VOFS:
2085      case VMAIN:
2086      case VMADDL:
2087      case VMDATAL:
2088      case VMDATAH:
2089      case M7SEL:
2090      case W34SEL:
2091      case WOBJSEL:
2092      case WH0:
2093      case WH2:
2094      case WH3:
2095      case WBGLOG:
2096         return m_ppu1_open_bus;
2097
2098      case MPYL:      /* Multiplication result (low) */
2099         {
2100            /* Perform 16bit * 8bit multiply */
2101            UINT32 c = (INT16)m_mode7.matrix_a * (INT8)(m_mode7.matrix_b >> 8);
2102            m_ppu1_open_bus = c & 0xff;
2103            return m_ppu1_open_bus;
2104         }
2105      case MPYM:      /* Multiplication result (mid) */
2106         {
2107            /* Perform 16bit * 8bit multiply */
2108            UINT32 c = (INT16)m_mode7.matrix_a * (INT8)(m_mode7.matrix_b >> 8);
2109            m_ppu1_open_bus = (c >> 8) & 0xff;
2110            return m_ppu1_open_bus;
2111         }
2112      case MPYH:      /* Multiplication result (high) */
2113         {
2114            /* Perform 16bit * 8bit multiply */
2115            UINT32 c = (INT16)m_mode7.matrix_a * (INT8)(m_mode7.matrix_b >> 8);
2116            m_ppu1_open_bus = (c >> 16) & 0xff;
2117            return m_ppu1_open_bus;
2118         }
2119      case SLHV:      /* Software latch for H/V counter */
2120         latch_counters(space.machine());
2121         return m_state->snes_open_bus_r(space, 0);       /* Return value is meaningless */
2122      case ROAMDATA:  /* Read data from OAM (DR) */
2123         m_ppu1_open_bus = oam_read(space, m_oam.address);
2124         PPU_REG(OAMDATA) = (PPU_REG(OAMDATA) + 1) % 2;
2125         if (!PPU_REG(OAMDATA))
2126         {
2127            m_oam.address++;
2128            m_oam.address &= 0x1ff;
2129            m_oam.first_sprite = m_oam.priority_rotation ? (m_oam.address >> 1) & 127 : 0;
2130         }
2131         return m_ppu1_open_bus;
2132      case RVMDATAL:  /* Read data from VRAM (low) */
2133         {
2134            UINT32 addr = get_vram_address(space.machine());
2135            m_ppu1_open_bus = m_vram_read_buffer & 0xff;
2136
2137            if (!m_vram_fgr_high)
2138            {
2139               m_vram_read_buffer = vram_read(space, addr);
2140               m_vram_read_buffer |= (vram_read(space, addr + 1) << 8);
2141
2142               m_vmadd = (m_vmadd + m_vram_fgr_increment) & 0xffff;
2143            }
2144
2145            return m_ppu1_open_bus;
2146         }
2147      case RVMDATAH:  /* Read data from VRAM (high) */
2148         {
2149            UINT32 addr = get_vram_address(space.machine());
2150            m_ppu1_open_bus = (m_vram_read_buffer >> 8) & 0xff;
2151
2152            if (m_vram_fgr_high)
2153            {
2154               m_vram_read_buffer = vram_read(space, addr);
2155               m_vram_read_buffer |= (vram_read(space, addr + 1) << 8);
2156
2157               m_vmadd = (m_vmadd + m_vram_fgr_increment) & 0xffff;
2158            }
2159
2160            return m_ppu1_open_bus;
2161         }
2162      case RCGDATA:   /* Read data from CGRAM */
2163         if (!(m_cgram_address & 0x01))
2164            m_ppu2_open_bus = cgram_read(space, m_cgram_address);
2165         else
2166         {
2167            m_ppu2_open_bus &= 0x80;
2168            m_ppu2_open_bus |= cgram_read(space, m_cgram_address) & 0x7f;
2169         }
2170
2171         m_cgram_address = (m_cgram_address + 1) % (SNES_CGRAM_SIZE - 2);
2172         return m_ppu2_open_bus;
2173      case OPHCT:     /* Horizontal counter data by ext/soft latch */
2174         if (m_read_ophct)
2175         {
2176            m_ppu2_open_bus &= 0xfe;
2177            m_ppu2_open_bus |= (m_beam.latch_horz >> 8) & 0x01;
2178         }
2179         else
2180         {
2181            m_ppu2_open_bus = m_beam.latch_horz & 0xff;
2182         }
2183         m_read_ophct ^= 1;
2184         return m_ppu2_open_bus;
2185      case OPVCT:     /* Vertical counter data by ext/soft latch */
2186         if (m_read_opvct)
2187         {
2188            m_ppu2_open_bus &= 0xfe;
2189            m_ppu2_open_bus |= (m_beam.latch_vert >> 8) & 0x01;
2190         }
2191         else
2192         {
2193            m_ppu2_open_bus = m_beam.latch_vert & 0xff;
2194         }
2195         m_read_opvct ^= 1;
2196         return m_ppu2_open_bus;
2197      case STAT77:    /* PPU status flag and version number */
2198         value = m_stat77 & 0xc0; // 0x80 & 0x40 are Time Over / Range Over Sprite flags, set by the video code
2199         // 0x20 - Master/slave mode select. Little is known about this bit. We always seem to read back 0 here.
2200         value |= (m_ppu1_open_bus & 0x10);
2201         value |= (m_ppu1_version & 0x0f);
2202         m_stat77 = value;  // not sure if this is needed...
2203         m_ppu1_open_bus = value;
2204         return m_ppu1_open_bus;
2205      case STAT78:    /* PPU status flag and version number */
2206         m_read_ophct = 0;
2207         m_read_opvct = 0;
2208         if (wrio_bit7)
2209            m_stat78 &= ~0x40; //clear ext latch if bit 7 of WRIO is set
2210         m_stat78 = (m_stat78 & ~0x2f) | (m_ppu2_open_bus & 0x20) | (m_ppu2_version & 0x0f);
2211         m_ppu2_open_bus = m_stat78;
2212         return m_ppu2_open_bus;
2213   }
2214
2215   /* note: remaining registers (Namely TM in Super Kick Boxing) returns MDR open bus, not PPU Open Bus! */
2216   return m_state->snes_open_bus_r(space, 0);
2217}
2218
2219
2220void snes_ppu_class::write(address_space &space, UINT32 offset, UINT8 data)
2221{
2222   switch (offset)
2223   {
2224      case INIDISP:   /* Initial settings for screen */
2225         if ((m_screen_disabled & 0x80) && (!(data & 0x80))) //a 1->0 force blank transition causes a reset OAM address
2226         {
2227            space.write_byte(OAMADDL, m_oam.saved_address_low);
2228            space.write_byte(OAMADDH, m_oam.saved_address_high);
2229            m_oam.first_sprite = m_oam.priority_rotation ? (m_oam.address >> 1) & 127 : 0;
2230         }
2231         m_screen_disabled = data & 0x80;
2232         m_screen_brightness = (data & 0x0f) + 1;
2233         break;
2234      case OBSEL:     /* Object size and data area designation */
2235         m_oam.next_charmap = (data & 0x03) << 1;
2236         m_oam.next_name_select = (((data & 0x18) >> 3) * 0x1000) << 1;
2237         m_oam.next_size = (data & 0xe0) >> 5;
2238         break;
2239      case OAMADDL:   /* Address for accessing OAM (low) */
2240         m_oam.saved_address_low = data;
2241         m_oam.address = (m_oam.address & 0xff00) + data;
2242         m_oam.first_sprite = m_oam.priority_rotation ? (m_oam.address >> 1) & 127 : 0;
2243         PPU_REG(OAMDATA) = 0;
2244         break;
2245      case OAMADDH:   /* Address for accessing OAM (high) */
2246         m_oam.saved_address_high = data;
2247         m_oam.address = (m_oam.address & 0x00ff) | ((data & 0x01) << 8);
2248         m_oam.priority_rotation = BIT(data, 7);
2249         m_oam.first_sprite = m_oam.priority_rotation ? (m_oam.address >> 1) & 127 : 0;
2250         PPU_REG(OAMDATA) = 0;
2251         break;
2252      case OAMDATA:   /* Data for OAM write (DW) */
2253         if (m_oam.address >= 0x100)
2254            oam_write(space, m_oam.address, data);
2255         else
2256         {
2257            if (!PPU_REG(OAMDATA))
2258               m_oam.write_latch = data;
2259            else
2260            {
2261               // in this case, we not only write data to the upper byte of the word,
2262               // but also m_oam.write_latch to the lower byte (recall that
2263               // PPU_REG(OAMDATA) is used to select high/low byte)
2264               oam_write(space, m_oam.address, data);
2265               PPU_REG(OAMDATA) = 0;
2266               oam_write(space, m_oam.address, m_oam.write_latch);
2267               PPU_REG(OAMDATA) = 1;
2268            }
2269         }
2270         PPU_REG(OAMDATA) = (PPU_REG(OAMDATA) + 1) % 2;
2271         if (!PPU_REG(OAMDATA))
2272         {
2273            m_oam.address++;
2274            m_oam.address &= 0x1ff;
2275            m_oam.first_sprite = m_oam.priority_rotation ? (m_oam.address >> 1) & 127 : 0;
2276         }
2277         return;
2278      case BGMODE:    /* BG mode and character size settings */
2279         m_mode = data & 0x07;
2280         dynamic_res_change(space.machine());
2281         m_bg3_priority_bit = BIT(data, 3);
2282         m_layer[SNES_BG1].tile_size = BIT(data, 4);
2283         m_layer[SNES_BG2].tile_size = BIT(data, 5);
2284         m_layer[SNES_BG3].tile_size = BIT(data, 6);
2285         m_layer[SNES_BG4].tile_size = BIT(data, 7);
2286         m_update_offsets = 1;
2287         break;
2288      case MOSAIC:    /* Size and screen designation for mosaic */
2289         m_mosaic_size = (data & 0xf0) >> 4;
2290         m_layer[SNES_BG1].mosaic_enabled = BIT(data, 0);
2291         m_layer[SNES_BG2].mosaic_enabled = BIT(data, 1);
2292         m_layer[SNES_BG3].mosaic_enabled = BIT(data, 2);
2293         m_layer[SNES_BG4].mosaic_enabled = BIT(data, 3);
2294         break;
2295      case BG1SC:     /* Address for storing SC data BG1 SC size designation */
2296      case BG2SC:     /* Address for storing SC data BG2 SC size designation  */
2297      case BG3SC:     /* Address for storing SC data BG3 SC size designation  */
2298      case BG4SC:     /* Address for storing SC data BG4 SC size designation  */
2299         m_layer[offset - BG1SC].tilemap = data & 0xfc;
2300         m_layer[offset - BG1SC].tilemap_size = data & 0x3;
2301         break;
2302      case BG12NBA:   /* Address for BG 1 and 2 character data */
2303         m_layer[SNES_BG1].charmap = (data & 0x0f);
2304         m_layer[SNES_BG2].charmap = (data & 0xf0) >> 4;
2305         break;
2306      case BG34NBA:   /* Address for BG 3 and 4 character data */
2307         m_layer[SNES_BG3].charmap = (data & 0x0f);
2308         m_layer[SNES_BG4].charmap = (data & 0xf0) >> 4;
2309         break;
2310
2311      // Anomie says "H Current = (Byte<<8) | (Prev&~7) | ((Current>>8)&7); V Current = (Current<<8) | Prev;" and Prev is shared by all scrolls but in Mode 7!
2312      case BG1HOFS:   /* BG1 - horizontal scroll (DW) */
2313         /* In Mode 0->6 we use ppu_last_scroll as Prev */
2314         m_layer[SNES_BG1].hoffs = (data << 8) | (m_ppu_last_scroll & ~7) | ((m_layer[SNES_BG1].hoffs >> 8) & 7);
2315         m_ppu_last_scroll = data;
2316         /* In Mode 7 we use mode7_last_scroll as Prev */
2317         m_mode7.hor_offset = (data << 8) | (m_mode7_last_scroll & ~7) | ((m_mode7.hor_offset >> 8) & 7);
2318         m_mode7_last_scroll = data;
2319         m_update_offsets = 1;
2320         return;
2321      case BG1VOFS:   /* BG1 - vertical scroll (DW) */
2322         /* In Mode 0->6 we use ppu_last_scroll as Prev */
2323         m_layer[SNES_BG1].voffs = (data << 8) | m_ppu_last_scroll;
2324         m_ppu_last_scroll = data;
2325         /* In Mode 7 we use mode7_last_scroll as Prev */
2326         m_mode7.ver_offset = (data << 8) | m_mode7_last_scroll;
2327         m_mode7_last_scroll = data;
2328         m_update_offsets = 1;
2329         return;
2330      case BG2HOFS:   /* BG2 - horizontal scroll (DW) */
2331         m_layer[SNES_BG2].hoffs = (data << 8) | (m_ppu_last_scroll & ~7) | ((m_layer[SNES_BG2].hoffs >> 8) & 7);
2332         m_ppu_last_scroll = data;
2333         m_update_offsets = 1;
2334         return;
2335      case BG2VOFS:   /* BG2 - vertical scroll (DW) */
2336         m_layer[SNES_BG2].voffs = (data << 8) | (m_ppu_last_scroll);
2337         m_ppu_last_scroll = data;
2338         m_update_offsets = 1;
2339         return;
2340      case BG3HOFS:   /* BG3 - horizontal scroll (DW) */
2341         m_layer[SNES_BG3].hoffs = (data << 8) | (m_ppu_last_scroll & ~7) | ((m_layer[SNES_BG3].hoffs >> 8) & 7);
2342         m_ppu_last_scroll = data;
2343         m_update_offsets = 1;
2344         return;
2345      case BG3VOFS:   /* BG3 - vertical scroll (DW) */
2346         m_layer[SNES_BG3].voffs = (data << 8) | (m_ppu_last_scroll);
2347         m_ppu_last_scroll = data;
2348         m_update_offsets = 1;
2349         return;
2350      case BG4HOFS:   /* BG4 - horizontal scroll (DW) */
2351         m_layer[SNES_BG4].hoffs = (data << 8) | (m_ppu_last_scroll & ~7) | ((m_layer[SNES_BG4].hoffs >> 8) & 7);
2352         m_ppu_last_scroll = data;
2353         m_update_offsets = 1;
2354         return;
2355      case BG4VOFS:   /* BG4 - vertical scroll (DW) */
2356         m_layer[SNES_BG4].voffs = (data << 8) | (m_ppu_last_scroll);
2357         m_ppu_last_scroll = data;
2358         m_update_offsets = 1;
2359         return;
2360      case VMAIN:     /* VRAM address increment value designation */
2361         m_vram_fgr_high = (data & 0x80);
2362         m_vram_fgr_increment = vram_fgr_inctab[data & 3];
2363
2364         if (data & 0xc)
2365         {
2366            int md = (data & 0xc) >> 2;
2367
2368            m_vram_fgr_count = vram_fgr_inccnts[md];         // 0x20, 0x40, 0x80
2369            m_vram_fgr_mask = (m_vram_fgr_count * 8) - 1; // 0xff, 0x1ff, 0x2ff
2370            m_vram_fgr_shift = vram_fgr_shiftab[md];         // 5, 6, 7
2371         }
2372         else
2373         {
2374            m_vram_fgr_count = 0;
2375         }
2376//          printf("VMAIN: high %x inc %x count %x mask %x shift %x\n", m_vram_fgr_high, m_vram_fgr_increment, m_vram_fgr_count, m_vram_fgr_mask, m_vram_fgr_shift);
2377         break;
2378      case VMADDL:    /* Address for VRAM read/write (low) */
2379         {
2380            UINT32 addr;
2381            m_vmadd = (m_vmadd & 0xff00) | (data << 0);
2382            addr = get_vram_address(space.machine());
2383            m_vram_read_buffer = vram_read(space, addr);
2384            m_vram_read_buffer |= (vram_read(space, addr + 1) << 8);
2385         }
2386         break;
2387      case VMADDH:    /* Address for VRAM read/write (high) */
2388         {
2389            UINT32 addr;
2390            m_vmadd = (m_vmadd & 0x00ff) | (data << 8);
2391            addr = get_vram_address(space.machine());
2392            m_vram_read_buffer = vram_read(space, addr);
2393            m_vram_read_buffer |= (vram_read(space, addr + 1) << 8);
2394         }
2395         break;
2396      case VMDATAL:   /* 2118: Data for VRAM write (low) */
2397         {
2398            UINT32 addr = get_vram_address(space.machine());
2399            vram_write(space, addr, data);
2400
2401            if (!m_vram_fgr_high)
2402               m_vmadd = (m_vmadd + m_vram_fgr_increment) & 0xffff;
2403         }
2404         return;
2405      case VMDATAH:   /* 2119: Data for VRAM write (high) */
2406         {
2407            UINT32 addr = get_vram_address(space.machine());
2408            vram_write(space, addr + 1, data);
2409
2410            if (m_vram_fgr_high)
2411               m_vmadd = (m_vmadd + m_vram_fgr_increment) & 0xffff;
2412         }
2413         return;
2414      case M7SEL:     /* Mode 7 initial settings */
2415         m_mode7.repeat = (data >> 6) & 3;
2416         m_mode7.vflip  = BIT(data, 1);
2417         m_mode7.hflip  = BIT(data, 0);
2418         break;
2419      /* As per Anomie's doc: Reg = (Current<<8) | Prev; and there is only one Prev, shared by these matrix regs and Mode 7 scroll regs */
2420      case M7A:       /* Mode 7 COS angle/x expansion (DW) */
2421         m_mode7.matrix_a = m_mode7_last_scroll + (data << 8);
2422         m_mode7_last_scroll = data;
2423         break;
2424      case M7B:       /* Mode 7 SIN angle/ x expansion (DW) */
2425         m_mode7.matrix_b = m_mode7_last_scroll + (data << 8);
2426         m_mode7_last_scroll = data;
2427         break;
2428      case M7C:       /* Mode 7 SIN angle/y expansion (DW) */
2429         m_mode7.matrix_c = m_mode7_last_scroll + (data << 8);
2430         m_mode7_last_scroll = data;
2431         break;
2432      case M7D:       /* Mode 7 COS angle/y expansion (DW) */
2433         m_mode7.matrix_d = m_mode7_last_scroll + (data << 8);
2434         m_mode7_last_scroll = data;
2435         break;
2436      case M7X:       /* Mode 7 x center position (DW) */
2437         m_mode7.origin_x = m_mode7_last_scroll + (data << 8);
2438         m_mode7_last_scroll = data;
2439         break;
2440      case M7Y:       /* Mode 7 y center position (DW) */
2441         m_mode7.origin_y = m_mode7_last_scroll + (data << 8);
2442         m_mode7_last_scroll = data;
2443         break;
2444      case CGADD:     /* Initial address for colour RAM writing */
2445         /* CGRAM is 16-bit, but when reading/writing we treat it as 8-bit, so we need to double the address */
2446         m_cgram_address = data << 1;
2447         break;
2448      case CGDATA:    /* Data for colour RAM */
2449         cgram_write(space, m_cgram_address, data);
2450         m_cgram_address = (m_cgram_address + 1) % (SNES_CGRAM_SIZE - 2);
2451         break;
2452      case W12SEL:    /* Window mask settings for BG1-2 */
2453         if (data != PPU_REG(W12SEL))
2454         {
2455            m_layer[SNES_BG1].window1_invert  = BIT(data, 0);
2456            m_layer[SNES_BG1].window1_enabled = BIT(data, 1);
2457            m_layer[SNES_BG1].window2_invert  = BIT(data, 2);
2458            m_layer[SNES_BG1].window2_enabled = BIT(data, 3);
2459            m_layer[SNES_BG2].window1_invert  = BIT(data, 4);
2460            m_layer[SNES_BG2].window1_enabled = BIT(data, 5);
2461            m_layer[SNES_BG2].window2_invert  = BIT(data, 6);
2462            m_layer[SNES_BG2].window2_enabled = BIT(data, 7);
2463            m_update_windows = 1;
2464         }
2465         break;
2466      case W34SEL:    /* Window mask settings for BG3-4 */
2467         if (data != PPU_REG(W34SEL))
2468         {
2469            m_layer[SNES_BG3].window1_invert  = BIT(data, 0);
2470            m_layer[SNES_BG3].window1_enabled = BIT(data, 1);
2471            m_layer[SNES_BG3].window2_invert  = BIT(data, 2);
2472            m_layer[SNES_BG3].window2_enabled = BIT(data, 3);
2473            m_layer[SNES_BG4].window1_invert  = BIT(data, 4);
2474            m_layer[SNES_BG4].window1_enabled = BIT(data, 5);
2475            m_layer[SNES_BG4].window2_invert  = BIT(data, 6);
2476            m_layer[SNES_BG4].window2_enabled = BIT(data, 7);
2477            m_update_windows = 1;
2478         }
2479         break;
2480      case WOBJSEL:   /* Window mask settings for objects */
2481         if (data != PPU_REG(WOBJSEL))
2482         {
2483            m_layer[SNES_OAM].window1_invert  = BIT(data, 0);
2484            m_layer[SNES_OAM].window1_enabled = BIT(data, 1);
2485            m_layer[SNES_OAM].window2_invert  = BIT(data, 2);
2486            m_layer[SNES_OAM].window2_enabled = BIT(data, 3);
2487            m_layer[SNES_COLOR].window1_invert  = BIT(data, 4);
2488            m_layer[SNES_COLOR].window1_enabled = BIT(data, 5);
2489            m_layer[SNES_COLOR].window2_invert  = BIT(data, 6);
2490            m_layer[SNES_COLOR].window2_enabled = BIT(data, 7);
2491            m_update_windows = 1;
2492         }
2493         break;
2494      case WH0:       /* Window 1 left position */
2495         if (data != PPU_REG(WH0))
2496         {
2497            m_window1_left = data;
2498            m_update_windows = 1;
2499         }
2500         break;
2501      case WH1:       /* Window 1 right position */
2502         if (data != PPU_REG(WH1))
2503         {
2504            m_window1_right = data;
2505            m_update_windows = 1;
2506         }
2507         break;
2508      case WH2:       /* Window 2 left position */
2509         if (data != PPU_REG(WH2))
2510         {
2511            m_window2_left = data;
2512            m_update_windows = 1;
2513         }
2514         break;
2515      case WH3:       /* Window 2 right position */
2516         if (data != PPU_REG(WH3))
2517         {
2518            m_window2_right = data;
2519            m_update_windows = 1;
2520         }
2521         break;
2522      case WBGLOG:    /* Window mask logic for BG's */
2523         if (data != PPU_REG(WBGLOG))
2524         {
2525            m_layer[SNES_BG1].wlog_mask = data & 0x03;
2526            m_layer[SNES_BG2].wlog_mask = (data & 0x0c) >> 2;
2527            m_layer[SNES_BG3].wlog_mask = (data & 0x30) >> 4;
2528            m_layer[SNES_BG4].wlog_mask = (data & 0xc0) >> 6;
2529            m_update_windows = 1;
2530         }
2531         break;
2532      case WOBJLOG:   /* Window mask logic for objects */
2533         if (data != PPU_REG(WOBJLOG))
2534         {
2535            m_layer[SNES_OAM].wlog_mask = data & 0x03;
2536            m_layer[SNES_COLOR].wlog_mask = (data & 0x0c) >> 2;
2537            m_update_windows = 1;
2538         }
2539         break;
2540      case TM:        /* Main screen designation */
2541         m_layer[SNES_BG1].main_bg_enabled = BIT(data, 0);
2542         m_layer[SNES_BG2].main_bg_enabled = BIT(data, 1);
2543         m_layer[SNES_BG3].main_bg_enabled = BIT(data, 2);
2544         m_layer[SNES_BG4].main_bg_enabled = BIT(data, 3);
2545         m_layer[SNES_OAM].main_bg_enabled = BIT(data, 4);
2546         break;
2547      case TS:        /* Subscreen designation */
2548         m_layer[SNES_BG1].sub_bg_enabled = BIT(data, 0);
2549         m_layer[SNES_BG2].sub_bg_enabled = BIT(data, 1);
2550         m_layer[SNES_BG3].sub_bg_enabled = BIT(data, 2);
2551         m_layer[SNES_BG4].sub_bg_enabled = BIT(data, 3);
2552         m_layer[SNES_OAM].sub_bg_enabled = BIT(data, 4);
2553         break;
2554      case TMW:       /* Window mask for main screen designation */
2555         m_layer[SNES_BG1].main_window_enabled = BIT(data, 0);
2556         m_layer[SNES_BG2].main_window_enabled = BIT(data, 1);
2557         m_layer[SNES_BG3].main_window_enabled = BIT(data, 2);
2558         m_layer[SNES_BG4].main_window_enabled = BIT(data, 3);
2559         m_layer[SNES_OAM].main_window_enabled = BIT(data, 4);
2560         break;
2561      case TSW:       /* Window mask for subscreen designation */
2562         m_layer[SNES_BG1].sub_window_enabled = BIT(data, 0);
2563         m_layer[SNES_BG2].sub_window_enabled = BIT(data, 1);
2564         m_layer[SNES_BG3].sub_window_enabled = BIT(data, 2);
2565         m_layer[SNES_BG4].sub_window_enabled = BIT(data, 3);
2566         m_layer[SNES_OAM].sub_window_enabled = BIT(data, 4);
2567         break;
2568      case CGWSEL:    /* Initial settings for Fixed colour addition or screen addition */
2569         m_clip_to_black = (data >> 6) & 0x03;
2570         m_prevent_color_math = (data >> 4) & 0x03;
2571         m_sub_add_mode = BIT(data, 1);
2572         m_direct_color = BIT(data, 0);
2573#ifdef SNES_DBG_REG_W
2574         if ((data & 0x2) != (PPU_REG(CGWSEL) & 0x2))
2575            mame_printf_debug("Add/Sub Layer: %s\n", ((data & 0x2) >> 1) ? "Subscreen" : "Fixed colour");
2576#endif
2577         break;
2578      case CGADSUB:   /* Addition/Subtraction designation for each screen */
2579         m_color_modes = data & 0xc0;
2580         m_layer[SNES_BG1].color_math = BIT(data, 0);
2581         m_layer[SNES_BG2].color_math = BIT(data, 1);
2582         m_layer[SNES_BG3].color_math = BIT(data, 2);
2583         m_layer[SNES_BG4].color_math = BIT(data, 3);
2584         m_layer[SNES_OAM].color_math = BIT(data, 4);
2585         m_layer[SNES_COLOR].color_math = BIT(data, 5);
2586         break;
2587      case COLDATA:   /* Fixed colour data for fixed colour addition/subtraction */
2588         {
2589            /* Store it in the extra space we made in the CGRAM. It doesn't really go there, but it's as good a place as any. */
2590            UINT8 r, g, b;
2591
2592            /* Get existing value. */
2593            r = m_cgram[FIXED_COLOUR] & 0x1f;
2594            g = (m_cgram[FIXED_COLOUR] & 0x3e0) >> 5;
2595            b = (m_cgram[FIXED_COLOUR] & 0x7c00) >> 10;
2596            /* Set new value */
2597            if (data & 0x20)
2598               r = data & 0x1f;
2599            if (data & 0x40)
2600               g = data & 0x1f;
2601            if (data & 0x80)
2602               b = data & 0x1f;
2603            m_cgram[FIXED_COLOUR] = (r | (g << 5) | (b << 10));
2604         } break;
2605      case SETINI:    /* Screen mode/video select */
2606         m_interlace = (data & 0x01) ? 2 : 1;
2607         m_obj_interlace = (data & 0x02) ? 2 : 1;
2608         m_beam.last_visible_line = (data & 0x04) ? 240 : 225;
2609         m_pseudo_hires = BIT(data, 3);
2610         m_mode7.extbg = BIT(data, 6);
2611         dynamic_res_change(space.machine());
2612#ifdef SNES_DBG_REG_W
2613         if ((data & 0x8) != (PPU_REG(SETINI) & 0x8))
2614            mame_printf_debug("Pseudo 512 mode: %s\n", (data & 0x8) ? "on" : "off");
2615#endif
2616         break;
2617      }
2618
2619   PPU_REG(offset) = data;
2620}
2621
2622/***** Debug Functions *****/
2623
2624#if SNES_LAYER_DEBUG
2625
2626#define DEBUG_TOGGLE(bit, debug_settings, MSG1, MSG2) \
2627   if (BIT(toggles, bit) && !debug_settings)       \
2628   {                                               \
2629      debug_settings = 1;                       \
2630      popmessage MSG1;                          \
2631   }                                               \
2632   else if (!BIT(toggles, bit) && debug_settings)  \
2633   {                                               \
2634      debug_settings = 0;                       \
2635      popmessage MSG2;                          \
2636   }
2637
2638UINT8 snes_ppu_class::dbg_video( running_machine &machine, UINT16 curline )
2639{
2640   int i;
2641   UINT8 toggles = machine.root_device().ioport("DEBUG1")->read_safe(0);
2642   m_debug_options.select_pri[SNES_BG1] = (toggles & 0x03);
2643   m_debug_options.select_pri[SNES_BG2] = (toggles & 0x0c) >> 2;
2644   m_debug_options.select_pri[SNES_BG3] = (toggles & 0x30) >> 4;
2645   m_debug_options.select_pri[SNES_BG4] = (toggles & 0xc0) >> 6;
2646
2647   toggles = machine.root_device().ioport("DEBUG2")->read_safe(0);
2648   for (i = 0; i < 4; i++)
2649      DEBUG_TOGGLE(i, m_debug_options.bg_disabled[i], ("Debug: Disabled BG%d.\n", i + 1), ("Debug: Enabled BG%d.\n", i + 1))
2650   DEBUG_TOGGLE(4, m_debug_options.bg_disabled[SNES_OAM], ("Debug: Disabled OAM.\n"), ("Debug: Enabled OAM.\n"))
2651   DEBUG_TOGGLE(5, m_debug_options.draw_subscreen, ("Debug: Switched screens.\n"), ("Debug: Switched screens.\n"))
2652   DEBUG_TOGGLE(6, m_debug_options.colormath_disabled, ("Debug: Disabled Color Math.\n"), ("Debug: Enabled Color Math.\n"))
2653   DEBUG_TOGGLE(7, m_debug_options.windows_disabled, ("Debug: Disabled Window Masks.\n"), ("Debug: Enabled Window Masks.\n"))
2654
2655   toggles = machine.root_device().ioport("DEBUG4")->read_safe(0);
2656   for (i = 0; i < 8; i++)
2657      DEBUG_TOGGLE(i, m_debug_options.mode_disabled[i], ("Debug: Disabled Mode %d drawing.\n", i), ("Debug: Enabled Mode %d drawing.\n", i))
2658
2659   toggles = machine.root_device().ioport("DEBUG3")->read_safe(0);
2660   DEBUG_TOGGLE(2, m_debug_options.mosaic_disabled, ("Debug: Disabled Mosaic.\n"), ("Debug: Enabled Mosaic.\n"))
2661   m_debug_options.sprite_reversed = BIT(toggles, 7);
2662   m_debug_options.select_pri[SNES_OAM] = (toggles & 0x70) >> 4;
2663
2664#ifdef MAME_DEBUG
2665   /* Once per frame, log video properties */
2666   if (curline == 1)
2667   {
2668      static const char WINLOGIC[4] = { '|', '&', '^', '!' };
2669
2670      logerror("%s", m_debug_options.windows_disabled?" ":"W");
2671      logerror("%s1 %s%s%s%s%s%c%s%s%d%s %d %4X %4X",
2672            m_debug_options.bg_disabled[0]?" ":"*",
2673            (PPU_REG(TM) & 0x1)?"M":" ",
2674            (PPU_REG(TS) & 0x1)?"S":" ",
2675            (PPU_REG(CGADSUB) & 0x1)?"B":" ",
2676            (PPU_REG(TMW) & 0x1)?"m":" ",
2677            (PPU_REG(TSW) & 0x1)?"s":" ",
2678            WINLOGIC[(PPU_REG(WBGLOG) & 0x3)],
2679            (PPU_REG(W12SEL) & 0x2)?((PPU_REG(W12SEL) & 0x1)?"o":"i"):" ",
2680            (PPU_REG(W12SEL) & 0x8)?((PPU_REG(W12SEL) & 0x4)?"o":"i"):" ",
2681            m_layer[SNES_BG1].tile_size + 1,
2682            (PPU_REG(MOSAIC) & 0x1)?"m":" ",
2683            PPU_REG(BG1SC) & 0x3,
2684            (PPU_REG(BG1SC) & 0xfc) << 9,
2685            m_layer[SNES_BG1].charmap << 13);
2686      logerror("%s2 %s%s%s%s%s%c%s%s%d%s %d %4X %4X",
2687            m_debug_options.bg_disabled[1]?" ":"*",
2688            (PPU_REG(TM) & 0x2)?"M":" ",
2689            (PPU_REG(TS) & 0x2)?"S":" ",
2690            (PPU_REG(CGADSUB) & 0x2)?"B":" ",
2691            (PPU_REG(TMW) & 0x2)?"m":" ",
2692            (PPU_REG(TSW) & 0x2)?"s":" ",
2693            WINLOGIC[(PPU_REG(WBGLOG) & 0xc) >> 2],
2694            (PPU_REG(W12SEL) & 0x20)?((PPU_REG(W12SEL) & 0x10)?"o":"i"):" ",
2695            (PPU_REG(W12SEL) & 0x80)?((PPU_REG(W12SEL) & 0x40)?"o":"i"):" ",
2696            m_layer[SNES_BG2].tile_size + 1,
2697            (PPU_REG(MOSAIC) & 0x2)?"m":" ",
2698            PPU_REG(BG2SC) & 0x3,
2699            (PPU_REG(BG2SC) & 0xfc) << 9,
2700            m_layer[SNES_BG2].charmap << 13);
2701      logerror("%s3 %s%s%s%s%s%c%s%s%d%s%s%d %4X %4X",
2702            m_debug_options.bg_disabled[2]?" ":"*",
2703            (PPU_REG(TM) & 0x4)?"M":" ",
2704            (PPU_REG(TS) & 0x4)?"S":" ",
2705            (PPU_REG(CGADSUB) & 0x4)?"B":" ",
2706            (PPU_REG(TMW) & 0x4)?"m":" ",
2707            (PPU_REG(TSW) & 0x4)?"s":" ",
2708            WINLOGIC[(PPU_REG(WBGLOG) & 0x30)>>4],
2709            (PPU_REG(W34SEL) & 0x2)?((PPU_REG(W34SEL) & 0x1)?"o":"i"):" ",
2710            (PPU_REG(W34SEL) & 0x8)?((PPU_REG(W34SEL) & 0x4)?"o":"i"):" ",
2711            m_layer[SNES_BG3].tile_size + 1,
2712            (PPU_REG(MOSAIC) & 0x4)?"m":" ",
2713            (PPU_REG(BGMODE) & 0x8)?"P":" ",
2714            PPU_REG(BG3SC) & 0x3,
2715            (PPU_REG(BG3SC) & 0xfc) << 9,
2716            m_layer[SNES_BG3].charmap << 13);
2717      logerror("%s4 %s%s%s%s%s%c%s%s%d%s %d %4X %4X",
2718            m_debug_options.bg_disabled[3]?" ":"*",
2719            (PPU_REG(TM) & 0x8)?"M":" ",
2720            (PPU_REG(TS) & 0x8)?"S":" ",
2721            (PPU_REG(CGADSUB) & 0x8)?"B":" ",
2722            (PPU_REG(TMW) & 0x8)?"m":" ",
2723            (PPU_REG(TSW) & 0x8)?"s":" ",
2724            WINLOGIC[(PPU_REG(WBGLOG) & 0xc0)>>6],
2725            (PPU_REG(W34SEL) & 0x20)?((PPU_REG(W34SEL) & 0x10)?"o":"i"):" ",
2726            (PPU_REG(W34SEL) & 0x80)?((PPU_REG(W34SEL) & 0x40)?"o":"i"):" ",
2727            m_layer[SNES_BG4].tile_size + 1,
2728            (PPU_REG(MOSAIC) & 0x8)?"m":" ",
2729            PPU_REG(BG4SC) & 0x3,
2730            (PPU_REG(BG4SC) & 0xfc) << 9,
2731            m_layer[SNES_BG4].charmap << 13 );
2732      logerror("%sO %s%s%s%s%s%c%s%s       %4X",
2733            m_debug_options.bg_disabled[4]?" ":"*",
2734            (PPU_REG(TM) & 0x10)?"M":" ",
2735            (PPU_REG(TS) & 0x10)?"S":" ",
2736            (PPU_REG(CGADSUB) & 0x10)?"B":" ",
2737            (PPU_REG(TMW) & 0x10)?"m":" ",
2738            (PPU_REG(TSW) & 0x10)?"s":" ",
2739            WINLOGIC[(PPU_REG(WOBJLOG) & 0x3)],
2740            (PPU_REG(WOBJSEL) & 0x2)?((PPU_REG(WOBJSEL) & 0x1)?"o":"i"):" ",
2741            (PPU_REG(WOBJSEL) & 0x8)?((PPU_REG(WOBJSEL) & 0x4)?"o":"i"):" ",
2742            m_layer[SNES_OAM].charmap << 13 );
2743      logerror("%sB   %s  %c%s%s",
2744            m_debug_options.colormath_disabled?" ":"*",
2745            (PPU_REG(CGADSUB) & 0x20)?"B":" ",
2746            WINLOGIC[(PPU_REG(WOBJLOG) & 0xc)>>2],
2747            (PPU_REG(WOBJSEL) & 0x20)?((PPU_REG(WOBJSEL) & 0x10)?"o":"i"):" ",
2748            (PPU_REG(WOBJSEL) & 0x80)?((PPU_REG(WOBJSEL) & 0x40)?"o":"i"):" " );
2749      logerror("Flags: %s%s%s %s %2d", (PPU_REG(CGWSEL) & 0x2)?"S":"F", (PPU_REG(CGADSUB) & 0x80)?"-":"+", (PPU_REG(CGADSUB) & 0x40)?" 50%":"100%",(PPU_REG(CGWSEL) & 0x1)?"D":"P", (PPU_REG(MOSAIC) & 0xf0) >> 4 );
2750      logerror("SetINI: %s %s %s %s %s %s", (PPU_REG(SETINI) & 0x1)?" I":"NI", (PPU_REG(SETINI) & 0x2)?"P":"R", (PPU_REG(SETINI) & 0x4)?"240":"225",(PPU_REG(SETINI) & 0x8)?"512":"256",(PPU_REG(SETINI) & 0x40)?"E":"N",(PPU_REG(SETINI) & 0x80)?"ES":"NS" );
2751      logerror("Mode7: A %5d B %5d", m_mode7.matrix_a, m_mode7.matrix_b );
2752      logerror(" %s%s%s   C %5d D %5d", (PPU_REG(M7SEL) & 0xc0)?((PPU_REG(M7SEL) & 0x40)?"0":"C"):"R", (PPU_REG(M7SEL) & 0x1)?"H":" ", (PPU_REG(M7SEL) & 0x2)?"V":" ", m_mode7.matrix_c, m_mode7.matrix_d );
2753      logerror("       X %5d Y %5d", m_mode7.origin_x, m_mode7.origin_y );
2754   }
2755#endif
2756
2757   return 0;
2758}
2759#endif /* SNES_LAYER_DEBUG */
branches/new_menus/src/mame/video/k053250.c
r29543r29544
33const device_type K053250 = &device_creator<k053250_device>;
44
55k053250_device::k053250_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
6   : device_t(mconfig, K053250, "K053250", tag, owner, clock, "k053250", __FILE__),
6   : device_t(mconfig, K053250, "Konami 053250", tag, owner, clock, "k053250", __FILE__),
77      device_gfx_interface(mconfig, *this),
88      device_video_interface(mconfig, *this)
99{
branches/new_menus/src/mame/video/seta001.c
r29543r29544
3030const device_type SETA001_SPRITE = &device_creator<seta001_device>;
3131
3232seta001_device::seta001_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
33   : device_t(mconfig, SETA001_SPRITE, "seta001_device", tag, owner, clock, "seta001", __FILE__),
33   : device_t(mconfig, SETA001_SPRITE, "SETA001 SPRITE", tag, owner, clock, "seta001", __FILE__),
3434      m_gfxdecode(*this),
3535      m_palette(*this)
3636{
branches/new_menus/src/mame/video/tc0280grd.h
r29543r29544
4747
4848#define TC0430GRW TC0280GRD
4949
50#define MCFG_TC0280GRD_ADD(_tag, _interface) \
51   MCFG_DEVICE_ADD(_tag, TC0280GRD, 0) \
52   MCFG_DEVICE_CONFIG(_interface)
53
54#define MCFG_TC0430GRW_ADD(_tag, _interface) \
55   MCFG_DEVICE_ADD(_tag, TC0430GRW, 0) \
56   MCFG_DEVICE_CONFIG(_interface)
57
5850#define MCFG_TC0280GRD_GFX_REGION(_region) \
5951   tc0280grd_device::set_gfx_region(*device, _region);
6052
branches/new_menus/src/mame/video/namcona1.c
r29543r29544
1616   const UINT16 *tilemap_videoram,
1717   bool use_4bpp_gfx )
1818{
19   //UINT16 *source;
20
2119   int data = tilemap_videoram[tile_index];
2220   int tile = data&0xfff;
2321   int gfx = use_4bpp_gfx ? 1 : 0;
branches/new_menus/src/mame/video/cps1.c
r29543r29544
13221322   {"mtwins",      CPS_B_14,     mapper_CK24B },
13231323   {"chikij",      CPS_B_14,     mapper_CK24B },   // wrong, this set uses CK22B, dumped but equations still not added
13241324   {"nemo",        CPS_B_15,     mapper_NM24B },
1325   {"nemoa",       CPS_B_15,     mapper_NM24B },
13251326   {"nemoj",       CPS_B_15,     mapper_NM24B },   // wrong, this set uses NM22B, still not dumped
13261327   {"cawing",      CPS_B_16,     mapper_CA24B },
13271328   {"cawingr1",    CPS_B_16,     mapper_CA24B },
branches/new_menus/src/mame/video/scn2674.c
r29543r29544
3434
3535
3636scn2674_device::scn2674_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
37   : device_t(mconfig, SCN2674_VIDEO, "scn2674_device", tag, owner, clock, "scn2674_device", __FILE__),
37   : device_t(mconfig, SCN2674_VIDEO, "SCN2674 VDC", tag, owner, clock, "scn2674_device", __FILE__),
3838      m_interrupt_callback(*this),
3939      m_gfxdecode(*this),
4040      m_palette(*this)
branches/new_menus/src/mame/video/gp9001.c
r29543r29544
203203const device_type GP9001_VDP = &device_creator<gp9001vdp_device>;
204204
205205gp9001vdp_device::gp9001vdp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
206   : device_t(mconfig, GP9001_VDP, "GP9001_VDP", tag, owner, clock, "gp9001vdp", __FILE__),
206   : device_t(mconfig, GP9001_VDP, "GP9001 VDP", tag, owner, clock, "gp9001vdp", __FILE__),
207207      device_video_interface(mconfig, *this),
208208      device_memory_interface(mconfig, *this),
209209      m_space_config("gp9001vdp", ENDIANNESS_BIG, 16,14, 0, NULL, *ADDRESS_MAP_NAME(gp9001vdp_map)),
branches/new_menus/src/mame/video/mcd212.c
r29543r29544
15091509//-------------------------------------------------
15101510
15111511mcd212_device::mcd212_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
1512   : device_t(mconfig, MACHINE_MCD212, "MCD212", tag, owner, clock, "mcd212", __FILE__),
1512   : device_t(mconfig, MACHINE_MCD212, "MCD212 video", tag, owner, clock, "mcd212", __FILE__),
15131513      device_video_interface(mconfig, *this)
15141514{
15151515}
branches/new_menus/src/mame/video/k037122.c
r29543r29544
1414const device_type K037122 = &device_creator<k037122_device>;
1515
1616k037122_device::k037122_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
17   : device_t(mconfig, K037122, "Konami 0371222", tag, owner, clock, "k037122", __FILE__),
17   : device_t(mconfig, K037122, "Konami 037122", tag, owner, clock, "k037122", __FILE__),
1818   device_video_interface(mconfig, *this),
1919   m_tile_ram(NULL),
2020   m_char_ram(NULL),
branches/new_menus/src/mame/drivers/battlera.c
r29543r29544
212212
213213/******************************************************************************/
214214
215static const c6280_interface c6280_config =
216{
217   "audiocpu"
218};
219
220215static MACHINE_CONFIG_START( battlera, battlera_state )
221216
222217   /* basic machine hardware */
r29543r29544
255250   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.85)
256251
257252   MCFG_SOUND_ADD("c6280", C6280, 21477270/6)
258   MCFG_SOUND_CONFIG(c6280_config)
253   MCFG_C6280_CPU("audiocpu")
259254   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.60)
260255   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.60)
261256MACHINE_CONFIG_END
branches/new_menus/src/mame/drivers/pengo.c
r29543r29544
346346GFXDECODE_END
347347
348348
349
350349/*************************************
351350 *
352 *  Sound interfaces
353 *
354 *************************************/
355
356static const namco_interface namco_config =
357{
358   3,          /* number of voices */
359   0           /* stereo */
360};
361
362
363
364/*************************************
365 *
366351 *  Machine drivers
367352 *
368353 *************************************/
r29543r29544
398383   MCFG_SPEAKER_STANDARD_MONO("mono")
399384
400385   MCFG_SOUND_ADD("namco", NAMCO, MASTER_CLOCK/6/32)
401   MCFG_SOUND_CONFIG(namco_config)
386   MCFG_NAMCO_AUDIO_VOICES(3)
402387   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
403388MACHINE_CONFIG_END
404389
branches/new_menus/src/mame/drivers/tourvis.c
r29543r29544
361361   DEVCB_DRIVER_LINE_MEMBER(tourvision_state,tourvision_timer_out)
362362};
363363
364static const c6280_interface c6280_config =
365{
366   "maincpu"
367};
368
369364WRITE_LINE_MEMBER(tourvision_state::pce_irq_changed)
370365{
371366   m_maincpu->set_input_line(0, state);
r29543r29544
401396
402397   MCFG_SPEAKER_STANDARD_STEREO("lspeaker","rspeaker")
403398   MCFG_SOUND_ADD("c6280", C6280, PCE_MAIN_CLOCK/6)
404   MCFG_SOUND_CONFIG(c6280_config)
399   MCFG_C6280_CPU("maincpu")
405400   MCFG_SOUND_ROUTE(0, "lspeaker", 1.00)
406401   MCFG_SOUND_ROUTE(1, "rspeaker", 1.00)
407402
branches/new_menus/src/mame/drivers/ggconnie.c
r29543r29544
175175   PORT_DIPSETTING(0x00, DEF_STR(On) )
176176INPUT_PORTS_END
177177
178static const c6280_interface c6280_config =
179{
180   "maincpu"
181};
182
183178static MACHINE_CONFIG_START( ggconnie, ggconnie_state )
184179   /* basic machine hardware */
185180   MCFG_CPU_ADD("maincpu", H6280, PCE_MAIN_CLOCK/3)
r29543r29544
221216
222217   MCFG_SPEAKER_STANDARD_STEREO("lspeaker","rspeaker")
223218   MCFG_SOUND_ADD("c6280", C6280, PCE_MAIN_CLOCK/6)
224   MCFG_SOUND_CONFIG(c6280_config)
219   MCFG_C6280_CPU("maincpu")
225220   MCFG_SOUND_ROUTE(0, "lspeaker", 1.00)
226221   MCFG_SOUND_ROUTE(1, "rspeaker", 1.00)
227222
branches/new_menus/src/mame/drivers/toypop.c
r29543r29544
473473   GFXDECODE_ENTRY( "gfx2", 0, spritelayout, 128*4,  64 )
474474GFXDECODE_END
475475
476
477
478static const namco_interface namco_config =
479{
480   8,      /* number of voices */
481   0       /* stereo */
482};
483
484
485476/***************************************************************************
486477
487478  Custom I/O initialization
r29543r29544
563554   MCFG_SPEAKER_STANDARD_MONO("mono")
564555
565556   MCFG_SOUND_ADD("namco", NAMCO_15XX, 24000)
566   MCFG_SOUND_CONFIG(namco_config)
557   MCFG_NAMCO_AUDIO_VOICES(8)
567558   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
568559MACHINE_CONFIG_END
569560
branches/new_menus/src/mame/drivers/polepos.c
r29543r29544
823823
824824
825825/*********************************************************************
826 * Sound interfaces
827 *********************************************************************/
828
829static const namco_interface namco_config =
830{
831   8,              /* number of voices */
832   1               /* stereo */
833};
834
835
836/*********************************************************************
837826 * Machine driver
838827 *********************************************************************/
839828
r29543r29544
911900   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
912901
913902   MCFG_SOUND_ADD("namco", NAMCO, MASTER_CLOCK/512)
914   MCFG_SOUND_CONFIG(namco_config)
903   MCFG_NAMCO_AUDIO_VOICES(8)
904   MCFG_NAMCO_AUDIO_STEREO(1)
915905   MCFG_SOUND_ROUTE(0, "lspeaker", 0.80)
916906   MCFG_SOUND_ROUTE(1, "rspeaker", 0.80)
917907
r29543r29544
979969   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
980970
981971   MCFG_SOUND_ADD("namco", NAMCO, MASTER_CLOCK/512)
982   MCFG_SOUND_CONFIG(namco_config)
972   MCFG_NAMCO_AUDIO_VOICES(8)
973   MCFG_NAMCO_AUDIO_STEREO(1)
983974   MCFG_SOUND_ROUTE(0, "lspeaker", 0.80)
984975   MCFG_SOUND_ROUTE(1, "rspeaker", 0.80)
985976
branches/new_menus/src/mame/drivers/ddz.c
r29543r29544
5858
5959INPUT_PORTS_END
6060
61
62static const vr0_interface vr0_config =
63{
64   0x04800000
65};
66
67
6861static MACHINE_CONFIG_START( ddz, ddz_state )
6962   MCFG_CPU_ADD("maincpu", SE3208, 43000000)
7063   MCFG_CPU_PROGRAM_MAP(ddz_mem)
r29543r29544
8881   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
8982
9083   MCFG_SOUND_ADD("vrender", VRENDER0, 0)
91   MCFG_SOUND_CONFIG(vr0_config)
84   MCFG_VR0_REGBASE(0x04800000)
9285   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
9386   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
9487MACHINE_CONFIG_END
branches/new_menus/src/mame/drivers/skykid.c
r29543r29544
415415GFXDECODE_END
416416
417417
418
419static const namco_interface namco_config =
420{
421   8,                  /* number of voices */
422   0                   /* stereo */
423};
424
425418INTERRUPT_GEN_MEMBER(skykid_state::main_vblank_irq)
426419{
427420   if(m_main_irq_mask)
r29543r29544
469462   MCFG_SPEAKER_STANDARD_MONO("mono")
470463
471464   MCFG_SOUND_ADD("namco", NAMCO_CUS30, 49152000/2048)
472   MCFG_SOUND_CONFIG(namco_config)
465   MCFG_NAMCO_AUDIO_VOICES(8)
473466   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
474467MACHINE_CONFIG_END
475468
branches/new_menus/src/mame/drivers/segahang.c
r29543r29544
778778   DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL
779779};
780780
781static const sega_pcm_interface segapcm_interface =
782{
783   BANK_512
784};
785
786
787
788781//**************************************************************************
789782//  GRAPHICS DECODING
790783//**************************************************************************
r29543r29544
882875   MCFG_SOUND_ROUTE(3, "rspeaker", 0.37)
883876
884877   MCFG_SEGAPCM_ADD("pcm", MASTER_CLOCK_8MHz)
885   MCFG_SOUND_CONFIG(segapcm_interface)
878   MCFG_SEGAPCM_BANK(BANK_512)
886879   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
887880   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
888881MACHINE_CONFIG_END
r29543r29544
921914   MCFG_SOUND_ROUTE(3, "rspeaker", 0.37)
922915
923916   MCFG_SEGAPCM_ADD("pcm", MASTER_CLOCK_8MHz/2)
924   MCFG_SOUND_CONFIG(segapcm_interface)
917   MCFG_SEGAPCM_BANK(BANK_512)
925918   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
926919   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
927920MACHINE_CONFIG_END
r29543r29544
943936   MCFG_SOUND_ROUTE(1, "rspeaker", 0.43)
944937
945938   MCFG_SEGAPCM_ADD("pcm", MASTER_CLOCK_8MHz/2)
946   MCFG_SOUND_CONFIG(segapcm_interface)
939   MCFG_SEGAPCM_BANK(BANK_512)
947940   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
948941   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
949942MACHINE_CONFIG_END
branches/new_menus/src/mame/drivers/megaphx.c
r29543r29544
5656
5757#include "emu.h"
5858#include "cpu/m68000/m68000.h"
59#include "cpu/pic16c5x/pic16c5x.h"
5960
6061
6162
r29543r29544
358359};
359360
360361
362static ADDRESS_MAP_START( megaphx_pic_io_map, AS_IO, 8, megaphx_state )
363//   AM_RANGE(0x00, 0x00) AM_WRITE(playmark_oki_banking_w)
364//   AM_RANGE(0x01, 0x01) AM_READWRITE(playmark_snd_command_r, playmark_oki_w)
365//   AM_RANGE(0x02, 0x02) AM_READWRITE(playmark_snd_flag_r, playmark_snd_control_w)
366//   AM_RANGE(PIC16C5x_T0, PIC16C5x_T0) AM_READ(PIC16C5X_T0_clk_r)
367ADDRESS_MAP_END
361368
369
362370static MACHINE_CONFIG_START( megaphx, megaphx_state )
363371
364372   MCFG_CPU_ADD("maincpu", M68000, 8000000) // ??  can't read xtal due to reflections, CPU is an 8Mhz part
365373   MCFG_CPU_PROGRAM_MAP(megaphx_68k_map)
366374
375   MCFG_CPU_ADD("pic", PIC16C54, 12000000)    /* 3MHz */
376   /* Program and Data Maps are internal to the MCU */
377   MCFG_CPU_IO_MAP(megaphx_pic_io_map)
367378
379
368380   MCFG_INDER_AUDIO_ADD("inder_sb")
369381
370382   MCFG_I8255A_ADD( "ppi8255_0", ppi8255_intf_0 )
r29543r29544
408420   ROM_REGION( 0x100000, "inder_sb:audiocpu", 0 )
409421   ROM_LOAD( "sonido_mph0.u35", 0x000000, 0x2000,  CRC(abc1b140) SHA1(8384a162d85cf9ea870d22f44b1ca64001c6a083) )
410422
423   ROM_REGION( 0x100000, "pic", 0 )
424   ROM_LOAD( "pic16c54-xt.bin", 0x000000, 0x430,  CRC(21f396fb) SHA1(c8badb9b3681e684bced0ced1de4c3a15641de8b) )
425
411426   ROM_REGION( 0x100000, "pals", 0 ) // jedutil won't convert these? are they bad?
412427   ROM_LOAD( "p31_u31_palce16v8h-25.jed", 0x000, 0xbd4, CRC(05ef04b7) SHA1(330dd81a832b6675fb0473868c26fe9bec2da854) )
413428   ROM_LOAD( "p40_u29_palce16v8h-25.jed", 0x000, 0xbd4, CRC(44b7e51c) SHA1(b8b34f3b319d664ec3ad72ed87d9f65701f183a5) )
414
415   // there is a PIC responsible for some I/O tasks (what type? what internal rom size?)
416429ROM_END
417430
418431GAME( 1991, megaphx,  0,        megaphx, megaphx, megaphx_state, megaphx, ROT0, "Dinamic / Inder", "Mega Phoenix", GAME_IMPERFECT_GRAPHICS | GAME_IMPERFECT_SOUND )
branches/new_menus/src/mame/drivers/psattack.c
r29543r29544
167167   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
168168INPUT_PORTS_END
169169
170static const vr0_interface vr0_config =
171{
172   0x04800000
173};
174
175
176170static MACHINE_CONFIG_START( psattack, psattack_state )
177171   MCFG_CPU_ADD("maincpu", SE3208, 43000000)
178172   MCFG_CPU_PROGRAM_MAP(psattack_mem)
r29543r29544
196190   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
197191
198192   MCFG_SOUND_ADD("vrender", VRENDER0, 0)
199   MCFG_SOUND_CONFIG(vr0_config)
193   MCFG_VR0_REGBASE(0x04800000)
200194   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
201195   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
202196MACHINE_CONFIG_END
branches/new_menus/src/mame/drivers/cham24.c
r29543r29544
272272   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
273273INPUT_PORTS_END
274274
275static const nesapu_interface cham24_interface_1 =
276{
277   "maincpu"
278};
279
280275void cham24_state::machine_reset()
281276{
282277}
r29543r29544
361356   MCFG_SPEAKER_STANDARD_MONO("mono")
362357
363358   MCFG_SOUND_ADD("nesapu", NES_APU, N2A03_DEFAULTCLOCK)
364   MCFG_SOUND_CONFIG(cham24_interface_1)
359   MCFG_NES_APU_CPU("maincpu")
365360   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
366361
367362   MCFG_DAC_ADD("dac")
branches/new_menus/src/mame/drivers/multigam.c
r29543r29544
11401140
11411141*******************************************************/
11421142
1143static const nesapu_interface multigam_interface_1 =
1144{
1145   "maincpu"
1146};
1147
11481143PALETTE_INIT_MEMBER(multigam_state, multigam)
11491144{
11501145   m_ppu->init_palette(palette, 0);
r29543r29544
12621257   MCFG_SPEAKER_STANDARD_MONO("mono")
12631258
12641259   MCFG_SOUND_ADD("nesapu", NES_APU, N2A03_DEFAULTCLOCK)
1265   MCFG_SOUND_CONFIG(multigam_interface_1)
1260   MCFG_NES_APU_CPU("maincpu")
12661261   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
12671262
12681263   MCFG_DAC_ADD("dac")
branches/new_menus/src/mame/drivers/baraduke.c
r29543r29544
364364
365365
366366
367static const namco_interface namco_config =
368{
369   8,                  /* number of voices */
370   0                   /* stereo */
371};
372
373
374
375367static MACHINE_CONFIG_START( baraduke, baraduke_state )
376368
377369   /* basic machine hardware */
r29543r29544
401393   MCFG_SPEAKER_STANDARD_MONO("mono")
402394
403395   MCFG_SOUND_ADD("namco", NAMCO_CUS30, XTAL_49_152MHz/2048)
404   MCFG_SOUND_CONFIG(namco_config)
396   MCFG_NAMCO_AUDIO_VOICES(8)
405397   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
406398MACHINE_CONFIG_END
407399
branches/new_menus/src/mame/drivers/nss.c
r29543r29544
844844   MCFG_SCREEN_RAW_PARAMS(DOTCLK_NTSC, SNES_HTOTAL, 0, SNES_SCR_WIDTH, SNES_VTOTAL_NTSC, 0, SNES_SCR_HEIGHT_NTSC)
845845   MCFG_SCREEN_UPDATE_DRIVER( snes_state, screen_update )
846846
847   MCFG_DEVICE_ADD("ppu", SNES_PPU, 0)
848   MCFG_SNES_PPU_OPENBUS_CB(READ8(snes_state, snes_open_bus_r))
849   MCFG_VIDEO_SET_SCREEN("screen")
850
847851   // NSS
848852   MCFG_SCREEN_ADD("osd", RASTER)
849853   MCFG_SCREEN_REFRESH_RATE(60)
branches/new_menus/src/mame/drivers/battlnts.c
r29543r29544
3838WRITE8_MEMBER(battlnts_state::battlnts_bankswitch_w)
3939{
4040   /* bits 6 & 7 = bank number */
41   membank("bank1")->set_entry((data & 0xc0) >> 6);
41   m_rombank->set_entry((data & 0xc0) >> 6);
4242
4343   /* bits 4 & 5 = coin counters */
4444   coin_counter_w(machine(), 0, data & 0x10);
r29543r29544
7070   AM_RANGE(0x2e10, 0x2e10) AM_WRITE(watchdog_reset_w)         /* watchdog reset */
7171   AM_RANGE(0x2e14, 0x2e14) AM_WRITE(soundlatch_byte_w)                /* sound code # */
7272   AM_RANGE(0x2e18, 0x2e18) AM_WRITE(battlnts_sh_irqtrigger_w) /* cause interrupt on audio CPU */
73   AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")                        /* banked ROM */
73   AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("rombank")              /* banked ROM */
7474   AM_RANGE(0x8000, 0xffff) AM_ROM                             /* ROM 777e02.bin */
7575ADDRESS_MAP_END
7676
r29543r29544
212212{
213213   UINT8 *ROM = memregion("maincpu")->base();
214214
215   membank("bank1")->configure_entries(0, 4, &ROM[0x10000], 0x4000);
215   m_rombank->configure_entries(0, 4, &ROM[0x10000], 0x4000);
216216
217217   save_item(NAME(m_spritebank));
218218   save_item(NAME(m_layer_colorbase));
branches/new_menus/src/mame/drivers/pacland.c
r29543r29544
402402GFXDECODE_END
403403
404404
405
406static const namco_interface namco_config =
407{
408   8,      /* number of voices */
409   0       /* stereo */
410};
411
412405INTERRUPT_GEN_MEMBER(pacland_state::main_vblank_irq)
413406{
414407   if(m_main_irq_mask)
r29543r29544
450443   MCFG_SPEAKER_STANDARD_MONO("mono")
451444
452445   MCFG_SOUND_ADD("namco", NAMCO_CUS30, XTAL_49_152MHz/2/1024)
453   MCFG_SOUND_CONFIG(namco_config)
446   MCFG_NAMCO_AUDIO_VOICES(8)
454447   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
455448MACHINE_CONFIG_END
456449
branches/new_menus/src/mame/drivers/namcos2.c
r29543r29544
16631663   GFXDECODE_ENTRY( "gfx2", 0x000000, chr_layout,              16*256, 16 )
16641664GFXDECODE_END
16651665
1666static const c140_interface c140_config =
1667{
1668   C140_TYPE_SYSTEM2
1669};
1670
16711666/* end */
16721667
16731668/******************************************
r29543r29544
17391734   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
17401735
17411736   MCFG_C140_ADD("c140", C140_SOUND_CLOCK) /* 21.333kHz */
1742   MCFG_SOUND_CONFIG(c140_config)
1737   MCFG_C140_BANK_TYPE(C140_TYPE_SYSTEM2)
17431738   MCFG_SOUND_ROUTE(0, "lspeaker", 0.75)
17441739   MCFG_SOUND_ROUTE(1, "rspeaker", 0.75)
17451740
r29543r29544
17521747static MACHINE_CONFIG_DERIVED( default2, default )
17531748
17541749   MCFG_C140_REPLACE("c140", C140_SOUND_CLOCK) /* 21.333kHz */
1755   MCFG_SOUND_CONFIG(c140_config)
1750   MCFG_C140_BANK_TYPE(C140_TYPE_SYSTEM2)
17561751   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
17571752   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
17581753MACHINE_CONFIG_END
r29543r29544
17661761static MACHINE_CONFIG_DERIVED( default3, default )
17671762
17681763   MCFG_C140_REPLACE("c140", C140_SOUND_CLOCK) /* 21.333kHz */
1769   MCFG_SOUND_CONFIG(c140_config)
1764   MCFG_C140_BANK_TYPE(C140_TYPE_SYSTEM2)
17701765   MCFG_SOUND_ROUTE(0, "lspeaker", 0.45)
17711766   MCFG_SOUND_ROUTE(1, "rspeaker", 0.45)
17721767
r29543r29544
18141809   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
18151810
18161811   MCFG_C140_ADD("c140", C140_SOUND_CLOCK) /* 21.333kHz */
1817   MCFG_SOUND_CONFIG(c140_config)
1812   MCFG_C140_BANK_TYPE(C140_TYPE_SYSTEM2)
18181813   MCFG_SOUND_ROUTE(0, "lspeaker", 0.75)
18191814   MCFG_SOUND_ROUTE(1, "rspeaker", 0.75)
18201815
r29543r29544
18671862   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
18681863
18691864   MCFG_C140_ADD("c140", C140_SOUND_CLOCK) /* 21.333kHz */
1870   MCFG_SOUND_CONFIG(c140_config)
1865   MCFG_C140_BANK_TYPE(C140_TYPE_SYSTEM2)
18711866   MCFG_SOUND_ROUTE(0, "lspeaker", 0.75)
18721867   MCFG_SOUND_ROUTE(1, "rspeaker", 0.75)
18731868
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19171912   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
19181913
19191914   MCFG_C140_ADD("c140", C140_SOUND_CLOCK) /* 21.333kHz */
1920   MCFG_SOUND_CONFIG(c140_config)
1915   MCFG_C140_BANK_TYPE(C140_TYPE_SYSTEM2)
19211916   MCFG_SOUND_ROUTE(0, "lspeaker", 0.75)
19221917   MCFG_SOUND_ROUTE(1, "rspeaker", 0.75)
19231918
r29543r29544
19721967   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
19731968
19741969   MCFG_C140_ADD("c140", C140_SOUND_CLOCK) /* 21.333kHz */
1975   MCFG_SOUND_CONFIG(c140_config)
1970   MCFG_C140_BANK_TYPE(C140_TYPE_SYSTEM2)
19761971   MCFG_SOUND_ROUTE(0, "lspeaker", 0.75)
19771972   MCFG_SOUND_ROUTE(1, "rspeaker", 0.75)
19781973
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20252020   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
20262021
20272022   MCFG_C140_ADD("c140", C140_SOUND_CLOCK) /* 21.333kHz */
2028   MCFG_SOUND_CONFIG(c140_config)
2023   MCFG_C140_BANK_TYPE(C140_TYPE_SYSTEM2)
20292024   MCFG_SOUND_ROUTE(0, "lspeaker", 0.75)
20302025   MCFG_SOUND_ROUTE(1, "rspeaker", 0.75)
20312026
r29543r29544
20752070   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
20762071
20772072   MCFG_C140_ADD("c140", C140_SOUND_CLOCK) /* 21.333kHz */
2078   MCFG_SOUND_CONFIG(c140_config)
2073   MCFG_C140_BANK_TYPE(C140_TYPE_SYSTEM2)
20792074   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
20802075   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
20812076
branches/new_menus/src/mame/drivers/cps1.c
r29543r29544
57295729   ROM_LOAD( "iob1.11e",     0x0000, 0x0117, CRC(3abc0700) SHA1(973043aa46ec6d5d1db20dc9d5937005a0f9f6ae) )
57305730ROM_END
57315731
5732/* B-Board 89624B-3 */
5733ROM_START( nemoa )
5734   ROM_REGION( CODE_SIZE, "maincpu", 0 )      /* 68000 code */
5735   ROM_LOAD16_BYTE( "nme_30.11f",    0x00000, 0x20000, CRC(71b333db) SHA1(8bd8b62d8fef2ad9d2788ccf46e89da953e5817c) )
5736   ROM_LOAD16_BYTE( "nme_35.11h",    0x00001, 0x20000, CRC(d153bc18) SHA1(2b4a9a50081d403a6485b7311e179a31b659b74d) )
5737   ROM_LOAD16_BYTE( "nme_31.12f",    0x40000, 0x20000, CRC(7e83dbd2) SHA1(d4c7e3786faab4dd9ded3c1a8f6fea114d423e64) )
5738   ROM_LOAD16_BYTE( "nme_36.12h",    0x40001, 0x20000, CRC(6aeeec81) SHA1(d7dce52d0f2225d844d852d2c3e81a48cb53a43d) )
5739   ROM_LOAD16_WORD_SWAP( "nm-32m.8h", 0x80000, 0x80000, CRC(d6d1add3) SHA1(61c3013d322dbb7622cca032adcd020ba318e885) )
5740
5741   ROM_REGION( 0x200000, "gfx", 0 )
5742   ROMX_LOAD( "nm-5m.7a",  0x000000, 0x80000, CRC(487b8747) SHA1(f14339b02b8f7ec2002632349e88fed4afc30050) , ROM_GROUPWORD | ROM_SKIP(6) )
5743   ROMX_LOAD( "nm-7m.9a",  0x000002, 0x80000, CRC(203dc8c6) SHA1(d52577500e822b89904d1510d559f8575c2aaa78) , ROM_GROUPWORD | ROM_SKIP(6) )
5744   ROMX_LOAD( "nm-1m.3a",  0x000004, 0x80000, CRC(9e878024) SHA1(9a5ce3a6a7952a8954d0709b9473db9253793d70) , ROM_GROUPWORD | ROM_SKIP(6) )
5745   ROMX_LOAD( "nm-3m.5a",  0x000006, 0x80000, CRC(bb01e6b6) SHA1(3883e28f721d0278b2f4f877a804e95ee14f53e4) , ROM_GROUPWORD | ROM_SKIP(6) )
5746
5747   ROM_REGION( 0x18000, "audiocpu", 0 ) /* 64k for the audio CPU (+banks) */
5748   ROM_LOAD( "nme_09.12b", 0x00000, 0x08000, CRC(0f4b0581) SHA1(2e5a2885149c632abfaf4292a1bf032c13c8da6c) )
5749   ROM_CONTINUE(           0x10000, 0x08000 )
5750
5751   ROM_REGION( 0x40000, "oki", 0 ) /* Samples */
5752   ROM_LOAD( "nme_18.11c", 0x00000, 0x20000, CRC(bab333d4) SHA1(c1d0fb61ec46f17eb7edf69e1ad5ac91b5d51daa) )
5753   ROM_LOAD( "nme_19.12c", 0x20000, 0x20000, CRC(2650a0a8) SHA1(e9e8cc1b27a2cb3e87124061fabcf42982f0611f) )
5754
5755   ROM_REGION( 0x0200, "aboardplds", 0 )
5756   ROM_LOAD( "buf1",         0x0000, 0x0117, CRC(eb122de7) SHA1(b26b5bfe258e3e184f069719f9fd008d6b8f6b9b) )
5757   ROM_LOAD( "ioa1",         0x0000, 0x0117, CRC(59c7ee3b) SHA1(fbb887c5b4f5cb8df77cec710eaac2985bc482a6) )
5758   ROM_LOAD( "prg1",         0x0000, 0x0117, CRC(f1129744) SHA1(a5300f301c1a08a7da768f0773fa0fe3f683b237) )
5759   ROM_LOAD( "rom1",         0x0000, 0x0117, CRC(41dc73b9) SHA1(7d4c9f1693c821fbf84e32dd6ef62ddf14967845) )
5760   ROM_LOAD( "sou1",         0x0000, 0x0117, CRC(84f4b2fe) SHA1(dcc9e86cc36316fe42eace02d6df75d08bc8bb6d) )
5761
5762   ROM_REGION( 0x0200, "bboardplds", 0 )
5763   ROM_LOAD( "nm24b.1a",     0x0000, 0x0117, CRC(7b25bac6) SHA1(fa0083c59c8d6da07798cb3a4fc25d388065b7cd) ) // no markings visible, assumed to be the same
5764   ROM_LOAD( "iob1.11e",     0x0000, 0x0117, CRC(3abc0700) SHA1(973043aa46ec6d5d1db20dc9d5937005a0f9f6ae) )
5765ROM_END
5766
5767
57325768/* B-Board 89625B-? */
57335769ROM_START( nemoj )
57345770   ROM_REGION( CODE_SIZE, "maincpu", 0 )      /* 68000 code */
r29543r29544
1146611502GAME( 1990, cawingu,     cawing,   cps1_10MHz, cawing,   cps_state,   cps1,     ROT0,   "Capcom", "Carrier Air Wing (USA 901012)", GAME_SUPPORTS_SAVE )
1146711503GAME( 1990, cawingj,     cawing,   cps1_10MHz, cawing,   cps_state,   cps1,     ROT0,   "Capcom", "U.S. Navy (Japan 901012)", GAME_SUPPORTS_SAVE )
1146811504GAME( 1990, nemo,        0,        cps1_10MHz, nemo,     cps_state,   cps1,     ROT0,   "Capcom", "Nemo (World 901130)", GAME_SUPPORTS_SAVE )   // "ETC"
11505GAME( 1990, nemoa,       nemo,     cps1_10MHz, nemo,     cps_state,   cps1,     ROT0,   "Capcom", "Nemo (World 901109)", GAME_SUPPORTS_SAVE )   // "ETC"
1146911506GAME( 1990, nemoj,       nemo,     cps1_10MHz, nemo,     cps_state,   cps1,     ROT0,   "Capcom", "Nemo (Japan 901120)", GAME_SUPPORTS_SAVE )
1147011507GAME( 1991, sf2,         0,        cps1_10MHz, sf2,      cps_state,   cps1,     ROT0,   "Capcom", "Street Fighter II: The World Warrior (World 910522)", GAME_SUPPORTS_SAVE )   // "ETC"
1147111508GAME( 1991, sf2eb,       sf2,      cps1_10MHz, sf2,      cps_state,   cps1,     ROT0,   "Capcom", "Street Fighter II: The World Warrior (World 910214)", GAME_SUPPORTS_SAVE )   // "ETC"
branches/new_menus/src/mame/drivers/segaorun.c
r29543r29544
11601160
11611161
11621162//**************************************************************************
1163//  SOUND DEFINITIONS
1164//**************************************************************************
1165
1166static const sega_pcm_interface segapcm_interface =
1167{
1168   BANK_512
1169};
1170
1171
1172
1173//**************************************************************************
11741163//  GRAPHICS DEFINITIONS
11751164//**************************************************************************
11761165
r29543r29544
12231212   MCFG_SOUND_ROUTE(1, "rspeaker", 0.43)
12241213
12251214   MCFG_SEGAPCM_ADD("pcm", SOUND_CLOCK/4)
1226   MCFG_SOUND_CONFIG(segapcm_interface)
1215   MCFG_SEGAPCM_BANK(BANK_512)
12271216   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
12281217   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
12291218MACHINE_CONFIG_END
branches/new_menus/src/mame/drivers/mappy.c
r29543r29544
15951595GFXDECODE_END
15961596
15971597
1598
15991598/***************************************************************************
16001599
1601  Sound interface
1602
1603***************************************************************************/
1604
1605static const namco_interface namco_config =
1606{
1607   8,              /* number of voices */
1608   0               /* stereo */
1609};
1610
1611
1612/***************************************************************************
1613
16141600  Custom I/O initialization
16151601
16161602***************************************************************************/
r29543r29544
17091695   MCFG_SPEAKER_STANDARD_MONO("mono")
17101696
17111697   MCFG_SOUND_ADD("namco", NAMCO_15XX, 18432000/768)
1712   MCFG_SOUND_CONFIG(namco_config)
1698   MCFG_NAMCO_AUDIO_VOICES(8)
17131699   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
17141700MACHINE_CONFIG_END
17151701
r29543r29544
18321818   MCFG_SPEAKER_STANDARD_MONO("mono")
18331819
18341820   MCFG_SOUND_ADD("namco", NAMCO_15XX, 18432000/768)
1835   MCFG_SOUND_CONFIG(namco_config)
1821   MCFG_NAMCO_AUDIO_VOICES(8)
18361822   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
18371823MACHINE_CONFIG_END
18381824
r29543r29544
18711857   MCFG_SPEAKER_STANDARD_MONO("mono")
18721858
18731859   MCFG_SOUND_ADD("namco", NAMCO_15XX, 18432000/768)
1874   MCFG_SOUND_CONFIG(namco_config)
1860   MCFG_NAMCO_AUDIO_VOICES(8)
18751861   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
18761862MACHINE_CONFIG_END
18771863
branches/new_menus/src/mame/drivers/namcona1.c
r29543r29544
300300
301301   if( source>=0x400000 && source<0xc00000 )
302302   {
303      data = m_mpBank1[(source-0x400000)/2];
303      data = m_maskrom[(source-0x400000)/2];
304304   }
305305   else if( source>=0xc00000 && source<0xe00000 )
306306   {
307      data = m_mpBank0[(source-0xc00000)/2];
307      data = m_prgrom[(source-0xc00000)/2];
308308   }
309309   else if( source<0x80000 && source>=0x1000 )
310310   {
r29543r29544
540540static ADDRESS_MAP_START( namcona1_main_map, AS_PROGRAM, 16, namcona1_state )
541541   AM_RANGE(0x000000, 0x07ffff) AM_RAM AM_SHARE("workram")
542542   AM_RANGE(0x3f8000, 0x3fffff) AM_READWRITE(mcu_mailbox_r, mcu_mailbox_w_68k)
543   AM_RANGE(0x400000, 0xbfffff) AM_ROM AM_REGION("maincpu", 0x280000)  /* data */
544   AM_RANGE(0xc00000, 0xdfffff) AM_ROM AM_REGION("maincpu", 0x080000)  /* code */
543   AM_RANGE(0x400000, 0xbfffff) AM_ROM AM_REGION("maskrom", 0)  // data
544   AM_RANGE(0xc00000, 0xdfffff) AM_ROM AM_REGION("maincpu", 0)  // code
545545   AM_RANGE(0xe00000, 0xe00fff) AM_DEVREADWRITE8("eeprom", eeprom_parallel_28xx_device, read, write, 0x00ff)
546546   AM_RANGE(0xe40000, 0xe4000f) AM_READWRITE(custom_key_r, custom_key_w)
547547   AM_RANGE(0xefff00, 0xefffff) AM_RAM_WRITE(namcona1_vreg_w) AM_SHARE("vreg")
r29543r29544
555555
556556
557557static ADDRESS_MAP_START( namcona2_main_map, AS_PROGRAM, 16, namcona1_state )
558   AM_RANGE(0x000000, 0x07ffff) AM_RAM AM_SHARE("workram")
559   AM_RANGE(0x3f8000, 0x3fffff) AM_READWRITE(mcu_mailbox_r, mcu_mailbox_w_68k)
560   AM_RANGE(0x400000, 0xbfffff) AM_ROM AM_REGION("maincpu", 0x280000)  /* data */
558   AM_IMPORT_FROM(namcona1_main_map)
561559   AM_RANGE(0xd00000, 0xd00001) AM_WRITENOP /* xday: serial out? */
562560   AM_RANGE(0xd40000, 0xd40001) AM_WRITENOP /* xday: serial out? */
563561   AM_RANGE(0xd80000, 0xd80001) AM_WRITENOP /* xday: serial out? */
564562   AM_RANGE(0xdc0000, 0xdc001f) AM_WRITENOP /* xday: serial config? */
565   AM_RANGE(0xc00000, 0xdfffff) AM_ROM AM_REGION("maincpu", 0x080000)  /* code */
566   AM_RANGE(0xe00000, 0xe00fff) AM_DEVREADWRITE8("eeprom", eeprom_parallel_28xx_device, read, write, 0x00ff)
567563   /* xday: additional battery-backed ram at 00E024FA? */
568   AM_RANGE(0xe40000, 0xe4000f) AM_READWRITE(custom_key_r, custom_key_w)
569   AM_RANGE(0xefff00, 0xefffff) AM_RAM_WRITE(namcona1_vreg_w) AM_SHARE("vreg")
570   AM_RANGE(0xf00000, 0xf01fff) AM_RAM_WRITE(namcona1_paletteram_w) AM_SHARE("paletteram")
571   AM_RANGE(0xf40000, 0xf7ffff) AM_READWRITE(namcona1_gfxram_r, namcona1_gfxram_w) AM_SHARE("cgram")
572   AM_RANGE(0xff0000, 0xffbfff) AM_RAM_WRITE(namcona1_videoram_w) AM_SHARE("videoram")
573   AM_RANGE(0xffd000, 0xffdfff) AM_RAM /* unknown */
574   AM_RANGE(0xffe000, 0xffefff) AM_RAM AM_SHARE("scroll")      /* scroll registers */
575   AM_RANGE(0xfff000, 0xffffff) AM_RAM AM_SHARE("spriteram")           /* spriteram */
576564ADDRESS_MAP_END
577565
578566
r29543r29544
580568
581569READ16_MEMBER(namcona1_state::na1mcu_shared_r)
582570{
583   UINT16 data;
571   UINT16 data = FLIPENDIAN_INT16(m_workram[offset]);
584572
585   data = m_workram[offset];
586
587573#if 0
588574   if (offset >= 0x70000/2)
589575   {
590      logerror("MD: %04x @ %x PC %x\n", ((data>>8)&0xff) | ((data<<8)&0xff00), offset*2, space.device().safe_pc());
576      logerror("MD: %04x @ %x PC %x\n", data, offset*2, space.device().safe_pc());
591577   }
592578#endif
593
594   return ((data>>8)&0xff) | ((data<<8)&0xff00);
579   return data;
595580}
596581
597582WRITE16_MEMBER(namcona1_state::na1mcu_shared_w)
r29543r29544
714699
715700void namcona1_state::machine_start()
716701{
702   m_prgrom = (UINT16 *)memregion("maincpu")->base();
703   m_maskrom = (UINT16 *)memregion("maskrom")->base();
704   m_mEnableInterrupts = 0;
717705   m_c140->set_base(m_workram);
718706}
719707
720// for games with the MCU emulated, the MCU boots the 68000.  don't allow it before that.
708// the MCU boots the 68000
721709void namcona1_state::machine_reset()
722710{
723711   m_maincpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
r29543r29544
911899
912900/***************************************************************************/
913901
902// MCU interrupts: IRQ 0 => process mail slot (probably set on mail slot write from 68k)
903//                 IRQ 1 =>
904//                 IRQ 2 =>
905
914906TIMER_DEVICE_CALLBACK_MEMBER(namcona1_state::namcona1_interrupt)
915907{
916908   int scanline = param;
917909   int enabled = m_mEnableInterrupts ? ~m_vreg[0x1a/2] : 0;
918910
911   // adc (timing guessed, when does this trigger?)
912   if (scanline == 0)
913      m_mcu->set_input_line(M37710_LINE_ADC, HOLD_LINE);
914
919915   // vblank
920916   if (scanline == 224)
921917   {
918      m_mcu->set_input_line(M37710_LINE_IRQ1, HOLD_LINE);
922919      simulate_mcu( );
923920      if (enabled & 8)
924921         m_maincpu->set_input_line(4, HOLD_LINE);
r29543r29544
935932   }
936933}
937934
938// MCU interrupts: IRQ 0 => process mail slot (probably set on mail slot write from 68k)
939//                 IRQ 1 =>
940//                 IRQ 2 =>
941
942TIMER_DEVICE_CALLBACK_MEMBER(namcona1_state::mcu_interrupt)
943{
944   int scanline = param;
945
946   // vblank
947   if (scanline == 224)
948      m_mcu->set_input_line(M37710_LINE_IRQ1, HOLD_LINE);
949
950   // adc (timing guessed, when does this trigger?)
951   if (scanline == 0)
952      m_mcu->set_input_line(M37710_LINE_ADC, HOLD_LINE);
953}
954
955static const c140_interface C140_interface_typeA =
956{
957   C140_TYPE_ASIC219
958};
959
960935/* cropped at sides */
961936static MACHINE_CONFIG_START( namcona1, namcona1_state )
962937
963938   /* basic machine hardware */
964939   MCFG_CPU_ADD("maincpu", M68000, MASTER_CLOCK/4)
965940   MCFG_CPU_PROGRAM_MAP(namcona1_main_map)
966   MCFG_TIMER_DRIVER_ADD_SCANLINE("scan_main", namcona1_state, namcona1_interrupt, "screen", 0, 1)
967941
968942   MCFG_CPU_ADD("mcu", M37702, MASTER_CLOCK/4)
969943   MCFG_CPU_PROGRAM_MAP(namcona1_mcu_map)
970944   MCFG_CPU_IO_MAP( namcona1_mcu_io_map)
971   MCFG_TIMER_DRIVER_ADD_SCANLINE("scan_mcu", namcona1_state, mcu_interrupt, "screen", 0, 1)
972945
946   MCFG_TIMER_DRIVER_ADD_SCANLINE("scan_main", namcona1_state, namcona1_interrupt, "screen", 0, 1)
947
973948   MCFG_EEPROM_2816_ADD("eeprom")
974   MCFG_QUANTUM_TIME(attotime::from_hz(2400))
975949
976950   /* video hardware */
977951   MCFG_SCREEN_ADD("screen", RASTER)
r29543r29544
984958
985959   MCFG_PALETTE_ADD("palette", 0x2000)
986960   MCFG_PALETTE_ENABLE_SHADOWS()
961
987962   MCFG_GFXDECODE_ADD("gfxdecode", "palette", namcona1)
988963
989964   /* sound hardware */
990965   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
991966
992967   MCFG_C140_ADD("c140", 44100)
993   MCFG_SOUND_CONFIG(C140_interface_typeA)
968   MCFG_C140_BANK_TYPE(C140_TYPE_ASIC219)
994969   MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
995970   MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
996971MACHINE_CONFIG_END
r29543r29544
1013988MACHINE_CONFIG_END
1014989
1015990
1016void namcona1_state::init_namcona1( int gametype )
1017{
1018   UINT16 *pMem = (UINT16 *)memregion( "maincpu" )->base();
991DRIVER_INIT_MEMBER(namcona1_state,bkrtmaq)   { m_gametype = NAMCO_BKRTMAQ; }
992DRIVER_INIT_MEMBER(namcona1_state,cgangpzl)  { m_gametype = NAMCO_CGANGPZL; }
993DRIVER_INIT_MEMBER(namcona1_state,emeralda)  { m_gametype = NAMCO_EMERALDA; } /* NA-2 Hardware */
994DRIVER_INIT_MEMBER(namcona1_state,emeraldj)  { m_gametype = NAMCO_EMERALDA; } /* NA-1 Hardware */
995DRIVER_INIT_MEMBER(namcona1_state,exbania)   { m_gametype = NAMCO_EXBANIA; }
996DRIVER_INIT_MEMBER(namcona1_state,fa)        { m_gametype = NAMCO_FA; }
997DRIVER_INIT_MEMBER(namcona1_state,knckhead)  { m_gametype = NAMCO_KNCKHEAD; }
998DRIVER_INIT_MEMBER(namcona1_state,numanath)  { m_gametype = NAMCO_NUMANATH; }
999DRIVER_INIT_MEMBER(namcona1_state,quiztou)   { m_gametype = NAMCO_QUIZTOU; }
1000DRIVER_INIT_MEMBER(namcona1_state,swcourt)   { m_gametype = NAMCO_SWCOURT; }
1001DRIVER_INIT_MEMBER(namcona1_state,tinklpit)  { m_gametype = NAMCO_TINKLPIT; }
1002DRIVER_INIT_MEMBER(namcona1_state,xday2)     { m_gametype = NAMCO_XDAY2; }
10191003
1020   m_gametype = gametype;
1021   m_mpBank0 = &pMem[0x80000/2];
1022   m_mpBank1 = m_mpBank0 +  0x200000/2;
1023
1024   m_mEnableInterrupts = 0;
1025}
1026
1027DRIVER_INIT_MEMBER(namcona1_state,bkrtmaq)   { init_namcona1(NAMCO_BKRTMAQ); }
1028DRIVER_INIT_MEMBER(namcona1_state,cgangpzl)  { init_namcona1(NAMCO_CGANGPZL); }
1029DRIVER_INIT_MEMBER(namcona1_state,emeralda)  { init_namcona1(NAMCO_EMERALDA); } /* NA-2 Hardware */
1030DRIVER_INIT_MEMBER(namcona1_state,emeraldj)  { init_namcona1(NAMCO_EMERALDA); } /* NA-1 Hardware */
1031DRIVER_INIT_MEMBER(namcona1_state,exbania)   { init_namcona1(NAMCO_EXBANIA); }
1032DRIVER_INIT_MEMBER(namcona1_state,fa)        { init_namcona1(NAMCO_FA); }
1033DRIVER_INIT_MEMBER(namcona1_state,knckhead)  { init_namcona1(NAMCO_KNCKHEAD); }
1034DRIVER_INIT_MEMBER(namcona1_state,numanath)  { init_namcona1(NAMCO_NUMANATH); }
1035DRIVER_INIT_MEMBER(namcona1_state,quiztou)   { init_namcona1(NAMCO_QUIZTOU); }
1036DRIVER_INIT_MEMBER(namcona1_state,swcourt)   { init_namcona1(NAMCO_SWCOURT); }
1037DRIVER_INIT_MEMBER(namcona1_state,tinklpit)  { init_namcona1(NAMCO_TINKLPIT); }
1038DRIVER_INIT_MEMBER(namcona1_state,xday2)     { init_namcona1(NAMCO_XDAY2); }
1039
10401004ROM_START( bkrtmaq )
1041   ROM_REGION( 0xa80000, "maincpu", 0 )
1042   ROM_LOAD16_BYTE( "mq1-ep0l.bin", 0x080001, 0x080000, CRC(f029bc57) SHA1(fdbf8b8b9f69d5755ca5197dda4f887b12dd66f4) ) /* 0xc00000 */
1043   ROM_LOAD16_BYTE( "mq1-ep0u.bin", 0x080000, 0x080000, CRC(4cff62b8) SHA1(5cac170dcfbeb3dcfa0840bdbe7541a9d2f44a14) )
1044   ROM_LOAD16_BYTE( "mq1-ep1l.bin", 0x180001, 0x080000, CRC(e3be6f4b) SHA1(75d9a4cff25e63a9d6c092aa6e241eccd1c61f91) )
1045   ROM_LOAD16_BYTE( "mq1-ep1u.bin", 0x180000, 0x080000, CRC(b44e31b2) SHA1(3d8c63789b98ada3663ba9e28c370815a9a9c3ed) )
1005   ROM_REGION( 0x200000, "maincpu", 0 )
1006   ROM_LOAD16_BYTE( "mq1-ep0l.bin", 0x000001, 0x080000, CRC(f029bc57) SHA1(fdbf8b8b9f69d5755ca5197dda4f887b12dd66f4) ) /* 0xc00000 */
1007   ROM_LOAD16_BYTE( "mq1-ep0u.bin", 0x000000, 0x080000, CRC(4cff62b8) SHA1(5cac170dcfbeb3dcfa0840bdbe7541a9d2f44a14) )
1008   ROM_LOAD16_BYTE( "mq1-ep1l.bin", 0x100001, 0x080000, CRC(e3be6f4b) SHA1(75d9a4cff25e63a9d6c092aa6e241eccd1c61f91) )
1009   ROM_LOAD16_BYTE( "mq1-ep1u.bin", 0x100000, 0x080000, CRC(b44e31b2) SHA1(3d8c63789b98ada3663ba9e28c370815a9a9c3ed) )
10461010
1047   ROM_LOAD16_BYTE( "mq1-ma0l.bin", 0x280001, 0x100000, CRC(11fed35f) SHA1(511d98b6b42b330238a1874bca031b1892654a48) ) /* 0x400000 */
1048   ROM_LOAD16_BYTE( "mq1-ma0u.bin", 0x280000, 0x100000, CRC(23442ac0) SHA1(fac706f24045d51a2712f51530967140ea8e875f) )
1049   ROM_LOAD16_BYTE( "mq1-ma1l.bin", 0x480001, 0x100000, CRC(fe82205f) SHA1(860cc7a96ae3f848ce594077c1362e4e22a36908) )
1050   ROM_LOAD16_BYTE( "mq1-ma1u.bin", 0x480000, 0x100000, CRC(0cdb6bd0) SHA1(b8b398477c9654e96921110fb30c754240183897) )
1011   ROM_REGION16_BE( 0x800000, "maskrom", 0 )
1012   ROM_LOAD16_BYTE( "mq1-ma0l.bin", 0x000001, 0x100000, CRC(11fed35f) SHA1(511d98b6b42b330238a1874bca031b1892654a48) ) /* 0x400000 */
1013   ROM_LOAD16_BYTE( "mq1-ma0u.bin", 0x000000, 0x100000, CRC(23442ac0) SHA1(fac706f24045d51a2712f51530967140ea8e875f) )
1014   ROM_LOAD16_BYTE( "mq1-ma1l.bin", 0x200001, 0x100000, CRC(fe82205f) SHA1(860cc7a96ae3f848ce594077c1362e4e22a36908) )
1015   ROM_LOAD16_BYTE( "mq1-ma1u.bin", 0x200000, 0x100000, CRC(0cdb6bd0) SHA1(b8b398477c9654e96921110fb30c754240183897) )
10511016
10521017   /* M37702 BIOS - labeled as Namco custom C69 */
10531018   ROM_REGION16_LE( 0x4000, "mcu", 0 )
r29543r29544
10551020ROM_END
10561021
10571022ROM_START( cgangpzl )
1058   ROM_REGION( 0xa80000, "maincpu", 0 )
1059   ROM_LOAD16_BYTE( "cp2-ep0l.bin", 0x080001, 0x80000, CRC(8f5cdcc5) SHA1(925db3f3f16224bc28f97a57aba0ab2b51c5067c) ) /* 0xc00000 */
1060   ROM_LOAD16_BYTE( "cp2-ep0u.bin", 0x080000, 0x80000, CRC(3a816140) SHA1(613c367e08a0a20ec62e1938faab0128743b26f8) )
1023   ROM_REGION( 0x200000, "maincpu", 0 )
1024   ROM_LOAD16_BYTE( "cp2-ep0l.bin", 0x000001, 0x080000, CRC(8f5cdcc5) SHA1(925db3f3f16224bc28f97a57aba0ab2b51c5067c) ) /* 0xc00000 */
1025   ROM_LOAD16_BYTE( "cp2-ep0u.bin", 0x000000, 0x080000, CRC(3a816140) SHA1(613c367e08a0a20ec62e1938faab0128743b26f8) )
10611026
1027   ROM_REGION16_BE( 0x800000, "maskrom", ROMREGION_ERASE00 )
1028   /* no mask roms */
1029
10621030   /* M37702 BIOS - labeled as Namco custom C69 */
10631031   ROM_REGION16_LE( 0x4000, "mcu", 0 )
10641032   ROM_LOAD( "c69.bin",      0x000000, 0x004000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
r29543r29544
10681036ROM_END
10691037
10701038ROM_START( cgangpzlj )
1071   ROM_REGION( 0xa80000, "maincpu", 0 )
1039   ROM_REGION( 0x200000, "maincpu", 0 )
10721040   ROM_LOAD16_BYTE( "cp1-ep0l.bin", 0x080001, 0x80000, CRC(2825f7ba) SHA1(5f6f8df6bdf0f45656904411cdbb31fdcf8f3be0) ) /* 0xc00000 */
10731041   ROM_LOAD16_BYTE( "cp1-ep0u.bin", 0x080000, 0x80000, CRC(94d7d6fc) SHA1(2460741e0dbb2ccff28f4fbc419a7507382467d2) )
10741042
1043   ROM_REGION16_BE( 0x800000, "maskrom", ROMREGION_ERASE00 )
1044   /* no mask roms */
1045
10751046   /* M37702 BIOS - labeled as Namco custom C69 */
10761047   ROM_REGION16_LE( 0x4000, "mcu", 0 )
10771048   ROM_LOAD( "c69.bin",      0x000000, 0x004000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
r29543r29544
10811052ROM_END
10821053
10831054ROM_START( emeraldaj ) /* NA-1 Game PCB, parent is NA-2 version listed below */
1084   ROM_REGION( 0xa80000, "maincpu", 0 )
1085   ROM_LOAD16_BYTE( "em1-ep0lb.bin", 0x080001, 0x080000, CRC(fcd55293) SHA1(fdabf9d5f528c37196ac1e031b097618b4c887b5) ) /* 0xc00000 */
1086   ROM_LOAD16_BYTE( "em1-ep0ub.bin", 0x080000, 0x080000, CRC(a52f00d5) SHA1(85f95d2a69a2df2e9195f55583645c064b0b6fe6) )
1087   ROM_LOAD16_BYTE( "em1-ep1l.bin",  0x180001, 0x080000, CRC(373c1c59) SHA1(385cb3bc056b798878de890dbff97a8bdd48fe4e) )
1088   ROM_LOAD16_BYTE( "em1-ep1u.bin",  0x180000, 0x080000, CRC(4e969152) SHA1(2c89ae5d43585f479f16cf8278f8fc001e077e45) )
1055   ROM_REGION( 0x200000, "maincpu", 0 )
1056   ROM_LOAD16_BYTE( "em1-ep0lb.bin", 0x000001, 0x080000, CRC(fcd55293) SHA1(fdabf9d5f528c37196ac1e031b097618b4c887b5) ) /* 0xc00000 */
1057   ROM_LOAD16_BYTE( "em1-ep0ub.bin", 0x000000, 0x080000, CRC(a52f00d5) SHA1(85f95d2a69a2df2e9195f55583645c064b0b6fe6) )
1058   ROM_LOAD16_BYTE( "em1-ep1l.bin",  0x100001, 0x080000, CRC(373c1c59) SHA1(385cb3bc056b798878de890dbff97a8bdd48fe4e) )
1059   ROM_LOAD16_BYTE( "em1-ep1u.bin",  0x100000, 0x080000, CRC(4e969152) SHA1(2c89ae5d43585f479f16cf8278f8fc001e077e45) )
10891060
1061   ROM_REGION16_BE( 0x800000, "maskrom", ROMREGION_ERASE00 )
1062   /* no mask roms */
1063
10901064   /* M37702 BIOS - labeled as Namco custom C69 */
10911065   ROM_REGION16_LE( 0x4000, "mcu", 0 )
10921066   ROM_LOAD( "c69.bin",      0x000000, 0x004000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
10931067ROM_END
10941068
10951069ROM_START( emeraldaja ) /* NA-1 Game PCB, parent is NA-2 version listed below */
1096   ROM_REGION( 0xa80000, "maincpu", 0 )
1097   ROM_LOAD16_BYTE( "em1-ep0l.bin", 0x080001, 0x080000, CRC(443f3fce) SHA1(35b6c834e5716c1e9b55f1e39f4e7336dbbe2d9b) ) /* 0xc00000 */
1098   ROM_LOAD16_BYTE( "em1-ep0u.bin", 0x080000, 0x080000, CRC(484a2a81) SHA1(1b60c18dfb2aebfd4aa8b2a85a1e90883a1f8e61) )
1099   ROM_LOAD16_BYTE( "em1-ep1l.bin", 0x180001, 0x080000, CRC(373c1c59) SHA1(385cb3bc056b798878de890dbff97a8bdd48fe4e) )
1100   ROM_LOAD16_BYTE( "em1-ep1u.bin", 0x180000, 0x080000, CRC(4e969152) SHA1(2c89ae5d43585f479f16cf8278f8fc001e077e45) )
1070   ROM_REGION( 0x200000, "maincpu", 0 )
1071   ROM_LOAD16_BYTE( "em1-ep0l.bin", 0x000001, 0x080000, CRC(443f3fce) SHA1(35b6c834e5716c1e9b55f1e39f4e7336dbbe2d9b) ) /* 0xc00000 */
1072   ROM_LOAD16_BYTE( "em1-ep0u.bin", 0x000000, 0x080000, CRC(484a2a81) SHA1(1b60c18dfb2aebfd4aa8b2a85a1e90883a1f8e61) )
1073   ROM_LOAD16_BYTE( "em1-ep1l.bin", 0x100001, 0x080000, CRC(373c1c59) SHA1(385cb3bc056b798878de890dbff97a8bdd48fe4e) )
1074   ROM_LOAD16_BYTE( "em1-ep1u.bin", 0x100000, 0x080000, CRC(4e969152) SHA1(2c89ae5d43585f479f16cf8278f8fc001e077e45) )
11011075
1076   ROM_REGION16_BE( 0x800000, "maskrom", ROMREGION_ERASE00 )
1077   /* no mask roms */
1078
11021079   /* M37702 BIOS - labeled as Namco custom C69 */
11031080   ROM_REGION16_LE( 0x4000, "mcu", 0 )
11041081   ROM_LOAD( "c69.bin",      0x000000, 0x004000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
11051082ROM_END
11061083
11071084ROM_START( exvania )
1108   ROM_REGION( 0xa80000, "maincpu", 0 )
1109   ROM_LOAD16_BYTE( "ex2-ep0l.4c", 0x080001, 0x080000, CRC(ccf46677) SHA1(f9d057a7b1c388323d49ef692f41242769f1a08c) ) /* 0xc00000 */
1110   ROM_LOAD16_BYTE( "ex2-ep0u.4f", 0x080000, 0x080000, CRC(37b8d890) SHA1(a0417a1b51d1206bd3eb5e7b58303a9a5691fa43) )
1085   ROM_REGION( 0x200000, "maincpu", 0 )
1086   ROM_LOAD16_BYTE( "ex2-ep0l.4c", 0x000001, 0x080000, CRC(ccf46677) SHA1(f9d057a7b1c388323d49ef692f41242769f1a08c) ) /* 0xc00000 */
1087   ROM_LOAD16_BYTE( "ex2-ep0u.4f", 0x000000, 0x080000, CRC(37b8d890) SHA1(a0417a1b51d1206bd3eb5e7b58303a9a5691fa43) )
11111088
1112   ROM_LOAD16_BYTE( "ex1-ma0l.2c", 0x280001, 0x100000, CRC(17922cd4) SHA1(af92c2335e7110c0c5e712f3148c1534d22d3814) ) /* 0x400000 */
1113   ROM_LOAD16_BYTE( "ex1-ma0u.2f", 0x280000, 0x100000, CRC(93d66106) SHA1(c5d665db04ae0e8992ef46544e2cb7b0e27c8bfe) )
1114   ROM_LOAD16_BYTE( "ex1-ma1l.3c", 0x480001, 0x100000, CRC(e4bba6ed) SHA1(6483ef91e5a5b8ddd13a3d889936c39829fa50d6) )
1115   ROM_LOAD16_BYTE( "ex1-ma1u.3f", 0x480000, 0x100000, CRC(04e7c4b0) SHA1(78180d96cd1fae583617d4d227ed4ee24f2f9e29) )
1089   ROM_REGION16_BE( 0x800000, "maskrom", 0 )
1090   ROM_LOAD16_BYTE( "ex1-ma0l.2c", 0x000001, 0x100000, CRC(17922cd4) SHA1(af92c2335e7110c0c5e712f3148c1534d22d3814) ) /* 0x400000 */
1091   ROM_LOAD16_BYTE( "ex1-ma0u.2f", 0x000000, 0x100000, CRC(93d66106) SHA1(c5d665db04ae0e8992ef46544e2cb7b0e27c8bfe) )
1092   ROM_LOAD16_BYTE( "ex1-ma1l.3c", 0x200001, 0x100000, CRC(e4bba6ed) SHA1(6483ef91e5a5b8ddd13a3d889936c39829fa50d6) )
1093   ROM_LOAD16_BYTE( "ex1-ma1u.3f", 0x200000, 0x100000, CRC(04e7c4b0) SHA1(78180d96cd1fae583617d4d227ed4ee24f2f9e29) )
11161094
11171095   /* M37702 BIOS - labeled as Namco custom C69 */
11181096   ROM_REGION16_LE( 0x4000, "mcu", 0 )
r29543r29544
11231101ROM_END
11241102
11251103ROM_START( exvaniaj )
1126   ROM_REGION( 0xa80000, "maincpu", 0 )
1127   ROM_LOAD16_BYTE( "ex1-ep0l.4c", 0x080001, 0x080000, CRC(18c12015) SHA1(e4f3524e798545c434549719b377c8b5863f580f) ) /* 0xc00000 */
1128   ROM_LOAD16_BYTE( "ex1-ep0u.4f", 0x080000, 0x080000, CRC(07d054d1) SHA1(e2d2cb81acd309c519686572804648bef4cbd191) )
1104   ROM_REGION( 0x200000, "maincpu", 0 )
1105   ROM_LOAD16_BYTE( "ex1-ep0l.4c", 0x000001, 0x080000, CRC(18c12015) SHA1(e4f3524e798545c434549719b377c8b5863f580f) ) /* 0xc00000 */
1106   ROM_LOAD16_BYTE( "ex1-ep0u.4f", 0x000000, 0x080000, CRC(07d054d1) SHA1(e2d2cb81acd309c519686572804648bef4cbd191) )
11291107
1130   ROM_LOAD16_BYTE( "ex1-ma0l.2c", 0x280001, 0x100000, CRC(17922cd4) SHA1(af92c2335e7110c0c5e712f3148c1534d22d3814) ) /* 0x400000 */
1131   ROM_LOAD16_BYTE( "ex1-ma0u.2f", 0x280000, 0x100000, CRC(93d66106) SHA1(c5d665db04ae0e8992ef46544e2cb7b0e27c8bfe) )
1132   ROM_LOAD16_BYTE( "ex1-ma1l.3c", 0x480001, 0x100000, CRC(e4bba6ed) SHA1(6483ef91e5a5b8ddd13a3d889936c39829fa50d6) )
1133   ROM_LOAD16_BYTE( "ex1-ma1u.3f", 0x480000, 0x100000, CRC(04e7c4b0) SHA1(78180d96cd1fae583617d4d227ed4ee24f2f9e29) )
1108   ROM_REGION16_BE( 0x800000, "maskrom", 0 )
1109   ROM_LOAD16_BYTE( "ex1-ma0l.2c", 0x000001, 0x100000, CRC(17922cd4) SHA1(af92c2335e7110c0c5e712f3148c1534d22d3814) ) /* 0x400000 */
1110   ROM_LOAD16_BYTE( "ex1-ma0u.2f", 0x000000, 0x100000, CRC(93d66106) SHA1(c5d665db04ae0e8992ef46544e2cb7b0e27c8bfe) )
1111   ROM_LOAD16_BYTE( "ex1-ma1l.3c", 0x200001, 0x100000, CRC(e4bba6ed) SHA1(6483ef91e5a5b8ddd13a3d889936c39829fa50d6) )
1112   ROM_LOAD16_BYTE( "ex1-ma1u.3f", 0x200000, 0x100000, CRC(04e7c4b0) SHA1(78180d96cd1fae583617d4d227ed4ee24f2f9e29) )
11341113
11351114   /* M37702 BIOS - labeled as Namco custom C69 */
11361115   ROM_REGION16_LE( 0x4000, "mcu", 0 )
r29543r29544
11411120ROM_END
11421121
11431122ROM_START( fghtatck )
1144   ROM_REGION( 0xa80000, "maincpu", 0 )
1145   ROM_LOAD16_BYTE( "fa2-ep0l.bin", 0x080001, 0x080000, CRC(8996db9c) SHA1(ebbe7d4cb2960a346cfbdf38c77638d71b6ba20e) ) /* 0xc00000 */
1146   ROM_LOAD16_BYTE( "fa2-ep0u.bin", 0x080000, 0x080000, CRC(58d5e090) SHA1(950219d4e9bf440f92e3c8765f47e23a9019d2d1) )
1147   ROM_LOAD16_BYTE( "fa1-ep1l.bin", 0x180001, 0x080000, CRC(b23a5b01) SHA1(4ba9bc2102fffc93a5ff73a107d557fc0f3beefd) )
1148   ROM_LOAD16_BYTE( "fa1-ep1u.bin", 0x180000, 0x080000, CRC(de2eb129) SHA1(912993cab1c2edcaf986478f2ae22a2f10edf807) )
1123   ROM_REGION( 0x200000, "maincpu", 0 )
1124   ROM_LOAD16_BYTE( "fa2-ep0l.bin", 0x000001, 0x080000, CRC(8996db9c) SHA1(ebbe7d4cb2960a346cfbdf38c77638d71b6ba20e) ) /* 0xc00000 */
1125   ROM_LOAD16_BYTE( "fa2-ep0u.bin", 0x000000, 0x080000, CRC(58d5e090) SHA1(950219d4e9bf440f92e3c8765f47e23a9019d2d1) )
1126   ROM_LOAD16_BYTE( "fa1-ep1l.bin", 0x100001, 0x080000, CRC(b23a5b01) SHA1(4ba9bc2102fffc93a5ff73a107d557fc0f3beefd) )
1127   ROM_LOAD16_BYTE( "fa1-ep1u.bin", 0x100000, 0x080000, CRC(de2eb129) SHA1(912993cab1c2edcaf986478f2ae22a2f10edf807) )
11491128
1150   ROM_LOAD16_BYTE( "fa1-ma0l.bin", 0x280001, 0x100000, CRC(a0a95e54) SHA1(da35f8a6a5bc9e2b5b6cacf8eb0d900ef1073a67) ) /* 0x400000 */
1151   ROM_LOAD16_BYTE( "fa1-ma0u.bin", 0x280000, 0x100000, CRC(1d0135bd) SHA1(2a7f8d09c213629a68376ce0379be61b37711d0a) )
1152   ROM_LOAD16_BYTE( "fa1-ma1l.bin", 0x480001, 0x100000, CRC(c4adf0a2) SHA1(4cc7adc68b1db7e725a973b31d52720bd7dc1140) )
1153   ROM_LOAD16_BYTE( "fa1-ma1u.bin", 0x480000, 0x100000, CRC(900297be) SHA1(57bb2078ff104c6f631c67219f80f8ede5ddbd09) )
1129   ROM_REGION16_BE( 0x800000, "maskrom", 0 )
1130   ROM_LOAD16_BYTE( "fa1-ma0l.bin", 0x000001, 0x100000, CRC(a0a95e54) SHA1(da35f8a6a5bc9e2b5b6cacf8eb0d900ef1073a67) ) /* 0x400000 */
1131   ROM_LOAD16_BYTE( "fa1-ma0u.bin", 0x000000, 0x100000, CRC(1d0135bd) SHA1(2a7f8d09c213629a68376ce0379be61b37711d0a) )
1132   ROM_LOAD16_BYTE( "fa1-ma1l.bin", 0x200001, 0x100000, CRC(c4adf0a2) SHA1(4cc7adc68b1db7e725a973b31d52720bd7dc1140) )
1133   ROM_LOAD16_BYTE( "fa1-ma1u.bin", 0x200000, 0x100000, CRC(900297be) SHA1(57bb2078ff104c6f631c67219f80f8ede5ddbd09) )
11541134
11551135   /* M37702 BIOS - labeled as Namco custom C69 */
11561136   ROM_REGION16_LE( 0x4000, "mcu", 0 )
r29543r29544
11581138ROM_END
11591139
11601140ROM_START( fa )
1161   ROM_REGION( 0xa80000, "maincpu", 0 )
1162   ROM_LOAD16_BYTE( "fa1-ep0l.bin", 0x080001, 0x080000, CRC(182eee5c) SHA1(49769e3b72b59fc3e7b73364fe97168977dbe66b) ) /* 0xc00000 */
1163   ROM_LOAD16_BYTE( "fa1-ep0u.bin", 0x080000, 0x080000, CRC(7ea7830e) SHA1(79390943eea0b8029b2b8869233caf27228e776a) )
1164   ROM_LOAD16_BYTE( "fa1-ep1l.bin", 0x180001, 0x080000, CRC(b23a5b01) SHA1(4ba9bc2102fffc93a5ff73a107d557fc0f3beefd) )
1165   ROM_LOAD16_BYTE( "fa1-ep1u.bin", 0x180000, 0x080000, CRC(de2eb129) SHA1(912993cab1c2edcaf986478f2ae22a2f10edf807) )
1141   ROM_REGION( 0x200000, "maincpu", 0 )
1142   ROM_LOAD16_BYTE( "fa1-ep0l.bin", 0x000001, 0x080000, CRC(182eee5c) SHA1(49769e3b72b59fc3e7b73364fe97168977dbe66b) ) /* 0xc00000 */
1143   ROM_LOAD16_BYTE( "fa1-ep0u.bin", 0x000000, 0x080000, CRC(7ea7830e) SHA1(79390943eea0b8029b2b8869233caf27228e776a) )
1144   ROM_LOAD16_BYTE( "fa1-ep1l.bin", 0x100001, 0x080000, CRC(b23a5b01) SHA1(4ba9bc2102fffc93a5ff73a107d557fc0f3beefd) )
1145   ROM_LOAD16_BYTE( "fa1-ep1u.bin", 0x100000, 0x080000, CRC(de2eb129) SHA1(912993cab1c2edcaf986478f2ae22a2f10edf807) )
11661146
1167   ROM_LOAD16_BYTE( "fa1-ma0l.bin", 0x280001, 0x100000, CRC(a0a95e54) SHA1(da35f8a6a5bc9e2b5b6cacf8eb0d900ef1073a67) ) /* 0x400000 */
1168   ROM_LOAD16_BYTE( "fa1-ma0u.bin", 0x280000, 0x100000, CRC(1d0135bd) SHA1(2a7f8d09c213629a68376ce0379be61b37711d0a) )
1169   ROM_LOAD16_BYTE( "fa1-ma1l.bin", 0x480001, 0x100000, CRC(c4adf0a2) SHA1(4cc7adc68b1db7e725a973b31d52720bd7dc1140) )
1170   ROM_LOAD16_BYTE( "fa1-ma1u.bin", 0x480000, 0x100000, CRC(900297be) SHA1(57bb2078ff104c6f631c67219f80f8ede5ddbd09) )
1147   ROM_REGION16_BE( 0x800000, "maskrom", 0 )
1148   ROM_LOAD16_BYTE( "fa1-ma0l.bin", 0x000001, 0x100000, CRC(a0a95e54) SHA1(da35f8a6a5bc9e2b5b6cacf8eb0d900ef1073a67) ) /* 0x400000 */
1149   ROM_LOAD16_BYTE( "fa1-ma0u.bin", 0x000000, 0x100000, CRC(1d0135bd) SHA1(2a7f8d09c213629a68376ce0379be61b37711d0a) )
1150   ROM_LOAD16_BYTE( "fa1-ma1l.bin", 0x200001, 0x100000, CRC(c4adf0a2) SHA1(4cc7adc68b1db7e725a973b31d52720bd7dc1140) )
1151   ROM_LOAD16_BYTE( "fa1-ma1u.bin", 0x200000, 0x100000, CRC(900297be) SHA1(57bb2078ff104c6f631c67219f80f8ede5ddbd09) )
11711152
11721153   /* M37702 BIOS - labeled as Namco custom C69 */
11731154   ROM_REGION16_LE( 0x4000, "mcu", 0 )
r29543r29544
11751156ROM_END
11761157
11771158ROM_START( swcourt )
1178   ROM_REGION( 0xa80000, "maincpu", 0 )
1179   ROM_LOAD16_BYTE( "sc2-ep0l.4c",  0x080001, 0x080000, CRC(5053a02e) SHA1(8ab5a085969cef5e01be01d8f531233002ea5bff) ) /* 0xc00000 */
1180   ROM_LOAD16_BYTE( "sc2-ep0u.4f",  0x080000, 0x080000, CRC(7b3fc7fa) SHA1(f96c03a03339b7677b8dc8689d907f2c8895886c) )
1181   ROM_LOAD16_BYTE( "sc1-ep1l.bin", 0x180001, 0x080000, CRC(fb45cf5f) SHA1(6ded351daa9b39d0b8149100caefc4fa0c598e79) )
1182   ROM_LOAD16_BYTE( "sc1-ep1u.bin", 0x180000, 0x080000, CRC(1ce07b15) SHA1(b1b28cc480301c9ad642597c7cdd8e9cdec996a6) )
1159   ROM_REGION( 0x200000, "maincpu", 0 )
1160   ROM_LOAD16_BYTE( "sc2-ep0l.4c",  0x000001, 0x080000, CRC(5053a02e) SHA1(8ab5a085969cef5e01be01d8f531233002ea5bff) ) /* 0xc00000 */
1161   ROM_LOAD16_BYTE( "sc2-ep0u.4f",  0x000000, 0x080000, CRC(7b3fc7fa) SHA1(f96c03a03339b7677b8dc8689d907f2c8895886c) )
1162   ROM_LOAD16_BYTE( "sc1-ep1l.bin", 0x100001, 0x080000, CRC(fb45cf5f) SHA1(6ded351daa9b39d0b8149100caefc4fa0c598e79) )
1163   ROM_LOAD16_BYTE( "sc1-ep1u.bin", 0x100000, 0x080000, CRC(1ce07b15) SHA1(b1b28cc480301c9ad642597c7cdd8e9cdec996a6) )
11831164
1184   ROM_LOAD16_BYTE( "sc1-ma0l.bin", 0x280001, 0x100000, CRC(3e531f5e) SHA1(6da56630bdfbb19f1639c539779c180d106f6ee2) ) /* 0x400000 */
1185   ROM_LOAD16_BYTE( "sc1-ma0u.bin", 0x280000, 0x100000, CRC(31e76a45) SHA1(5c278c167c1025c648ce2da2c3764645e96dcd55) )
1186   ROM_LOAD16_BYTE( "sc1-ma1l.bin", 0x480001, 0x100000, CRC(8ba3a4ec) SHA1(f881e7b4728f388d18450ba85e13e233071fbc88) )
1187   ROM_LOAD16_BYTE( "sc1-ma1u.bin", 0x480000, 0x100000, CRC(252dc4b7) SHA1(f1be6bd045495c7a0ecd97f01d1dc8ad341fecfd) )
1165   ROM_REGION16_BE( 0x800000, "maskrom", 0 )
1166   ROM_LOAD16_BYTE( "sc1-ma0l.bin", 0x000001, 0x100000, CRC(3e531f5e) SHA1(6da56630bdfbb19f1639c539779c180d106f6ee2) ) /* 0x400000 */
1167   ROM_LOAD16_BYTE( "sc1-ma0u.bin", 0x000000, 0x100000, CRC(31e76a45) SHA1(5c278c167c1025c648ce2da2c3764645e96dcd55) )
1168   ROM_LOAD16_BYTE( "sc1-ma1l.bin", 0x200001, 0x100000, CRC(8ba3a4ec) SHA1(f881e7b4728f388d18450ba85e13e233071fbc88) )
1169   ROM_LOAD16_BYTE( "sc1-ma1u.bin", 0x200000, 0x100000, CRC(252dc4b7) SHA1(f1be6bd045495c7a0ecd97f01d1dc8ad341fecfd) )
11881170
11891171   /* M37702 BIOS - labeled as Namco custom C69 */
11901172   ROM_REGION16_LE( 0x4000, "mcu", 0 )
r29543r29544
11921174ROM_END
11931175
11941176ROM_START( swcourtj )
1195   ROM_REGION( 0xa80000, "maincpu", 0 )
1196   ROM_LOAD16_BYTE( "sc1-ep0l.4c",  0x080001, 0x080000, CRC(145111dd) SHA1(f8f74f77fb80af2ea37ea8ddbf02c1f3fcaf3fdb) ) /* 0xc00000 */
1197   ROM_LOAD16_BYTE( "sc1-ep0u.4f",  0x080000, 0x080000, CRC(c721c138) SHA1(5d30d66629d982b54c3bb62118be940dc7b69a6b) )
1198   ROM_LOAD16_BYTE( "sc1-ep1l.bin", 0x180001, 0x080000, CRC(fb45cf5f) SHA1(6ded351daa9b39d0b8149100caefc4fa0c598e79) )
1199   ROM_LOAD16_BYTE( "sc1-ep1u.bin", 0x180000, 0x080000, CRC(1ce07b15) SHA1(b1b28cc480301c9ad642597c7cdd8e9cdec996a6) )
1177   ROM_REGION( 0x200000, "maincpu", 0 )
1178   ROM_LOAD16_BYTE( "sc1-ep0l.4c",  0x000001, 0x080000, CRC(145111dd) SHA1(f8f74f77fb80af2ea37ea8ddbf02c1f3fcaf3fdb) ) /* 0xc00000 */
1179   ROM_LOAD16_BYTE( "sc1-ep0u.4f",  0x000000, 0x080000, CRC(c721c138) SHA1(5d30d66629d982b54c3bb62118be940dc7b69a6b) )
1180   ROM_LOAD16_BYTE( "sc1-ep1l.bin", 0x100001, 0x080000, CRC(fb45cf5f) SHA1(6ded351daa9b39d0b8149100caefc4fa0c598e79) )
1181   ROM_LOAD16_BYTE( "sc1-ep1u.bin", 0x100000, 0x080000, CRC(1ce07b15) SHA1(b1b28cc480301c9ad642597c7cdd8e9cdec996a6) )
12001182
1201   ROM_LOAD16_BYTE( "sc1-ma0l.bin", 0x280001, 0x100000, CRC(3e531f5e) SHA1(6da56630bdfbb19f1639c539779c180d106f6ee2) ) /* 0x400000 */
1202   ROM_LOAD16_BYTE( "sc1-ma0u.bin", 0x280000, 0x100000, CRC(31e76a45) SHA1(5c278c167c1025c648ce2da2c3764645e96dcd55) )
1203   ROM_LOAD16_BYTE( "sc1-ma1l.bin", 0x480001, 0x100000, CRC(8ba3a4ec) SHA1(f881e7b4728f388d18450ba85e13e233071fbc88) )
1204   ROM_LOAD16_BYTE( "sc1-ma1u.bin", 0x480000, 0x100000, CRC(252dc4b7) SHA1(f1be6bd045495c7a0ecd97f01d1dc8ad341fecfd) )
1183   ROM_REGION16_BE( 0x800000, "maskrom", 0 )
1184   ROM_LOAD16_BYTE( "sc1-ma0l.bin", 0x000001, 0x100000, CRC(3e531f5e) SHA1(6da56630bdfbb19f1639c539779c180d106f6ee2) ) /* 0x400000 */
1185   ROM_LOAD16_BYTE( "sc1-ma0u.bin", 0x000000, 0x100000, CRC(31e76a45) SHA1(5c278c167c1025c648ce2da2c3764645e96dcd55) )
1186   ROM_LOAD16_BYTE( "sc1-ma1l.bin", 0x200001, 0x100000, CRC(8ba3a4ec) SHA1(f881e7b4728f388d18450ba85e13e233071fbc88) )
1187   ROM_LOAD16_BYTE( "sc1-ma1u.bin", 0x200000, 0x100000, CRC(252dc4b7) SHA1(f1be6bd045495c7a0ecd97f01d1dc8ad341fecfd) )
12051188
12061189   /* M37702 BIOS - labeled as Namco custom C69 */
12071190   ROM_REGION16_LE( 0x4000, "mcu", 0 )
r29543r29544
12091192ROM_END
12101193
12111194ROM_START( tinklpit )
1212   ROM_REGION( 0xa80000, "maincpu", 0 )
1213   ROM_LOAD16_BYTE( "tk1-ep0l.bin", 0x080001, 0x080000, CRC(fdccae42) SHA1(398384482ccb3eb08bfb9db495513272a5188d92) ) /* 0xc00000 */
1214   ROM_LOAD16_BYTE( "tk1-ep0u.bin", 0x080000, 0x080000, CRC(62cdb48c) SHA1(73c7b99b117b8dc567bc254b0ffcc117c9d42fb5) )
1215   ROM_LOAD16_BYTE( "tk1-ep1l.bin", 0x180001, 0x080000, CRC(7e90f104) SHA1(79e371426b2e32dc8f687e4d124d23c251198937) )
1216   ROM_LOAD16_BYTE( "tk1-ep1u.bin", 0x180000, 0x080000, CRC(9c0b70d6) SHA1(eac44d3470f4c2ddd9c41f82e6398bca0cc8a4fd) )
1195   ROM_REGION( 0x200000, "maincpu", 0 )
1196   ROM_LOAD16_BYTE( "tk1-ep0l.bin", 0x000001, 0x080000, CRC(fdccae42) SHA1(398384482ccb3eb08bfb9db495513272a5188d92) ) /* 0xc00000 */
1197   ROM_LOAD16_BYTE( "tk1-ep0u.bin", 0x000000, 0x080000, CRC(62cdb48c) SHA1(73c7b99b117b8dc567bc254b0ffcc117c9d42fb5) )
1198   ROM_LOAD16_BYTE( "tk1-ep1l.bin", 0x100001, 0x080000, CRC(7e90f104) SHA1(79e371426b2e32dc8f687e4d124d23c251198937) )
1199   ROM_LOAD16_BYTE( "tk1-ep1u.bin", 0x100000, 0x080000, CRC(9c0b70d6) SHA1(eac44d3470f4c2ddd9c41f82e6398bca0cc8a4fd) )
12171200
1218   ROM_LOAD16_BYTE( "tk1-ma0l.bin", 0x280001, 0x100000, CRC(c6b4e15d) SHA1(55252ba4d904b14940436f1b4dc5e2a6bd163bdf) ) /* 0x400000 */
1219   ROM_LOAD16_BYTE( "tk1-ma0u.bin", 0x280000, 0x100000, CRC(a3ad6f67) SHA1(54289eed5347defb5464ec5a610a6748909159f6) )
1220   ROM_LOAD16_BYTE( "tk1-ma1l.bin", 0x480001, 0x100000, CRC(61cfb92a) SHA1(eacf0e7557f33d552045f43a116ff08c533a2771) )
1221   ROM_LOAD16_BYTE( "tk1-ma1u.bin", 0x480000, 0x100000, CRC(54b77816) SHA1(9341d07858623e1920eaae7b2b90126c7057297e) )
1222   ROM_LOAD16_BYTE( "tk1-ma2l.bin", 0x680001, 0x100000, CRC(087311d2) SHA1(6fe50f9e08551e57d15a15b01e3822a6cb7c8352) )
1223   ROM_LOAD16_BYTE( "tk1-ma2u.bin", 0x680000, 0x100000, CRC(5ce20c2c) SHA1(7eaff21714bae44f8b21b6db98f055e04bfbae18) )
1201   ROM_REGION16_BE( 0x800000, "maskrom", 0 )
1202   ROM_LOAD16_BYTE( "tk1-ma0l.bin", 0x000001, 0x100000, CRC(c6b4e15d) SHA1(55252ba4d904b14940436f1b4dc5e2a6bd163bdf) ) /* 0x400000 */
1203   ROM_LOAD16_BYTE( "tk1-ma0u.bin", 0x000000, 0x100000, CRC(a3ad6f67) SHA1(54289eed5347defb5464ec5a610a6748909159f6) )
1204   ROM_LOAD16_BYTE( "tk1-ma1l.bin", 0x200001, 0x100000, CRC(61cfb92a) SHA1(eacf0e7557f33d552045f43a116ff08c533a2771) )
1205   ROM_LOAD16_BYTE( "tk1-ma1u.bin", 0x200000, 0x100000, CRC(54b77816) SHA1(9341d07858623e1920eaae7b2b90126c7057297e) )
1206   ROM_LOAD16_BYTE( "tk1-ma2l.bin", 0x400001, 0x100000, CRC(087311d2) SHA1(6fe50f9e08551e57d15a15b01e3822a6cb7c8352) )
1207   ROM_LOAD16_BYTE( "tk1-ma2u.bin", 0x400000, 0x100000, CRC(5ce20c2c) SHA1(7eaff21714bae44f8b21b6db98f055e04bfbae18) )
12241208
12251209   /* M37702 BIOS - labeled as Namco custom C69 */
12261210   ROM_REGION16_LE( 0x4000, "mcu", 0 )
r29543r29544
12341218
12351219
12361220ROM_START( emeralda ) /* NA-2 Game PCB, clones are NA-1 based; see games listed above */
1237   ROM_REGION( 0xa80000, "maincpu", 0 )
1238   ROM_LOAD16_BYTE( "em2-ep0l.6c", 0x080001, 0x080000, CRC(ff1479dc) SHA1(ea945d97ed909be13fb6e062742c7142c0d96c31) ) /* 0xc00000 */
1239   ROM_LOAD16_BYTE( "em2-ep0u.6f", 0x080000, 0x080000, CRC(ffe750a2) SHA1(d10d31489ae364572d7517dd515a6af2182ac764) )
1240   ROM_LOAD16_BYTE( "em2-ep1l.7c", 0x180001, 0x080000, CRC(6c3e5b53) SHA1(72b941e28c7fda8cb81240a8226386fe55c14e2d) )
1241   ROM_LOAD16_BYTE( "em2-ep1u.7f", 0x180000, 0x080000, CRC(dee15a81) SHA1(474a264029bd77e4205773a7461dea695e65933f) )
1221   ROM_REGION( 0x200000, "maincpu", 0 )
1222   ROM_LOAD16_BYTE( "em2-ep0l.6c", 0x000001, 0x080000, CRC(ff1479dc) SHA1(ea945d97ed909be13fb6e062742c7142c0d96c31) ) /* 0xc00000 */
1223   ROM_LOAD16_BYTE( "em2-ep0u.6f", 0x000000, 0x080000, CRC(ffe750a2) SHA1(d10d31489ae364572d7517dd515a6af2182ac764) )
1224   ROM_LOAD16_BYTE( "em2-ep1l.7c", 0x100001, 0x080000, CRC(6c3e5b53) SHA1(72b941e28c7fda8cb81240a8226386fe55c14e2d) )
1225   ROM_LOAD16_BYTE( "em2-ep1u.7f", 0x100000, 0x080000, CRC(dee15a81) SHA1(474a264029bd77e4205773a7461dea695e65933f) )
12421226
1227   ROM_REGION16_BE( 0x800000, "maskrom", ROMREGION_ERASE00 )
1228   /* no mask roms */
1229
12431230   /* M37702 BIOS - labeled as Namco custom C70 */
12441231   ROM_REGION16_LE( 0x4000, "mcu", 0 )
12451232   ROM_LOAD( "c70.bin",      0x000000, 0x004000, CRC(b4015f23) SHA1(7ce91eda76e86b5cab625e2b67c463b7d143832e) )
12461233ROM_END
12471234
12481235ROM_START( knckhead )
1249   ROM_REGION( 0xa80000, "maincpu", 0 )
1250   ROM_LOAD16_BYTE( "kh2-ep0l.6c", 0x080001, 0x080000, CRC(b4b88077) SHA1(9af03d1832ad6c77222e18427f4afca330a41ce6) ) /* 0xc00000 */
1251   ROM_LOAD16_BYTE( "kh2-ep0u.6f", 0x080000, 0x080000, CRC(a578d97e) SHA1(9a5bb6649cca7b98daf538a66c813f61cca2e2ec) )
1252   ROM_LOAD16_BYTE( "kh1-ep1l.7c", 0x180001, 0x080000, CRC(27e6ab4e) SHA1(66f397cc2117c1e73652c4800c0937e6d8116380) )
1253   ROM_LOAD16_BYTE( "kh1-ep1u.7f", 0x180000, 0x080000, CRC(487b2434) SHA1(2d62db85ceac1fca61c39e4db92c96ae80ba3323) )
1236   ROM_REGION( 0x200000, "maincpu", 0 )
1237   ROM_LOAD16_BYTE( "kh2-ep0l.6c", 0x000001, 0x080000, CRC(b4b88077) SHA1(9af03d1832ad6c77222e18427f4afca330a41ce6) ) /* 0xc00000 */
1238   ROM_LOAD16_BYTE( "kh2-ep0u.6f", 0x000000, 0x080000, CRC(a578d97e) SHA1(9a5bb6649cca7b98daf538a66c813f61cca2e2ec) )
1239   ROM_LOAD16_BYTE( "kh1-ep1l.7c", 0x100001, 0x080000, CRC(27e6ab4e) SHA1(66f397cc2117c1e73652c4800c0937e6d8116380) )
1240   ROM_LOAD16_BYTE( "kh1-ep1u.7f", 0x100000, 0x080000, CRC(487b2434) SHA1(2d62db85ceac1fca61c39e4db92c96ae80ba3323) )
12541241
1255   ROM_LOAD16_BYTE( "kh1-ma0l.2c", 0x280001, 0x100000, CRC(7b2db5df) SHA1(ecc392c4683cf0718d986e73336b69952d324548) ) /* 0x400000 */
1256   ROM_LOAD16_BYTE( "kh1-ma0u.2f", 0x280000, 0x100000, CRC(6983228b) SHA1(5f3eeb780e9d91445b4c11da63d4ca580e654f34) )
1257   ROM_LOAD16_BYTE( "kh1-ma1l.3c", 0x480001, 0x100000, CRC(b24f93e6) SHA1(3d8951485dc8a2810da9ddf2f4896efa31779bf4) )
1258   ROM_LOAD16_BYTE( "kh1-ma1u.3f", 0x480000, 0x100000, CRC(18a60348) SHA1(298e0e0e7649e872791c3c99c81a19f273e9eb8a) )
1259   ROM_LOAD16_BYTE( "kh1-ma2l.4c", 0x680001, 0x100000, CRC(82064ee9) SHA1(0b984565d17e580f49fff982a1621ef90e14c064) )
1260   ROM_LOAD16_BYTE( "kh1-ma2u.4f", 0x680000, 0x100000, CRC(17fe8c3d) SHA1(88c45076477725faa5f8a23512e65a40385bb27d) )
1261   ROM_LOAD16_BYTE( "kh1-ma3l.5c", 0x880001, 0x100000, CRC(ad9a7807) SHA1(c40f18a68306e76acd89ccb3fc82b8106556912e) )
1262   ROM_LOAD16_BYTE( "kh1-ma3u.5f", 0x880000, 0x100000, CRC(efeb768d) SHA1(15d016244549f3ea0d19f5cfb04bcebd65ac6134) )
1242   ROM_REGION16_BE( 0x800000, "maskrom", 0 )
1243   ROM_LOAD16_BYTE( "kh1-ma0l.2c", 0x000001, 0x100000, CRC(7b2db5df) SHA1(ecc392c4683cf0718d986e73336b69952d324548) ) /* 0x400000 */
1244   ROM_LOAD16_BYTE( "kh1-ma0u.2f", 0x000000, 0x100000, CRC(6983228b) SHA1(5f3eeb780e9d91445b4c11da63d4ca580e654f34) )
1245   ROM_LOAD16_BYTE( "kh1-ma1l.3c", 0x200001, 0x100000, CRC(b24f93e6) SHA1(3d8951485dc8a2810da9ddf2f4896efa31779bf4) )
1246   ROM_LOAD16_BYTE( "kh1-ma1u.3f", 0x200000, 0x100000, CRC(18a60348) SHA1(298e0e0e7649e872791c3c99c81a19f273e9eb8a) )
1247   ROM_LOAD16_BYTE( "kh1-ma2l.4c", 0x400001, 0x100000, CRC(82064ee9) SHA1(0b984565d17e580f49fff982a1621ef90e14c064) )
1248   ROM_LOAD16_BYTE( "kh1-ma2u.4f", 0x400000, 0x100000, CRC(17fe8c3d) SHA1(88c45076477725faa5f8a23512e65a40385bb27d) )
1249   ROM_LOAD16_BYTE( "kh1-ma3l.5c", 0x600001, 0x100000, CRC(ad9a7807) SHA1(c40f18a68306e76acd89ccb3fc82b8106556912e) )
1250   ROM_LOAD16_BYTE( "kh1-ma3u.5f", 0x600000, 0x100000, CRC(efeb768d) SHA1(15d016244549f3ea0d19f5cfb04bcebd65ac6134) )
12631251
12641252   /* M37702 BIOS - labeled as Namco custom C70 */
12651253   ROM_REGION16_LE( 0x4000, "mcu", 0 )
r29543r29544
12671255ROM_END
12681256
12691257ROM_START( knckheadj )
1270   ROM_REGION( 0xa80000, "maincpu", 0 )
1271   ROM_LOAD16_BYTE( "kh1-ep0l.6c", 0x080001, 0x080000, CRC(94660bec) SHA1(42fa23f759cf66b05f30c2fc03a12fd14ae1f796) ) /* 0xc00000 */
1272   ROM_LOAD16_BYTE( "kh1-ep0u.6f", 0x080000, 0x080000, CRC(ad640d69) SHA1(62595a9d1d5952cbe3dd7266cfda9292be51d269) )
1273   ROM_LOAD16_BYTE( "kh1-ep1l.7c", 0x180001, 0x080000, CRC(27e6ab4e) SHA1(66f397cc2117c1e73652c4800c0937e6d8116380) )
1274   ROM_LOAD16_BYTE( "kh1-ep1u.7f", 0x180000, 0x080000, CRC(487b2434) SHA1(2d62db85ceac1fca61c39e4db92c96ae80ba3323) )
1258   ROM_REGION( 0x200000, "maincpu", 0 )
1259   ROM_LOAD16_BYTE( "kh1-ep0l.6c", 0x000001, 0x080000, CRC(94660bec) SHA1(42fa23f759cf66b05f30c2fc03a12fd14ae1f796) ) /* 0xc00000 */
1260   ROM_LOAD16_BYTE( "kh1-ep0u.6f", 0x000000, 0x080000, CRC(ad640d69) SHA1(62595a9d1d5952cbe3dd7266cfda9292be51d269) )
1261   ROM_LOAD16_BYTE( "kh1-ep1l.7c", 0x100001, 0x080000, CRC(27e6ab4e) SHA1(66f397cc2117c1e73652c4800c0937e6d8116380) )
1262   ROM_LOAD16_BYTE( "kh1-ep1u.7f", 0x100000, 0x080000, CRC(487b2434) SHA1(2d62db85ceac1fca61c39e4db92c96ae80ba3323) )
12751263
1276   ROM_LOAD16_BYTE( "kh1-ma0l.2c", 0x280001, 0x100000, CRC(7b2db5df) SHA1(ecc392c4683cf0718d986e73336b69952d324548) ) /* 0x400000 */
1277   ROM_LOAD16_BYTE( "kh1-ma0u.2f", 0x280000, 0x100000, CRC(6983228b) SHA1(5f3eeb780e9d91445b4c11da63d4ca580e654f34) )
1278   ROM_LOAD16_BYTE( "kh1-ma1l.3c", 0x480001, 0x100000, CRC(b24f93e6) SHA1(3d8951485dc8a2810da9ddf2f4896efa31779bf4) )
1279   ROM_LOAD16_BYTE( "kh1-ma1u.3f", 0x480000, 0x100000, CRC(18a60348) SHA1(298e0e0e7649e872791c3c99c81a19f273e9eb8a) )
1280   ROM_LOAD16_BYTE( "kh1-ma2l.4c", 0x680001, 0x100000, CRC(82064ee9) SHA1(0b984565d17e580f49fff982a1621ef90e14c064) )
1281   ROM_LOAD16_BYTE( "kh1-ma2u.4f", 0x680000, 0x100000, CRC(17fe8c3d) SHA1(88c45076477725faa5f8a23512e65a40385bb27d) )
1282   ROM_LOAD16_BYTE( "kh1-ma3l.5c", 0x880001, 0x100000, CRC(ad9a7807) SHA1(c40f18a68306e76acd89ccb3fc82b8106556912e) )
1283   ROM_LOAD16_BYTE( "kh1-ma3u.5f", 0x880000, 0x100000, CRC(efeb768d) SHA1(15d016244549f3ea0d19f5cfb04bcebd65ac6134) )
1264   ROM_REGION16_BE( 0x800000, "maskrom", 0 )
1265   ROM_LOAD16_BYTE( "kh1-ma0l.2c", 0x000001, 0x100000, CRC(7b2db5df) SHA1(ecc392c4683cf0718d986e73336b69952d324548) ) /* 0x400000 */
1266   ROM_LOAD16_BYTE( "kh1-ma0u.2f", 0x000000, 0x100000, CRC(6983228b) SHA1(5f3eeb780e9d91445b4c11da63d4ca580e654f34) )
1267   ROM_LOAD16_BYTE( "kh1-ma1l.3c", 0x200001, 0x100000, CRC(b24f93e6) SHA1(3d8951485dc8a2810da9ddf2f4896efa31779bf4) )
1268   ROM_LOAD16_BYTE( "kh1-ma1u.3f", 0x200000, 0x100000, CRC(18a60348) SHA1(298e0e0e7649e872791c3c99c81a19f273e9eb8a) )
1269   ROM_LOAD16_BYTE( "kh1-ma2l.4c", 0x400001, 0x100000, CRC(82064ee9) SHA1(0b984565d17e580f49fff982a1621ef90e14c064) )
1270   ROM_LOAD16_BYTE( "kh1-ma2u.4f", 0x400000, 0x100000, CRC(17fe8c3d) SHA1(88c45076477725faa5f8a23512e65a40385bb27d) )
1271   ROM_LOAD16_BYTE( "kh1-ma3l.5c", 0x600001, 0x100000, CRC(ad9a7807) SHA1(c40f18a68306e76acd89ccb3fc82b8106556912e) )
1272   ROM_LOAD16_BYTE( "kh1-ma3u.5f", 0x600000, 0x100000, CRC(efeb768d) SHA1(15d016244549f3ea0d19f5cfb04bcebd65ac6134) )
12841273
12851274   /* M37702 BIOS - labeled as Namco custom C70 */
12861275   ROM_REGION16_LE( 0x4000, "mcu", 0 )
r29543r29544
12881277ROM_END
12891278
12901279ROM_START( knckheadjp ) /* Older or possible prototype. Doesn't show rom test at boot up */
1291   ROM_REGION( 0xa80000, "maincpu", 0 )
1292   ROM_LOAD16_BYTE( "2-10_9o.6c", 0x080001, 0x080000, CRC(600faf17) SHA1(21197ad1d54a68c1510d9ae6999ca41efaaed05d) ) /* handwritten label 2/10 9O */ /* 0xc00000 */
1293   ROM_LOAD16_BYTE( "2-10_9e.6f", 0x080000, 0x080000, CRC(16ccc0b0) SHA1(e9b98eae7ee47c7cce2cc3de9dc39428e0648a40) ) /* handwritten label 2/10 9E */
1294   ROM_LOAD16_BYTE( "2-10_8o.7c", 0x180001, 0x080000, CRC(27e6ab4e) SHA1(66f397cc2117c1e73652c4800c0937e6d8116380) ) /* handwritten label 2/10 8O */
1295   ROM_LOAD16_BYTE( "2-10_8e.7f", 0x180000, 0x080000, CRC(487b2434) SHA1(2d62db85ceac1fca61c39e4db92c96ae80ba3323) ) /* handwritten label 2/10 8E */
1280   ROM_REGION( 0x200000, "maincpu", 0 )
1281   ROM_LOAD16_BYTE( "2-10_9o.6c", 0x000001, 0x080000, CRC(600faf17) SHA1(21197ad1d54a68c1510d9ae6999ca41efaaed05d) ) /* handwritten label 2/10 9O */ /* 0xc00000 */
1282   ROM_LOAD16_BYTE( "2-10_9e.6f", 0x000000, 0x080000, CRC(16ccc0b0) SHA1(e9b98eae7ee47c7cce2cc3de9dc39428e0648a40) ) /* handwritten label 2/10 9E */
1283   ROM_LOAD16_BYTE( "2-10_8o.7c", 0x100001, 0x080000, CRC(27e6ab4e) SHA1(66f397cc2117c1e73652c4800c0937e6d8116380) ) /* handwritten label 2/10 8O */
1284   ROM_LOAD16_BYTE( "2-10_8e.7f", 0x100000, 0x080000, CRC(487b2434) SHA1(2d62db85ceac1fca61c39e4db92c96ae80ba3323) ) /* handwritten label 2/10 8E */
12961285
1297   ROM_LOAD16_BYTE( "kh1-ma0l.2c", 0x280001, 0x100000, CRC(7b2db5df) SHA1(ecc392c4683cf0718d986e73336b69952d324548) ) /* 0x400000 */
1298   ROM_LOAD16_BYTE( "kh1-ma0u.2f", 0x280000, 0x100000, CRC(6983228b) SHA1(5f3eeb780e9d91445b4c11da63d4ca580e654f34) )
1299   ROM_LOAD16_BYTE( "kh1-ma1l.3c", 0x480001, 0x100000, CRC(b24f93e6) SHA1(3d8951485dc8a2810da9ddf2f4896efa31779bf4) )
1300   ROM_LOAD16_BYTE( "kh1-ma1u.3f", 0x480000, 0x100000, CRC(18a60348) SHA1(298e0e0e7649e872791c3c99c81a19f273e9eb8a) )
1301   ROM_LOAD16_BYTE( "kh1-ma2l.4c", 0x680001, 0x100000, CRC(82064ee9) SHA1(0b984565d17e580f49fff982a1621ef90e14c064) )
1302   ROM_LOAD16_BYTE( "kh1-ma2u.4f", 0x680000, 0x100000, CRC(17fe8c3d) SHA1(88c45076477725faa5f8a23512e65a40385bb27d) )
1303   ROM_LOAD16_BYTE( "kh1-ma3l.5c", 0x880001, 0x100000, CRC(ad9a7807) SHA1(c40f18a68306e76acd89ccb3fc82b8106556912e) )
1304   ROM_LOAD16_BYTE( "kh1-ma3u.5f", 0x880000, 0x100000, CRC(efeb768d) SHA1(15d016244549f3ea0d19f5cfb04bcebd65ac6134) )
1286   ROM_REGION16_BE( 0x800000, "maskrom", 0 )
1287   ROM_LOAD16_BYTE( "kh1-ma0l.2c", 0x000001, 0x100000, CRC(7b2db5df) SHA1(ecc392c4683cf0718d986e73336b69952d324548) ) /* 0x400000 */
1288   ROM_LOAD16_BYTE( "kh1-ma0u.2f", 0x000000, 0x100000, CRC(6983228b) SHA1(5f3eeb780e9d91445b4c11da63d4ca580e654f34) )
1289   ROM_LOAD16_BYTE( "kh1-ma1l.3c", 0x200001, 0x100000, CRC(b24f93e6) SHA1(3d8951485dc8a2810da9ddf2f4896efa31779bf4) )
1290   ROM_LOAD16_BYTE( "kh1-ma1u.3f", 0x200000, 0x100000, CRC(18a60348) SHA1(298e0e0e7649e872791c3c99c81a19f273e9eb8a) )
1291   ROM_LOAD16_BYTE( "kh1-ma2l.4c", 0x400001, 0x100000, CRC(82064ee9) SHA1(0b984565d17e580f49fff982a1621ef90e14c064) )
1292   ROM_LOAD16_BYTE( "kh1-ma2u.4f", 0x400000, 0x100000, CRC(17fe8c3d) SHA1(88c45076477725faa5f8a23512e65a40385bb27d) )
1293   ROM_LOAD16_BYTE( "kh1-ma3l.5c", 0x600001, 0x100000, CRC(ad9a7807) SHA1(c40f18a68306e76acd89ccb3fc82b8106556912e) )
1294   ROM_LOAD16_BYTE( "kh1-ma3u.5f", 0x600000, 0x100000, CRC(efeb768d) SHA1(15d016244549f3ea0d19f5cfb04bcebd65ac6134) )
13051295
13061296   /* M37702 BIOS - labeled as Namco custom C70 */
13071297   ROM_REGION16_LE( 0x4000, "mcu", 0 )
r29543r29544
13121302ROM_END
13131303
13141304ROM_START( numanath )
1315   ROM_REGION( 0xa80000, "maincpu", 0 )
1316   ROM_LOAD16_BYTE( "nm2-ep0l.bin", 0x080001, 0x080000, CRC(f24414bb) SHA1(68b13dfdc2292afd5279edb891fe63972f991e7b) ) /* 0xc00000 */
1317   ROM_LOAD16_BYTE( "nm2-ep0u.bin", 0x080000, 0x080000, CRC(25c41616) SHA1(68ba67d3dd45f3bdddfa2fd21b574535306c1214) )
1318   ROM_LOAD16_BYTE( "nm1-ep1l.bin", 0x180001, 0x080000, CRC(4581dcb4) SHA1(1f46f98e63a7c9cdfde9e8ee2696a13c3f9bcc8e) )
1319   ROM_LOAD16_BYTE( "nm1-ep1u.bin", 0x180000, 0x080000, CRC(30cd589a) SHA1(74a14ec41fe4fc9f73e5357b0903f1199ed96337) )
1305   ROM_REGION( 0x200000, "maincpu", 0 )
1306   ROM_LOAD16_BYTE( "nm2-ep0l.bin", 0x000001, 0x080000, CRC(f24414bb) SHA1(68b13dfdc2292afd5279edb891fe63972f991e7b) ) /* 0xc00000 */
1307   ROM_LOAD16_BYTE( "nm2-ep0u.bin", 0x000000, 0x080000, CRC(25c41616) SHA1(68ba67d3dd45f3bdddfa2fd21b574535306c1214) )
1308   ROM_LOAD16_BYTE( "nm1-ep1l.bin", 0x100001, 0x080000, CRC(4581dcb4) SHA1(1f46f98e63a7c9cdfde9e8ee2696a13c3f9bcc8e) )
1309   ROM_LOAD16_BYTE( "nm1-ep1u.bin", 0x100000, 0x080000, CRC(30cd589a) SHA1(74a14ec41fe4fc9f73e5357b0903f1199ed96337) )
13201310
1321   ROM_LOAD16_BYTE( "nm1-ma0l.bin", 0x280001, 0x100000, CRC(20faaa57) SHA1(9dbfc0dd48eec37b2c0715a5691c6e6f923fc7f7) ) /* 0x400000 */
1322   ROM_LOAD16_BYTE( "nm1-ma0u.bin", 0x280000, 0x100000, CRC(ed7c37f2) SHA1(829751af33754ade941f76982e196b494d56ab0a) )
1323   ROM_LOAD16_BYTE( "nm1-ma1l.bin", 0x480001, 0x100000, CRC(2232e3b4) SHA1(e9da3dc34eb2576c8a88e23cb9007129e885496d) )
1324   ROM_LOAD16_BYTE( "nm1-ma1u.bin", 0x480000, 0x100000, CRC(6cc9675c) SHA1(fec74da4479f2a088760efc6908e6acfaea3989f) )
1325   ROM_LOAD16_BYTE( "nm1-ma2l.bin", 0x680001, 0x100000, CRC(208abb39) SHA1(52d7247a71c6a14467f12f5270921bba1824cc3f) )
1326   ROM_LOAD16_BYTE( "nm1-ma2u.bin", 0x680000, 0x100000, CRC(03a3f204) SHA1(9cb0422c8ecc819d0cc8a65c29a228369d78d986) )
1327   ROM_LOAD16_BYTE( "nm1-ma3l.bin", 0x880001, 0x100000, CRC(42a539e9) SHA1(1c53a5a031648891ab7a37cf026c979404ce9589) )
1328   ROM_LOAD16_BYTE( "nm1-ma3u.bin", 0x880000, 0x100000, CRC(f79e2112) SHA1(8bb8639a9d3a5d3ac5c9bb78e72b3d76582a9c25) )
1311   ROM_REGION16_BE( 0x800000, "maskrom", 0 )
1312   ROM_LOAD16_BYTE( "nm1-ma0l.bin", 0x000001, 0x100000, CRC(20faaa57) SHA1(9dbfc0dd48eec37b2c0715a5691c6e6f923fc7f7) ) /* 0x400000 */
1313   ROM_LOAD16_BYTE( "nm1-ma0u.bin", 0x000000, 0x100000, CRC(ed7c37f2) SHA1(829751af33754ade941f76982e196b494d56ab0a) )
1314   ROM_LOAD16_BYTE( "nm1-ma1l.bin", 0x200001, 0x100000, CRC(2232e3b4) SHA1(e9da3dc34eb2576c8a88e23cb9007129e885496d) )
1315   ROM_LOAD16_BYTE( "nm1-ma1u.bin", 0x200000, 0x100000, CRC(6cc9675c) SHA1(fec74da4479f2a088760efc6908e6acfaea3989f) )
1316   ROM_LOAD16_BYTE( "nm1-ma2l.bin", 0x400001, 0x100000, CRC(208abb39) SHA1(52d7247a71c6a14467f12f5270921bba1824cc3f) )
1317   ROM_LOAD16_BYTE( "nm1-ma2u.bin", 0x400000, 0x100000, CRC(03a3f204) SHA1(9cb0422c8ecc819d0cc8a65c29a228369d78d986) )
1318   ROM_LOAD16_BYTE( "nm1-ma3l.bin", 0x600001, 0x100000, CRC(42a539e9) SHA1(1c53a5a031648891ab7a37cf026c979404ce9589) )
1319   ROM_LOAD16_BYTE( "nm1-ma3u.bin", 0x600000, 0x100000, CRC(f79e2112) SHA1(8bb8639a9d3a5d3ac5c9bb78e72b3d76582a9c25) )
13291320
13301321   /* M37702 BIOS - labeled as Namco custom C70 */
13311322   ROM_REGION16_LE( 0x4000, "mcu", 0 )
r29543r29544
13331324ROM_END
13341325
13351326ROM_START( numanathj )
1336   ROM_REGION( 0xa80000, "maincpu", 0 )
1337   ROM_LOAD16_BYTE( "nm1-ep0l.bin", 0x080001, 0x080000, CRC(4398b898) SHA1(0d1517409ba181f796f7f413cac704c60085b505) ) /* 0xc00000 */
1338   ROM_LOAD16_BYTE( "nm1-ep0u.bin", 0x080000, 0x080000, CRC(be90aa79) SHA1(6884a8d72dd34c889527e8e653f5e5b4cf3fb5d6) )
1339   ROM_LOAD16_BYTE( "nm1-ep1l.bin", 0x180001, 0x080000, CRC(4581dcb4) SHA1(1f46f98e63a7c9cdfde9e8ee2696a13c3f9bcc8e) )
1340   ROM_LOAD16_BYTE( "nm1-ep1u.bin", 0x180000, 0x080000, CRC(30cd589a) SHA1(74a14ec41fe4fc9f73e5357b0903f1199ed96337) )
1327   ROM_REGION( 0x200000, "maincpu", 0 )
1328   ROM_LOAD16_BYTE( "nm1-ep0l.bin", 0x000001, 0x080000, CRC(4398b898) SHA1(0d1517409ba181f796f7f413cac704c60085b505) ) /* 0xc00000 */
1329   ROM_LOAD16_BYTE( "nm1-ep0u.bin", 0x000000, 0x080000, CRC(be90aa79) SHA1(6884a8d72dd34c889527e8e653f5e5b4cf3fb5d6) )
1330   ROM_LOAD16_BYTE( "nm1-ep1l.bin", 0x100001, 0x080000, CRC(4581dcb4) SHA1(1f46f98e63a7c9cdfde9e8ee2696a13c3f9bcc8e) )
1331   ROM_LOAD16_BYTE( "nm1-ep1u.bin", 0x100000, 0x080000, CRC(30cd589a) SHA1(74a14ec41fe4fc9f73e5357b0903f1199ed96337) )
13411332
1342   ROM_LOAD16_BYTE( "nm1-ma0l.bin", 0x280001, 0x100000, CRC(20faaa57) SHA1(9dbfc0dd48eec37b2c0715a5691c6e6f923fc7f7) ) /* 0x400000 */
1343   ROM_LOAD16_BYTE( "nm1-ma0u.bin", 0x280000, 0x100000, CRC(ed7c37f2) SHA1(829751af33754ade941f76982e196b494d56ab0a) )
1344   ROM_LOAD16_BYTE( "nm1-ma1l.bin", 0x480001, 0x100000, CRC(2232e3b4) SHA1(e9da3dc34eb2576c8a88e23cb9007129e885496d) )
1345   ROM_LOAD16_BYTE( "nm1-ma1u.bin", 0x480000, 0x100000, CRC(6cc9675c) SHA1(fec74da4479f2a088760efc6908e6acfaea3989f) )
1346   ROM_LOAD16_BYTE( "nm1-ma2l.bin", 0x680001, 0x100000, CRC(208abb39) SHA1(52d7247a71c6a14467f12f5270921bba1824cc3f) )
1347   ROM_LOAD16_BYTE( "nm1-ma2u.bin", 0x680000, 0x100000, CRC(03a3f204) SHA1(9cb0422c8ecc819d0cc8a65c29a228369d78d986) )
1348   ROM_LOAD16_BYTE( "nm1-ma3l.bin", 0x880001, 0x100000, CRC(42a539e9) SHA1(1c53a5a031648891ab7a37cf026c979404ce9589) )
1349   ROM_LOAD16_BYTE( "nm1-ma3u.bin", 0x880000, 0x100000, CRC(f79e2112) SHA1(8bb8639a9d3a5d3ac5c9bb78e72b3d76582a9c25) )
1333   ROM_REGION16_BE( 0x800000, "maskrom", 0 )
1334   ROM_LOAD16_BYTE( "nm1-ma0l.bin", 0x000001, 0x100000, CRC(20faaa57) SHA1(9dbfc0dd48eec37b2c0715a5691c6e6f923fc7f7) ) /* 0x400000 */
1335   ROM_LOAD16_BYTE( "nm1-ma0u.bin", 0x000000, 0x100000, CRC(ed7c37f2) SHA1(829751af33754ade941f76982e196b494d56ab0a) )
1336   ROM_LOAD16_BYTE( "nm1-ma1l.bin", 0x200001, 0x100000, CRC(2232e3b4) SHA1(e9da3dc34eb2576c8a88e23cb9007129e885496d) )
1337   ROM_LOAD16_BYTE( "nm1-ma1u.bin", 0x200000, 0x100000, CRC(6cc9675c) SHA1(fec74da4479f2a088760efc6908e6acfaea3989f) )
1338   ROM_LOAD16_BYTE( "nm1-ma2l.bin", 0x400001, 0x100000, CRC(208abb39) SHA1(52d7247a71c6a14467f12f5270921bba1824cc3f) )
1339   ROM_LOAD16_BYTE( "nm1-ma2u.bin", 0x400000, 0x100000, CRC(03a3f204) SHA1(9cb0422c8ecc819d0cc8a65c29a228369d78d986) )
1340   ROM_LOAD16_BYTE( "nm1-ma3l.bin", 0x600001, 0x100000, CRC(42a539e9) SHA1(1c53a5a031648891ab7a37cf026c979404ce9589) )
1341   ROM_LOAD16_BYTE( "nm1-ma3u.bin", 0x600000, 0x100000, CRC(f79e2112) SHA1(8bb8639a9d3a5d3ac5c9bb78e72b3d76582a9c25) )
13501342
13511343   /* M37702 BIOS - labeled as Namco custom C70 */
13521344   ROM_REGION16_LE( 0x4000, "mcu", 0 )
r29543r29544
13541346ROM_END
13551347
13561348ROM_START( quiztou )
1357   ROM_REGION( 0xa80000, "maincpu", 0 )
1358   ROM_LOAD16_BYTE( "qt1ep0l.6c", 0x080001, 0x080000, CRC(b680e543) SHA1(f10f38113a46c821d8e9d66f52d7311d9d52e595) ) /* 0xc00000 */
1359   ROM_LOAD16_BYTE( "qt1ep0u.6f", 0x080000, 0x080000, CRC(143c5e4d) SHA1(24c584986c97a5e6fe7e73f0e9af4af28ed20c4a) )
1360   ROM_LOAD16_BYTE( "qt1ep1l.7c", 0x180001, 0x080000, CRC(33a72242) SHA1(5d17f033878d28dbebba50931a549ccf84802c05) )
1361   ROM_LOAD16_BYTE( "qt1ep1u.7f", 0x180000, 0x080000, CRC(69f876cb) SHA1(d0c7e972a04c45d3ab34ef5be88614d6389189c6) )
1349   ROM_REGION( 0x200000, "maincpu", 0 )
1350   ROM_LOAD16_BYTE( "qt1ep0l.6c", 0x000001, 0x080000, CRC(b680e543) SHA1(f10f38113a46c821d8e9d66f52d7311d9d52e595) ) /* 0xc00000 */
1351   ROM_LOAD16_BYTE( "qt1ep0u.6f", 0x000000, 0x080000, CRC(143c5e4d) SHA1(24c584986c97a5e6fe7e73f0e9af4af28ed20c4a) )
1352   ROM_LOAD16_BYTE( "qt1ep1l.7c", 0x100001, 0x080000, CRC(33a72242) SHA1(5d17f033878d28dbebba50931a549ccf84802c05) )
1353   ROM_LOAD16_BYTE( "qt1ep1u.7f", 0x100000, 0x080000, CRC(69f876cb) SHA1(d0c7e972a04c45d3ab34ef5be88614d6389189c6) )
13621354
1363   ROM_LOAD16_BYTE( "qt1ma0l.2c", 0x280001, 0x100000, CRC(5597f2b9) SHA1(747c4be867d4eb37ffab8303740729686a00b825) ) /* 0x400000 */
1364   ROM_LOAD16_BYTE( "qt1ma0u.2f", 0x280000, 0x100000, CRC(f0a4cb7d) SHA1(364e85af956e7cfc29c957da11574a4b389f7797) )
1365   ROM_LOAD16_BYTE( "qt1ma1l.3c", 0x480001, 0x100000, CRC(1b9ce7a6) SHA1(dac1da9dd8076f238211fed5c780b4b8bededf22) )
1366   ROM_LOAD16_BYTE( "qt1ma1u.3f", 0x480000, 0x100000, CRC(58910872) SHA1(c0acbd64e90672564c3839fd21870672aa32e439) )
1367   ROM_LOAD16_BYTE( "qt1ma2l.4c", 0x680001, 0x100000, CRC(94739917) SHA1(b5be5c9fd7223d3fb601f769cb80f56a5a586de0) )
1368   ROM_LOAD16_BYTE( "qt1ma2u.4f", 0x680000, 0x100000, CRC(6ba5b893) SHA1(071caed9cf261f1f8af7079875bd206177baef1a) )
1369   ROM_LOAD16_BYTE( "qt1ma3l.5c", 0x880001, 0x100000, CRC(aa9dc6ff) SHA1(c738f8c59bb5245874576c5bcf88c7138fa9a147) )
1370   ROM_LOAD16_BYTE( "qt1ma3u.5f", 0x880000, 0x100000, CRC(14a5a163) SHA1(1107f50e491bedeb4ab7ac3f32cfe47727274ba9) )
1355   ROM_REGION16_BE( 0x800000, "maskrom", 0 )
1356   ROM_LOAD16_BYTE( "qt1ma0l.2c", 0x000001, 0x100000, CRC(5597f2b9) SHA1(747c4be867d4eb37ffab8303740729686a00b825) ) /* 0x400000 */
1357   ROM_LOAD16_BYTE( "qt1ma0u.2f", 0x000000, 0x100000, CRC(f0a4cb7d) SHA1(364e85af956e7cfc29c957da11574a4b389f7797) )
1358   ROM_LOAD16_BYTE( "qt1ma1l.3c", 0x200001, 0x100000, CRC(1b9ce7a6) SHA1(dac1da9dd8076f238211fed5c780b4b8bededf22) )
1359   ROM_LOAD16_BYTE( "qt1ma1u.3f", 0x200000, 0x100000, CRC(58910872) SHA1(c0acbd64e90672564c3839fd21870672aa32e439) )
1360   ROM_LOAD16_BYTE( "qt1ma2l.4c", 0x400001, 0x100000, CRC(94739917) SHA1(b5be5c9fd7223d3fb601f769cb80f56a5a586de0) )
1361   ROM_LOAD16_BYTE( "qt1ma2u.4f", 0x400000, 0x100000, CRC(6ba5b893) SHA1(071caed9cf261f1f8af7079875bd206177baef1a) )
1362   ROM_LOAD16_BYTE( "qt1ma3l.5c", 0x600001, 0x100000, CRC(aa9dc6ff) SHA1(c738f8c59bb5245874576c5bcf88c7138fa9a147) )
1363   ROM_LOAD16_BYTE( "qt1ma3u.5f", 0x600000, 0x100000, CRC(14a5a163) SHA1(1107f50e491bedeb4ab7ac3f32cfe47727274ba9) )
13711364
13721365   /* M37702 BIOS - labeled as Namco custom C70 */
13731366   ROM_REGION16_LE( 0x4000, "mcu", 0 )
r29543r29544
13781371ROM_END
13791372
13801373ROM_START( xday2 )
1381   ROM_REGION( 0xa80000, "maincpu", 0 )
1382   ROM_LOAD16_BYTE( "xds1-mpr0.4b", 0x080001, 0x080000, CRC(83539aaa) SHA1(42d97bb2daaf5ff48efac70f0ff37869c5ba177d) ) /* 0xc00000 */
1383   ROM_LOAD16_BYTE( "xds1-mpr1.8b", 0x080000, 0x080000, CRC(468b36de) SHA1(52817be9913a6938ce6add2834ba1a727b1d677e) )
1374   ROM_REGION( 0x200000, "maincpu", 0 )
1375   ROM_LOAD16_BYTE( "xds1-mpr0.4b", 0x000001, 0x080000, CRC(83539aaa) SHA1(42d97bb2daaf5ff48efac70f0ff37869c5ba177d) ) /* 0xc00000 */
1376   ROM_LOAD16_BYTE( "xds1-mpr1.8b", 0x000000, 0x080000, CRC(468b36de) SHA1(52817be9913a6938ce6add2834ba1a727b1d677e) )
13841377
1385   ROM_LOAD16_BYTE( "xds1-dat0.4b", 0x280001, 0x200000, CRC(42cecc8b) SHA1(7510f16b908dd0f7828887dcfa26c5e4643df66c) ) /* 0x400000 */
1386   ROM_LOAD16_BYTE( "xds1-dat1.8b", 0x280000, 0x200000, CRC(d250b7e8) SHA1(b99251ae8e25fae062d33e74ff800ab43fb308a2) )
1387   ROM_LOAD16_BYTE( "xds1-dat2.4c", 0x680001, 0x200000, CRC(99d72a08) SHA1(4615b43b9a81240ffee8b0f021037f554f4f1f24) )
1388   ROM_LOAD16_BYTE( "xds1-dat3.8c", 0x680000, 0x200000, CRC(8980acc4) SHA1(ecd94a3d3a38923e8e322cd8863671af26e30812) )
1378   ROM_REGION16_BE( 0x800000, "maskrom", 0 )
1379   ROM_LOAD16_BYTE( "xds1-dat0.4b", 0x000001, 0x200000, CRC(42cecc8b) SHA1(7510f16b908dd0f7828887dcfa26c5e4643df66c) ) /* 0x400000 */
1380   ROM_LOAD16_BYTE( "xds1-dat1.8b", 0x000000, 0x200000, CRC(d250b7e8) SHA1(b99251ae8e25fae062d33e74ff800ab43fb308a2) )
1381   ROM_LOAD16_BYTE( "xds1-dat2.4c", 0x400001, 0x200000, CRC(99d72a08) SHA1(4615b43b9a81240ffee8b0f021037f554f4f1f24) )
1382   ROM_LOAD16_BYTE( "xds1-dat3.8c", 0x400000, 0x200000, CRC(8980acc4) SHA1(ecd94a3d3a38923e8e322cd8863671af26e30812) )
13891383
13901384   /* M37702 BIOS - labeled as Namco custom C70 */
13911385   ROM_REGION16_LE( 0x4000, "mcu", 0 )
branches/new_menus/src/mame/drivers/uapce.c
r29543r29544
300300   AM_RANGE( 0x00, 0x03) AM_DEVREADWRITE( "huc6270", huc6270_device, read, write )
301301ADDRESS_MAP_END
302302
303static const c6280_interface c6280_config =
304{
305   "maincpu"
306};
307
308303WRITE_LINE_MEMBER(uapce_state::pce_irq_changed)
309304{
310305   m_maincpu->set_input_line(0, state);
r29543r29544
339334
340335   MCFG_SPEAKER_STANDARD_STEREO("lspeaker","rspeaker")
341336   MCFG_SOUND_ADD("c6280", C6280, PCE_MAIN_CLOCK/6)
342   MCFG_SOUND_CONFIG(c6280_config)
337   MCFG_C6280_CPU("maincpu")
343338   MCFG_SOUND_ROUTE(0, "lspeaker", 0.5)
344339   MCFG_SOUND_ROUTE(1, "rspeaker", 0.5)
345340
branches/new_menus/src/mame/drivers/20pacgal.c
r29543r29544
121121
122122/*************************************
123123 *
124 *  Audio
125 *
126 *************************************/
127
128static const namco_interface namco_config =
129{
130   3,      /* number of voices */
131   0       /* stereo */
132};
133
134
135
136/*************************************
137 *
138124 *  Coin counter
139125 *
140126 *************************************/
r29543r29544
408394   MCFG_SPEAKER_STANDARD_MONO("mono")
409395
410396   MCFG_SOUND_ADD("namco", NAMCO_CUS30, NAMCO_AUDIO_CLOCK)
411   MCFG_SOUND_CONFIG(namco_config)
397   MCFG_NAMCO_AUDIO_VOICES(3)
412398   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
413399
414400   MCFG_DAC_ADD("dac")
branches/new_menus/src/mame/drivers/paranoia.c
r29543r29544
169169   DEVCB_DRIVER_LINE_MEMBER(paranoia_state,paranoia_i8155_timer_out)
170170};
171171
172static const c6280_interface c6280_config =
173{
174   "maincpu"
175};
176
177172static MACHINE_CONFIG_START( paranoia, paranoia_state )
178173   /* basic machine hardware */
179174   MCFG_CPU_ADD("maincpu", H6280, PCE_MAIN_CLOCK/3)
r29543r29544
208203
209204   MCFG_SPEAKER_STANDARD_STEREO("lspeaker","rspeaker")
210205   MCFG_SOUND_ADD("c6280", C6280, PCE_MAIN_CLOCK/6)
211   MCFG_SOUND_CONFIG(c6280_config)
206   MCFG_C6280_CPU("maincpu")
212207   MCFG_SOUND_ROUTE(0, "lspeaker", 1.00)
213208   MCFG_SOUND_ROUTE(1, "rspeaker", 1.00)
214209
branches/new_menus/src/mame/drivers/segaxbd.c
r29543r29544
15031503
15041504
15051505//**************************************************************************
1506//  SOUND DEFINITIONS
1507//**************************************************************************
1508
1509static const sega_pcm_interface segapcm_interface =
1510{
1511   BANK_512
1512};
1513
1514
1515
1516//**************************************************************************
15171506//  GRAPHICS DEFINITIONS
15181507//**************************************************************************
15191508
r29543r29544
15781567   MCFG_SOUND_ROUTE(1, "rspeaker", 0.43)
15791568
15801569   MCFG_SEGAPCM_ADD("pcm", SOUND_CLOCK/4)
1581   MCFG_SOUND_CONFIG(segapcm_interface)
1570   MCFG_SEGAPCM_BANK(BANK_512)
15821571   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
15831572   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
15841573MACHINE_CONFIG_END
r29543r29544
16251614   MCFG_SPEAKER_STANDARD_STEREO("rearleft", "rearright")
16261615
16271616   MCFG_SEGAPCM_ADD("pcm2", SOUND_CLOCK/4)
1628   MCFG_SOUND_CONFIG(segapcm_interface)
1617   MCFG_SEGAPCM_BANK(BANK_512)
16291618   MCFG_SOUND_ROUTE(0, "rearleft", 1.0)
16301619   MCFG_SOUND_ROUTE(1, "rearright", 1.0)
16311620MACHINE_CONFIG_END
branches/new_menus/src/mame/drivers/seta2.c
r29543r29544
20652065   m_tmp68301->external_interrupt_2();   // to do: hook up x1-10 interrupts
20662066}
20672067
2068static const x1_010_interface x1_010_sound_intf =
2069{
2070   0x0000,     /* address */
2071};
2072
2073
20742068static MACHINE_CONFIG_START( seta2, seta2_state )
20752069   MCFG_CPU_ADD("maincpu", M68301, XTAL_50MHz/3)   // !! TMP68301 !!
20762070   MCFG_CPU_PROGRAM_MAP(mj4simai_map)
r29543r29544
20982092   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
20992093
21002094   MCFG_SOUND_ADD("x1snd", X1_010, XTAL_50MHz/3)   // clock?
2101   MCFG_SOUND_CONFIG(x1_010_sound_intf)
21022095   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
21032096   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
21042097MACHINE_CONFIG_END
branches/new_menus/src/mame/drivers/galaga.c
r29543r29544
15741574/* The resistance path of the namco sound is 16k compared to
15751575 * the 10k of the highest gain 54xx filter. Giving a 10/16 gain.
15761576 */
1577static const namco_interface namco_config =
1578{
1579   3,              /* number of voices */
1580   0               /* stereo */
1581};
15821577
15831578static const char *const battles_sample_names[] =
15841579{
r29543r29544
16821677   MCFG_SPEAKER_STANDARD_MONO("mono")
16831678
16841679   MCFG_SOUND_ADD("namco", NAMCO, MASTER_CLOCK/6/32)
1685   MCFG_SOUND_CONFIG(namco_config)
1680   MCFG_NAMCO_AUDIO_VOICES(3)
16861681   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90 * 10.0 / 16.0)
16871682
16881683   /* discrete circuit on the 54XX outputs */
r29543r29544
17461741   MCFG_SPEAKER_STANDARD_MONO("mono")
17471742
17481743   MCFG_SOUND_ADD("namco", NAMCO, MASTER_CLOCK/6/32)
1749   MCFG_SOUND_CONFIG(namco_config)
1744   MCFG_NAMCO_AUDIO_VOICES(3)
17501745   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90 * 10.0 / 16.0)
17511746
17521747   /* discrete circuit on the 54XX outputs */
r29543r29544
18341829   MCFG_SPEAKER_STANDARD_MONO("mono")
18351830
18361831   MCFG_SOUND_ADD("namco", NAMCO, MASTER_CLOCK/6/32)
1837   MCFG_SOUND_CONFIG(namco_config)
1832   MCFG_NAMCO_AUDIO_VOICES(3)
18381833   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90 * 10.0 / 16.0)
18391834
18401835   /* discrete circuit on the 54XX outputs */
r29543r29544
19351930   MCFG_SPEAKER_STANDARD_MONO("mono")
19361931
19371932   MCFG_SOUND_ADD("namco", NAMCO, MASTER_CLOCK/6/32)
1938   MCFG_SOUND_CONFIG(namco_config)
1933   MCFG_NAMCO_AUDIO_VOICES(3)
19391934   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90 * 10.0 / 16.0)
19401935MACHINE_CONFIG_END
19411936
branches/new_menus/src/mame/drivers/segaybd.c
r29543r29544
11381138INPUT_PORTS_END
11391139
11401140
1141
11421141//**************************************************************************
1143//  SOUND DEFINITIONS
1144//**************************************************************************
1145
1146static const sega_pcm_interface segapcm_interface =
1147{
1148   BANK_12M | BANK_MASKF8
1149};
1150
1151
1152
1153//**************************************************************************
11541142//  GENERIC MACHINE DRIVERS
11551143//**************************************************************************
11561144
r29543r29544
12061194   MCFG_SOUND_ROUTE(1, "rspeaker", 0.43)
12071195
12081196   MCFG_SEGAPCM_ADD("pcm", SOUND_CLOCK/8)
1209   MCFG_SOUND_CONFIG(segapcm_interface)
1197   MCFG_SEGAPCM_BANK(BANK_12M | BANK_MASKF8)
12101198   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
12111199   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
12121200MACHINE_CONFIG_END
branches/new_menus/src/mame/drivers/bladestl.c
r29543r29544
7676   /* bit 4 = relay (???) */
7777
7878   /* bits 5-6 = bank number */
79   membank("bank1")->set_entry((data & 0x60) >> 5);
79   m_rombank->set_entry((data & 0x60) >> 5);
8080
8181   /* bit 7 = select sprite bank */
8282   m_spritebank = (data & 0x80) << 3;
r29543r29544
131131   AM_RANGE(0x2f80, 0x2f9f) AM_DEVREADWRITE("k051733", k051733_device, read, write)    /* Protection: 051733 */
132132   AM_RANGE(0x2fc0, 0x2fc0) AM_WRITENOP                        /* ??? */
133133   AM_RANGE(0x4000, 0x5fff) AM_RAM                             /* Work RAM */
134   AM_RANGE(0x6000, 0x7fff) AM_ROMBANK("bank1")                        /* banked ROM */
134   AM_RANGE(0x6000, 0x7fff) AM_ROMBANK("rombank")              /* banked ROM */
135135   AM_RANGE(0x8000, 0xffff) AM_ROM
136136ADDRESS_MAP_END
137137
r29543r29544
258258};
259259
260260static GFXDECODE_START( bladestl )
261   GFXDECODE_ENTRY( "gfx1", 0x000000, charlayout,     0,   2 ) /* colors 00..31 */
262   GFXDECODE_ENTRY( "gfx1", 0x040000, spritelayout,   32,  16 )    /* colors 32..47 but using lookup table */
261   GFXDECODE_ENTRY( "gfx1", 0, charlayout,    0,  2 ) /* colors 00..31 */
262   GFXDECODE_ENTRY( "gfx2", 0, spritelayout, 32, 16 ) /* colors 32..47 but using lookup table */
263263GFXDECODE_END
264264
265265
r29543r29544
282282
283283void bladestl_state::machine_start()
284284{
285   UINT8 *ROM = memregion("maincpu")->base();
285   m_rombank->configure_entries(0, 4, memregion("maincpu")->base(), 0x2000);
286286
287   membank("bank1")->configure_entries(0, 4, &ROM[0x10000], 0x2000);
288
289287   save_item(NAME(m_spritebank));
290288   save_item(NAME(m_layer_colorbase));
291289   save_item(NAME(m_last_track));
r29543r29544
363361 *************************************/
364362
365363ROM_START( bladestl )
366   ROM_REGION( 0x18000, "maincpu", 0 ) /* code + banked roms */
367   ROM_LOAD( "797-t01.19c", 0x10000, 0x08000, CRC(89d7185d) SHA1(0d2f346d9515cab0389106c0e227fb0bd84a2c9c) )   /* fixed ROM */
368   ROM_CONTINUE(            0x08000, 0x08000 )             /* banked ROM */
364   ROM_REGION( 0x10000, "maincpu", 0 ) /* code + banked roms */
365   ROM_LOAD( "797-t01.19c", 0x00000, 0x10000, CRC(89d7185d) SHA1(0d2f346d9515cab0389106c0e227fb0bd84a2c9c) )
369366
370367   ROM_REGION( 0x10000, "audiocpu", 0 ) /* 64k for the sound CPU */
371368   ROM_LOAD( "797-c02.12d", 0x08000, 0x08000, CRC(65a331ea) SHA1(f206f6c5f0474542a5b7686b2f4d2cc7077dd5b9) )
372369
373   ROM_REGION( 0x080000, "gfx1", 0 )
374   ROM_LOAD( "797a05.19h", 0x000000, 0x40000, CRC(5491ba28) SHA1(c807774827c55c211ab68f548e1e835289cc5744) )   /* tiles */
375   ROM_LOAD( "797a06.13h", 0x040000, 0x40000, CRC(d055f5cc) SHA1(3723b39b2a3e6dd8e7fc66bbfe1eef9f80818774) )   /* sprites */
370   ROM_REGION( 0x40000, "gfx1", 0 )
371   ROM_LOAD( "797a05.19h", 0x00000, 0x40000, CRC(5491ba28) SHA1(c807774827c55c211ab68f548e1e835289cc5744) )   /* tiles */
376372
373   ROM_REGION( 0x40000, "gfx2", 0 )
374   ROM_LOAD( "797a06.13h", 0x00000, 0x40000, CRC(d055f5cc) SHA1(3723b39b2a3e6dd8e7fc66bbfe1eef9f80818774) )   /* sprites */
375
377376   ROM_REGION( 0x0100, "proms", 0 )
378377   ROM_LOAD( "797a07.16i", 0x0000, 0x0100, CRC(7aecad4e) SHA1(05150a8dd25bdd6ab0c5b350e6ffd272f040e46a) ) /* sprites lookup table, 63S141N BPROM */
379378
r29543r29544
383382ROM_END
384383
385384ROM_START( bladestll )
386   ROM_REGION( 0x18000, "maincpu", 0 ) /* code + banked roms */
387   ROM_LOAD( "797-l01.19c", 0x10000, 0x08000, CRC(1ab14c40) SHA1(c566e31a666b467d75f5fc9fa427986c3ebc705c) )   /* fixed ROM */
388   ROM_CONTINUE(            0x08000, 0x08000 )             /* banked ROM */
385   ROM_REGION( 0x10000, "maincpu", 0 ) /* code + banked roms */
386   ROM_LOAD( "797-l01.19c", 0x00000, 0x10000, CRC(1ab14c40) SHA1(c566e31a666b467d75f5fc9fa427986c3ebc705c) )
389387
390388   ROM_REGION( 0x10000, "audiocpu", 0 ) /* 64k for the sound CPU */
391389   ROM_LOAD( "797-c02.12d", 0x08000, 0x08000, CRC(65a331ea) SHA1(f206f6c5f0474542a5b7686b2f4d2cc7077dd5b9) )
392390
393   ROM_REGION( 0x080000, "gfx1", 0 )
394   ROM_LOAD( "797a05.19h", 0x000000, 0x40000, CRC(5491ba28) SHA1(c807774827c55c211ab68f548e1e835289cc5744) )   /* tiles */
395   ROM_LOAD( "797a06.13h", 0x040000, 0x40000, CRC(d055f5cc) SHA1(3723b39b2a3e6dd8e7fc66bbfe1eef9f80818774) )   /* sprites */
391   ROM_REGION( 0x40000, "gfx1", 0 )
392   ROM_LOAD( "797a05.19h", 0x00000, 0x40000, CRC(5491ba28) SHA1(c807774827c55c211ab68f548e1e835289cc5744) )   /* tiles */
396393
394   ROM_REGION( 0x40000, "gfx2", 0 )
395   ROM_LOAD( "797a06.13h", 0x00000, 0x40000, CRC(d055f5cc) SHA1(3723b39b2a3e6dd8e7fc66bbfe1eef9f80818774) )   /* sprites */
396
397397   ROM_REGION( 0x0100, "proms", 0 )
398398   ROM_LOAD( "797a07.16i", 0x0000, 0x0100, CRC(7aecad4e) SHA1(05150a8dd25bdd6ab0c5b350e6ffd272f040e46a) ) /* sprites lookup table, 63S141N BPROM */
399399
r29543r29544
403403ROM_END
404404
405405ROM_START( bladestle )
406   ROM_REGION( 0x18000, "maincpu", 0 ) /* code + banked roms */
407   ROM_LOAD( "797-e01.19c", 0x10000, 0x08000, CRC(f8472e95) SHA1(8b6caa905fb1642300dd9da508871b00429872c3) )   /* fixed ROM */
408   ROM_CONTINUE(            0x08000, 0x08000 )             /* banked ROM */
406   ROM_REGION( 0x10000, "maincpu", 0 ) /* code + banked roms */
407   ROM_LOAD( "797-e01.19c", 0x00000, 0x10000, CRC(f8472e95) SHA1(8b6caa905fb1642300dd9da508871b00429872c3) )
409408
410409   ROM_REGION( 0x10000, "audiocpu", 0 ) /* 64k for the sound CPU */
411410   ROM_LOAD( "797-c02.12d", 0x08000, 0x08000, CRC(65a331ea) SHA1(f206f6c5f0474542a5b7686b2f4d2cc7077dd5b9) )
412411
413   ROM_REGION( 0x080000, "gfx1", 0 )
414   ROM_LOAD( "797a05.19h", 0x000000, 0x40000, CRC(5491ba28) SHA1(c807774827c55c211ab68f548e1e835289cc5744) )   /* tiles */
415   ROM_LOAD( "797a06.13h", 0x040000, 0x40000, CRC(d055f5cc) SHA1(3723b39b2a3e6dd8e7fc66bbfe1eef9f80818774) )   /* sprites */
412   ROM_REGION( 0x40000, "gfx1", 0 )
413   ROM_LOAD( "797a05.19h", 0x00000, 0x40000, CRC(5491ba28) SHA1(c807774827c55c211ab68f548e1e835289cc5744) )   /* tiles */
416414
415   ROM_REGION( 0x40000, "gfx2", 0 )
416   ROM_LOAD( "797a06.13h", 0x00000, 0x40000, CRC(d055f5cc) SHA1(3723b39b2a3e6dd8e7fc66bbfe1eef9f80818774) )   /* sprites */
417
417418   ROM_REGION( 0x0100, "proms", 0 )
418419   ROM_LOAD( "797a07.16i", 0x0000, 0x0100, CRC(7aecad4e) SHA1(05150a8dd25bdd6ab0c5b350e6ffd272f040e46a) ) /* sprites lookup table, 63S141N BPROM */
419420
branches/new_menus/src/mame/drivers/overdriv.c
r29543r29544
260260INPUT_PORTS_END
261261
262262
263static const k053260_interface k053260_config =
264{
265   "shared"
266};
267
268263static const k053247_interface overdriv_k053246_intf =
269264{
270265   "gfx1", 0,
r29543r29544
375370   MCFG_SOUND_ROUTE(1, "rspeaker", 0.5)
376371
377372   MCFG_K053260_ADD("k053260_1", 3579545)
378   MCFG_SOUND_CONFIG(k053260_config)
373   MCFG_K053260_REGION("shared")
379374   MCFG_SOUND_ROUTE(0, "lspeaker", 0.35)
380375   MCFG_SOUND_ROUTE(1, "rspeaker", 0.35)
381376
382377   MCFG_K053260_ADD("k053260_2", 3579545)
383   MCFG_SOUND_CONFIG(k053260_config)
378   MCFG_K053260_REGION("shared")
384379   MCFG_SOUND_ROUTE(0, "lspeaker", 0.35)
385380   MCFG_SOUND_ROUTE(1, "rspeaker", 0.35)
386381MACHINE_CONFIG_END
branches/new_menus/src/mame/drivers/peplus.c
r29543r29544
162162      illustration purposes and to archive the sets.
163163
164164NOTE: Currently some of the 32K sets read the "OPEN DOOR" and cycle too quickly to be played. Some can be played
165      if the game thinks the door is closed when you start the game, like PP0120 Wild Sevens Poker.
165      if the door status is closed when you start the game, like PP0120 Wild Sevens Poker.
166166
167167***********************************************************************************/
168168
r29543r29544
24862486                                        w/D     w/oD
24872487PayTable   3K   STR  FL  FH  4K  SF  5K  RF  4D  RF  (Bonus)
24882488----------------------------------------------------------
2489  P56A     1     2    3   3   4   8  10  20 200 250    800
2490  % Range: 89.4-91.4%  Optimum: 93.4%  Hit Frequency: 45.1%
2491     Programs Available: PP0242
2489  P47A      1    2    2   3   4  13  16  22 200 250    800
2490  % Range: 92.8-94.8%  Optimum: 96.8%  Hit Frequency: 44.9%
2491     Programs Available: PP0290, X000224P & PP0224 - Non Double-up Only
24922492*/
24932493   ROM_LOAD( "pp0224_a47-a76.u68",   0x00000, 0x10000, CRC(5d6881ad) SHA1(38953ffadea04df614b14c70177736039495c408) ) /* Game Version: A47, Library Version: A76 */
24942494
r29543r29544
25082508                                        w/D     w/oD
25092509PayTable   3K   STR  FL  FH  4K  SF  5K  RF  4D  RF  (Bonus)
25102510----------------------------------------------------------
2511  P56A     1     2    3   3   4   8  10  20 200 250    800
2512  % Range: 89.4-91.4%  Optimum: 93.4%  Hit Frequency: 45.1%
2513     Programs Available: PP0242
2511  P47A      1    2    2   3   4  13  16  22 200 250    800
2512  % Range: 92.8-94.8%  Optimum: 96.8%  Hit Frequency: 44.9%
2513     Programs Available: PP0290, X000224P & PP0224 - Non Double-up Only
25142514*/
25152515
25162516   ROM_LOAD( "pp0224_961-984.u68",   0x00000, 0x10000, CRC(71d5e112) SHA1(528f06ad7ea7e1e297939c7b3ca0bb7faa8ce8c1) ) /* Game Version: 961, Library Version: 984 */
r29543r29544
25392539   ROM_LOAD( "cap740.u50", 0x0000, 0x0100, CRC(6fe619c4) SHA1(49e43dafd010ce0fe9b2a63b96a4ddedcb933c6d) ) /* BPROM type DM74LS471 (compatible with N82S135N) verified */
25402540ROM_END
25412541
2542ROM_START( pepp0242 ) /* Normal board : Deuces Wild Poker (PP0242) - Multi Regional / Multi Currency in English / Spanish */
2543   ROM_REGION( 0x10000, "maincpu", 0 )
2544/*
2545                                        w/D     w/oD
2546PayTable   3K   STR  FL  FH  4K  SF  5K  RF  4D  RF  (Bonus)
2547----------------------------------------------------------
2548  P56A     1     2    3   3   4   8  10  20 200 250    800
2549  % Range: 89.4-91.4%  Optimum: 93.4%  Hit Frequency: 45.1%
2550     Programs Available: PP0242, X000242P
2551*/
2552
2553   ROM_LOAD( "pp0242_a1c-a31.u68",   0x00000, 0x10000, CRC(cb7cdf2b) SHA1(989db6bf860637ef0c9d38c4ec824e2ab92acb89) ) /* Game Version: A1C, Library Version: A31 */
2554
2555   ROM_REGION( 0x020000, "gfx1", 0 )
2556   ROM_LOAD( "mro-cg1325.u72",  0x00000, 0x8000, CRC(ebb81436) SHA1(211cc0f881703b3cceb51c65209075154c9536db) )
2557   ROM_LOAD( "mgo-cg1325.u73",  0x08000, 0x8000, CRC(ef86e83a) SHA1(854fc31173c7647a9ed986f2fe58ec3795eb8542) )
2558   ROM_LOAD( "mbo-cg1325.u74",  0x10000, 0x8000, CRC(8387b4ba) SHA1(cab77982464e9e70e6ad4ecf51a5cafe7aefb478) )
2559   ROM_LOAD( "mxo-cg1325.u75",  0x18000, 0x8000, CRC(9dddc501) SHA1(a0ab8b3866b0ae018b3f6e0199bdc756d4e5f967) )
2560
2561   ROM_REGION( 0x100, "proms", 0 )
2562   ROM_LOAD( "cap1215.u50", 0x0000, 0x0100, CRC(294b7b10) SHA1(a405a4b8547b713c5c02dacb19e7354095a7b584) )
2563ROM_END
2564
25422565ROM_START( pepp0249 ) /* Normal board : Deuces Wild Poker (PP0249) */
25432566/*
25442567                                        w/D     w/oD
r29543r29544
26442667   ROM_LOAD( "cap740.u50", 0x0000, 0x0100, CRC(6fe619c4) SHA1(49e43dafd010ce0fe9b2a63b96a4ddedcb933c6d) ) /* BPROM type DM74LS471 (compatible with N82S135N) verified */
26452668ROM_END
26462669
2670ROM_START( pepp0288 ) /* Normal board : Standard Draw Poker (PP0288) - Spanish */
2671/*
2672PayTable   Js+  2PR  3K   STR  FL  FH  4K  SF  RF  (Bonus)
2673----------------------------------------------------------
2674   KK       1    2    3    4    6   9  25  50 500    500
2675  % Range: 94.9-96.9%  Optimum: 98.9%  Hit Frequency: 45.5%
2676     Programs Available: PP0288
2677
2678Spanish version of PP0150
2679*/
2680   ROM_REGION( 0x10000, "maincpu", 0 )
2681   ROM_LOAD( "pp0288_964-988.u68",   0x00000, 0x10000, CRC(f7e1cb4c) SHA1(651c4306764200611aae7280ce0a9756d42ccb21) ) /* Game Version: 964, Library Version: 988 */
2682
2683   ROM_REGION( 0x020000, "gfx1", 0 )
2684   ROM_LOAD( "mro-cg1152.u72",   0x00000, 0x8000, CRC(55aca7f6) SHA1(9a0b25908e4fee8346da4726f38993e233a2cb2f) )
2685   ROM_LOAD( "mgo-cg1152.u73",   0x08000, 0x8000, CRC(c5185314) SHA1(7fc385d2b44e68364f2b5a3702737c5d5fea5ea2) )
2686   ROM_LOAD( "mbo-cg1152.u74",   0x10000, 0x8000, CRC(bd19aef6) SHA1(77126ea73d0a5da4b8856b5ebcbbab84cfaef008) )
2687   ROM_LOAD( "mxo-cg1152.u75",   0x18000, 0x8000, CRC(d65f7362) SHA1(d56fa0d13126f1599d538c81a2c7ea1f3c94b62f) )
2688
2689   ROM_REGION( 0x100, "proms", 0 )
2690   ROM_LOAD( "cap740.u50", 0x0000, 0x0100, CRC(6fe619c4) SHA1(49e43dafd010ce0fe9b2a63b96a4ddedcb933c6d) ) /* BPROM type DM74LS471 (compatible with N82S135N) verified */
2691ROM_END
2692
26472693ROM_START( pepp0290 ) /* Normal board : Deuces Wild Poker (PP0290) */
26482694/*
26492695                                        w/D     w/oD
r29543r29544
29052951   ROM_LOAD( "cap740.u50", 0x0000, 0x0100, CRC(6fe619c4) SHA1(49e43dafd010ce0fe9b2a63b96a4ddedcb933c6d) ) /* BPROM type DM74LS471 (compatible with N82S135N) verified */
29062952ROM_END
29072953
2954ROM_START( pepp0431 ) /* Normal board : Deuces Joker Wild Poker (PP0431) */
2955/*
2956                                         With  w/o  w/o  With
2957                                         Wild  JKR  Wild JKR
2958PayTable   3K   STR  FL  FH  4K  SF  5K   RF    4D   RF   4D  (Bonus)
2959--------------------------------------------------------------------
2960  P76N     1     1    3   3   3   6   9   12    25  800  1000  2000
2961  % Range: 95.1-97.1%  Optimum: 99.1%  Hit Frequency: 50.4%
2962     Programs Available: PP0431, PP0812, PP0813, X000225P & PP0225 - Non Double-up Only
2963*/
2964   ROM_REGION( 0x10000, "maincpu", 0 )
2965   ROM_LOAD( "pp0431_a47-a76.u68",   0x00000, 0x10000, CRC(2997aaac) SHA1(b52525154f4ae39a341ecf829c33449f31a8ce07) ) /* Game Version: A47, Library Version: A76 */
2966
2967   ROM_REGION( 0x020000, "gfx1", 0 )
2968   ROM_LOAD( "mro-cg1215.u72",   0x00000, 0x8000, CRC(425f57be) SHA1(6d53ae86bec7189a35671a7f691e101a2ed4d8c4) ) /*  06/09/93   @ IGT  L93-1585  */
2969   ROM_LOAD( "mgo-cg1215.u73",   0x08000, 0x8000, CRC(0f66cd94) SHA1(9ac0cd01aca87e045c4fd6045ed907a092d6b2ee) )
2970   ROM_LOAD( "mbo-cg1215.u74",   0x10000, 0x8000, CRC(10f89e44) SHA1(cdc34970b0325a24cfd5c187a4b4dbf42be8fc93) )
2971   ROM_LOAD( "mxo-cg1215.u75",   0x18000, 0x8000, CRC(73c24e43) SHA1(f09beaf374ad371db2701767ce6ac5bdb13c445a) )
2972
2973   ROM_REGION( 0x100, "proms", 0 )
2974   ROM_LOAD( "cap1215.u50", 0x0000, 0x0100, CRC(294b7b10) SHA1(a405a4b8547b713c5c02dacb19e7354095a7b584) )
2975ROM_END
2976
29082977ROM_START( pepp0434 ) /* Normal board : Bonus Poker Deluxe (PP0434) */
29092978/*
29102979PayTable   Js+  2PR  3K   STR  FL  FH  4K  SF  RF  (Bonus)
r29543r29544
29893058   ROM_LOAD( "cap740.u50", 0x0000, 0x0100, CRC(6fe619c4) SHA1(49e43dafd010ce0fe9b2a63b96a4ddedcb933c6d) ) /* BPROM type DM74LS471 (compatible with N82S135N) verified */
29903059ROM_END
29913060
3061ROM_START( pepp0449a ) /* Normal board : Standard Draw Poker (PP0449) - Multi Regional / Multi Currency in English / Spanish */
3062/*
3063PayTable   Js+  2PR  3K   STR  FL  FH  4K  SF  RF  (Bonus)
3064----------------------------------------------------------
3065  P11A     1     2    3    4    5   9  25  50 250    800
3066  % Range: 92.1-94.1%  Optimum: 96.1%  Hit Frequency: 45.5%
3067     Programs Available: PP0449, X000449P & PP0221 - Non Double-up Only
3068*/
3069   ROM_REGION( 0x10000, "maincpu", 0 )
3070   ROM_LOAD( "pp0449_a19-a2x.u68",   0x00000, 0x10000, CRC(0bde4a5b) SHA1(dacce2a56ede8145fc22cad4cc75967aaea3b6e4) ) /* Game Version: A19, Library Version: A2X */
3071
3072   ROM_REGION( 0x020000, "gfx1", 0 )
3073   ROM_LOAD( "mro-cg1426.u74",  0x00000, 0x8000, CRC(b99b3856) SHA1(a7de74bc712c68ae3da2d546c49dcd70e54c26a1) )
3074   ROM_LOAD( "mgo-cg1426.u73",  0x08000, 0x8000, CRC(d7145ea0) SHA1(7b23cf7840bab11f7ba9229e990e2c9dd995d59f) )
3075   ROM_LOAD( "mbo-cg1426.u72",  0x10000, 0x8000, CRC(5fd94bc5) SHA1(b2a23a6a8eb23fbefd7b16e7afb7eddad5f6656c) )
3076   ROM_LOAD( "mxo-cg1426.u75",  0x18000, 0x8000, CRC(74bc1556) SHA1(9afc00ec4643baa448e0131e1c7aeb3da4739f59) )
3077
3078
3079   ROM_REGION( 0x100, "proms", 0 )
3080   ROM_LOAD( "cap904.u50", 0x0000, 0x0100, CRC(0eec8336) SHA1(a6585c978dbc2f4f3818e3a5b92f8c28be23c4c0) ) /* BPROM type N82S135N verified */
3081ROM_END
3082
29923083ROM_START( pepp0452 ) /* Normal board : Double Deuces Wild Poker (PP0452) */
29933084/*
29943085                                        w/D     wo/D
r29543r29544
42524343   ROM_LOAD( "x000055p.u66",   0x00000, 0x10000, CRC(e06819df) SHA1(36590c4588b8036908e63714fbb3e77d23e60eae) ) /* Deuces Wild Poker */
42534344
42544345   ROM_REGION( 0x020000, "gfx1", 0 )
4255   ROM_LOAD( "mro-cg2185.u77",  0x00000, 0x8000, CRC(7e64bd1a) SHA1(e988a380ee58078bf5bdc7747e83aed1393cfad8) ) /*  07/10/95   @ IGT  L95-1506  */
4256   ROM_LOAD( "mgo-cg2185.u78",  0x08000, 0x8000, CRC(d4127893) SHA1(75039c45ba6fd171a66876c91abc3191c7feddfc) )
4257   ROM_LOAD( "mbo-cg2185.u79",  0x10000, 0x8000, CRC(17dba955) SHA1(5f77379c88839b3a04e235e4fb0120c77e17b60e) )
4258   ROM_LOAD( "mxo-cg2185.u80",  0x18000, 0x8000, CRC(583eb3b1) SHA1(4a2952424969917fb1594698a779fe5a1e99bff5) )
4346   ROM_LOAD( "mro-cg2399.u72",  0x00000, 0x8000, CRC(0424f4ba) SHA1(c8b192a6f63c8c9937cb3923d27b9ba2c39823cd) ) /* Custom The Fun Ships graphics */
4347   ROM_LOAD( "mgo-cg2399.u73",  0x08000, 0x8000, CRC(5848a2fa) SHA1(4173a473016b7a776d2b59bf3ded0be35bd43721) )
4348   ROM_LOAD( "mbo-cg2399.u74",  0x10000, 0x8000, CRC(5c3e16f6) SHA1(a4aa457f239527bffa6472e0d6f9d836f796b326) )
4349   ROM_LOAD( "mxo-cg2399.u75",  0x18000, 0x8000, CRC(bd7669d5) SHA1(4343a9764fd563e2e1cdd8558f2f53f77006b159) )
42594350
42604351   ROM_REGION( 0x200, "proms", 0 )
42614352   ROM_LOAD( "capx1321.u43", 0x0000, 0x0200, CRC(4b57569f) SHA1(fa29c0f627e7ce79951ec6dadec114864144f37d) )
r29543r29544
46854776   ROM_LOAD( "capx1321.u43", 0x0000, 0x0200, CRC(4b57569f) SHA1(fa29c0f627e7ce79951ec6dadec114864144f37d) )
46864777ROM_END
46874778
4779ROM_START( pex0150p ) /* Superboard : Standard Draw Poker (X000150P+XP000038) */
4780/*
4781PayTable   Js+  2PR  3K   STR  FL  FH  4K  SF  RF  (Bonus)
4782----------------------------------------------------------
4783   KK       1    2    3    4    6   9  25  50 500    500
4784  % Range: 94.9-96.9%  Optimum: 98.9%  Hit Frequency: 45.5%
4785     Programs Available: PP0150, X000150P
4786*/
4787   ROM_REGION( 0x10000, "maincpu", 0 )
4788   ROM_LOAD( "xp000038.u67",   0x00000, 0x10000, CRC(8707ab9e) SHA1(3e00a2ad8017e1495c6d6fe900d0efa68a1772b8) ) /* 07/01/96   @IGT  L96-1119 */
4789
4790   ROM_REGION( 0x10000, "user1", 0 )
4791   ROM_LOAD( "x000150p.u66",   0x00000, 0x10000, CRC(d10759fa) SHA1(eae633d03ac9db86520a70825ac0a59ee9ebc819) ) /* Standard Draw Poker */
4792
4793   ROM_REGION( 0x020000, "gfx1", 0 )
4794   ROM_LOAD( "mro-cg2185.u77",  0x00000, 0x8000, CRC(7e64bd1a) SHA1(e988a380ee58078bf5bdc7747e83aed1393cfad8) ) /*  07/10/95   @ IGT  L95-1506  */
4795   ROM_LOAD( "mgo-cg2185.u78",  0x08000, 0x8000, CRC(d4127893) SHA1(75039c45ba6fd171a66876c91abc3191c7feddfc) )
4796   ROM_LOAD( "mbo-cg2185.u79",  0x10000, 0x8000, CRC(17dba955) SHA1(5f77379c88839b3a04e235e4fb0120c77e17b60e) )
4797   ROM_LOAD( "mxo-cg2185.u80",  0x18000, 0x8000, CRC(583eb3b1) SHA1(4a2952424969917fb1594698a779fe5a1e99bff5) )
4798
4799   ROM_REGION( 0x200, "proms", 0 )
4800   ROM_LOAD( "capx1321.u43", 0x0000, 0x0200, CRC(4b57569f) SHA1(fa29c0f627e7ce79951ec6dadec114864144f37d) )
4801ROM_END
4802
46884803ROM_START( pex0158p ) /* Superboard : 4 of a Kind Bonus Poker (X000158P+XP000038) */
46894804/*
46904805                                       5-K 2-4
r29543r29544
48844999   ROM_LOAD( "capx1321.u43", 0x0000, 0x0200, CRC(4b57569f) SHA1(fa29c0f627e7ce79951ec6dadec114864144f37d) )
48855000ROM_END
48865001
5002ROM_START( pex0242p ) /* Superboard : Deuces Wild Poker (X000242P+XP000053) */
5003/*
5004                                        w/D     w/oD
5005PayTable   3K   STR  FL  FH  4K  SF  5K  RF  4D  RF  (Bonus)
5006----------------------------------------------------------
5007  P56A     1     2    3   3   4   8  10  20 200 250    800
5008  % Range: 89.4-91.4%  Optimum: 93.4%  Hit Frequency: 45.1%
5009     Programs Available: PP0242, X000242P
5010*/
5011   ROM_REGION( 0x10000, "maincpu", 0 )
5012   ROM_LOAD( "xp000053.u67",   0x00000, 0x10000, CRC(f4f1f986) SHA1(84cfc2c4a10ed24d3a971fe75041a4108ec1d7f2) )
5013
5014   ROM_REGION( 0x10000, "user1", 0 )
5015   ROM_LOAD( "x000242p.u66",   0x00000, 0x10000, CRC(e0292d63) SHA1(8d8ec5dc1abaf8e8a8a7451d3a814023d8195fb5) ) /* Deuces Wild Poker */
5016
5017   ROM_REGION( 0x020000, "gfx1", 0 )
5018   ROM_LOAD( "mro-cg2185.u77",  0x00000, 0x8000, CRC(7e64bd1a) SHA1(e988a380ee58078bf5bdc7747e83aed1393cfad8) ) /*  07/10/95   @ IGT  L95-1506  */
5019   ROM_LOAD( "mgo-cg2185.u78",  0x08000, 0x8000, CRC(d4127893) SHA1(75039c45ba6fd171a66876c91abc3191c7feddfc) )
5020   ROM_LOAD( "mbo-cg2185.u79",  0x10000, 0x8000, CRC(17dba955) SHA1(5f77379c88839b3a04e235e4fb0120c77e17b60e) )
5021   ROM_LOAD( "mxo-cg2185.u80",  0x18000, 0x8000, CRC(583eb3b1) SHA1(4a2952424969917fb1594698a779fe5a1e99bff5) )
5022
5023   ROM_REGION( 0x200, "proms", 0 )
5024   ROM_LOAD( "capx1321.u43", 0x0000, 0x0200, CRC(4b57569f) SHA1(fa29c0f627e7ce79951ec6dadec114864144f37d) )
5025ROM_END
5026
48875027ROM_START( pex0265p ) /* Superboard : 4 of a Kind Bonus Poker (X000265P+XP000038) */
48885028/*
48895029                                       5-K 2-4
r29543r29544
52805420   ROM_LOAD( "capx1321.u43", 0x0000, 0x0200, CRC(4b57569f) SHA1(fa29c0f627e7ce79951ec6dadec114864144f37d) )
52815421ROM_END
52825422
5423ROM_START( pex0516p ) /* Superboard : Double Double Bonus Poker (X000516P+XP000038) */
5424/*
5425                                      5-K 2-4
5426PayTable   Js+  2PR  3K  STR  FL  FH  4K  4K  4A  SF  RF  (Bonus)
5427-----------------------------------------------------------------
5428  P325A     1    2    3   4    5   8  50  80 160  50 250    800
5429  % Range: 93.8-95.8%  Optimum: 97.8%  Hit Frequency: 44.5%
5430     Programs Available: PP0516, X000516P & PP0540 - Non Double-up Only
5431*/
5432   ROM_REGION( 0x10000, "maincpu", 0 )
5433   ROM_LOAD( "xp000038.u67",   0x00000, 0x10000, CRC(8707ab9e) SHA1(3e00a2ad8017e1495c6d6fe900d0efa68a1772b8) ) /* 07/01/96   @IGT  L96-1119 */
5434
5435   ROM_REGION( 0x10000, "user1", 0 )
5436   ROM_LOAD( "x000516p.u66",   0x00000, 0x10000, CRC(37f84ce7) SHA1(2e5157d02febec0ff31eb5a23254f7c49a486cf5) ) /* Double Bonus Poker */
5437
5438   ROM_REGION( 0x020000, "gfx1", 0 )
5439   ROM_LOAD( "mro-cg2185.u77",  0x00000, 0x8000, CRC(7e64bd1a) SHA1(e988a380ee58078bf5bdc7747e83aed1393cfad8) ) /*  07/10/95   @ IGT  L95-1506  */
5440   ROM_LOAD( "mgo-cg2185.u78",  0x08000, 0x8000, CRC(d4127893) SHA1(75039c45ba6fd171a66876c91abc3191c7feddfc) )
5441   ROM_LOAD( "mbo-cg2185.u79",  0x10000, 0x8000, CRC(17dba955) SHA1(5f77379c88839b3a04e235e4fb0120c77e17b60e) )
5442   ROM_LOAD( "mxo-cg2185.u80",  0x18000, 0x8000, CRC(583eb3b1) SHA1(4a2952424969917fb1594698a779fe5a1e99bff5) )
5443
5444   ROM_REGION( 0x200, "proms", 0 )
5445   ROM_LOAD( "capx1321.u43", 0x0000, 0x0200, CRC(4b57569f) SHA1(fa29c0f627e7ce79951ec6dadec114864144f37d) )
5446ROM_END
5447
52835448ROM_START( pex0536p ) /* Superboard : Joker Poker (X000536P+XP000038) */
52845449/*
52855450                                            w/J     w/oJ
r29543r29544
57075872   ROM_LOAD( "capx2174.u43", 0x0000, 0x0200, CRC(50bdad55) SHA1(958d463c7effb3457c1f9c44c9b7822339c04e8b) )
57085873ROM_END
57095874
5875ROM_START( pex2038p ) /* Superboard : Nevada Bonus Poker (X002038P+XP000038) */
5876/*
5877                                         2-K
5878PayTable   Js+  2PR  3K  3A  STR  FL  FH  4K  4A  SF  RF  (Bonus)
5879-----------------------------------------------------------------
5880  P576A     1    1    3   6   5    7  10  25 200 100 250    800
5881  % Range: 93.2-95.2%  Optimum: 97.2%  Hit Frequency: 43.4%
5882     Programs Available: X002038P
5883*/
5884   ROM_REGION( 0x10000, "maincpu", 0 )
5885   ROM_LOAD( "xp000038.u67",   0x00000, 0x10000, CRC(8707ab9e) SHA1(3e00a2ad8017e1495c6d6fe900d0efa68a1772b8) ) /* 07/01/96   @IGT  L96-1119 */
5886
5887   ROM_REGION( 0x10000, "user1", 0 )
5888   ROM_LOAD( "x002038p.u66",   0x00000, 0x10000, CRC(58d01ba5) SHA1(6d4cde9c9e55967db2b661c7123cce9958a00639) ) /* Nevada Bonus Poker */
5889
5890   ROM_REGION( 0x020000, "gfx1", 0 )
5891   ROM_LOAD( "mro-cg2185.u77",  0x00000, 0x8000, CRC(7e64bd1a) SHA1(e988a380ee58078bf5bdc7747e83aed1393cfad8) ) /*  07/10/95   @ IGT  L95-1506  */
5892   ROM_LOAD( "mgo-cg2185.u78",  0x08000, 0x8000, CRC(d4127893) SHA1(75039c45ba6fd171a66876c91abc3191c7feddfc) )
5893   ROM_LOAD( "mbo-cg2185.u79",  0x10000, 0x8000, CRC(17dba955) SHA1(5f77379c88839b3a04e235e4fb0120c77e17b60e) )
5894   ROM_LOAD( "mxo-cg2185.u80",  0x18000, 0x8000, CRC(583eb3b1) SHA1(4a2952424969917fb1594698a779fe5a1e99bff5) )
5895
5896   ROM_REGION( 0x200, "proms", 0 )
5897   ROM_LOAD( "capx1321.u43", 0x0000, 0x0200, CRC(4b57569f) SHA1(fa29c0f627e7ce79951ec6dadec114864144f37d) )
5898ROM_END
5899
57105900ROM_START( pex2040p ) /* Superboard : Nevada Bonus Poker (X002040P+XP000038) */
57115901/*
57125902                                         2-K
r29543r29544
57825972   ROM_LOAD( "capx1321.u43", 0x0000, 0x0200, CRC(4b57569f) SHA1(fa29c0f627e7ce79951ec6dadec114864144f37d) )
57835973ROM_END
57845974
5975ROM_START( pex2044p ) /* Superboard : Triple Bonus Poker (X002044P+XP000038) */
5976/*
5977                                      5-K 2-4
5978PayTable   Js+  2PR  3K  STR  FL  FH  4K  4K  4A  SF  RF  (Bonus)
5979-----------------------------------------------------------------
5980  P606A     1    1    3   4    7   9  75 120 240  50 250    800
5981  % Range: 93.5-95.5%  Optimum: 97.5%  Hit Frequency: 34.7%
5982     Programs Available: X002044P
5983*/
5984   ROM_REGION( 0x10000, "maincpu", 0 )
5985   ROM_LOAD( "xp000038.u67",   0x00000, 0x10000, CRC(8707ab9e) SHA1(3e00a2ad8017e1495c6d6fe900d0efa68a1772b8) ) /* 07/01/96   @IGT  L96-1119 */
5986
5987   ROM_REGION( 0x10000, "user1", 0 )
5988   ROM_LOAD( "x002044p.u66",   0x00000, 0x10000, CRC(158af97f) SHA1(452247d981f1202da8c44a31f0d3343184d3db41) ) /* Triple Bonus Poker */
5989
5990   ROM_REGION( 0x020000, "gfx1", 0 )
5991   ROM_LOAD( "mro-cg2275.u77",  0x00000, 0x8000, CRC(15d5d6b8) SHA1(61b6821d4cc059732bc3831bf19bf01aa3910b31) )
5992   ROM_LOAD( "mgo-cg2275.u78",  0x08000, 0x8000, CRC(bcb49579) SHA1(d5d9f523304582fa6f0a0c69aade77629bdec006) )
5993   ROM_LOAD( "mbo-cg2275.u79",  0x10000, 0x8000, CRC(9f893787) SHA1(0b79d5cbac920394d5f5c04d0d9d3727e0060366) )
5994   ROM_LOAD( "mxo-cg2275.u80",  0x18000, 0x8000, CRC(6187c68b) SHA1(7777b141fd1379d37d93a228b2e2159476c2b89e) )
5995
5996   ROM_REGION( 0x200, "proms", 0 )
5997   ROM_LOAD( "capx1321.u43", 0x0000, 0x0200, CRC(4b57569f) SHA1(fa29c0f627e7ce79951ec6dadec114864144f37d) )
5998ROM_END
5999
57856000ROM_START( pex2045p ) /* Superboard : Triple Bonus Poker (X002045P+XP000038) */
57866001/*
57876002                                      5-K 2-4
r29543r29544
62096424   ROM_LOAD( "capx2309.u43", 0x0000, 0x0200, CRC(5da912cc) SHA1(6294f8be682e70e9052c9ae5f6865467e9dba2e3) )
62106425ROM_END
62116426
6427ROM_START( pex2272p ) /* Superboard : Black Jack Bonus Poker (X002272P+XP000055) */
6428/*
6429Black Jack as in Jack of Spades/Clubs, not 21       With With
6430                                                     BJ   BJ  With
6431                                        5-K 2-4     5-K  2-4   BJ
6432PayTable   Js+ 2PR  STR  FL  FH  4K  SF  4K  4K  4A  4K   4K   4A  RF (Bonus)
6433-----------------------------------------------------------------------------
6434 P870BB     1   1    3    4   7   9  50  25  80 160 160  400  400 400   800
6435  % Range: 95.4-97.4%  Optimum: 99.4%  Hit Frequency: ???%
6436     Programs Available: X002272P
6437*/
6438   ROM_REGION( 0x10000, "maincpu", 0 )
6439   ROM_LOAD( "xp000055.u67",   0x00000, 0x10000, CRC(339821e0) SHA1(127d4eff01136feaf1e3242d57433349afb7b6ca) )
6440
6441   ROM_REGION( 0x10000, "user1", 0 )
6442   ROM_LOAD( "x002272p.u66",   0x00000, 0x10000, CRC(ee4f27b9) SHA1(1ee105430358ea27badd943bb6b18663e4029388) ) /* Black Jack Bonus Poker */
6443
6444   ROM_REGION( 0x020000, "gfx1", 0 )
6445   ROM_LOAD( "mro-cg2324.u77",  0x00000, 0x8000, CRC(6eceef42) SHA1(a2ddd2a3290c41e510f483c6b633fe0002694d0b) )
6446   ROM_LOAD( "mgo-cg2324.u78",  0x08000, 0x8000, CRC(26d0acbe) SHA1(09a9127deb88185cd5b748bac657461eadb2f48f) )
6447   ROM_LOAD( "mbo-cg2324.u79",  0x10000, 0x8000, CRC(47baee32) SHA1(d8af09022ccb5fc06aa3aa4c200a734b66cbee00) )
6448   ROM_LOAD( "mxo-cg2324.u80",  0x18000, 0x8000, CRC(60449fc0) SHA1(251d1e04786b70c1d2bc7b02f3b69cd58ac76398) )
6449
6450   ROM_REGION( 0x200, "proms", 0 )
6451   ROM_LOAD( "capx1321.u43", 0x0000, 0x0200, CRC(4b57569f) SHA1(fa29c0f627e7ce79951ec6dadec114864144f37d) )
6452ROM_END
6453
6454ROM_START( pex2275p ) /* Superboard : Black Jack Bonus Poker (X002275P+XP000055) */
6455/*
6456Black Jack as in Jack of Spades/Clubs, not 21       With With
6457                                                     BJ   BJ  With
6458                                        5-K 2-4     5-K  2-4   BJ
6459PayTable   Js+ 2PR  STR  FL  FH  4K  SF  4K  4K  4A  4K   4K   4A  RF (Bonus)
6460-----------------------------------------------------------------------------
6461 P873BB     1   1    3    4   5   8  50  25  80 160 160  400  400 400   800
6462  % Range: 92.0-94.0%  Optimum: 96.0%  Hit Frequency: ???%
6463     Programs Available: X002275P
6464*/
6465   ROM_REGION( 0x10000, "maincpu", 0 )
6466   ROM_LOAD( "xp000055.u67",   0x00000, 0x10000, CRC(339821e0) SHA1(127d4eff01136feaf1e3242d57433349afb7b6ca) )
6467
6468   ROM_REGION( 0x10000, "user1", 0 )
6469   ROM_LOAD( "x002275p.u66",   0x00000, 0x10000, CRC(5ba4f5ab) SHA1(def069025ec4aa340646dfd7cfacc8ce836a210c) ) /* Black Jack Bonus Poker */
6470
6471   ROM_REGION( 0x020000, "gfx1", 0 )
6472   ROM_LOAD( "mro-cg2324.u77",  0x00000, 0x8000, CRC(6eceef42) SHA1(a2ddd2a3290c41e510f483c6b633fe0002694d0b) )
6473   ROM_LOAD( "mgo-cg2324.u78",  0x08000, 0x8000, CRC(26d0acbe) SHA1(09a9127deb88185cd5b748bac657461eadb2f48f) )
6474   ROM_LOAD( "mbo-cg2324.u79",  0x10000, 0x8000, CRC(47baee32) SHA1(d8af09022ccb5fc06aa3aa4c200a734b66cbee00) )
6475   ROM_LOAD( "mxo-cg2324.u80",  0x18000, 0x8000, CRC(60449fc0) SHA1(251d1e04786b70c1d2bc7b02f3b69cd58ac76398) )
6476
6477   ROM_REGION( 0x200, "proms", 0 )
6478   ROM_LOAD( "capx1321.u43", 0x0000, 0x0200, CRC(4b57569f) SHA1(fa29c0f627e7ce79951ec6dadec114864144f37d) )
6479ROM_END
6480
62126481ROM_START( pex2283p ) /* Superboard : Dealt Deuces Wild Bonus (X002283P+XP000057) */
62136482/*
62146483                                   w/D 6-K 3-5         w/A w/oD
r29543r29544
63266595   ROM_LOAD( "capx2174.u43", 0x0000, 0x0200, CRC(50bdad55) SHA1(958d463c7effb3457c1f9c44c9b7822339c04e8b) )
63276596ROM_END
63286597
6598ROM_START( pex2306p ) /* Superboard : Triple Double Bonus Poker (X002306P+XP000112) */
6599/*
6600                                                  2-4
6601                                                   4K    4A
6602                                      5-K 2-4     with   with
6603PayTable   Js+  2PR  3K  STR  FL  FH  4K  4K  4A  A,2-4  2-4  SF  RF  (Bonus)
6604-----------------------------------------------------------------------------
6605 P908BM     1    1    2   4    7   9  50  80 160   400   400  50 400    800
6606  % Range: 95.6-97.6%  Optimum: 99.6%  Hit Frequency: 43.3%
6607     Programs Available: X002306P
6608*/
6609   ROM_REGION( 0x10000, "maincpu", 0 )
6610   ROM_LOAD( "xp000112.u67",   0x00000, 0x10000, CRC(c1ae96ad) SHA1(da109602f0fbe9b225cdcd60be0613fd41014864) )
6611
6612   ROM_REGION( 0x10000, "user1", 0 )
6613   ROM_LOAD( "x002306p.u66",   0x00000, 0x10000, CRC(ef36ea67) SHA1(8914ad20526fd63e14d9fa1901e9c779a11eb29d) ) /* Triple Double Bonus Poker */
6614
6615   ROM_REGION( 0x020000, "gfx1", 0 )
6616   ROM_LOAD( "mro-cg2324.u77",  0x00000, 0x8000, CRC(6eceef42) SHA1(a2ddd2a3290c41e510f483c6b633fe0002694d0b) )
6617   ROM_LOAD( "mgo-cg2324.u78",  0x08000, 0x8000, CRC(26d0acbe) SHA1(09a9127deb88185cd5b748bac657461eadb2f48f) )
6618   ROM_LOAD( "mbo-cg2324.u79",  0x10000, 0x8000, CRC(47baee32) SHA1(d8af09022ccb5fc06aa3aa4c200a734b66cbee00) )
6619   ROM_LOAD( "mxo-cg2324.u80",  0x18000, 0x8000, CRC(60449fc0) SHA1(251d1e04786b70c1d2bc7b02f3b69cd58ac76398) )
6620
6621   ROM_REGION( 0x200, "proms", 0 )
6622   ROM_LOAD( "capx2174.u43", 0x0000, 0x0200, CRC(50bdad55) SHA1(958d463c7effb3457c1f9c44c9b7822339c04e8b) )
6623ROM_END
6624
63296625ROM_START( pex2307p ) /* Superboard : Triple Double Bonus Poker (X002307P+XP000112) */
63306626/*
63316627                                                  2-4
r29543r29544
63536649   ROM_LOAD( "capx2174.u43", 0x0000, 0x0200, CRC(50bdad55) SHA1(958d463c7effb3457c1f9c44c9b7822339c04e8b) )
63546650ROM_END
63556651
6652ROM_START( pex2310p ) /* Superboard : Triple Double Bonus Poker (X002310P+XP000112) */
6653/*
6654                                                  2-4
6655                                                   4K    4A
6656                                      5-K 2-4     with   with
6657PayTable   Js+  2PR  3K  STR  FL  FH  4K  4K  4A  A,2-4  2-4  SF  RF  (Bonus)
6658-----------------------------------------------------------------------------
6659 P908BM     1    1    2   4    5   7  50  80 160   400   400  50 400    800
6660  % Range: 90.9-92.9%  Optimum: 94.9%  Hit Frequency: 44.5%
6661     Programs Available: X002310P
6662*/
6663   ROM_REGION( 0x10000, "maincpu", 0 )
6664   ROM_LOAD( "xp000112.u67",   0x00000, 0x10000, CRC(c1ae96ad) SHA1(da109602f0fbe9b225cdcd60be0613fd41014864) )
6665
6666   ROM_REGION( 0x10000, "user1", 0 )
6667   ROM_LOAD( "x002310p.u66",   0x00000, 0x10000, CRC(c006c3f1) SHA1(45c87a2f882147d1d132237cfa12ae47b202264f) ) /* Triple Double Bonus Poker */
6668
6669   ROM_REGION( 0x020000, "gfx1", 0 )
6670   ROM_LOAD( "mro-cg2324.u77",  0x00000, 0x8000, CRC(6eceef42) SHA1(a2ddd2a3290c41e510f483c6b633fe0002694d0b) )
6671   ROM_LOAD( "mgo-cg2324.u78",  0x08000, 0x8000, CRC(26d0acbe) SHA1(09a9127deb88185cd5b748bac657461eadb2f48f) )
6672   ROM_LOAD( "mbo-cg2324.u79",  0x10000, 0x8000, CRC(47baee32) SHA1(d8af09022ccb5fc06aa3aa4c200a734b66cbee00) )
6673   ROM_LOAD( "mxo-cg2324.u80",  0x18000, 0x8000, CRC(60449fc0) SHA1(251d1e04786b70c1d2bc7b02f3b69cd58ac76398) )
6674
6675   ROM_REGION( 0x200, "proms", 0 )
6676   ROM_LOAD( "capx2174.u43", 0x0000, 0x0200, CRC(50bdad55) SHA1(958d463c7effb3457c1f9c44c9b7822339c04e8b) )
6677ROM_END
6678
63566679ROM_START( pex2314p ) /* Superboard : Triple Bonus Poker Plus (X002314P+XP000112) */
63576680/*
63586681                                      5-K 2-4
r29543r29544
67237046   ROM_LOAD( "capx2174.u43", 0x0000, 0x0200, CRC(50bdad55) SHA1(958d463c7effb3457c1f9c44c9b7822339c04e8b) )
67247047ROM_END
67257048
7049ROM_START( pexmp013 ) /* Superboard : 5-in-1 Wingboard (XMP00013) Program in Spanish, Requires Spanish Wingboard CG rom set */
7050/*
7051
7052Known Wingboard compatible program roms:
7053   XMP00013 - Spanish
7054   XMP00014 (not dumped)
7055   XMP00017
7056   XMP00026 - Spanish
7057   XMP00030
7058
7059The CG2346 set seems to support all games supported in CG2298 as well as graphics support for the following XnnnnnnP Data game types:
7060  Triple Double Bonus
7061  Black Jack Bonus (comes up as Back Jack Poker)
7062
7063*/
7064   ROM_REGION( 0x10000, "maincpu", 0 )
7065   ROM_LOAD( "xmp00013.u67",   0x00000, 0x10000, CRC(76ca7c2b) SHA1(cdcbfc648d007362bb50541e6415354c07815d66) )
7066
7067   ROM_REGION( 0x10000, "user1", 0 )
7068   ROM_LOAD( "x000055p.u66",   0x00000, 0x10000, CRC(e06819df) SHA1(36590c4588b8036908e63714fbb3e77d23e60eae) ) /* Deuces Wild Poker */
7069
7070   ROM_REGION( 0x10000, "user2", 0 )
7071   ROM_LOAD( "x000188p.u66",   0x00000, 0x10000, CRC(3eb7580e) SHA1(86f2280542fb8a55767efd391d0fb04a12ed9408) ) /* Standard Draw Poker */
7072
7073   ROM_REGION( 0x10000, "user3", 0 )
7074   ROM_LOAD( "x000516p.u66",   0x00000, 0x10000, CRC(37f84ce7) SHA1(2e5157d02febec0ff31eb5a23254f7c49a486cf5) ) /* Double Bonus Poker */
7075
7076   ROM_REGION( 0x10000, "user4", 0 )
7077   ROM_LOAD( "x002275p.u66",   0x00000, 0x10000, CRC(5ba4f5ab) SHA1(def069025ec4aa340646dfd7cfacc8ce836a210c) ) /* Black Jack Bonus Poker */
7078
7079   ROM_REGION( 0x10000, "user5", 0 )
7080   ROM_LOAD( "x002310p.u66",   0x00000, 0x10000, CRC(c006c3f1) SHA1(45c87a2f882147d1d132237cfa12ae47b202264f) ) /* Triple Double Bonus Poker */
7081
7082   ROM_REGION( 0x040000, "gfx1", 0 )
7083   ROM_LOAD( "mro-cg2346.u77",  0x00000, 0x10000, CRC(3d721779) SHA1(01ac540eddeab5ecdba9b543c69fe7f4b53151a4) ) /* Game titles in English */
7084   ROM_LOAD( "mgo-cg2346.u78",  0x10000, 0x10000, CRC(a4a4856b) SHA1(db0e7528a63c80fab02b463dfb366d32061a93bb) ) /* Poker hands in Spanish */
7085   ROM_LOAD( "mbo-cg2346.u79",  0x20000, 0x10000, CRC(15253b57) SHA1(503b5cb514d9552ed7cf09f236aec63c81cfd828) )
7086   ROM_LOAD( "mxo-cg2346.u80",  0x30000, 0x10000, CRC(68ffb37e) SHA1(b6de07452e52a8c6f8657fbefef081aa9d86dbf0) )
7087
7088   ROM_REGION( 0x200, "proms", 0 )
7089   ROM_LOAD( "capx2346.u43", 0x0000, 0x0200, CRC(8df8ad29) SHA1(2d6a598fdc4290abe83a3d95c0ec8da6eb0f0e84) )
7090ROM_END
7091
67267092ROM_START( pexmp017 ) /* Superboard : 5-in-1 Wingboard (XMP00017) */
67277093/*
67287094
67297095Known Wingboard compatible program roms:
7096   XMP00013 - Spanish
67307097   XMP00014 (not dumped)
67317098   XMP00017
7099   XMP00026 - Spanish
67327100   XMP00030
67337101
67347102XMP00017 is not compatible with:
r29543r29544
68127180/*
68137181
68147182The CG2426 set supersedes both CG2298 & CG2352 and adds graphics support for the following XnnnnnnP Data game types:
7183  Black Jack Bonus
7184  Super Double Bonus
68157185  Triple Double Bonus
6816  Super Double Bonus
68177186
68187187*/
68197188   ROM_REGION( 0x10000, "maincpu", 0 )
68207189   ROM_LOAD( "xmp00017.u67",   0x00000, 0x10000, CRC(129e6eaa) SHA1(1dd2b83a672a618f338b553a6cbd598b6d4ce672) )
68217190
68227191   ROM_REGION( 0x10000, "user1", 0 )
6823   ROM_LOAD( "x000045p.u66",   0x00000, 0x10000, CRC(5412e1f9) SHA1(a962b7731df2f534ea79b6d3e376abf45104df37) ) /* Standard Draw Poker (10's or Better) */
7192   ROM_LOAD( "x002272p.u66",   0x00000, 0x10000, CRC(ee4f27b9) SHA1(1ee105430358ea27badd943bb6b18663e4029388) ) /* Black Jack Bonus Poker */
68247193
68257194   ROM_REGION( 0x10000, "user2", 0 )
68267195   ROM_LOAD( "x002029p.u66",   0x00000, 0x10000, CRC(e2f6fb89) SHA1(4b60b580b00b4268d1cb9065ffe0d21f8fa6a931) ) /* Deuces Wild Bonus Poker */
68277196
68287197   ROM_REGION( 0x10000, "user3", 0 )
6829   ROM_LOAD( "x002307p.u66",   0x00000, 0x10000, CRC(c6d5db70) SHA1(017e1e382fb789e4cd8b410362ad5e82b61f61db) ) /* Triple Double Bonus Poker */
7198   ROM_LOAD( "x002040p.u66",   0x00000, 0x10000, CRC(38acb477) SHA1(894f5861ac84323e50e8972602251f2873988e6c) ) /* Nevada Bonus Poker */
68307199
68317200   ROM_REGION( 0x10000, "user4", 0 )
6832   ROM_LOAD( "x002040p.u66",   0x00000, 0x10000, CRC(38acb477) SHA1(894f5861ac84323e50e8972602251f2873988e6c) ) /* Nevada Bonus Poker */
7201   ROM_LOAD( "x002018p.u66",   0x00000, 0x10000, CRC(a7b79cfa) SHA1(89216fafffc64fda22a016a906483b76174c3f02) ) /* Full House Bonus Poker */
68337202
68347203   ROM_REGION( 0x10000, "user5", 0 )
6835   ROM_LOAD( "x002018p.u66",   0x00000, 0x10000, CRC(a7b79cfa) SHA1(89216fafffc64fda22a016a906483b76174c3f02) ) /* Full House Bonus Poker */
7204   ROM_LOAD( "x002307p.u66",   0x00000, 0x10000, CRC(c6d5db70) SHA1(017e1e382fb789e4cd8b410362ad5e82b61f61db) ) /* Triple Double Bonus Poker */
68367205
68377206   ROM_REGION( 0x040000, "gfx1", 0 )
68387207   ROM_LOAD( "mro-cg2426.u77",  0x00000, 0x10000, CRC(e7622901) SHA1(f653aaf02de840aef56d3efd7680572356e94da7) )
r29543r29544
68447213   ROM_LOAD( "capx2298.u43", 0x0000, 0x0200, CRC(77856036) SHA1(820487c8494965408402ddee6a54511906218e66) )
68457214ROM_END
68467215
7216ROM_START( pexmp026 ) /* Superboard : 5-in-1 Wingboard (XMP00026) Program in Spanish, Requires Spanish Wingboard CG rom set */
7217   ROM_REGION( 0x10000, "maincpu", 0 )
7218   ROM_LOAD( "xmp00026.u67",   0x00000, 0x10000, CRC(0b82387f) SHA1(8348c586cf692c5cbecfe7b52a4271e5aec55027) )
7219
7220   ROM_REGION( 0x10000, "user1", 0 )
7221   ROM_LOAD( "x000242p.u66",   0x00000, 0x10000, CRC(e0292d63) SHA1(8d8ec5dc1abaf8e8a8a7451d3a814023d8195fb5) ) /* Deuces Wild Poker */
7222
7223   ROM_REGION( 0x10000, "user2", 0 )
7224   ROM_LOAD( "x000150p.u66",   0x00000, 0x10000, CRC(d10759fa) SHA1(eae633d03ac9db86520a70825ac0a59ee9ebc819) ) /* Standard Draw Poker */
7225
7226   ROM_REGION( 0x10000, "user3", 0 )
7227   ROM_LOAD( "x002044p.u66",   0x00000, 0x10000, CRC(158af97f) SHA1(452247d981f1202da8c44a31f0d3343184d3db41) ) /* Triple Bonus Poker */
7228
7229   ROM_REGION( 0x10000, "user4", 0 )
7230   ROM_LOAD( "x002038p.u66",   0x00000, 0x10000, CRC(58d01ba5) SHA1(6d4cde9c9e55967db2b661c7123cce9958a00639) ) /* Nevada Bonus Poker */
7231
7232   ROM_REGION( 0x10000, "user5", 0 )
7233   ROM_LOAD( "x002306p.u66",   0x00000, 0x10000, CRC(ef36ea67) SHA1(8914ad20526fd63e14d9fa1901e9c779a11eb29d) ) /* Triple Double Bonus Poker */
7234
7235   ROM_REGION( 0x040000, "gfx1", 0 )
7236   ROM_LOAD( "mro-cg2346.u77",  0x00000, 0x10000, CRC(3d721779) SHA1(01ac540eddeab5ecdba9b543c69fe7f4b53151a4) ) /* Game titles in English */
7237   ROM_LOAD( "mgo-cg2346.u78",  0x10000, 0x10000, CRC(a4a4856b) SHA1(db0e7528a63c80fab02b463dfb366d32061a93bb) ) /* Poker hands in Spanish */
7238   ROM_LOAD( "mbo-cg2346.u79",  0x20000, 0x10000, CRC(15253b57) SHA1(503b5cb514d9552ed7cf09f236aec63c81cfd828) )
7239   ROM_LOAD( "mxo-cg2346.u80",  0x30000, 0x10000, CRC(68ffb37e) SHA1(b6de07452e52a8c6f8657fbefef081aa9d86dbf0) )
7240
7241   ROM_REGION( 0x200, "proms", 0 )
7242   ROM_LOAD( "capx2346.u43", 0x0000, 0x0200, CRC(8df8ad29) SHA1(2d6a598fdc4290abe83a3d95c0ec8da6eb0f0e84) )
7243ROM_END
7244
68477245ROM_START( pexmp030 ) /* Superboard : 5-in-1 Wingboard (XMP00030) */
68487246   ROM_REGION( 0x10000, "maincpu", 0 )
68497247   ROM_LOAD( "xmp00030.u67",   0x00000, 0x10000, CRC(da3fcb6f) SHA1(114e581e5ebb5c40c3f3da2784122d3281f269ee) ) /*  11/12/00   @ IGT  L01-0197  */
r29543r29544
69387336GAMEL(1987, pepp0224,  pepp0055, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0224) Deuces Wild Poker (set 1)",     0, layout_pe_poker )
69397337GAMEL(1987, pepp0224a, pepp0055, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0224) Deuces Wild Poker (set 2)",     0, layout_pe_poker )
69407338GAMEL(1987, pepp0230,  pepp0002, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0230) Standard Draw Poker",           0, layout_pe_poker )
7339GAMEL(1987, pepp0242,  pepp0055, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0242) Deuces Wild Poker (International English/Spanish)", 0, layout_pe_poker )
69417340GAMEL(1987, pepp0249,  pepp0055, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0249) Deuces Wild Poker",             0, layout_pe_poker )
69427341GAMEL(1987, pepp0250,  0,        peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0250) Double Down Stud Poker",        0, layout_pe_poker )
69437342GAMEL(1987, pepp0265,  pepp0158, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0265) 4 of a Kind Bonus Poker (set 1)",  0, layout_pe_poker )
69447343GAMEL(1987, pepp0265a, pepp0158, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0265) 4 of a Kind Bonus Poker (set 2)",  0, layout_pe_poker )
69457344GAMEL(1987, pepp0274,  pepp0002, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0274) Standard Draw Poker",           0, layout_pe_poker )
7345GAMEL(1987, pepp0288,  pepp0002, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0288) Standard Draw Poker (Spanish)", 0, layout_pe_poker )
69467346GAMEL(1987, pepp0290,  pepp0055, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0290) Deuces Wild Poker",             0, layout_pe_poker )
69477347GAMEL(1987, pepp0291,  pepp0055, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0291) Deuces Wild Poker",             0, layout_pe_poker )
69487348GAMEL(1987, pepp0409,  pepp0158, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0409) 4 of a Kind Bonus Poker",       0, layout_pe_poker )
r29543r29544
69557355GAMEL(1987, pepp0426,  pepp0053, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0426) Joker Poker",                   0, layout_pe_poker )
69567356GAMEL(1987, pepp0428,  pepp0053, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0428) Joker Poker",                   0, layout_pe_poker )
69577357GAMEL(1987, pepp0429,  pepp0053, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0429) Joker Poker (Aces or Better)",  0, layout_pe_poker )
7358GAMEL(1987, pepp0431,  pepp0127, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0431) Deuces Joker Wild Poker",       0, layout_pe_poker )
69587359GAMEL(1987, pepp0434,  0,        peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0434) Bonus Poker Deluxe",            0, layout_pe_poker )
69597360GAMEL(1987, pepp0447,  pepp0002, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0447) Standard Draw Poker (set 1)",   0, layout_pe_poker )
69607361GAMEL(1987, pepp0447a, pepp0002, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0447) Standard Draw Poker (set 2)",   0, layout_pe_poker )
69617362GAMEL(1987, pepp0449,  pepp0002, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0449) Standard Draw Poker",           0, layout_pe_poker )
7363GAMEL(1987, pepp0449a, pepp0002, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0449) Standard Draw Poker (International English/Spanish)", 0, layout_pe_poker )
69627364GAMEL(1987, pepp0452,  0,        peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0452) Double Deuces Wild Poker",      0, layout_pe_poker )
69637365GAMEL(1987, pepp0454,  pepp0434, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0454) Bonus Poker Deluxe",            0, layout_pe_poker )
69647366GAMEL(1987, pepp0455,  pepp0053, peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0455) Joker Poker",                   0, layout_pe_poker )
r29543r29544
70337435GAMEL(1995, pex0054p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000054P+XP000038) Deuces Wild Poker",  0, layout_pe_poker )
70347436GAMEL(1995, pex0055p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000019) Deuces Wild Poker",  0, layout_pe_poker )
70357437GAMEL(1995, pex0055pa, pex0055p,  peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000022) Deuces Wild Poker (The Orleans)", 0, layout_pe_poker )
7036GAMEL(1995, pex0055pb, pex0055p,  peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000023) Deuces Wild Poker", 0, layout_pe_poker )
7438GAMEL(1995, pex0055pb, pex0055p,  peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000023) Deuces Wild Poker (The Fun Ships)", 0, layout_pe_poker )
70377439GAMEL(1995, pex0055pc, pex0055p,  peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000028) Deuces Wild Poker",  0, layout_pe_poker )
70387440GAMEL(1995, pex0055pd, pex0055p,  peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000035) Deuces Wild Poker",  0, layout_pe_poker )
70397441GAMEL(1995, pex0055pe, pex0055p,  peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000038) Deuces Wild Poker",  0, layout_pe_poker )
r29543r29544
70517453GAMEL(1995, pex0055pq, pex0055p,  peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000112) Deuces Wild Poker",  0, layout_pe_poker )
70527454GAMEL(1995, pex0055pr, pex0055p,  peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000126) Deuces Wild Poker",  0, layout_pe_poker )
70537455GAMEL(1995, pex0060p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000060P+XP000038) Standard Draw Poker", 0, layout_pe_poker )
7456GAMEL(1995, pex0150p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000150P+XP000038) Standard Draw Poker", 0, layout_pe_poker )
70547457GAMEL(1995, pex0158p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000158P+XP000038) 4 of a Kind Bonus Poker", 0, layout_pe_poker )
70557458GAMEL(1995, pex0171p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000171P+XP000038) Joker Poker",        0, layout_pe_poker )
70567459GAMEL(1995, pex0188p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000188P+XP000038) Standard Draw Poker", 0, layout_pe_poker )
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70597462GAMEL(1995, pex0203p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000203P+XP000038) 4 of a Kind Bonus Poker", 0, layout_pe_poker )
70607463GAMEL(1995, pex0224p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000224P+XP000053) Deuces Wild Poker",  0, layout_pe_poker )
70617464GAMEL(1995, pex0225p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000225P+XP000079) Dueces Joker Wild Poker", 0,layout_pe_poker )
7465GAMEL(1995, pex0242p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000242P+XP000053) Deuces Wild Poker",  0, layout_pe_poker )
70627466GAMEL(1995, pex0265p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000265P+XP000038) 4 of a Kind Bonus Poker", 0, layout_pe_poker )
70637467GAMEL(1995, pex0291p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000291P+XP000053) Deuces Wild Poker",  0, layout_pe_poker )
70647468GAMEL(1995, pex0417p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000417P+XP000053) Deuces Wild Poker",  0, layout_pe_poker )
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70757479GAMEL(1995, pex0508p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000508P+XP000038) Loose Deuce Deuces Wild! Poker", 0, layout_pe_poker )
70767480GAMEL(1995, pex0514p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000514P+XP000038) Double Bonus Poker", 0, layout_pe_poker )
70777481GAMEL(1995, pex0515p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000515P+XP000038) Double Bonus Poker", 0, layout_pe_poker )
7482GAMEL(1995, pex0516p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000516P+XP000038) Double Bonus Poker", 0, layout_pe_poker )
70787483GAMEL(1995, pex0536p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000536P+XP000038) Joker Poker",        0, layout_pe_poker )
70797484GAMEL(1995, pex0537p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000537P+XP000038) Standard Draw Poker", 0, layout_pe_poker )
70807485GAMEL(1995, pex0568p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X000568P+XP000038) Joker Poker",        0, layout_pe_poker )
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70927497GAMEL(1995, pex2031p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002031P+XP000112) Lucky Deal Poker",   0, layout_pe_poker )
70937498GAMEL(1995, pex2035p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002035P+XP000112) White Hot Aces Poker", 0, layout_pe_poker )
70947499GAMEL(1995, pex2036p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002036P+XP000112) White Hot Aces Poker", 0, layout_pe_poker )
7500GAMEL(1995, pex2038p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002038P+XP000038) Nevada Bonus Poker", 0, layout_pe_poker )
70957501GAMEL(1995, pex2040p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002040P+XP000038) Nevada Bonus Poker", 0, layout_pe_poker )
70967502GAMEL(1995, pex2042p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002042P+XP000038) Triple Bonus Poker", 0, layout_pe_poker )
70977503GAMEL(1995, pex2043p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002043P+XP000038) Triple Bonus Poker", 0, layout_pe_poker )
7504GAMEL(1995, pex2044p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002044P+XP000038) Triple Bonus Poker", 0, layout_pe_poker )
70987505GAMEL(1995, pex2045p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002045P+XP000038) Triple Bonus Poker", 0, layout_pe_poker )
70997506GAMEL(1995, pex2066p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002066P+XP000038) Double Double Bonus Poker", 0, layout_pe_poker )
71007507GAMEL(1995, pex2067p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002067P+XP000038) Double Double Bonus Poker", 0, layout_pe_poker )
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71127519GAMEL(1995, pex2245pa, pex2245p,  peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002245P+XP000079) Standard Draw Poker", 0,layout_pe_poker )
71137520GAMEL(1995, pex2250p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002250P+XP000050) Shockwave Poker",    0, layout_pe_poker )
71147521GAMEL(1995, pex2251p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002251P+XP000050) Shockwave Poker",    0, layout_pe_poker )
7522GAMEL(1995, pex2272p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002272P+XP000055) Black Jack Bonus Poker", 0, layout_pe_poker )
7523GAMEL(1995, pex2275p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002275P+XP000055) Black Jack Bonus Poker", 0, layout_pe_poker )
71157524GAMEL(1995, pex2283p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002283P+XP000057) Dealt Deuces Wild Bonus Poker", 0, layout_pe_poker ) /* Undumped color CAP but should have correct colors anyways */
71167525GAMEL(1995, pex2284p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002284P+XP000057) Barbaric Decues Wild Bonus Poker", 0, layout_pe_poker ) /* Undumped color CAP but should have correct colors anyways */
71177526GAMEL(1995, pex2302p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002302P+XP000038) Bonus Poker Deluxe", 0, layout_pe_poker )
71187527GAMEL(1995, pex2303p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002303P+XP000112) White Hot Aces Poker", 0, layout_pe_poker )
7528GAMEL(1995, pex2306p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002306P+XP000112) Triple Double Bonus Poker", 0, layout_pe_poker )
71197529GAMEL(1995, pex2307p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002307P+XP000112) Triple Double Bonus Poker", 0, layout_pe_poker )
7530GAMEL(1995, pex2310p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002310P+XP000112) Triple Double Bonus Poker", 0, layout_pe_poker )
71207531GAMEL(1995, pex2314p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002314P+XP000112) Triple Bonus Poker Plus", 0, layout_pe_poker )
71217532GAMEL(1995, pex2374p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002374P+XP000112) Super Aces Poker (Horseshoe)", 0, layout_pe_poker )
71227533GAMEL(1995, pex2377p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002377P+XP000112) Super Double Bonus Poker", 0, layout_pe_poker )
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71357546GAMEL(1995, pexm008p,  0,        peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (XM00008P+XMP00006) Multi-Poker",        GAME_IMPERFECT_GRAPHICS, layout_pe_poker ) /* Needs CG2228 graphics roms for correct MENU game banners */
71367547
71377548/* Superboard : Multi-Poker (Wingboard) */
7549GAMEL(1995, pexmp013,  0,        peplus,  peplus_poker, peplus_state, peplussbw,ROT0,  "IGT - International Game Technology", "Player's Edge Plus (XMP00013) 5-in-1 Wingboard (CG2346) - Spanish", 0, layout_pe_poker )
71387550GAMEL(1995, pexmp017,  0,        peplus,  peplus_poker, peplus_state, peplussbw,ROT0,  "IGT - International Game Technology", "Player's Edge Plus (XMP00017) 5-in-1 Wingboard (CG2298)",   0, layout_pe_poker )
71397551GAMEL(1995, pexmp017a, pexmp017, peplus,  peplus_poker, peplus_state, peplussbw,ROT0,  "IGT - International Game Technology", "Player's Edge Plus (XMP00017) 5-in-1 Wingboard (CG2352)",   0, layout_pe_poker )
71407552GAMEL(1995, pexmp017b, pexmp017, peplus,  peplus_poker, peplus_state, peplussbw,ROT0,  "IGT - International Game Technology", "Player's Edge Plus (XMP00017) 5-in-1 Wingboard (CG2426)",   0, layout_pe_poker )
7553GAMEL(1995, pexmp026,  0,        peplus,  peplus_poker, peplus_state, peplussbw,ROT0,  "IGT - International Game Technology", "Player's Edge Plus (XMP00026) 5-in-1 Wingboard (CG2346) - Spanish", 0, layout_pe_poker )
71417554GAMEL(1995, pexmp030,  0,        peplus,  peplus_poker, peplus_state, peplussbw,ROT0,  "IGT - International Game Technology", "Player's Edge Plus (XMP00030) 5-in-1 Wingboard (CG2426)",   0, layout_pe_poker )
71427555
71437556/* Superboard : Slots machine */
branches/new_menus/src/mame/drivers/playch10.c
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660660      device.execute().set_input_line(INPUT_LINE_NMI, PULSE_LINE);
661661}
662662
663static const nesapu_interface nes_config =
664{
665   "cart"
666};
667
668663static MACHINE_CONFIG_START( playch10, playch10_state )
669664   // basic machine hardware
670665   MCFG_CPU_ADD("maincpu", Z80, 8000000/2) // 4 MHz
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705700   // sound hardware
706701   MCFG_SPEAKER_STANDARD_MONO("mono")
707702   MCFG_SOUND_ADD("nesapu", NES_APU, N2A03_DEFAULTCLOCK)
708   MCFG_SOUND_CONFIG(nes_config)
703   MCFG_NES_APU_CPU("cart")
709704   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
710705
711706   MCFG_DAC_ADD("dac")
branches/new_menus/src/mame/drivers/snesb.c
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144144
145145
146146#include "emu.h"
147#include "cpu/spc700/spc700.h"
148#include "cpu/g65816/g65816.h"
149147#include "includes/snes.h"
150#include "audio/snes_snd.h"
151148
152149
153150class snesb_state : public snes_state
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634631   MCFG_SCREEN_RAW_PARAMS(DOTCLK_NTSC, SNES_HTOTAL, 0, SNES_SCR_WIDTH, SNES_VTOTAL_NTSC, 0, SNES_SCR_HEIGHT_NTSC)
635632   MCFG_SCREEN_UPDATE_DRIVER( snes_state, screen_update )
636633
634   MCFG_DEVICE_ADD("ppu", SNES_PPU, 0)
635   MCFG_SNES_PPU_OPENBUS_CB(READ8(snes_state, snes_open_bus_r))
636   MCFG_VIDEO_SET_SCREEN("screen")
637
637638   /* sound hardware */
638639   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
639640   MCFG_SOUND_ADD("spc700", SNES, 0)
branches/new_menus/src/mame/drivers/rockrage.c
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6464WRITE8_MEMBER(rockrage_state::rockrage_bankswitch_w)
6565{
6666   /* bits 4-6 = bank number */
67   membank("bank1")->set_entry((data & 0x70) >> 4);
67   m_rombank->set_entry((data & 0x70) >> 4);
6868
6969   /* bits 0 & 1 = coin counters */
7070   coin_counter_w(machine(), 0,data & 0x01);
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107107   AM_RANGE(0x2f00, 0x2f00) AM_WRITE(rockrage_vreg_w)                          /* ??? */
108108   AM_RANGE(0x2f40, 0x2f40) AM_WRITE(rockrage_bankswitch_w)                    /* bankswitch control */
109109   AM_RANGE(0x4000, 0x5fff) AM_RAM                                             /* RAM */
110   AM_RANGE(0x6000, 0x7fff) AM_ROMBANK("bank1")                                        /* banked ROM */
110   AM_RANGE(0x6000, 0x7fff) AM_ROMBANK("rombank")                              /* banked ROM */
111111   AM_RANGE(0x8000, 0xffff) AM_ROM                                             /* ROM */
112112ADDRESS_MAP_END
113113
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189189
190190static const gfx_layout charlayout =
191191{
192   8,8,            /* 8*8 characters */
193   0x20000/16,     /* 8192 characters */
194   4,              /* 4 bpp */
192   8,8,            /* 8 x 8 characters */
193   0x40000/32,     /* 8192 characters */
194   4,              /* 4bpp */
195195   { 0, 1, 2, 3 }, /* the four bitplanes are packed in one nibble */
196   { 0*4, 1*4, 0x20000*8+0*4, 0x20000*8+1*4, 2*4, 3*4, 0x20000*8+2*4, 0x20000*8+3*4 },
197   { 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16 },
198   16*8        /* every char takes 16 consecutive bytes */
196   { 2*4, 3*4, 0*4, 1*4, 6*4, 7*4, 4*4, 5*4 },
197   { 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32 },
198   32*8            /* every character takes 32 consecutive bytes */
199199};
200200
201201static const gfx_layout spritelayout =
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224224{
225225   UINT8 *ROM = memregion("maincpu")->base();
226226
227   membank("bank1")->configure_entries(0, 8, &ROM[0x10000], 0x2000);
227   m_rombank->configure_entries(0, 8, &ROM[0x10000], 0x2000);
228228
229229   save_item(NAME(m_vreg));
230230   save_item(NAME(m_layer_colorbase));
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300300   ROM_LOAD( "620k03.11c", 0x08000, 0x08000, CRC(9fbefe82) SHA1(ab42b7e519a0dd08f2249dad0819edea0976f39a) )
301301
302302   ROM_REGION( 0x040000, "gfx1", 0 )
303   ROM_LOAD( "620k06.rom", 0x000000, 0x20000, CRC(7fa2c57c) SHA1(8c5d85c31dc26cb59a012ebb1ea195c3db80cda8)  )  /* tiles */
304   ROM_LOAD( "620k05.rom", 0x020000, 0x20000, CRC(145d387c) SHA1(4fb0c54f9a218d512d8aec09ef995494a06912d6)  ) /* Both World & Japan use the same "K" code for these??? */
303   ROM_LOAD16_BYTE( "620k05.rom", 0x00000, 0x20000, CRC(145d387c) SHA1(4fb0c54f9a218d512d8aec09ef995494a06912d6)  )  /* tiles */
304   ROM_LOAD16_BYTE( "620k06.rom", 0x00001, 0x20000, CRC(7fa2c57c) SHA1(8c5d85c31dc26cb59a012ebb1ea195c3db80cda8)  ) /* Both World & Japan use the same "K" code for these??? */
305305
306306   ROM_REGION( 0x040000, "gfx2", 0 )
307307   ROM_LOAD( "620k11.rom", 0x000000, 0x20000, CRC(70449239) SHA1(07653ea3bfe0063c9d2b2102ac52a1b50fc2971e) )   /* sprites */
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325325   ROM_LOAD( "620k03.11c", 0x08000, 0x08000, CRC(9fbefe82) SHA1(ab42b7e519a0dd08f2249dad0819edea0976f39a) ) /* Same rom but labeled as ver "G" */
326326
327327   ROM_REGION( 0x040000, "gfx1", 0 )
328   ROM_LOAD( "620d06a.15g", 0x000000, 0x10000, CRC(8cc05d4b) SHA1(0d6fef98bdc4d299229de4e0044241aedee83b85) )  /* tiles */
329   ROM_LOAD( "620d06b.15f", 0x010000, 0x10000, CRC(3892d41d) SHA1(c49f2e61f24a59be4e59e2f3c60e731b8a05ddd3) )
330   ROM_LOAD( "620d05a.16g", 0x020000, 0x10000, CRC(4d53fde9) SHA1(941fb6c94922727516945330b4b738aa052f7734) )
331   ROM_LOAD( "620d05b.16f", 0x030000, 0x10000, CRC(69f4599f) SHA1(664581874d74ed7bf59bde6730799e15f4e0144d) )
328   ROM_LOAD16_BYTE( "620d05a.16g", 0x00000, 0x10000, CRC(4d53fde9) SHA1(941fb6c94922727516945330b4b738aa052f7734) )  /* tiles */
329   ROM_LOAD16_BYTE( "620d06a.15g", 0x00001, 0x10000, CRC(8cc05d4b) SHA1(0d6fef98bdc4d299229de4e0044241aedee83b85) )
330   ROM_LOAD16_BYTE( "620d05b.16f", 0x20000, 0x10000, CRC(69f4599f) SHA1(664581874d74ed7bf59bde6730799e15f4e0144d) )
331   ROM_LOAD16_BYTE( "620d06b.15f", 0x20001, 0x10000, CRC(3892d41d) SHA1(c49f2e61f24a59be4e59e2f3c60e731b8a05ddd3) )
332332
333333   ROM_REGION( 0x040000, "gfx2", 0 )
334334   ROM_LOAD( "620g11a.7g", 0x000000, 0x10000, CRC(0ef40c2c) SHA1(2c0b7e611333a072ebcef60c1985211d5936bf66) )   /* sprites */
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354354   ROM_LOAD( "620k03.11c", 0x08000, 0x08000, CRC(9fbefe82) SHA1(ab42b7e519a0dd08f2249dad0819edea0976f39a) )
355355
356356   ROM_REGION( 0x040000, "gfx1", 0 )
357   ROM_LOAD( "620k06.15g", 0x000000, 0x20000, CRC(c0e2b35c) SHA1(fb37a151188f27f883fed5fdfb0094c3efa9470d) )   /* tiles */
358   ROM_LOAD( "620k05.16g", 0x020000, 0x20000, CRC(ca9d9346) SHA1(fee8d98def802f312c6cd0ec751c67aa18acfacd) ) /* Both World & Japan use the same "K" code for these??? */
357   ROM_LOAD16_BYTE( "620k05.16g", 0x00000, 0x20000, CRC(ca9d9346) SHA1(fee8d98def802f312c6cd0ec751c67aa18acfacd) )   /* tiles */
358   ROM_LOAD16_BYTE( "620k06.15g", 0x00001, 0x20000, CRC(c0e2b35c) SHA1(fb37a151188f27f883fed5fdfb0094c3efa9470d) ) /* Both World & Japan use the same "K" code for these??? */
359359
360360   ROM_REGION( 0x040000, "gfx2", 0 )
361361   ROM_LOAD( "620k11.7g",  0x000000, 0x20000, CRC(7430f6e9) SHA1(5d488c7b7b0eb4e502b3e566ac102cd3267e8568) )   /* sprites */
branches/new_menus/src/mame/drivers/pacman.c
r29543r29544
32983298GFXDECODE_END
32993299
33003300
3301
33023301/*************************************
33033302 *
3304 *  Sound interfaces
3305 *
3306 *************************************/
3307
3308static const namco_interface namco_config =
3309{
3310   3,          /* number of voices */
3311   0           /* stereo */
3312};
3313
3314
3315/*************************************
3316 *
33173303 *  Machine drivers
33183304 *
33193305 *************************************/
r29543r29544
33443330   MCFG_SPEAKER_STANDARD_MONO("mono")
33453331
33463332   MCFG_SOUND_ADD("namco", NAMCO, MASTER_CLOCK/6/32)
3347   MCFG_SOUND_CONFIG(namco_config)
3333   MCFG_NAMCO_AUDIO_VOICES(3)
33483334   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
33493335MACHINE_CONFIG_END
33503336
branches/new_menus/src/mame/drivers/tceptor.c
r29543r29544
323323
324324/*******************************************************************/
325325
326static const namco_interface namco_config =
327{
328   8,          /* number of voices */
329   1           /* stereo */
330};
331
332
333/*******************************************************************/
334
335326void tceptor_state::machine_start()
336327{
337328   save_item(NAME(m_m6809_irq_enable));
r29543r29544
424415   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
425416
426417   MCFG_SOUND_ADD("namco", NAMCO_CUS30, 49152000/2048)
427   MCFG_SOUND_CONFIG(namco_config)
418   MCFG_NAMCO_AUDIO_VOICES(8)
419   MCFG_NAMCO_AUDIO_STEREO(1)
428420   MCFG_SOUND_ROUTE(0, "lspeaker", 0.40)
429421   MCFG_SOUND_ROUTE(1, "rspeaker", 0.40)
430422
branches/new_menus/src/mame/drivers/chihiro.c
r29543r29544
416416   void dword_write_le(UINT8 *addr,UINT32 d);
417417   void word_write_le(UINT8 *addr,UINT16 d);
418418   void debug_generate_irq(int irq,bool active);
419   void debug_grab_texture(int type, char *filename);
419420
420421   void vblank_callback(screen_device &screen, bool state);
421422   UINT32 screen_update_callback(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
r29543r29544
445446      UINT32 words[256/4];
446447   } smbusst;
447448   struct apu_state {
448      UINT32 memory0_sgaddress;
449      UINT32 memory0_sgblocks;
450      UINT32 memory0_address;
451      UINT32 memory1_sgaddress;
452      UINT32 memory1_sgblocks;
449      UINT32 memory[0x60000/4];
450      UINT32 gpdsp_sgaddress; // global processor scatter-gather
451      UINT32 gpdsp_sgblocks;
452      UINT32 gpdsp_address;
453      UINT32 epdsp_sgaddress; // encoder processor scatter-gather
454      UINT32 epdsp_sgblocks;
455      UINT32 unknown_sgaddress;
456      UINT32 unknown_sgblocks;
457      int voice_number;
458      UINT32 voices_heap_blockaddr[1024];
459      UINT64 voices_active[4]; //one bit for each voice: 1 playing 0 not
460      UINT32 voicedata_address;
461      int voices_frequency[256]; // sample rate
462      int voices_position[256]; // position in samples * 1000
463      int voices_position_start[256]; // position in samples * 1000
464      int voices_position_end[256]; // position in samples * 1000
465      int voices_position_increment[256]; // position increment every 1ms * 1000
453466      emu_timer *timer;
454467      address_space *space;
455468   } apust;
r29543r29544
503516      combiner.used=0;
504517      combiner.lock=osd_lock_alloc();
505518      enabled_vertex_attributes=0;
506      memset(words_vertex_attributes,0,sizeof(words_vertex_attributes));
519      indexesleft_count = 0;
520      debug_grab_texttype = -1;
521      debug_grab_textfile = NULL;
522      memset(words_vertex_attributes, 0, sizeof(words_vertex_attributes));
507523   }
508524   DECLARE_READ32_MEMBER( geforce_r );
509525   DECLARE_WRITE32_MEMBER( geforce_w );
r29543r29544
546562   void computedilated(void);
547563   void putpixtex(int xp,int yp,int up,int vp);
548564   int toggle_register_combiners_usage();
565   void debug_grab_texture(int type, const char *filename);
549566   void savestate_items();
550567
551568   struct {
r29543r29544
570587      int rectangle_pitch;
571588      void *buffer;
572589   } texture[4];
590   int primitives_count;
591   int indexesleft_count;
592   UINT32 indexesleft[8];
573593   struct {
574594      float variable_A[4]; // 0=R 1=G 2=B 3=A
575595      float variable_B[4];
r29543r29544
673693      int used;
674694      osd_lock *lock;
675695   } combiner;
696   struct {
697      float modelview[16];
698      float modelview_inverse[16];
699      float projection[16];
700      float translate[4];
701      float scale[4];
702   } matrix;
703   struct {
704      UINT32 instruction[1024];
705      int instructions;
706      int upload_instruction;
707      UINT32 parameter[1024];
708      int upload_parameter;
709   } vertexprogram;
676710   int enabled_vertex_attributes;
677711   int words_vertex_attributes[16];
678712   bitmap_rgb32 fb;
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680714   UINT32 dilated1[16][2048];
681715   int dilatechose[256];
682716   nvidia_object_data *objectdata;
717   int debug_grab_texttype;
718   char *debug_grab_textfile;
683719
684720   enum NV2A_BEGIN_END {
685721      STOP=0,
r29543r29544
10521088      debug_console_printf(machine,"Register combiners disabled\n");
10531089}
10541090
1091static void grab_texture_command(running_machine &machine, int ref, int params, const char **param)
1092{
1093   UINT64 type;
1094   chihiro_state *chst = machine.driver_data<chihiro_state>();
1095
1096   if (params < 2)
1097      return;
1098   if (!debug_command_parameter_number(machine, param[0], &type))
1099      return;
1100   if ((param[1][0] == 0) || (strlen(param[1]) > 127))
1101      return;
1102   chst->nvidia_nv2a->debug_grab_texture((int)type,param[1]);
1103}
1104
10551105static void help_command(running_machine &machine, int ref, int params, const char **param)
10561106{
10571107   debug_console_printf(machine,"Available Chihiro commands:\n");
r29543r29544
10621112   debug_console_printf(machine,"  chihiro curthread -- Print information about current thread\n");
10631113   debug_console_printf(machine,"  chihiro irq,<number> -- Generate interrupt with irq number 0-15\n");
10641114   debug_console_printf(machine,"  chihiro nv2a_combiners -- Toggle use of register combiners\n");
1115   debug_console_printf(machine,"  chihiro grab_texture,<type>,<filename> -- Save to <filename> the next used texture of type <type>\n");
10651116   debug_console_printf(machine,"  chihiro help -- this list\n");
10661117}
10671118
r29543r29544
10831134      generate_irq_command(machine,ref,params-1,param+1);
10841135   else if (strcmp("nv2a_combiners",param[0]) == 0)
10851136      nv2a_combiners_command(machine,ref,params-1,param+1);
1137   else if (strcmp("grab_texture", param[0]) == 0)
1138      grab_texture_command(machine, ref, params - 1, param + 1);
10861139   else
10871140      help_command(machine,ref,params-1,param+1);
10881141}
r29543r29544
12561309
12571310UINT32 nv2a_renderer::texture_get_texel(int number,int x,int y)
12581311{
1259   UINT32 to,s,c,sa,ca;
1260   UINT32 a4r4g4b4,a1r5g5b5,r5g6b5;
1261   int bx,by;
1262   int color0,color1,color0m2,color1m2;
1312   UINT32 to, s, c, sa, ca;
1313   UINT32 a4r4g4b4, a1r5g5b5, r5g6b5;
1314   int bx, by;
1315   int color0, color1, color0m2, color1m2, alpha0, alpha1;
12631316   UINT32 codes;
12641317   UINT64 alphas;
1265   int cr,cg,cb;
1318   int cr, cg, cb;
12661319
1320   // force to [0,size-1]
1321   x = (unsigned int)x & (texture[number].sizeu - 1);
1322   y = (unsigned int)y & (texture[number].sizev - 1);
12671323   switch (texture[number].format) {
1268      case A8R8G8B8:
1269         to=dilated0[texture[number].dilate][x]+dilated1[texture[number].dilate][y]; // offset of texel in texture memory
1270         return *(((UINT32 *)texture[number].buffer)+to); // get texel color
1271      case DXT1:
1272         bx=x >> 2;
1273         by=y >> 2;
1274         x=x & 3;
1275         y=y & 3;
1276         //to=dilated0[texture[number].dilate][bx]+dilated1[texture[number].dilate][by]; // swizzle 4x4 blocks ?
1277         to=bx+by*(texture[number].sizeu >> 2);
1278         color0=*((UINT16 *)(((UINT64 *)texture[number].buffer)+to)+0);
1279         color1=*((UINT16 *)(((UINT64 *)texture[number].buffer)+to)+1);
1280         codes=*((UINT32 *)(((UINT64 *)texture[number].buffer)+to)+1);
1281         s=(y << 3)+(x << 1);
1282         c=(codes >> s) & 3;
1283         c=c+(color0 > color1 ? 0 : 4);
1284         color0m2=color0 << 1;
1285         color1m2=color1 << 1;
1286         switch (c) {
1287            case 0:
1288               return 0xff000000+convert_r5g6b5_r8g8b8(color0);
1289               break;
1290            case 1:
1291               return 0xff000000+convert_r5g6b5_r8g8b8(color1);
1292               break;
1293            case 2:
1294               cb=pal5bit(((color0m2 & 0x003e)+(color1 & 0x001f))/3);
1295               cg=pal6bit(((color0m2 & 0x0fc0)+(color1 & 0x07e0))/3 >> 5);
1296               cr=pal5bit(((color0m2 & 0x1f000)+color1)/3 >> 11);
1297               return 0xff000000|(cr<<16)|(cg<<8)|(cb);
1298               break;
1299            case 3:
1300               cb=pal5bit(((color1m2 & 0x003e)+(color0 & 0x001f))/3);
1301               cg=pal6bit(((color1m2 & 0x0fc0)+(color0 & 0x07e0))/3 >> 5);
1302               cr=pal5bit(((color1m2 & 0x1f000)+color0)/3 >> 11);
1303               return 0xff000000|(cr<<16)|(cg<<8)|(cb);
1304               break;
1305            case 4:
1306               return 0xff000000+convert_r5g6b5_r8g8b8(color0);
1307               break;
1308            case 5:
1309               return 0xff000000+convert_r5g6b5_r8g8b8(color1);
1310               break;
1311            case 6:
1312               cb=pal5bit(((color0 & 0x001f)+(color1 & 0x001f))/2);
1313               cg=pal6bit(((color0 & 0x07e0)+(color1 & 0x07e0))/2 >> 5);
1314               cr=pal5bit((color0+color1)/2 >> 11);
1315               return 0xff000000|(cr<<16)|(cg<<8)|(cb);
1316               break;
1317            default:
1318               return 0xff000000;
1319               break;
1320         }
1321      case DXT3:
1322         bx=x >> 2;
1323         by=y >> 2;
1324         x=x & 3;
1325         y=y & 3;
1326         //to=(dilated0[texture[number].dilate][bx]+dilated1[texture[number].dilate][by]) << 1; // swizzle 4x4 blocks ?
1327         to=(bx+by*(texture[number].sizeu >> 2)) << 1;
1328         color0=*((UINT16 *)(((UINT64 *)texture[number].buffer)+to)+4);
1329         color1=*((UINT16 *)(((UINT64 *)texture[number].buffer)+to)+5);
1330         codes=*((UINT32 *)(((UINT64 *)texture[number].buffer)+to)+3);
1331         alphas=*(((UINT64 *)texture[number].buffer)+to);
1332         s=(y << 3)+(x << 1);
1333         sa=((y << 2)+x) << 2;
1334         c=(codes >> s) & 3;
1335         ca=(alphas >> sa) & 15;
1336         switch (c) {
1337            case 0:
1338               return ((ca+(ca << 4)) << 24)+convert_r5g6b5_r8g8b8(color0);
1339               break;
1340            case 1:
1341               return ((ca+(ca << 4)) << 24)+convert_r5g6b5_r8g8b8(color1);
1342               break;
1343            case 2:
1344               cb=pal5bit(((color0 & 0x001f)+(color1 & 0x001f))/2);
1345               cg=pal6bit(((color0 & 0x07e0)+(color1 & 0x07e0))/2 >> 5);
1346               cr=pal5bit((color0+color1)/2 >> 11);
1347               return ((ca+(ca << 4)) << 24)|(cr<<16)|(cg<<8)|(cb);
1348               break;
1349            default:
1350               return (ca+(ca << 4)) << 24;
1351               break;
1352         }
1324   case A8R8G8B8:
1325      to = dilated0[texture[number].dilate][x] + dilated1[texture[number].dilate][y]; // offset of texel in texture memory
1326      return *(((UINT32 *)texture[number].buffer) + to); // get texel color
1327   case DXT1:
1328      bx = x >> 2;
1329      by = y >> 2;
1330      x = x & 3;
1331      y = y & 3;
1332      to = bx + by*(texture[number].sizeu >> 2);
1333      color0 = *((UINT16 *)(((UINT64 *)texture[number].buffer) + to) + 0);
1334      color1 = *((UINT16 *)(((UINT64 *)texture[number].buffer) + to) + 1);
1335      codes = *((UINT32 *)(((UINT64 *)texture[number].buffer) + to) + 1);
1336      s = (y << 3) + (x << 1);
1337      c = (codes >> s) & 3;
1338      c = c + (color0 > color1 ? 0 : 4);
1339      color0m2 = color0 << 1;
1340      color1m2 = color1 << 1;
1341      switch (c) {
1342      case 0:
1343         return 0xff000000 + convert_r5g6b5_r8g8b8(color0);
13531344         break;
1354      case A4R4G4B4:
1355         to=dilated0[texture[number].dilate][x]+dilated1[texture[number].dilate][y]; // offset of texel in texture memory
1356         a4r4g4b4=*(((UINT16 *)texture[number].buffer)+to); // get texel color
1357         return convert_a4r4g4b4_a8r8g8b8(a4r4g4b4);
1358      case A1R5G5B5:
1359         to=dilated0[texture[number].dilate][x]+dilated1[texture[number].dilate][y]; // offset of texel in texture memory
1360         a1r5g5b5=*(((UINT16 *)texture[number].buffer)+to); // get texel color
1361         return convert_a1r5g5b5_a8r8g8b8(a1r5g5b5);
1362      case R5G6B5:
1363         to=dilated0[texture[number].dilate][x]+dilated1[texture[number].dilate][y]; // offset of texel in texture memory
1364         r5g6b5=*(((UINT16 *)texture[number].buffer)+to); // get texel color
1365         return 0xff000000+convert_r5g6b5_r8g8b8(r5g6b5);
1366      case R8G8B8_RECT:
1367         to=texture[number].rectangle_pitch*y+(x << 2);
1368         return *((UINT32 *)(((UINT8 *)texture[number].buffer)+to));
1345      case 1:
1346         return 0xff000000 + convert_r5g6b5_r8g8b8(color1);
1347         break;
1348      case 2:
1349         cb = pal5bit(((color0m2 & 0x003e) + (color1 & 0x001f)) / 3);
1350         cg = pal6bit(((color0m2 & 0x0fc0) + (color1 & 0x07e0)) / 3 >> 5);
1351         cr = pal5bit(((color0m2 & 0x1f000) + color1) / 3 >> 11);
1352         return 0xff000000 | (cr << 16) | (cg << 8) | (cb);
1353         break;
1354      case 3:
1355         cb = pal5bit(((color1m2 & 0x003e) + (color0 & 0x001f)) / 3);
1356         cg = pal6bit(((color1m2 & 0x0fc0) + (color0 & 0x07e0)) / 3 >> 5);
1357         cr = pal5bit(((color1m2 & 0x1f000) + color0) / 3 >> 11);
1358         return 0xff000000 | (cr << 16) | (cg << 8) | (cb);
1359         break;
1360      case 4:
1361         return 0xff000000 + convert_r5g6b5_r8g8b8(color0);
1362         break;
1363      case 5:
1364         return 0xff000000 + convert_r5g6b5_r8g8b8(color1);
1365         break;
1366      case 6:
1367         cb = pal5bit(((color0 & 0x001f) + (color1 & 0x001f)) / 2);
1368         cg = pal6bit(((color0 & 0x07e0) + (color1 & 0x07e0)) / 2 >> 5);
1369         cr = pal5bit(((color0 & 0xf800) + (color1 & 0xf800)) / 2 >> 11);
1370         return 0xff000000 | (cr << 16) | (cg << 8) | (cb);
1371         break;
13691372      default:
1370         return 0xff00ff00;
1373         return 0xff000000;
1374         break;
1375      }
1376   case DXT3:
1377      bx = x >> 2;
1378      by = y >> 2;
1379      x = x & 3;
1380      y = y & 3;
1381      to = (bx + by*(texture[number].sizeu >> 2)) << 1;
1382      color0 = *((UINT16 *)(((UINT64 *)texture[number].buffer) + to) + 4);
1383      color1 = *((UINT16 *)(((UINT64 *)texture[number].buffer) + to) + 5);
1384      codes = *((UINT32 *)(((UINT64 *)texture[number].buffer) + to) + 3);
1385      alphas = *(((UINT64 *)texture[number].buffer) + to);
1386      s = (y << 3) + (x << 1);
1387      sa = ((y << 2) + x) << 2;
1388      c = (codes >> s) & 3;
1389      ca = (alphas >> sa) & 15;
1390      switch (c) {
1391      case 0:
1392         return ((ca + (ca << 4)) << 24) + convert_r5g6b5_r8g8b8(color0);
1393         break;
1394      case 1:
1395         return ((ca + (ca << 4)) << 24) + convert_r5g6b5_r8g8b8(color1);
1396         break;
1397      case 2:
1398         cb = pal5bit((2 * (color0 & 0x001f) + (color1 & 0x001f)) / 3);
1399         cg = pal6bit((2 * (color0 & 0x07e0) + (color1 & 0x07e0)) / 3 >> 5);
1400         cr = pal5bit((2 * (color0 & 0xf800) + (color1 & 0xf800)) / 3 >> 11);
1401         return ((ca + (ca << 4)) << 24) | (cr << 16) | (cg << 8) | (cb);
1402         break;
1403      default:
1404         cb = pal5bit(((color0 & 0x001f) + 2 * (color1 & 0x001f)) / 3);
1405         cg = pal6bit(((color0 & 0x07e0) + 2 * (color1 & 0x07e0)) / 3 >> 5);
1406         cr = pal5bit(((color0 & 0xf800) + 2 * (color1 & 0xf800)) / 3 >> 11);
1407         return ((ca + (ca << 4)) << 24) | (cr << 16) | (cg << 8) | (cb);
1408         break;
1409      }
1410      break;
1411   case A4R4G4B4:
1412      to = dilated0[texture[number].dilate][x] + dilated1[texture[number].dilate][y]; // offset of texel in texture memory
1413      a4r4g4b4 = *(((UINT16 *)texture[number].buffer) + to); // get texel color
1414      return convert_a4r4g4b4_a8r8g8b8(a4r4g4b4);
1415   case A1R5G5B5:
1416      to = dilated0[texture[number].dilate][x] + dilated1[texture[number].dilate][y]; // offset of texel in texture memory
1417      a1r5g5b5 = *(((UINT16 *)texture[number].buffer) + to); // get texel color
1418      return convert_a1r5g5b5_a8r8g8b8(a1r5g5b5);
1419   case R5G6B5:
1420      to = dilated0[texture[number].dilate][x] + dilated1[texture[number].dilate][y]; // offset of texel in texture memory
1421      r5g6b5 = *(((UINT16 *)texture[number].buffer) + to); // get texel color
1422      return 0xff000000 + convert_r5g6b5_r8g8b8(r5g6b5);
1423   case R8G8B8_RECT:
1424      to = texture[number].rectangle_pitch*y + (x << 2);
1425      return *((UINT32 *)(((UINT8 *)texture[number].buffer) + to));
1426   case A8R8G8B8_RECT:
1427      to = texture[number].rectangle_pitch*y + (x << 2);
1428      return *((UINT32 *)(((UINT8 *)texture[number].buffer) + to));
1429   case DXT5:
1430      bx = x >> 2;
1431      by = y >> 2;
1432      x = x & 3;
1433      y = y & 3;
1434      to = (bx + by*(texture[number].sizeu >> 2)) << 1;
1435      color0 = *((UINT16 *)(((UINT64 *)texture[number].buffer) + to) + 4);
1436      color1 = *((UINT16 *)(((UINT64 *)texture[number].buffer) + to) + 5);
1437      codes = *((UINT32 *)(((UINT64 *)texture[number].buffer) + to) + 3);
1438      alpha0 = *((UINT8 *)(((UINT64 *)texture[number].buffer) + to) + 0);
1439      alpha1 = *((UINT8 *)(((UINT64 *)texture[number].buffer) + to) + 1);
1440      alphas = *(((UINT64 *)texture[number].buffer) + to);
1441      s = (y << 3) + (x << 1);
1442      sa = ((y << 2) + x) * 3;
1443      c = (codes >> s) & 3;
1444      ca = (alphas >> sa) & 7;
1445      ca = ca + (alpha0 > alpha1 ? 0 : 8);
1446      switch (ca) {
1447      case 0:
1448         ca = alpha0;
1449         break;
1450      case 1:
1451         ca = alpha1;
1452         break;
1453      case 2:
1454         ca = (6 * alpha0 + 1 * alpha1) / 7;
1455         break;
1456      case 3:
1457         ca = (5 * alpha0 + 2 * alpha1) / 7;
1458         break;
1459      case 4:
1460         ca = (4 * alpha0 + 3 * alpha1) / 7;
1461         break;
1462      case 5:
1463         ca = (3 * alpha0 + 4 * alpha1) / 7;
1464         break;
1465      case 6:
1466         ca = (2 * alpha0 + 5 * alpha1) / 7;
1467         break;
1468      case 7:
1469         ca = (1 * alpha0 + 6 * alpha1) / 7;
1470         break;
1471      case 8:
1472         ca = alpha0;
1473         break;
1474      case 9:
1475         ca = alpha1;
1476         break;
1477      case 10:
1478         ca = (4 * alpha0 + 1 * alpha1) / 5;
1479         break;
1480      case 11:
1481         ca = (3 * alpha0 + 2 * alpha1) / 5;
1482         break;
1483      case 12:
1484         ca = (2 * alpha0 + 3 * alpha1) / 5;
1485         break;
1486      case 13:
1487         ca = (1 * alpha0 + 4 * alpha1) / 5;
1488         break;
1489      case 14:
1490         ca = 0;
1491         break;
1492      case 15:
1493         ca = 255;
1494         break;
1495      }
1496      switch (c) {
1497      case 0:
1498         return (ca << 24) + convert_r5g6b5_r8g8b8(color0);
1499         break;
1500      case 1:
1501         return (ca << 24) + convert_r5g6b5_r8g8b8(color1);
1502         break;
1503      case 2:
1504         cb = pal5bit((2 * (color0 & 0x001f) + (color1 & 0x001f)) / 3);
1505         cg = pal6bit((2 * (color0 & 0x07e0) + (color1 & 0x07e0)) / 3 >> 5);
1506         cr = pal5bit((2 * (color0 & 0xf800) + (color1 & 0xf800)) / 3 >> 11);
1507         return (ca << 24) | (cr << 16) | (cg << 8) | (cb);
1508         break;
1509      default:
1510         cb = pal5bit(((color0 & 0x001f) + 2 * (color1 & 0x001f)) / 3);
1511         cg = pal6bit(((color0 & 0x07e0) + 2 * (color1 & 0x07e0)) / 3 >> 5);
1512         cr = pal5bit(((color0 & 0xf800) + 2 * (color1 & 0xf800)) / 3 >> 11);
1513         return (ca << 24) | (cr << 16) | (cg << 8) | (cb);
1514         break;
1515      }
1516   default:
1517      return 0xff00ff00;
13711518   }
13721519}
13731520
r29543r29544
16161763   maddress=method*4;
16171764   data=space.read_dword(address);
16181765   channel[chanel][subchannel].object.method[method]=data;
1766   if (maddress == 0x17fc) {
1767      indexesleft_count = 0;
1768      primitives_count = 0;
1769      countlen--;
1770   }
16191771   if (maddress == 0x1810) {
16201772      // draw vertices
16211773      int offset,count,type;
r29543r29544
16291781      offset=data & 0xffffff;
16301782      count=(data >> 24) & 0xff;
16311783      type=channel[chanel][subchannel].object.method[0x17fc/4];
1632      tmp=channel[chanel][subchannel].object.method[0x1720/4];
16331784      dmahand[0]=channel[chanel][subchannel].object.method[0x019c/4];
16341785      dmahand[1]=channel[chanel][subchannel].object.method[0x01a0/4];
16351786      geforce_read_dma_object(dmahand[0],dmaoff[0],smasiz[0]);
r29543r29544
16741825               *((UINT32 *)(&xy[m].y))=space.read_dword(vtxbuf_address[0]+(n+m+offset)*vtxbuf_stride[0]+4);
16751826               *((UINT32 *)(&z[m]))=space.read_dword(vtxbuf_address[0]+(n+m+offset)*vtxbuf_stride[0]+8);
16761827               *((UINT32 *)(&w[m]))=space.read_dword(vtxbuf_address[0]+(n+m+offset)*vtxbuf_stride[0]+12);
1677               c[m]=space.read_dword(vtxbuf_address[3]+(n+m+offset)*vtxbuf_stride[0]+0); // color
1828               c[m]=space.read_dword(vtxbuf_address[3]+(n+m+offset)*vtxbuf_stride[3]+0); // color
16781829               xy[m].p[0]=c[m] & 0xff; // b
16791830               xy[m].p[1]=(c[m] & 0xff00) >> 8; // g
16801831               xy[m].p[2]=(c[m] & 0xff0000) >> 16; // r
r29543r29544
17111862            *((UINT32 *)(&xy[m].y))=space.read_dword(vtxbuf_address[0]+(m+offset)*vtxbuf_stride[0]+4);
17121863            *((UINT32 *)(&z[m]))=space.read_dword(vtxbuf_address[0]+(m+offset)*vtxbuf_stride[0]+8);
17131864            *((UINT32 *)(&w[m]))=space.read_dword(vtxbuf_address[0]+(m+offset)*vtxbuf_stride[0]+12);
1714            c[m]=space.read_dword(vtxbuf_address[3]+(m+offset)*vtxbuf_stride[0]+0); // color
1865            c[m]=space.read_dword(vtxbuf_address[3]+(m+offset)*vtxbuf_stride[3]+0); // color
17151866            xy[m].p[0]=c[m] & 0xff; // b
17161867            xy[m].p[1]=(c[m] & 0xff00) >> 8;  // g
17171868            xy[m].p[2]=(c[m] & 0xff0000) >> 16;  // r
r29543r29544
17311882            *((UINT32 *)(&xy[2].y))=space.read_dword(vtxbuf_address[0]+(n+offset)*vtxbuf_stride[0]+4);
17321883            *((UINT32 *)(&z[2]))=space.read_dword(vtxbuf_address[0]+(n+offset)*vtxbuf_stride[0]+8);
17331884            *((UINT32 *)(&w[2]))=space.read_dword(vtxbuf_address[0]+(n+offset)*vtxbuf_stride[0]+12);
1734            c[2]=space.read_dword(vtxbuf_address[3]+(n+offset)*vtxbuf_stride[0]+0); // color
1885            c[2]=space.read_dword(vtxbuf_address[3]+(n+offset)*vtxbuf_stride[3]+0); // color
17351886            xy[2].p[0]=c[2] & 0xff; // b
17361887            xy[2].p[1]=(c[2] & 0xff00) >> 8; // g
17371888            xy[2].p[2]=(c[2] & 0xff0000) >> 16; // r
r29543r29544
17601911      }
17611912      countlen--;
17621913   }
1914   if (maddress == 0x1800) {
1915      int vtxbuf_stride[16];
1916      UINT32 vtxbuf_address[16];
1917      UINT32 dmahand[2], dmaoff[2], smasiz[2];
1918      UINT32 type, tmp, n, m, u;
1919      render_delegate renderspans;
1920
1921      // vertices are selected from the vertex buffer using an array of indexes
1922      // each dword after 1800 contains two 16 bit index values to select the vartices
1923      type = channel[chanel][subchannel].object.method[0x17fc / 4];
1924      dmahand[0] = channel[chanel][subchannel].object.method[0x019c / 4];
1925      dmahand[1] = channel[chanel][subchannel].object.method[0x01a0 / 4];
1926      geforce_read_dma_object(dmahand[0], dmaoff[0], smasiz[0]);
1927      geforce_read_dma_object(dmahand[1], dmaoff[1], smasiz[1]);
1928      if (((channel[chanel][subchannel].object.method[0x1e60 / 4] & 7) > 0) && (combiner.used != 0)) {
1929         renderspans = render_delegate(FUNC(nv2a_renderer::render_register_combiners), this);
1930      }
1931      else if (texture[0].enabled) {
1932         renderspans = render_delegate(FUNC(nv2a_renderer::render_texture_simple), this);
1933      }
1934      else
1935         renderspans = render_delegate(FUNC(nv2a_renderer::render_color), this);
1936#ifdef LOG_NV2A
1937      printf("vertex %d %d %d\n\r", type, offset, count);
1938#endif
1939      for (n = 0; n < 16; n++) {
1940#ifdef LOG_NV2A
1941         printf(" %08X %08X\n\r", channel[chanel][subchannel].object.method[0x1720 / 4 + n], channel[chanel][subchannel].object.method[0x1760 / 4 + n]);
1942#endif
1943         tmp = channel[chanel][subchannel].object.method[0x1760 / 4 + n]; // VTXBUF_FMT
1944         //vtxbuf_kind[n]=tmp & 15;
1945         //vtxbuf_size[n]=(tmp >> 4) & 15;
1946         vtxbuf_stride[n] = (tmp >> 8) & 255;
1947         tmp = channel[chanel][subchannel].object.method[0x1720 / 4 + n]; // VTXBUF_OFFSET
1948         if (tmp & 0x80000000)
1949            vtxbuf_address[n] = (tmp & 0x0fffffff) + dmaoff[1];
1950         else
1951            vtxbuf_address[n] = (tmp & 0x0fffffff) + dmaoff[0];
1952      }
1953      if (type == nv2a_renderer::QUADS) {
1954         while (1) {
1955            vertex_t xy[4];
1956            float z[4], w[4];
1957            UINT32 c[4];
1958
1959            // need 4 per object
1960            // get remaining
1961            while ((indexesleft_count < 4) && (countlen > 0)) {
1962               indexesleft[indexesleft_count] = data & 0xffff;
1963               indexesleft[indexesleft_count+ 1] = (data >> 16) & 0xffff;
1964               indexesleft_count+=2;
1965               countlen--;
1966               address = address + 4;
1967               data = space.read_dword(address);
1968            }
1969            if ((indexesleft_count < 4) && (countlen == 0))
1970               break;
1971            //printf("draw quad\n\r");
1972            for (m = 0; m < 4; m++) {
1973               *((UINT32 *)(&xy[m].x)) = space.read_dword(vtxbuf_address[0] + indexesleft[m] * vtxbuf_stride[0] + 0);
1974               *((UINT32 *)(&xy[m].y)) = space.read_dword(vtxbuf_address[0] + indexesleft[m] * vtxbuf_stride[0] + 4);
1975               *((UINT32 *)(&z[m])) = space.read_dword(vtxbuf_address[0] + indexesleft[m] * vtxbuf_stride[0] + 8);
1976               *((UINT32 *)(&w[m])) = space.read_dword(vtxbuf_address[0] + indexesleft[m] * vtxbuf_stride[0] + 12);
1977               c[m] = space.read_dword(vtxbuf_address[3] + indexesleft[m] * vtxbuf_stride[3] + 0); // color
1978               xy[m].p[0] = c[m] & 0xff; // b
1979               xy[m].p[1] = (c[m] & 0xff00) >> 8; // g
1980               xy[m].p[2] = (c[m] & 0xff0000) >> 16; // r
1981               xy[m].p[3] = (c[m] & 0xff000000) >> 24; // a
1982               for (u = 0; u < 4; u++) {
1983                  xy[m].p[4 + u * 2] = 0;
1984                  xy[m].p[5 + u * 2] = 0;
1985                  if (texture[u].enabled) {
1986                     *((UINT32 *)(&xy[m].p[4 + u * 2])) = space.read_dword(vtxbuf_address[9 + u] + indexesleft[m] * vtxbuf_stride[9 + u] + 0);
1987                     *((UINT32 *)(&xy[m].p[5 + u * 2])) = space.read_dword(vtxbuf_address[9 + u] + indexesleft[m] * vtxbuf_stride[9 + u] + 4);
1988                  }
1989               }
1990            }
1991
1992            render_polygon<4>(fb.cliprect(), renderspans, 4 + 4 * 2, xy); // 4 rgba, 4 texture units 2 uv
1993            /*myline(fb,xy[0].x,xy[0].y,xy[1].x,xy[1].y);
1994            myline(fb,xy[1].x,xy[1].y,xy[2].x,xy[2].y);
1995            myline(fb,xy[2].x,xy[2].y,xy[3].x,xy[3].y);
1996            myline(fb,xy[3].x,xy[3].y,xy[0].x,xy[0].y);*/
1997#ifdef LOG_NV2A
1998            printf(" (%f,%f,%f)-(%f,%f,%f)-(%f,%f,%f)-(%f,%f,%f)\n\r", xy[0].x, xy[0].y, z[0], xy[1].x, xy[1].y, z[1], xy[2].x, xy[2].y, z[2], xy[3].x, xy[3].y, z[3]);
1999#endif
2000            for (m = 4; m < indexesleft_count; m++)
2001               indexesleft[m - 4] = indexesleft[m];
2002            indexesleft_count = indexesleft_count - 4;
2003         }
2004         wait();
2005      }
2006      else if (type == nv2a_renderer::TRIANGLES) {
2007         while (1) {
2008            vertex_t xy[4];
2009            float z[4], w[4];
2010            UINT32 c[4];
2011
2012            // need 3 dwords per object
2013            // get remaining
2014            while ((indexesleft_count < 3) && (countlen > 0)) {
2015               indexesleft[indexesleft_count] = data & 0xffff;
2016               indexesleft[indexesleft_count + 1] = (data >> 16) & 0xffff;
2017               indexesleft_count += 2;
2018               countlen--;
2019               address = address + 4;
2020               data = space.read_dword(address);
2021            }
2022            if ((indexesleft_count < 3) && (countlen == 0))
2023               break;
2024            //printf("draw triangle\n\r");
2025            for (m = 0; m < 3; m++) {
2026               *((UINT32 *)(&xy[m].x)) = space.read_dword(vtxbuf_address[0] + indexesleft[m] * vtxbuf_stride[0] + 0);
2027               *((UINT32 *)(&xy[m].y)) = space.read_dword(vtxbuf_address[0] + indexesleft[m] * vtxbuf_stride[0] + 4);
2028               *((UINT32 *)(&z[m])) = space.read_dword(vtxbuf_address[0] + indexesleft[m] * vtxbuf_stride[0] + 8);
2029               *((UINT32 *)(&w[m])) = space.read_dword(vtxbuf_address[0] + indexesleft[m] * vtxbuf_stride[0] + 12);
2030               c[m] = space.read_dword(vtxbuf_address[3] + indexesleft[m] * vtxbuf_stride[3] + 0); // color
2031               xy[m].p[0] = c[m] & 0xff; // b
2032               xy[m].p[1] = (c[m] & 0xff00) >> 8; // g
2033               xy[m].p[2] = (c[m] & 0xff0000) >> 16; // r
2034               xy[m].p[3] = (c[m] & 0xff000000) >> 24; // a
2035               for (u = 0; u < 4; u++) {
2036                  xy[m].p[4 + u * 2] = 0;
2037                  xy[m].p[5 + u * 2] = 0;
2038                  if (texture[u].enabled) {
2039                     *((UINT32 *)(&xy[m].p[4 + u * 2])) = space.read_dword(vtxbuf_address[9 + u] + indexesleft[m] * vtxbuf_stride[9 + u] + 0);
2040                     *((UINT32 *)(&xy[m].p[5 + u * 2])) = space.read_dword(vtxbuf_address[9 + u] + indexesleft[m] * vtxbuf_stride[9 + u] + 4);
2041                  }
2042               }
2043            }
2044
2045            render_triangle(fb.cliprect(), renderspans, 4 + 4 * 2, xy[0], xy[1], xy[2]); // 4 rgba, 4 texture units 2 uv
2046            /*myline(fb,xy[0].x,xy[0].y,xy[1].x,xy[1].y);
2047            myline(fb,xy[1].x,xy[1].y,xy[2].x,xy[2].y);
2048            myline(fb,xy[2].x,xy[2].y,xy[3].x,xy[3].y);*/
2049#ifdef LOG_NV2A
2050            printf(" (%f,%f,%f)-(%f,%f,%f)-(%f,%f,%f)\n\r", xy[0].x, xy[0].y, z[0], xy[1].x, xy[1].y, z[1], xy[2].x, xy[2].y, z[2]);
2051#endif
2052            for (m = 3; m < indexesleft_count; m++)
2053               indexesleft[m - 3] = indexesleft[m];
2054            indexesleft_count = indexesleft_count - 3;
2055         }
2056         wait();
2057      }
2058      else if (type == nv2a_renderer::TRIANGLE_STRIP) {
2059         while (1) {
2060            vertex_t xy[4];
2061            float z[4], w[4];
2062            UINT32 c[4];
2063
2064            // need 3 dwords per object
2065            // get remaining
2066            while ((indexesleft_count < 3) && (countlen > 0)) {
2067               indexesleft[indexesleft_count] = data & 0xffff;
2068               indexesleft[indexesleft_count + 1] = (data >> 16) & 0xffff;
2069               indexesleft_count += 2;
2070               countlen--;
2071               address = address + 4;
2072               data = space.read_dword(address);
2073            }
2074            if ((indexesleft_count < 3) && (countlen == 0))
2075               break;
2076            //printf("draw triangle\n\r");
2077            for (m = 0; m < 3; m++) {
2078               *((UINT32 *)(&xy[m].x)) = space.read_dword(vtxbuf_address[0] + indexesleft[m] * vtxbuf_stride[0] + 0);
2079               *((UINT32 *)(&xy[m].y)) = space.read_dword(vtxbuf_address[0] + indexesleft[m] * vtxbuf_stride[0] + 4);
2080               *((UINT32 *)(&z[m])) = space.read_dword(vtxbuf_address[0] + indexesleft[m] * vtxbuf_stride[0] + 8);
2081               *((UINT32 *)(&w[m])) = space.read_dword(vtxbuf_address[0] + indexesleft[m] * vtxbuf_stride[0] + 12);
2082               c[m] = space.read_dword(vtxbuf_address[3] + indexesleft[m] * vtxbuf_stride[3] + 0); // color
2083               xy[m].p[0] = c[m] & 0xff; // b
2084               xy[m].p[1] = (c[m] & 0xff00) >> 8; // g
2085               xy[m].p[2] = (c[m] & 0xff0000) >> 16; // r
2086               xy[m].p[3] = (c[m] & 0xff000000) >> 24; // a
2087               for (u = 0; u < 4; u++) {
2088                  xy[m].p[4 + u * 2] = 0;
2089                  xy[m].p[5 + u * 2] = 0;
2090                  if (texture[u].enabled) {
2091                     *((UINT32 *)(&xy[m].p[4 + u * 2])) = space.read_dword(vtxbuf_address[9 + u] + indexesleft[m] * vtxbuf_stride[9 + u] + 0);
2092                     *((UINT32 *)(&xy[m].p[5 + u * 2])) = space.read_dword(vtxbuf_address[9 + u] + indexesleft[m] * vtxbuf_stride[9 + u] + 4);
2093                  }
2094               }
2095            }
2096
2097            render_triangle(fb.cliprect(), renderspans, 4 + 4 * 2, xy[primitives_count & 1], xy[~primitives_count & 1], xy[2]); // 012,102,012,102...
2098            /*myline(fb,xy[0].x,xy[0].y,xy[1].x,xy[1].y);
2099            myline(fb,xy[1].x,xy[1].y,xy[2].x,xy[2].y);
2100            myline(fb,xy[2].x,xy[2].y,xy[3].x,xy[3].y);*/
2101#ifdef LOG_NV2A
2102            printf(" (%f,%f,%f)-(%f,%f,%f)-(%f,%f,%f)\n\r", xy[0].x, xy[0].y, z[0], xy[1].x, xy[1].y, z[1], xy[2].x, xy[2].y, z[2]);
2103#endif
2104            primitives_count++;
2105            for (m = 1; m < indexesleft_count; m++)
2106               indexesleft[m - 1] = indexesleft[m];
2107            indexesleft_count = indexesleft_count - 1;
2108         }
2109         wait();
2110      }
2111      else {
2112         logerror("Unsupported primitive %d for method 0x1800\n", type);
2113         countlen = 0;
2114      }
2115   }
17632116   if (maddress == 0x1818) {
17642117      int n,m,u,vwords;
17652118      int vattrpos[16];
r29543r29544
19002253         }
19012254         for (n=2;countlen > 0;n++) {
19022255            // put vertex n data in element 2 of arrays
1903            // put vertex n data in element 2 of arrays
19042256            // position
19052257            *((UINT32 *)(&xy[2].x))=space.read_dword(address+vattrpos[0]*4+0);
19062258            *((UINT32 *)(&xy[2].y))=space.read_dword(address+vattrpos[0]*4+4);
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20552407         wait();
20562408      } else {
20572409         logerror("Unsupported primitive %d for method 0x1818\n",type);
2410         countlen = 0;
20582411      }
20592412   }
2413   if ((maddress >= 0x1760) && (maddress < 0x17A0)) {
2414      int bit=method-0x1760/4;
2415
2416      data=data & 255;
2417      if (data > 15)
2418         enabled_vertex_attributes |= (1 << bit);
2419      else
2420         enabled_vertex_attributes &= ~(1 << bit);
2421      switch (data & 15) {
2422         case 0:
2423            words_vertex_attributes[bit]=(((data >> 4) + 3) & 15) >> 2;
2424            break;
2425         case nv2a_renderer::FLOAT:
2426            words_vertex_attributes[bit]=(data >> 4);
2427            break;
2428         case nv2a_renderer::UBYTE:
2429            words_vertex_attributes[bit]=(((data >> 4) + 3) & 15) >> 2;
2430            break;
2431         case nv2a_renderer::USHORT:
2432            words_vertex_attributes[bit]=(((data >> 4) + 1) & 15) >> 1;
2433            break;
2434         default:
2435            words_vertex_attributes[bit]=0;
2436      }
2437      countlen--;
2438   }
20602439   if ((maddress == 0x1d6c) || (maddress == 0x1d70) || (maddress == 0x1a4))
20612440      countlen--;
20622441   if (maddress == 0x1d70) {
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21242503         texture[unit].sizew=1 << basesizew;
21252504         texture[unit].dilate=dilatechose[(basesizeu << 4)+basesizev];
21262505         texture[unit].format=format;
2506         if (debug_grab_texttype == format) {
2507            FILE *f;
2508            int written;
2509
2510            debug_grab_texttype = -1;
2511            f = fopen(debug_grab_textfile, "wb");
2512            if (f) {
2513               written=(int)fwrite(texture[unit].buffer, texture[unit].sizeu*texture[unit].sizev*4, 1, f);
2514               fclose(f);
2515               logerror("Written %d bytes of texture to specified file\n", written);
2516            } else
2517               logerror("Unable to save texture to specified file\n");
2518         }
21272519      }
21282520      if (maddress == 0x1b0c) {
21292521         // enable texture
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21372529      }
21382530      countlen--;
21392531   }
2140   if ((maddress >= 0x1760) && (maddress < 0x17A0)) {
2141      int bit=method-0x1760/4;
2142
2143      data=data & 255;
2144      if (data > 15)
2145         enabled_vertex_attributes |= (1 << bit);
2532   // modelview matrix
2533   if ((maddress >= 0x0480) && (maddress < 0x04c0)) {
2534      maddress = (maddress - 0x0480) / 4;
2535      *(UINT32 *)(&matrix.modelview[maddress]) = data;
2536      countlen--;
2537   }
2538   // inverse modelview matrix
2539   if ((maddress >= 0x0580) && (maddress < 0x05c0)) {
2540      maddress = (maddress - 0x0580) / 4;
2541      *(UINT32 *)(&matrix.modelview_inverse[maddress]) = data;
2542      countlen--;
2543   }
2544   // projection matrix
2545   if ((maddress >= 0x0680) && (maddress < 0x06c0)) {
2546      maddress = (maddress - 0x0680) / 4;
2547      *(UINT32 *)(&matrix.projection[maddress]) = data;
2548      countlen--;
2549   }
2550   // viewport translate
2551   if ((maddress >= 0x0a20) && (maddress < 0x0a30)) {
2552      maddress = (maddress - 0x0a20) / 4;
2553      *(UINT32 *)(&matrix.translate[maddress]) = data;
2554      countlen--;
2555   }
2556   // viewport scale
2557   if ((maddress >= 0x0af0) && (maddress < 0x0b00)) {
2558      maddress = (maddress - 0x0af0) / 4;
2559      *(UINT32 *)(&matrix.scale[maddress]) = data;
2560      countlen--;
2561   }
2562   // Vertex program (shader)
2563   if (maddress == 0x1e94) {
2564      /*if (data == 2)
2565         logerror("Enabled vertex program\n");
2566      else if (data == 4)
2567         logerror("Enabled fixed function pipeline\n");
2568      else if (data == 6)
2569         logerror("Enabled both fixed function pipeline and vertex program ?\n");
21462570      else
2147         enabled_vertex_attributes &= ~(1 << bit);
2148      switch (data & 15) {
2149         case 0:
2150            words_vertex_attributes[bit]=(((data >> 4) + 3) & 15) >> 2;
2151            break;
2152         case nv2a_renderer::FLOAT:
2153            words_vertex_attributes[bit]=(data >> 4);
2154            break;
2155         case nv2a_renderer::UBYTE:
2156            words_vertex_attributes[bit]=(((data >> 4) + 3) & 15) >> 2;
2157            break;
2158         case nv2a_renderer::USHORT:
2159            words_vertex_attributes[bit]=(((data >> 4) + 1) & 15) >> 1;
2160            break;
2161         default:
2162            words_vertex_attributes[bit]=0;
2163      }
2571         logerror("Unknown value %d to method 0x1e94\n",data);*/
2572      countlen--;
21642573   }
2574   if (maddress == 0x1e9c) {
2575      //logerror("VP_UPLOAD_FROM_ID %d\n",data);
2576      vertexprogram.upload_instruction=data*4;
2577      countlen--;
2578   }
2579   if (maddress == 0x1ea0) {
2580      //logerror("VP_START_FROM_ID %d\n",data);
2581      vertexprogram.instructions=vertexprogram.upload_instruction/4;
2582      countlen--;
2583   }
2584   if (maddress == 0x1ea4) {
2585      //logerror("VP_UPLOAD_CONST_ID %d\n",data);
2586      vertexprogram.upload_parameter=data;
2587      countlen--;
2588   }
2589   if ((maddress >= 0x0b00) && (maddress < 0x0b80)) {
2590      //logerror("VP_UPLOAD_INST\n");
2591      if (vertexprogram.upload_instruction < 1024)
2592         vertexprogram.instruction[vertexprogram.upload_instruction]=data;
2593      else
2594         logerror("Need to increase size of vertexprogram.instruction to %d\n\r", vertexprogram.upload_parameter);
2595      vertexprogram.upload_instruction++;
2596   }
2597   if ((maddress >= 0x0b80) && (maddress < 0x0c00)) {
2598      //logerror("VP_UPLOAD_CONST\n");
2599      if (vertexprogram.upload_parameter < 1024)
2600         vertexprogram.parameter[vertexprogram.upload_parameter] = data;
2601      else
2602         logerror("Need to increase size of vertexprogram.parameter to %d\n\r", vertexprogram.upload_parameter);
2603      vertexprogram.upload_parameter++;
2604   }
2605   // Register combiners
21652606   if (maddress == 0x1e60) {
21662607      combiner.stages=data & 15;
21672608      countlen--;
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22902731   return combiner.used;
22912732}
22922733
2734void nv2a_renderer::debug_grab_texture(int type, const char *filename)
2735{
2736   debug_grab_texttype = type;
2737   if (debug_grab_textfile == NULL)
2738      debug_grab_textfile = (char *)malloc(128);
2739   strncpy(debug_grab_textfile, filename, 127);
2740}
2741
22932742void nv2a_renderer::savestate_items()
22942743{
22952744}
r29543r29544
30083457   }
30093458}
30103459
3460void chihiro_state::debug_grab_texture(int type, char *filename)
3461{
3462   nvidia_nv2a->debug_grab_texture(type, filename);
3463}
3464
30113465void chihiro_state::vblank_callback(screen_device &screen, bool state)
30123466{
30133467   nvidia_nv2a->vblank_callback(screen,state);
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33383792READ32_MEMBER( chihiro_state::audio_apu_r )
33393793{
33403794   logerror("Audio_APU: read from %08X mask %08X\n",0xfe800000+offset*4,mem_mask);
3341   if (offset == 0x20010/4)
3795   if (offset == 0x20010/4) // some kind of internal counter or state value
33423796      return 0x20+4+8+0x48+0x80;
3343   return 0;
3797   return apust.memory[offset];
33443798}
33453799
33463800WRITE32_MEMBER( chihiro_state::audio_apu_w )
33473801{
3802   //UINT32 old;
3803   UINT32 v;
3804
33483805   logerror("Audio_APU: write at %08X mask %08X value %08X\n",0xfe800000+offset*4,mem_mask,data);
3349   if (offset == 0x2040/4)
3350      apust.memory0_sgaddress=data;
3351   if (offset == 0x20d4/4) {
3352      apust.memory0_sgblocks=data;
3353      apust.memory0_address=apust.space->read_dword(apust.memory0_sgaddress);
3806   //old = apust.memory[offset];
3807   apust.memory[offset] = data;
3808   if (offset == 0x02040/4) // address of memory area with scatter-gather info (gpdsp scratch dma)
3809      apust.gpdsp_sgaddress=data;
3810   if (offset == 0x020d4/4) { // block count (gpdsp)
3811      apust.gpdsp_sgblocks=data;
3812      apust.gpdsp_address=apust.space->read_dword(apust.gpdsp_sgaddress); // memory address of first block
33543813      apust.timer->enable();
33553814      apust.timer->adjust(attotime::from_msec(1),0,attotime::from_msec(1));
33563815   }
3357   if (offset == 0x2048/4)
3358      apust.memory1_sgaddress=data;
3359   if (offset == 0x20dc/4)
3360      apust.memory1_sgblocks=data;
3816   if (offset == 0x02048 / 4) // (epdsp scratch dma)
3817      apust.epdsp_sgaddress=data;
3818   if (offset == 0x020dc / 4) // (epdsp)
3819      apust.epdsp_sgblocks=data;
3820   if (offset == 0x0204c / 4) // address of memory area with information about blocks
3821      apust.unknown_sgaddress = data;
3822   if (offset == 0x020e0 / 4) // block count - 1
3823      apust.unknown_sgblocks = data;
3824   if (offset == 0x0202c / 4) { // address of memory area with 0x80 bytes for each voice
3825      apust.voicedata_address = data;
3826      return;
3827   }
3828   if (offset == 0x04024 / 4) // offset in memory area indicated by 0x204c (analog output ?)
3829      return;
3830   if (offset == 0x04034 / 4) // size
3831      return;
3832   if (offset == 0x04028 / 4) // offset in memory area indicated by 0x204c (digital output ?)
3833      return;
3834   if (offset == 0x04038 / 4) // size
3835      return;
3836   if (offset == 0x20804 / 4) { // block number for scatter-gather heap that stores sampled audio to be played
3837      if (data >= 1024) {
3838         logerror("Audio_APU: sg block number too high, increase size of voices_heap_blockaddr\n");
3839         apust.memory[offset] = 1023;
3840      }
3841      return;
3842   }
3843   if (offset == 0x20808 / 4) { // block address for scatter-gather heap that stores sampled audio to be played
3844      apust.voices_heap_blockaddr[apust.memory[0x20804 / 4]] = data;
3845      return;
3846   }
3847   if (offset == 0x202f8 / 4) { // voice number for parameters ?
3848      apust.voice_number = data;
3849      return;
3850   }
3851   if (offset == 0x202fc / 4) // 1 when accessing voice parameters 0 otherwise
3852      return;
3853   if (offset == 0x20304 / 4) { // format
3854      /*
3855        bits 28-31 sample format:
3856         0  8-bit pcm
3857         5  16-bit pcm
3858         10 adpcm ?
3859         14 24-bit pcm
3860         15 32-bit pcm
3861        bits 16-20 number of channels - 1:
3862         0  mono
3863         1  stereo
3864      */
3865      return;
3866   }
3867   if (offset == 0x2037c / 4) { // value related to sample rate
3868      INT16 v = (INT16)(data >> 16); // upper 16 bits as a signed 16 bit value
3869      float vv = ((float)v) / 4096.0; // divide by 4096
3870      float vvv = powf(2, vv); // two to the vv
3871      int f = vvv*48000.0; // sample rate
3872      apust.voices_frequency[apust.voice_number] = f;
3873      return;
3874   }
3875   if (offset == 0x203a0 / 4) // start offset of data in scatter-gather heap
3876      return;
3877   if (offset == 0x203a4 / 4) { // first sample to play
3878      apust.voices_position_start[apust.voice_number] = data*1000;
3879      return;
3880   }
3881   if (offset == 0x203dc / 4) { // last sample to play
3882      apust.voices_position_end[apust.voice_number] = data*1000;
3883      return;
3884   }
3885   if (offset == 0x2010c / 4) // voice processor 0 idle 1 not idle ?
3886      return;
3887   if (offset == 0x20124 / 4) { // voice number to activate ?
3888      v = apust.voice_number;
3889      apust.voices_active[v >> 6] |= ((UINT64)1 << (v & 63));
3890      apust.voices_position[v] = apust.voices_position_start[apust.voice_number];
3891      apust.voices_position_increment[apust.voice_number] = apust.voices_frequency[apust.voice_number];
3892      return;
3893   }
3894   if (offset == 0x20128 / 4) { // voice number to deactivate ?
3895      v = apust.voice_number;
3896      apust.voices_active[v >> 6] &= ~(1 << (v & 63));
3897      return;
3898   }
3899   if (offset == 0x20140 / 4) // voice number to ?
3900      return;
3901   if ((offset >= 0x20200 / 4) && (offset < 0x20280 / 4)) // headroom for each of the 32 mixbins
3902      return;
3903   if (offset == 0x20280 / 4) // hrtf headroom ?
3904      return;
33613905}
33623906
33633907READ32_MEMBER( chihiro_state::audio_ac93_r )
r29543r29544
34053949
34063950TIMER_CALLBACK_MEMBER(chihiro_state::audio_apu_timer)
34073951{
3408   int cmd=apust.space->read_dword(apust.memory0_address+0x800+0x10);
3952   int cmd;
3953   int bb, b, v;
3954   UINT64 bv;
3955   UINT32 phys;
3956
3957   cmd=apust.space->read_dword(apust.gpdsp_address+0x800+0x10);
34093958   if (cmd == 3)
3410      apust.space->write_dword(apust.memory0_address+0x800+0x10,0);
3959      apust.space->write_dword(apust.gpdsp_address+0x800+0x10,0);
34113960   /*else
3412       logerror("Audio_APU: unexpected value at address %d\n",apust.memory0_address+0x800+0x10);*/
3961       logerror("Audio_APU: unexpected value at address %d\n",apust.gpdsp_address+0x800+0x10);*/
3962   for (b = 0; b < 4; b++) {
3963      bv = 1;
3964      for (bb = 0; bb < 64; bb++) {
3965         if (apust.voices_active[b] & bv) {
3966            v = bb + (b << 6);
3967            apust.voices_position[v] += apust.voices_position_increment[v];
3968            while (apust.voices_position[v] >= apust.voices_position_end[v])
3969               apust.voices_position[v] = apust.voices_position_start[v] + apust.voices_position[v] - apust.voices_position_end[v] - 1000;
3970            phys = apust.voicedata_address + 0x80 * v;
3971            apust.space->write_dword(phys + 0x58, apust.voices_position[v] / 1000);
3972         }
3973         bv = bv << 1;
3974      }
3975   }
34133976}
34143977
34153978/*
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39024465   if (chihiro_devs.dimmboard != NULL) {
39034466      dimm_board_memory=chihiro_devs.dimmboard->memory(dimm_board_memory_size);
39044467   }
3905   apust.space=&m_maincpu->space();
4468   memset(apust.memory, 0, sizeof(apust.memory));
4469   memset(apust.voices_heap_blockaddr, 0, sizeof(apust.voices_heap_blockaddr));
4470   memset(apust.voices_active, 0, sizeof(apust.voices_active));
4471   memset(apust.voices_position, 0, sizeof(apust.voices_position));
4472   memset(apust.voices_position_start, 0, sizeof(apust.voices_position_start));
4473   memset(apust.voices_position_end, 0, sizeof(apust.voices_position_end));
4474   memset(apust.voices_position_increment, 0, sizeof(apust.voices_position_increment));
4475   apust.space = &m_maincpu->space();
39064476   apust.timer=machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(chihiro_state::audio_apu_timer),this),(void *)"APU Timer");
39074477   apust.timer->enable(false);
39084478   if (machine().debug_flags & DEBUG_FLAG_ENABLED)
branches/new_menus/src/mame/drivers/gaplus.c
r29543r29544
467467   GFXDECODE_ENTRY( "gfx2", 0x0000, spritelayout, 64*4, 64 )
468468GFXDECODE_END
469469
470static const namco_interface namco_config =
471{
472   8,              /* number of voices */
473   0               /* stereo */
474};
475
476470static const char *const gaplus_sample_names[] =
477471{
478472   "*gaplus",
r29543r29544
583577   MCFG_SPEAKER_STANDARD_MONO("mono")
584578
585579   MCFG_SOUND_ADD("namco", NAMCO_15XX, 24576000/1024)
586   MCFG_SOUND_CONFIG(namco_config)
580   MCFG_NAMCO_AUDIO_VOICES(8)
587581   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
588582
589583   MCFG_SAMPLES_ADD("samples", gaplus_samples_interface)
branches/new_menus/src/mame/drivers/vsnes.c
r29543r29544
16961696   PORT_DIPSETTING(    0xc0, "RP2C04-0004" )
16971697INPUT_PORTS_END
16981698
1699static const nesapu_interface nes_interface_1 =
1700{
1701   "maincpu"
1702};
1703
1704static const nesapu_interface nes_interface_2 =
1705{
1706   "sub"
1707};
1708
17091699static MACHINE_CONFIG_START( vsnes, vsnes_state )
17101700
17111701   /* basic machine hardware */
r29543r29544
17371727   MCFG_SPEAKER_STANDARD_MONO("mono")
17381728
17391729   MCFG_SOUND_ADD("nesapu1", NES_APU, N2A03_DEFAULTCLOCK)
1740   MCFG_SOUND_CONFIG(nes_interface_1)
1730   MCFG_NES_APU_CPU("maincpu")
17411731   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
17421732
17431733   MCFG_DAC_ADD("dac1")
r29543r29544
18291819   MCFG_SPEAKER_STANDARD_MONO("mono")
18301820
18311821   MCFG_SOUND_ADD("nesapu1", NES_APU, N2A03_DEFAULTCLOCK)
1832   MCFG_SOUND_CONFIG(nes_interface_1)
1822   MCFG_NES_APU_CPU("maincpu")
18331823   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
18341824
18351825   MCFG_SOUND_ADD("nesapu2", NES_APU, N2A03_DEFAULTCLOCK)
1836   MCFG_SOUND_CONFIG(nes_interface_2)
1826   MCFG_NES_APU_CPU("sub")
18371827   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
18381828
18391829   MCFG_DAC_ADD("dac1")
r29543r29544
18791869   MCFG_SPEAKER_STANDARD_MONO("mono")
18801870
18811871   MCFG_SOUND_ADD("nesapu1", NES_APU, N2A03_DEFAULTCLOCK)
1882   MCFG_SOUND_CONFIG(nes_interface_1)
1872   MCFG_NES_APU_CPU("maincpu")
18831873   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
18841874
18851875   MCFG_DAC_ADD("dac1")
branches/new_menus/src/mame/drivers/sfcbox.c
r29543r29544
116116***************************************************************************/
117117
118118#include "emu.h"
119#include "cpu/spc700/spc700.h"
120#include "cpu/g65816/g65816.h"
121119#include "cpu/z180/z180.h"
122120#include "machine/s3520cf.h"
123121#include "video/mb90082.h"
124122#include "includes/snes.h"
125#include "audio/snes_snd.h"
126123#include "rendlay.h"
127124
128125class sfcbox_state : public snes_state
r29543r29544
477474   MCFG_SCREEN_RAW_PARAMS(DOTCLK_NTSC, SNES_HTOTAL, 0, SNES_SCR_WIDTH, SNES_VTOTAL_NTSC, 0, SNES_SCR_HEIGHT_NTSC)
478475   MCFG_SCREEN_UPDATE_DRIVER( snes_state, screen_update )
479476
477   MCFG_DEVICE_ADD("ppu", SNES_PPU, 0)
478   MCFG_SNES_PPU_OPENBUS_CB(READ8(snes_state, snes_open_bus_r))
479   MCFG_VIDEO_SET_SCREEN("screen")
480
480481   // SFCBOX
481482   MCFG_SCREEN_ADD("osd", RASTER)
482483   MCFG_SCREEN_REFRESH_RATE(60)
branches/new_menus/src/mame/drivers/namcos1.c
r29543r29544
10561056
10571057
10581058
1059static const namco_interface namco_config =
1060{
1061   8,          /* number of voices */
1062   1           /* stereo */
1063};
1064
10651059/*
10661060    namcos1 has two 8bit dac channel. But They are mixed before pre-amp.
10671061    And,they are connected with pre-amp through active LPF.
r29543r29544
11151109   MCFG_SOUND_ROUTE(1, "rspeaker", 0.50)
11161110
11171111   MCFG_SOUND_ADD("namco", NAMCO_CUS30, XTAL_49_152MHz/2048/2)
1118   MCFG_SOUND_CONFIG(namco_config)
1112   MCFG_NAMCO_AUDIO_VOICES(8)
1113   MCFG_NAMCO_AUDIO_STEREO(1)
11191114   MCFG_SOUND_ROUTE(0, "lspeaker", 0.50)
11201115   MCFG_SOUND_ROUTE(1, "rspeaker", 0.50)
11211116
branches/new_menus/src/mame/drivers/balsente.c
r29543r29544
11771177INPUT_PORTS_END
11781178
11791179
1180
11811180/*************************************
11821181 *
1183 *  Sound definitions
1184 *
1185 *************************************/
1186
1187static const cem3394_interface cem_interface =
1188{
1189   431.894,
1190   1300.0,
1191   balsente_noise_gen
1192};
1193
1194
1195
1196/*************************************
1197 *
11981182 *  Machine driver
11991183 *
12001184 *************************************/
r29543r29544
12331217   MCFG_SPEAKER_STANDARD_MONO("mono")
12341218
12351219   MCFG_CEM3394_ADD("cem1", 0)
1236   MCFG_SOUND_CONFIG(cem_interface)
1220   MCFG_CEM3394_EXT_INPUT_CB(balsente_state, noise_gen_0)
1221   MCFG_CEM3394_VCO_ZERO(431.894)
1222   MCFG_CEM3394_FILTER_ZERO(1300.0)
12371223   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90)
12381224
12391225   MCFG_CEM3394_ADD("cem2", 0)
1240   MCFG_SOUND_CONFIG(cem_interface)
1226   MCFG_CEM3394_EXT_INPUT_CB(balsente_state, noise_gen_1)
1227   MCFG_CEM3394_VCO_ZERO(431.894)
1228   MCFG_CEM3394_FILTER_ZERO(1300.0)
12411229   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90)
12421230
12431231   MCFG_CEM3394_ADD("cem3", 0)
1244   MCFG_SOUND_CONFIG(cem_interface)
1232   MCFG_CEM3394_EXT_INPUT_CB(balsente_state, noise_gen_2)
1233   MCFG_CEM3394_VCO_ZERO(431.894)
1234   MCFG_CEM3394_FILTER_ZERO(1300.0)
12451235   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90)
12461236
12471237   MCFG_CEM3394_ADD("cem4", 0)
1248   MCFG_SOUND_CONFIG(cem_interface)
1238   MCFG_CEM3394_EXT_INPUT_CB(balsente_state, noise_gen_3)
1239   MCFG_CEM3394_VCO_ZERO(431.894)
1240   MCFG_CEM3394_FILTER_ZERO(1300.0)
12491241   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90)
12501242
12511243   MCFG_CEM3394_ADD("cem5", 0)
1252   MCFG_SOUND_CONFIG(cem_interface)
1244   MCFG_CEM3394_EXT_INPUT_CB(balsente_state, noise_gen_4)
1245   MCFG_CEM3394_VCO_ZERO(431.894)
1246   MCFG_CEM3394_FILTER_ZERO(1300.0)
12531247   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90)
12541248
12551249   MCFG_CEM3394_ADD("cem6", 0)
1256   MCFG_SOUND_CONFIG(cem_interface)
1250   MCFG_CEM3394_EXT_INPUT_CB(balsente_state, noise_gen_5)
1251   MCFG_CEM3394_VCO_ZERO(431.894)
1252   MCFG_CEM3394_FILTER_ZERO(1300.0)
12571253   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90)
12581254MACHINE_CONFIG_END
12591255
branches/new_menus/src/mame/drivers/punchout.c
r29543r29544
911911GFXDECODE_END
912912
913913
914
915static const nesapu_interface nes_config =
916{
917   "audiocpu"
918};
919
920914void punchout_state::machine_reset()
921915{
922916   m_rp5c01_mode_sel = 0;
r29543r29544
971965   MCFG_SPEAKER_STANDARD_MONO("mono")
972966
973967   MCFG_SOUND_ADD("nesapu", NES_APU, N2A03_DEFAULTCLOCK)
974   MCFG_SOUND_CONFIG(nes_config)
968   MCFG_NES_APU_CPU("audiocpu")
975969   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
976970
977971   MCFG_SOUND_ADD("vlm", VLM5030, 3580000)
branches/new_menus/src/mame/drivers/namcos86.c
r29543r29544
979979
980980/*******************************************************************/
981981
982static const namco_interface namco_config =
983{
984   8,      /* number of voices */
985   0       /* stereo */
986};
987
988
989982static MACHINE_CONFIG_START( hopmappy, namcos86_state )
990983
991984   /* basic machine hardware */
r29543r29544
10241017   MCFG_SOUND_ROUTE(1, "mono", 0.60)   /* only right channel is connected */
10251018
10261019   MCFG_SOUND_ADD("namco", NAMCO_CUS30, XTAL_49_152MHz/2048)
1027   MCFG_SOUND_CONFIG(namco_config)
1020   MCFG_NAMCO_AUDIO_VOICES(8)
10281021   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
10291022MACHINE_CONFIG_END
10301023
branches/new_menus/src/mame/drivers/gal3.c
r29543r29544
582582   GFXDECODE_ENTRY( "obj_board1", 0x000000, tile_layout,  0x000, 0x20 )
583583GFXDECODE_END
584584
585static const c140_interface C140_interface =
586{
587   C140_TYPE_SYSTEM21
588};
589
590585static MACHINE_CONFIG_START( gal3, gal3_state )
591586   MCFG_CPU_ADD("maincpu", M68020, 49152000/2)
592587   MCFG_CPU_PROGRAM_MAP(cpu_mst_map)
r29543r29544
638633   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
639634
640635   MCFG_C140_ADD("c140_16g", 8000000/374)
641   MCFG_SOUND_CONFIG(C140_interface)   //to be verified
636   MCFG_C140_BANK_TYPE(C140_TYPE_SYSTEM21)    //to be verified
642637   MCFG_SOUND_ROUTE(0, "lspeaker", 0.50)
643638   MCFG_SOUND_ROUTE(1, "rspeaker", 0.50)
644639
645640   MCFG_C140_ADD("c140_16a", 8000000/374)
646   MCFG_SOUND_CONFIG(C140_interface)
641   MCFG_C140_BANK_TYPE(C140_TYPE_SYSTEM21)
647642   MCFG_SOUND_ROUTE(0, "lspeaker", 0.50)
648643   MCFG_SOUND_ROUTE(1, "rspeaker", 0.50)
649644MACHINE_CONFIG_END
branches/new_menus/src/mame/drivers/namcos21.c
r29543r29544
14721472   GFXDECODE_ENTRY( "gfx1", 0x000000, tile_layout,  0x1000, 0x10 )
14731473GFXDECODE_END
14741474
1475static const c140_interface C140_interface =
1476{
1477   C140_TYPE_SYSTEM21
1478};
1479
14801475MACHINE_START_MEMBER(namcos21_state,namcos21)
14811476{
14821477   MACHINE_START_CALL_MEMBER( namcos2 );
r29543r29544
15351530   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
15361531
15371532   MCFG_C140_ADD("c140", 8000000/374)
1538   MCFG_SOUND_CONFIG(C140_interface)
1533   MCFG_C140_BANK_TYPE(C140_TYPE_SYSTEM21)
15391534   MCFG_SOUND_ROUTE(0, "lspeaker", 0.50)
15401535   MCFG_SOUND_ROUTE(1, "rspeaker", 0.50)
15411536
r29543r29544
15911586   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
15921587
15931588   MCFG_C140_ADD("c140", 8000000/374)
1594   MCFG_SOUND_CONFIG(C140_interface)
1589   MCFG_C140_BANK_TYPE(C140_TYPE_SYSTEM21)
15951590   MCFG_SOUND_ROUTE(0, "lspeaker", 0.50)
15961591   MCFG_SOUND_ROUTE(1, "rspeaker", 0.50)
15971592
r29543r29544
16511646   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
16521647
16531648   MCFG_C140_ADD("c140", 8000000/374)
1654   MCFG_SOUND_CONFIG(C140_interface)
1649   MCFG_C140_BANK_TYPE(C140_TYPE_SYSTEM21)
16551650   MCFG_SOUND_ROUTE(0, "lspeaker", 0.50)
16561651   MCFG_SOUND_ROUTE(1, "rspeaker", 0.50)
16571652
branches/new_menus/src/mame/drivers/seta.c
r29543r29544
14761476
14771477***************************************************************************/
14781478
1479static const x1_010_interface seta_sound_intf =
1480{
1481   0x0000,     /* address */
1482};
1483static const x1_010_interface seta_sound_intf2 =
1484{
1485   0x1000,     /* address */
1486};
1487
14881479WRITE_LINE_MEMBER(seta_state::utoukond_ym3438_interrupt)
14891480{
14901481   m_audiocpu->set_input_line(INPUT_LINE_NMI, state);
r29543r29544
76517642   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
76527643
76537644   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
7654   MCFG_SOUND_CONFIG(seta_sound_intf)
76557645   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
76567646   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
76577647MACHINE_CONFIG_END
r29543r29544
76957685   /* sound hardware */
76967686   MCFG_SPEAKER_STANDARD_MONO("mono")
76977687   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
7698   MCFG_SOUND_CONFIG(seta_sound_intf)
76997688   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
77007689MACHINE_CONFIG_END
77017690
r29543r29544
77607749   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
77617750
77627751   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
7763   MCFG_SOUND_CONFIG(seta_sound_intf2)
7752   MCFG_X1_010_ADDRESS(0x1000)
77647753   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
77657754   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
77667755MACHINE_CONFIG_END
r29543r29544
78107799   /* sound hardware */
78117800   MCFG_SPEAKER_STANDARD_MONO("mono")
78127801   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
7813   MCFG_SOUND_CONFIG(seta_sound_intf2)
7802   MCFG_X1_010_ADDRESS(0x1000)
78147803   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
78157804MACHINE_CONFIG_END
78167805
r29543r29544
78547843   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
78557844
78567845   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
7857   MCFG_SOUND_CONFIG(seta_sound_intf)
78587846   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
78597847   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
78607848MACHINE_CONFIG_END
r29543r29544
78937881   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
78947882
78957883   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
7896   MCFG_SOUND_CONFIG(seta_sound_intf)
78977884   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
78987885   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
78997886MACHINE_CONFIG_END
r29543r29544
79427929   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
79437930
79447931   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
7945   MCFG_SOUND_CONFIG(seta_sound_intf)
79467932   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
79477933   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
79487934MACHINE_CONFIG_END
r29543r29544
79807966   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
79817967
79827968   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
7983   MCFG_SOUND_CONFIG(seta_sound_intf)
79847969   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
79857970   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
79867971MACHINE_CONFIG_END
r29543r29544
80198004   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
80208005
80218006   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8022   MCFG_SOUND_CONFIG(seta_sound_intf)
80238007   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
80248008   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
80258009MACHINE_CONFIG_END
r29543r29544
80948078   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
80958079
80968080   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8097   MCFG_SOUND_CONFIG(seta_sound_intf)
80988081   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
80998082   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
81008083MACHINE_CONFIG_END
r29543r29544
81398122   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
81408123
81418124   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8142   MCFG_SOUND_CONFIG(seta_sound_intf)
81438125   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
81448126   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
81458127MACHINE_CONFIG_END
r29543r29544
81778159   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
81788160
81798161   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8180   MCFG_SOUND_CONFIG(seta_sound_intf)
81818162   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
81828163   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
81838164MACHINE_CONFIG_END
r29543r29544
82328213   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
82338214
82348215   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8235   MCFG_SOUND_CONFIG(seta_sound_intf)
82368216   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
82378217   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
82388218MACHINE_CONFIG_END
r29543r29544
82718251   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
82728252
82738253   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8274   MCFG_SOUND_CONFIG(seta_sound_intf)
82758254   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
82768255   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
82778256MACHINE_CONFIG_END
r29543r29544
83188297   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
83198298
83208299   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8321   MCFG_SOUND_CONFIG(seta_sound_intf)
83228300   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
83238301   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
83248302MACHINE_CONFIG_END
r29543r29544
83848362   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
83858363
83868364   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8387   MCFG_SOUND_CONFIG(seta_sound_intf)
83888365   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
83898366   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
83908367MACHINE_CONFIG_END
r29543r29544
84308407   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
84318408
84328409   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8433   MCFG_SOUND_CONFIG(seta_sound_intf)
84348410   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
84358411   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
84368412MACHINE_CONFIG_END
r29543r29544
84678443   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
84688444
84698445   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8470   MCFG_SOUND_CONFIG(seta_sound_intf)
84718446   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
84728447   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
84738448MACHINE_CONFIG_END
r29543r29544
85108485   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
85118486
85128487   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8513   MCFG_SOUND_CONFIG(seta_sound_intf)
85148488   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
85158489   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
85168490MACHINE_CONFIG_END
r29543r29544
85508524   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
85518525
85528526   MCFG_SOUND_ADD("x1snd", X1_010, 14318180)   /* 14.318180 MHz */
8553   MCFG_SOUND_CONFIG(seta_sound_intf)
85548527   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
85558528   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
85568529MACHINE_CONFIG_END
r29543r29544
85938566   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
85948567
85958568   MCFG_SOUND_ADD("x1snd", X1_010, 14318180)   /* 14.318180 MHz */
8596   MCFG_SOUND_CONFIG(seta_sound_intf)
85978569   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
85988570   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
85998571MACHINE_CONFIG_END
r29543r29544
86358607   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
86368608
86378609   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8638   MCFG_SOUND_CONFIG(seta_sound_intf)
86398610   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
86408611   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
86418612MACHINE_CONFIG_END
r29543r29544
86828653   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
86838654
86848655   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8685   MCFG_SOUND_CONFIG(seta_sound_intf)
86868656   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
86878657   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
86888658MACHINE_CONFIG_END
r29543r29544
87258695   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
87268696
87278697   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8728   MCFG_SOUND_CONFIG(seta_sound_intf)
87298698   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
87308699   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
87318700MACHINE_CONFIG_END
r29543r29544
87758744   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
87768745
87778746   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8778   MCFG_SOUND_CONFIG(seta_sound_intf)
87798747   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
87808748   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
87818749MACHINE_CONFIG_END
r29543r29544
88158783   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
88168784
88178785   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8818   MCFG_SOUND_CONFIG(seta_sound_intf)
88198786   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
88208787   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
88218788MACHINE_CONFIG_END
r29543r29544
88938860   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
88948861
88958862   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8896   MCFG_SOUND_CONFIG(seta_sound_intf)
88978863   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
88988864   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
88998865MACHINE_CONFIG_END
r29543r29544
89358901   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
89368902
89378903   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8938   MCFG_SOUND_CONFIG(seta_sound_intf)
89398904   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
89408905   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
89418906MACHINE_CONFIG_END
r29543r29544
89778942   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
89788943
89798944   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
8980   MCFG_SOUND_CONFIG(seta_sound_intf)
89818945   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
89828946   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
89838947MACHINE_CONFIG_END
r29543r29544
90889052   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
90899053
90909054   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
9091   MCFG_SOUND_CONFIG(seta_sound_intf)
90929055   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
90939056   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
90949057MACHINE_CONFIG_END
r29543r29544
91279090   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
91289091
91299092   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
9130   MCFG_SOUND_CONFIG(seta_sound_intf)
91319093   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
91329094   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
91339095MACHINE_CONFIG_END
r29543r29544
91709132   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
91719133
91729134   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)
9173   MCFG_SOUND_CONFIG(seta_sound_intf)
91749135   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
91759136   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
91769137
r29543r29544
92229183   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
92239184
92249185   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
9225   MCFG_SOUND_CONFIG(seta_sound_intf)
92269186   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
92279187   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
92289188MACHINE_CONFIG_END
r29543r29544
92719231   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
92729232
92739233   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
9274   MCFG_SOUND_CONFIG(seta_sound_intf)
92759234   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
92769235   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
92779236MACHINE_CONFIG_END
r29543r29544
93269285   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
93279286
93289287   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)   /* 16 MHz */
9329   MCFG_SOUND_CONFIG(seta_sound_intf)
93309288   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
93319289   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
93329290MACHINE_CONFIG_END
r29543r29544
94439401   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
94449402
94459403   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)
9446   MCFG_SOUND_CONFIG(seta_sound_intf)
94479404   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
94489405   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
94499406
branches/new_menus/src/mame/drivers/jrpacman.c
r29543r29544
260260
261261/*************************************
262262 *
263 *  Sound interfaces
264 *
265 *************************************/
266
267static const namco_interface namco_config =
268{
269   3,          /* number of voices */
270   0           /* stereo */
271};
272
273
274
275/*************************************
276 *
277263 *  Machine drivers
278264 *
279265 *************************************/
r29543r29544
311297   MCFG_SPEAKER_STANDARD_MONO("mono")
312298
313299   MCFG_SOUND_ADD("namco", NAMCO, 3072000/32)
314   MCFG_SOUND_CONFIG(namco_config)
300   MCFG_NAMCO_AUDIO_VOICES(3)
315301   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
316302MACHINE_CONFIG_END
317303
branches/new_menus/src/mame/drivers/crystal.c
r29543r29544
894894INPUT_PORTS_END
895895
896896
897
898static const vr0_interface vr0_config =
899{
900   0x04800000
901};
902
903897static MACHINE_CONFIG_START( crystal, crystal_state )
904898
905899   MCFG_CPU_ADD("maincpu", SE3208, 43000000)
r29543r29544
927921   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
928922
929923   MCFG_SOUND_VRENDER0_ADD("vrender", 0)
930   MCFG_SOUND_CONFIG(vr0_config)
924   MCFG_VR0_REGBASE(0x04800000)
931925   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
932926   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
933927MACHINE_CONFIG_END
branches/new_menus/src/mame/drivers/famibox.c
r29543r29544
511511
512512*******************************************************/
513513
514static const nesapu_interface famibox_interface_1 =
515{
516   "maincpu"
517};
518
519514PALETTE_INIT_MEMBER(famibox_state, famibox)
520515{
521516   m_ppu->init_palette(palette, 0);
r29543r29544
574569   MCFG_CPU_ADD("maincpu", N2A03, N2A03_DEFAULTCLOCK)
575570   MCFG_CPU_PROGRAM_MAP(famibox_map)
576571
577
578572   /* video hardware */
579573   MCFG_SCREEN_ADD("screen", RASTER)
580574   MCFG_SCREEN_REFRESH_RATE(60)
r29543r29544
595589   MCFG_SPEAKER_STANDARD_MONO("mono")
596590
597591   MCFG_SOUND_ADD("nesapu", NES_APU, N2A03_DEFAULTCLOCK)
598   MCFG_SOUND_CONFIG(famibox_interface_1)
592   MCFG_NES_APU_CPU("maincpu")
599593   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
600594
601595   MCFG_DAC_ADD("dac")
branches/new_menus/src/mame/drivers/rallyx.c
r29543r29544
797797 *
798798 *************************************/
799799
800static const namco_interface namco_config =
801{
802   3,              /* number of voices */
803   0               /* stereo */
804};
805
806800static const char *const rallyx_sample_names[] =
807801{
808802   "*rallyx",
r29543r29544
880874   MCFG_SPEAKER_STANDARD_MONO("mono")
881875
882876   MCFG_SOUND_ADD("namco", NAMCO, MASTER_CLOCK/6/32) /* 96 KHz */
883   MCFG_SOUND_CONFIG(namco_config)
877   MCFG_NAMCO_AUDIO_VOICES(3)
884878   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
885879
886880   MCFG_SAMPLES_ADD("samples", rallyx_samples_interface)
branches/new_menus/src/mame/drivers/champbwl.c
r29543r29544
430430   GFXDECODE_ENTRY( "gfx1", 0, charlayout, 0, 32 )
431431GFXDECODE_END
432432
433static const x1_010_interface champbwl_sound_intf =
434{
435   0x0000      /* address */
436};
437
438433MACHINE_START_MEMBER(champbwl_state,champbwl)
439434{
440435   UINT8 *ROM = memregion("maincpu")->base();
r29543r29544
508503   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
509504
510505   MCFG_SOUND_ADD("x1snd", X1_010, 16000000)
511   MCFG_SOUND_CONFIG(champbwl_sound_intf)
512506   MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
513507   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
514508MACHINE_CONFIG_END
r29543r29544
573567   /* sound hardware */
574568   MCFG_SPEAKER_STANDARD_MONO("mono")
575569   MCFG_SOUND_ADD("x1snd", X1_010, XTAL_14_31818MHz)
576   MCFG_SOUND_CONFIG(champbwl_sound_intf)
577570   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
578571MACHINE_CONFIG_END
579572
Property changes on: branches/new_menus
Modified: svn:mergeinfo
   Merged /trunk:r29506-29535

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