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r29497 Wednesday 9th April, 2014 at 17:06:26 UTC by Osso
g1_device: converted to devcb2 (nw)

[src/emu/bus/isa]

gus.c gus.h

trunk/src/emu/bus/isa/gus.c

r29496	r29497
85	85	{
86	86	if(data & 0x80)
87	87	{
88		m_timer1_irq_func(0);
89		m_timer2_irq_func(0);
	88	m_timer1_irq_handler(0);
	89	m_timer2_irq_handler(0);
90	90	m_adlib_status &= ~0xe0;
91	91	logerror("GUS: Timer flags reset\n");
92	92	}
r29496	r29497
122	122	if(m_timer_ctrl & 0x02)
123	123	{
124	124	m_adlib_status |= 0x01;
125		m_nmi_func(1);
	125	m_nmi_handler(1);
126	126	logerror("GUS: 2X9 Timer triggered!\n");
127	127	}
128	128	}
r29496	r29497
209	209	m_adlib_status |= 0xc0;
210	210	m_timer1_count = m_timer1_value;
211	211	if(m_timer_ctrl & 0x04)
212		m_timer1_irq_func(1);
	212	m_timer1_irq_handler(1);
213	213	}
214	214	m_timer1_count++;
215	215	}
r29496	r29497
222	222	m_adlib_status |= 0xa0;
223	223	m_timer2_count = m_timer2_value;
224	224	if(m_timer_ctrl & 0x08)
225		m_timer2_irq_func(1);
	225	m_timer2_irq_handler(1);
226	226	}
227	227	m_timer2_count++;
228	228	}
229	229	break;
230	230	case DMA_TIMER:
231		m_drq1(1);
	231	m_drq1_handler(1);
232	232	break;
233	233	case VOL_RAMP_TIMER:
234	234	update_volume_ramps();
r29496	r29497
352	352	acia6850_device(mconfig, GGF1, "Gravis GF1", tag, owner, clock, "gf1", __FILE__),
353	353	device_sound_interface( mconfig, *this ),
354	354	m_txirq_handler(*this),
355		m_rxirq_handler(*this)
	355	m_rxirq_handler(*this),
	356	m_wave_irq_handler(*this),
	357	m_ramp_irq_handler(*this),
	358	m_timer1_irq_handler(*this),
	359	m_timer2_irq_handler(*this),
	360	m_sb_irq_handler(*this),
	361	m_dma_irq_handler(*this),
	362	m_drq1_handler(*this),
	363	m_drq2_handler(*this),
	364	m_nmi_handler(*this)
356	365	{
357	366	}
358	367
359		void gf1_device::device_config_complete()
360		{
361		// inherit a copy of the static data
362		const gf1_interface *intf = reinterpret_cast<const gf1_interface *>(static_config());
363		if (intf != NULL)
364		*static_cast<gf1_interface *>(this) = *intf;
365
366		// or initialize to defaults if none provided
367		else
368		{
369		memset(&wave_irq_cb, 0, sizeof(wave_irq_cb));
370		memset(&ramp_irq_cb, 0, sizeof(ramp_irq_cb));
371		memset(&timer1_irq_cb, 0, sizeof(timer1_irq_cb));
372		memset(&timer2_irq_cb, 0, sizeof(timer2_irq_cb));
373		memset(&sb_irq_cb, 0, sizeof(sb_irq_cb));
374		memset(&dma_irq_cb, 0, sizeof(dma_irq_cb));
375		memset(&drq1_cb, 0, sizeof(drq1_cb));
376		memset(&drq2_cb, 0, sizeof(drq2_cb));
377		memset(&nmi_cb, 0, sizeof(nmi_cb));
378		}
379		}
380
381	368	//-------------------------------------------------
382	369	//  device_start - device-specific startup
383	370	//-------------------------------------------------
r29496	r29497
391	378
392	379	m_txirq_handler.resolve_safe();
393	380	m_rxirq_handler.resolve_safe();
	381	m_wave_irq_handler.resolve_safe();
	382	m_ramp_irq_handler.resolve_safe();
	383	m_timer1_irq_handler.resolve_safe();
	384	m_timer2_irq_handler.resolve_safe();
	385	m_sb_irq_handler.resolve_safe();
	386	m_dma_irq_handler.resolve_safe();
	387	m_drq1_handler.resolve_safe();
	388	m_drq2_handler.resolve_safe();
	389	m_nmi_handler.resolve_safe();
394	390
395	391	// TODO: make DRAM size configurable.  Can be 256k, 512k, 768k, or 1024k
396	392	m_wave_ram.resize_and_clear(1024*1024);
r29496	r29497
405	401
406	402	save_item(NAME(m_wave_ram));
407	403
408		m_wave_irq_func.resolve(wave_irq_cb, *this);
409		m_ramp_irq_func.resolve(ramp_irq_cb, *this);
410		m_timer1_irq_func.resolve(timer1_irq_cb, *this);
411		m_timer2_irq_func.resolve(timer2_irq_cb, *this);
412		m_sb_irq_func.resolve(sb_irq_cb, *this);
413		m_dma_irq_func.resolve(dma_irq_cb, *this);
414		m_drq1.resolve(drq1_cb,*this);
415		m_drq2.resolve(drq2_cb,*this);
416		m_nmi_func.resolve(nmi_cb, *this);
417
418	404	m_voice_irq_current = 0;
419	405	m_voice_irq_ptr = 0;
420	406	m_dma_channel1 = 0;
r29496	r29497
499	485	{
500	486	ret = m_dma_dram_ctrl;
501	487	m_dma_dram_ctrl &= ~0x40;
502		m_dma_irq_func(0);
	488	m_dma_irq_handler(0);
503	489	return ret;
504	490	}
505	491	case 0x45:  // Timer control
r29496	r29497
595	581	m_voice_irq_current++;
596	582	else
597	583	ret = 0xe0;
598		m_wave_irq_func(0);
599		m_ramp_irq_func(0);
	584	m_wave_irq_handler(0);
	585	m_ramp_irq_handler(0);
600	586	return ret;
601	587	}
602	588	break;
r29496	r29497
799	785	if(!(data & 0x02))
800	786	m_adlib_status &= ~0x01;
801	787	if(!(m_adlib_status & 0x19))
802		m_sb_irq_func(0);
	788	m_sb_irq_handler(0);
803	789	if(!(data & 0x04))
804	790	{
805	791	m_adlib_status &= ~0x40;
806		m_timer1_irq_func(0);
	792	m_timer1_irq_handler(0);
807	793	}
808	794	if(!(data & 0x08))
809	795	{
810	796	m_adlib_status &= ~0x20;
811		m_timer2_irq_func(0);
	797	m_timer2_irq_handler(0);
812	798	}
813	799	if((m_adlib_status & 0x60) != 0)
814	800	m_adlib_status &= ~0x80;
r29496	r29497
1044	1030	break;
1045	1031	case 0x05:
1046	1032	m_statread = 0;
1047		//m_other_irq_func(0);
	1033	//m_other_irq_handler(0);
1048	1034	break;
1049	1035	case 0x06:
1050	1036	// TODO: Jumper register (joy/MIDI enable)
r29496	r29497
1093	1079	if(m_reg_ctrl & 0x80)
1094	1080	{
1095	1081	m_statread |= 0x80;
1096		m_nmi_func(1);
	1082	m_nmi_handler(1);
1097	1083	}
1098	1084	return m_sb_data_2xe;
1099	1085	}
r29496	r29497
1108	1094	if(m_timer_ctrl & 0x20)
1109	1095	{
1110	1096	m_adlib_status |= 0x10;
1111		m_nmi_func(1);
	1097	m_nmi_handler(1);
1112	1098	logerror("GUS: SB 0x2XC IRQ active\n");
1113	1099	}
1114	1100	break;
r29496	r29497
1128	1114	if(m_timer_ctrl & 0x20)
1129	1115	{
1130	1116	m_adlib_status |= 0x08;
1131		m_nmi_func(1);
	1117	m_nmi_handler(1);
1132	1118	logerror("GUS: SB 0x2X6 IRQ active\n");
1133	1119	}
1134	1120	}
r29496	r29497
1153	1139	{
1154	1140	m_irq_source = 0xe0 | (voice & 0x1f);
1155	1141	m_irq_source &= ~0x80;
1156		m_wave_irq_func(1);
	1142	m_wave_irq_handler(1);
1157	1143	m_voice_irq_fifo[m_voice_irq_ptr % 32] = m_irq_source;
1158	1144	m_voice_irq_ptr++;
1159	1145	m_voice[voice].voice_ctrl |= 0x80;
r29496	r29497
1162	1148	{
1163	1149	m_irq_source = 0xe0 | (voice & 0x1f);
1164	1150	m_irq_source &= ~0x40;
1165		m_ramp_irq_func(1);
	1151	m_ramp_irq_handler(1);
1166	1152	m_voice_irq_fifo[m_voice_irq_ptr % 32] = m_irq_source;
1167	1153	m_voice_irq_ptr++;
1168	1154	}
r29496	r29497
1173	1159	if(source & IRQ_WAVETABLE)
1174	1160	{
1175	1161	m_irq_source |= 0x80;
1176		m_wave_irq_func(0);
	1162	m_wave_irq_handler(0);
1177	1163	}
1178	1164	if(source & IRQ_VOLUME_RAMP)
1179	1165	{
1180	1166	m_irq_source |= 0x40;
1181		m_ramp_irq_func(0);
	1167	m_ramp_irq_handler(0);
1182	1168	}
1183	1169	}
1184	1170
r29496	r29497
1204	1190	}
1205	1191	m_wave_ram[m_dma_current & 0xfffff] = data;
1206	1192	m_dma_current++;
1207		m_drq1(0);
	1193	m_drq1_handler(0);
1208	1194	}
1209	1195
1210	1196	void gf1_device::eop_w(int state)
r29496	r29497
1212	1198	if(state == ASSERT_LINE) {
1213	1199	// end of transfer
1214	1200	m_dmatimer->reset();
1215		//m_drq1(0);
	1201	//m_drq1_handler(0);
1216	1202	if(m_dma_dram_ctrl & 0x20)
1217	1203	{
1218	1204	m_dma_dram_ctrl |= 0x40;
1219		m_dma_irq_func(1);
	1205	m_dma_irq_handler(1);
1220	1206	}
1221	1207	logerror("GUS: End of transfer. (%05x)\n",m_dma_current);
1222	1208	}
r29496	r29497
1225	1211
1226	1212	/* 16-bit ISA card device implementation */
1227	1213
1228		static const gf1_interface gus_gf1_config =
1229		{
1230		DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER,isa16_gus_device,wavetable_irq),
1231		DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER,isa16_gus_device,volumeramp_irq),
1232		DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER,isa16_gus_device,timer1_irq),
1233		DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER,isa16_gus_device,timer2_irq),
1234		DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER,isa16_gus_device,sb_irq),
1235		DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER,isa16_gus_device,dma_irq),
1236		DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER,isa16_gus_device,drq1_w),
1237		DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER,isa16_gus_device,drq2_w),
1238		DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER,isa16_gus_device,nmi_w)
1239		};
1240
1241	1214	static MACHINE_CONFIG_FRAGMENT( gus_config )
1242	1215	MCFG_SPEAKER_STANDARD_STEREO("lspeaker","rspeaker")
1243	1216	MCFG_SOUND_ADD("gf1",GGF1,GF1_CLOCK)
1244		MCFG_SOUND_CONFIG(gus_gf1_config)
1245	1217	MCFG_SOUND_ROUTE(0,"lspeaker",0.50)
1246	1218	MCFG_SOUND_ROUTE(1,"rspeaker",0.50)
1247	1219
1248	1220	MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("mdout", midi_port_device, write_txd))
1249	1221	MCFG_GF1_TXIRQ_HANDLER(WRITELINE(isa16_gus_device, midi_txirq))
1250	1222	MCFG_GF1_RXIRQ_HANDLER(WRITELINE(isa16_gus_device, midi_txirq))
	1223	MCFG_GF1_WAVE_IRQ_HANDLER(WRITELINE(isa16_gus_device, wavetable_irq))
	1224	MCFG_GF1_RAMP_IRQ_HANDLER(WRITELINE(isa16_gus_device, volumeramp_irq))
	1225	MCFG_GF1_TIMER1_IRQ_HANDLER(WRITELINE(isa16_gus_device, timer1_irq))
	1226	MCFG_GF1_TIMER2_IRQ_HANDLER(WRITELINE(isa16_gus_device, timer2_irq))
	1227	MCFG_GF1_SB_IRQ_HANDLER(WRITELINE(isa16_gus_device, sb_irq))
	1228	MCFG_GF1_DMA_IRQ_HANDLER(WRITELINE(isa16_gus_device, dma_irq))
	1229	MCFG_GF1_DRQ1_HANDLER(WRITELINE(isa16_gus_device, drq1_w))
	1230	MCFG_GF1_DRQ2_HANDLER(WRITELINE(isa16_gus_device, drq2_w))
	1231	MCFG_GF1_NMI_HANDLER(WRITELINE(isa16_gus_device, nmi_w))
1251	1232
1252	1233	MCFG_MIDI_PORT_ADD("mdin", midiin_slot, "midiin")
1253	1234	MCFG_MIDI_RX_HANDLER(DEVWRITELINE("gf1", acia6850_device, write_rxd))

trunk/src/emu/bus/isa/gus.h

r29496	r29497
50	50	#define MCFG_GF1_RXIRQ_HANDLER(_devcb) \
51	51	devcb = &gf1_device::set_rxirq_handler(*device, DEVCB2_##_devcb);
52	52
	53	#define MCFG_GF1_WAVE_IRQ_HANDLER(_devcb) \
	54	devcb = &gf1_device::set_wave_irq_handler(*device, DEVCB2_##_devcb);
	55
	56	#define MCFG_GF1_RAMP_IRQ_HANDLER(_devcb) \
	57	devcb = &gf1_device::set_ramp_irq_handler(*device, DEVCB2_##_devcb);
	58
	59	#define MCFG_GF1_TIMER1_IRQ_HANDLER(_devcb) \
	60	devcb = &gf1_device::set_timer1_irq_handler(*device, DEVCB2_##_devcb);
	61
	62	#define MCFG_GF1_TIMER2_IRQ_HANDLER(_devcb) \
	63	devcb = &gf1_device::set_timer2_irq_handler(*device, DEVCB2_##_devcb);
	64
	65	#define MCFG_GF1_SB_IRQ_HANDLER(_devcb) \
	66	devcb = &gf1_device::set_sb_irq_handler(*device, DEVCB2_##_devcb);
	67
	68	#define MCFG_GF1_DMA_IRQ_HANDLER(_devcb) \
	69	devcb = &gf1_device::set_dma_irq_handler(*device, DEVCB2_##_devcb);
	70
	71	#define MCFG_GF1_DRQ1_HANDLER(_devcb) \
	72	devcb = &gf1_device::set_drq1_handler(*device, DEVCB2_##_devcb);
	73
	74	#define MCFG_GF1_DRQ2_HANDLER(_devcb) \
	75	devcb = &gf1_device::set_drq2_handler(*device, DEVCB2_##_devcb);
	76
	77	#define MCFG_GF1_NMI_HANDLER(_devcb) \
	78	devcb = &gf1_device::set_nmi_handler(*device, DEVCB2_##_devcb);
	79
53	80	//**************************************************************************
54	81	//  TYPE DEFINITIONS
55	82	//**************************************************************************
r29496	r29497
86	113	INT16 sample;  // current sample data
87	114	};
88	115
89		struct gf1_interface
90		{
91		devcb_write_line wave_irq_cb;
92		devcb_write_line ramp_irq_cb;
93		devcb_write_line timer1_irq_cb;
94		devcb_write_line timer2_irq_cb;
95		devcb_write_line sb_irq_cb;
96		devcb_write_line dma_irq_cb;
97		devcb_write_line drq1_cb;
98		devcb_write_line drq2_cb;
99		devcb_write_line nmi_cb;
100		};
101
102	116	class gf1_device :
103	117	public acia6850_device,
104		public device_sound_interface,
105		public gf1_interface
	118	public device_sound_interface
106	119	{
107	120	public:
108	121	// construction/destruction
r29496	r29497
110	123
111	124	template<class _Object> static devcb2_base &set_txirq_handler(device_t &device, _Object object) { return downcast<gf1_device &>(device).m_txirq_handler.set_callback(object); }
112	125	template<class _Object> static devcb2_base &set_rxirq_handler(device_t &device, _Object object) { return downcast<gf1_device &>(device).m_rxirq_handler.set_callback(object); }
	126	template<class _Object> static devcb2_base &set_wave_irq_handler(device_t &device, _Object object) { return downcast<gf1_device &>(device).m_wave_irq_handler.set_callback(object); }
	127	template<class _Object> static devcb2_base &set_ramp_irq_handler(device_t &device, _Object object) { return downcast<gf1_device &>(device).m_ramp_irq_handler.set_callback(object); }
	128	template<class _Object> static devcb2_base &set_timer1_irq_handler(device_t &device, _Object object) { return downcast<gf1_device &>(device).m_timer1_irq_handler.set_callback(object); }
	129	template<class _Object> static devcb2_base &set_timer2_irq_handler(device_t &device, _Object object) { return downcast<gf1_device &>(device).m_timer2_irq_handler.set_callback(object); }
	130	template<class _Object> static devcb2_base &set_sb_irq_handler(device_t &device, _Object object) { return downcast<gf1_device &>(device).m_sb_irq_handler.set_callback(object); }
	131	template<class _Object> static devcb2_base &set_dma_irq_handler(device_t &device, _Object object) { return downcast<gf1_device &>(device).m_dma_irq_handler.set_callback(object); }
	132	template<class _Object> static devcb2_base &set_drq1_handler(device_t &device, _Object object) { return downcast<gf1_device &>(device).m_drq1_handler.set_callback(object); }
	133	template<class _Object> static devcb2_base &set_drq2_handler(device_t &device, _Object object) { return downcast<gf1_device &>(device).m_drq2_handler.set_callback(object); }
	134	template<class _Object> static devcb2_base &set_nmi_handler(device_t &device, _Object object) { return downcast<gf1_device &>(device).m_nmi_handler.set_callback(object); }
113	135
114	136	// current IRQ/DMA channel getters
115	137	UINT8 gf1_irq() { if(m_gf1_irq != 0) return m_gf1_irq; else return m_midi_irq; }  // workaround for win95 loading dumb values
r29496	r29497
143	165	// optional information overrides
144	166	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
145	167	virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples);
146		virtual void device_config_complete();
147	168
148	169	// voice-specific registers
149	170	gus_voice m_voice[32];
r29496	r29497
178	199
179	200	virtual void update_irq();
180	201
181		devcb_resolved_write_line m_wave_irq_func;
182		devcb_resolved_write_line m_ramp_irq_func;
183		devcb_resolved_write_line m_timer1_irq_func;
184		devcb_resolved_write_line m_timer2_irq_func;
185		devcb_resolved_write_line m_sb_irq_func;
186		devcb_resolved_write_line m_dma_irq_func;
187		devcb_resolved_write_line m_drq1;
188		devcb_resolved_write_line m_drq2;
189		devcb_resolved_write_line m_nmi_func;
190
191	202	private:
192	203	// internal state
193	204	sound_stream* m_stream;
r29496	r29497
238	249
239	250	devcb2_write_line m_txirq_handler;
240	251	devcb2_write_line m_rxirq_handler;
	252	devcb2_write_line m_wave_irq_handler;
	253	devcb2_write_line m_ramp_irq_handler;
	254	devcb2_write_line m_timer1_irq_handler;
	255	devcb2_write_line m_timer2_irq_handler;
	256	devcb2_write_line m_sb_irq_handler;
	257	devcb2_write_line m_dma_irq_handler;
	258	devcb2_write_line m_drq1_handler;
	259	devcb2_write_line m_drq2_handler;
	260	devcb2_write_line m_nmi_handler;
241	261	};
242	262
243	263	class isa16_gus_device :

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