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r26448 Saturday 30th November, 2013 at 02:31:01 UTC by David Haywood
various PGM protection cleanups / fixes (orlegend, olds, svgpcb) [iq_132]
[src/mame/includes]pgm.h
[src/mame/machine]igs028.c pgmcrypt.c pgmprot_orlegend.c

trunk/src/mame/machine/igs028.c
r26447r26448
6666      case 0x6: return 0x4030a4;
6767      case 0x7: return 0x403000;
6868      case 0x9: return 0x40306e;
69      case 0xb: return 0x403044;
6970   }
7071
7172   return 0;
trunk/src/mame/machine/pgmprot_orlegend.c
r26447r26448
1313#include "emu.h"
1414#include "includes/pgm.h"
1515
16/*** ASIC 3 (oriental legends protection) ****************************************/
17
18void pgm_asic3_state::asic3_compute_hold()
16void pgm_asic3_state::asic3_compute_hold(int y, int z)
1917{
20   // The mode is dependent on the region
21   static const int modes[4] = { 1, 1, 3, 2 };
22   int mode = modes[ioport("Region")->read() & 3];
18   unsigned short old = m_asic3_hold;
2319
24   switch (mode)
20   m_asic3_hold = ((old << 1) | (old >> 15));
21
22   m_asic3_hold ^= 0x2bad;
23   m_asic3_hold ^= BIT(z, y);
24   m_asic3_hold ^= BIT(m_asic3_x, 1) << 6;
25   m_asic3_hold ^= BIT(m_asic3_x, 2) << 10;
26   m_asic3_hold ^= BIT(old, 5);
27
28   switch (ioport("Region")->read()) // The mode is dependent on the region
2529   {
26   case 1:
27      m_asic3_hold =
28         (m_asic3_hold << 1)
29            ^ 0x2bad
30            ^ BIT(m_asic3_hold, 15) ^ BIT(m_asic3_hold, 10) ^ BIT(m_asic3_hold, 8) ^ BIT(m_asic3_hold, 5)
31            ^ BIT(m_asic3_z, m_asic3_y)
32            ^ (BIT(m_asic3_x, 0) << 1) ^ (BIT(m_asic3_x, 1) << 6) ^ (BIT(m_asic3_x, 2) << 10) ^ (BIT(m_asic3_x, 3) << 14);
30      case 0:
31      case 1:
32         m_asic3_hold ^= BIT(old, 10) ^ BIT(old, 8) ^ (BIT(m_asic3_x, 0) << 1) ^ (BIT(m_asic3_x, 3) << 14);
3333      break;
34   case 2:
35      m_asic3_hold =
36         (m_asic3_hold << 1)
37            ^ 0x2bad
38            ^ BIT(m_asic3_hold, 15) ^ BIT(m_asic3_hold, 7) ^ BIT(m_asic3_hold, 6) ^ BIT(m_asic3_hold, 5)
39            ^ BIT(m_asic3_z, m_asic3_y)
40            ^ (BIT(m_asic3_x, 0) << 4) ^ (BIT(m_asic3_x, 1) << 6) ^ (BIT(m_asic3_x, 2) << 10) ^ (BIT(m_asic3_x, 3) << 12);
34
35      case 2:
36         m_asic3_hold ^= BIT(old, 10) ^ BIT(old, 8) ^ (BIT(m_asic3_x, 0) << 4) ^ (BIT(m_asic3_x, 3) << 12);
4137      break;
42   case 3:
43      m_asic3_hold =
44         (m_asic3_hold << 1)
45            ^ 0x2bad
46            ^ BIT(m_asic3_hold, 15) ^ BIT(m_asic3_hold, 10) ^ BIT(m_asic3_hold, 8) ^ BIT(m_asic3_hold, 5)
47            ^ BIT(m_asic3_z, m_asic3_y)
48            ^ (BIT(m_asic3_x, 0) << 4) ^ (BIT(m_asic3_x, 1) << 6) ^ (BIT(m_asic3_x, 2) << 10) ^ (BIT(m_asic3_x, 3) << 12);
38
39      case 3:
40         m_asic3_hold ^= BIT(old,  7) ^ BIT(old, 6) ^ (BIT(m_asic3_x, 0) << 4) ^ (BIT(m_asic3_x, 3) << 12);
4941      break;
5042   }
5143}
5244
53READ16_MEMBER(pgm_asic3_state::pgm_asic3_r )
45READ16_MEMBER(pgm_asic3_state::pgm_asic3_r)
5446{
55   UINT8 res = 0;
56   /* region is supplied by the protection device */
57
5847   switch (m_asic3_reg)
5948   {
60   case 0x00: res = (m_asic3_latch[0] & 0xf7) | ((ioport("Region")->read() << 3) & 0x08); break;
61   case 0x01: res = m_asic3_latch[1]; break;
62   case 0x02: res = (m_asic3_latch[2] & 0x7f) | ((ioport("Region")->read() << 6) & 0x80); break;
63   case 0x03:
64      res = (BIT(m_asic3_hold, 15) << 0)
65         | (BIT(m_asic3_hold, 12) << 1)
66         | (BIT(m_asic3_hold, 13) << 2)
67         | (BIT(m_asic3_hold, 10) << 3)
68         | (BIT(m_asic3_hold, 7) << 4)
69         | (BIT(m_asic3_hold, 9) << 5)
70         | (BIT(m_asic3_hold, 2) << 6)
71         | (BIT(m_asic3_hold, 5) << 7);
72      break;
73   case 0x20: res = 0x49; break;
74   case 0x21: res = 0x47; break;
75   case 0x22: res = 0x53; break;
76   case 0x24: res = 0x41; break;
77   case 0x25: res = 0x41; break;
78   case 0x26: res = 0x7f; break;
79   case 0x27: res = 0x41; break;
80   case 0x28: res = 0x41; break;
81   case 0x2a: res = 0x3e; break;
82   case 0x2b: res = 0x41; break;
83   case 0x2c: res = 0x49; break;
84   case 0x2d: res = 0xf9; break;
85   case 0x2e: res = 0x0a; break;
86   case 0x30: res = 0x26; break;
87   case 0x31: res = 0x49; break;
88   case 0x32: res = 0x49; break;
89   case 0x33: res = 0x49; break;
90   case 0x34: res = 0x32; break;
49      case 0x00: // region is supplied by the protection device
50         return (m_asic3_latch[0] & 0xf7) | ((ioport("Region")->read() << 3) & 0x08);
51
52      case 0x01:
53         return m_asic3_latch[1];
54
55      case 0x02: // region is supplied by the protection device
56         return (m_asic3_latch[2] & 0x7f) | ((ioport("Region")->read() << 6) & 0x80);
57
58      case 0x03:
59         return BITSWAP8(m_asic3_hold, 5,2,9,7,10,13,12,15);
60
61      // case $157674, expected return $157686
62      case 0x20: return 0x49; // "IGS"
63      case 0x21: return 0x47;
64      case 0x22: return 0x53;
65
66      case 0x24: return 0x41;
67      case 0x25: return 0x41;
68      case 0x26: return 0x7f;
69      case 0x27: return 0x41;
70      case 0x28: return 0x41;
71
72      case 0x2a: return 0x3e;
73      case 0x2b: return 0x41;
74      case 0x2c: return 0x49;
75      case 0x2d: return 0xf9;
76      case 0x2e: return 0x0a;
77
78      case 0x30: return 0x26;
79      case 0x31: return 0x49;
80      case 0x32: return 0x49;
81      case 0x33: return 0x49;
82      case 0x34: return 0x32;
83
84   //   default:
85   //       logerror("ASIC3 R: CMD %2.2X PC: %6.6x\n", m_asic3_reg, space.device().safe_pc());
9186   }
9287
93   return res;
88   return 0;
9489}
9590
96WRITE16_MEMBER(pgm_asic3_state::pgm_asic3_w )
91WRITE16_MEMBER(pgm_asic3_state::pgm_asic3_w)
9792{
98   if(ACCESSING_BITS_0_7)
93   if (offset == 0) {
94      m_asic3_reg = data;
95      return;
96   }
97
98   switch (m_asic3_reg)
9999   {
100      if (m_asic3_reg < 3)
100      case 0x00:
101      case 0x01:
102      case 0x02:
101103         m_asic3_latch[m_asic3_reg] = data << 1;
102      else if (m_asic3_reg == 0xa0)
103         m_asic3_hold = 0;
104      else if (m_asic3_reg == 0x40)
104      break;
105
106   //   case 0x03: // move.w  #$88, $c0400e.l
107   //   case 0x04: // move.w  #$84, $c0400e.l
108   //   case 0x05: // move.w  #$A0, $c0400e.l
109   //   break;
110
111      case 0x40:
112         m_asic3_hilo = (m_asic3_hilo << 8) | data;
113      break;
114
115      case 0x41: // Same as CMD 40. What is the purpose of writing data here again??
116      case 0x42:
117      case 0x43:
118      case 0x44:
119      case 0x45:
120      case 0x46:
121      case 0x47:
122      break;
123
124      case 0x48:
105125      {
106         m_asic3_h2 = m_asic3_h1;
107         m_asic3_h1 = data;
108      }
109      else if (m_asic3_reg == 0x48)
110      {
111126         m_asic3_x = 0;
112         if (!(m_asic3_h2 & 0x0a))
113            m_asic3_x |= 8;
114         if (!(m_asic3_h2 & 0x90))
115            m_asic3_x |= 4;
116         if (!(m_asic3_h1 & 0x06))
117            m_asic3_x |= 2;
118         if (!(m_asic3_h1 & 0x90))
119            m_asic3_x |= 1;
127         if ((m_asic3_hilo & 0x0090) == 0) m_asic3_x |= 0x01;
128         if ((m_asic3_hilo & 0x0006) == 0) m_asic3_x |= 0x02;
129         if ((m_asic3_hilo & 0x9000) == 0) m_asic3_x |= 0x04;
130         if ((m_asic3_hilo & 0x0a00) == 0) m_asic3_x |= 0x08;
120131      }
121      else if(m_asic3_reg >= 0x80 && m_asic3_reg <= 0x87)
122      {
123         m_asic3_y = m_asic3_reg & 7;
124         m_asic3_z = data;
125         asic3_compute_hold();
126      }
127   }
128}
132      break;
129133
130WRITE16_MEMBER(pgm_asic3_state::pgm_asic3_reg_w )
131{
132   if(ACCESSING_BITS_0_7)
133      m_asic3_reg = data & 0xff;
134}
134   //   case 0x50: // move.w  #$50, $c0400e.l
135   //   break;
135136
137      case 0x80:
138      case 0x81:
139      case 0x82:
140      case 0x83:
141      case 0x84:
142      case 0x85:
143      case 0x86:
144      case 0x87:
145         asic3_compute_hold(m_asic3_reg & 0x07, data);
146      break;
136147
148      case 0xa0:
149         m_asic3_hold = 0;
150      break;
137151
152      default:
153          logerror("ASIC3 W: CMD %2.2X DATA: %4.4x, PC: %6.6x\n", m_asic3_reg, data, space.device().safe_pc());
154   }
155}
138156
139
140157/* Oriental Legend INIT */
141158
142159DRIVER_INIT_MEMBER(pgm_asic3_state,orlegend)
143160{
144161   pgm_basic_init();
145162
146   m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xC0400e, 0xC0400f, read16_delegate(FUNC(pgm_asic3_state::pgm_asic3_r),this), write16_delegate(FUNC(pgm_asic3_state::pgm_asic3_w),this));
147   m_maincpu->space(AS_PROGRAM).install_write_handler(0xC04000, 0xC04001, write16_delegate(FUNC(pgm_asic3_state::pgm_asic3_reg_w),this));
163   m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xC04000, 0xC0400f, read16_delegate(FUNC(pgm_asic3_state::pgm_asic3_r),this), write16_delegate(FUNC(pgm_asic3_state::pgm_asic3_w),this));
148164
149165   m_asic3_reg = 0;
150166   m_asic3_latch[0] = 0;
151167   m_asic3_latch[1] = 0;
152168   m_asic3_latch[2] = 0;
153169   m_asic3_x = 0;
154   m_asic3_y = 0;
155   m_asic3_z = 0;
156   m_asic3_h1 = 0;
157   m_asic3_h2 = 0;
170   m_asic3_hilo = 0;
158171   m_asic3_hold = 0;
159172
160173   save_item(NAME(m_asic3_reg));
161174   save_item(NAME(m_asic3_latch));
162175   save_item(NAME(m_asic3_x));
163   save_item(NAME(m_asic3_y));
164   save_item(NAME(m_asic3_z));
165   save_item(NAME(m_asic3_h1));
166   save_item(NAME(m_asic3_h2));
176   save_item(NAME(m_asic3_hilo));
167177   save_item(NAME(m_asic3_hold));
168178}
169179
trunk/src/mame/machine/pgmcrypt.c
r26447r26448
743743      IGS27_CRYPT2_ALT3
744744      IGS27_CRYPT3
745745      IGS27_CRYPT4 // ok?
746      IGS27_CRYPT5_ALT  //
746      IGS27_CRYPT5  // ok?
747747      IGS27_CRYPT6_ALT // ok?
748748      IGS27_CRYPT7
749749      IGS27_CRYPT8_ALT
trunk/src/mame/includes/pgm.h
r26447r26448
106106};
107107
108108
109/* for machine/pgmprot.c type games */
109/* for machine/pgmprot_orlegend.c type games */
110110class pgm_asic3_state : public pgm_state
111111{
112112public:
r26447r26448
118118   UINT8         m_asic3_reg;
119119   UINT8         m_asic3_latch[3];
120120   UINT8         m_asic3_x;
121   UINT8         m_asic3_y;
122   UINT8         m_asic3_z;
123   UINT16        m_asic3_h1;
124   UINT16        m_asic3_h2;
121   UINT16        m_asic3_hilo;
125122   UINT16        m_asic3_hold;
126123
127
128
129124   DECLARE_DRIVER_INIT(orlegend);
130   void asic3_compute_hold();
125   void asic3_compute_hold(int,int);
131126   DECLARE_READ16_MEMBER( pgm_asic3_r );
132127   DECLARE_WRITE16_MEMBER( pgm_asic3_w );
133128   DECLARE_WRITE16_MEMBER( pgm_asic3_reg_w );

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