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r26447 Saturday 30th November, 2013 at 00:40:20 UTC by Barry Rodewald
i386: Added the ability to read and write to the Pentium and P6 event/performance counter MSRs.  Nothing is actually counted, though.  Also added reading and writing of the time stamp counter MSR.
[src/emu/cpu/i386]i386priv.h

trunk/src/emu/cpu/i386/i386priv.h
r26446r26447
402402   UINT32 cpu_version;
403403   UINT32 feature_flags;
404404   UINT64 tsc;
405   UINT64 perfctr[2];
405406
406
407407   // FPU
408408   floatx80 x87_reg[8];
409409
r26446r26447
13761376    MSR ACCESS
13771377***********************************************************************************/
13781378
1379// Pentium MSR handling
1380UINT64 pentium_msr_read(i386_state *cpustate, UINT32 offset,UINT8 *valid_msr)
1381{
1382   switch(offset)
1383   {
1384   // Machine Check Exception (TODO)
1385   case 0x00:
1386      *valid_msr = 1;
1387      popmessage("RDMSR: Reading P5_MC_ADDR");
1388      return 0;
1389   case 0x01:
1390      *valid_msr = 1;
1391      popmessage("RDMSR: Reading P5_MC_TYPE");
1392      return 0;
1393   // Time Stamp Counter
1394   case 0x10:
1395      *valid_msr = 1;
1396      popmessage("RDMSR: Reading TSC");
1397      return cpustate->tsc;
1398   // Event Counters (TODO)
1399   case 0x11:  // CESR
1400      *valid_msr = 1;
1401      popmessage("WRMSR: Reading CESR");
1402      return 0;
1403   case 0x12:  // CTR0
1404      *valid_msr = 1;
1405      return cpustate->perfctr[0];
1406   case 0x13:  // CTR1
1407      *valid_msr = 1;
1408      return cpustate->perfctr[1];
1409   default:
1410      logerror("RDMSR: invalid P5 MSR read %08x at %08x\n",offset,cpustate->pc-2);
1411      *valid_msr = 0;
1412      return 0;
1413   }
1414   return -1;
1415}
1416
1417void pentium_msr_write(i386_state *cpustate, UINT32 offset, UINT64 data, UINT8 *valid_msr)
1418{
1419   switch(offset)
1420   {
1421   // Machine Check Exception (TODO)
1422   case 0x00:
1423      popmessage("WRMSR: Writing P5_MC_ADDR");
1424      *valid_msr = 1;
1425      break;
1426   case 0x01:
1427      popmessage("WRMSR: Writing P5_MC_TYPE");
1428      *valid_msr = 1;
1429      break;
1430   // Time Stamp Counter
1431   case 0x10:
1432      cpustate->tsc = data;
1433      popmessage("WRMSR: Writing to TSC");
1434      *valid_msr = 1;
1435      break;
1436   // Event Counters (TODO)
1437   case 0x11:  // CESR
1438      popmessage("WRMSR: Writing to CESR");
1439      *valid_msr = 1;
1440      break;
1441   case 0x12:  // CTR0
1442      cpustate->perfctr[0] = data;
1443      *valid_msr = 1;
1444      break;
1445   case 0x13:  // CTR1
1446      cpustate->perfctr[1] = data;
1447      *valid_msr = 1;
1448      break;
1449   default:
1450      logerror("WRMSR: invalid MSR write %08x (%08x%08x) at %08x\n",offset,(UINT32)(data >> 32),(UINT32)data,cpustate->pc-2);
1451      *valid_msr = 0;
1452      break;
1453   }
1454}
1455
1456// P6 (Pentium Pro, Pentium II, Pentium III) MSR handling
1457UINT64 p6_msr_read(i386_state *cpustate, UINT32 offset,UINT8 *valid_msr)
1458{
1459   switch(offset)
1460   {
1461   // Machine Check Exception (TODO)
1462   case 0x00:
1463      *valid_msr = 1;
1464      popmessage("RDMSR: Reading P5_MC_ADDR");
1465      return 0;
1466   case 0x01:
1467      *valid_msr = 1;
1468      popmessage("RDMSR: Reading P5_MC_TYPE");
1469      return 0;
1470   // Time Stamp Counter
1471   case 0x10:
1472      *valid_msr = 1;
1473      popmessage("RDMSR: Reading TSC");
1474      return cpustate->tsc;
1475   // Performance Counters (TODO)
1476   case 0xc1:  // PerfCtr0
1477      *valid_msr = 1;
1478      return cpustate->perfctr[0];
1479   case 0xc2:  // PerfCtr1
1480      *valid_msr = 1;
1481      return cpustate->perfctr[1];
1482   default:
1483      logerror("RDMSR: unimplemented register called %08x at %08x\n",offset,cpustate->pc-2);
1484      *valid_msr = 1;
1485      return 0;
1486   }
1487   return -1;
1488}
1489
1490void p6_msr_write(i386_state *cpustate, UINT32 offset, UINT64 data, UINT8 *valid_msr)
1491{
1492   switch(offset)
1493   {
1494   // Time Stamp Counter
1495   case 0x10:
1496      cpustate->tsc = data;
1497      popmessage("WRMSR: Writing to TSC");
1498      *valid_msr = 1;
1499      break;
1500   // Performance Counters (TODO)
1501   case 0xc1:  // PerfCtr0
1502      cpustate->perfctr[0] = data;
1503      *valid_msr = 1;
1504      break;
1505   case 0xc2:  // PerfCtr1
1506      cpustate->perfctr[1] = data;
1507      *valid_msr = 1;
1508      break;
1509   default:
1510      logerror("WRMSR: unimplemented register called %08x (%08x%08x) at %08x\n",offset,(UINT32)(data >> 32),(UINT32)data,cpustate->pc-2);
1511      *valid_msr = 1;
1512      break;
1513   }
1514}
1515
13791516INLINE UINT64 MSR_READ(i386_state *cpustate, UINT32 offset,UINT8 *valid_msr)
13801517{
13811518   UINT64 res;
1519   UINT8 cpu_type = (cpustate->cpu_version >> 8) & 0x0f;
13821520
13831521   *valid_msr = 0;
13841522
1385   switch(offset)
1523   switch(cpu_type)
13861524   {
1387      default:
1388         logerror("RDMSR: unimplemented register called %08x at %08x\n",offset,cpustate->pc-2);
1389         res = -1;
1390         *valid_msr = 1;
1391         break;
1525   case 5:  // Pentium
1526      res = pentium_msr_read(cpustate,offset,valid_msr);
1527      break;
1528   case 6:  // Pentium Pro, Pentium II, Pentium III
1529      res = p6_msr_read(cpustate,offset,valid_msr);
1530      break;
1531   default:
1532      res = 0;
1533      break;
13921534   }
13931535
13941536   return res;
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13971539INLINE void MSR_WRITE(i386_state *cpustate, UINT32 offset, UINT64 data, UINT8 *valid_msr)
13981540{
13991541   *valid_msr = 0;
1542   UINT8 cpu_type = (cpustate->cpu_version >> 8) & 0x0f;
14001543
1401   switch(offset)
1544   switch(cpu_type)
14021545   {
1403      default:
1404         logerror("WRMSR: unimplemented register called %08x (%08x%08x) at %08x\n",offset,(UINT32)(data >> 32),(UINT32)data,cpustate->pc-2);
1405         *valid_msr = 1;
1406         break;
1546   case 5:  // Pentium
1547      pentium_msr_write(cpustate,offset,data,valid_msr);
1548      break;
1549   case 6:  // Pentium Pro, Pentium II, Pentium III
1550      p6_msr_write(cpustate,offset,data,valid_msr);
1551      break;
14071552   }
14081553}
14091554

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