Previous 199869 Revisions Next

r26356 Friday 22nd November, 2013 at 13:06:44 UTC by Jürgen Buchmüller
Don't reset sub-devices on soft reset. Move iomem access to a2mem. Simplify execution loop and fix comments.
[/branches/alto2/src/emu/cpu/alto2]a2disp.c a2mem.c alto2cpu.c

branches/alto2/src/emu/cpu/alto2/a2mem.c
r26355r26356
598598   return data;
599599}
600600
601//! read i/o space RAM
602READ16_MEMBER ( alto2_cpu_device::ioram_r )
603{
604   offs_t dword_addr = offset / 2;
605   return static_cast<UINT16>(offset & 1 ? GET_ODD(m_mem.ram[dword_addr]) : GET_EVEN(m_mem.ram[dword_addr]));
606}
607
608//! write i/o space RAM
609WRITE16_MEMBER( alto2_cpu_device::ioram_w )
610{
611   offs_t dword_addr = offset / 2;
612   if (offset & 1)
613      PUT_ODD(m_mem.ram[dword_addr], data);
614   else
615      PUT_EVEN(m_mem.ram[dword_addr], data);
616}
617
601618/**
602619 * @brief load the memory address register with some value
603620 *
branches/alto2/src/emu/cpu/alto2/a2disp.c
r26355r26356
482482   m_dsp.a63 = a63;
483483   m_dsp.a66 = a66;
484484   m_dsp.state = next;
485   m_dsp_time += ALTO2_DISPLAY_BITTIME(32);
485486}
486487
487488/**
branches/alto2/src/emu/cpu/alto2/alto2cpu.c
r26355r26356
11201120   *reinterpret_cast<UINT32 *>(m_ucode_cram + offset * 4) = data;
11211121}
11221122
1123//! direct read access to the microcode CROM
1124#define   RD_CROM(addr) (addr < ALTO2_UCODE_RAM_BASE ? \
1125   *reinterpret_cast<UINT32 *>(m_ucode_crom + addr * 4) : \
1126   *reinterpret_cast<UINT32 *>(m_ucode_cram + (addr - ALTO2_UCODE_RAM_BASE) * 4))
1127
1128
11291123//! read constants PROM
11301124READ16_MEMBER ( alto2_cpu_device::const_r )
11311125{
11321126   return *reinterpret_cast<UINT16 *>(m_const_data + offset * 2);
11331127}
11341128
1135#define   PUT_EVEN(dword,word)         X_WRBITS(dword,32, 0,15,word)
1136#define   GET_EVEN(dword)               X_RDBITS(dword,32, 0,15)
1137#define   PUT_ODD(dword,word)            X_WRBITS(dword,32,16,31,word)
1138#define   GET_ODD(dword)               X_RDBITS(dword,32,16,31)
1129//! direct read access to the microcode CROM or CRAM
1130#define   RD_UCODE(addr) (addr < ALTO2_UCODE_RAM_BASE ? \
1131   *reinterpret_cast<UINT32 *>(m_ucode_crom + addr * 4) : \
1132   *reinterpret_cast<UINT32 *>(m_ucode_cram + (addr - ALTO2_UCODE_RAM_BASE) * 4))
11391133
1140//! read i/o space RAM
1141READ16_MEMBER ( alto2_cpu_device::ioram_r )
1142{
1143   offs_t dword_addr = offset / 2;
1144   return static_cast<UINT16>(offset & 1 ? GET_ODD(m_mem.ram[dword_addr]) : GET_EVEN(m_mem.ram[dword_addr]));
1145}
1146
1147//! write i/o space RAM
1148WRITE16_MEMBER( alto2_cpu_device::ioram_w )
1149{
1150   offs_t dword_addr = offset / 2;
1151   if (offset & 1)
1152      PUT_ODD(m_mem.ram[dword_addr], data);
1153   else
1154      PUT_EVEN(m_mem.ram[dword_addr], data);
1155}
1156
11571134//-------------------------------------------------
11581135//  device_reset - device-specific reset
11591136//-------------------------------------------------
r26355r26356
11611138void alto2_cpu_device::device_reset()
11621139{
11631140   soft_reset();
1164}
1141   // call all sub-devices' reset_...
1142   reset_memory();
1143   reset_disk();
1144   reset_disp();
1145   reset_kbd();
1146   reset_mouse();
1147   reset_hw();
11651148
1149   reset_emu();
1150   reset_ksec();
1151   reset_ether();
1152   reset_mrt();
1153   reset_dwt();
1154   reset_curt();
1155   reset_dht();
1156   reset_dvt();
1157   reset_part();
1158   reset_kwd();}
1159
11661160/**
11671161 * @brief callback is called by the drive timer whenever a new sector starts
11681162 *
r26355r26356
23302324   do {
23312325      int do_bs, flags;
23322326
2333      m_cycle++;
2334      /* nano seconds per cycle */
2335      m_pico_time[m_task] += ALTO2_UCYCLE;
2327      m_mpc = m_next;            // next instruction's micro program counter
2328      m_mir = RD_UCODE(m_mpc);   // fetch the micro code
23362329
2337      /* next instruction's mpc */
2338      m_mpc = m_next;
2339      m_mir = RD_CROM(m_mpc);
2340
2330      // extract the bit fields
23412331      m_d_rsel = m_rsel = X_RDBITS(m_mir, 32, DRSEL0, DRSEL4);
23422332      m_d_aluf = X_RDBITS(m_mir, 32, DALUF0, DALUF3);
23432333      m_d_bs = X_RDBITS(m_mir, 32, DBS0, DBS2);
r26355r26356
23452335      m_d_f2 = X_RDBITS(m_mir, 32, DF2_0, DF2_3);
23462336      m_d_loadt = X_BIT(m_mir, 32, DLOADT);
23472337      m_d_loadl = X_BIT(m_mir, 32, DLOADL);
2348      m_next = X_RDBITS(m_mir, 32, NEXT0, NEXT9) | m_next2;
2349      m_next2 = X_RDBITS(RD_CROM(m_next), 32, NEXT0, NEXT9) | (m_next2 & ~ALTO2_UCODE_PAGE_MASK);
2350      LOG((LOG_CPU,2,"%s-%04o: %011o r:%02o aluf:%02o bs:%02o f1:%02o f2:%02o t:%o l:%o next:%05o next2:%05o\n",
2351         task_name(m_task), m_mpc, m_mir, m_rsel, m_d_aluf, m_d_bs, m_d_f1, m_d_f2, m_d_loadt, m_d_loadl, m_next, m_next2));
2338
23522339      debugger_instruction_hook(this, m_mpc);
23532340
2341      m_cycle++;
2342      m_pico_time[m_task] += ALTO2_UCYCLE;   // add per task pico seconds per cycle
2343
23542344      /*
2355       * This bus source decoding is not performed if f1 = 7 or f2 = 7.
2356       * These functions use the BS field to provide part of the address
2357       * to the constant ROM
2345       * This bus source decoding is not performed if f1 == f1_const
2346       * or f2 == f2_const. These functions use the MIR BS field to
2347       * provide a part of the address to the constant ROM instead.
23582348       */
23592349      do_bs = !(m_d_f1 == f1_const || m_d_f2 == f2_const);
23602350
2361      if (m_d_f1 == f1_load_mar) {
2362         if (check_mem_load_mar_stall(m_rsel)) {
2363            LOG((LOG_CPU,3, "   MAR← stall\n"));
2364            m_next2 = m_next;
2365            m_next = m_mpc;
2366            continue;
2367         }
2368      } else if (m_d_f2 == f2_load_md) {
2369         if (check_mem_write_stall()) {
2370            LOG((LOG_CPU,3, "   MD← stall\n"));
2371            m_next2 = m_next;
2372            m_next = m_mpc;
2373            continue;
2374         }
2351      if (m_d_f1 == f1_load_mar && check_mem_load_mar_stall(m_rsel)) {
2352         LOG((LOG_CPU,3, "   MAR← stall\n"));
2353         continue;
23752354      }
2376      if (do_bs && m_d_bs == bs_read_md) {
2377         if (check_mem_read_stall()) {
2378            LOG((LOG_CPU,3, "   ←MD stall\n"));
2379            m_next2 = m_next;
2380            m_next = m_mpc;
2381            continue;
2382         }
2355      if (m_d_f2 == f2_load_md && check_mem_write_stall()) {
2356         LOG((LOG_CPU,3, "   MD← stall\n"));
2357         continue;
23832358      }
2359      if (do_bs && m_d_bs == bs_read_md && check_mem_read_stall()) {
2360         LOG((LOG_CPU,3, "   ←MD stall\n"));
2361         continue;
2362      }
2363      // now read the next instruction field from the MIR and modify it
2364      m_next = X_RDBITS(m_mir, 32, NEXT0, NEXT9) | m_next2;
2365      // prefetch the next instruction's next field as next2
2366      m_next2 = X_RDBITS(RD_UCODE(m_next), 32, NEXT0, NEXT9) | (m_next2 & ~ALTO2_UCODE_PAGE_MASK);
2367      LOG((LOG_CPU,2,"%s-%04o: %011o r:%02o aluf:%02o bs:%02o f1:%02o f2:%02o t:%o l:%o next:%05o next2:%05o\n",
2368         task_name(m_task), m_mpc, m_mir, m_rsel, m_d_aluf, m_d_bs, m_d_f1, m_d_f2, m_d_loadt, m_d_loadl, m_next, m_next2));
23842369
2370      // BUS is all ones at the start of each cycle
23852371      m_bus = 0177777;
23862372
23872373      if (m_rdram_flag)
23882374         rdram();
23892375
2390      /*
2391       * The constant memory is gated to the bus by F1 == f1_const, F2 == f2_const, or BS >= 4
2392       */
2376      // The constant memory is gated to the bus by F1 == f1_const, F2 == f2_const, or BS >= 4
23932377      if (!do_bs || m_d_bs >= bs_task_4) {
2394         int addr = 8 * m_rsel + m_d_bs;
2395         UINT16 data = m_const_data[2*addr+0] | (m_const_data[2*addr+1] << 8);
2378         UINT32 addr = 8 * m_rsel + m_d_bs;
2379         // FIXME: is the format of m_const_data endian safe?
2380         UINT16 data = m_const_data[2*addr] | (m_const_data[2*addr+1] << 8);
23962381         m_bus &= data;
23972382         LOG((LOG_CPU,2,"   %#o; BUS &= %#o CONST[%03o]\n", m_bus, data, addr));
23982383      }
23992384
24002385      /*
2401       * early f2 has to be done before early bs, because the
2402       * emulator f2 acsource or acdest may change m_rsel
2386       * early F2 function has to be called before early BS,
2387       * because the emulator task F2 acsource or acdest may
2388       * change the m_rsel
24032389       */
24042390      ((*this).*m_f2[0][m_task][m_d_f2])();
24052391
2406      /*
2407       * early bs can be done now
2408       */
2392      // early BS function can be done now
24092393      if (do_bs)
24102394         ((*this).*m_bs[0][m_task][m_d_bs])();
24112395
2412      /*
2413       * early f1
2414       */
2396      // early F1 function
24152397      ((*this).*m_f1[0][m_task][m_d_f1])();
24162398
24172399#if   USE_ALU_74181
2418      // The ALU a10 PROM address lines are
2419      // A4:SKIP      A3:ALUF0     A2:ALUF1     A1:ALUF2     A0:ALUF3
2420      // The PROM output lines are
2421      // B0: unused   B1: TSELECT  B2: ALUCI'   B3: ALUM'
2422      // B4: ALUS0'   B5: ALUS1'   B6: ALUS2'   B7: ALUS3'
2423      // B1 and B3-B7 are inverted on loading the PROM
2400      /**
2401       * The ALU a10 PROM address lines are
2402       * A4:SKIP      A3:ALUF0     A2:ALUF1     A1:ALUF2     A0:ALUF3
2403       * The PROM output lines are
2404       * B0: unused   B1: TSELECT  B2: ALUCI'   B3: ALUM'
2405       * B4: ALUS0'   B5: ALUS1'   B6: ALUS2'   B7: ALUS3'
2406       *
2407       * B1 and B3-B7 are inverted on loading the PROM
2408       */
24242409      UINT8 a10 = m_alu_a10[(m_emu.skip << 4) | m_d_aluf];
24252410      UINT32 alu = alu_74181(m_bus, m_t, a10);
24262411      m_aluc0 = (alu >> 16) & 1;
r26355r26356
26412626      m_alu = static_cast<UINT16>(alu);
26422627#endif
26432628
2644      /* WRTRAM now, before L is changed */
2629      // WRTRAM must happen now before L is changed
26452630      if (m_wrtram_flag)
26462631         wrtram();
26472632
26482633      // shifter passes L, if F1 is not one of L LSH 1, L RSH 1 or L LCY 8
26492634      m_shifter = m_l;
26502635
2651      /* late F1 is done now */
2636      // late F1 function call now
26522637      ((*this).*m_f1[1][m_task][m_d_f1])();
26532638
2654      /* late F2 is done now */
2639      // late F2 function call now
26552640      ((*this).*m_f2[1][m_task][m_d_f2])();
26562641
2657      /* late BS is done now, if no constant was put on the bus */
2642      // late BS function call now, if no constant was put on the bus
26582643      if (do_bs)
26592644         ((*this).*m_bs[1][m_task][m_d_bs])();
26602645
r26355r26356
26702655         }
26712656      }
26722657
2673      // update L register and LALUC0
2658      // update L register and LALUC0 if LOADL is set
26742659      if (m_d_loadl) {
26752660         m_l = m_alu;         // load L from ALU
26762661         if (flags & ALUM) {
2677            m_laluc0 = 0;      // logic operation - latch 0
2662            m_laluc0 = 0;      // logic operation - put 0 into latched carry
26782663            LOG((LOG_CPU,2, "   L← ALU (%#o); LALUC0← %o\n", m_alu, 0));
26792664         } else {
2680            m_laluc0 = m_aluc0;   // arithmethic operation - latch carry
2665            m_laluc0 = m_aluc0;   // arithmethic operation - put ALU carry into latched carry
26812666            LOG((LOG_CPU,2, "   L← ALU (%#o); LALUC0← ALUC0 (%o)\n", m_alu, m_aluc0));
26822667         }
26832668         // update M (MYL) register, if a RAM related task is active
r26355r26356
26902675
26912676      // handle task switching
26922677      if (m_task != m_next2_task) {
2693         /* switch now? */
2678         // switch now?
26942679         if (m_task == m_next_task) {
2695            /* one more microinstruction */
2680            // one more microinstruction
26962681            m_next_task = m_next2_task;
26972682         } else {
2698            /* save this task's mpc and next2 */
2683            // save this task's next and next2
26992684            m_task_mpc[m_task] = m_next;
27002685            m_task_next2[m_task] = m_next2;
27012686            m_task = m_next_task;
r26355r26356
27082693         }
27092694      }
27102695
2711      /*
2696      /**
27122697       * Subtract the microcycle time from the display time accu.
27132698       * If it underflows, call the display state machine and add
2714       * the time for 24 pixel clocks to the accu.
2715       * This is very close to every seventh CPU cycle.
2699       * the time for 32(!) pixel clocks to the accu.
2700       * This is very close to every seventh CPU cycle (really?)
27162701       */
2717      m_dsp_time -= ALTO2_UCYCLE;
2718      if (m_dsp_time < 0) {
2719         display_state_machine();
2720         m_dsp_time += ALTO2_DISPLAY_BITTIME(24);
2702      if (m_dsp_time >= 0) {
2703         m_dsp_time -= ALTO2_UCYCLE;
2704         if (m_dsp_time < 0)
2705            display_state_machine();
27212706      }
27222707      if (m_unload_time >= 0) {
2723         /*
2708         /**
27242709          * Subtract the microcycle time from the unload time accu.
27252710          * If it underflows, call the unload word function which adds
27262711          * the time for 16 or 32 pixel clocks to the accu, or ends
r26355r26356
28532838#if   (USE_BITCLK_TIMER == 0)
28542839   m_bitclk_time = 0;            // reset the bitclk timing accu
28552840#endif
2856
2857   // call all sub-devices' reset_...
2858   reset_memory();
2859   reset_disk();
2860   reset_disp();
2861   reset_kbd();
2862   reset_mouse();
2863   reset_hw();
2864
2865   reset_emu();
2866   reset_ksec();
2867   reset_ether();
2868   reset_mrt();
2869   reset_dwt();
2870   reset_curt();
2871   reset_dht();
2872   reset_dvt();
2873   reset_part();
2874   reset_kwd();
28752841}

Previous 199869 Revisions Next

© 1997-2024 The MAME Team