branches/alto2/src/emu/cpu/alto2/a2disp.c
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| 248 | 248 | *pix++ = (word >> 0) & 1; |
| 249 | 249 | } |
| 250 | 250 | |
| 251 | | #define HLC1 ((m_dsp.hlc >> 0) & 1) //!< horizontal line counter bit 0 |
| 251 | #define HLC1 ((m_dsp.hlc >> 0) & 1) //!< horizontal line counter bit 0 (mid of the scanline) |
| 252 | 252 | #define HLC2 ((m_dsp.hlc >> 1) & 1) //!< horizontal line counter bit 1 |
| 253 | 253 | #define HLC4 ((m_dsp.hlc >> 2) & 1) //!< horizontal line counter bit 2 |
| 254 | 254 | #define HLC8 ((m_dsp.hlc >> 3) & 1) //!< horizontal line counter bit 3 |
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| 258 | 258 | #define HLC128 ((m_dsp.hlc >> 7) & 1) //!< horizontal line counter bit 7 |
| 259 | 259 | #define HLC256 ((m_dsp.hlc >> 8) & 1) //!< horizontal line counter bit 8 |
| 260 | 260 | #define HLC512 ((m_dsp.hlc >> 9) & 1) //!< horizontal line counter bit 9 |
| 261 | | #define HLC1024 ((m_dsp.hlc >> 10) & 1) //!< horizontal line counter bit 10 |
| 261 | #define HLC1024 ((m_dsp.hlc >> 10) & 1) //!< horizontal line counter bit 10 (odd/even field) |
| 262 | 262 | |
| 263 | 263 | #define GET_SETMODE_SPEEDY(mode) X_RDBITS(mode,16,0,0) //!< get the pixel clock speed from a SETMODE<- bus value |
| 264 | 264 | #define GET_SETMODE_INVERSE(mode) X_RDBITS(mode,16,1,1) //!< get the inverse video flag from a SETMODE<- bus value |
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| 351 | 351 | |
| 352 | 352 | UINT8 a63 = m_disp_a63[m_dsp.state]; |
| 353 | 353 | if (A63_HLCGATE(a63)) { |
| 354 | | /* reset or count horizontal line counters */ |
| 355 | | if (m_dsp.hlc == ALTO2_DISPLAY_HLC_END) |
| 354 | // reset or count horizontal line counters |
| 355 | m_dsp.hlc += 1; |
| 356 | if (m_dsp.hlc == ALTO2_DISPLAY_HLC_END + 1) |
| 356 | 357 | m_dsp.hlc = ALTO2_DISPLAY_HLC_START; |
| 357 | | else |
| 358 | | m_dsp.hlc++; |
| 359 | 358 | /* start the refresh task _twice_ on each scanline */ |
| 360 | 359 | m_task_wakeup |= 1 << task_mrt; |
| 361 | 360 | if (m_ewfct) { |
branches/alto2/src/emu/cpu/alto2/a2mem.c
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| 619 | 619 | if (addr < m_mem.size) { |
| 620 | 620 | LOG((LOG_MEM,2, " MAR←; mar = %#o\n", addr)); |
| 621 | 621 | m_mem.access = ALTO2_MEM_RAM; |
| 622 | | /* fetch memory double-word to read/write latches */ |
| 622 | // fetch the memory double-word to the read/write latches |
| 623 | 623 | m_mem.rmdd = m_mem.wmdd = m_mem.ram[m_mem.mar/2]; |
| 624 | // keep track of the current CPU cycle |
| 624 | 625 | m_mem.cycle = cycle(); |
| 625 | 626 | } else { |
| 626 | 627 | m_mem.access = ALTO2_MEM_NIRVANA; |
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| 672 | 673 | #endif |
| 673 | 674 | |
| 674 | 675 | if (m_mem.access & ALTO2_MEM_ODD) { |
| 676 | // after reading the odd word, reset the access flag |
| 675 | 677 | m_mem.access = ALTO2_MEM_NONE; |
| 676 | 678 | } else { |
| 679 | // after reading the even word word, toggle access flag (and address) to the odd word |
| 677 | 680 | m_mem.mar ^= ALTO2_MEM_ODD; |
| 678 | 681 | m_mem.access ^= ALTO2_MEM_ODD; |
| 682 | // extend the read succeeds window by one cycle |
| 679 | 683 | m_mem.cycle++; |
| 680 | 684 | } |
| 681 | 685 | return m_mem.md; |
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| 730 | 734 | #if ALTO2_DEBUG |
| 731 | 735 | watch_write(m_mem.mar, m_mem.md); |
| 732 | 736 | #endif |
| 733 | | /* don't reset mem.access to permit double word exchange */ |
| 737 | // Toggle the odd/even word access flag |
| 738 | // NB: don't reset mem.access to permit double word exchange |
| 734 | 739 | m_mem.mar ^= ALTO2_MEM_ODD; |
| 735 | 740 | m_mem.access ^= ALTO2_MEM_ODD; |
| 741 | // extend the write succeeds window by one cycle |
| 736 | 742 | m_mem.cycle++; |
| 737 | 743 | } |
| 738 | 744 | |
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| 744 | 750 | */ |
| 745 | 751 | UINT16 alto2_cpu_device::debug_read_mem(UINT32 addr) |
| 746 | 752 | { |
| 753 | space(AS_2).set_debugger_access(true); |
| 747 | 754 | int base_addr = addr & 0177777; |
| 748 | 755 | int data = 0177777; |
| 749 | 756 | if (base_addr >= ALTO2_IO_PAGE_BASE && addr < ALTO2_RAM_SIZE) { |
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| 751 | 758 | } else { |
| 752 | 759 | data = (addr & ALTO2_MEM_ODD) ? GET_ODD(m_mem.ram[addr/2]) : GET_EVEN(m_mem.ram[addr/2]); |
| 753 | 760 | } |
| 761 | space(AS_2).set_debugger_access(false); |
| 754 | 762 | return data; |
| 755 | 763 | } |
| 756 | 764 | |
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| 762 | 770 | */ |
| 763 | 771 | void alto2_cpu_device::debug_write_mem(UINT32 addr, UINT16 data) |
| 764 | 772 | { |
| 773 | space(AS_2).set_debugger_access(true); |
| 765 | 774 | int base_addr = addr & 0177777; |
| 766 | 775 | if (base_addr >= ALTO2_IO_PAGE_BASE && addr < ALTO2_RAM_SIZE) { |
| 767 | 776 | m_iomem->write_word(m_iomem->address_to_byte(base_addr), data); |
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| 770 | 779 | } else { |
| 771 | 780 | PUT_EVEN(m_mem.ram[addr/2], data); |
| 772 | 781 | } |
| 782 | space(AS_2).set_debugger_access(false); |
| 773 | 783 | } |
| 774 | 784 | |
| 775 | 785 | /** |