branches/alto2/src/emu/cpu/alto2/a2hw.c
r26352 | r26353 | |
8 | 8 | * |
9 | 9 | *****************************************************************************/ |
10 | 10 | #include "alto2cpu.h" |
| 11 | #include "a2roms.h" |
11 | 12 | |
12 | 13 | /** |
13 | 14 | * @brief read printer paper ready bit |
r26352 | r26353 | |
315 | 316 | } |
316 | 317 | |
317 | 318 | /** |
| 319 | * <PRE> |
| 320 | * TODO: use madr.a65 and madr.a64 to determine the actual I/O address ranges |
| 321 | * |
| 322 | * madr.a65 |
| 323 | * address line connected to |
| 324 | * ------------------------------- |
| 325 | * A0 MAR[11] |
| 326 | * A1 KEYSEL |
| 327 | * A2 MAR[7-10] == 0 |
| 328 | * A3 MAR[12] |
| 329 | * A4 MAR[13] |
| 330 | * A5 MAR[14] |
| 331 | * A6 MAR[15] |
| 332 | * A7 IOREF (MAR[0-6] == 1) |
| 333 | * |
| 334 | * output data connected to |
| 335 | * ------------------------------- |
| 336 | * D0 IOSEL0 |
| 337 | * D1 IOSEL1 |
| 338 | * D2 IOSEL2 |
| 339 | * D3 INTIO |
| 340 | * |
| 341 | * madr.a64 |
| 342 | * address line connected to |
| 343 | * ------------------------------- |
| 344 | * A0 STORE |
| 345 | * A1 MAR[11] |
| 346 | * A2 MAR[7-10] == 0 |
| 347 | * A3 MAR[12] |
| 348 | * A4 MAR[13] |
| 349 | * A5 MAR[14] |
| 350 | * A6 MAR[15] |
| 351 | * A7 IOREF (MAR[0-6] == 1) |
| 352 | * |
| 353 | * output data connected to |
| 354 | * ------------------------------- |
| 355 | * D0 & MISYSCLK -> SELP |
| 356 | * D1 ^ INTIO -> INTIOX |
| 357 | * " ^ 1 -> NERRSEL |
| 358 | * " & WRTCLK -> NRSTE |
| 359 | * D2 XREG' |
| 360 | * D3 & MISYSCLK -> LOADERC |
| 361 | * </PRE> |
| 362 | */ |
| 363 | |
| 364 | static const prom_load_t pl_madr_a64 = |
| 365 | { |
| 366 | "madr.a64", |
| 367 | 0, |
| 368 | "a66b0eda", |
| 369 | "4d9088f592caa3299e90966b17765be74e523144", |
| 370 | /* size */ 0400, |
| 371 | /* amap */ AMAP_DEFAULT, |
| 372 | /* axor */ 0, |
| 373 | /* dxor */ 017, // invert D0-D3 |
| 374 | /* width */ 4, |
| 375 | /* shift */ 0, |
| 376 | /* dmap */ DMAP_DEFAULT, |
| 377 | /* dand */ ZERO, |
| 378 | /* type */ sizeof(UINT8) |
| 379 | }; |
| 380 | |
| 381 | static const prom_load_t pl_madr_a65 = |
| 382 | { |
| 383 | "madr.a65", |
| 384 | 0, |
| 385 | "ba37febd", |
| 386 | "82e9db1cb65f451755295f0d179e6f8fe3349d4d", |
| 387 | /* size */ 0400, |
| 388 | /* amap */ AMAP_DEFAULT, |
| 389 | /* axor */ 0, |
| 390 | /* dxor */ 017, // invert D0-D3 |
| 391 | /* width */ 4, |
| 392 | /* shift */ 0, |
| 393 | /* dmap */ DMAP_DEFAULT, |
| 394 | /* dand */ ZERO, |
| 395 | /* type */ sizeof(UINT8) |
| 396 | }; |
| 397 | |
| 398 | /** |
318 | 399 | * @brief clear all keys and install the mmio handler for KBDAD to KBDAD+3 |
319 | 400 | */ |
320 | 401 | void alto2_cpu_device::init_hw() |
321 | 402 | { |
322 | 403 | memset(&m_hw, 0, sizeof(m_hw)); |
| 404 | m_madr_a64 = prom_load(machine(), &pl_madr_a64, memregion("madr_a64")->base()); |
| 405 | m_madr_a65 = prom_load(machine(), &pl_madr_a65, memregion("madr_a65")->base()); |
| 406 | } |
323 | 407 | |
324 | | // open inputs on UTILIN |
325 | | m_hw.utilin = 0177777; |
| 408 | void alto2_cpu_device::exit_hw() |
| 409 | { |
| 410 | // nothing to do yet |
| 411 | } |
326 | 412 | |
| 413 | void alto2_cpu_device::reset_hw() |
| 414 | { |
| 415 | m_hw.eia = 0; |
| 416 | m_hw.utilout = 0; |
327 | 417 | // open inputs on the XBUS (?) |
328 | 418 | m_hw.xbus[0] = 0177777; |
329 | 419 | m_hw.xbus[1] = 0177777; |
330 | 420 | m_hw.xbus[2] = 0177777; |
331 | 421 | m_hw.xbus[3] = 0177777; |
| 422 | // open inputs on UTILIN |
| 423 | m_hw.utilin = 0177777; |
332 | 424 | } |
333 | | |
334 | | void alto2_cpu_device::exit_hw() |
335 | | { |
336 | | // nothing to do yet |
337 | | } |
338 | | |
branches/alto2/src/emu/cpu/alto2/a2mem.c
r26352 | r26353 | |
782 | 782 | */ |
783 | 783 | void alto2_cpu_device::init_memory() |
784 | 784 | { |
785 | | memset(&m_mem, 0, sizeof(m_mem)); |
| 785 | memset(&m_mem, 0, sizeof(m_mem)); |
| 786 | } |
786 | 787 | |
787 | | #if 0 // can't read ioport() at this time |
788 | | // allocate 64KB or 128KB of main memory |
789 | | m_mem.size = ioport("CONFIG")->read() & 1 ? ALTO2_RAM_SIZE : 2 * ALTO2_RAM_SIZE; |
790 | | #else |
791 | | m_mem.size = 2 * ALTO2_RAM_SIZE; |
792 | | #endif |
793 | | printf("main memory %u KB\n", m_mem.size / 1024); |
794 | | m_mem.ram = auto_alloc_array_clear(machine(), UINT32, sizeof(UINT16) * m_mem.size); |
795 | | m_mem.hpb = auto_alloc_array_clear(machine(), UINT8, sizeof(UINT16) * m_mem.size); |
796 | | |
797 | | /** |
798 | | * <PRE> |
799 | | * TODO: use madr.a65 and madr.a64 to determine the actual I/O address ranges |
800 | | * |
801 | | * madr.a65 |
802 | | * address line connected to |
803 | | * ------------------------------- |
804 | | * A0 MAR[11] |
805 | | * A1 KEYSEL |
806 | | * A2 MAR[7-10] == 0 |
807 | | * A3 MAR[12] |
808 | | * A4 MAR[13] |
809 | | * A5 MAR[14] |
810 | | * A6 MAR[15] |
811 | | * A7 IOREF (MAR[0-6] == 1) |
812 | | * |
813 | | * output data connected to |
814 | | * ------------------------------- |
815 | | * D0 IOSEL0 |
816 | | * D1 IOSEL1 |
817 | | * D2 IOSEL2 |
818 | | * D3 INTIO |
819 | | * |
820 | | * madr.a64 |
821 | | * address line connected to |
822 | | * ------------------------------- |
823 | | * A0 STORE |
824 | | * A1 MAR[11] |
825 | | * A2 MAR[7-10] == 0 |
826 | | * A3 MAR[12] |
827 | | * A4 MAR[13] |
828 | | * A5 MAR[14] |
829 | | * A6 MAR[15] |
830 | | * A7 IOREF (MAR[0-6] == 1) |
831 | | * |
832 | | * output data connected to |
833 | | * ------------------------------- |
834 | | * D0 & MISYSCLK -> SELP |
835 | | * D1 ^ INTIO -> INTIOX |
836 | | * " ^ 1 -> NERRSEL |
837 | | * " & WRTCLK -> NRSTE |
838 | | * D2 XREG' |
839 | | * D3 & MISYSCLK -> LOADERC |
840 | | * </PRE> |
841 | | */ |
842 | | |
843 | | #if ALTO2_HAMMING_CHECK |
844 | | // Initialize the hamming codes and parity bit |
845 | | for (UINT32 addr = 0; addr < ALTO2_IO_PAGE_BASE; addr++) { |
846 | | hamming_code(1, addr, 0); |
847 | | hamming_code(1, 0200000 + addr, 0); |
| 788 | void alto2_cpu_device::exit_memory() |
| 789 | { |
| 790 | if (m_mem.ram) { |
| 791 | auto_free(machine(), m_mem.ram); |
| 792 | m_mem.ram = 0; |
848 | 793 | } |
849 | | #endif |
| 794 | if (m_mem.hpb) { |
| 795 | auto_free(machine(), m_mem.hpb); |
| 796 | m_mem.hpb = 0; |
| 797 | } |
850 | 798 | } |
851 | 799 | |
852 | | void alto2_cpu_device::exit_memory() |
| 800 | void alto2_cpu_device::reset_memory() |
853 | 801 | { |
854 | 802 | if (m_mem.ram) { |
855 | 803 | auto_free(machine(), m_mem.ram); |
r26352 | r26353 | |
859 | 807 | auto_free(machine(), m_mem.hpb); |
860 | 808 | m_mem.hpb = 0; |
861 | 809 | } |
| 810 | // allocate 64K or 128K words of main memory |
| 811 | ioport_port* config = ioport("CONFIG"); |
| 812 | if (config) |
| 813 | m_mem.size = config->read() & 1 ? ALTO2_RAM_SIZE : 2 * ALTO2_RAM_SIZE; |
| 814 | else |
| 815 | m_mem.size = ALTO2_RAM_SIZE; |
| 816 | logerror("Main memory %u KiB\n", static_cast<UINT32>(sizeof(UINT16) * m_mem.size / 1024)); |
| 817 | |
| 818 | m_mem.ram = auto_alloc_array_clear(machine(), UINT32, sizeof(UINT16) * m_mem.size); |
| 819 | m_mem.hpb = auto_alloc_array_clear(machine(), UINT8, sizeof(UINT16) * m_mem.size); |
| 820 | |
| 821 | #if ALTO2_HAMMING_CHECK |
| 822 | // Initialize the hamming codes and parity bit |
| 823 | for (UINT32 addr = 0; addr < ALTO2_IO_PAGE_BASE; addr++) { |
| 824 | hamming_code(1, addr, 0); |
| 825 | hamming_code(1, 0200000 + addr, 0); |
| 826 | } |
| 827 | #endif |
| 828 | m_mem.mar = 0; |
| 829 | m_mem.rmdd = 0; |
| 830 | m_mem.wmdd = 0; |
| 831 | m_mem.md = 0; |
| 832 | m_mem.cycle = 0; |
| 833 | m_mem.access = 0; |
| 834 | m_mem.error = 0; |
| 835 | m_mem.mear = 0; |
| 836 | m_mem.mesr = 0; |
| 837 | m_mem.mecr = 0; |
862 | 838 | } |
branches/alto2/src/emu/cpu/alto2/a2mem.h
r26352 | r26353 | |
64 | 64 | * @return false, if memory address can be loaded |
65 | 65 | */ |
66 | 66 | inline bool check_mem_load_mar_stall(UINT8 rsel) { |
67 | | if (ALTO2_MEM_NONE == m_mem.access) |
68 | | return false; |
69 | | return cycle() < m_mem.cycle+5; |
| 67 | if (ALTO2_MEM_NONE == m_mem.access) |
| 68 | return false; |
| 69 | return cycle() < m_mem.cycle+5; |
70 | 70 | } |
71 | 71 | |
72 | 72 | /** |
r26352 | r26353 | |
82 | 82 | * @return false, if memory can be read without wait cycle |
83 | 83 | */ |
84 | 84 | inline bool check_mem_read_stall() { |
85 | | if (ALTO2_MEM_NONE == m_mem.access) |
86 | | return false; |
87 | | return cycle() < m_mem.cycle+4; |
| 85 | if (ALTO2_MEM_NONE == m_mem.access) |
| 86 | return false; |
| 87 | return cycle() < m_mem.cycle+4; |
88 | 88 | } |
89 | 89 | |
90 | 90 | /** |
r26352 | r26353 | |
99 | 99 | * @return false, if memory can be written without wait cycle |
100 | 100 | */ |
101 | 101 | inline bool check_mem_write_stall() { |
102 | | if (ALTO2_MEM_NONE == m_mem.access) |
103 | | return false; |
104 | | return cycle() < m_mem.cycle+2; |
| 102 | if (ALTO2_MEM_NONE == m_mem.access) |
| 103 | return false; |
| 104 | return cycle() < m_mem.cycle+2; |
105 | 105 | } |
106 | 106 | |
107 | 107 | |
r26352 | r26353 | |
136 | 136 | |
137 | 137 | void init_memory(); //!< initialize the memory system |
138 | 138 | void exit_memory(); //!< deinitialize the memory system |
| 139 | void reset_memory(); //!< reset the memory system |
139 | 140 | #endif // _A2MEM_H_ |
140 | 141 | #endif // ALTO2_DEFINE_CONSTANTS |
branches/alto2/src/emu/cpu/alto2/a2ram.h
r26352 | r26353 | |
50 | 50 | |
51 | 51 | //!< F1 functions for RAM related tasks |
52 | 52 | enum { |
53 | | f1_ram_swmode = f1_task_10, //!< f1 10: switch mode to CROM/CRAM in same page |
54 | | f1_ram_wrtram = f1_task_11, //!< f1 11: start WRTRAM cycle |
55 | | f1_ram_rdram = f1_task_12, //!< f1 12: start RDRAM cycle |
| 53 | f1_ram_swmode = f1_task_10, //!< f1 10: switch mode to CROM/CRAM in same page |
| 54 | f1_ram_wrtram = f1_task_11, //!< f1 11: start WRTRAM cycle |
| 55 | f1_ram_rdram = f1_task_12, //!< f1 12: start RDRAM cycle |
56 | 56 | #if (ALTO2_UCODE_RAM_PAGES == 3) |
57 | | f1_ram_load_rmr = f1_task_13, //!< f1 13: load the reset mode register |
| 57 | f1_ram_load_rmr = f1_task_13, //!< f1 13: load the reset mode register |
58 | 58 | #else // ALTO2_UCODE_RAM_PAGES != 3 |
59 | | f1_ram_load_srb = f1_task_13 //!< f1 14: load the S register bank from BUS[12-14] |
| 59 | f1_ram_load_srb = f1_task_13 //!< f1 14: load the S register bank from BUS[12-14] |
60 | 60 | #endif |
61 | 61 | }; |
62 | 62 | |
r26352 | r26353 | |
74 | 74 | void f1_late_load_srb(); //!< F1 func: load the S register bank from BUS[12-14] |
75 | 75 | #endif |
76 | 76 | void init_ram(int task); //!< called by RAM related tasks |
77 | | void exit_ram(); |
| 77 | void exit_ram(); //!< deinitialize the RAM related tasks |
| 78 | void reset_ram(); //!< reset the RAM related tasks |
78 | 79 | #endif // A2RAM_H |
79 | 80 | #endif // ALTO2_DEFINE_CONSTANTS |
branches/alto2/src/emu/cpu/alto2/a2dwt.h
r26352 | r26353 | |
15 | 15 | |
16 | 16 | //! F2 functions for display word task |
17 | 17 | enum { |
18 | | f2_dwt_load_ddr = f2_task_10 //!< f2 10: load display data register |
| 18 | f2_dwt_load_ddr = f2_task_10 //!< f2 10: load display data register |
19 | 19 | }; |
20 | 20 | |
21 | 21 | void f1_early_dwt_block(); //!< F1 func: block the display word task |
22 | 22 | void f2_late_dwt_load_ddr(); //!< F2 func: load the display data register |
23 | | void init_dwt(int task = task_dwt); //!< initialize display word task |
24 | | void exit_dwt(); //!< deinitialize display word task |
| 23 | void init_dwt(int task = task_dwt); //!< initialize the display word task |
| 24 | void exit_dwt(); //!< deinitialize the display word task |
| 25 | void reset_dwt(); //!< reset the display word task |
25 | 26 | #endif // _A2DWT_H_ |
26 | 27 | #endif // ALTO2_DEFINE_CONSTANTS |
branches/alto2/src/emu/cpu/alto2/a2ether.c
r26352 | r26353 | |
808 | 808 | m_ether_a42 = prom_load(machine(), &pl_enet_a42, memregion("ether_a42")->base()); |
809 | 809 | m_ether_a49 = prom_load(machine(), &pl_enet_a49, memregion("ether_a49")->base()); |
810 | 810 | |
811 | | // FIXME: read configuration for m_eth.duckbreath enable |
812 | | m_eth.duckbreath = m_duckbreath_sec; |
813 | | |
814 | 811 | set_bs(task, bs_ether_eidfct, &alto2_cpu_device::bs_early_eidfct, 0); |
815 | 812 | |
816 | 813 | set_f1(task, f1_block, &alto2_cpu_device::f1_early_eth_block, 0); |
r26352 | r26353 | |
846 | 843 | // nothing to do yet |
847 | 844 | } |
848 | 845 | |
| 846 | //! delay between two duckbreaths in seconds |
| 847 | static const int duckbreath_sec[8] = { |
| 848 | 0, 5, 10, 15, 30, 60, 90, 120 |
| 849 | }; |
| 850 | void alto2_cpu_device::reset_ether() |
| 851 | { |
| 852 | memset(m_eth.fifo, 0, sizeof(m_eth.fifo)); |
| 853 | m_eth.fifo_rd = 0; |
| 854 | m_eth.fifo_wr = 0; |
| 855 | m_eth.status = 0; |
| 856 | m_eth.rx_crc = 0; |
| 857 | m_eth.tx_crc = 0; |
| 858 | m_eth.rx_count = 0; |
| 859 | m_eth.tx_count = 0; |
| 860 | m_eth.rx_timer->reset(); |
| 861 | m_eth.tx_timer->reset(); |
| 862 | ioport_port* config = ioport("CONFIG"); |
| 863 | if (config) |
| 864 | m_eth.duckbreath = duckbreath_sec[(config->read() >> 4) & 7]; |
| 865 | else |
| 866 | m_eth.duckbreath = 0; |
| 867 | } |
branches/alto2/src/emu/cpu/alto2/a2disk.c
r26352 | r26353 | |
1690 | 1690 | } |
1691 | 1691 | |
1692 | 1692 | /** |
1693 | | * @brief exit disk controller - free all timers |
| 1693 | * @brief exit disk controller - free all timers? |
1694 | 1694 | */ |
1695 | 1695 | void alto2_cpu_device::exit_disk() |
1696 | 1696 | { |
1697 | 1697 | // nothing to do yet |
1698 | 1698 | } |
1699 | 1699 | |
| 1700 | void alto2_cpu_device::reset_disk() |
| 1701 | { |
| 1702 | m_dsk.drive = 0; |
| 1703 | m_dsk.kaddr = 0; |
| 1704 | m_dsk.kadr = 0; |
| 1705 | m_dsk.kstat = 0; |
| 1706 | m_dsk.kcom = 0; |
| 1707 | m_dsk.krecno = 0; |
| 1708 | m_dsk.egate = 1; |
| 1709 | m_dsk.wrgate = 1; |
| 1710 | m_dsk.rdgate = 1; |
| 1711 | m_dsk.shiftin = 0; |
| 1712 | m_dsk.shiftout = 0; |
| 1713 | m_dsk.datain = 0; |
| 1714 | m_dsk.dataout = 0; |
| 1715 | m_dsk.krwc = 0; |
| 1716 | m_dsk.kfer = 0; |
| 1717 | m_dsk.wdtskena = 1; |
| 1718 | m_dsk.wddone = 0; |
| 1719 | m_dsk.wdinit0 = 0; |
| 1720 | m_dsk.wdinit = 0; |
| 1721 | m_dsk.strobe = 0; |
| 1722 | m_dsk.strobon_timer->reset(); |
| 1723 | m_dsk.bitclk = 0; |
| 1724 | #if USE_BITCLK_TIMER |
| 1725 | m_dsk.bitclk_timer->reset(); |
| 1726 | #else |
| 1727 | m_dsk.bitclk_time[0] = static_cast<int>(attotime::from_nsec(300).as_attoseconds() / 1000000); |
| 1728 | m_dsk.bitclk_time[1] = static_cast<int>(attotime::from_nsec(300).as_attoseconds() / 1000000); |
| 1729 | #endif |
| 1730 | m_dsk.datin = 0; |
| 1731 | m_dsk.bitcount = 0; |
| 1732 | m_dsk.carry = 0; |
| 1733 | m_dsk.seclate = 0; |
| 1734 | m_dsk.seclate_timer->reset(); |
| 1735 | m_dsk.seekok = 0; |
| 1736 | m_dsk.ok_to_run = 0; |
| 1737 | m_dsk.ok_to_run_timer->adjust(attotime::from_nsec(35 * ALTO2_UCYCLE / 1000), 1); |
| 1738 | m_dsk.ready_mf31a = 0; |
| 1739 | m_dsk.ready_timer->reset(); |
| 1740 | m_dsk.seclate_mf31b = 0; |
| 1741 | m_dsk.ff_21a = JKFF_0; |
| 1742 | m_dsk.ff_21a_old = JKFF_0; |
| 1743 | m_dsk.ff_21b = JKFF_0; |
| 1744 | m_dsk.ff_22a = JKFF_0; |
| 1745 | m_dsk.ff_22b = JKFF_0; |
| 1746 | m_dsk.ff_43b = JKFF_0; |
| 1747 | m_dsk.ff_53a = JKFF_0; |
| 1748 | m_dsk.ff_43a = JKFF_0; |
| 1749 | m_dsk.ff_53b = JKFF_0; |
| 1750 | m_dsk.ff_44a = JKFF_0; |
| 1751 | m_dsk.ff_44b = JKFF_0; |
| 1752 | m_dsk.ff_45a = JKFF_0; |
| 1753 | m_dsk.ff_45b = JKFF_0; |
| 1754 | |
| 1755 | } |
branches/alto2/src/emu/cpu/alto2/a2disp.c
r26352 | r26353 | |
528 | 528 | // nothing to do yet |
529 | 529 | } |
530 | 530 | |
| 531 | void alto2_cpu_device::reset_disp() |
| 532 | { |
| 533 | m_dsp.state = 020; |
| 534 | m_dsp.hlc = ALTO2_DISPLAY_HLC_START; |
| 535 | m_dsp.a63 = 0; |
| 536 | m_dsp.a66 = 0; |
| 537 | m_dsp.setmode = 0; |
| 538 | m_dsp.inverse = 0; |
| 539 | m_dsp.halfclock = 0; |
| 540 | m_dsp.clr = 0; |
| 541 | m_dsp.fifo_wr = 0; |
| 542 | m_dsp.fifo_rd = 0; |
| 543 | m_dsp.dht_blocks = false; |
| 544 | m_dsp.dwt_blocks = false; |
| 545 | m_dsp.curt_blocks = false; |
| 546 | m_dsp.curt_wakeup = false; |
| 547 | m_dsp.vblank = 0; |
| 548 | m_dsp.xpreg = 0; |
| 549 | m_dsp.csr = 0; |
| 550 | m_dsp.curword = 0; |
| 551 | m_dsp.curdata = 0; |
| 552 | memset(m_dsp.raw_bitmap, 0, sizeof(UINT16) * ALTO2_DISPLAY_HEIGHT * ALTO2_DISPLAY_SCANLINE_WORDS); |
| 553 | for (int y = 0; y < ALTO2_DISPLAY_HEIGHT; y++) |
| 554 | memset(m_dsp.scanline[y], 0, sizeof(UINT8) * ALTO2_DISPLAY_TOTAL_WIDTH); |
| 555 | m_dsp.odd_frame = false; |
| 556 | } |
| 557 | |
531 | 558 | /* Video update */ |
532 | 559 | UINT32 alto2_cpu_device::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect) |
533 | 560 | { |
branches/alto2/src/emu/cpu/alto2/a2dvt.h
r26352 | r26353 | |
15 | 15 | |
16 | 16 | //! F2 functions for display vertical task |
17 | 17 | enum { |
18 | | f2_dvt_evenfield = f2_task_10 //!< f2 10: load even field |
| 18 | f2_dvt_evenfield = f2_task_10 //!< f2 10: load even field |
19 | 19 | }; |
20 | 20 | |
21 | 21 | void f1_early_dvt_block(); //!< F1 func: disable the display word task |
22 | 22 | void activate_dvt(); //!< called by the CPU when the display vertical task becomes active |
23 | | void init_dvt(int task = task_dvt); //!< initialize display vertical task |
24 | | void exit_dvt(); //!< deinitialize display vertical task |
| 23 | void init_dvt(int task = task_dvt); //!< initialize the display vertical task |
| 24 | void exit_dvt(); //!< deinitialize the display vertical task |
| 25 | void reset_dvt(); //!< reset the display vertical task |
25 | 26 | #endif // _A2DVT_H_ |
26 | 27 | #endif // ALTO2_DEFINE_CONSTANTS |
branches/alto2/src/emu/cpu/alto2/alto2cpu.c
r26352 | r26353 | |
757 | 757 | /* type */ sizeof(UINT8) |
758 | 758 | }; |
759 | 759 | |
760 | | static const prom_load_t pl_madr_a64 = |
761 | | { |
762 | | "madr.a64", |
763 | | 0, |
764 | | "a66b0eda", |
765 | | "4d9088f592caa3299e90966b17765be74e523144", |
766 | | /* size */ 0400, |
767 | | /* amap */ AMAP_DEFAULT, |
768 | | /* axor */ 0, |
769 | | /* dxor */ 017, // invert D0-D3 |
770 | | /* width */ 4, |
771 | | /* shift */ 0, |
772 | | /* dmap */ DMAP_DEFAULT, |
773 | | /* dand */ ZERO, |
774 | | /* type */ sizeof(UINT8) |
775 | | }; |
776 | | |
777 | | static const prom_load_t pl_madr_a65 = |
778 | | { |
779 | | "madr.a65", |
780 | | 0, |
781 | | "ba37febd", |
782 | | "82e9db1cb65f451755295f0d179e6f8fe3349d4d", |
783 | | /* size */ 0400, |
784 | | /* amap */ AMAP_DEFAULT, |
785 | | /* axor */ 0, |
786 | | /* dxor */ 017, // invert D0-D3 |
787 | | /* width */ 4, |
788 | | /* shift */ 0, |
789 | | /* dmap */ DMAP_DEFAULT, |
790 | | /* dand */ ZERO, |
791 | | /* type */ sizeof(UINT8) |
792 | | }; |
793 | | |
794 | 760 | static const prom_load_t pl_madr_a90 = |
795 | 761 | { |
796 | 762 | "madr.a90", |
r26352 | r26353 | |
867 | 833 | m_ctl2k_u76 = prom_load(machine(), &pl_2kctl_u76, memregion("2kctl_u76")->base()); |
868 | 834 | m_alu_a10 = prom_load(machine(), &pl_alu_a10, memregion("alu_a10")->base()); |
869 | 835 | m_cram3k_a37 = prom_load(machine(), &pl_3kcram_a37, memregion("3kcram_a37")->base()); |
870 | | m_madr_a64 = prom_load(machine(), &pl_madr_a64, memregion("madr_a64")->base()); |
871 | | m_madr_a65 = prom_load(machine(), &pl_madr_a65, memregion("madr_a65")->base()); |
872 | 836 | m_madr_a90 = prom_load(machine(), &pl_madr_a90, memregion("madr_a90")->base()); |
873 | 837 | m_madr_a91 = prom_load(machine(), &pl_madr_a91, memregion("madr_a91")->base()); |
874 | 838 | |
r26352 | r26353 | |
1194 | 1158 | // device_reset - device-specific reset |
1195 | 1159 | //------------------------------------------------- |
1196 | 1160 | |
1197 | | // FIXME |
1198 | 1161 | void alto2_cpu_device::device_reset() |
1199 | 1162 | { |
1200 | 1163 | soft_reset(); |
| 1164 | |
| 1165 | // call all sub-devices' reset_... |
| 1166 | reset_memory(); |
| 1167 | reset_disk(); |
| 1168 | reset_disp(); |
| 1169 | reset_kbd(); |
| 1170 | reset_mouse(); |
| 1171 | reset_hw(); |
| 1172 | |
| 1173 | reset_emu(); |
| 1174 | reset_ksec(); |
| 1175 | reset_ether(); |
| 1176 | reset_mrt(); |
| 1177 | reset_dwt(); |
| 1178 | reset_curt(); |
| 1179 | reset_dht(); |
| 1180 | reset_dvt(); |
| 1181 | reset_part(); |
| 1182 | reset_kwd(); |
1201 | 1183 | } |
1202 | 1184 | |
1203 | 1185 | /** |
r26352 | r26353 | |
1213 | 1195 | |
1214 | 1196 | void alto2_cpu_device::interface_post_reset() |
1215 | 1197 | { |
1216 | | |
1217 | 1198 | // set the disk unit sector callbacks |
1218 | 1199 | for (int unit = 0; unit < diablo_hd_device::DIABLO_UNIT_MAX; unit++) { |
1219 | 1200 | diablo_hd_device* dhd = m_drive[unit]; |
r26352 | r26353 | |
2872 | 2853 | } |
2873 | 2854 | |
2874 | 2855 | /** @brief software initiated reset (STARTF) */ |
2875 | | int alto2_cpu_device::soft_reset() |
| 2856 | void alto2_cpu_device::soft_reset() |
2876 | 2857 | { |
2877 | 2858 | |
2878 | 2859 | for (int task = 0; task < ALTO2_TASKS; task++) { |
r26352 | r26353 | |
2886 | 2867 | |
2887 | 2868 | m_dsp_time = 0; // reset the display state timing |
2888 | 2869 | |
2889 | | // FIXME: all sub-devices need a reset_... method as well |
2890 | | |
2891 | | return m_next_task; // return next task (?) |
| 2870 | m_task = task_emu; // start with task 0 (emulator) |
| 2871 | m_task_wakeup |= 1 << task_emu; // set wakeup flag |
2892 | 2872 | } |
branches/alto2/src/mess/drivers/alto2.c
r26352 | r26353 | |
123 | 123 | PORT_CONFNAME( 0x01, 0x01, "Memory switch") |
124 | 124 | PORT_CONFSETTING( 0x00, "on") |
125 | 125 | PORT_CONFSETTING( 0x01, "off") |
| 126 | PORT_CONFNAME( 0x70, 0x00, "Ethernet 'duckbreath' fake") |
| 127 | PORT_CONFSETTING( 0x00, "off") |
| 128 | PORT_CONFSETTING( 0x10, "5 seconds") |
| 129 | PORT_CONFSETTING( 0x20, "10 seconds") |
| 130 | PORT_CONFSETTING( 0x30, "15 seconds") |
| 131 | PORT_CONFSETTING( 0x40, "30 seconds") |
| 132 | PORT_CONFSETTING( 0x50, "60 seconds") |
| 133 | PORT_CONFSETTING( 0x60, "90 seconds") |
| 134 | PORT_CONFSETTING( 0x70, "120 seconds") |
126 | 135 | INPUT_PORTS_END |
127 | 136 | |
128 | 137 | /* ROM */ |