branches/alto2/src/emu/cpu/alto2/a2ether.c
r26351 | r26352 | |
83 | 83 | /** |
84 | 84 | * @brief BPROM; P3601-1; 265x4 enet.a49 "AFIFO" |
85 | 85 | * |
86 | | * Perhaps try with the contents of the display FIFO, as it is |
87 | | * the same type and the display FIFO has the same size. |
88 | | * |
89 | 86 | * FIFO control |
90 | 87 | * |
91 | 88 | * a49: P3601-1; 256x4; "AFIFO" |
r26351 | r26352 | |
104 | 101 | * outputs active low |
105 | 102 | * ---------------------------- |
106 | 103 | * D0 (12) BE' (buffer empty) |
107 | | * D1 (11) BNE' (buffer next empty ?) |
108 | | * D2 (10) BNNE' (buffer next next empty ?) |
| 104 | * D1 (11) BNE' (buffer nearly empty) |
| 105 | * D2 (10) BNNE' (buffer next nearly empty) |
109 | 106 | * D3 (9) BF' (buffer full) |
110 | 107 | */ |
111 | 108 | static const prom_load_t pl_enet_a49 = |
r26351 | r26352 | |
161 | 158 | #define GET_ETH_IT(st) X_BIT(st,16,15) //!< hardware status: IT flip flop & ISRFULL' |
162 | 159 | #define PUT_ETH_IT(st,val) X_WRBITS(st,16,15,15,val) |
163 | 160 | |
164 | | //! PROM ether.u49; buffer empty (active low) |
165 | | #define ETHER_A49_BE (m_ether_a49[16 * m_eth.fifo_wr + m_eth.fifo_rd] & (1 << 0)) |
| 161 | #define BE(a49) ((a49 & ether_a49_BE) ? 1 : 0) //! buffer empty |
| 162 | #define BNE(a49) ((a49 & ether_a49_BNE) ? 1 : 0) //! buffer next empty |
| 163 | #define BNNE(a49) ((a49 & ether_a49_BNNE) ? 1 : 0) //! buffer next next empty |
| 164 | #define BF(a49) ((a49 & ether_a49_BF) ? 1 : 0) //! buffer full |
166 | 165 | |
167 | | //! PROM ether.u49; buffer next(?) empty (active low) |
168 | | #define ETHER_A49_BNE (m_ether_a49[16 * m_eth.fifo_wr + m_eth.fifo_rd] & (1 << 1)) |
169 | | |
170 | | //! PROM ether.u49; buffer next next(?) empty (active low) |
171 | | #define ETHER_A49_BNNE (m_ether_a49[16 * m_eth.fifo_wr + m_eth.fifo_rd] & (1 << 2)) |
172 | | |
173 | | //! PROM ether.u49; buffer full (active low) |
174 | | #define ETHER_A49_BF (m_ether_a49[16 * m_eth.fifo_wr + m_eth.fifo_rd] & (1 << 3)) |
175 | | |
176 | 166 | #define BREATHLEN ALTO2_ETHER_PACKET_SIZE //!< ethernet packet length |
177 | 167 | #define BREATHADDR 0177400 //!< destination and source |
178 | 168 | #define BREATHTYPE 0000602 //!< ethernet packet type |
r26351 | r26352 | |
258 | 248 | */ |
259 | 249 | void alto2_cpu_device::eth_wakeup() |
260 | 250 | { |
261 | | register int etac = m_task == task_ether; |
262 | | |
263 | | LOG((LOG_ETH,0,"eth_wakeup: ibusy=%d obusy=%d ", GET_ETH_IBUSY(m_eth.status), GET_ETH_OBUSY(m_eth.status))); |
264 | | register int busy = GET_ETH_IBUSY(m_eth.status) | GET_ETH_OBUSY(m_eth.status); |
| 251 | register int st = m_eth.status; |
| 252 | LOG((LOG_ETH,0,"IBUSY=%d OBUSY=%d ", GET_ETH_IBUSY(st), GET_ETH_OBUSY(st))); |
| 253 | UINT8 busy = GET_ETH_IBUSY(st) | GET_ETH_OBUSY(st); |
265 | 254 | if (0 == busy) { |
266 | 255 | // if not busy, reset the FIFO read and write counters |
267 | 256 | m_eth.fifo_rd = 0; |
r26351 | r26352 | |
276 | 265 | * output gone |
277 | 266 | * input gone |
278 | 267 | */ |
279 | | if (GET_ETH_IDL(m_eth.status)) { |
280 | | LOG((LOG_ETH,0,"post (input data late)\n")); |
| 268 | if (GET_ETH_IDL(st)) { |
| 269 | LOG((LOG_ETH,0,"POST (input data late)\n")); |
281 | 270 | m_task_wakeup |= 1 << task_ether; |
282 | 271 | return; |
283 | 272 | } |
284 | | if (GET_ETH_OCMD(m_eth.status)) { |
285 | | LOG((LOG_ETH,0,"post (output command)\n")); |
| 273 | if (GET_ETH_OCMD(st)) { |
| 274 | LOG((LOG_ETH,0,"POST (output command)\n")); |
286 | 275 | m_task_wakeup |= 1 << task_ether; |
287 | 276 | return; |
288 | 277 | } |
289 | | if (GET_ETH_ICMD(m_eth.status)) { |
290 | | LOG((LOG_ETH,0,"post (input command)\n")); |
| 278 | if (GET_ETH_ICMD(st)) { |
| 279 | LOG((LOG_ETH,0,"POST (input command)\n")); |
291 | 280 | m_task_wakeup |= 1 << task_ether; |
292 | 281 | return; |
293 | 282 | } |
294 | | if (GET_ETH_OGONE(m_eth.status)) { |
295 | | LOG((LOG_ETH,0,"post (output gone)\n")); |
| 283 | if (GET_ETH_OGONE(st)) { |
| 284 | LOG((LOG_ETH,0,"POST (output gone)\n")); |
296 | 285 | m_task_wakeup |= 1 << task_ether; |
297 | 286 | return; |
298 | 287 | } |
299 | | if (GET_ETH_IGONE(m_eth.status)) { |
300 | | LOG((LOG_ETH,0,"post (input gone)\n")); |
| 288 | if (GET_ETH_IGONE(st)) { |
| 289 | LOG((LOG_ETH,0,"POST (input gone)\n")); |
301 | 290 | m_task_wakeup |= 1 << task_ether; |
302 | 291 | return; |
303 | 292 | } |
r26351 | r26352 | |
305 | 294 | /* |
306 | 295 | * IDR (input data ready) conditions to wakeup the Ether task (AND): |
307 | 296 | * IBUSY input busy |
308 | | * BNNE buffer next next empty |
309 | | * BNE buffer next empty |
| 297 | * BNNE buffer next nearly empty |
| 298 | * BNE buffer nearly empty |
310 | 299 | * ETAC ether task active |
311 | 300 | * |
312 | 301 | * IDR' = (IBUSY & (BNNE & (BNE' & ETAC')')')' |
313 | 302 | */ |
314 | | register int idr = GET_ETH_IBUSY(m_eth.status) && (ETHER_A49_BNNE || (ETHER_A49_BNE == 0 && etac)); |
| 303 | UINT8 a49 = m_ether_a49[16 * m_eth.fifo_rd + m_eth.fifo_wr]; |
| 304 | UINT8 etac = m_task == task_ether ? 0 : 1; |
| 305 | UINT8 idr = GET_ETH_IBUSY(st) & ~(~BNNE(a49) & ~(BNE(a49) & etac)); |
315 | 306 | if (idr) { |
316 | 307 | m_task_wakeup |= 1 << task_ether; |
317 | 308 | LOG((LOG_ETH,0,"input data ready\n")); |
r26351 | r26352 | |
327 | 318 | * |
328 | 319 | * ODR' = (OBUSY & OEOT' & (BF' & WLF')')' |
329 | 320 | */ |
330 | | register int odr = GET_ETH_OBUSY(m_eth.status) && (GET_ETH_OEOT(m_eth.status) || (GET_ETH_WLF(m_eth.status) && ETHER_A49_BF == 0)); |
| 321 | UINT8 odr = GET_ETH_OBUSY(st) & ~(~GET_ETH_OEOT(st) & ~(BF(a49) & ~GET_ETH_WLF(st))); |
331 | 322 | if (odr) { |
332 | 323 | m_task_wakeup |= 1 << task_ether; |
333 | 324 | LOG((LOG_ETH,0,"output data ready\n")); |
r26351 | r26352 | |
342 | 333 | */ |
343 | 334 | if (m_ewfct) { |
344 | 335 | m_task_wakeup |= 1 << task_ether; |
345 | | LOG((LOG_ETH,0,"ether wake function\n")); |
| 336 | LOG((LOG_ETH,0,"EWFCT (ether wake function)\n")); |
346 | 337 | return; |
347 | 338 | } |
348 | 339 | |
349 | 340 | // otherwise no more wakeups for the ether task |
350 | | LOG((LOG_ETH,0,"-/-\n")); |
| 341 | LOG((LOG_ETH,0,"stop wake\n")); |
351 | 342 | m_task_wakeup &= ~(1 << task_ether); |
352 | 343 | } |
353 | 344 | |
r26351 | r26352 | |
449 | 440 | */ |
450 | 441 | UINT32 f9401_7(UINT32 crc, UINT32 data) |
451 | 442 | { |
452 | | int i; |
453 | | for (i = 0; i < 16; i++) { |
454 | | crc <<= 1; |
455 | | if (data & (1 << 15)) |
456 | | crc ^= (1 << 10) | (1 << 3) | (1 << 0); |
457 | | data <<= 1; |
458 | | } |
| 443 | static const UINT32 XOR = (1 << 10) | (1 << 3) | (1 << 0); |
| 444 | crc ^= data; |
| 445 | for (int i = 0; i < 16; i++) |
| 446 | crc = (crc >> 1) ^ ((crc & 1) ? XOR : 0); |
459 | 447 | return crc & 0177777; |
460 | 448 | } |
461 | 449 | |
r26351 | r26352 | |
470 | 458 | UINT32 data; |
471 | 459 | |
472 | 460 | if (arg == 0) { |
473 | | // first word: set the IBUSY flip flop |
| 461 | // on the first word set the IBUSY flip flop |
474 | 462 | PUT_ETH_IBUSY(m_eth.status, 1); |
475 | 463 | m_eth.rx_count = 0; |
476 | 464 | } |
477 | 465 | |
478 | | data = duckbreath_data[arg++]; |
| 466 | if (arg >= BREATHLEN) { |
| 467 | // CRC after the data |
| 468 | data = m_eth.rx_crc; |
| 469 | arg++; |
| 470 | } else { |
| 471 | // next data word |
| 472 | data = duckbreath_data[arg++]; |
| 473 | } |
479 | 474 | m_eth.rx_crc = f9401_7(m_eth.rx_crc, data); |
480 | | |
481 | 475 | m_eth.fifo[m_eth.fifo_wr] = data; |
482 | 476 | m_eth.fifo_wr = (m_eth.fifo_wr + 1) % ALTO2_ETHER_FIFO_SIZE; |
483 | 477 | |
484 | | if (m_eth.rx_count < ALTO2_ETHER_PACKET_SIZE) |
485 | | m_eth.rx_packet[m_eth.rx_count] = data; |
486 | | m_eth.rx_count++; |
| 478 | // PUT_ETH_WLF(m_eth.status, 1); // set WLF (write latch full)? |
487 | 479 | |
488 | | PUT_ETH_WLF(m_eth.status, 1); |
489 | | if (ETHER_A49_BF == 0) { |
490 | | /* fifo is overrun: set input data late flip flop */ |
491 | | PUT_ETH_IDL(m_eth.status, 1); |
492 | | } |
| 480 | UINT8 a49 = m_ether_a49[16 * m_eth.fifo_rd + m_eth.fifo_wr]; |
| 481 | if (0 == BF(a49)) |
| 482 | PUT_ETH_IDL(m_eth.status, 1); // fifo is overrun: set input data late flip flop |
493 | 483 | |
494 | | if (arg == BREATHLEN) { |
| 484 | if (arg > BREATHLEN) { |
495 | 485 | /* |
496 | | * last word: reset the receiver CRC |
497 | | * |
498 | 486 | * TODO: if data comes from some other source, |
499 | 487 | * compare our CRC with the next word received |
500 | 488 | * and set the CRC error flag if they differ. |
501 | 489 | */ |
502 | 490 | m_eth.rx_crc = 0; |
503 | | |
504 | | // set the IGONE flip flop |
505 | | PUT_ETH_IGONE(m_eth.status, 1); |
506 | | #if DEBUG_PACKETS |
507 | | dump_packet(m_eth.rx_packet, 0, m_eth.rx_count); |
508 | | #endif |
| 491 | PUT_ETH_IGONE(m_eth.status, 1); // set the IGONE flip flop |
509 | 492 | m_eth.rx_timer->adjust(attotime::from_seconds(m_duckbreath_sec), 0); |
510 | 493 | } else { |
511 | 494 | // receive at a rate of 5.44us per word |
r26351 | r26352 | |
517 | 500 | /** |
518 | 501 | * @brief transmit data from the FIFO to <nirvana for now> |
519 | 502 | * |
520 | | * @param id timer id |
| 503 | * @param ptr unused pointer |
521 | 504 | * @param arg word count if >= 0, -1 if CRC is to be transmitted (last word) |
522 | 505 | */ |
523 | 506 | void alto2_cpu_device::tx_packet(void* ptr, INT32 arg) |
r26351 | r26352 | |
528 | 511 | if (-1 == arg) { |
529 | 512 | m_eth.tx_timer->reset(); |
530 | 513 | LOG((LOG_ETH,0," CRC:%06o\n", m_eth.tx_crc)); |
531 | | #if DEBUG_PACKETS |
532 | | dump_packet(m_eth.tx_packet, 0, m_eth.tx_count); |
533 | | #endif |
534 | 514 | // TODO: send the CRC as final word of the packet |
535 | 515 | m_eth.tx_crc = 0; |
536 | 516 | PUT_ETH_OGONE(m_eth.status, 1); // set the OGONE flip flop |
r26351 | r26352 | |
542 | 522 | m_eth.tx_crc = f9401_7(m_eth.tx_crc, data); |
543 | 523 | m_eth.fifo_rd = (m_eth.fifo_rd + 1) % ALTO2_ETHER_FIFO_SIZE; |
544 | 524 | |
545 | | if (m_eth.tx_count < ALTO2_ETHER_PACKET_SIZE) |
546 | | m_eth.tx_packet[m_eth.tx_count] = data; |
547 | | m_eth.tx_count++; |
548 | | |
549 | | // is the FIFO empty now? |
550 | | if (ETHER_A49_BE) { |
551 | | /* clear the OBUSY and WLF flip flops */ |
| 525 | UINT8 a49 = m_ether_a49[16 * m_eth.fifo_rd + m_eth.fifo_wr]; |
| 526 | if (0 == BE(a49)) { |
| 527 | // the FIFO is empty now: clear the OBUSY and WLF flip flops |
552 | 528 | PUT_ETH_OBUSY(m_eth.status, 0); |
553 | 529 | PUT_ETH_WLF(m_eth.status, 0); |
554 | 530 | m_eth.tx_timer->adjust(attotime::from_usec(5.44), -1); |
555 | | eth_wakeup(); |
556 | | return; |
| 531 | } else { |
| 532 | // transmit teh next word after 5.44µs |
| 533 | m_eth.tx_timer->adjust(attotime::from_usec(5.44), arg + 1); |
557 | 534 | } |
558 | | |
559 | | /* transmit teh next word after 5.44µs */ |
560 | | m_eth.tx_timer->adjust(attotime::from_usec(5.44), arg + 1); |
561 | 535 | eth_wakeup(); |
562 | 536 | } |
563 | 537 | |
r26351 | r26352 | |
568 | 542 | { |
569 | 543 | PUT_ETH_ICMD(m_eth.status, X_BIT(m_bus,16,14)); |
570 | 544 | PUT_ETH_OCMD(m_eth.status, X_BIT(m_bus,16,15)); |
571 | | if (GET_ETH_ICMD(m_eth.status) || GET_ETH_OCMD(m_eth.status)) |
572 | | m_task_wakeup |= 1 << task_ether; |
| 545 | LOG((LOG_ETH,3, " STARTF; ICMD=%u OCMD=%u\n", GET_ETH_ICMD(m_eth.status), GET_ETH_ICMD(m_eth.status))); |
| 546 | eth_wakeup(); |
573 | 547 | } |
574 | 548 | |
575 | 549 | /** |
r26351 | r26352 | |
581 | 555 | void alto2_cpu_device::bs_early_eidfct() |
582 | 556 | { |
583 | 557 | UINT16 r = m_eth.fifo[m_eth.fifo_rd]; |
584 | | |
585 | 558 | LOG((LOG_ETH,3, " ←EIDFCT; pull %06o from FIFO[%02o]\n", r, m_eth.fifo_rd)); |
586 | 559 | m_eth.fifo_rd = (m_eth.fifo_rd + 1) % ALTO2_ETHER_FIFO_SIZE; |
587 | 560 | m_bus &= r; |
| 561 | |
| 562 | #if DEBUG_PACKETS |
| 563 | if (m_eth.rx_count < ALTO2_ETHER_PACKET_SIZE) |
| 564 | m_eth.rx_packet[m_eth.rx_count] = r; |
| 565 | m_eth.rx_count++; |
| 566 | if (ALTO2_ETHER_PACKET_SIZE == m_eth.rx_count) { |
| 567 | dump_packet(m_eth.rx_packet, 0, m_eth.rx_count); |
| 568 | m_eth.rx_count = 0; |
| 569 | } |
| 570 | #endif |
588 | 571 | eth_wakeup(); |
589 | 572 | } |
590 | 573 | |
r26351 | r26352 | |
627 | 610 | void alto2_cpu_device::f1_early_epfct() |
628 | 611 | { |
629 | 612 | UINT16 r = ~X_RDBITS(m_eth.status,16,10,15) & 0177777; |
| 613 | m_eth.status = 0; |
| 614 | m_eth.tx_count = 0; |
| 615 | eth_wakeup(); |
630 | 616 | |
631 | 617 | LOG((LOG_ETH,3, " ←EPFCT; BUS[8-15] = STATUS (%#o)\n", r)); |
632 | | LOG((LOG_ETH,5, " IDL : %u\n", GET_ETH_IDL(m_eth.status))); |
633 | | LOG((LOG_ETH,5, " COLL : %u\n", GET_ETH_COLL(m_eth.status))); |
634 | | LOG((LOG_ETH,5, " CRC : %u\n", GET_ETH_CRC(m_eth.status))); |
635 | | LOG((LOG_ETH,5, " ICMD : %u\n", GET_ETH_ICMD(m_eth.status))); |
636 | | LOG((LOG_ETH,5, " OCMD : %u\n", GET_ETH_OCMD(m_eth.status))); |
637 | | LOG((LOG_ETH,5, " IT : %u\n", GET_ETH_IT(m_eth.status))); |
| 618 | LOG((LOG_ETH,5, " IDL' : %u\n", GET_ETH_IDL(r))); |
| 619 | LOG((LOG_ETH,5, " COLL' : %u\n", GET_ETH_COLL(r))); |
| 620 | LOG((LOG_ETH,5, " CRC' : %u\n", GET_ETH_CRC(r))); |
| 621 | LOG((LOG_ETH,5, " ICMD' : %u\n", GET_ETH_ICMD(r))); |
| 622 | LOG((LOG_ETH,5, " OCMD' : %u\n", GET_ETH_OCMD(r))); |
| 623 | LOG((LOG_ETH,5, " IT' : %u\n", GET_ETH_IT(r))); |
638 | 624 | |
639 | 625 | m_bus &= r; |
640 | | |
641 | | m_eth.status = 0; |
642 | | m_eth.tx_count = 0; |
643 | | eth_wakeup(); |
644 | 626 | } |
645 | 627 | |
646 | 628 | /** |
r26351 | r26352 | |
665 | 647 | * |
666 | 648 | * Loads the FIFO from BUS[0-15], then increments the write |
667 | 649 | * pointer at the end of the cycle. |
| 650 | * |
| 651 | * Comment from the micro code: |
| 652 | *<PRE> |
| 653 | * Ether Output Data Function - EODFCT. Copy the bus into the |
| 654 | * interface data buffer, increment the write pointer, clears wakeup |
| 655 | * request if the buffer is now nearly full (one slot available). |
| 656 | *</PRE> |
668 | 657 | */ |
669 | 658 | void alto2_cpu_device::f2_late_eodfct() |
670 | 659 | { |
671 | 660 | LOG((LOG_ETH,3, " EODFCT←; push %06o into FIFO[%02o]\n", m_bus, m_eth.fifo_wr)); |
672 | | |
673 | 661 | m_eth.fifo[m_eth.fifo_wr] = m_bus; |
674 | 662 | m_eth.fifo_wr = (m_eth.fifo_wr + 1) % ALTO2_ETHER_FIFO_SIZE; |
675 | 663 | |
676 | | PUT_ETH_WLF(m_eth.status, 1); |
677 | | PUT_ETH_OBUSY(m_eth.status, 1); |
678 | | // if the FIFO is full, kick off the timer |
679 | | if (0 == ETHER_A49_BF) |
| 664 | #if DEBUG_PACKETS |
| 665 | if (m_eth.tx_count < ALTO2_ETHER_PACKET_SIZE) |
| 666 | m_eth.tx_packet[m_eth.tx_count] = m_bus; |
| 667 | m_eth.tx_count++; |
| 668 | if (ALTO2_ETHER_PACKET_SIZE == m_eth.tx_count) { |
| 669 | dump_packet(m_eth.tx_packet, 0, m_eth.tx_count); |
| 670 | m_eth.tx_count = 0; |
| 671 | } |
| 672 | #endif |
| 673 | |
| 674 | PUT_ETH_WLF(m_eth.status, 1); // set WLF (write latch full) |
| 675 | PUT_ETH_OBUSY(m_eth.status, 1); // set OBUSY (output busy) |
| 676 | eth_wakeup(); |
| 677 | // if the FIFO is full, stop wakeup and kick off the timer |
| 678 | UINT8 a49 = m_ether_a49[16 * m_eth.fifo_rd + m_eth.fifo_wr]; |
| 679 | if (0 == BF(a49)) { |
| 680 | m_task_wakeup &= ~(1 << task_ether); |
680 | 681 | m_eth.tx_timer->adjust(attotime::from_usec(5.44), 0); |
681 | | eth_wakeup(); |
| 682 | } |
682 | 683 | } |
683 | 684 | |
684 | 685 | /** |
r26351 | r26352 | |
692 | 693 | void alto2_cpu_device::f2_late_eosfct() |
693 | 694 | { |
694 | 695 | LOG((LOG_ETH,3, " EOSFCT\n")); |
695 | | PUT_ETH_WLF(m_eth.status, 0); |
696 | | PUT_ETH_OBUSY(m_eth.status, 0); |
| 696 | PUT_ETH_WLF(m_eth.status, 1); |
| 697 | PUT_ETH_OBUSY(m_eth.status, 1); |
697 | 698 | eth_wakeup(); |
698 | 699 | } |
699 | 700 | |
r26351 | r26352 | |
746 | 747 | { |
747 | 748 | UINT16 r = 0; |
748 | 749 | X_WRBITS(r,10,6,6, GET_ETH_COLL(m_eth.status)); |
749 | | X_WRBITS(r,10,7,7, GET_ETH_IDL(m_eth.status) | |
750 | | GET_ETH_ICMD(m_eth.status) | |
751 | | GET_ETH_OCMD(m_eth.status) | |
752 | | GET_ETH_IGONE(m_eth.status) | |
753 | | GET_ETH_OGONE(m_eth.status)); |
| 750 | X_WRBITS(r,10,7,7, |
| 751 | GET_ETH_IDL(m_eth.status) | |
| 752 | GET_ETH_ICMD(m_eth.status) | |
| 753 | GET_ETH_OCMD(m_eth.status) | |
| 754 | GET_ETH_IGONE(m_eth.status) | |
| 755 | GET_ETH_OGONE(m_eth.status)); |
754 | 756 | LOG((LOG_ETH,3, " EBFCT; NEXT ... (%#o | %#o)\n", m_next2, r)); |
755 | 757 | m_next2 |= r; |
756 | 758 | } |
r26351 | r26352 | |
758 | 760 | /** |
759 | 761 | * @brief f2_ecbfct late: ethernet countdown branch function |
760 | 762 | * |
| 763 | * The BE' (buffer empty) signal is output D0 of PROM a49 |
761 | 764 | * ORs a one into NEXT[7] if the FIFO is not empty. |
762 | 765 | */ |
763 | 766 | void alto2_cpu_device::f2_late_ecbfct() |
764 | 767 | { |
765 | 768 | UINT16 r = 0; |
766 | | /* TODO: the BE' (buffer empty) signal is output D0 of PROM a49 */ |
767 | | X_WRBITS(r,10,7,7,ETHER_A49_BE); |
| 769 | UINT8 a49 = m_ether_a49[16 * m_eth.fifo_rd + m_eth.fifo_wr]; |
| 770 | X_WRBITS(r,10,7,7,~BE(a49)); |
768 | 771 | LOG((LOG_ETH,3, " ECBFCT; NEXT[7] = FIFO %sempty (%#o | %#o)\n", r ? "not " : "is ", m_next2, r)); |
769 | 772 | m_next2 |= r; |
770 | 773 | } |
r26351 | r26352 | |
780 | 783 | void alto2_cpu_device::f2_late_eisfct() |
781 | 784 | { |
782 | 785 | LOG((LOG_ETH,3, " EISFCT\n")); |
783 | | PUT_ETH_IBUSY(m_eth.status, 0); |
| 786 | PUT_ETH_IBUSY(m_eth.status, 1); |
784 | 787 | eth_wakeup(); |
785 | 788 | } |
786 | 789 | |