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r24795 Wednesday 7th August, 2013 at 17:19:22 UTC by Wilbert Pol
m6800.c: Modernized cpu core (nw)

[src/emu/cpu/m6800]	6800ops.c 6800tbl.c m6800.c m6800.h
[src/mame/audio]	midway.h
[src/mame/drivers]	baraduke.c namcos1.c namcos86.c pacland.c skykid.c tceptor.c
[src/mess/drivers]	adam.c atarist.c hx20.c mc10.c psion.c
[src/mess/includes]	psion.h
[src/mess/machine]	adam_ddp.c adam_fdc.c adam_kb.c adam_prn.c adam_spi.c pf10.c

trunk/src/mame/audio/midway.h

r24794	r24795
295	295
296	296	private:
297	297	// devices
298		required_device<m6802_device> m_cpu;
	298	required_device<m6802_cpu_device> m_cpu;
299	299	required_device<pia6821_device> m_pia0;
300	300	required_device<pia6821_device> m_pia1;
301	301	optional_device<tms5200_device> m_tms5200;

trunk/src/mame/drivers/tceptor.c

r24794	r24795
206	206
207	207
208	208	static ADDRESS_MAP_START( mcu_map, AS_PROGRAM, 8, tceptor_state )
209		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r, m6801_io_w)
	209	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE("mcu", hd63701_cpu_device, m6801_io_r, m6801_io_w)
210	210	AM_RANGE(0x0080, 0x00ff) AM_RAM
211	211	AM_RANGE(0x1000, 0x13ff) AM_DEVREADWRITE("namco", namco_cus30_device, namcos1_cus30_r, namcos1_cus30_w)
212	212	AM_RANGE(0x1400, 0x154d) AM_RAM

trunk/src/mame/drivers/namcos1.c

r24794	r24795
477	477
478	478
479	479	static ADDRESS_MAP_START( mcu_map, AS_PROGRAM, 8, namcos1_state )
480		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r, m6801_io_w)
	480	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE("mcu", hd63701_cpu_device, m6801_io_r, m6801_io_w)
481	481	AM_RANGE(0x0080, 0x00ff) AM_RAM /* built in RAM */
482	482	AM_RANGE(0x1000, 0x1003) AM_READ(dsw_r)
483	483	AM_RANGE(0x1400, 0x1400) AM_READ_PORT("CONTROL0")

trunk/src/mame/drivers/namcos86.c

r24794	r24795
387	387
388	388	#define MCU_MEMORY(NAME,ADDR_LOWROM,ADDR_INPUT,ADDR_UNK1,ADDR_UNK2)         \
389	389	static ADDRESS_MAP_START( NAME##_mcu_map, AS_PROGRAM, 8, namcos86_state )   \
390		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r,m6801_io_w) \
	390	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE("mcu", hd63701_cpu_device, m6801_io_r,m6801_io_w) \
391	391	AM_RANGE(0x0080, 0x00ff) AM_RAM                                                     \
392	392	AM_RANGE(0x1000, 0x13ff) AM_DEVREADWRITE("namco", namco_cus30_device, namcos1_cus30_r, namcos1_cus30_w) /* PSG device, shared RAM */ \
393	393	AM_RANGE(0x1400, 0x1fff) AM_RAM                                                     \

trunk/src/mame/drivers/skykid.c

r24794	r24795
115	115	ADDRESS_MAP_END
116	116
117	117	static ADDRESS_MAP_START( mcu_map, AS_PROGRAM, 8, skykid_state )
118		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r, m6801_io_w)
	118	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE("mcu", hd63701_cpu_device, m6801_io_r, m6801_io_w)
119	119	AM_RANGE(0x0080, 0x00ff) AM_RAM
120	120	AM_RANGE(0x1000, 0x13ff) AM_DEVREADWRITE("namco", namco_cus30_device, namcos1_cus30_r, namcos1_cus30_w) /* PSG device, shared RAM */
121	121	AM_RANGE(0x2000, 0x3fff) AM_WRITE(watchdog_reset_w)     /* watchdog? */

trunk/src/mame/drivers/pacland.c

r24794	r24795
251	251	ADDRESS_MAP_END
252	252
253	253	static ADDRESS_MAP_START( mcu_map, AS_PROGRAM, 8, pacland_state )
254		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r, m6801_io_w)
	254	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE("mcu", hd63701_cpu_device, m6801_io_r, m6801_io_w)
255	255	AM_RANGE(0x0080, 0x00ff) AM_RAM
256	256	AM_RANGE(0x1000, 0x13ff) AM_DEVREADWRITE("namco", namco_cus30_device, namcos1_cus30_r, namcos1_cus30_w)      /* PSG device, shared RAM */
257	257	AM_RANGE(0x2000, 0x3fff) AM_WRITE(watchdog_reset_w)     /* watchdog? */

trunk/src/mame/drivers/baraduke.c

r24794	r24795
177	177	}
178	178
179	179	static ADDRESS_MAP_START( mcu_map, AS_PROGRAM, 8, baraduke_state )
180		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r,m6801_io_w)/* internal registers */
	180	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE("mcu", hd63701_cpu_device, m6801_io_r,m6801_io_w)/* internal registers */
181	181	AM_RANGE(0x0080, 0x00ff) AM_RAM                             /* built in RAM */
182	182	AM_RANGE(0x1105, 0x1105) AM_READ(soundkludge_r)             /* cures speech */
183	183	AM_RANGE(0x1000, 0x13ff) AM_DEVREADWRITE("namco", namco_cus30_device, namcos1_cus30_r, namcos1_cus30_w) /* PSG device, shared RAM */

trunk/src/emu/cpu/m6800/m6800.c

r24794	r24795
105	105	};
106	106	#endif
107	107
108		/* 6800 Registers */
109		struct m6800_state
110		{
111		//  int     subtype;        /* CPU subtype */
112		PAIR    ppc;            /* Previous program counter */
113		PAIR    pc;             /* Program counter */
114		PAIR    s;              /* Stack pointer */
115		PAIR    x;              /* Index register */
116		PAIR    d;              /* Accumulators */
117		UINT8   cc;             /* Condition codes */
118		UINT8   wai_state;      /* WAI opcode state ,(or sleep opcode state) */
119		UINT8   nmi_state;      /* NMI line state */
120		UINT8   nmi_pending;    /* NMI pending */
121		UINT8   irq_state[3];   /* IRQ line state [IRQ1,TIN,SC1] */
122		UINT8   ic_eddge;       /* InputCapture eddge , b.0=fall,b.1=raise */
123		int     sc1_state;
124	108
125		device_irq_acknowledge_callback irq_callback;
126		legacy_cpu_device *device;
127
128		/* Memory spaces */
129		address_space *program;
130		direct_read_data *direct;
131		address_space *data;
132		address_space *io;
133
134		void    (* const * insn)(m6800_state *);    /* instruction table */
135		const UINT8 *cycles;            /* clock cycle of instruction table */
136		/* internal registers */
137		UINT8   port1_ddr;
138		UINT8   port2_ddr;
139		UINT8   port3_ddr;
140		UINT8   port4_ddr;
141		UINT8   port1_data;
142		UINT8   port2_data;
143		UINT8   port3_data;
144		UINT8   port4_data;
145		UINT8   p3csr;          // Port 3 Control/Status Register
146		UINT8   tcsr;           /* Timer Control and Status Register */
147		UINT8   pending_tcsr;   /* pending IRQ flag for clear IRQflag process */
148		UINT8   irq2;           /* IRQ2 flags */
149		UINT8   ram_ctrl;
150		PAIR    counter;        /* free running counter */
151		PAIR    output_compare; /* output compare       */
152		UINT16  input_capture;  /* input capture        */
153		int     p3csr_is3_flag_read;
154		int     port3_latched;
155
156		int     clock;
157		UINT8   trcsr, rmcr, rdr, tdr, rsr, tsr;
158		int     rxbits, txbits, txstate, trcsr_read_tdre, trcsr_read_orfe, trcsr_read_rdrf, tx;
159		int     port2_written;
160
161		int     icount;
162		int     latch09;
163
164		PAIR    timer_over;
165		emu_timer *sci_timer;
166		PAIR ea;        /* effective address */
167
168		devcb_resolved_write_line   out_sc2_func;
169		};
170
171		INLINE m6800_state *get_safe_token(device_t *device)
172		{
173		assert(device != NULL);
174		assert(device->type() == M6800 ||
175		device->type() == M6801 ||
176		device->type() == M6802 ||
177		device->type() == M6803 ||
178		device->type() == M6808 ||
179		device->type() == HD6301 ||
180		device->type() == HD63701 ||
181		device->type() == NSC8105 ||
182		device->type() == HD6303R ||
183		device->type() == HD6303Y);
184		return (m6800_state *)downcast<legacy_cpu_device *>(device)->token();
185		}
186
187	109	#if 0
188		static void hd63701_trap_pc(m6800_state *cpustate);
	110	static void hd63701_trap_pc();
189	111	#endif
190	112
191		#define pPPC    cpustate->ppc
192		#define pPC     cpustate->pc
193		#define pS      cpustate->s
194		#define pX      cpustate->x
195		#define pD      cpustate->d
	113	#define pPPC    m_ppc
	114	#define pPC     m_pc
	115	#define pS      m_s
	116	#define pX      m_x
	117	#define pD      m_d
196	118
197		#define PC      cpustate->pc.w.l
198		#define PCD     cpustate->pc.d
199		#define S       cpustate->s.w.l
200		#define SD      cpustate->s.d
201		#define X       cpustate->x.w.l
202		#define D       cpustate->d.w.l
203		#define A       cpustate->d.b.h
204		#define B       cpustate->d.b.l
205		#define CC      cpustate->cc
	119	#define PC      m_pc.w.l
	120	#define PCD     m_pc.d
	121	#define S       m_s.w.l
	122	#define SD      m_s.d
	123	#define X       m_x.w.l
	124	#define D       m_d.w.l
	125	#define A       m_d.b.h
	126	#define B       m_d.b.l
	127	#define CC      m_cc
206	128
207		#define CT      cpustate->counter.w.l
208		#define CTH     cpustate->counter.w.h
209		#define CTD     cpustate->counter.d
210		#define OC      cpustate->output_compare.w.l
211		#define OCH     cpustate->output_compare.w.h
212		#define OCD     cpustate->output_compare.d
213		#define TOH     cpustate->timer_over.w.l
214		#define TOD     cpustate->timer_over.d
	129	#define CT      m_counter.w.l
	130	#define CTH     m_counter.w.h
	131	#define CTD     m_counter.d
	132	#define OC      m_output_compare.w.l
	133	#define OCH     m_output_compare.w.h
	134	#define OCD     m_output_compare.d
	135	#define TOH     m_timer_over.w.l
	136	#define TOD     m_timer_over.d
215	137
216		#define EAD     cpustate->ea.d
217		#define EA      cpustate->ea.w.l
	138	#define EAD     m_ea.d
	139	#define EA      m_ea.w.l
218	140
219	141	/* point of next timer event */
220	142	static UINT32 timer_next;
r24794	r24795
224	146	/****************************************************************************/
225	147	/* Read a byte from given memory location                                   */
226	148	/****************************************************************************/
227		#define RM(Addr) ((unsigned)cpustate->program->read_byte(Addr))
	149	#define RM(Addr) ((unsigned)m_program->read_byte(Addr))
228	150
229	151	/****************************************************************************/
230	152	/* Write a byte to given memory location                                    */
231	153	/****************************************************************************/
232		#define WM(Addr,Value) (cpustate->program->write_byte(Addr,Value))
	154	#define WM(Addr,Value) (m_program->write_byte(Addr,Value))
233	155
234	156	/****************************************************************************/
235	157	/* M6800_RDOP() is identical to M6800_RDMEM() except it is used for reading */
236	158	/* opcodes. In case of system with memory mapped I/O, this function can be  */
237	159	/* used to greatly speed up emulation                                       */
238	160	/****************************************************************************/
239		#define M_RDOP(Addr) ((unsigned)cpustate->direct->read_decrypted_byte(Addr))
	161	#define M_RDOP(Addr) ((unsigned)m_direct->read_decrypted_byte(Addr))
240	162
241	163	/****************************************************************************/
242	164	/* M6800_RDOP_ARG() is identical to M6800_RDOP() but it's used for reading  */
243	165	/* opcode arguments. This difference can be used to support systems that    */
244	166	/* use different encoding mechanisms for opcodes and opcode arguments       */
245	167	/****************************************************************************/
246		#define M_RDOP_ARG(Addr) ((unsigned)cpustate->direct->read_raw_byte(Addr))
	168	#define M_RDOP_ARG(Addr) ((unsigned)m_direct->read_raw_byte(Addr))
247	169
248	170	/* macros to access memory */
249	171	#define IMMBYTE(b)  b = M_RDOP_ARG(PCD); PC++
r24794	r24795
255	177	#define PULLWORD(w) S++; w.d = RM(SD)<<8; S++; w.d |= RM(SD)
256	178
257	179	#define MODIFIED_tcsr { \
258		cpustate->irq2 = (cpustate->tcsr&(cpustate->tcsr<<3))&(TCSR_ICF|TCSR_OCF|TCSR_TOF); \
	180	m_irq2 = (m_tcsr&(m_tcsr<<3))&(TCSR_ICF|TCSR_OCF|TCSR_TOF); \
259	181	}
260	182
261	183	#define SET_TIMER_EVENT {                   \
r24794	r24795
352	274	};
353	275
354	276	/* take interrupt */
355		#define TAKE_ICI enter_interrupt(cpustate, "M6800 '%s' take ICI\n",0xfff6)
356		#define TAKE_OCI enter_interrupt(cpustate, "M6800 '%s' take OCI\n",0xfff4)
357		#define TAKE_TOI enter_interrupt(cpustate, "M6800 '%s' take TOI\n",0xfff2)
358		#define TAKE_SCI enter_interrupt(cpustate, "M6800 '%s' take SCI\n",0xfff0)
359		#define TAKE_TRAP enter_interrupt(cpustate, "M6800 '%s' take TRAP\n",0xffee)
	277	#define TAKE_ICI enter_interrupt("M6800 '%s' take ICI\n",0xfff6)
	278	#define TAKE_OCI enter_interrupt("M6800 '%s' take OCI\n",0xfff4)
	279	#define TAKE_TOI enter_interrupt("M6800 '%s' take TOI\n",0xfff2)
	280	#define TAKE_SCI enter_interrupt("M6800 '%s' take SCI\n",0xfff0)
	281	#define TAKE_TRAP enter_interrupt("M6800 '%s' take TRAP\n",0xffee)
360	282
361	283	/* operate one instruction for */
362	284	#define ONE_MORE_INSN() {       \
363	285	UINT8 ireg;                             \
364	286	pPPC = pPC;                             \
365		debugger_instruction_hook(cpustate->device, PCD);                       \
	287	debugger_instruction_hook(this, PCD);                       \
366	288	ireg=M_RDOP(PCD);                       \
367	289	PC++;                                   \
368		(*cpustate->insn[ireg])(cpustate);                  \
369		increment_counter(cpustate, cpustate->cycles[ireg]);    \
	290	(this->*m_insn[ireg])();               \
	291	increment_counter(m_cycles[ireg]);    \
370	292	}
371	293
372	294	/* CC masks                       HI NZVC
r24794	r24795
392	314	#define SET_V8(a,b,r)   CC|=((((a)^(b)^(r)^((r)>>1))&0x80)>>6)
393	315	#define SET_V16(a,b,r)  CC|=((((a)^(b)^(r)^((r)>>1))&0x8000)>>14)
394	316
395		static const UINT8 flags8i[256]=     /* increment */
	317	const UINT8 m6800_cpu_device::flags8i[256]=     /* increment */
396	318	{
397	319	0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
398	320	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
r24794	r24795
411	333	0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
412	334	0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08
413	335	};
414		static const UINT8 flags8d[256]= /* decrement */
	336
	337
	338	const UINT8 m6800_cpu_device::flags8d[256]= /* decrement */
415	339	{
416	340	0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
417	341	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
r24794	r24795
430	354	0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
431	355	0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08
432	356	};
	357
433	358	#define SET_FLAGS8I(a)      {CC|=flags8i[(a)&0xff];}
434	359	#define SET_FLAGS8D(a)      {CC|=flags8d[(a)&0xff];}
435	360
r24794	r24795
446	371	#define DIRECT IMMBYTE(EAD)
447	372	#define IMM8 EA=PC++
448	373	#define IMM16 {EA=PC;PC+=2;}
449		#define EXTENDED IMMWORD(cpustate->ea)
	374	#define EXTENDED IMMWORD(m_ea)
450	375	#define INDEXED {EA=X+(UINT8)M_RDOP_ARG(PCD);PC++;}
451	376
452	377	/* macros to set status flags */
r24794	r24795
478	403
479	404	/* macros for convenience */
480	405	#define DIRBYTE(b) {DIRECT;b=RM(EAD);}
481		#define DIRWORD(w) {DIRECT;w.d=RM16(cpustate, EAD);}
	406	#define DIRWORD(w) {DIRECT;w.d=RM16(EAD);}
482	407	#define EXTBYTE(b) {EXTENDED;b=RM(EAD);}
483		#define EXTWORD(w) {EXTENDED;w.d=RM16(cpustate, EAD);}
	408	#define EXTWORD(w) {EXTENDED;w.d=RM16(EAD);}
484	409
485	410	#define IDXBYTE(b) {INDEXED;b=RM(EAD);}
486		#define IDXWORD(w) {INDEXED;w.d=RM16(cpustate, EAD);}
	411	#define IDXWORD(w) {INDEXED;w.d=RM16(EAD);}
487	412
488	413	/* Macros for branch instructions */
489	414	#define BRANCH(f) {IMMBYTE(t);if(f){PC+=SIGNED(t);}}
r24794	r24795
495	420	/* Note: don't use 0 cycles here for invalid opcodes so that we don't */
496	421	/* hang in an infinite loop if we hit one */
497	422	#define XX 5 // invalid opcode unknown cc
498		static const UINT8 cycles_6800[] =
	423	const UINT8 m6800_cpu_device::cycles_6800[256] =
499	424	{
500	425	/* 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F */
501	426	/*0*/ XX, 2,XX,XX,XX,XX, 2, 2, 4, 4, 2, 2, 2, 2, 2, 2,
r24794	r24795
516	441	/*F*/  4, 4, 4,XX, 4, 4, 4, 5, 4, 4, 4, 4,XX,XX, 5, 6
517	442	};
518	443
519		static const UINT8 cycles_6803[] =
	444	const UINT8 m6800_cpu_device::cycles_6803[256] =
520	445	{
521	446	/* 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F */
522	447	/*0*/ XX, 2,XX,XX, 3, 3, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2,
r24794	r24795
537	462	/*F*/  4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5
538	463	};
539	464
540		static const UINT8 cycles_63701[] =
	465	const UINT8 m6800_cpu_device::cycles_63701[256] =
541	466	{
542	467	/* 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F */
543	468	/*0*/ XX, 1,XX,XX, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
r24794	r24795
558	483	/*F*/  4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5
559	484	};
560	485
561		static const UINT8 cycles_nsc8105[] =
	486	const UINT8 m6800_cpu_device::cycles_nsc8105[256] =
562	487	{
563	488	/* 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F */
564	489	/*0*/ XX,XX, 2,XX,XX, 2,XX, 2, 4, 2, 4, 2, 2, 2, 2, 2,
r24794	r24795
585	510	int cycles_to_eat;                                              \
586	511	\
587	512	cycles_to_eat = timer_next - CTD;                               \
588		if( cycles_to_eat > cpustate->icount) cycles_to_eat = cpustate->icount; \
	513	if( cycles_to_eat > m_icount) cycles_to_eat = m_icount; \
589	514	if (cycles_to_eat > 0)                                          \
590	515	{                                                               \
591		increment_counter(cpustate, cycles_to_eat);                         \
	516	increment_counter(cycles_to_eat);                         \
592	517	}                                                               \
593	518	}
594	519
595		INLINE UINT32 RM16(m6800_state *cpustate, UINT32 Addr )
	520
	521	const device_type M6800 = &device_creator<m6800_cpu_device>;
	522	const device_type M6801 = &device_creator<m6801_cpu_device>;
	523	const device_type M6802 = &device_creator<m6802_cpu_device>;
	524	const device_type M6803 = &device_creator<m6803_cpu_device>;
	525	const device_type M6808 = &device_creator<m6808_cpu_device>;
	526	const device_type HD6301 = &device_creator<hd6301_cpu_device>;
	527	const device_type HD63701 = &device_creator<hd63701_cpu_device>;
	528	const device_type NSC8105 = &device_creator<nsc8105_cpu_device>;
	529	const device_type HD6303R = &device_creator<hd6303r_cpu_device>;
	530	const device_type HD6303Y = &device_creator<hd6303y_cpu_device>;
	531
	532
	533	m6800_cpu_device::m6800_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	534	: cpu_device(mconfig, M6800, "M6800", tag, owner, clock, "m6800", __FILE__)
	535	, m_program_config("program", ENDIANNESS_BIG, 8, 16, 0)
	536	, m_io_config("io", ENDIANNESS_BIG, 8, 9, 0)
	537	, m_has_io(false)
	538	, m_out_sc2_func(*this)
	539	, m_insn(m6800_insn)
	540	, m_cycles(cycles_6800)
596	541	{
	542	m_clock_divider = 1;
	543	}
	544
	545	m6800_cpu_device::m6800_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, bool has_io, int clock_divider, const op_func *insn, const UINT8 *cycles, address_map_constructor internal)
	546	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
	547	, m_program_config("program", ENDIANNESS_BIG, 8, 16, 0, internal)
	548	, m_io_config("io", ENDIANNESS_BIG, 8, 9, 0)
	549	, m_has_io(has_io)
	550	, m_out_sc2_func(*this)
	551	, m_insn(insn)
	552	, m_cycles(cycles)
	553	{
	554	m_clock_divider = clock_divider;
	555	}
	556
	557	m6801_cpu_device::m6801_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	558	: m6800_cpu_device(mconfig, M6801, "M6801", tag, owner, clock, "m6801", __FILE__, true, 4, m6803_insn, cycles_6803)
	559	{
	560	}
	561
	562	m6801_cpu_device::m6801_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, const op_func *insn, const UINT8 *cycles, address_map_constructor internal)
	563	: m6800_cpu_device(mconfig, type, name, tag, owner, clock, shortname, source, true, 4, insn, cycles, internal)
	564	{
	565	}
	566
	567	m6802_cpu_device::m6802_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	568	: m6800_cpu_device(mconfig, M6802, "M6802", tag, owner, clock, "m6802", __FILE__, false, 4, m6800_insn, cycles_6800)
	569	{
	570	}
	571
	572	m6802_cpu_device::m6802_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, const op_func *insn, const UINT8 *cycles)
	573	: m6800_cpu_device(mconfig, type, name, tag, owner, clock, shortname, source, false, 4, insn, cycles)
	574	{
	575	}
	576
	577	static ADDRESS_MAP_START(m6803_mem, AS_PROGRAM, 8, m6800_cpu_device)
	578	AM_RANGE(0x0000, 0x001f) AM_READWRITE(m6801_io_r, m6801_io_w)
	579	AM_RANGE(0x0020, 0x007f) AM_NOP        /* unused */
	580	AM_RANGE(0x0080, 0x00ff) AM_RAM        /* 6803 internal RAM */
	581	ADDRESS_MAP_END
	582
	583
	584	m6803_cpu_device::m6803_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	585	: m6801_cpu_device(mconfig, M6803, "M6803", tag, owner, clock, "m6803", __FILE__, m6803_insn, cycles_6803, ADDRESS_MAP_NAME(m6803_mem))
	586	{
	587	}
	588
	589	m6808_cpu_device::m6808_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	590	: m6802_cpu_device(mconfig, M6808, "M6808", tag, owner, clock, "m6808", __FILE__, m6800_insn, cycles_6800)
	591	{
	592	}
	593
	594	hd6301_cpu_device::hd6301_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	595	: m6801_cpu_device(mconfig, HD6301, "HD6301", tag, owner, clock, "hd6301", __FILE__, hd63701_insn, cycles_63701)
	596	{
	597	}
	598
	599	hd6301_cpu_device::hd6301_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
	600	: m6801_cpu_device(mconfig, type, name, tag, owner, clock, shortname, source, hd63701_insn, cycles_63701)
	601	{
	602	}
	603
	604	hd63701_cpu_device::hd63701_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	605	: m6801_cpu_device(mconfig, HD63701, "HD63701", tag, owner, clock, "hd63701", __FILE__, hd63701_insn, cycles_63701)
	606	{
	607	}
	608
	609	nsc8105_cpu_device::nsc8105_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	610	: m6802_cpu_device(mconfig, NSC8105, "NSC8105", tag, owner, clock, "nsc8105", __FILE__, nsc8105_insn, cycles_nsc8105)
	611	{
	612	}
	613
	614	hd6303r_cpu_device::hd6303r_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	615	: hd6301_cpu_device(mconfig, HD6303R, "HD6303R", tag, owner, clock, "hd6303r", __FILE__)
	616	{
	617	}
	618
	619	hd6303y_cpu_device::hd6303y_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	620	: hd6301_cpu_device(mconfig, HD6303Y, "HD6303Y", tag, owner, clock, "hd6303y", __FILE__)
	621	{
	622	}
	623
	624
	625	UINT32 m6800_cpu_device::RM16(UINT32 Addr )
	626	{
597	627	UINT32 result = RM(Addr) << 8;
598	628	return result | RM((Addr+1)&0xffff);
599	629	}
600	630
601		INLINE void WM16(m6800_state *cpustate, UINT32 Addr, PAIR *p )
	631	void m6800_cpu_device::WM16(UINT32 Addr, PAIR *p )
602	632	{
603	633	WM( Addr, p->b.h );
604	634	WM( (Addr+1)&0xffff, p->b.l );
605	635	}
606	636
607	637	/* IRQ enter */
608		static void enter_interrupt(m6800_state *cpustate, const char *message,UINT16 irq_vector)
	638	void m6800_cpu_device::enter_interrupt(const char *message,UINT16 irq_vector)
609	639	{
610		LOG((message, cpustate->device->tag()));
611		if( cpustate->wai_state & (M6800_WAI|M6800_SLP) )
	640	LOG((message, tag()));
	641	if( m_wai_state & (M6800_WAI|M6800_SLP) )
612	642	{
613		if( cpustate->wai_state & M6800_WAI )
614		cpustate->icount -= 4;
615		cpustate->wai_state &= ~(M6800_WAI|M6800_SLP);
	643	if( m_wai_state & M6800_WAI )
	644	m_icount -= 4;
	645	m_wai_state &= ~(M6800_WAI|M6800_SLP);
616	646	}
617	647	else
618	648	{
r24794	r24795
621	651	PUSHBYTE(A);
622	652	PUSHBYTE(B);
623	653	PUSHBYTE(CC);
624		cpustate->icount -= 12;
	654	m_icount -= 12;
625	655	}
626	656	SEI;
627		PCD = RM16(cpustate, irq_vector );
	657	PCD = RM16( irq_vector );
628	658	}
629	659
630	660
631	661
632		static void m6800_check_irq2(m6800_state *cpustate)
	662	void m6800_cpu_device::m6800_check_irq2()
633	663	{
634		if ((cpustate->tcsr & (TCSR_EICI|TCSR_ICF)) == (TCSR_EICI|TCSR_ICF))
	664	if ((m_tcsr & (TCSR_EICI|TCSR_ICF)) == (TCSR_EICI|TCSR_ICF))
635	665	{
636	666	TAKE_ICI;
637		if( cpustate->irq_callback )
638		(void)(*cpustate->irq_callback)(cpustate->device, M6801_TIN_LINE);
	667	standard_irq_callback(M6801_TIN_LINE);
639	668	}
640		else if ((cpustate->tcsr & (TCSR_EOCI|TCSR_OCF)) == (TCSR_EOCI|TCSR_OCF))
	669	else if ((m_tcsr & (TCSR_EOCI|TCSR_OCF)) == (TCSR_EOCI|TCSR_OCF))
641	670	{
642	671	TAKE_OCI;
643	672	}
644		else if ((cpustate->tcsr & (TCSR_ETOI|TCSR_TOF)) == (TCSR_ETOI|TCSR_TOF))
	673	else if ((m_tcsr & (TCSR_ETOI|TCSR_TOF)) == (TCSR_ETOI|TCSR_TOF))
645	674	{
646	675	TAKE_TOI;
647	676	}
648		else if (((cpustate->trcsr & (M6800_TRCSR_RIE|M6800_TRCSR_RDRF)) == (M6800_TRCSR_RIE|M6800_TRCSR_RDRF)) ||
649		((cpustate->trcsr & (M6800_TRCSR_RIE|M6800_TRCSR_ORFE)) == (M6800_TRCSR_RIE|M6800_TRCSR_ORFE)) ||
650		((cpustate->trcsr & (M6800_TRCSR_TIE|M6800_TRCSR_TDRE)) == (M6800_TRCSR_TIE|M6800_TRCSR_TDRE)))
	677	else if (((m_trcsr & (M6800_TRCSR_RIE|M6800_TRCSR_RDRF)) == (M6800_TRCSR_RIE|M6800_TRCSR_RDRF)) ||
	678	((m_trcsr & (M6800_TRCSR_RIE|M6800_TRCSR_ORFE)) == (M6800_TRCSR_RIE|M6800_TRCSR_ORFE)) ||
	679	((m_trcsr & (M6800_TRCSR_TIE|M6800_TRCSR_TDRE)) == (M6800_TRCSR_TIE|M6800_TRCSR_TDRE)))
651	680	{
652		//logerror("M6800 '%s' SCI interrupt\n", cpustate->device->tag());
	681	//logerror("M6800 '%s' SCI interrupt\n", tag());
653	682	TAKE_SCI;
654	683	}
655	684	}
656	685
657	686
658	687	/* check the IRQ lines for pending interrupts */
659		INLINE void CHECK_IRQ_LINES(m6800_state *cpustate)
	688	void m6800_cpu_device::CHECK_IRQ_LINES()
660	689	{
661	690	// TODO: IS3 interrupt
662	691
663		if (cpustate->nmi_pending)
	692	if (m_nmi_pending)
664	693	{
665		if(cpustate->wai_state & M6800_SLP)
666		cpustate->wai_state &= ~M6800_SLP;
	694	if(m_wai_state & M6800_SLP)
	695	m_wai_state &= ~M6800_SLP;
667	696
668		cpustate->nmi_pending = FALSE;
669		enter_interrupt(cpustate, "M6800 '%s' take NMI\n",0xfffc);
	697	m_nmi_pending = FALSE;
	698	enter_interrupt("M6800 '%s' take NMI\n",0xfffc);
670	699	}
671	700	else
672	701	{
673		if( cpustate->irq_state[M6800_IRQ_LINE] != CLEAR_LINE )
	702	if( m_irq_state[M6800_IRQ_LINE] != CLEAR_LINE )
674	703	{   /* standard IRQ */
675		if(cpustate->wai_state & M6800_SLP)
676		cpustate->wai_state &= ~M6800_SLP;
	704	if(m_wai_state & M6800_SLP)
	705	m_wai_state &= ~M6800_SLP;
677	706
678	707	if( !(CC & 0x10) )
679	708	{
680		enter_interrupt(cpustate, "M6800 '%s' take IRQ1\n",0xfff8);
681		if( cpustate->irq_callback )
682		(void)(*cpustate->irq_callback)(cpustate->device, M6800_IRQ_LINE);
	709	enter_interrupt("M6800 '%s' take IRQ1\n",0xfff8);
	710	standard_irq_callback(M6800_IRQ_LINE);
683	711	}
684	712	}
685	713	else
686	714	if( !(CC & 0x10) )
687		m6800_check_irq2(cpustate);
	715	m6800_check_irq2();
688	716	}
689	717	}
690	718
691	719	/* check OCI or TOI */
692		static void check_timer_event(m6800_state *cpustate)
	720	void m6800_cpu_device::check_timer_event()
693	721	{
694	722	/* OCI */
695	723	if( CTD >= OCD)
696	724	{
697	725	OCH++;  // next IRQ point
698		cpustate->tcsr |= TCSR_OCF;
699		cpustate->pending_tcsr |= TCSR_OCF;
	726	m_tcsr |= TCSR_OCF;
	727	m_pending_tcsr |= TCSR_OCF;
700	728	MODIFIED_tcsr;
701		if((cpustate->tcsr & TCSR_EOCI) && cpustate->wai_state & M6800_SLP)
702		cpustate->wai_state &= ~M6800_SLP;
703		if ( !(CC & 0x10) && (cpustate->tcsr & TCSR_EOCI))
	729	if((m_tcsr & TCSR_EOCI) && m_wai_state & M6800_SLP)
	730	m_wai_state &= ~M6800_SLP;
	731	if ( !(CC & 0x10) && (m_tcsr & TCSR_EOCI))
704	732	TAKE_OCI;
705	733	}
706	734	/* TOI */
r24794	r24795
710	738	#if 0
711	739	CLEANUP_COUNTERS();
712	740	#endif
713		cpustate->tcsr |= TCSR_TOF;
714		cpustate->pending_tcsr |= TCSR_TOF;
	741	m_tcsr |= TCSR_TOF;
	742	m_pending_tcsr |= TCSR_TOF;
715	743	MODIFIED_tcsr;
716		if((cpustate->tcsr & TCSR_ETOI) && cpustate->wai_state & M6800_SLP)
717		cpustate->wai_state &= ~M6800_SLP;
718		if ( !(CC & 0x10) && (cpustate->tcsr & TCSR_ETOI))
	744	if((m_tcsr & TCSR_ETOI) && m_wai_state & M6800_SLP)
	745	m_wai_state &= ~M6800_SLP;
	746	if ( !(CC & 0x10) && (m_tcsr & TCSR_ETOI))
719	747	TAKE_TOI;
720	748	}
721	749	/* set next event */
722	750	SET_TIMER_EVENT;
723	751	}
724	752
725		INLINE void increment_counter(m6800_state *cpustate, int amount)
	753	void m6800_cpu_device::increment_counter(int amount)
726	754	{
727		cpustate->icount -= amount;
	755	m_icount -= amount;
728	756	CTD += amount;
729	757	if( CTD >= timer_next)
730		check_timer_event(cpustate);
	758	check_timer_event();
731	759	}
732	760
733		INLINE void set_rmcr(m6800_state *cpustate, UINT8 data)
	761	void m6800_cpu_device::set_rmcr(UINT8 data)
734	762	{
735		if (cpustate->rmcr == data) return;
	763	if (m_rmcr == data) return;
736	764
737		cpustate->rmcr = data;
	765	m_rmcr = data;
738	766
739		switch ((cpustate->rmcr & M6800_RMCR_CC_MASK) >> 2)
	767	switch ((m_rmcr & M6800_RMCR_CC_MASK) >> 2)
740	768	{
741	769	case 0:
742	770	case 3: // not implemented
743		cpustate->sci_timer->enable(false);
	771	m_sci_timer->enable(false);
744	772	break;
745	773
746	774	case 1:
747	775	case 2:
748	776	{
749		int divisor = M6800_RMCR_SS[cpustate->rmcr & M6800_RMCR_SS_MASK];
	777	int divisor = M6800_RMCR_SS[m_rmcr & M6800_RMCR_SS_MASK];
	778	int clock = m_clock / m_clock_divider;
750	779
751		cpustate->sci_timer->adjust(attotime::from_hz(cpustate->clock / divisor), 0, attotime::from_hz(cpustate->clock / divisor));
	780	m_sci_timer->adjust(attotime::from_hz(clock / divisor), 0, attotime::from_hz(clock / divisor));
752	781	}
753	782	break;
754	783	}
755	784	}
756	785
757		INLINE void write_port2(m6800_state *cpustate)
	786	void m6800_cpu_device::write_port2()
758	787	{
759		if (!cpustate->port2_written) return;
	788	if (!m_port2_written) return;
760	789
761		UINT8 data = cpustate->port2_data;
762		UINT8 ddr = cpustate->port2_ddr & 0x1f;
	790	UINT8 data = m_port2_data;
	791	UINT8 ddr = m_port2_ddr & 0x1f;
763	792
764	793	if ((ddr != 0x1f) && ddr)
765	794	{
766		data = (cpustate->port2_data & ddr) | (ddr ^ 0xff);
	795	data = (m_port2_data & ddr) | (ddr ^ 0xff);
767	796	}
768	797
769		if (cpustate->trcsr & M6800_TRCSR_TE)
	798	if (m_trcsr & M6800_TRCSR_TE)
770	799	{
771		data = (data & 0xef) | (cpustate->tx << 4);
	800	data = (data & 0xef) | (m_tx << 4);
772	801	}
773	802
774	803	data &= 0x1f;
775	804
776		cpustate->io->write_byte(M6801_PORT2, data);
	805	m_io->write_byte(M6801_PORT2, data);
777	806	}
778	807
779	808	/* include the opcode prototypes and function pointer tables */
r24794	r24795
782	811	/* include the opcode functions */
783	812	#include "6800ops.c"
784	813
785		static int m6800_rx(m6800_state *cpustate)
	814	int m6800_cpu_device::m6800_rx()
786	815	{
787		return (cpustate->io->read_byte(M6801_PORT2) & M6800_PORT2_IO3) >> 3;
	816	return (m_io->read_byte(M6801_PORT2) & M6800_PORT2_IO3) >> 3;
788	817	}
789	818
790		static void serial_transmit(m6800_state *cpustate)
	819	void m6800_cpu_device::serial_transmit()
791	820	{
792		//logerror("M6800 '%s' Tx Tick\n", cpustate->device->tag());
	821	//logerror("M6800 '%s' Tx Tick\n", tag());
793	822
794		if (cpustate->trcsr & M6800_TRCSR_TE)
	823	if (m_trcsr & M6800_TRCSR_TE)
795	824	{
796	825	// force Port 2 bit 4 as output
797		cpustate->port2_ddr |= M6800_PORT2_IO4;
	826	m_port2_ddr |= M6800_PORT2_IO4;
798	827
799		switch (cpustate->txstate)
	828	switch (m_txstate)
800	829	{
801	830	case M6800_TX_STATE_INIT:
802		cpustate->tx = 1;
803		cpustate->txbits++;
	831	m_tx = 1;
	832	m_txbits++;
804	833
805		if (cpustate->txbits == 10)
	834	if (m_txbits == 10)
806	835	{
807		cpustate->txstate = M6800_TX_STATE_READY;
808		cpustate->txbits = M6800_SERIAL_START;
	836	m_txstate = M6800_TX_STATE_READY;
	837	m_txbits = M6800_SERIAL_START;
809	838	}
810	839	break;
811	840
812	841	case M6800_TX_STATE_READY:
813		switch (cpustate->txbits)
	842	switch (m_txbits)
814	843	{
815	844	case M6800_SERIAL_START:
816		if (cpustate->trcsr & M6800_TRCSR_TDRE)
	845	if (m_trcsr & M6800_TRCSR_TDRE)
817	846	{
818	847	// transmit buffer is empty, send consecutive '1's
819		cpustate->tx = 1;
	848	m_tx = 1;
820	849	}
821	850	else
822	851	{
823	852	// transmit buffer is full, send data
824	853
825	854	// load TDR to shift register
826		cpustate->tsr = cpustate->tdr;
	855	m_tsr = m_tdr;
827	856
828	857	// transmit buffer is empty, set TDRE flag
829		cpustate->trcsr |= M6800_TRCSR_TDRE;
	858	m_trcsr |= M6800_TRCSR_TDRE;
830	859
831	860	// send start bit '0'
832		cpustate->tx = 0;
	861	m_tx = 0;
833	862
834		cpustate->txbits++;
	863	m_txbits++;
835	864
836		//logerror("M6800 '%s' Transmit START Data %02x\n", cpustate->device->tag(), cpustate->tsr);
	865	//logerror("M6800 '%s' Transmit START Data %02x\n", tag(), m_tsr);
837	866	}
838	867	break;
839	868
840	869	case M6800_SERIAL_STOP:
841	870	// send stop bit '1'
842		cpustate->tx = 1;
	871	m_tx = 1;
843	872
844		CHECK_IRQ_LINES(cpustate);
	873	CHECK_IRQ_LINES();
845	874
846		cpustate->txbits = M6800_SERIAL_START;
	875	m_txbits = M6800_SERIAL_START;
847	876
848		//logerror("M6800 '%s' Transmit STOP\n", cpustate->device->tag());
	877	//logerror("M6800 '%s' Transmit STOP\n", tag());
849	878	break;
850	879
851	880	default:
852	881	// send data bit '0' or '1'
853		cpustate->tx = cpustate->tsr & 0x01;
	882	m_tx = m_tsr & 0x01;
854	883
855	884	// shift transmit register
856		cpustate->tsr >>= 1;
	885	m_tsr >>= 1;
857	886
858		//logerror("M6800 '%s' Transmit Bit %u: %u\n", cpustate->device->tag(), cpustate->txbits, cpustate->tx);
	887	//logerror("M6800 '%s' Transmit Bit %u: %u\n", tag(), m_txbits, m_tx);
859	888
860		cpustate->txbits++;
	889	m_txbits++;
861	890	break;
862	891	}
863	892	break;
864	893	}
865	894
866		cpustate->port2_written = 1;
867		write_port2(cpustate);
	895	m_port2_written = 1;
	896	write_port2();
868	897	}
869	898	}
870	899
871		static void serial_receive(m6800_state *cpustate)
	900	void m6800_cpu_device::serial_receive()
872	901	{
873		//logerror("M6800 '%s' Rx Tick TRCSR %02x bits %u check %02x\n", cpustate->device->tag(), cpustate->trcsr, cpustate->rxbits, cpustate->trcsr & M6800_TRCSR_RE);
	902	//logerror("M6800 '%s' Rx Tick TRCSR %02x bits %u check %02x\n", tag(), m_trcsr, m_rxbits, m_trcsr & M6800_TRCSR_RE);
874	903
875		if (cpustate->trcsr & M6800_TRCSR_RE)
	904	if (m_trcsr & M6800_TRCSR_RE)
876	905	{
877		if (cpustate->trcsr & M6800_TRCSR_WU)
	906	if (m_trcsr & M6800_TRCSR_WU)
878	907	{
879	908	// wait for 10 bits of '1'
880		if (m6800_rx(cpustate) == 1)
	909	if (m6800_rx() == 1)
881	910	{
882		cpustate->rxbits++;
	911	m_rxbits++;
883	912
884		//logerror("M6800 '%s' Received WAKE UP bit %u\n", cpustate->device->tag(), cpustate->rxbits);
	913	//logerror("M6800 '%s' Received WAKE UP bit %u\n", tag(), m_rxbits);
885	914
886		if (cpustate->rxbits == 10)
	915	if (m_rxbits == 10)
887	916	{
888		//logerror("M6800 '%s' Receiver Wake Up\n", cpustate->device->tag());
	917	//logerror("M6800 '%s' Receiver Wake Up\n", tag());
889	918
890		cpustate->trcsr &= ~M6800_TRCSR_WU;
891		cpustate->rxbits = M6800_SERIAL_START;
	919	m_trcsr &= ~M6800_TRCSR_WU;
	920	m_rxbits = M6800_SERIAL_START;
892	921	}
893	922	}
894	923	else
895	924	{
896		//logerror("M6800 '%s' Receiver Wake Up interrupted\n", cpustate->device->tag());
	925	//logerror("M6800 '%s' Receiver Wake Up interrupted\n", tag());
897	926
898		cpustate->rxbits = M6800_SERIAL_START;
	927	m_rxbits = M6800_SERIAL_START;
899	928	}
900	929	}
901	930	else
902	931	{
903	932	// receive data
904		switch (cpustate->rxbits)
	933	switch (m_rxbits)
905	934	{
906	935	case M6800_SERIAL_START:
907		if (m6800_rx(cpustate) == 0)
	936	if (m6800_rx() == 0)
908	937	{
909	938	// start bit found
910		cpustate->rxbits++;
	939	m_rxbits++;
911	940
912		//logerror("M6800 '%s' Received START bit\n", cpustate->device->tag());
	941	//logerror("M6800 '%s' Received START bit\n", tag());
913	942	}
914	943	break;
915	944
916	945	case M6800_SERIAL_STOP:
917		if (m6800_rx(cpustate) == 1)
	946	if (m6800_rx() == 1)
918	947	{
919		//logerror("M6800 '%s' Received STOP bit\n", cpustate->device->tag());
	948	//logerror("M6800 '%s' Received STOP bit\n", tag());
920	949
921		if (cpustate->trcsr & M6800_TRCSR_RDRF)
	950	if (m_trcsr & M6800_TRCSR_RDRF)
922	951	{
923	952	// overrun error
924		cpustate->trcsr |= M6800_TRCSR_ORFE;
	953	m_trcsr |= M6800_TRCSR_ORFE;
925	954
926		//logerror("M6800 '%s' Receive Overrun Error\n", cpustate->device->tag());
	955	//logerror("M6800 '%s' Receive Overrun Error\n", tag());
927	956
928		CHECK_IRQ_LINES(cpustate);
	957	CHECK_IRQ_LINES();
929	958	}
930	959	else
931	960	{
932		if (!(cpustate->trcsr & M6800_TRCSR_ORFE))
	961	if (!(m_trcsr & M6800_TRCSR_ORFE))
933	962	{
934	963	// transfer data into receive register
935		cpustate->rdr = cpustate->rsr;
	964	m_rdr = m_rsr;
936	965
937		//logerror("M6800 '%s' Receive Data Register: %02x\n", cpustate->device->tag(), cpustate->rdr);
	966	//logerror("M6800 '%s' Receive Data Register: %02x\n", tag(), m_rdr);
938	967
939	968	// set RDRF flag
940		cpustate->trcsr |= M6800_TRCSR_RDRF;
	969	m_trcsr |= M6800_TRCSR_RDRF;
941	970
942		CHECK_IRQ_LINES(cpustate);
	971	CHECK_IRQ_LINES();
943	972	}
944	973	}
945	974	}
946	975	else
947	976	{
948	977	// framing error
949		if (!(cpustate->trcsr & M6800_TRCSR_ORFE))
	978	if (!(m_trcsr & M6800_TRCSR_ORFE))
950	979	{
951	980	// transfer unframed data into receive register
952		cpustate->rdr = cpustate->rsr;
	981	m_rdr = m_rsr;
953	982	}
954	983
955		cpustate->trcsr |= M6800_TRCSR_ORFE;
956		cpustate->trcsr &= ~M6800_TRCSR_RDRF;
	984	m_trcsr |= M6800_TRCSR_ORFE;
	985	m_trcsr &= ~M6800_TRCSR_RDRF;
957	986
958		//logerror("M6800 '%s' Receive Framing Error\n", cpustate->device->tag());
	987	//logerror("M6800 '%s' Receive Framing Error\n", tag());
959	988
960		CHECK_IRQ_LINES(cpustate);
	989	CHECK_IRQ_LINES();
961	990	}
962	991
963		cpustate->rxbits = M6800_SERIAL_START;
	992	m_rxbits = M6800_SERIAL_START;
964	993	break;
965	994
966	995	default:
967	996	// shift receive register
968		cpustate->rsr >>= 1;
	997	m_rsr >>= 1;
969	998
970	999	// receive bit into register
971		cpustate->rsr |= (m6800_rx(cpustate) << 7);
	1000	m_rsr |= (m6800_rx() << 7);
972	1001
973		//logerror("M6800 '%s' Received DATA bit %u: %u\n", cpustate->device->tag(), cpustate->rxbits, BIT(cpustate->rsr, 7));
	1002	//logerror("M6800 '%s' Received DATA bit %u: %u\n", tag(), m_rxbits, BIT(m_rsr, 7));
974	1003
975		cpustate->rxbits++;
	1004	m_rxbits++;
976	1005	break;
977	1006	}
978	1007	}
979	1008	}
980	1009	}
981	1010
982		static TIMER_CALLBACK( sci_tick )
	1011	TIMER_CALLBACK_MEMBER( m6800_cpu_device::sci_tick )
983	1012	{
984		m6800_state *cpustate = (m6800_state *)ptr;
985
986		serial_transmit(cpustate);
987		serial_receive(cpustate);
	1013	serial_transmit();
	1014	serial_receive();
988	1015	}
989	1016
990		/****************************************************************************
991		* Reset registers to their initial values
992		****************************************************************************/
993		static void state_register(m6800_state *cpustate, const char *type)
	1017
	1018	void m6800_cpu_device::device_start()
994	1019	{
995		cpustate->device->save_item(NAME(cpustate->ppc.w.l));
996		cpustate->device->save_item(NAME(cpustate->pc.w.l));
997		cpustate->device->save_item(NAME(cpustate->s.w.l));
998		cpustate->device->save_item(NAME(cpustate->x.w.l));
999		cpustate->device->save_item(NAME(cpustate->d.w.l));
1000		cpustate->device->save_item(NAME(cpustate->cc));
1001		cpustate->device->save_item(NAME(cpustate->wai_state));
1002		cpustate->device->save_item(NAME(cpustate->nmi_state));
1003		cpustate->device->save_item(NAME(cpustate->nmi_pending));
1004		cpustate->device->save_item(NAME(cpustate->irq_state));
1005		cpustate->device->save_item(NAME(cpustate->ic_eddge));
	1020	m_program = &space(AS_PROGRAM);
	1021	m_direct = &m_program->direct();
	1022	if ( m_has_io )
	1023	m_io = &space(AS_IO);
1006	1024
1007		cpustate->device->save_item(NAME(cpustate->port1_ddr));
1008		cpustate->device->save_item(NAME(cpustate->port2_ddr));
1009		cpustate->device->save_item(NAME(cpustate->port3_ddr));
1010		cpustate->device->save_item(NAME(cpustate->port4_ddr));
1011		cpustate->device->save_item(NAME(cpustate->port1_data));
1012		cpustate->device->save_item(NAME(cpustate->port2_data));
1013		cpustate->device->save_item(NAME(cpustate->port3_data));
1014		cpustate->device->save_item(NAME(cpustate->port4_data));
1015		cpustate->device->save_item(NAME(cpustate->port2_written));
1016		cpustate->device->save_item(NAME(cpustate->port3_latched));
1017		cpustate->device->save_item(NAME(cpustate->p3csr));
1018		cpustate->device->save_item(NAME(cpustate->p3csr_is3_flag_read));
1019		cpustate->device->save_item(NAME(cpustate->tcsr));
1020		cpustate->device->save_item(NAME(cpustate->pending_tcsr));
1021		cpustate->device->save_item(NAME(cpustate->irq2));
1022		cpustate->device->save_item(NAME(cpustate->ram_ctrl));
	1025	m_out_sc2_func.resolve_safe();
	1026	m_sci_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(m6800_cpu_device::sci_tick),this));
1023	1027
1024		cpustate->device->save_item(NAME(cpustate->counter.d));
1025		cpustate->device->save_item(NAME(cpustate->output_compare.d));
1026		cpustate->device->save_item(NAME(cpustate->input_capture));
1027		cpustate->device->save_item(NAME(cpustate->timer_over.d));
	1028	save_item(NAME(m_ppc.w.l));
	1029	save_item(NAME(m_pc.w.l));
	1030	save_item(NAME(m_s.w.l));
	1031	save_item(NAME(m_x.w.l));
	1032	save_item(NAME(m_d.w.l));
	1033	save_item(NAME(m_cc));
	1034	save_item(NAME(m_wai_state));
	1035	save_item(NAME(m_nmi_state));
	1036	save_item(NAME(m_nmi_pending));
	1037	save_item(NAME(m_irq_state));
	1038	save_item(NAME(m_ic_eddge));
1028	1039
1029		cpustate->device->save_item(NAME(cpustate->clock));
1030		cpustate->device->save_item(NAME(cpustate->trcsr));
1031		cpustate->device->save_item(NAME(cpustate->rmcr));
1032		cpustate->device->save_item(NAME(cpustate->rdr));
1033		cpustate->device->save_item(NAME(cpustate->tdr));
1034		cpustate->device->save_item(NAME(cpustate->rsr));
1035		cpustate->device->save_item(NAME(cpustate->tsr));
1036		cpustate->device->save_item(NAME(cpustate->rxbits));
1037		cpustate->device->save_item(NAME(cpustate->txbits));
1038		cpustate->device->save_item(NAME(cpustate->txstate));
1039		cpustate->device->save_item(NAME(cpustate->trcsr_read_tdre));
1040		cpustate->device->save_item(NAME(cpustate->trcsr_read_orfe));
1041		cpustate->device->save_item(NAME(cpustate->trcsr_read_rdrf));
1042		cpustate->device->save_item(NAME(cpustate->tx));
1043		}
	1040	save_item(NAME(m_port1_ddr));
	1041	save_item(NAME(m_port2_ddr));
	1042	save_item(NAME(m_port3_ddr));
	1043	save_item(NAME(m_port4_ddr));
	1044	save_item(NAME(m_port1_data));
	1045	save_item(NAME(m_port2_data));
	1046	save_item(NAME(m_port3_data));
	1047	save_item(NAME(m_port4_data));
	1048	save_item(NAME(m_port2_written));
	1049	save_item(NAME(m_port3_latched));
	1050	save_item(NAME(m_p3csr));
	1051	save_item(NAME(m_p3csr_is3_flag_read));
	1052	save_item(NAME(m_tcsr));
	1053	save_item(NAME(m_pending_tcsr));
	1054	save_item(NAME(m_irq2));
	1055	save_item(NAME(m_ram_ctrl));
1044	1056
1045		static CPU_INIT( m6800 )
1046		{
1047		m6800_state *cpustate = get_safe_token(device);
	1057	save_item(NAME(m_counter.d));
	1058	save_item(NAME(m_output_compare.d));
	1059	save_item(NAME(m_input_capture));
	1060	save_item(NAME(m_timer_over.d));
1048	1061
1049		cpustate->program = &device->space(AS_PROGRAM);
1050		cpustate->direct = &cpustate->program->direct();
1051		//cpustate->data = &device->space(AS_DATA);
1052		//cpustate->io = &device->space(AS_IO);
	1062	save_item(NAME(m_clock_divider));
	1063	save_item(NAME(m_trcsr));
	1064	save_item(NAME(m_rmcr));
	1065	save_item(NAME(m_rdr));
	1066	save_item(NAME(m_tdr));
	1067	save_item(NAME(m_rsr));
	1068	save_item(NAME(m_tsr));
	1069	save_item(NAME(m_rxbits));
	1070	save_item(NAME(m_txbits));
	1071	save_item(NAME(m_txstate));
	1072	save_item(NAME(m_trcsr_read_tdre));
	1073	save_item(NAME(m_trcsr_read_orfe));
	1074	save_item(NAME(m_trcsr_read_rdrf));
	1075	save_item(NAME(m_tx));
1053	1076
1054		//  cpustate->subtype   = SUBTYPE_M6800;
1055		cpustate->insn = m6800_insn;
1056		cpustate->cycles = cycles_6800;
1057		cpustate->irq_callback = irqcallback;
1058		cpustate->device = device;
1059		state_register(cpustate, "m6800");
	1077	state_add( M6800_A,         "A", m_d.b.h).formatstr("%02X");
	1078	state_add( M6800_B,         "B", m_d.b.l).formatstr("%02X");
	1079	state_add( M6800_PC,        "PC", m_pc.w.l).formatstr("%04X");
	1080	state_add( M6800_S,         "S", m_s.w.l).formatstr("%04X");
	1081	state_add( M6800_X,         "X", m_x.w.l).formatstr("%04X");
	1082	state_add( M6800_CC,        "CC", m_cc).formatstr("%02X");
	1083	state_add( M6800_WAI_STATE, "WAI", m_wai_state).formatstr("%01X");
	1084
	1085	state_add( STATE_GENPC, "GENPC", m_pc.w.l).noshow();
	1086	state_add( STATE_GENFLAGS, "GENFLAGS", m_cc).formatstr("%8s").noshow();
	1087
	1088	m_icountptr = &m_icount;
1060	1089	}
1061	1090
1062		static CPU_RESET( m6800 )
	1091	void m6800_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
1063	1092	{
1064		m6800_state *cpustate = get_safe_token(device);
	1093	switch (entry.index())
	1094	{
	1095	case STATE_GENFLAGS:
	1096	string.printf( "%c%c%c%c%c%c%c%c",
	1097	m_cc & 0x80 ? '?':'.',
	1098	m_cc & 0x40 ? '?':'.',
	1099	m_cc & 0x20 ? 'H':'.',
	1100	m_cc & 0x10 ? 'I':'.',
	1101	m_cc & 0x08 ? 'N':'.',
	1102	m_cc & 0x04 ? 'Z':'.',
	1103	m_cc & 0x02 ? 'V':'.',
	1104	m_cc & 0x01 ? 'C':'.');
	1105	break;
	1106	}
	1107	}
1065	1108
1066		cpustate->cc = 0xc0;
	1109	void m6800_cpu_device::device_reset()
	1110	{
	1111	m_cc = 0xc0;
1067	1112	SEI;                /* IRQ disabled */
1068		PCD = RM16(cpustate, 0xfffe );
	1113	PCD = RM16( 0xfffe );
1069	1114
1070		cpustate->wai_state = 0;
1071		cpustate->nmi_state = 0;
1072		cpustate->nmi_pending = 0;
1073		cpustate->sc1_state = 0;
1074		cpustate->irq_state[M6800_IRQ_LINE] = 0;
1075		cpustate->irq_state[M6801_TIN_LINE] = 0;
1076		cpustate->ic_eddge = 0;
	1115	m_wai_state = 0;
	1116	m_nmi_state = 0;
	1117	m_nmi_pending = 0;
	1118	m_sc1_state = 0;
	1119	m_irq_state[M6800_IRQ_LINE] = 0;
	1120	m_irq_state[M6801_TIN_LINE] = 0;
	1121	m_ic_eddge = 0;
1077	1122
1078		cpustate->port1_ddr = 0x00;
1079		cpustate->port2_ddr = 0x00;
1080		cpustate->port3_ddr = 0x00;
1081		cpustate->p3csr = 0x00;
1082		cpustate->p3csr_is3_flag_read = 0;
1083		cpustate->port2_written = 0;
1084		cpustate->port3_latched = 0;
	1123	m_port1_ddr = 0x00;
	1124	m_port2_ddr = 0x00;
	1125	m_port3_ddr = 0x00;
	1126	m_p3csr = 0x00;
	1127	m_p3csr_is3_flag_read = 0;
	1128	m_port2_written = 0;
	1129	m_port3_latched = 0;
1085	1130	/* TODO: on reset port 2 should be read to determine the operating mode (bits 0-2) */
1086		cpustate->tcsr = 0x00;
1087		cpustate->pending_tcsr = 0x00;
1088		cpustate->irq2 = 0;
	1131	m_tcsr = 0x00;
	1132	m_pending_tcsr = 0x00;
	1133	m_irq2 = 0;
1089	1134	CTD = 0x0000;
1090	1135	OCD = 0xffff;
1091	1136	TOD = 0xffff;
1092		cpustate->ram_ctrl |= 0x40;
	1137	m_ram_ctrl |= 0x40;
1093	1138
1094		cpustate->trcsr = M6800_TRCSR_TDRE;
	1139	m_trcsr = M6800_TRCSR_TDRE;
1095	1140
1096		cpustate->txstate = M6800_TX_STATE_INIT;
1097		cpustate->txbits = cpustate->rxbits = 0;
1098		cpustate->tx = 1;
1099		cpustate->trcsr_read_tdre = 0;
1100		cpustate->trcsr_read_orfe = 0;
1101		cpustate->trcsr_read_rdrf = 0;
	1141	m_txstate = M6800_TX_STATE_INIT;
	1142	m_txbits = m_rxbits = 0;
	1143	m_tx = 1;
	1144	m_trcsr_read_tdre = 0;
	1145	m_trcsr_read_orfe = 0;
	1146	m_trcsr_read_rdrf = 0;
1102	1147
1103		set_rmcr(cpustate, 0);
	1148	set_rmcr(0);
1104	1149	}
1105	1150
1106		/****************************************************************************
1107		* Shut down CPU emulation
1108		****************************************************************************/
1109		static CPU_EXIT( m6800 )
1110		{
1111		/* nothing to do */
1112		}
1113	1151
1114
1115		static void set_irq_line(m6800_state *cpustate, int irqline, int state)
	1152	void m6800_cpu_device::execute_set_input(int irqline, int state)
1116	1153	{
1117	1154	switch (irqline)
1118	1155	{
1119	1156	case INPUT_LINE_NMI:
1120		if (!cpustate->nmi_state && state != CLEAR_LINE)
1121		cpustate->nmi_pending = TRUE;
1122		cpustate->nmi_state = state;
	1157	if (!m_nmi_state && state != CLEAR_LINE)
	1158	m_nmi_pending = TRUE;
	1159	m_nmi_state = state;
1123	1160	break;
1124	1161
1125	1162	case M6801_SC1_LINE:
1126		if (!cpustate->port3_latched && (cpustate->p3csr & M6801_P3CSR_LE))
	1163	if (!m_port3_latched && (m_p3csr & M6801_P3CSR_LE))
1127	1164	{
1128		if (!cpustate->sc1_state && state)
	1165	if (!m_sc1_state && state)
1129	1166	{
1130	1167	// latch input data to port 3
1131		cpustate->port3_data = (cpustate->io->read_byte(M6801_PORT3) & (cpustate->port3_ddr ^ 0xff)) | (cpustate->port3_data & cpustate->port3_ddr);
1132		cpustate->port3_latched = 1;
1133		//logerror("M6801 '%s' Latched Port 3 Data: %02x\n", cpustate->device->tag(), cpustate->port3_data);
	1168	m_port3_data = (m_io->read_byte(M6801_PORT3) & (m_port3_ddr ^ 0xff)) | (m_port3_data & m_port3_ddr);
	1169	m_port3_latched = 1;
	1170	//logerror("M6801 '%s' Latched Port 3 Data: %02x\n", tag(), m_port3_data);
1134	1171
1135	1172	// set IS3 flag bit
1136		cpustate->p3csr |= M6801_P3CSR_IS3_FLAG;
	1173	m_p3csr |= M6801_P3CSR_IS3_FLAG;
1137	1174	}
1138	1175	}
1139		cpustate->sc1_state = state;
	1176	m_sc1_state = state;
1140	1177	break;
1141	1178
1142	1179	default:
1143		LOG(("M6800 '%s' set_irq_line %d,%d\n", cpustate->device->tag(), irqline, state));
1144		cpustate->irq_state[irqline] = state;
	1180	LOG(("M6800 '%s' set_irq_line %d,%d\n", tag(), irqline, state));
	1181	m_irq_state[irqline] = state;
1145	1182
1146		if (irqline == M6801_TIN_LINE && state != cpustate->irq_state[irqline])
	1183	if (irqline == M6801_TIN_LINE && state != m_irq_state[irqline])
1147	1184	{
1148	1185	//eddge = (state == CLEAR_LINE ) ? 2 : 0;
1149		if( ((cpustate->tcsr&TCSR_IEDG) ^ (state==CLEAR_LINE ? TCSR_IEDG : 0))==0 )
	1186	if( ((m_tcsr&TCSR_IEDG) ^ (state==CLEAR_LINE ? TCSR_IEDG : 0))==0 )
1150	1187	return;
1151	1188	/* active edge in */
1152		cpustate->tcsr |= TCSR_ICF;
1153		cpustate->pending_tcsr |= TCSR_ICF;
1154		cpustate->input_capture = CT;
	1189	m_tcsr |= TCSR_ICF;
	1190	m_pending_tcsr |= TCSR_ICF;
	1191	m_input_capture = CT;
1155	1192	MODIFIED_tcsr;
1156	1193	}
1157	1194	}
r24794	r24795
1160	1197	/****************************************************************************
1161	1198	* Execute cycles CPU cycles. Return number of cycles really executed
1162	1199	****************************************************************************/
1163		static CPU_EXECUTE( m6800 )
	1200	void m6800_cpu_device::execute_run()
1164	1201	{
1165		m6800_state *cpustate = get_safe_token(device);
1166	1202	UINT8 ireg;
1167	1203
1168		CHECK_IRQ_LINES(cpustate); /* HJB 990417 */
	1204	CHECK_IRQ_LINES(); /* HJB 990417 */
1169	1205
1170	1206	CLEANUP_COUNTERS();
1171	1207
1172	1208	do
1173	1209	{
1174		if( cpustate->wai_state & (M6800_WAI|M6800_SLP) )
	1210	if( m_wai_state & (M6800_WAI|M6800_SLP) )
1175	1211	{
1176	1212	EAT_CYCLES;
1177	1213	}
1178	1214	else
1179	1215	{
1180	1216	pPPC = pPC;
1181		debugger_instruction_hook(device, PCD);
	1217	debugger_instruction_hook(this, PCD);
1182	1218	ireg=M_RDOP(PCD);
1183	1219	PC++;
1184		(*cpustate->insn[ireg])(cpustate);
1185		increment_counter(cpustate, cpustate->cycles[ireg]);
	1220	(this->*m_insn[ireg])();
	1221	increment_counter(m_cycles[ireg]);
1186	1222	}
1187		} while( cpustate->icount>0 );
	1223	} while( m_icount>0 );
1188	1224	}
1189	1225
1190		/****************************************************************************
1191		* M6801 almost (fully?) equal to the M6803
1192		****************************************************************************/
1193		static CPU_INIT( m6801 )
1194		{
1195		m6800_state *cpustate = get_safe_token(device);
1196		//  cpustate->subtype = SUBTYPE_M6801;
1197		cpustate->insn = m6803_insn;
1198		cpustate->cycles = cycles_6803;
1199		cpustate->irq_callback = irqcallback;
1200		cpustate->device = device;
1201	1226
1202		cpustate->program = &device->space(AS_PROGRAM);
1203		cpustate->direct = &cpustate->program->direct();
1204		//cpustate->data = &device->space(AS_DATA);
1205		cpustate->io = &device->space(AS_IO);
1206
1207		cpustate->clock = device->clock() / 4;
1208		cpustate->sci_timer = device->machine().scheduler().timer_alloc(FUNC(sci_tick), cpustate);
1209
1210		state_register(cpustate, "m6801");
1211
1212		if (device->static_config() != NULL)
1213		{
1214		m6801_interface *intf = (m6801_interface *) device->static_config();
1215
1216		cpustate->out_sc2_func.resolve(intf->out_sc2_func, *device);
1217		}
1218		else
1219		{
1220		devcb_write_line nullcb = DEVCB_NULL;
1221		cpustate->out_sc2_func.resolve(nullcb, *device);
1222		}
1223		}
1224
1225		/****************************************************************************
1226		* M6802 almost (fully?) equal to the M6800
1227		****************************************************************************/
1228		static CPU_INIT( m6802 )
1229		{
1230		m6800_state *cpustate = get_safe_token(device);
1231		//  cpustate->subtype   = SUBTYPE_M6802;
1232		cpustate->insn = m6800_insn;
1233		cpustate->cycles = cycles_6800;
1234		cpustate->irq_callback = irqcallback;
1235		cpustate->device = device;
1236
1237		cpustate->program = &device->space(AS_PROGRAM);
1238		cpustate->direct = &cpustate->program->direct();
1239		//cpustate->data = &device->space(AS_DATA);
1240		//cpustate->io = &device->space(AS_IO);
1241
1242		state_register(cpustate, "m6802");
1243		}
1244
1245		/****************************************************************************
1246		* M6803 almost (fully?) equal to the M6801
1247		****************************************************************************/
1248		static CPU_INIT( m6803 )
1249		{
1250		m6800_state *cpustate = get_safe_token(device);
1251		//  cpustate->subtype = SUBTYPE_M6803;
1252		cpustate->insn = m6803_insn;
1253		cpustate->cycles = cycles_6803;
1254		cpustate->irq_callback = irqcallback;
1255		cpustate->device = device;
1256
1257		cpustate->program = &device->space(AS_PROGRAM);
1258		cpustate->direct = &cpustate->program->direct();
1259		//cpustate->data = &device->space(AS_DATA);
1260		cpustate->io = &device->space(AS_IO);
1261
1262		cpustate->clock = device->clock() / 4;
1263		cpustate->sci_timer = device->machine().scheduler().timer_alloc(FUNC(sci_tick), cpustate);
1264
1265		state_register(cpustate, "m6803");
1266
1267		if (device->static_config() != NULL)
1268		{
1269		m6801_interface *intf = (m6801_interface *) device->static_config();
1270
1271		cpustate->out_sc2_func.resolve(intf->out_sc2_func, *device);
1272		}
1273		else
1274		{
1275		devcb_write_line nullcb = DEVCB_NULL;
1276		cpustate->out_sc2_func.resolve(nullcb, *device);
1277		}
1278		}
1279
1280		static ADDRESS_MAP_START(m6803_mem, AS_PROGRAM, 8, legacy_cpu_device)
1281		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r, m6801_io_w)
1282		AM_RANGE(0x0020, 0x007f) AM_NOP        /* unused */
1283		AM_RANGE(0x0080, 0x00ff) AM_RAM        /* 6803 internal RAM */
1284		ADDRESS_MAP_END
1285
1286
1287		/****************************************************************************
1288		* M6808 almost (fully?) equal to the M6800
1289		****************************************************************************/
1290		static CPU_INIT( m6808 )
1291		{
1292		m6800_state *cpustate = get_safe_token(device);
1293		//  cpustate->subtype = SUBTYPE_M6808;
1294		cpustate->insn = m6800_insn;
1295		cpustate->cycles = cycles_6800;
1296		cpustate->irq_callback = irqcallback;
1297		cpustate->device = device;
1298
1299		cpustate->program = &device->space(AS_PROGRAM);
1300		cpustate->direct = &cpustate->program->direct();
1301		//cpustate->data = &device->space(AS_DATA);
1302		//cpustate->io = &device->space(AS_IO);
1303
1304		state_register(cpustate, "m6808");
1305
1306		if (device->static_config() != NULL)
1307		{
1308		m6801_interface *intf = (m6801_interface *) device->static_config();
1309
1310		cpustate->out_sc2_func.resolve(intf->out_sc2_func, *device);
1311		}
1312		else
1313		{
1314		devcb_write_line nullcb = DEVCB_NULL;
1315		cpustate->out_sc2_func.resolve(nullcb, *device);
1316		}
1317		}
1318
1319		/****************************************************************************
1320		* HD6301 similiar to the M6800
1321		****************************************************************************/
1322
1323		static CPU_INIT( hd6301 )
1324		{
1325		m6800_state *cpustate = get_safe_token(device);
1326		//  cpustate->subtype = SUBTYPE_HD6301;
1327		cpustate->insn = hd63701_insn;
1328		cpustate->cycles = cycles_63701;
1329		cpustate->irq_callback = irqcallback;
1330		cpustate->device = device;
1331
1332		cpustate->program = &device->space(AS_PROGRAM);
1333		cpustate->direct = &cpustate->program->direct();
1334		//cpustate->data = &device->space(AS_DATA);
1335		cpustate->io = &device->space(AS_IO);
1336
1337		cpustate->clock = device->clock() / 4;
1338		cpustate->sci_timer = device->machine().scheduler().timer_alloc(FUNC(sci_tick), cpustate);
1339
1340		state_register(cpustate, "hd6301");
1341
1342		if (device->static_config() != NULL)
1343		{
1344		m6801_interface *intf = (m6801_interface *) device->static_config();
1345
1346		cpustate->out_sc2_func.resolve(intf->out_sc2_func, *device);
1347		}
1348		else
1349		{
1350		devcb_write_line nullcb = DEVCB_NULL;
1351		cpustate->out_sc2_func.resolve(nullcb, *device);
1352		}
1353		}
1354
1355
1356		/****************************************************************************
1357		* HD63701 similiar to the HD6301
1358		****************************************************************************/
1359
1360		static CPU_INIT( hd63701 )
1361		{
1362		m6800_state *cpustate = get_safe_token(device);
1363		//  cpustate->subtype = SUBTYPE_HD63701;
1364		cpustate->insn = hd63701_insn;
1365		cpustate->cycles = cycles_63701;
1366		cpustate->irq_callback = irqcallback;
1367		cpustate->device = device;
1368
1369		cpustate->program = &device->space(AS_PROGRAM);
1370		cpustate->direct = &cpustate->program->direct();
1371		//cpustate->data = &device->space(AS_DATA);
1372		cpustate->io = &device->space(AS_IO);
1373
1374		cpustate->clock = device->clock() / 4;
1375		cpustate->sci_timer = device->machine().scheduler().timer_alloc(FUNC(sci_tick), cpustate);
1376
1377		state_register(cpustate, "hd63701");
1378
1379		if (device->static_config() != NULL)
1380		{
1381		m6801_interface *intf = (m6801_interface *) device->static_config();
1382
1383		cpustate->out_sc2_func.resolve(intf->out_sc2_func, *device);
1384		}
1385		else
1386		{
1387		devcb_write_line nullcb = DEVCB_NULL;
1388		cpustate->out_sc2_func.resolve(nullcb, *device);
1389		}
1390		}
1391
1392	1227	/*
1393		if change_pc(cpustate) direccted these areas ,Call hd63701_trap_pc(cpustate).
	1228	if change_pc() direccted these areas ,Call hd63701_trap_pc().
1394	1229	'mode' is selected by the sense of p2.0,p2.1,and p2.3 at reset timming.
1395	1230	mode 0,1,2,4,6 : $0000-$001f
1396	1231	mode 5         : $0000-$001f,$0200-$efff
1397	1232	mode 7         : $0000-$001f,$0100-$efff
1398	1233	*/
1399	1234	#if 0
1400		static void hd63701_trap_pc(m6800_state *cpustate)
	1235	void m6800_cpu_device::hd63701_trap_pc()
1401	1236	{
1402	1237	TAKE_TRAP;
1403	1238	}
1404	1239	#endif
1405	1240
1406		/****************************************************************************
1407		* NSC-8105 similiar to the M6800, but the opcodes are scrambled and there
1408		* is at least one new opcode ($fc)
1409		****************************************************************************/
1410		static CPU_INIT( nsc8105 )
	1241	void m6800_cpu_device::set_os3(int state)
1411	1242	{
1412		m6800_state *cpustate = get_safe_token(device);
1413		//  cpustate->subtype = SUBTYPE_NSC8105;
1414		cpustate->device = device;
	1243	//logerror("M6801 '%s' OS3: %u\n", tag(), state);
1415	1244
1416		cpustate->program = &device->space(AS_PROGRAM);
1417		cpustate->direct = &cpustate->program->direct();
1418		//cpustate->data = &device->space(AS_DATA);
1419		//cpustate->io = &device->space(AS_IO);
1420
1421		cpustate->insn = nsc8105_insn;
1422		cpustate->cycles = cycles_nsc8105;
1423		state_register(cpustate, "nsc8105");
	1245	m_out_sc2_func(state);
1424	1246	}
1425	1247
1426		INLINE void set_os3(m6800_state *cpustate, int state)
	1248	READ8_MEMBER( m6800_cpu_device::m6801_io_r )
1427	1249	{
1428		//logerror("M6801 '%s' OS3: %u\n", cpustate->device->tag(), state);
1429
1430		cpustate->out_sc2_func(state);
1431		}
1432
1433		READ8_HANDLER( m6801_io_r )
1434		{
1435		m6800_state *cpustate = get_safe_token(&space.device());
1436
1437	1250	UINT8 data = 0;
1438	1251
1439	1252	switch (offset)
1440	1253	{
1441	1254	case IO_P1DDR:
1442		data = cpustate->port1_ddr;
	1255	data = m_port1_ddr;
1443	1256	break;
1444	1257
1445	1258	case IO_P2DDR:
1446		data = cpustate->port2_ddr;
	1259	data = m_port2_ddr;
1447	1260	break;
1448	1261
1449	1262	case IO_P1DATA:
1450		if(cpustate->port1_ddr == 0xff)
1451		data = cpustate->port1_data;
	1263	if(m_port1_ddr == 0xff)
	1264	data = m_port1_data;
1452	1265	else
1453		data = (cpustate->io->read_byte(M6801_PORT1) & (cpustate->port1_ddr ^ 0xff))
1454		| (cpustate->port1_data & cpustate->port1_ddr);
	1266	data = (m_io->read_byte(M6801_PORT1) & (m_port1_ddr ^ 0xff))
	1267	| (m_port1_data & m_port1_ddr);
1455	1268	break;
1456	1269
1457	1270	case IO_P2DATA:
1458		if(cpustate->port2_ddr == 0xff)
1459		data = cpustate->port2_data;
	1271	if(m_port2_ddr == 0xff)
	1272	data = m_port2_data;
1460	1273	else
1461		data = (cpustate->io->read_byte(M6801_PORT2) & (cpustate->port2_ddr ^ 0xff))
1462		| (cpustate->port2_data & cpustate->port2_ddr);
	1274	data = (m_io->read_byte(M6801_PORT2) & (m_port2_ddr ^ 0xff))
	1275	| (m_port2_data & m_port2_ddr);
1463	1276	break;
1464	1277
1465	1278	case IO_P3DDR:
r24794	r24795
1467	1280	break;
1468	1281
1469	1282	case IO_P4DDR:
1470		data = cpustate->port4_ddr;
	1283	data = m_port4_ddr;
1471	1284	break;
1472	1285
1473	1286	case IO_P3DATA:
1474	1287	if (!space.debugger_access())
1475	1288	{
1476		if (cpustate->p3csr_is3_flag_read)
	1289	if (m_p3csr_is3_flag_read)
1477	1290	{
1478	1291	//logerror("M6801 '%s' Cleared IS3\n", space.device().tag());
1479		cpustate->p3csr &= ~M6801_P3CSR_IS3_FLAG;
1480		cpustate->p3csr_is3_flag_read = 0;
	1292	m_p3csr &= ~M6801_P3CSR_IS3_FLAG;
	1293	m_p3csr_is3_flag_read = 0;
1481	1294	}
1482	1295
1483		if (!(cpustate->p3csr & M6801_P3CSR_OSS))
	1296	if (!(m_p3csr & M6801_P3CSR_OSS))
1484	1297	{
1485		set_os3(cpustate, ASSERT_LINE);
	1298	set_os3(ASSERT_LINE);
1486	1299	}
1487	1300	}
1488	1301
1489		if ((cpustate->p3csr & M6801_P3CSR_LE) || (cpustate->port3_ddr == 0xff))
1490		data = cpustate->port3_data;
	1302	if ((m_p3csr & M6801_P3CSR_LE) || (m_port3_ddr == 0xff))
	1303	data = m_port3_data;
1491	1304	else
1492		data = (cpustate->io->read_byte(M6801_PORT3) & (cpustate->port3_ddr ^ 0xff))
1493		| (cpustate->port3_data & cpustate->port3_ddr);
	1305	data = (m_io->read_byte(M6801_PORT3) & (m_port3_ddr ^ 0xff))
	1306	| (m_port3_data & m_port3_ddr);
1494	1307
1495	1308	if (!space.debugger_access())
1496	1309	{
1497		cpustate->port3_latched = 0;
	1310	m_port3_latched = 0;
1498	1311
1499		if (!(cpustate->p3csr & M6801_P3CSR_OSS))
	1312	if (!(m_p3csr & M6801_P3CSR_OSS))
1500	1313	{
1501		set_os3(cpustate, CLEAR_LINE);
	1314	set_os3(CLEAR_LINE);
1502	1315	}
1503	1316	}
1504	1317	break;
1505	1318
1506	1319	case IO_P4DATA:
1507		if(cpustate->port4_ddr == 0xff)
1508		data = cpustate->port4_data;
	1320	if(m_port4_ddr == 0xff)
	1321	data = m_port4_data;
1509	1322	else
1510		data = (cpustate->io->read_byte(M6801_PORT4) & (cpustate->port4_ddr ^ 0xff))
1511		| (cpustate->port4_data & cpustate->port4_ddr);
	1323	data = (m_io->read_byte(M6801_PORT4) & (m_port4_ddr ^ 0xff))
	1324	| (m_port4_data & m_port4_ddr);
1512	1325	break;
1513	1326
1514	1327	case IO_TCSR:
1515		cpustate->pending_tcsr = 0;
1516		data = cpustate->tcsr;
	1328	m_pending_tcsr = 0;
	1329	data = m_tcsr;
1517	1330	break;
1518	1331
1519	1332	case IO_CH:
1520		if(!(cpustate->pending_tcsr&TCSR_TOF) && !space.debugger_access())
	1333	if(!(m_pending_tcsr&TCSR_TOF) && !space.debugger_access())
1521	1334	{
1522		cpustate->tcsr &= ~TCSR_TOF;
	1335	m_tcsr &= ~TCSR_TOF;
1523	1336	MODIFIED_tcsr;
1524	1337	}
1525		data = cpustate->counter.b.h;
	1338	data = m_counter.b.h;
1526	1339	break;
1527	1340
1528	1341	case IO_CL:
1529		data = cpustate->counter.b.l;
	1342	data = m_counter.b.l;
1530	1343	// HACK there should be a break here, but Coleco Adam won't boot with it present, proper fix required to the free-running counter
1531	1344
1532	1345	case IO_OCRH:
1533		if(!(cpustate->pending_tcsr&TCSR_OCF) && !space.debugger_access())
	1346	if(!(m_pending_tcsr&TCSR_OCF) && !space.debugger_access())
1534	1347	{
1535		cpustate->tcsr &= ~TCSR_OCF;
	1348	m_tcsr &= ~TCSR_OCF;
1536	1349	MODIFIED_tcsr;
1537	1350	}
1538		data = cpustate->output_compare.b.h;
	1351	data = m_output_compare.b.h;
1539	1352	break;
1540	1353
1541	1354	case IO_OCRL:
1542		if(!(cpustate->pending_tcsr&TCSR_OCF) && !space.debugger_access())
	1355	if(!(m_pending_tcsr&TCSR_OCF) && !space.debugger_access())
1543	1356	{
1544		cpustate->tcsr &= ~TCSR_OCF;
	1357	m_tcsr &= ~TCSR_OCF;
1545	1358	MODIFIED_tcsr;
1546	1359	}
1547		data = cpustate->output_compare.b.l;
	1360	data = m_output_compare.b.l;
1548	1361	break;
1549	1362
1550	1363	case IO_ICRH:
1551		if(!(cpustate->pending_tcsr&TCSR_ICF) && !space.debugger_access())
	1364	if(!(m_pending_tcsr&TCSR_ICF) && !space.debugger_access())
1552	1365	{
1553		cpustate->tcsr &= ~TCSR_ICF;
	1366	m_tcsr &= ~TCSR_ICF;
1554	1367	MODIFIED_tcsr;
1555	1368	}
1556		data = (cpustate->input_capture >> 0) & 0xff;
	1369	data = (m_input_capture >> 0) & 0xff;
1557	1370	break;
1558	1371
1559	1372	case IO_ICRL:
1560		data = (cpustate->input_capture >> 8) & 0xff;
	1373	data = (m_input_capture >> 8) & 0xff;
1561	1374	break;
1562	1375
1563	1376	case IO_P3CSR:
1564		if ((cpustate->p3csr & M6801_P3CSR_IS3_FLAG) && !space.debugger_access())
	1377	if ((m_p3csr & M6801_P3CSR_IS3_FLAG) && !space.debugger_access())
1565	1378	{
1566		cpustate->p3csr_is3_flag_read = 1;
	1379	m_p3csr_is3_flag_read = 1;
1567	1380	}
1568	1381
1569		data = cpustate->p3csr;
	1382	data = m_p3csr;
1570	1383	break;
1571	1384
1572	1385	case IO_RMCR:
1573		data = cpustate->rmcr;
	1386	data = m_rmcr;
1574	1387	break;
1575	1388
1576	1389	case IO_TRCSR:
1577	1390	if (!space.debugger_access())
1578	1391	{
1579		if (cpustate->trcsr & M6800_TRCSR_TDRE)
	1392	if (m_trcsr & M6800_TRCSR_TDRE)
1580	1393	{
1581		cpustate->trcsr_read_tdre = 1;
	1394	m_trcsr_read_tdre = 1;
1582	1395	}
1583	1396
1584		if (cpustate->trcsr & M6800_TRCSR_ORFE)
	1397	if (m_trcsr & M6800_TRCSR_ORFE)
1585	1398	{
1586		cpustate->trcsr_read_orfe = 1;
	1399	m_trcsr_read_orfe = 1;
1587	1400	}
1588	1401
1589		if (cpustate->trcsr & M6800_TRCSR_RDRF)
	1402	if (m_trcsr & M6800_TRCSR_RDRF)
1590	1403	{
1591		cpustate->trcsr_read_rdrf = 1;
	1404	m_trcsr_read_rdrf = 1;
1592	1405	}
1593	1406	}
1594	1407
1595		data = cpustate->trcsr;
	1408	data = m_trcsr;
1596	1409	break;
1597	1410
1598	1411	case IO_RDR:
1599	1412	if (!space.debugger_access())
1600	1413	{
1601		if (cpustate->trcsr_read_orfe)
	1414	if (m_trcsr_read_orfe)
1602	1415	{
1603	1416	//logerror("M6801 '%s' Cleared ORFE\n", space.device().tag());
1604		cpustate->trcsr_read_orfe = 0;
1605		cpustate->trcsr &= ~M6800_TRCSR_ORFE;
	1417	m_trcsr_read_orfe = 0;
	1418	m_trcsr &= ~M6800_TRCSR_ORFE;
1606	1419	}
1607	1420
1608		if (cpustate->trcsr_read_rdrf)
	1421	if (m_trcsr_read_rdrf)
1609	1422	{
1610	1423	//logerror("M6801 '%s' Cleared RDRF\n", space.device().tag());
1611		cpustate->trcsr_read_rdrf = 0;
1612		cpustate->trcsr &= ~M6800_TRCSR_RDRF;
	1424	m_trcsr_read_rdrf = 0;
	1425	m_trcsr &= ~M6800_TRCSR_RDRF;
1613	1426	}
1614	1427	}
1615	1428
1616		data = cpustate->rdr;
	1429	data = m_rdr;
1617	1430	break;
1618	1431
1619	1432	case IO_TDR:
1620		data = cpustate->tdr;
	1433	data = m_tdr;
1621	1434	break;
1622	1435
1623	1436	case IO_RCR:
1624		data = cpustate->ram_ctrl;
	1437	data = m_ram_ctrl;
1625	1438	break;
1626	1439
1627	1440	case IO_CAAH:
r24794	r24795
1642	1455	return data;
1643	1456	}
1644	1457
1645		WRITE8_HANDLER( m6801_io_w )
	1458	WRITE8_MEMBER( m6800_cpu_device::m6801_io_w )
1646	1459	{
1647		m6800_state *cpustate = get_safe_token(&space.device());
1648
1649	1460	switch (offset)
1650	1461	{
1651	1462	case IO_P1DDR:
1652	1463	//logerror("M6801 '%s' Port 1 Data Direction Register: %02x\n", space.device().tag(), data);
1653	1464
1654		if (cpustate->port1_ddr != data)
	1465	if (m_port1_ddr != data)
1655	1466	{
1656		cpustate->port1_ddr = data;
1657		if(cpustate->port1_ddr == 0xff)
1658		cpustate->io->write_byte(M6801_PORT1,cpustate->port1_data);
	1467	m_port1_ddr = data;
	1468	if(m_port1_ddr == 0xff)
	1469	m_io->write_byte(M6801_PORT1,m_port1_data);
1659	1470	else
1660		cpustate->io->write_byte(M6801_PORT1,(cpustate->port1_data & cpustate->port1_ddr) | (cpustate->port1_ddr ^ 0xff));
	1471	m_io->write_byte(M6801_PORT1,(m_port1_data & m_port1_ddr) | (m_port1_ddr ^ 0xff));
1661	1472	}
1662	1473	break;
1663	1474
1664	1475	case IO_P2DDR:
1665	1476	//logerror("M6801 '%s' Port 2 Data Direction Register: %02x\n", space.device().tag(), data);
1666	1477
1667		if (cpustate->port2_ddr != data)
	1478	if (m_port2_ddr != data)
1668	1479	{
1669		cpustate->port2_ddr = data;
1670		write_port2(cpustate);
	1480	m_port2_ddr = data;
	1481	write_port2();
1671	1482
1672		if (cpustate->port2_ddr & 2)
	1483	if (m_port2_ddr & 2)
1673	1484	logerror("CPU '%s' PC %04x: warning - port 2 bit 1 set as output (OLVL) - not supported\n",space.device().tag(),space.device().safe_pc());
1674	1485	}
1675	1486	break;
r24794	r24795
1677	1488	case IO_P1DATA:
1678	1489	//logerror("M6801 '%s' Port 1 Data Register: %02x\n", space.device().tag(), data);
1679	1490
1680		cpustate->port1_data = data;
1681		if(cpustate->port1_ddr == 0xff)
1682		cpustate->io->write_byte(M6801_PORT1,cpustate->port1_data);
	1491	m_port1_data = data;
	1492	if(m_port1_ddr == 0xff)
	1493	m_io->write_byte(M6801_PORT1,m_port1_data);
1683	1494	else
1684		cpustate->io->write_byte(M6801_PORT1,(cpustate->port1_data & cpustate->port1_ddr) | (cpustate->port1_ddr ^ 0xff));
	1495	m_io->write_byte(M6801_PORT1,(m_port1_data & m_port1_ddr) | (m_port1_ddr ^ 0xff));
1685	1496	break;
1686	1497
1687	1498	case IO_P2DATA:
1688	1499	//logerror("M6801 '%s' Port 2 Data Register: %02x\n", space.device().tag(), data);
1689	1500
1690		cpustate->port2_data = data;
1691		cpustate->port2_written = 1;
1692		write_port2(cpustate);
	1501	m_port2_data = data;
	1502	m_port2_written = 1;
	1503	write_port2();
1693	1504	break;
1694	1505
1695	1506	case IO_P3DDR:
1696	1507	//logerror("M6801 '%s' Port 3 Data Direction Register: %02x\n", space.device().tag(), data);
1697	1508
1698		if (cpustate->port3_ddr != data)
	1509	if (m_port3_ddr != data)
1699	1510	{
1700		cpustate->port3_ddr = data;
1701		if(cpustate->port3_ddr == 0xff)
1702		cpustate->io->write_byte(M6801_PORT3,cpustate->port3_data);
	1511	m_port3_ddr = data;
	1512	if(m_port3_ddr == 0xff)
	1513	m_io->write_byte(M6801_PORT3,m_port3_data);
1703	1514	else
1704		cpustate->io->write_byte(M6801_PORT3,(cpustate->port3_data & cpustate->port3_ddr) | (cpustate->port3_ddr ^ 0xff));
	1515	m_io->write_byte(M6801_PORT3,(m_port3_data & m_port3_ddr) | (m_port3_ddr ^ 0xff));
1705	1516	}
1706	1517	break;
1707	1518
1708	1519	case IO_P4DDR:
1709	1520	//logerror("M6801 '%s' Port 4 Data Direction Register: %02x\n", space.device().tag(), data);
1710	1521
1711		if (cpustate->port4_ddr != data)
	1522	if (m_port4_ddr != data)
1712	1523	{
1713		cpustate->port4_ddr = data;
1714		if(cpustate->port4_ddr == 0xff)
1715		cpustate->io->write_byte(M6801_PORT4,cpustate->port4_data);
	1524	m_port4_ddr = data;
	1525	if(m_port4_ddr == 0xff)
	1526	m_io->write_byte(M6801_PORT4,m_port4_data);
1716	1527	else
1717		cpustate->io->write_byte(M6801_PORT4,(cpustate->port4_data & cpustate->port4_ddr) | (cpustate->port4_ddr ^ 0xff));
	1528	m_io->write_byte(M6801_PORT4,(m_port4_data & m_port4_ddr) | (m_port4_ddr ^ 0xff));
1718	1529	}
1719	1530	break;
1720	1531
1721	1532	case IO_P3DATA:
1722	1533	//logerror("M6801 '%s' Port 3 Data Register: %02x\n", space.device().tag(), data);
1723	1534
1724		if (cpustate->p3csr_is3_flag_read)
	1535	if (m_p3csr_is3_flag_read)
1725	1536	{
1726	1537	//logerror("M6801 '%s' Cleared IS3\n", space.device().tag());
1727		cpustate->p3csr &= ~M6801_P3CSR_IS3_FLAG;
1728		cpustate->p3csr_is3_flag_read = 0;
	1538	m_p3csr &= ~M6801_P3CSR_IS3_FLAG;
	1539	m_p3csr_is3_flag_read = 0;
1729	1540	}
1730	1541
1731		if (cpustate->p3csr & M6801_P3CSR_OSS)
	1542	if (m_p3csr & M6801_P3CSR_OSS)
1732	1543	{
1733		set_os3(cpustate, ASSERT_LINE);
	1544	set_os3(ASSERT_LINE);
1734	1545	}
1735	1546
1736		cpustate->port3_data = data;
1737		if(cpustate->port3_ddr == 0xff)
1738		cpustate->io->write_byte(M6801_PORT3,cpustate->port3_data);
	1547	m_port3_data = data;
	1548	if(m_port3_ddr == 0xff)
	1549	m_io->write_byte(M6801_PORT3,m_port3_data);
1739	1550	else
1740		cpustate->io->write_byte(M6801_PORT3,(cpustate->port3_data & cpustate->port3_ddr) | (cpustate->port3_ddr ^ 0xff));
	1551	m_io->write_byte(M6801_PORT3,(m_port3_data & m_port3_ddr) | (m_port3_ddr ^ 0xff));
1741	1552
1742		if (cpustate->p3csr & M6801_P3CSR_OSS)
	1553	if (m_p3csr & M6801_P3CSR_OSS)
1743	1554	{
1744		set_os3(cpustate, CLEAR_LINE);
	1555	set_os3(CLEAR_LINE);
1745	1556	}
1746	1557	break;
1747	1558
1748	1559	case IO_P4DATA:
1749	1560	//logerror("M6801 '%s' Port 4 Data Register: %02x\n", space.device().tag(), data);
1750	1561
1751		cpustate->port4_data = data;
1752		if(cpustate->port4_ddr == 0xff)
1753		cpustate->io->write_byte(M6801_PORT4,cpustate->port4_data);
	1562	m_port4_data = data;
	1563	if(m_port4_ddr == 0xff)
	1564	m_io->write_byte(M6801_PORT4,m_port4_data);
1754	1565	else
1755		cpustate->io->write_byte(M6801_PORT4,(cpustate->port4_data & cpustate->port4_ddr) | (cpustate->port4_ddr ^ 0xff));
	1566	m_io->write_byte(M6801_PORT4,(m_port4_data & m_port4_ddr) | (m_port4_ddr ^ 0xff));
1756	1567	break;
1757	1568
1758	1569	case IO_TCSR:
1759	1570	//logerror("M6801 '%s' Timer Control and Status Register: %02x\n", space.device().tag(), data);
1760	1571
1761		cpustate->tcsr = data;
1762		cpustate->pending_tcsr &= cpustate->tcsr;
	1572	m_tcsr = data;
	1573	m_pending_tcsr &= m_tcsr;
1763	1574	MODIFIED_tcsr;
1764	1575	if( !(CC & 0x10) )
1765		m6800_check_irq2(cpustate);
	1576	m6800_check_irq2();
1766	1577	break;
1767	1578
1768	1579	case IO_CH:
1769	1580	//logerror("M6801 '%s' Counter High Register: %02x\n", space.device().tag(), data);
1770	1581
1771		cpustate->latch09 = data & 0xff;    /* 6301 only */
	1582	m_latch09 = data & 0xff;    /* 6301 only */
1772	1583	CT  = 0xfff8;
1773	1584	TOH = CTH;
1774	1585	MODIFIED_counters;
r24794	r24795
1777	1588	case IO_CL: /* 6301 only */
1778	1589	//logerror("M6801 '%s' Counter Low Register: %02x\n", space.device().tag(), data);
1779	1590
1780		CT = (cpustate->latch09 << 8) | (data & 0xff);
	1591	CT = (m_latch09 << 8) | (data & 0xff);
1781	1592	TOH = CTH;
1782	1593	MODIFIED_counters;
1783	1594	break;
r24794	r24795
1785	1596	case IO_OCRH:
1786	1597	//logerror("M6801 '%s' Output Compare High Register: %02x\n", space.device().tag(), data);
1787	1598
1788		if( cpustate->output_compare.b.h != data)
	1599	if( m_output_compare.b.h != data)
1789	1600	{
1790		cpustate->output_compare.b.h = data;
	1601	m_output_compare.b.h = data;
1791	1602	MODIFIED_counters;
1792	1603	}
1793	1604	break;
r24794	r24795
1795	1606	case IO_OCRL:
1796	1607	//logerror("M6801 '%s' Output Compare Low Register: %02x\n", space.device().tag(), data);
1797	1608
1798		if( cpustate->output_compare.b.l != data)
	1609	if( m_output_compare.b.l != data)
1799	1610	{
1800		cpustate->output_compare.b.l = data;
	1611	m_output_compare.b.l = data;
1801	1612	MODIFIED_counters;
1802	1613	}
1803	1614	break;
r24794	r24795
1811	1622	case IO_P3CSR:
1812	1623	//logerror("M6801 '%s' Port 3 Control and Status Register: %02x\n", space.device().tag(), data);
1813	1624
1814		cpustate->p3csr = data;
	1625	m_p3csr = data;
1815	1626	break;
1816	1627
1817	1628	case IO_RMCR:
1818	1629	//logerror("M6801 '%s' Rate and Mode Control Register: %02x\n", space.device().tag(), data);
1819	1630
1820		set_rmcr(cpustate, data);
	1631	set_rmcr(data);
1821	1632	break;
1822	1633
1823	1634	case IO_TRCSR:
1824	1635	//logerror("M6801 '%s' Transmit/Receive Control and Status Register: %02x\n", space.device().tag(), data);
1825	1636
1826		if ((data & M6800_TRCSR_TE) && !(cpustate->trcsr & M6800_TRCSR_TE))
	1637	if ((data & M6800_TRCSR_TE) && !(m_trcsr & M6800_TRCSR_TE))
1827	1638	{
1828		cpustate->txstate = M6800_TX_STATE_INIT;
1829		cpustate->txbits = 0;
1830		cpustate->tx = 1;
	1639	m_txstate = M6800_TX_STATE_INIT;
	1640	m_txbits = 0;
	1641	m_tx = 1;
1831	1642	}
1832	1643
1833		if ((data & M6800_TRCSR_RE) && !(cpustate->trcsr & M6800_TRCSR_RE))
	1644	if ((data & M6800_TRCSR_RE) && !(m_trcsr & M6800_TRCSR_RE))
1834	1645	{
1835		cpustate->rxbits = 0;
	1646	m_rxbits = 0;
1836	1647	}
1837	1648
1838		cpustate->trcsr = (cpustate->trcsr & 0xe0) | (data & 0x1f);
	1649	m_trcsr = (m_trcsr & 0xe0) | (data & 0x1f);
1839	1650	break;
1840	1651
1841	1652	case IO_TDR:
1842	1653	//logerror("M6800 '%s' Transmit Data Register: %02x\n", space.device().tag(), data);
1843	1654
1844		if (cpustate->trcsr_read_tdre)
	1655	if (m_trcsr_read_tdre)
1845	1656	{
1846		cpustate->trcsr_read_tdre = 0;
1847		cpustate->trcsr &= ~M6800_TRCSR_TDRE;
	1657	m_trcsr_read_tdre = 0;
	1658	m_trcsr &= ~M6800_TRCSR_TDRE;
1848	1659	}
1849		cpustate->tdr = data;
	1660	m_tdr = data;
1850	1661	break;
1851	1662
1852	1663	case IO_RCR:
1853	1664	//logerror("M6801 '%s' RAM Control Register: %02x\n", space.device().tag(), data);
1854	1665
1855		cpustate->ram_ctrl = data;
	1666	m_ram_ctrl = data;
1856	1667	break;
1857	1668
1858	1669	case IO_CAAH:
r24794	r24795
1873	1684	}
1874	1685
1875	1686
1876		/**************************************************************************
1877		* Generic set_info
1878		**************************************************************************/
1879
1880		static CPU_SET_INFO( m6800 )
	1687	offs_t m6800_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
1881	1688	{
1882		m6800_state *cpustate = get_safe_token(device);
1883
1884		switch (state)
1885		{
1886		/* --- the following bits of info are set as 64-bit signed integers --- */
1887		case CPUINFO_INT_INPUT_STATE + M6800_IRQ_LINE:  set_irq_line(cpustate, M6800_IRQ_LINE, info->i);    break;
1888		case CPUINFO_INT_INPUT_STATE + M6801_TIN_LINE:  set_irq_line(cpustate, M6801_TIN_LINE, info->i);    break;
1889		case CPUINFO_INT_INPUT_STATE + M6801_SC1_LINE:  set_irq_line(cpustate, M6801_SC1_LINE, info->i);    break;
1890		case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI:  set_irq_line(cpustate, INPUT_LINE_NMI, info->i);    break;
1891
1892		case CPUINFO_INT_PC:                            PC = info->i;                               break;
1893		case CPUINFO_INT_REGISTER + M6800_PC:           cpustate->pc.w.l = info->i;                 break;
1894		case CPUINFO_INT_SP:                            S = info->i;                            break;
1895		case CPUINFO_INT_REGISTER + M6800_S:            cpustate->s.w.l = info->i;                  break;
1896		case CPUINFO_INT_REGISTER + M6800_CC:           cpustate->cc = info->i;                     break;
1897		case CPUINFO_INT_REGISTER + M6800_A:            cpustate->d.b.h = info->i;                  break;
1898		case CPUINFO_INT_REGISTER + M6800_B:            cpustate->d.b.l = info->i;                  break;
1899		case CPUINFO_INT_REGISTER + M6800_X:            cpustate->x.w.l = info->i;                  break;
1900		}
	1689	extern CPU_DISASSEMBLE( m6800 );
	1690	return CPU_DISASSEMBLE_NAME(m6800)(this, buffer, pc, oprom, opram, options);
1901	1691	}
1902	1692
1903	1693
1904
1905		/**************************************************************************
1906		* Generic get_info
1907		**************************************************************************/
1908
1909		CPU_GET_INFO( m6800 )
	1694	offs_t m6801_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
1910	1695	{
1911		m6800_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
1912		switch (state)
1913		{
1914		/* --- the following bits of info are returned as 64-bit signed integers --- */
1915		case CPUINFO_INT_CONTEXT_SIZE:                  info->i = sizeof(m6800_state);          break;
1916		case CPUINFO_INT_INPUT_LINES:                   info->i = 2;                            break;
1917		case CPUINFO_INT_DEFAULT_IRQ_VECTOR:            info->i = 0;                            break;
1918		case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;               break;
1919		case CPUINFO_INT_CLOCK_MULTIPLIER:              info->i = 1;                            break;
1920		case CPUINFO_INT_CLOCK_DIVIDER:                 info->i = 1;                            break;
1921		case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 1;                            break;
1922		case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 4;                            break;
1923		case CPUINFO_INT_MIN_CYCLES:                    info->i = 1;                            break;
1924		case CPUINFO_INT_MAX_CYCLES:                    info->i = 12;                           break;
1925
1926		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:    info->i = 8;                    break;
1927		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16;                  break;
1928		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0;                   break;
1929		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:   info->i = 0;                    break;
1930		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:   info->i = 0;                    break;
1931		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:   info->i = 0;                    break;
1932		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:     info->i = 0;                    break;
1933		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:     info->i = 0;                    break;
1934		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO:     info->i = 0;                    break;
1935
1936		case CPUINFO_INT_INPUT_STATE + M6800_IRQ_LINE:  info->i = cpustate->irq_state[M6800_IRQ_LINE]; break;
1937		case CPUINFO_INT_INPUT_STATE + M6801_TIN_LINE:  info->i = cpustate->irq_state[M6801_TIN_LINE]; break;
1938		case CPUINFO_INT_INPUT_STATE + M6801_SC1_LINE:  info->i = cpustate->irq_state[M6801_SC1_LINE]; break;
1939		case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI:  info->i = cpustate->nmi_state;              break;
1940
1941		case CPUINFO_INT_PREVIOUSPC:                    info->i = cpustate->ppc.w.l;                break;
1942
1943		case CPUINFO_INT_PC:                            info->i = PC;                           break;
1944		case CPUINFO_INT_REGISTER + M6800_PC:           info->i = cpustate->pc.w.l;                 break;
1945		case CPUINFO_INT_SP:                            info->i = S;                            break;
1946		case CPUINFO_INT_REGISTER + M6800_S:            info->i = cpustate->s.w.l;                  break;
1947		case CPUINFO_INT_REGISTER + M6800_CC:           info->i = cpustate->cc;                     break;
1948		case CPUINFO_INT_REGISTER + M6800_A:            info->i = cpustate->d.b.h;                  break;
1949		case CPUINFO_INT_REGISTER + M6800_B:            info->i = cpustate->d.b.l;                  break;
1950		case CPUINFO_INT_REGISTER + M6800_X:            info->i = cpustate->x.w.l;                  break;
1951		case CPUINFO_INT_REGISTER + M6800_WAI_STATE:    info->i = cpustate->wai_state;              break;
1952
1953		/* --- the following bits of info are returned as pointers to data or functions --- */
1954		case CPUINFO_FCT_SET_INFO:                      info->setinfo = CPU_SET_INFO_NAME(m6800);           break;
1955		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(m6800);              break;
1956		case CPUINFO_FCT_RESET:                         info->reset = CPU_RESET_NAME(m6800);                break;
1957		case CPUINFO_FCT_EXIT:                          info->exit = CPU_EXIT_NAME(m6800);              break;
1958		case CPUINFO_FCT_EXECUTE:                       info->execute = CPU_EXECUTE_NAME(m6800);            break;
1959		case CPUINFO_FCT_BURN:                          info->burn = NULL;                      break;
1960		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(m6800);            break;
1961		case CPUINFO_PTR_INSTRUCTION_COUNTER:           info->icount = &cpustate->icount;           break;
1962
1963		/* --- the following bits of info are returned as NULL-terminated strings --- */
1964		case CPUINFO_STR_NAME:                          strcpy(info->s, "M6800");               break;
1965		case CPUINFO_STR_FAMILY:                    strcpy(info->s, "Motorola 6800");       break;
1966		case CPUINFO_STR_VERSION:                   strcpy(info->s, "1.1");                 break;
1967		case CPUINFO_STR_SOURCE_FILE:                       strcpy(info->s, __FILE__);              break;
1968		case CPUINFO_STR_CREDITS:                   strcpy(info->s, "The MAME team.");      break;
1969
1970		case CPUINFO_STR_FLAGS:
1971		sprintf(info->s, "%c%c%c%c%c%c%c%c",
1972		cpustate->cc & 0x80 ? '?':'.',
1973		cpustate->cc & 0x40 ? '?':'.',
1974		cpustate->cc & 0x20 ? 'H':'.',
1975		cpustate->cc & 0x10 ? 'I':'.',
1976		cpustate->cc & 0x08 ? 'N':'.',
1977		cpustate->cc & 0x04 ? 'Z':'.',
1978		cpustate->cc & 0x02 ? 'V':'.',
1979		cpustate->cc & 0x01 ? 'C':'.');
1980		break;
1981
1982		case CPUINFO_STR_REGISTER + M6800_A:            sprintf(info->s, "A:%02X", cpustate->d.b.h); break;
1983		case CPUINFO_STR_REGISTER + M6800_B:            sprintf(info->s, "B:%02X", cpustate->d.b.l); break;
1984		case CPUINFO_STR_REGISTER + M6800_PC:           sprintf(info->s, "PC:%04X", cpustate->pc.w.l); break;
1985		case CPUINFO_STR_REGISTER + M6800_S:            sprintf(info->s, "S:%04X", cpustate->s.w.l); break;
1986		case CPUINFO_STR_REGISTER + M6800_X:            sprintf(info->s, "X:%04X", cpustate->x.w.l); break;
1987		case CPUINFO_STR_REGISTER + M6800_CC:           sprintf(info->s, "CC:%02X", cpustate->cc); break;
1988		case CPUINFO_STR_REGISTER + M6800_WAI_STATE:    sprintf(info->s, "WAI:%X", cpustate->wai_state); break;
1989		}
	1696	extern CPU_DISASSEMBLE( m6801 );
	1697	return CPU_DISASSEMBLE_NAME(m6801)(this, buffer, pc, oprom, opram, options);
1990	1698	}
1991	1699
1992	1700
1993		/**************************************************************************
1994		* CPU-specific set_info
1995		**************************************************************************/
1996
1997		CPU_GET_INFO( m6801 )
	1701	offs_t m6802_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
1998	1702	{
1999		switch (state)
2000		{
2001		/* --- the following bits of info are returned as 64-bit signed integers --- */
2002		case CPUINFO_INT_CLOCK_DIVIDER:                         info->i = 4;                    break;
2003		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:     info->i = 8;                    break;
2004		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:     info->i = 9;                    break;
2005
2006		/* --- the following bits of info are returned as pointers to data or functions --- */
2007		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(m6801);              break;
2008		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(m6801);            break;
2009
2010		/* --- the following bits of info are returned as NULL-terminated strings --- */
2011		case CPUINFO_STR_NAME:                          strcpy(info->s, "M6801");               break;
2012
2013		default:                                        CPU_GET_INFO_CALL(m6800);               break;
2014		}
	1703	extern CPU_DISASSEMBLE( m6802 );
	1704	return CPU_DISASSEMBLE_NAME(m6802)(this, buffer, pc, oprom, opram, options);
2015	1705	}
2016	1706
2017	1707
2018		/**************************************************************************
2019		* CPU-specific set_info
2020		**************************************************************************/
2021
2022		CPU_GET_INFO( m6802 )
	1708	offs_t m6803_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
2023	1709	{
2024		switch (state)
2025		{
2026		/* --- the following bits of info are returned as 64-bit signed integers --- */
2027		case CPUINFO_INT_CLOCK_DIVIDER:                 info->i = 4;                            break;
2028
2029		/* --- the following bits of info are returned as pointers to data or functions --- */
2030		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(m6802);              break;
2031		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(m6802);            break;
2032
2033		/* --- the following bits of info are returned as NULL-terminated strings --- */
2034		case CPUINFO_STR_NAME:                          strcpy(info->s, "M6802");               break;
2035
2036		default:                                        CPU_GET_INFO_CALL(m6800);               break;
2037		}
	1710	extern CPU_DISASSEMBLE( m6803 );
	1711	return CPU_DISASSEMBLE_NAME(m6803)(this, buffer, pc, oprom, opram, options);
2038	1712	}
2039	1713
2040	1714
2041		/**************************************************************************
2042		* CPU-specific set_info
2043		**************************************************************************/
2044
2045		CPU_GET_INFO( m6803 )
	1715	offs_t m6808_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
2046	1716	{
2047		switch (state)
2048		{
2049		/* --- the following bits of info are returned as 64-bit signed integers --- */
2050		case CPUINFO_INT_CLOCK_DIVIDER:                         info->i = 4;                    break;
2051		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:     info->i = 8;                    break;
2052		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:     info->i = 9;                    break;
2053
2054		/* --- the following bits of info are returned as pointers to data or functions --- */
2055		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(m6803);              break;
2056		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(m6803);            break;
2057
2058		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(m6803_mem); break;
2059
2060		/* --- the following bits of info are returned as NULL-terminated strings --- */
2061		case CPUINFO_STR_NAME:                          strcpy(info->s, "M6803");               break;
2062
2063		default:                                        CPU_GET_INFO_CALL(m6800);               break;
2064		}
	1717	extern CPU_DISASSEMBLE( m6808 );
	1718	return CPU_DISASSEMBLE_NAME(m6808)(this, buffer, pc, oprom, opram, options);
2065	1719	}
2066	1720
2067	1721
2068		/**************************************************************************
2069		* CPU-specific set_info
2070		**************************************************************************/
2071
2072		CPU_GET_INFO( m6808 )
	1722	offs_t hd6301_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
2073	1723	{
2074		switch (state)
2075		{
2076		/* --- the following bits of info are returned as 64-bit signed integers --- */
2077		case CPUINFO_INT_CLOCK_DIVIDER:                 info->i = 4;                            break;
2078
2079		/* --- the following bits of info are returned as pointers to data or functions --- */
2080		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(m6808);              break;
2081		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(m6808);            break;
2082
2083		/* --- the following bits of info are returned as NULL-terminated strings --- */
2084		case CPUINFO_STR_NAME:                          strcpy(info->s, "M6808");               break;
2085
2086		default:                                        CPU_GET_INFO_CALL(m6800);               break;
2087		}
	1724	extern CPU_DISASSEMBLE( hd6301 );
	1725	return CPU_DISASSEMBLE_NAME(hd6301)(this, buffer, pc, oprom, opram, options);
2088	1726	}
2089	1727
2090	1728
2091		/**************************************************************************
2092		* CPU-specific set_info
2093		**************************************************************************/
2094
2095		CPU_GET_INFO( hd6301 )
	1729	offs_t hd63701_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
2096	1730	{
2097		switch (state)
2098		{
2099		/* --- the following bits of info are returned as 64-bit signed integers --- */
2100		case CPUINFO_INT_CLOCK_DIVIDER:                         info->i = 4;                    break;
2101		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:     info->i = 8;                    break;
2102		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:     info->i = 9;                    break;
2103
2104		/* --- the following bits of info are returned as pointers to data or functions --- */
2105		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(hd6301);             break;
2106		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(hd6301);       break;
2107
2108		/* --- the following bits of info are returned as NULL-terminated strings --- */
2109		case CPUINFO_STR_NAME:                          strcpy(info->s, "HD6301");              break;
2110
2111		default:                                        CPU_GET_INFO_CALL(m6800);               break;
2112		}
	1731	extern CPU_DISASSEMBLE( hd63701 );
	1732	return CPU_DISASSEMBLE_NAME(hd63701)(this, buffer, pc, oprom, opram, options);
2113	1733	}
2114	1734
2115		/**************************************************************************
2116		* CPU-specific set_info
2117		**************************************************************************/
2118	1735
2119		// has integrated peripherals, not yet emulated
2120		CPU_GET_INFO( hd6303r )
	1736	offs_t nsc8105_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
2121	1737	{
2122		switch (state)
2123		{
2124		/* --- the following bits of info are returned as 64-bit signed integers --- */
2125		case CPUINFO_INT_CLOCK_DIVIDER:                         info->i = 4;                    break;
2126		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:     info->i = 8;                    break;
2127		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:     info->i = 9;                    break;
2128
2129		/* --- the following bits of info are returned as pointers to data or functions --- */
2130		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(hd6301);             break;
2131		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(hd6301);       break;
2132
2133		/* --- the following bits of info are returned as NULL-terminated strings --- */
2134		case CPUINFO_STR_NAME:                          strcpy(info->s, "HD6303R");             break;
2135
2136		default:                                        CPU_GET_INFO_CALL(m6800);               break;
2137		}
	1738	extern CPU_DISASSEMBLE( nsc8105 );
	1739	return CPU_DISASSEMBLE_NAME(nsc8105)(this, buffer, pc, oprom, opram, options);
2138	1740	}
2139	1741
2140	1742
2141		/**************************************************************************
2142		* CPU-specific set_info
2143		**************************************************************************/
2144
2145		// has integrated peripherals, not yet emulated
2146		CPU_GET_INFO( hd6303y )
2147		{
2148		switch (state)
2149		{
2150		/* --- the following bits of info are returned as 64-bit signed integers --- */
2151		case CPUINFO_INT_CLOCK_DIVIDER:                         info->i = 4;                    break;
2152		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:     info->i = 8;                    break;
2153		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:     info->i = 9;                    break;
2154
2155		/* --- the following bits of info are returned as pointers to data or functions --- */
2156		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(hd6301);             break;
2157		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(hd6301);       break;
2158
2159		/* --- the following bits of info are returned as NULL-terminated strings --- */
2160		case CPUINFO_STR_NAME:                          strcpy(info->s, "HD6303Y");             break;
2161
2162		default:                                        CPU_GET_INFO_CALL(m6800);               break;
2163		}
2164		}
2165
2166		/**************************************************************************
2167		* CPU-specific set_info
2168		**************************************************************************/
2169
2170		CPU_GET_INFO( hd63701 )
2171		{
2172		switch (state)
2173		{
2174		/* --- the following bits of info are returned as 64-bit signed integers --- */
2175		case CPUINFO_INT_CLOCK_DIVIDER:                         info->i = 4;                    break;
2176		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:     info->i = 8;                    break;
2177		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:     info->i = 9;                    break;
2178
2179		/* --- the following bits of info are returned as pointers to data or functions --- */
2180		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(hd63701);                break;
2181		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(hd63701);      break;
2182
2183		/* --- the following bits of info are returned as NULL-terminated strings --- */
2184		case CPUINFO_STR_NAME:                          strcpy(info->s, "HD63701");             break;
2185
2186		default:                                        CPU_GET_INFO_CALL(m6800);               break;
2187		}
2188		}
2189
2190
2191		/**************************************************************************
2192		* CPU-specific set_info
2193		**************************************************************************/
2194
2195		CPU_GET_INFO( nsc8105 )
2196		{
2197		switch (state)
2198		{
2199		/* --- the following bits of info are returned as 64-bit signed integers --- */
2200		case CPUINFO_INT_CLOCK_DIVIDER:                 info->i = 4;                            break;
2201
2202		/* --- the following bits of info are returned as pointers to data or functions --- */
2203		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(nsc8105);                break;
2204		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(nsc8105);      break;
2205
2206		/* --- the following bits of info are returned as NULL-terminated strings --- */
2207		case CPUINFO_STR_NAME:                          strcpy(info->s, "NSC8105");             break;
2208
2209		default:                                        CPU_GET_INFO_CALL(m6800);               break;
2210		}
2211		}
2212
2213		DEFINE_LEGACY_CPU_DEVICE(M6800, m6800);
2214		DEFINE_LEGACY_CPU_DEVICE(M6801, m6801);
2215		DEFINE_LEGACY_CPU_DEVICE(M6802, m6802);
2216		DEFINE_LEGACY_CPU_DEVICE(M6803, m6803);
2217		DEFINE_LEGACY_CPU_DEVICE(M6808, m6808);
2218		DEFINE_LEGACY_CPU_DEVICE(HD6301, hd6301);
2219		DEFINE_LEGACY_CPU_DEVICE(HD63701, hd63701);
2220		DEFINE_LEGACY_CPU_DEVICE(NSC8105, nsc8105);
2221
2222		// DP-40 package: HD6303RP,  HD63A03RP,  HD63B03RP,
2223		// FP-54 package: HD6303RF,  HD63A03RF,  HD63B03RF,
2224		// CG-40 package: HD6303RCG, HD63A03RCG, HD63B03RCG,
2225		DEFINE_LEGACY_CPU_DEVICE(HD6303R, hd6303r);
2226
2227		// DP-64S package: HD6303YP,  HD63A03YP,  HD63B03YP,  HD63C03YP
2228		// FP-64  package: HD6303YF,  HD63A03YF,  HD63B03YF,  HD63C03YF
2229		// FP-64A package: HD6303YH,  HD63A03YH,  HD63B03YH,  HD63C03YH
2230		// CP-68  package: HD6303YCP, HD63A03YCP, HD63B03YCP, HD63C03YCP
2231		DEFINE_LEGACY_CPU_DEVICE(HD6303Y, hd6303y);

trunk/src/emu/cpu/m6800/6800ops.c

r24794	r24795
13	13
14	14	*/
15	15
16		#define OP_HANDLER(_name) INLINE void _name (m6800_state *cpustate)
	16	#define OP_HANDLER(_name) void m6800_cpu_device::_name ()
17	17
18	18	//OP_HANDLER( illegal )
19	19	OP_HANDLER( illegal )
r24794	r24795
63	63	{
64	64	CC=A;
65	65	ONE_MORE_INSN();
66		CHECK_IRQ_LINES(cpustate); /* HJB 990417 */
	66	CHECK_IRQ_LINES(); /* HJB 990417 */
67	67	}
68	68
69	69	/* $07 TPA inherent ----- */
r24794	r24795
115	115	{
116	116	CLI;
117	117	ONE_MORE_INSN();
118		CHECK_IRQ_LINES(cpustate); /* HJB 990417 */
	118	CHECK_IRQ_LINES(); /* HJB 990417 */
119	119	}
120	120
121	121	/* $0f SEI */
r24794	r24795
123	123	{
124	124	SEI;
125	125	ONE_MORE_INSN();
126		CHECK_IRQ_LINES(cpustate); /* HJB 990417 */
	126	CHECK_IRQ_LINES(); /* HJB 990417 */
127	127	}
128	128
129	129	/* $10 SBA inherent -**** */
r24794	r24795
203	203	OP_HANDLER( slp )
204	204	{
205	205	/* wait for next IRQ (same as waiting of wai) */
206		cpustate->wai_state |= M6800_SLP;
	206	m_wai_state |= M6800_SLP;
207	207	EAT_CYCLES;
208	208	}
209	209
r24794	r24795
352	352	/* $32 PULA inherent ----- */
353	353	OP_HANDLER( pula )
354	354	{
355		PULLBYTE(cpustate->d.b.h);
	355	PULLBYTE(m_d.b.h);
356	356	}
357	357
358	358	/* $33 PULB inherent ----- */
359	359	OP_HANDLER( pulb )
360	360	{
361		PULLBYTE(cpustate->d.b.l);
	361	PULLBYTE(m_d.b.l);
362	362	}
363	363
364	364	/* $34 DES inherent ----- */
r24794	r24795
376	376	/* $36 PSHA inherent ----- */
377	377	OP_HANDLER( psha )
378	378	{
379		PUSHBYTE(cpustate->d.b.h);
	379	PUSHBYTE(m_d.b.h);
380	380	}
381	381
382	382	/* $37 PSHB inherent ----- */
383	383	OP_HANDLER( pshb )
384	384	{
385		PUSHBYTE(cpustate->d.b.l);
	385	PUSHBYTE(m_d.b.l);
386	386	}
387	387
388	388	/* $38 PULX inherent ----- */
r24794	r24795
411	411	PULLBYTE(A);
412	412	PULLWORD(pX);
413	413	PULLWORD(pPC);
414		CHECK_IRQ_LINES(cpustate); /* HJB 990417 */
	414	CHECK_IRQ_LINES(); /* HJB 990417 */
415	415	}
416	416
417	417	/* $3c PSHX inherent ----- */
r24794	r24795
437	437	* WAI stacks the entire machine state on the
438	438	* hardware stack, then waits for an interrupt.
439	439	*/
440		cpustate->wai_state |= M6800_WAI;
	440	m_wai_state |= M6800_WAI;
441	441	PUSHWORD(pPC);
442	442	PUSHWORD(pX);
443	443	PUSHBYTE(A);
444	444	PUSHBYTE(B);
445	445	PUSHBYTE(CC);
446		CHECK_IRQ_LINES(cpustate);
447		if (cpustate->wai_state & M6800_WAI) EAT_CYCLES;
	446	CHECK_IRQ_LINES();
	447	if (m_wai_state & M6800_WAI) EAT_CYCLES;
448	448	}
449	449
450	450	/* $3f SWI absolute indirect ----- */
r24794	r24795
456	456	PUSHBYTE(B);
457	457	PUSHBYTE(CC);
458	458	SEI;
459		PCD = RM16(cpustate, 0xfffa);
	459	PCD = RM16(0xfffa);
460	460	}
461	461
462	462	/* $40 NEGA inherent ?**** */
r24794	r24795
1086	1086	/* $8e LDS immediate -**0- */
1087	1087	OP_HANDLER( lds_im )
1088	1088	{
1089		IMMWORD(cpustate->s);
	1089	IMMWORD(m_s);
1090	1090	CLR_NZV;
1091	1091	SET_NZ16(S);
1092	1092	}
r24794	r24795
1097	1097	CLR_NZV;
1098	1098	SET_NZ16(S);
1099	1099	IMM16;
1100		WM16(cpustate, EAD,&cpustate->s);
	1100	WM16(EAD,&m_s);
1101	1101	}
1102	1102
1103	1103	/* $90 SUBA direct ?**** */
r24794	r24795
1252	1252	/* $9e LDS direct -**0- */
1253	1253	OP_HANDLER( lds_di )
1254	1254	{
1255		DIRWORD(cpustate->s);
	1255	DIRWORD(m_s);
1256	1256	CLR_NZV;
1257	1257	SET_NZ16(S);
1258	1258	}
r24794	r24795
1263	1263	CLR_NZV;
1264	1264	SET_NZ16(S);
1265	1265	DIRECT;
1266		WM16(cpustate, EAD,&cpustate->s);
	1266	WM16(EAD,&m_s);
1267	1267	}
1268	1268
1269	1269	/* $a0 SUBA indexed ?**** */
r24794	r24795
1426	1426	/* $ae LDS indexed -**0- */
1427	1427	OP_HANDLER( lds_ix )
1428	1428	{
1429		IDXWORD(cpustate->s);
	1429	IDXWORD(m_s);
1430	1430	CLR_NZV;
1431	1431	SET_NZ16(S);
1432	1432	}
r24794	r24795
1437	1437	CLR_NZV;
1438	1438	SET_NZ16(S);
1439	1439	INDEXED;
1440		WM16(cpustate, EAD,&cpustate->s);
	1440	WM16(EAD,&m_s);
1441	1441	}
1442	1442
1443	1443	/* $b0 SUBA extended ?**** */
r24794	r24795
1602	1602	/* $be LDS extended -**0- */
1603	1603	OP_HANDLER( lds_ex )
1604	1604	{
1605		EXTWORD(cpustate->s);
	1605	EXTWORD(m_s);
1606	1606	CLR_NZV;
1607	1607	SET_NZ16(S);
1608	1608	}
r24794	r24795
1613	1613	CLR_NZV;
1614	1614	SET_NZ16(S);
1615	1615	EXTENDED;
1616		WM16(cpustate, EAD,&cpustate->s);
	1616	WM16(EAD,&m_s);
1617	1617	}
1618	1618
1619	1619	/* $c0 SUBB immediate ?**** */
r24794	r24795
1746	1746	/* $CC LDD immediate -**0- */
1747	1747	OP_HANDLER( ldd_im )
1748	1748	{
1749		IMMWORD(cpustate->d);
	1749	IMMWORD(m_d);
1750	1750	CLR_NZV;
1751	1751	SET_NZ16(D);
1752	1752	}
r24794	r24795
1758	1758	IMM16;
1759	1759	CLR_NZV;
1760	1760	SET_NZ16(D);
1761		WM16(cpustate, EAD,&cpustate->d);
	1761	WM16(EAD,&m_d);
1762	1762	}
1763	1763
1764	1764	/* $ce LDX immediate -**0- */
1765	1765	OP_HANDLER( ldx_im )
1766	1766	{
1767		IMMWORD(cpustate->x);
	1767	IMMWORD(m_x);
1768	1768	CLR_NZV;
1769	1769	SET_NZ16(X);
1770	1770	}
r24794	r24795
1775	1775	CLR_NZV;
1776	1776	SET_NZ16(X);
1777	1777	IMM16;
1778		WM16(cpustate, EAD,&cpustate->x);
	1778	WM16(EAD,&m_x);
1779	1779	}
1780	1780
1781	1781	/* $d0 SUBB direct ?**** */
r24794	r24795
1907	1907	/* $dc LDD direct -**0- */
1908	1908	OP_HANDLER( ldd_di )
1909	1909	{
1910		DIRWORD(cpustate->d);
	1910	DIRWORD(m_d);
1911	1911	CLR_NZV;
1912	1912	SET_NZ16(D);
1913	1913	}
r24794	r24795
1918	1918	DIRECT;
1919	1919	CLR_NZV;
1920	1920	SET_NZ16(D);
1921		WM16(cpustate, EAD,&cpustate->d);
	1921	WM16(EAD,&m_d);
1922	1922	}
1923	1923
1924	1924	/* $de LDX direct -**0- */
1925	1925	OP_HANDLER( ldx_di )
1926	1926	{
1927		DIRWORD(cpustate->x);
	1927	DIRWORD(m_x);
1928	1928	CLR_NZV;
1929	1929	SET_NZ16(X);
1930	1930	}
r24794	r24795
1935	1935	CLR_NZV;
1936	1936	SET_NZ16(X);
1937	1937	DIRECT;
1938		WM16(cpustate, EAD,&cpustate->x);
	1938	WM16(EAD,&m_x);
1939	1939	}
1940	1940
1941	1941	/* $e0 SUBB indexed ?**** */
r24794	r24795
2067	2067	/* $ec LDD indexed -**0- */
2068	2068	OP_HANDLER( ldd_ix )
2069	2069	{
2070		IDXWORD(cpustate->d);
	2070	IDXWORD(m_d);
2071	2071	CLR_NZV;
2072	2072	SET_NZ16(D);
2073	2073	}
r24794	r24795
2090	2090	INDEXED;
2091	2091	CLR_NZV;
2092	2092	SET_NZ16(D);
2093		WM16(cpustate, EAD,&cpustate->d);
	2093	WM16(EAD,&m_d);
2094	2094	}
2095	2095
2096	2096	/* $ee LDX indexed -**0- */
2097	2097	OP_HANDLER( ldx_ix )
2098	2098	{
2099		IDXWORD(cpustate->x);
	2099	IDXWORD(m_x);
2100	2100	CLR_NZV;
2101	2101	SET_NZ16(X);
2102	2102	}
r24794	r24795
2107	2107	CLR_NZV;
2108	2108	SET_NZ16(X);
2109	2109	INDEXED;
2110		WM16(cpustate, EAD,&cpustate->x);
	2110	WM16(EAD,&m_x);
2111	2111	}
2112	2112
2113	2113	/* $f0 SUBB extended ?**** */
r24794	r24795
2239	2239	/* $fc LDD extended -**0- */
2240	2240	OP_HANDLER( ldd_ex )
2241	2241	{
2242		EXTWORD(cpustate->d);
	2242	EXTWORD(m_d);
2243	2243	CLR_NZV;
2244	2244	SET_NZ16(D);
2245	2245	}
r24794	r24795
2263	2263	EXTENDED;
2264	2264	CLR_NZV;
2265	2265	SET_NZ16(D);
2266		WM16(cpustate, EAD,&cpustate->d);
	2266	WM16(EAD,&m_d);
2267	2267	}
2268	2268
2269	2269	/* $fe LDX extended -**0- */
2270	2270	OP_HANDLER( ldx_ex )
2271	2271	{
2272		EXTWORD(cpustate->x);
	2272	EXTWORD(m_x);
2273	2273	CLR_NZV;
2274	2274	SET_NZ16(X);
2275	2275	}
r24794	r24795
2280	2280	CLR_NZV;
2281	2281	SET_NZ16(X);
2282	2282	EXTENDED;
2283		WM16(cpustate, EAD,&cpustate->x);
	2283	WM16(EAD,&m_x);
2284	2284	}

trunk/src/emu/cpu/m6800/6800tbl.c

r24794	r24795
1		INLINE void aba(m6800_state *cpustate);
2		INLINE void abx(m6800_state *cpustate);
3		INLINE void adca_di(m6800_state *cpustate);
4		INLINE void adca_ex(m6800_state *cpustate);
5		INLINE void adca_im(m6800_state *cpustate);
6		INLINE void adca_ix(m6800_state *cpustate);
7		INLINE void adcb_di(m6800_state *cpustate);
8		INLINE void adcb_ex(m6800_state *cpustate);
9		INLINE void adcb_im(m6800_state *cpustate);
10		INLINE void adcb_ix(m6800_state *cpustate);
11		INLINE void adcx_im(m6800_state *cpustate);
12		INLINE void adda_di(m6800_state *cpustate);
13		INLINE void adda_ex(m6800_state *cpustate);
14		INLINE void adda_im(m6800_state *cpustate);
15		INLINE void adda_ix(m6800_state *cpustate);
16		INLINE void addb_di(m6800_state *cpustate);
17		INLINE void addb_ex(m6800_state *cpustate);
18		INLINE void addb_im(m6800_state *cpustate);
19		INLINE void addb_ix(m6800_state *cpustate);
20		INLINE void addd_di(m6800_state *cpustate);
21		INLINE void addd_ex(m6800_state *cpustate);
22		INLINE void addx_ex(m6800_state *cpustate);
23		INLINE void addd_im(m6800_state *cpustate);
24		INLINE void addd_ix(m6800_state *cpustate);
25		INLINE void aim_di(m6800_state *cpustate);
26		INLINE void aim_ix(m6800_state *cpustate);
27		INLINE void anda_di(m6800_state *cpustate);
28		INLINE void anda_ex(m6800_state *cpustate);
29		INLINE void anda_im(m6800_state *cpustate);
30		INLINE void anda_ix(m6800_state *cpustate);
31		INLINE void andb_di(m6800_state *cpustate);
32		INLINE void andb_ex(m6800_state *cpustate);
33		INLINE void andb_im(m6800_state *cpustate);
34		INLINE void andb_ix(m6800_state *cpustate);
35		INLINE void asl_ex(m6800_state *cpustate);
36		INLINE void asl_ix(m6800_state *cpustate);
37		INLINE void asla(m6800_state *cpustate);
38		INLINE void aslb(m6800_state *cpustate);
39		INLINE void asld(m6800_state *cpustate);
40		INLINE void asr_ex(m6800_state *cpustate);
41		INLINE void asr_ix(m6800_state *cpustate);
42		INLINE void asra(m6800_state *cpustate);
43		INLINE void asrb(m6800_state *cpustate);
44		INLINE void bcc(m6800_state *cpustate);
45		INLINE void bcs(m6800_state *cpustate);
46		INLINE void beq(m6800_state *cpustate);
47		INLINE void bge(m6800_state *cpustate);
48		INLINE void bgt(m6800_state *cpustate);
49		INLINE void bhi(m6800_state *cpustate);
50		INLINE void bita_di(m6800_state *cpustate);
51		INLINE void bita_ex(m6800_state *cpustate);
52		INLINE void bita_im(m6800_state *cpustate);
53		INLINE void bita_ix(m6800_state *cpustate);
54		INLINE void bitb_di(m6800_state *cpustate);
55		INLINE void bitb_ex(m6800_state *cpustate);
56		INLINE void bitb_im(m6800_state *cpustate);
57		INLINE void bitb_ix(m6800_state *cpustate);
58		INLINE void ble(m6800_state *cpustate);
59		INLINE void bls(m6800_state *cpustate);
60		INLINE void blt(m6800_state *cpustate);
61		INLINE void bmi(m6800_state *cpustate);
62		INLINE void bne(m6800_state *cpustate);
63		INLINE void bpl(m6800_state *cpustate);
64		INLINE void bra(m6800_state *cpustate);
65		INLINE void brn(m6800_state *cpustate);
66		INLINE void bsr(m6800_state *cpustate);
67		INLINE void bvc(m6800_state *cpustate);
68		INLINE void bvs(m6800_state *cpustate);
69		INLINE void cba(m6800_state *cpustate);
70		INLINE void clc(m6800_state *cpustate);
71		INLINE void cli(m6800_state *cpustate);
72		INLINE void clr_ex(m6800_state *cpustate);
73		INLINE void clr_ix(m6800_state *cpustate);
74		INLINE void clra(m6800_state *cpustate);
75		INLINE void clrb(m6800_state *cpustate);
76		INLINE void clv(m6800_state *cpustate);
77		INLINE void cmpa_di(m6800_state *cpustate);
78		INLINE void cmpa_ex(m6800_state *cpustate);
79		INLINE void cmpa_im(m6800_state *cpustate);
80		INLINE void cmpa_ix(m6800_state *cpustate);
81		INLINE void cmpb_di(m6800_state *cpustate);
82		INLINE void cmpb_ex(m6800_state *cpustate);
83		INLINE void cmpb_im(m6800_state *cpustate);
84		INLINE void cmpb_ix(m6800_state *cpustate);
85		INLINE void cmpx_di(m6800_state *cpustate);
86		INLINE void cmpx_ex(m6800_state *cpustate);
87		INLINE void cmpx_im(m6800_state *cpustate);
88		INLINE void cmpx_ix(m6800_state *cpustate);
89		INLINE void com_ex(m6800_state *cpustate);
90		INLINE void com_ix(m6800_state *cpustate);
91		INLINE void coma(m6800_state *cpustate);
92		INLINE void comb(m6800_state *cpustate);
93		INLINE void daa(m6800_state *cpustate);
94		INLINE void dec_ex(m6800_state *cpustate);
95		INLINE void dec_ix(m6800_state *cpustate);
96		INLINE void deca(m6800_state *cpustate);
97		INLINE void decb(m6800_state *cpustate);
98		INLINE void des(m6800_state *cpustate);
99		INLINE void dex(m6800_state *cpustate);
100		INLINE void eim_di(m6800_state *cpustate);
101		INLINE void eim_ix(m6800_state *cpustate);
102		INLINE void eora_di(m6800_state *cpustate);
103		INLINE void eora_ex(m6800_state *cpustate);
104		INLINE void eora_im(m6800_state *cpustate);
105		INLINE void eora_ix(m6800_state *cpustate);
106		INLINE void eorb_di(m6800_state *cpustate);
107		INLINE void eorb_ex(m6800_state *cpustate);
108		INLINE void eorb_im(m6800_state *cpustate);
109		INLINE void eorb_ix(m6800_state *cpustate);
110		INLINE void illegal(m6800_state *cpustate);
111		INLINE void inc_ex(m6800_state *cpustate);
112		INLINE void inc_ix(m6800_state *cpustate);
113		INLINE void inca(m6800_state *cpustate);
114		INLINE void incb(m6800_state *cpustate);
115		INLINE void ins(m6800_state *cpustate);
116		INLINE void inx(m6800_state *cpustate);
117		INLINE void jmp_ex(m6800_state *cpustate);
118		INLINE void jmp_ix(m6800_state *cpustate);
119		INLINE void jsr_di(m6800_state *cpustate);
120		INLINE void jsr_ex(m6800_state *cpustate);
121		INLINE void jsr_ix(m6800_state *cpustate);
122		INLINE void lda_di(m6800_state *cpustate);
123		INLINE void lda_ex(m6800_state *cpustate);
124		INLINE void lda_im(m6800_state *cpustate);
125		INLINE void lda_ix(m6800_state *cpustate);
126		INLINE void ldb_di(m6800_state *cpustate);
127		INLINE void ldb_ex(m6800_state *cpustate);
128		INLINE void ldb_im(m6800_state *cpustate);
129		INLINE void ldb_ix(m6800_state *cpustate);
130		INLINE void ldd_di(m6800_state *cpustate);
131		INLINE void ldd_ex(m6800_state *cpustate);
132		INLINE void ldd_im(m6800_state *cpustate);
133		INLINE void ldd_ix(m6800_state *cpustate);
134		INLINE void lds_di(m6800_state *cpustate);
135		INLINE void lds_ex(m6800_state *cpustate);
136		INLINE void lds_im(m6800_state *cpustate);
137		INLINE void lds_ix(m6800_state *cpustate);
138		INLINE void ldx_di(m6800_state *cpustate);
139		INLINE void ldx_ex(m6800_state *cpustate);
140		INLINE void ldx_im(m6800_state *cpustate);
141		INLINE void ldx_ix(m6800_state *cpustate);
142		INLINE void lsr_ex(m6800_state *cpustate);
143		INLINE void lsr_ix(m6800_state *cpustate);
144		INLINE void lsra(m6800_state *cpustate);
145		INLINE void lsrb(m6800_state *cpustate);
146		INLINE void lsrd(m6800_state *cpustate);
147		INLINE void mul(m6800_state *cpustate);
148		INLINE void neg_ex(m6800_state *cpustate);
149		INLINE void neg_ix(m6800_state *cpustate);
150		INLINE void nega(m6800_state *cpustate);
151		INLINE void negb(m6800_state *cpustate);
152		INLINE void nop(m6800_state *cpustate);
153		INLINE void oim_di(m6800_state *cpustate);
154		INLINE void oim_ix(m6800_state *cpustate);
155		INLINE void ora_di(m6800_state *cpustate);
156		INLINE void ora_ex(m6800_state *cpustate);
157		INLINE void ora_im(m6800_state *cpustate);
158		INLINE void ora_ix(m6800_state *cpustate);
159		INLINE void orb_di(m6800_state *cpustate);
160		INLINE void orb_ex(m6800_state *cpustate);
161		INLINE void orb_im(m6800_state *cpustate);
162		INLINE void orb_ix(m6800_state *cpustate);
163		INLINE void psha(m6800_state *cpustate);
164		INLINE void pshb(m6800_state *cpustate);
165		INLINE void pshx(m6800_state *cpustate);
166		INLINE void pula(m6800_state *cpustate);
167		INLINE void pulb(m6800_state *cpustate);
168		INLINE void pulx(m6800_state *cpustate);
169		INLINE void rol_ex(m6800_state *cpustate);
170		INLINE void rol_ix(m6800_state *cpustate);
171		INLINE void rola(m6800_state *cpustate);
172		INLINE void rolb(m6800_state *cpustate);
173		INLINE void ror_ex(m6800_state *cpustate);
174		INLINE void ror_ix(m6800_state *cpustate);
175		INLINE void rora(m6800_state *cpustate);
176		INLINE void rorb(m6800_state *cpustate);
177		INLINE void rti(m6800_state *cpustate);
178		INLINE void rts(m6800_state *cpustate);
179		INLINE void sba(m6800_state *cpustate);
180		INLINE void sbca_di(m6800_state *cpustate);
181		INLINE void sbca_ex(m6800_state *cpustate);
182		INLINE void sbca_im(m6800_state *cpustate);
183		INLINE void sbca_ix(m6800_state *cpustate);
184		INLINE void sbcb_di(m6800_state *cpustate);
185		INLINE void sbcb_ex(m6800_state *cpustate);
186		INLINE void sbcb_im(m6800_state *cpustate);
187		INLINE void sbcb_ix(m6800_state *cpustate);
188		INLINE void sec(m6800_state *cpustate);
189		INLINE void sei(m6800_state *cpustate);
190		INLINE void sev(m6800_state *cpustate);
191		INLINE void slp(m6800_state *cpustate);
192		INLINE void sta_di(m6800_state *cpustate);
193		INLINE void sta_ex(m6800_state *cpustate);
194		INLINE void sta_im(m6800_state *cpustate);
195		INLINE void sta_ix(m6800_state *cpustate);
196		INLINE void stb_di(m6800_state *cpustate);
197		INLINE void stb_ex(m6800_state *cpustate);
198		INLINE void stb_im(m6800_state *cpustate);
199		INLINE void stb_ix(m6800_state *cpustate);
200		INLINE void std_di(m6800_state *cpustate);
201		INLINE void std_ex(m6800_state *cpustate);
202		INLINE void std_im(m6800_state *cpustate);
203		INLINE void std_ix(m6800_state *cpustate);
204		INLINE void sts_di(m6800_state *cpustate);
205		INLINE void sts_ex(m6800_state *cpustate);
206		INLINE void sts_im(m6800_state *cpustate);
207		INLINE void sts_ix(m6800_state *cpustate);
208		INLINE void stx_di(m6800_state *cpustate);
209		INLINE void stx_ex(m6800_state *cpustate);
210		INLINE void stx_im(m6800_state *cpustate);
211		INLINE void stx_ix(m6800_state *cpustate);
212		INLINE void suba_di(m6800_state *cpustate);
213		INLINE void suba_ex(m6800_state *cpustate);
214		INLINE void suba_im(m6800_state *cpustate);
215		INLINE void suba_ix(m6800_state *cpustate);
216		INLINE void subb_di(m6800_state *cpustate);
217		INLINE void subb_ex(m6800_state *cpustate);
218		INLINE void subb_im(m6800_state *cpustate);
219		INLINE void subb_ix(m6800_state *cpustate);
220		INLINE void subd_di(m6800_state *cpustate);
221		INLINE void subd_ex(m6800_state *cpustate);
222		INLINE void subd_im(m6800_state *cpustate);
223		INLINE void subd_ix(m6800_state *cpustate);
224		INLINE void swi(m6800_state *cpustate);
225		INLINE void tab(m6800_state *cpustate);
226		INLINE void tap(m6800_state *cpustate);
227		INLINE void tba(m6800_state *cpustate);
228		INLINE void tim_di(m6800_state *cpustate);
229		INLINE void tim_ix(m6800_state *cpustate);
230		INLINE void tpa(m6800_state *cpustate);
231		INLINE void tst_ex(m6800_state *cpustate);
232		INLINE void tst_ix(m6800_state *cpustate);
233		INLINE void tsta(m6800_state *cpustate);
234		INLINE void tstb(m6800_state *cpustate);
235		INLINE void tsx(m6800_state *cpustate);
236		INLINE void txs(m6800_state *cpustate);
237		INLINE void undoc1(m6800_state *cpustate);
238		INLINE void undoc2(m6800_state *cpustate);
239		INLINE void wai(m6800_state *cpustate);
240		INLINE void xgdx(m6800_state *cpustate);
241	1
242		INLINE void cpx_di(m6800_state *cpustate);
243		INLINE void cpx_ex(m6800_state *cpustate);
244		INLINE void cpx_im(m6800_state *cpustate);
245		INLINE void cpx_ix(m6800_state *cpustate);
246		INLINE void trap(m6800_state *cpustate);
247
248		static void (*const m6800_insn[0x100])(m6800_state *cpustate) = {
249		illegal,nop,    illegal,illegal,illegal,illegal,tap,    tpa,
250		inx,    dex,    clv,    sev,    clc,    sec,    cli,    sei,
251		sba,    cba,    illegal,illegal,illegal,illegal,tab,    tba,
252		illegal,daa,    illegal,aba,    illegal,illegal,illegal,illegal,
253		bra,    brn,    bhi,    bls,    bcc,    bcs,    bne,    beq,
254		bvc,    bvs,    bpl,    bmi,    bge,    blt,    bgt,    ble,
255		tsx,    ins,    pula,   pulb,   des,    txs,    psha,   pshb,
256		illegal,rts,    illegal,rti,    illegal,illegal,wai,    swi,
257		nega,   illegal,illegal,coma,   lsra,   illegal,rora,   asra,
258		asla,   rola,   deca,   illegal,inca,   tsta,   illegal,clra,
259		negb,   illegal,illegal,comb,   lsrb,   illegal,rorb,   asrb,
260		aslb,   rolb,   decb,   illegal,incb,   tstb,   illegal,clrb,
261		neg_ix, illegal,illegal,com_ix, lsr_ix, illegal,ror_ix, asr_ix,
262		asl_ix, rol_ix, dec_ix, illegal,inc_ix, tst_ix, jmp_ix, clr_ix,
263		neg_ex, illegal,illegal,com_ex, lsr_ex, illegal,ror_ex, asr_ex,
264		asl_ex, rol_ex, dec_ex, illegal,inc_ex, tst_ex, jmp_ex, clr_ex,
265		suba_im,cmpa_im,sbca_im,illegal,anda_im,bita_im,lda_im, sta_im,
266		eora_im,adca_im,ora_im, adda_im,cmpx_im,bsr,    lds_im, sts_im,
267		suba_di,cmpa_di,sbca_di,illegal,anda_di,bita_di,lda_di, sta_di,
268		eora_di,adca_di,ora_di, adda_di,cmpx_di,jsr_di, lds_di, sts_di,
269		suba_ix,cmpa_ix,sbca_ix,illegal,anda_ix,bita_ix,lda_ix, sta_ix,
270		eora_ix,adca_ix,ora_ix, adda_ix,cmpx_ix,jsr_ix, lds_ix, sts_ix,
271		suba_ex,cmpa_ex,sbca_ex,illegal,anda_ex,bita_ex,lda_ex, sta_ex,
272		eora_ex,adca_ex,ora_ex, adda_ex,cmpx_ex,jsr_ex, lds_ex, sts_ex,
273		subb_im,cmpb_im,sbcb_im,illegal,andb_im,bitb_im,ldb_im, stb_im,
274		eorb_im,adcb_im,orb_im, addb_im,illegal,illegal,ldx_im, stx_im,
275		subb_di,cmpb_di,sbcb_di,illegal,andb_di,bitb_di,ldb_di, stb_di,
276		eorb_di,adcb_di,orb_di, addb_di,illegal,illegal,ldx_di, stx_di,
277		subb_ix,cmpb_ix,sbcb_ix,illegal,andb_ix,bitb_ix,ldb_ix, stb_ix,
278		eorb_ix,adcb_ix,orb_ix, addb_ix,illegal,illegal,ldx_ix, stx_ix,
279		subb_ex,cmpb_ex,sbcb_ex,illegal,andb_ex,bitb_ex,ldb_ex, stb_ex,
280		eorb_ex,adcb_ex,orb_ex, addb_ex,illegal,illegal,ldx_ex, stx_ex
	2	const m6800_cpu_device::op_func m6800_cpu_device::m6800_insn[0x100] = {
	3	&m6800_cpu_device::illegal,&m6800_cpu_device::nop,    &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::tap,    &m6800_cpu_device::tpa,
	4	&m6800_cpu_device::inx,    &m6800_cpu_device::dex,    &m6800_cpu_device::clv,    &m6800_cpu_device::sev,    &m6800_cpu_device::clc,    &m6800_cpu_device::sec,    &m6800_cpu_device::cli,    &m6800_cpu_device::sei,
	5	&m6800_cpu_device::sba,    &m6800_cpu_device::cba,    &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::tab,    &m6800_cpu_device::tba,
	6	&m6800_cpu_device::illegal,&m6800_cpu_device::daa,    &m6800_cpu_device::illegal,&m6800_cpu_device::aba,    &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,
	7	&m6800_cpu_device::bra,    &m6800_cpu_device::brn,    &m6800_cpu_device::bhi,    &m6800_cpu_device::bls,    &m6800_cpu_device::bcc,    &m6800_cpu_device::bcs,    &m6800_cpu_device::bne,    &m6800_cpu_device::beq,
	8	&m6800_cpu_device::bvc,    &m6800_cpu_device::bvs,    &m6800_cpu_device::bpl,    &m6800_cpu_device::bmi,    &m6800_cpu_device::bge,    &m6800_cpu_device::blt,    &m6800_cpu_device::bgt,    &m6800_cpu_device::ble,
	9	&m6800_cpu_device::tsx,    &m6800_cpu_device::ins,    &m6800_cpu_device::pula,   &m6800_cpu_device::pulb,   &m6800_cpu_device::des,    &m6800_cpu_device::txs,    &m6800_cpu_device::psha,   &m6800_cpu_device::pshb,
	10	&m6800_cpu_device::illegal,&m6800_cpu_device::rts,    &m6800_cpu_device::illegal,&m6800_cpu_device::rti,    &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::wai,    &m6800_cpu_device::swi,
	11	&m6800_cpu_device::nega,   &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::coma,   &m6800_cpu_device::lsra,   &m6800_cpu_device::illegal,&m6800_cpu_device::rora,   &m6800_cpu_device::asra,
	12	&m6800_cpu_device::asla,   &m6800_cpu_device::rola,   &m6800_cpu_device::deca,   &m6800_cpu_device::illegal,&m6800_cpu_device::inca,   &m6800_cpu_device::tsta,   &m6800_cpu_device::illegal,&m6800_cpu_device::clra,
	13	&m6800_cpu_device::negb,   &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::comb,   &m6800_cpu_device::lsrb,   &m6800_cpu_device::illegal,&m6800_cpu_device::rorb,   &m6800_cpu_device::asrb,
	14	&m6800_cpu_device::aslb,   &m6800_cpu_device::rolb,   &m6800_cpu_device::decb,   &m6800_cpu_device::illegal,&m6800_cpu_device::incb,   &m6800_cpu_device::tstb,   &m6800_cpu_device::illegal,&m6800_cpu_device::clrb,
	15	&m6800_cpu_device::neg_ix, &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::com_ix, &m6800_cpu_device::lsr_ix, &m6800_cpu_device::illegal,&m6800_cpu_device::ror_ix, &m6800_cpu_device::asr_ix,
	16	&m6800_cpu_device::asl_ix, &m6800_cpu_device::rol_ix, &m6800_cpu_device::dec_ix, &m6800_cpu_device::illegal,&m6800_cpu_device::inc_ix, &m6800_cpu_device::tst_ix, &m6800_cpu_device::jmp_ix, &m6800_cpu_device::clr_ix,
	17	&m6800_cpu_device::neg_ex, &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::com_ex, &m6800_cpu_device::lsr_ex, &m6800_cpu_device::illegal,&m6800_cpu_device::ror_ex, &m6800_cpu_device::asr_ex,
	18	&m6800_cpu_device::asl_ex, &m6800_cpu_device::rol_ex, &m6800_cpu_device::dec_ex, &m6800_cpu_device::illegal,&m6800_cpu_device::inc_ex, &m6800_cpu_device::tst_ex, &m6800_cpu_device::jmp_ex, &m6800_cpu_device::clr_ex,
	19	&m6800_cpu_device::suba_im,&m6800_cpu_device::cmpa_im,&m6800_cpu_device::sbca_im,&m6800_cpu_device::illegal,&m6800_cpu_device::anda_im,&m6800_cpu_device::bita_im,&m6800_cpu_device::lda_im, &m6800_cpu_device::sta_im,
	20	&m6800_cpu_device::eora_im,&m6800_cpu_device::adca_im,&m6800_cpu_device::ora_im, &m6800_cpu_device::adda_im,&m6800_cpu_device::cmpx_im,&m6800_cpu_device::bsr,    &m6800_cpu_device::lds_im, &m6800_cpu_device::sts_im,
	21	&m6800_cpu_device::suba_di,&m6800_cpu_device::cmpa_di,&m6800_cpu_device::sbca_di,&m6800_cpu_device::illegal,&m6800_cpu_device::anda_di,&m6800_cpu_device::bita_di,&m6800_cpu_device::lda_di, &m6800_cpu_device::sta_di,
	22	&m6800_cpu_device::eora_di,&m6800_cpu_device::adca_di,&m6800_cpu_device::ora_di, &m6800_cpu_device::adda_di,&m6800_cpu_device::cmpx_di,&m6800_cpu_device::jsr_di, &m6800_cpu_device::lds_di, &m6800_cpu_device::sts_di,
	23	&m6800_cpu_device::suba_ix,&m6800_cpu_device::cmpa_ix,&m6800_cpu_device::sbca_ix,&m6800_cpu_device::illegal,&m6800_cpu_device::anda_ix,&m6800_cpu_device::bita_ix,&m6800_cpu_device::lda_ix, &m6800_cpu_device::sta_ix,
	24	&m6800_cpu_device::eora_ix,&m6800_cpu_device::adca_ix,&m6800_cpu_device::ora_ix, &m6800_cpu_device::adda_ix,&m6800_cpu_device::cmpx_ix,&m6800_cpu_device::jsr_ix, &m6800_cpu_device::lds_ix, &m6800_cpu_device::sts_ix,
	25	&m6800_cpu_device::suba_ex,&m6800_cpu_device::cmpa_ex,&m6800_cpu_device::sbca_ex,&m6800_cpu_device::illegal,&m6800_cpu_device::anda_ex,&m6800_cpu_device::bita_ex,&m6800_cpu_device::lda_ex, &m6800_cpu_device::sta_ex,
	26	&m6800_cpu_device::eora_ex,&m6800_cpu_device::adca_ex,&m6800_cpu_device::ora_ex, &m6800_cpu_device::adda_ex,&m6800_cpu_device::cmpx_ex,&m6800_cpu_device::jsr_ex, &m6800_cpu_device::lds_ex, &m6800_cpu_device::sts_ex,
	27	&m6800_cpu_device::subb_im,&m6800_cpu_device::cmpb_im,&m6800_cpu_device::sbcb_im,&m6800_cpu_device::illegal,&m6800_cpu_device::andb_im,&m6800_cpu_device::bitb_im,&m6800_cpu_device::ldb_im, &m6800_cpu_device::stb_im,
	28	&m6800_cpu_device::eorb_im,&m6800_cpu_device::adcb_im,&m6800_cpu_device::orb_im, &m6800_cpu_device::addb_im,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::ldx_im, &m6800_cpu_device::stx_im,
	29	&m6800_cpu_device::subb_di,&m6800_cpu_device::cmpb_di,&m6800_cpu_device::sbcb_di,&m6800_cpu_device::illegal,&m6800_cpu_device::andb_di,&m6800_cpu_device::bitb_di,&m6800_cpu_device::ldb_di, &m6800_cpu_device::stb_di,
	30	&m6800_cpu_device::eorb_di,&m6800_cpu_device::adcb_di,&m6800_cpu_device::orb_di, &m6800_cpu_device::addb_di,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::ldx_di, &m6800_cpu_device::stx_di,
	31	&m6800_cpu_device::subb_ix,&m6800_cpu_device::cmpb_ix,&m6800_cpu_device::sbcb_ix,&m6800_cpu_device::illegal,&m6800_cpu_device::andb_ix,&m6800_cpu_device::bitb_ix,&m6800_cpu_device::ldb_ix, &m6800_cpu_device::stb_ix,
	32	&m6800_cpu_device::eorb_ix,&m6800_cpu_device::adcb_ix,&m6800_cpu_device::orb_ix, &m6800_cpu_device::addb_ix,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::ldx_ix, &m6800_cpu_device::stx_ix,
	33	&m6800_cpu_device::subb_ex,&m6800_cpu_device::cmpb_ex,&m6800_cpu_device::sbcb_ex,&m6800_cpu_device::illegal,&m6800_cpu_device::andb_ex,&m6800_cpu_device::bitb_ex,&m6800_cpu_device::ldb_ex, &m6800_cpu_device::stb_ex,
	34	&m6800_cpu_device::eorb_ex,&m6800_cpu_device::adcb_ex,&m6800_cpu_device::orb_ex, &m6800_cpu_device::addb_ex,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::ldx_ex, &m6800_cpu_device::stx_ex
281	35	};
282	36
283		static void (*const m6803_insn[0x100])(m6800_state *cpustate) = {
284		illegal,nop,    illegal,illegal,lsrd,   asld,   tap,    tpa,
285		inx,    dex,    clv,    sev,    clc,    sec,    cli,    sei,
286		sba,    cba,    illegal,illegal,illegal,illegal,tab,    tba,
287		illegal,daa,    illegal,aba,    illegal,illegal,illegal,illegal,
288		bra,    brn,    bhi,    bls,    bcc,    bcs,    bne,    beq,
289		bvc,    bvs,    bpl,    bmi,    bge,    blt,    bgt,    ble,
290		tsx,    ins,    pula,   pulb,   des,    txs,    psha,   pshb,
291		pulx,   rts,    abx,    rti,    pshx,   mul,    wai,    swi,
292		nega,   illegal,illegal,coma,   lsra,   illegal,rora,   asra,
293		asla,   rola,   deca,   illegal,inca,   tsta,   illegal,clra,
294		negb,   illegal,illegal,comb,   lsrb,   illegal,rorb,   asrb,
295		aslb,   rolb,   decb,   illegal,incb,   tstb,   illegal,clrb,
296		neg_ix, illegal,illegal,com_ix, lsr_ix, illegal,ror_ix, asr_ix,
297		asl_ix, rol_ix, dec_ix, illegal,inc_ix, tst_ix, jmp_ix, clr_ix,
298		neg_ex, illegal,illegal,com_ex, lsr_ex, illegal,ror_ex, asr_ex,
299		asl_ex, rol_ex, dec_ex, illegal,inc_ex, tst_ex, jmp_ex, clr_ex,
300		suba_im,cmpa_im,sbca_im,subd_im,anda_im,bita_im,lda_im, sta_im,
301		eora_im,adca_im,ora_im, adda_im,cpx_im ,bsr,    lds_im, sts_im,
302		suba_di,cmpa_di,sbca_di,subd_di,anda_di,bita_di,lda_di, sta_di,
303		eora_di,adca_di,ora_di, adda_di,cpx_di ,jsr_di, lds_di, sts_di,
304		suba_ix,cmpa_ix,sbca_ix,subd_ix,anda_ix,bita_ix,lda_ix, sta_ix,
305		eora_ix,adca_ix,ora_ix, adda_ix,cpx_ix ,jsr_ix, lds_ix, sts_ix,
306		suba_ex,cmpa_ex,sbca_ex,subd_ex,anda_ex,bita_ex,lda_ex, sta_ex,
307		eora_ex,adca_ex,ora_ex, adda_ex,cpx_ex ,jsr_ex, lds_ex, sts_ex,
308		subb_im,cmpb_im,sbcb_im,addd_im,andb_im,bitb_im,ldb_im, stb_im,
309		eorb_im,adcb_im,orb_im, addb_im,ldd_im, std_im, ldx_im, stx_im,
310		subb_di,cmpb_di,sbcb_di,addd_di,andb_di,bitb_di,ldb_di, stb_di,
311		eorb_di,adcb_di,orb_di, addb_di,ldd_di, std_di, ldx_di, stx_di,
312		subb_ix,cmpb_ix,sbcb_ix,addd_ix,andb_ix,bitb_ix,ldb_ix, stb_ix,
313		eorb_ix,adcb_ix,orb_ix, addb_ix,ldd_ix, std_ix, ldx_ix, stx_ix,
314		subb_ex,cmpb_ex,sbcb_ex,addd_ex,andb_ex,bitb_ex,ldb_ex, stb_ex,
315		eorb_ex,adcb_ex,orb_ex, addb_ex,ldd_ex, std_ex, ldx_ex, stx_ex
	37	const m6800_cpu_device::op_func m6800_cpu_device::m6803_insn[0x100] = {
	38	&m6800_cpu_device::illegal,&m6800_cpu_device::nop,    &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::lsrd,   &m6800_cpu_device::asld,   &m6800_cpu_device::tap,    &m6800_cpu_device::tpa,
	39	&m6800_cpu_device::inx,    &m6800_cpu_device::dex,    &m6800_cpu_device::clv,    &m6800_cpu_device::sev,    &m6800_cpu_device::clc,    &m6800_cpu_device::sec,    &m6800_cpu_device::cli,    &m6800_cpu_device::sei,
	40	&m6800_cpu_device::sba,    &m6800_cpu_device::cba,    &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::tab,    &m6800_cpu_device::tba,
	41	&m6800_cpu_device::illegal,&m6800_cpu_device::daa,    &m6800_cpu_device::illegal,&m6800_cpu_device::aba,    &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,
	42	&m6800_cpu_device::bra,    &m6800_cpu_device::brn,    &m6800_cpu_device::bhi,    &m6800_cpu_device::bls,    &m6800_cpu_device::bcc,    &m6800_cpu_device::bcs,    &m6800_cpu_device::bne,    &m6800_cpu_device::beq,
	43	&m6800_cpu_device::bvc,    &m6800_cpu_device::bvs,    &m6800_cpu_device::bpl,    &m6800_cpu_device::bmi,    &m6800_cpu_device::bge,    &m6800_cpu_device::blt,    &m6800_cpu_device::bgt,    &m6800_cpu_device::ble,
	44	&m6800_cpu_device::tsx,    &m6800_cpu_device::ins,    &m6800_cpu_device::pula,   &m6800_cpu_device::pulb,   &m6800_cpu_device::des,    &m6800_cpu_device::txs,    &m6800_cpu_device::psha,   &m6800_cpu_device::pshb,
	45	&m6800_cpu_device::pulx,   &m6800_cpu_device::rts,    &m6800_cpu_device::abx,    &m6800_cpu_device::rti,    &m6800_cpu_device::pshx,   &m6800_cpu_device::mul,    &m6800_cpu_device::wai,    &m6800_cpu_device::swi,
	46	&m6800_cpu_device::nega,   &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::coma,   &m6800_cpu_device::lsra,   &m6800_cpu_device::illegal,&m6800_cpu_device::rora,   &m6800_cpu_device::asra,
	47	&m6800_cpu_device::asla,   &m6800_cpu_device::rola,   &m6800_cpu_device::deca,   &m6800_cpu_device::illegal,&m6800_cpu_device::inca,   &m6800_cpu_device::tsta,   &m6800_cpu_device::illegal,&m6800_cpu_device::clra,
	48	&m6800_cpu_device::negb,   &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::comb,   &m6800_cpu_device::lsrb,   &m6800_cpu_device::illegal,&m6800_cpu_device::rorb,   &m6800_cpu_device::asrb,
	49	&m6800_cpu_device::aslb,   &m6800_cpu_device::rolb,   &m6800_cpu_device::decb,   &m6800_cpu_device::illegal,&m6800_cpu_device::incb,   &m6800_cpu_device::tstb,   &m6800_cpu_device::illegal,&m6800_cpu_device::clrb,
	50	&m6800_cpu_device::neg_ix, &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::com_ix, &m6800_cpu_device::lsr_ix, &m6800_cpu_device::illegal,&m6800_cpu_device::ror_ix, &m6800_cpu_device::asr_ix,
	51	&m6800_cpu_device::asl_ix, &m6800_cpu_device::rol_ix, &m6800_cpu_device::dec_ix, &m6800_cpu_device::illegal,&m6800_cpu_device::inc_ix, &m6800_cpu_device::tst_ix, &m6800_cpu_device::jmp_ix, &m6800_cpu_device::clr_ix,
	52	&m6800_cpu_device::neg_ex, &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::com_ex, &m6800_cpu_device::lsr_ex, &m6800_cpu_device::illegal,&m6800_cpu_device::ror_ex, &m6800_cpu_device::asr_ex,
	53	&m6800_cpu_device::asl_ex, &m6800_cpu_device::rol_ex, &m6800_cpu_device::dec_ex, &m6800_cpu_device::illegal,&m6800_cpu_device::inc_ex, &m6800_cpu_device::tst_ex, &m6800_cpu_device::jmp_ex, &m6800_cpu_device::clr_ex,
	54	&m6800_cpu_device::suba_im,&m6800_cpu_device::cmpa_im,&m6800_cpu_device::sbca_im,&m6800_cpu_device::subd_im,&m6800_cpu_device::anda_im,&m6800_cpu_device::bita_im,&m6800_cpu_device::lda_im, &m6800_cpu_device::sta_im,
	55	&m6800_cpu_device::eora_im,&m6800_cpu_device::adca_im,&m6800_cpu_device::ora_im, &m6800_cpu_device::adda_im,&m6800_cpu_device::cpx_im ,&m6800_cpu_device::bsr,    &m6800_cpu_device::lds_im, &m6800_cpu_device::sts_im,
	56	&m6800_cpu_device::suba_di,&m6800_cpu_device::cmpa_di,&m6800_cpu_device::sbca_di,&m6800_cpu_device::subd_di,&m6800_cpu_device::anda_di,&m6800_cpu_device::bita_di,&m6800_cpu_device::lda_di, &m6800_cpu_device::sta_di,
	57	&m6800_cpu_device::eora_di,&m6800_cpu_device::adca_di,&m6800_cpu_device::ora_di, &m6800_cpu_device::adda_di,&m6800_cpu_device::cpx_di ,&m6800_cpu_device::jsr_di, &m6800_cpu_device::lds_di, &m6800_cpu_device::sts_di,
	58	&m6800_cpu_device::suba_ix,&m6800_cpu_device::cmpa_ix,&m6800_cpu_device::sbca_ix,&m6800_cpu_device::subd_ix,&m6800_cpu_device::anda_ix,&m6800_cpu_device::bita_ix,&m6800_cpu_device::lda_ix, &m6800_cpu_device::sta_ix,
	59	&m6800_cpu_device::eora_ix,&m6800_cpu_device::adca_ix,&m6800_cpu_device::ora_ix, &m6800_cpu_device::adda_ix,&m6800_cpu_device::cpx_ix ,&m6800_cpu_device::jsr_ix, &m6800_cpu_device::lds_ix, &m6800_cpu_device::sts_ix,
	60	&m6800_cpu_device::suba_ex,&m6800_cpu_device::cmpa_ex,&m6800_cpu_device::sbca_ex,&m6800_cpu_device::subd_ex,&m6800_cpu_device::anda_ex,&m6800_cpu_device::bita_ex,&m6800_cpu_device::lda_ex, &m6800_cpu_device::sta_ex,
	61	&m6800_cpu_device::eora_ex,&m6800_cpu_device::adca_ex,&m6800_cpu_device::ora_ex, &m6800_cpu_device::adda_ex,&m6800_cpu_device::cpx_ex ,&m6800_cpu_device::jsr_ex, &m6800_cpu_device::lds_ex, &m6800_cpu_device::sts_ex,
	62	&m6800_cpu_device::subb_im,&m6800_cpu_device::cmpb_im,&m6800_cpu_device::sbcb_im,&m6800_cpu_device::addd_im,&m6800_cpu_device::andb_im,&m6800_cpu_device::bitb_im,&m6800_cpu_device::ldb_im, &m6800_cpu_device::stb_im,
	63	&m6800_cpu_device::eorb_im,&m6800_cpu_device::adcb_im,&m6800_cpu_device::orb_im, &m6800_cpu_device::addb_im,&m6800_cpu_device::ldd_im, &m6800_cpu_device::std_im, &m6800_cpu_device::ldx_im, &m6800_cpu_device::stx_im,
	64	&m6800_cpu_device::subb_di,&m6800_cpu_device::cmpb_di,&m6800_cpu_device::sbcb_di,&m6800_cpu_device::addd_di,&m6800_cpu_device::andb_di,&m6800_cpu_device::bitb_di,&m6800_cpu_device::ldb_di, &m6800_cpu_device::stb_di,
	65	&m6800_cpu_device::eorb_di,&m6800_cpu_device::adcb_di,&m6800_cpu_device::orb_di, &m6800_cpu_device::addb_di,&m6800_cpu_device::ldd_di, &m6800_cpu_device::std_di, &m6800_cpu_device::ldx_di, &m6800_cpu_device::stx_di,
	66	&m6800_cpu_device::subb_ix,&m6800_cpu_device::cmpb_ix,&m6800_cpu_device::sbcb_ix,&m6800_cpu_device::addd_ix,&m6800_cpu_device::andb_ix,&m6800_cpu_device::bitb_ix,&m6800_cpu_device::ldb_ix, &m6800_cpu_device::stb_ix,
	67	&m6800_cpu_device::eorb_ix,&m6800_cpu_device::adcb_ix,&m6800_cpu_device::orb_ix, &m6800_cpu_device::addb_ix,&m6800_cpu_device::ldd_ix, &m6800_cpu_device::std_ix, &m6800_cpu_device::ldx_ix, &m6800_cpu_device::stx_ix,
	68	&m6800_cpu_device::subb_ex,&m6800_cpu_device::cmpb_ex,&m6800_cpu_device::sbcb_ex,&m6800_cpu_device::addd_ex,&m6800_cpu_device::andb_ex,&m6800_cpu_device::bitb_ex,&m6800_cpu_device::ldb_ex, &m6800_cpu_device::stb_ex,
	69	&m6800_cpu_device::eorb_ex,&m6800_cpu_device::adcb_ex,&m6800_cpu_device::orb_ex, &m6800_cpu_device::addb_ex,&m6800_cpu_device::ldd_ex, &m6800_cpu_device::std_ex, &m6800_cpu_device::ldx_ex, &m6800_cpu_device::stx_ex
316	70	};
317	71
318		static void (*const hd63701_insn[0x100])(m6800_state *cpustate) = {
319		trap,   nop,    trap,   trap,   lsrd,   asld,   tap,    tpa,
320		inx,    dex,    clv,    sev,    clc,    sec,    cli,    sei,
321		sba,    cba,    undoc1, undoc2, trap,   trap,   tab,    tba,
322		xgdx,   daa,    slp,    aba,    trap,   trap,   trap,   trap,
323		bra,    brn,    bhi,    bls,    bcc,    bcs,    bne,    beq,
324		bvc,    bvs,    bpl,    bmi,    bge,    blt,    bgt,    ble,
325		tsx,    ins,    pula,   pulb,   des,    txs,    psha,   pshb,
326		pulx,   rts,    abx,    rti,    pshx,   mul,    wai,    swi,
327		nega,   trap,   trap,   coma,   lsra,   trap,   rora,   asra,
328		asla,   rola,   deca,   trap,   inca,   tsta,   trap,   clra,
329		negb,   trap,   trap,   comb,   lsrb,   trap,   rorb,   asrb,
330		aslb,   rolb,   decb,   trap,   incb,   tstb,   trap,   clrb,
331		neg_ix, aim_ix, oim_ix, com_ix, lsr_ix, eim_ix, ror_ix, asr_ix,
332		asl_ix, rol_ix, dec_ix, tim_ix, inc_ix, tst_ix, jmp_ix, clr_ix,
333		neg_ex, aim_di, oim_di, com_ex, lsr_ex, eim_di, ror_ex, asr_ex,
334		asl_ex, rol_ex, dec_ex, tim_di, inc_ex, tst_ex, jmp_ex, clr_ex,
335		suba_im,cmpa_im,sbca_im,subd_im,anda_im,bita_im,lda_im, sta_im,
336		eora_im,adca_im,ora_im, adda_im,cpx_im ,bsr,    lds_im, sts_im,
337		suba_di,cmpa_di,sbca_di,subd_di,anda_di,bita_di,lda_di, sta_di,
338		eora_di,adca_di,ora_di, adda_di,cpx_di ,jsr_di, lds_di, sts_di,
339		suba_ix,cmpa_ix,sbca_ix,subd_ix,anda_ix,bita_ix,lda_ix, sta_ix,
340		eora_ix,adca_ix,ora_ix, adda_ix,cpx_ix ,jsr_ix, lds_ix, sts_ix,
341		suba_ex,cmpa_ex,sbca_ex,subd_ex,anda_ex,bita_ex,lda_ex, sta_ex,
342		eora_ex,adca_ex,ora_ex, adda_ex,cpx_ex ,jsr_ex, lds_ex, sts_ex,
343		subb_im,cmpb_im,sbcb_im,addd_im,andb_im,bitb_im,ldb_im, stb_im,
344		eorb_im,adcb_im,orb_im, addb_im,ldd_im, std_im, ldx_im, stx_im,
345		subb_di,cmpb_di,sbcb_di,addd_di,andb_di,bitb_di,ldb_di, stb_di,
346		eorb_di,adcb_di,orb_di, addb_di,ldd_di, std_di, ldx_di, stx_di,
347		subb_ix,cmpb_ix,sbcb_ix,addd_ix,andb_ix,bitb_ix,ldb_ix, stb_ix,
348		eorb_ix,adcb_ix,orb_ix, addb_ix,ldd_ix, std_ix, ldx_ix, stx_ix,
349		subb_ex,cmpb_ex,sbcb_ex,addd_ex,andb_ex,bitb_ex,ldb_ex, stb_ex,
350		eorb_ex,adcb_ex,orb_ex, addb_ex,ldd_ex, std_ex, ldx_ex, stx_ex
	72	const m6800_cpu_device::op_func m6800_cpu_device::hd63701_insn[0x100] = {
	73	&m6800_cpu_device::trap,   &m6800_cpu_device::nop,    &m6800_cpu_device::trap,   &m6800_cpu_device::trap,   &m6800_cpu_device::lsrd,   &m6800_cpu_device::asld,   &m6800_cpu_device::tap,    &m6800_cpu_device::tpa,
	74	&m6800_cpu_device::inx,    &m6800_cpu_device::dex,    &m6800_cpu_device::clv,    &m6800_cpu_device::sev,    &m6800_cpu_device::clc,    &m6800_cpu_device::sec,    &m6800_cpu_device::cli,    &m6800_cpu_device::sei,
	75	&m6800_cpu_device::sba,    &m6800_cpu_device::cba,    &m6800_cpu_device::undoc1, &m6800_cpu_device::undoc2, &m6800_cpu_device::trap,   &m6800_cpu_device::trap,   &m6800_cpu_device::tab,    &m6800_cpu_device::tba,
	76	&m6800_cpu_device::xgdx,   &m6800_cpu_device::daa,    &m6800_cpu_device::slp,    &m6800_cpu_device::aba,    &m6800_cpu_device::trap,   &m6800_cpu_device::trap,   &m6800_cpu_device::trap,   &m6800_cpu_device::trap,
	77	&m6800_cpu_device::bra,    &m6800_cpu_device::brn,    &m6800_cpu_device::bhi,    &m6800_cpu_device::bls,    &m6800_cpu_device::bcc,    &m6800_cpu_device::bcs,    &m6800_cpu_device::bne,    &m6800_cpu_device::beq,
	78	&m6800_cpu_device::bvc,    &m6800_cpu_device::bvs,    &m6800_cpu_device::bpl,    &m6800_cpu_device::bmi,    &m6800_cpu_device::bge,    &m6800_cpu_device::blt,    &m6800_cpu_device::bgt,    &m6800_cpu_device::ble,
	79	&m6800_cpu_device::tsx,    &m6800_cpu_device::ins,    &m6800_cpu_device::pula,   &m6800_cpu_device::pulb,   &m6800_cpu_device::des,    &m6800_cpu_device::txs,    &m6800_cpu_device::psha,   &m6800_cpu_device::pshb,
	80	&m6800_cpu_device::pulx,   &m6800_cpu_device::rts,    &m6800_cpu_device::abx,    &m6800_cpu_device::rti,    &m6800_cpu_device::pshx,   &m6800_cpu_device::mul,    &m6800_cpu_device::wai,    &m6800_cpu_device::swi,
	81	&m6800_cpu_device::nega,   &m6800_cpu_device::trap,   &m6800_cpu_device::trap,   &m6800_cpu_device::coma,   &m6800_cpu_device::lsra,   &m6800_cpu_device::trap,   &m6800_cpu_device::rora,   &m6800_cpu_device::asra,
	82	&m6800_cpu_device::asla,   &m6800_cpu_device::rola,   &m6800_cpu_device::deca,   &m6800_cpu_device::trap,   &m6800_cpu_device::inca,   &m6800_cpu_device::tsta,   &m6800_cpu_device::trap,   &m6800_cpu_device::clra,
	83	&m6800_cpu_device::negb,   &m6800_cpu_device::trap,   &m6800_cpu_device::trap,   &m6800_cpu_device::comb,   &m6800_cpu_device::lsrb,   &m6800_cpu_device::trap,   &m6800_cpu_device::rorb,   &m6800_cpu_device::asrb,
	84	&m6800_cpu_device::aslb,   &m6800_cpu_device::rolb,   &m6800_cpu_device::decb,   &m6800_cpu_device::trap,   &m6800_cpu_device::incb,   &m6800_cpu_device::tstb,   &m6800_cpu_device::trap,   &m6800_cpu_device::clrb,
	85	&m6800_cpu_device::neg_ix, &m6800_cpu_device::aim_ix, &m6800_cpu_device::oim_ix, &m6800_cpu_device::com_ix, &m6800_cpu_device::lsr_ix, &m6800_cpu_device::eim_ix, &m6800_cpu_device::ror_ix, &m6800_cpu_device::asr_ix,
	86	&m6800_cpu_device::asl_ix, &m6800_cpu_device::rol_ix, &m6800_cpu_device::dec_ix, &m6800_cpu_device::tim_ix, &m6800_cpu_device::inc_ix, &m6800_cpu_device::tst_ix, &m6800_cpu_device::jmp_ix, &m6800_cpu_device::clr_ix,
	87	&m6800_cpu_device::neg_ex, &m6800_cpu_device::aim_di, &m6800_cpu_device::oim_di, &m6800_cpu_device::com_ex, &m6800_cpu_device::lsr_ex, &m6800_cpu_device::eim_di, &m6800_cpu_device::ror_ex, &m6800_cpu_device::asr_ex,
	88	&m6800_cpu_device::asl_ex, &m6800_cpu_device::rol_ex, &m6800_cpu_device::dec_ex, &m6800_cpu_device::tim_di, &m6800_cpu_device::inc_ex, &m6800_cpu_device::tst_ex, &m6800_cpu_device::jmp_ex, &m6800_cpu_device::clr_ex,
	89	&m6800_cpu_device::suba_im,&m6800_cpu_device::cmpa_im,&m6800_cpu_device::sbca_im,&m6800_cpu_device::subd_im,&m6800_cpu_device::anda_im,&m6800_cpu_device::bita_im,&m6800_cpu_device::lda_im, &m6800_cpu_device::sta_im,
	90	&m6800_cpu_device::eora_im,&m6800_cpu_device::adca_im,&m6800_cpu_device::ora_im, &m6800_cpu_device::adda_im,&m6800_cpu_device::cpx_im ,&m6800_cpu_device::bsr,    &m6800_cpu_device::lds_im, &m6800_cpu_device::sts_im,
	91	&m6800_cpu_device::suba_di,&m6800_cpu_device::cmpa_di,&m6800_cpu_device::sbca_di,&m6800_cpu_device::subd_di,&m6800_cpu_device::anda_di,&m6800_cpu_device::bita_di,&m6800_cpu_device::lda_di, &m6800_cpu_device::sta_di,
	92	&m6800_cpu_device::eora_di,&m6800_cpu_device::adca_di,&m6800_cpu_device::ora_di, &m6800_cpu_device::adda_di,&m6800_cpu_device::cpx_di ,&m6800_cpu_device::jsr_di, &m6800_cpu_device::lds_di, &m6800_cpu_device::sts_di,
	93	&m6800_cpu_device::suba_ix,&m6800_cpu_device::cmpa_ix,&m6800_cpu_device::sbca_ix,&m6800_cpu_device::subd_ix,&m6800_cpu_device::anda_ix,&m6800_cpu_device::bita_ix,&m6800_cpu_device::lda_ix, &m6800_cpu_device::sta_ix,
	94	&m6800_cpu_device::eora_ix,&m6800_cpu_device::adca_ix,&m6800_cpu_device::ora_ix, &m6800_cpu_device::adda_ix,&m6800_cpu_device::cpx_ix ,&m6800_cpu_device::jsr_ix, &m6800_cpu_device::lds_ix, &m6800_cpu_device::sts_ix,
	95	&m6800_cpu_device::suba_ex,&m6800_cpu_device::cmpa_ex,&m6800_cpu_device::sbca_ex,&m6800_cpu_device::subd_ex,&m6800_cpu_device::anda_ex,&m6800_cpu_device::bita_ex,&m6800_cpu_device::lda_ex, &m6800_cpu_device::sta_ex,
	96	&m6800_cpu_device::eora_ex,&m6800_cpu_device::adca_ex,&m6800_cpu_device::ora_ex, &m6800_cpu_device::adda_ex,&m6800_cpu_device::cpx_ex ,&m6800_cpu_device::jsr_ex, &m6800_cpu_device::lds_ex, &m6800_cpu_device::sts_ex,
	97	&m6800_cpu_device::subb_im,&m6800_cpu_device::cmpb_im,&m6800_cpu_device::sbcb_im,&m6800_cpu_device::addd_im,&m6800_cpu_device::andb_im,&m6800_cpu_device::bitb_im,&m6800_cpu_device::ldb_im, &m6800_cpu_device::stb_im,
	98	&m6800_cpu_device::eorb_im,&m6800_cpu_device::adcb_im,&m6800_cpu_device::orb_im, &m6800_cpu_device::addb_im,&m6800_cpu_device::ldd_im, &m6800_cpu_device::std_im, &m6800_cpu_device::ldx_im, &m6800_cpu_device::stx_im,
	99	&m6800_cpu_device::subb_di,&m6800_cpu_device::cmpb_di,&m6800_cpu_device::sbcb_di,&m6800_cpu_device::addd_di,&m6800_cpu_device::andb_di,&m6800_cpu_device::bitb_di,&m6800_cpu_device::ldb_di, &m6800_cpu_device::stb_di,
	100	&m6800_cpu_device::eorb_di,&m6800_cpu_device::adcb_di,&m6800_cpu_device::orb_di, &m6800_cpu_device::addb_di,&m6800_cpu_device::ldd_di, &m6800_cpu_device::std_di, &m6800_cpu_device::ldx_di, &m6800_cpu_device::stx_di,
	101	&m6800_cpu_device::subb_ix,&m6800_cpu_device::cmpb_ix,&m6800_cpu_device::sbcb_ix,&m6800_cpu_device::addd_ix,&m6800_cpu_device::andb_ix,&m6800_cpu_device::bitb_ix,&m6800_cpu_device::ldb_ix, &m6800_cpu_device::stb_ix,
	102	&m6800_cpu_device::eorb_ix,&m6800_cpu_device::adcb_ix,&m6800_cpu_device::orb_ix, &m6800_cpu_device::addb_ix,&m6800_cpu_device::ldd_ix, &m6800_cpu_device::std_ix, &m6800_cpu_device::ldx_ix, &m6800_cpu_device::stx_ix,
	103	&m6800_cpu_device::subb_ex,&m6800_cpu_device::cmpb_ex,&m6800_cpu_device::sbcb_ex,&m6800_cpu_device::addd_ex,&m6800_cpu_device::andb_ex,&m6800_cpu_device::bitb_ex,&m6800_cpu_device::ldb_ex, &m6800_cpu_device::stb_ex,
	104	&m6800_cpu_device::eorb_ex,&m6800_cpu_device::adcb_ex,&m6800_cpu_device::orb_ex, &m6800_cpu_device::addb_ex,&m6800_cpu_device::ldd_ex, &m6800_cpu_device::std_ex, &m6800_cpu_device::ldx_ex, &m6800_cpu_device::stx_ex
351	105	};
352	106
353		static void (*const nsc8105_insn[0x100])(m6800_state *cpustate) = {
354		illegal,illegal,nop,    illegal,illegal,tap,    illegal,tpa,
355		inx,    clv,    dex,    sev,    clc,    cli,    sec,    sei,
356		sba,    illegal,cba,    illegal,illegal,tab,    illegal,tba,
357		illegal,illegal,daa,    aba,    illegal,illegal,illegal,illegal,
358		bra,    bhi,    brn,    bls,    bcc,    bne,    bcs,    beq,
359		bvc,    bpl,    bvs,    bmi,    bge,    bgt,    blt,    ble,
360		tsx,    pula,   ins,    pulb,   des,    psha,   txs,    pshb,
361		illegal,illegal,rts,    rti,    illegal,wai,    illegal,swi,
362		suba_im,sbca_im,cmpa_im,illegal,anda_im,lda_im, bita_im,sta_im,
363		eora_im,ora_im, adca_im,adda_im,cmpx_im,lds_im, bsr,    sts_im,
364		suba_di,sbca_di,cmpa_di,illegal,anda_di,lda_di, bita_di,sta_di,
365		eora_di,ora_di, adca_di,adda_di,cmpx_di,lds_di, jsr_di, sts_di,
366		suba_ix,sbca_ix,cmpa_ix,illegal,anda_ix,lda_ix, bita_ix,sta_ix,
367		eora_ix,ora_ix, adca_ix,adda_ix,cmpx_ix,lds_ix, jsr_ix, sts_ix,
368		suba_ex,sbca_ex,cmpa_ex,illegal,anda_ex,lda_ex, bita_ex,sta_ex,
369		eora_ex,ora_ex, adca_ex,adda_ex,cmpx_ex,lds_ex, jsr_ex, sts_ex,
370		nega,   illegal,illegal,coma,   lsra,   rora,   illegal,asra,
371		asla,   deca,   rola,   illegal,inca,   illegal,tsta,   clra,
372		negb,   illegal,illegal,comb,   lsrb,   rorb,   illegal,asrb,
373		aslb,   decb,   rolb,   illegal,incb,   illegal,tstb,   clrb,
374		neg_ix, illegal,illegal,com_ix, lsr_ix, ror_ix, illegal,asr_ix,
375		asl_ix, dec_ix, rol_ix, illegal,inc_ix, jmp_ix, tst_ix, clr_ix,
376		neg_ex, illegal,illegal,com_ex, lsr_ex, ror_ex, illegal,asr_ex,
377		asl_ex, dec_ex, rol_ex, illegal,inc_ex, jmp_ex, tst_ex, clr_ex,
378		subb_im,sbcb_im,cmpb_im,illegal,andb_im,ldb_im, bitb_im,stb_im,
379		eorb_im,orb_im, adcb_im,addb_im,illegal,ldx_im, illegal,stx_im,
380		subb_di,sbcb_di,cmpb_di,illegal,andb_di,ldb_di, bitb_di,stb_di,
381		eorb_di,orb_di, adcb_di,addb_di,illegal,ldx_di, illegal,stx_di,
382		subb_ix,sbcb_ix,cmpb_ix,illegal,andb_ix,ldb_ix, bitb_ix,stb_ix,
383		eorb_ix,orb_ix, adcb_ix,addb_ix,adcx_im,ldx_ix, illegal,stx_ix,
384		subb_ex,sbcb_ex,cmpb_ex,illegal,andb_ex,ldb_ex, bitb_ex,stb_ex,
385		eorb_ex,orb_ex, adcb_ex,addb_ex,addx_ex,ldx_ex, illegal,stx_ex
	107	const m6800_cpu_device::op_func m6800_cpu_device::nsc8105_insn[0x100] = {
	108	&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::nop,    &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::tap,    &m6800_cpu_device::illegal,&m6800_cpu_device::tpa,
	109	&m6800_cpu_device::inx,    &m6800_cpu_device::clv,    &m6800_cpu_device::dex,    &m6800_cpu_device::sev,    &m6800_cpu_device::clc,    &m6800_cpu_device::cli,    &m6800_cpu_device::sec,    &m6800_cpu_device::sei,
	110	&m6800_cpu_device::sba,    &m6800_cpu_device::illegal,&m6800_cpu_device::cba,    &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::tab,    &m6800_cpu_device::illegal,&m6800_cpu_device::tba,
	111	&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::daa,    &m6800_cpu_device::aba,    &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,
	112	&m6800_cpu_device::bra,    &m6800_cpu_device::bhi,    &m6800_cpu_device::brn,    &m6800_cpu_device::bls,    &m6800_cpu_device::bcc,    &m6800_cpu_device::bne,    &m6800_cpu_device::bcs,    &m6800_cpu_device::beq,
	113	&m6800_cpu_device::bvc,    &m6800_cpu_device::bpl,    &m6800_cpu_device::bvs,    &m6800_cpu_device::bmi,    &m6800_cpu_device::bge,    &m6800_cpu_device::bgt,    &m6800_cpu_device::blt,    &m6800_cpu_device::ble,
	114	&m6800_cpu_device::tsx,    &m6800_cpu_device::pula,   &m6800_cpu_device::ins,    &m6800_cpu_device::pulb,   &m6800_cpu_device::des,    &m6800_cpu_device::psha,   &m6800_cpu_device::txs,    &m6800_cpu_device::pshb,
	115	&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::rts,    &m6800_cpu_device::rti,    &m6800_cpu_device::illegal,&m6800_cpu_device::wai,    &m6800_cpu_device::illegal,&m6800_cpu_device::swi,
	116	&m6800_cpu_device::suba_im,&m6800_cpu_device::sbca_im,&m6800_cpu_device::cmpa_im,&m6800_cpu_device::illegal,&m6800_cpu_device::anda_im,&m6800_cpu_device::lda_im, &m6800_cpu_device::bita_im,&m6800_cpu_device::sta_im,
	117	&m6800_cpu_device::eora_im,&m6800_cpu_device::ora_im, &m6800_cpu_device::adca_im,&m6800_cpu_device::adda_im,&m6800_cpu_device::cmpx_im,&m6800_cpu_device::lds_im, &m6800_cpu_device::bsr,    &m6800_cpu_device::sts_im,
	118	&m6800_cpu_device::suba_di,&m6800_cpu_device::sbca_di,&m6800_cpu_device::cmpa_di,&m6800_cpu_device::illegal,&m6800_cpu_device::anda_di,&m6800_cpu_device::lda_di, &m6800_cpu_device::bita_di,&m6800_cpu_device::sta_di,
	119	&m6800_cpu_device::eora_di,&m6800_cpu_device::ora_di, &m6800_cpu_device::adca_di,&m6800_cpu_device::adda_di,&m6800_cpu_device::cmpx_di,&m6800_cpu_device::lds_di, &m6800_cpu_device::jsr_di, &m6800_cpu_device::sts_di,
	120	&m6800_cpu_device::suba_ix,&m6800_cpu_device::sbca_ix,&m6800_cpu_device::cmpa_ix,&m6800_cpu_device::illegal,&m6800_cpu_device::anda_ix,&m6800_cpu_device::lda_ix, &m6800_cpu_device::bita_ix,&m6800_cpu_device::sta_ix,
	121	&m6800_cpu_device::eora_ix,&m6800_cpu_device::ora_ix, &m6800_cpu_device::adca_ix,&m6800_cpu_device::adda_ix,&m6800_cpu_device::cmpx_ix,&m6800_cpu_device::lds_ix, &m6800_cpu_device::jsr_ix, &m6800_cpu_device::sts_ix,
	122	&m6800_cpu_device::suba_ex,&m6800_cpu_device::sbca_ex,&m6800_cpu_device::cmpa_ex,&m6800_cpu_device::illegal,&m6800_cpu_device::anda_ex,&m6800_cpu_device::lda_ex, &m6800_cpu_device::bita_ex,&m6800_cpu_device::sta_ex,
	123	&m6800_cpu_device::eora_ex,&m6800_cpu_device::ora_ex, &m6800_cpu_device::adca_ex,&m6800_cpu_device::adda_ex,&m6800_cpu_device::cmpx_ex,&m6800_cpu_device::lds_ex, &m6800_cpu_device::jsr_ex, &m6800_cpu_device::sts_ex,
	124	&m6800_cpu_device::nega,   &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::coma,   &m6800_cpu_device::lsra,   &m6800_cpu_device::rora,   &m6800_cpu_device::illegal,&m6800_cpu_device::asra,
	125	&m6800_cpu_device::asla,   &m6800_cpu_device::deca,   &m6800_cpu_device::rola,   &m6800_cpu_device::illegal,&m6800_cpu_device::inca,   &m6800_cpu_device::illegal,&m6800_cpu_device::tsta,   &m6800_cpu_device::clra,
	126	&m6800_cpu_device::negb,   &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::comb,   &m6800_cpu_device::lsrb,   &m6800_cpu_device::rorb,   &m6800_cpu_device::illegal,&m6800_cpu_device::asrb,
	127	&m6800_cpu_device::aslb,   &m6800_cpu_device::decb,   &m6800_cpu_device::rolb,   &m6800_cpu_device::illegal,&m6800_cpu_device::incb,   &m6800_cpu_device::illegal,&m6800_cpu_device::tstb,   &m6800_cpu_device::clrb,
	128	&m6800_cpu_device::neg_ix, &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::com_ix, &m6800_cpu_device::lsr_ix, &m6800_cpu_device::ror_ix, &m6800_cpu_device::illegal,&m6800_cpu_device::asr_ix,
	129	&m6800_cpu_device::asl_ix, &m6800_cpu_device::dec_ix, &m6800_cpu_device::rol_ix, &m6800_cpu_device::illegal,&m6800_cpu_device::inc_ix, &m6800_cpu_device::jmp_ix, &m6800_cpu_device::tst_ix, &m6800_cpu_device::clr_ix,
	130	&m6800_cpu_device::neg_ex, &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::com_ex, &m6800_cpu_device::lsr_ex, &m6800_cpu_device::ror_ex, &m6800_cpu_device::illegal,&m6800_cpu_device::asr_ex,
	131	&m6800_cpu_device::asl_ex, &m6800_cpu_device::dec_ex, &m6800_cpu_device::rol_ex, &m6800_cpu_device::illegal,&m6800_cpu_device::inc_ex, &m6800_cpu_device::jmp_ex, &m6800_cpu_device::tst_ex, &m6800_cpu_device::clr_ex,
	132	&m6800_cpu_device::subb_im,&m6800_cpu_device::sbcb_im,&m6800_cpu_device::cmpb_im,&m6800_cpu_device::illegal,&m6800_cpu_device::andb_im,&m6800_cpu_device::ldb_im, &m6800_cpu_device::bitb_im,&m6800_cpu_device::stb_im,
	133	&m6800_cpu_device::eorb_im,&m6800_cpu_device::orb_im, &m6800_cpu_device::adcb_im,&m6800_cpu_device::addb_im,&m6800_cpu_device::illegal,&m6800_cpu_device::ldx_im, &m6800_cpu_device::illegal,&m6800_cpu_device::stx_im,
	134	&m6800_cpu_device::subb_di,&m6800_cpu_device::sbcb_di,&m6800_cpu_device::cmpb_di,&m6800_cpu_device::illegal,&m6800_cpu_device::andb_di,&m6800_cpu_device::ldb_di, &m6800_cpu_device::bitb_di,&m6800_cpu_device::stb_di,
	135	&m6800_cpu_device::eorb_di,&m6800_cpu_device::orb_di, &m6800_cpu_device::adcb_di,&m6800_cpu_device::addb_di,&m6800_cpu_device::illegal,&m6800_cpu_device::ldx_di, &m6800_cpu_device::illegal,&m6800_cpu_device::stx_di,
	136	&m6800_cpu_device::subb_ix,&m6800_cpu_device::sbcb_ix,&m6800_cpu_device::cmpb_ix,&m6800_cpu_device::illegal,&m6800_cpu_device::andb_ix,&m6800_cpu_device::ldb_ix, &m6800_cpu_device::bitb_ix,&m6800_cpu_device::stb_ix,
	137	&m6800_cpu_device::eorb_ix,&m6800_cpu_device::orb_ix, &m6800_cpu_device::adcb_ix,&m6800_cpu_device::addb_ix,&m6800_cpu_device::adcx_im,&m6800_cpu_device::ldx_ix, &m6800_cpu_device::illegal,&m6800_cpu_device::stx_ix,
	138	&m6800_cpu_device::subb_ex,&m6800_cpu_device::sbcb_ex,&m6800_cpu_device::cmpb_ex,&m6800_cpu_device::illegal,&m6800_cpu_device::andb_ex,&m6800_cpu_device::ldb_ex, &m6800_cpu_device::bitb_ex,&m6800_cpu_device::stb_ex,
	139	&m6800_cpu_device::eorb_ex,&m6800_cpu_device::orb_ex, &m6800_cpu_device::adcb_ex,&m6800_cpu_device::addb_ex,&m6800_cpu_device::addx_ex,&m6800_cpu_device::ldx_ex, &m6800_cpu_device::illegal,&m6800_cpu_device::stx_ex
386	140	};

trunk/src/emu/cpu/m6800/m6800.h

r24794	r24795
6	6	#define __M6800_H__
7	7
8	8
9		struct m6801_interface
10		{
11		devcb_write_line        out_sc2_func;
12		};
13		#define M6801_INTERFACE(name) const m6801_interface (name) =
14
15
16	9	enum
17	10	{
18	11	M6800_PC=1, M6800_S, M6800_A, M6800_B, M6800_X, M6800_CC,
r24794	r24795
50	43	M6801_PORT4
51	44	};
52	45
53		DECLARE_LEGACY_CPU_DEVICE(M6800, m6800);
54		DECLARE_LEGACY_CPU_DEVICE(M6801, m6801);
55		DECLARE_LEGACY_CPU_DEVICE(M6802, m6802);
56		DECLARE_LEGACY_CPU_DEVICE(M6803, m6803);
57		DECLARE_LEGACY_CPU_DEVICE(M6808, m6808);
58		DECLARE_LEGACY_CPU_DEVICE(HD6301, hd6301);
59		DECLARE_LEGACY_CPU_DEVICE(HD63701, hd63701);
60		DECLARE_LEGACY_CPU_DEVICE(NSC8105, nsc8105);
61	46
62		DECLARE_LEGACY_CPU_DEVICE(HD6303R, hd6303r);
63		DECLARE_LEGACY_CPU_DEVICE(HD6303Y, hd6303y);
	47	#define MCFG_M6801_SC2(_devcb) \
	48	m6800_cpu_device::set_out_sc2_func(*device, DEVCB2_##_devcb);
64	49
65	50
66		DECLARE_READ8_HANDLER( m6801_io_r );
67		DECLARE_WRITE8_HANDLER( m6801_io_w );
	51	class m6800_cpu_device :  public cpu_device
	52	{
	53	public:
	54	typedef void (m6800_cpu_device::*op_func)();
68	55
69		CPU_DISASSEMBLE( m6800 );
70		CPU_DISASSEMBLE( m6801 );
71		CPU_DISASSEMBLE( m6802 );
72		CPU_DISASSEMBLE( m6803 );
73		CPU_DISASSEMBLE( m6808 );
74		CPU_DISASSEMBLE( hd6301 );
75		CPU_DISASSEMBLE( hd63701 );
76		CPU_DISASSEMBLE( nsc8105 );
	56	// construction/destruction
	57	m6800_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	58	m6800_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, bool has_io, int clock_divider, const m6800_cpu_device::op_func *insn, const UINT8 *cycles, address_map_constructor internal = NULL);
77	59
	60	// static configuration helpers
	61	template<class _Object> static devcb2_base &set_out_sc2_func(device_t &device, _Object object) { return downcast<m6800_cpu_device &>(device).m_out_sc2_func.set_callback(object); }
	62
	63	DECLARE_READ8_MEMBER( m6801_io_r );
	64	DECLARE_WRITE8_MEMBER( m6801_io_w );
	65
	66	protected:
	67	// device-level overrides
	68	virtual void device_start();
	69	virtual void device_reset();
	70
	71	// device_execute_interface overrides
	72	virtual UINT32 execute_min_cycles() const { return 1; }
	73	virtual UINT32 execute_max_cycles() const { return 12; }
	74	virtual UINT32 execute_input_lines() const { return 2; }
	75	virtual UINT32 execute_default_irq_vector() const { return 0; }
	76	virtual void execute_run();
	77	virtual void execute_set_input(int inputnum, int state);
	78
	79	// device_memory_interface overrides
	80	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO && m_has_io) ? &m_io_config : NULL ); }
	81
	82	// device_state_interface overrides
	83	void state_string_export(const device_state_entry &entry, astring &string);
	84
	85	// device_disasm_interface overrides
	86	virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
	87	virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
	88	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	89
	90	address_space_config m_program_config;
	91	address_space_config m_io_config;
	92	bool m_has_io;
	93
	94	devcb2_write_line m_out_sc2_func;
	95
	96	PAIR    m_ppc;            /* Previous program counter */
	97	PAIR    m_pc;             /* Program counter */
	98	PAIR    m_s;              /* Stack pointer */
	99	PAIR    m_x;              /* Index register */
	100	PAIR    m_d;              /* Accumulators */
	101	UINT8   m_cc;             /* Condition codes */
	102	UINT8   m_wai_state;      /* WAI opcode state ,(or sleep opcode state) */
	103	UINT8   m_nmi_state;      /* NMI line state */
	104	UINT8   m_nmi_pending;    /* NMI pending */
	105	UINT8   m_irq_state[3];   /* IRQ line state [IRQ1,TIN,SC1] */
	106	UINT8   m_ic_eddge;       /* InputCapture eddge , b.0=fall,b.1=raise */
	107	int     m_sc1_state;
	108
	109	/* Memory spaces */
	110	address_space *m_program;
	111	direct_read_data *m_direct;
	112	address_space *m_io;
	113
	114	const op_func *m_insn;
	115	const UINT8 *m_cycles;            /* clock cycle of instruction table */
	116	/* internal registers */
	117	UINT8   m_port1_ddr;
	118	UINT8   m_port2_ddr;
	119	UINT8   m_port3_ddr;
	120	UINT8   m_port4_ddr;
	121	UINT8   m_port1_data;
	122	UINT8   m_port2_data;
	123	UINT8   m_port3_data;
	124	UINT8   m_port4_data;
	125	UINT8   m_p3csr;          // Port 3 Control/Status Register
	126	UINT8   m_tcsr;           /* Timer Control and Status Register */
	127	UINT8   m_pending_tcsr;   /* pending IRQ flag for clear IRQflag process */
	128	UINT8   m_irq2;           /* IRQ2 flags */
	129	UINT8   m_ram_ctrl;
	130	PAIR    m_counter;        /* free running counter */
	131	PAIR    m_output_compare; /* output compare       */
	132	UINT16  m_input_capture;  /* input capture        */
	133	int     m_p3csr_is3_flag_read;
	134	int     m_port3_latched;
	135
	136	int     m_clock_divider;
	137	UINT8   m_trcsr, m_rmcr, m_rdr, m_tdr, m_rsr, m_tsr;
	138	int     m_rxbits, m_txbits, m_txstate, m_trcsr_read_tdre, m_trcsr_read_orfe, m_trcsr_read_rdrf, m_tx;
	139	int     m_port2_written;
	140
	141	int     m_icount;
	142	int     m_latch09;
	143
	144	PAIR    m_timer_over;
	145	emu_timer *m_sci_timer;
	146	PAIR m_ea;        /* effective address */
	147
	148	static const UINT8 flags8i[256];
	149	static const UINT8 flags8d[256];
	150	static const UINT8 cycles_6800[256];
	151	static const UINT8 cycles_6803[256];
	152	static const UINT8 cycles_63701[256];
	153	static const UINT8 cycles_nsc8105[256];
	154	static const op_func m6800_insn[256];
	155	static const op_func m6803_insn[256];
	156	static const op_func hd63701_insn[256];
	157	static const op_func nsc8105_insn[256];
	158
	159	UINT32 RM16(UINT32 Addr );
	160	void WM16(UINT32 Addr, PAIR *p );
	161	void enter_interrupt(const char *message,UINT16 irq_vector);
	162	void m6800_check_irq2();
	163	void CHECK_IRQ_LINES();
	164	void check_timer_event();
	165	void increment_counter(int amount);
	166	void set_rmcr(UINT8 data);
	167	void write_port2();
	168	int m6800_rx();
	169	void serial_transmit();
	170	void serial_receive();
	171	TIMER_CALLBACK_MEMBER( sci_tick );
	172	void set_os3(int state);
	173
	174	void aba();
	175	void abx();
	176	void adca_di();
	177	void adca_ex();
	178	void adca_im();
	179	void adca_ix();
	180	void adcb_di();
	181	void adcb_ex();
	182	void adcb_im();
	183	void adcb_ix();
	184	void adcx_im();
	185	void adda_di();
	186	void adda_ex();
	187	void adda_im();
	188	void adda_ix();
	189	void addb_di();
	190	void addb_ex();
	191	void addb_im();
	192	void addb_ix();
	193	void addd_di();
	194	void addd_ex();
	195	void addx_ex();
	196	void addd_im();
	197	void addd_ix();
	198	void aim_di();
	199	void aim_ix();
	200	void anda_di();
	201	void anda_ex();
	202	void anda_im();
	203	void anda_ix();
	204	void andb_di();
	205	void andb_ex();
	206	void andb_im();
	207	void andb_ix();
	208	void asl_ex();
	209	void asl_ix();
	210	void asla();
	211	void aslb();
	212	void asld();
	213	void asr_ex();
	214	void asr_ix();
	215	void asra();
	216	void asrb();
	217	void bcc();
	218	void bcs();
	219	void beq();
	220	void bge();
	221	void bgt();
	222	void bhi();
	223	void bita_di();
	224	void bita_ex();
	225	void bita_im();
	226	void bita_ix();
	227	void bitb_di();
	228	void bitb_ex();
	229	void bitb_im();
	230	void bitb_ix();
	231	void ble();
	232	void bls();
	233	void blt();
	234	void bmi();
	235	void bne();
	236	void bpl();
	237	void bra();
	238	void brn();
	239	void bsr();
	240	void bvc();
	241	void bvs();
	242	void cba();
	243	void clc();
	244	void cli();
	245	void clr_ex();
	246	void clr_ix();
	247	void clra();
	248	void clrb();
	249	void clv();
	250	void cmpa_di();
	251	void cmpa_ex();
	252	void cmpa_im();
	253	void cmpa_ix();
	254	void cmpb_di();
	255	void cmpb_ex();
	256	void cmpb_im();
	257	void cmpb_ix();
	258	void cmpx_di();
	259	void cmpx_ex();
	260	void cmpx_im();
	261	void cmpx_ix();
	262	void com_ex();
	263	void com_ix();
	264	void coma();
	265	void comb();
	266	void daa();
	267	void dec_ex();
	268	void dec_ix();
	269	void deca();
	270	void decb();
	271	void des();
	272	void dex();
	273	void eim_di();
	274	void eim_ix();
	275	void eora_di();
	276	void eora_ex();
	277	void eora_im();
	278	void eora_ix();
	279	void eorb_di();
	280	void eorb_ex();
	281	void eorb_im();
	282	void eorb_ix();
	283	void illegal();
	284	void inc_ex();
	285	void inc_ix();
	286	void inca();
	287	void incb();
	288	void ins();
	289	void inx();
	290	void jmp_ex();
	291	void jmp_ix();
	292	void jsr_di();
	293	void jsr_ex();
	294	void jsr_ix();
	295	void lda_di();
	296	void lda_ex();
	297	void lda_im();
	298	void lda_ix();
	299	void ldb_di();
	300	void ldb_ex();
	301	void ldb_im();
	302	void ldb_ix();
	303	void ldd_di();
	304	void ldd_ex();
	305	void ldd_im();
	306	void ldd_ix();
	307	void lds_di();
	308	void lds_ex();
	309	void lds_im();
	310	void lds_ix();
	311	void ldx_di();
	312	void ldx_ex();
	313	void ldx_im();
	314	void ldx_ix();
	315	void lsr_ex();
	316	void lsr_ix();
	317	void lsra();
	318	void lsrb();
	319	void lsrd();
	320	void mul();
	321	void neg_ex();
	322	void neg_ix();
	323	void nega();
	324	void negb();
	325	void nop();
	326	void oim_di();
	327	void oim_ix();
	328	void ora_di();
	329	void ora_ex();
	330	void ora_im();
	331	void ora_ix();
	332	void orb_di();
	333	void orb_ex();
	334	void orb_im();
	335	void orb_ix();
	336	void psha();
	337	void pshb();
	338	void pshx();
	339	void pula();
	340	void pulb();
	341	void pulx();
	342	void rol_ex();
	343	void rol_ix();
	344	void rola();
	345	void rolb();
	346	void ror_ex();
	347	void ror_ix();
	348	void rora();
	349	void rorb();
	350	void rti();
	351	void rts();
	352	void sba();
	353	void sbca_di();
	354	void sbca_ex();
	355	void sbca_im();
	356	void sbca_ix();
	357	void sbcb_di();
	358	void sbcb_ex();
	359	void sbcb_im();
	360	void sbcb_ix();
	361	void sec();
	362	void sei();
	363	void sev();
	364	void slp();
	365	void sta_di();
	366	void sta_ex();
	367	void sta_im();
	368	void sta_ix();
	369	void stb_di();
	370	void stb_ex();
	371	void stb_im();
	372	void stb_ix();
	373	void std_di();
	374	void std_ex();
	375	void std_im();
	376	void std_ix();
	377	void sts_di();
	378	void sts_ex();
	379	void sts_im();
	380	void sts_ix();
	381	void stx_di();
	382	void stx_ex();
	383	void stx_im();
	384	void stx_ix();
	385	void suba_di();
	386	void suba_ex();
	387	void suba_im();
	388	void suba_ix();
	389	void subb_di();
	390	void subb_ex();
	391	void subb_im();
	392	void subb_ix();
	393	void subd_di();
	394	void subd_ex();
	395	void subd_im();
	396	void subd_ix();
	397	void swi();
	398	void tab();
	399	void tap();
	400	void tba();
	401	void tim_di();
	402	void tim_ix();
	403	void tpa();
	404	void tst_ex();
	405	void tst_ix();
	406	void tsta();
	407	void tstb();
	408	void tsx();
	409	void txs();
	410	void undoc1();
	411	void undoc2();
	412	void wai();
	413	void xgdx();
	414	void cpx_di();
	415	void cpx_ex();
	416	void cpx_im();
	417	void cpx_ix();
	418	void trap();
	419	};
	420
	421
	422	class m6801_cpu_device : public m6800_cpu_device
	423	{
	424	public:
	425	m6801_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	426	m6801_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, const m6800_cpu_device::op_func *insn, const UINT8 *cycles, address_map_constructor internal = NULL);
	427
	428	protected:
	429	virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 4 - 1) / 4; }
	430	virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 4); }
	431	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	432	};
	433
	434
	435	class m6802_cpu_device : public m6800_cpu_device
	436	{
	437	public:
	438	m6802_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	439	m6802_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, const m6800_cpu_device::op_func *insn, const UINT8 *cycles);
	440
	441	protected:
	442	virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 4 - 1) / 4; }
	443	virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 4); }
	444	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	445	};
	446
	447
	448	class m6803_cpu_device : public m6801_cpu_device
	449	{
	450	public:
	451	m6803_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	452
	453	protected:
	454	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	455	};
	456
	457
	458	class m6808_cpu_device : public m6802_cpu_device
	459	{
	460	public:
	461	m6808_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	462
	463	protected:
	464	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	465	};
	466
	467
	468	class hd6301_cpu_device : public m6801_cpu_device
	469	{
	470	public:
	471	hd6301_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	472	hd6301_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
	473
	474	protected:
	475	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	476	};
	477
	478
	479	class hd63701_cpu_device : public m6801_cpu_device
	480	{
	481	public:
	482	hd63701_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	483
	484	protected:
	485	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	486	};
	487
	488
	489	class nsc8105_cpu_device : public m6802_cpu_device
	490	{
	491	public:
	492	nsc8105_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	493
	494	protected:
	495	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	496	};
	497
	498
	499	// DP-40 package: HD6303RP,  HD63A03RP,  HD63B03RP,
	500	// FP-54 package: HD6303RF,  HD63A03RF,  HD63B03RF,
	501	// CG-40 package: HD6303RCG, HD63A03RCG, HD63B03RCG,
	502	// Not fully emulated yet
	503	class hd6303r_cpu_device : public hd6301_cpu_device
	504	{
	505	public:
	506	hd6303r_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	507	};
	508
	509
	510	// DP-64S package: HD6303YP,  HD63A03YP,  HD63B03YP,  HD63C03YP
	511	// FP-64  package: HD6303YF,  HD63A03YF,  HD63B03YF,  HD63C03YF
	512	// FP-64A package: HD6303YH,  HD63A03YH,  HD63B03YH,  HD63C03YH
	513	// CP-68  package: HD6303YCP, HD63A03YCP, HD63B03YCP, HD63C03YCP
	514	// Not fully emulated yet
	515	class hd6303y_cpu_device : public hd6301_cpu_device
	516	{
	517	public:
	518	hd6303y_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	519	};
	520
	521
	522	extern const device_type M6800;
	523	extern const device_type M6801;
	524	extern const device_type M6802;
	525	extern const device_type M6803;
	526	extern const device_type M6808;
	527	extern const device_type HD6301;
	528	extern const device_type HD63701;
	529	extern const device_type NSC8105;
	530	extern const device_type HD6303R;
	531	extern const device_type HD6303Y;
	532
78	533	#endif /* __M6800_H__ */

trunk/src/mess/machine/adam_fdc.c

r24794	r24795
68	68	//-------------------------------------------------
69	69
70	70	static ADDRESS_MAP_START( adam_fdc_mem, AS_PROGRAM, 8, adam_fdc_device )
71		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r, m6801_io_w)
	71	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE(M6801_TAG, m6801_cpu_device, m6801_io_r, m6801_io_w)
72	72	AM_RANGE(0x0080, 0x00ff) AM_RAM
73	73	AM_RANGE(0x0400, 0x07ff) AM_RAM AM_WRITEONLY AM_SHARE("ram")
74	74	AM_RANGE(0x0800, 0x0800) AM_MIRROR(0xff) AM_DEVREAD(WD2793_TAG, wd2793_t, status_r)

trunk/src/mess/machine/adam_spi.c

r24794	r24795
51	51	//-------------------------------------------------
52	52
53	53	static ADDRESS_MAP_START( adam_spi_mem, AS_PROGRAM, 8, adam_spi_device )
54		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r, m6801_io_w)
	54	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE(M6801_TAG, m6801_cpu_device, m6801_io_r, m6801_io_w)
55	55	AM_RANGE(0x0080, 0x00ff) AM_RAM
56	56	AM_RANGE(0xf800, 0xffff) AM_ROM AM_REGION(M6801_TAG, 0)
57	57	ADDRESS_MAP_END

trunk/src/mess/machine/adam_kb.c

r24794	r24795
51	51	//-------------------------------------------------
52	52
53	53	static ADDRESS_MAP_START( adam_kb_mem, AS_PROGRAM, 8, adam_keyboard_device )
54		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r, m6801_io_w)
	54	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE(M6801_TAG, m6801_cpu_device, m6801_io_r, m6801_io_w)
55	55	AM_RANGE(0x0080, 0x00ff) AM_RAM
56	56	AM_RANGE(0xf800, 0xffff) AM_ROM AM_REGION(M6801_TAG, 0)
57	57	ADDRESS_MAP_END

trunk/src/mess/machine/pf10.c

r24794	r24795
26	26	//-------------------------------------------------
27	27
28	28	static ADDRESS_MAP_START( cpu_mem, AS_PROGRAM, 8, epson_pf10_device )
29		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r, m6801_io_w)
	29	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE("maincpu", hd6303y_cpu_device, m6801_io_r, m6801_io_w)
30	30	AM_RANGE(0x0040, 0x00ff) AM_RAM /* 192 bytes internal ram */
31	31	AM_RANGE(0x0800, 0x0fff) AM_RAM /* external 2k ram */
32	32	AM_RANGE(0xe000, 0xffff) AM_ROM AM_REGION("maincpu", 0)

trunk/src/mess/machine/adam_prn.c

r24794	r24795
51	51	//-------------------------------------------------
52	52
53	53	static ADDRESS_MAP_START( adam_prn_mem, AS_PROGRAM, 8, adam_printer_device )
54		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r, m6801_io_w)
	54	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE(M6801_TAG, m6801_cpu_device, m6801_io_r, m6801_io_w)
55	55	AM_RANGE(0x0080, 0x00ff) AM_RAM
56	56	AM_RANGE(0xf800, 0xffff) AM_ROM AM_REGION(M6801_TAG, 0)
57	57	ADDRESS_MAP_END

trunk/src/mess/machine/adam_ddp.c

r24794	r24795
51	51	//-------------------------------------------------
52	52
53	53	static ADDRESS_MAP_START( adam_ddp_mem, AS_PROGRAM, 8, adam_digital_data_pack_device )
54		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r, m6801_io_w)
	54	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE(M6801_TAG, m6801_cpu_device, m6801_io_r, m6801_io_w)
55	55	AM_RANGE(0x0080, 0x00ff) AM_RAM
56	56	AM_RANGE(0x0400, 0x07ff) AM_RAM
57	57	AM_RANGE(0xf800, 0xffff) AM_ROM AM_REGION(M6801_TAG, 0)

trunk/src/mess/includes/psion.h

r24794	r24795
30	30	m_sys_register(*this, "sys_register"),
31	31	m_ram(*this, "ram"){ }
32	32
33		required_device<cpu_device> m_maincpu;
	33	required_device<hd63701_cpu_device> m_maincpu;
34	34	required_device<hd44780_device> m_lcdc;
35	35	required_device<beep_device> m_beep;
36	36	required_device<datapack_device> m_pack1;

trunk/src/mess/drivers/atarist.c

r24794	r24795
1183	1183	//-------------------------------------------------
1184	1184
1185	1185	static ADDRESS_MAP_START( ikbd_map, AS_PROGRAM, 8, st_state )
1186		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r, m6801_io_w)
	1186	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE(HD6301V1_TAG, hd6301_cpu_device, m6801_io_r, m6801_io_w)
1187	1187	AM_RANGE(0x0080, 0x00ff) AM_RAM
1188	1188	AM_RANGE(0xf000, 0xffff) AM_ROM AM_REGION(HD6301V1_TAG, 0)
1189	1189	ADDRESS_MAP_END

trunk/src/mess/drivers/hx20.c

r24794	r24795
537	537	//-------------------------------------------------
538	538
539	539	static ADDRESS_MAP_START( hx20_mem, AS_PROGRAM, 8, hx20_state )
540		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r, m6801_io_w)
	540	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE(HD6301V1_MAIN_TAG, hd63701_cpu_device, m6801_io_r, m6801_io_w)
541	541	AM_RANGE(0x0020, 0x0020) AM_WRITE(ksc_w)
542	542	AM_RANGE(0x0022, 0x0022) AM_READ(krtn07_r)
543	543	AM_RANGE(0x0026, 0x0026) AM_WRITE(lcd_cs_w)
r24794	r24795
568	568	//-------------------------------------------------
569	569
570	570	static ADDRESS_MAP_START( hx20_sub_mem, AS_PROGRAM, 8, hx20_state )
571		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r, m6801_io_w)
	571	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE(HD6301V1_SLAVE_TAG, hd63701_cpu_device, m6801_io_r, m6801_io_w)
572	572	AM_RANGE(0x0080, 0x00ff) AM_RAM
573	573	AM_RANGE(0xf000, 0xffff) AM_ROM AM_REGION(HD6301V1_SLAVE_TAG, 0)
574	574	ADDRESS_MAP_END

trunk/src/mess/drivers/mc10.c

r24794	r24795
47	47	m_printer(*this, "printer")
48	48	{ }
49	49
50		required_device<cpu_device> m_maincpu;
	50	required_device<m6803_cpu_device> m_maincpu;
51	51	optional_device<mc6847_base_device> m_mc6847;
52	52	optional_device<ef9345_device> m_ef9345;
53	53	required_device<dac_device> m_dac;
r24794	r24795
260	260
261	261	//for alice32 force port4 DDR to 0xff at startup
262	262	if (!strcmp(machine().system().name, "alice32") || !strcmp(machine().system().name, "alice90"))
263		m6801_io_w(prg, 0x05, 0xff);
	263	m_maincpu->m6801_io_w(prg, 0x05, 0xff);
264	264	}
265	265
266	266

trunk/src/mess/drivers/psion.c

r24794	r24795
100	100	break;
101	101	}
102	102
103		m6801_io_w(space, offset, data);
	103	m_maincpu->m6801_io_w(space, offset, data);
104	104	}
105	105
106	106	READ8_MEMBER( psion_state::hd63701_int_reg_r )
r24794	r24795
111	111	/* datapack i/o data bus */
112	112	return (m_pack1->data_r() | m_pack2->data_r()) & (~m_port2_ddr);
113	113	case 0x14:
114		return (m6801_io_r(space, offset)&0x7f) | (m_stby_pwr<<7);
	114	return (m_maincpu->m6801_io_r(space, offset)&0x7f) | (m_stby_pwr<<7);
115	115	case 0x15:
116	116	/*
117	117	x--- ---- ON key active high
r24794	r24795
124	124	/* datapack control lines */
125	125	return (m_pack1->control_r() | (m_pack2->control_r() & 0x8f)) | ((m_pack2->control_r() & 0x10)<<1);
126	126	case 0x08:
127		m6801_io_w(space, offset, m_tcsr_value);
	127	m_maincpu->m6801_io_w(space, offset, m_tcsr_value);
128	128	default:
129		return m6801_io_r(space, offset);
	129	return m_maincpu->m6801_io_r(space, offset);
130	130	}
131	131	}
132	132

trunk/src/mess/drivers/adam.c

r24794	r24795
931	931	//-------------------------------------------------
932	932
933	933	static ADDRESS_MAP_START( m6801_mem, AS_PROGRAM, 8, adam_state )
934		AM_RANGE(0x0000, 0x001f) AM_READWRITE_LEGACY(m6801_io_r, m6801_io_w)
	934	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE(M6801_TAG, m6801_cpu_device, m6801_io_r, m6801_io_w)
935	935	AM_RANGE(0x0080, 0x00ff) AM_RAM
936	936	AM_RANGE(0xf800, 0xffff) AM_ROM AM_REGION(M6801_TAG, 0)
937	937	ADDRESS_MAP_END
r24794	r24795
1011	1011	}
1012	1012	}
1013	1013
1014		static M6801_INTERFACE( m6801_intf )
1015		{
1016		DEVCB_DRIVER_LINE_MEMBER(adam_state, os3_w)
1017		};
1018	1014
1019
1020	1015	//-------------------------------------------------
1021	1016	//  ADAM_EXPANSION_SLOT_INTERFACE( slot1_intf )
1022	1017	//-------------------------------------------------
r24794	r24795
1116	1111	MCFG_CPU_ADD(M6801_TAG, M6801, XTAL_4MHz)
1117	1112	MCFG_CPU_PROGRAM_MAP(m6801_mem)
1118	1113	MCFG_CPU_IO_MAP(m6801_io)
1119		MCFG_CPU_CONFIG(m6801_intf)
	1114	MCFG_M6801_SC2(WRITELINE(adam_state, os3_w))
1120	1115	MCFG_QUANTUM_PERFECT_CPU(M6801_TAG)
1121	1116
1122	1117	// video hardware

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