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r24794 Wednesday 7th August, 2013 at 17:10:39 UTC by Ville Linde
tms32082: more PP disasm fixes (nw)

[src/emu/cpu/tms32082]

dis_pp.c

trunk/src/emu/cpu/tms32082/dis_pp.c

r24793	r24794
31	31	"???",      "???",      "???",      "???",      "tag0",      "tag1",      "tag2",      "tag3"
32	32	};
33	33
	34	static const char *CONDITION_CODES[16] =
	35	{
	36	"",         "[p] ",      "[ls] ",   "[hi] ",
	37	"[lt] ",   "[le] ",   "[ge] ",   "[gt] ",
	38	"[hs] ",   "[lo] ",   "[eq] ",   "[ne] ",
	39	"[v] ",      "[nv] ",   "[n] ",      "[nn] "
	40	};
34	41
	42	static const char *TRANSFER_SIZE[4] =
	43	{
	44	"b:", "h:", "w:", ""
	45	};
	46
	47
35	48	static char *output;
36	49
37	50	static void ATTR_PRINTF(1,2) print(const char *fmt, ...)
r24793	r24794
43	56	va_end(vl);
44	57	}
45	58
	59	static char *format_address_mode(int mode, int areg, int s, int limx)
	60	{
	61	static char buffer[64];
	62
	63	memset(buffer, 0, sizeof(char)*64);
	64
	65	switch (mode)
	66	{
	67	case 0x4: sprintf(buffer, "*(a%d++=x%d)", areg, limx); break;
	68	case 0x5: sprintf(buffer, "*(a%d--=x%d)", areg, limx); break;
	69	case 0x6: sprintf(buffer, "*(a%d++0x%04X)", areg, limx); break;
	70	case 0x7: sprintf(buffer, "*(a%d--0x%04X)", areg, limx); break;
	71	case 0x8: sprintf(buffer, "*(a%d+x%d)", areg, limx); break;
	72	case 0x9: sprintf(buffer, "*(a%d-x%d)", areg, limx); break;
	73	case 0xa: sprintf(buffer, "*(a%d+0x%04X)", areg, limx); break;
	74	case 0xb: sprintf(buffer, "*(a%d-0x%04X)", areg, limx); break;
	75	case 0xc: sprintf(buffer, "*(a%d+=x%d)", areg, limx); break;
	76	case 0xd: sprintf(buffer, "*(a%d-=x%d)", areg, limx); break;
	77	case 0xe: sprintf(buffer, "*(a%d+=0x%04X)", areg, limx); break;
	78	case 0xf: sprintf(buffer, "*(a%d-=0x%04X)", areg, limx); break;
	79	}
	80
	81	return buffer;
	82	}
	83
46	84	static void format_transfer(UINT64 op)
47	85	{
48	86	int lmode = (op >> 35) & 0xf;
49	87	int gmode = (op >> 13) & 0xf;
50	88
51		print(" | ");
	89	print(" || ");
52	90
53	91	switch (lmode)
54	92	{
r24793	r24794
57	95	case 0x2:
58	96	case 0x3:
59	97	{
	98	int cond = (op >> 32) & 0xf;
	99
60	100	switch (gmode)
61	101	{
62		case 0x00:
	102	case 0x00:                              // Format 7: Conditional DU || Conditional Move
63	103	{
64	104	int dstbank = (op >> 18) & 0xf;
65	105	int srcbank = (op >> 6) & 0xf;
r24793	r24794
69	109	int dreg = (dstbank << 3) | dst;
70	110	int sreg = (srcbank << 3) | src;
71	111
72		print("cond du||cond move %s = %s", REG_NAMES[dreg], REG_NAMES[sreg]);
	112	print("%s", CONDITION_CODES[cond]);
	113	print("%s = %s", REG_NAMES[dreg], REG_NAMES[sreg]);
73	114	break;
74	115	}
75		case 0x01:
	116	case 0x01:                              // Format 8: Conditional DU ||Conditional Field Move
76	117	{
77		print("cond du||cond field move");
	118	int dstbank = (op >> 18) & 0xf;
	119	int src = (op >> 10) & 0x7;
	120	int dst = (op >> 3) & 0x7;
	121	int itm = (op >> 22) & 0x3;
	122	int size = (op >> 7) & 0x3;
	123	//      int e = (op & (1 << 9));
	124
	125	int dreg = (dstbank << 3) | dst;
	126	int sreg = (4 << 3) | src;
	127
	128	print("%s", CONDITION_CODES[cond]);
	129	print("%s = [%s:%d]%s", REG_NAMES[dreg], TRANSFER_SIZE[size], itm, REG_NAMES[sreg]);
78	130	break;
79	131	}
80		case 0x02: case 0x03:
	132	case 0x02: case 0x03:                     // Format 10: Conditional Non-D Data Unit
81	133	{
82		print("cond non-d du");
	134	int as1bank = (op >> 6) & 0xf;
	135	int adstbank = (op >> 18) & 0xf;
	136	int src = (op >> 45) & 0x7;
	137	int dst = (op >> 48) & 0x7;
	138
	139	int dreg = (adstbank << 3) | dst;
	140	int sreg = (as1bank << 3) | src;
	141
	142	if (dreg == 0x20 && sreg == 0x20)
	143	{
	144	print("nop");
	145	}
	146	else
	147	{
	148	print("%s", CONDITION_CODES[cond]);
	149	print("%s = %s", REG_NAMES[dreg], REG_NAMES[sreg]);
	150	}
83	151	break;
84	152	}
85	153	default:
86	154	{
87		if (op & 0x4)
	155	if (op & 0x4)                        // Format 9: Conditional DU || Conditional Global
88	156	{
	157	print("%s", CONDITION_CODES[cond]);
89	158	print("cond du||cond global");
90	159	}
91		else
	160	else                              // Format 5: Global (Long Offset)
92	161	{
93		print("global (long offset)");
	162	int bank = (op >> 18) & 0xf;
	163	int le = ((op >> 16) & 2) | ((op >> 9) & 1);
	164	int size = (op >> 7) & 0x3;
	165	int s = (op & (1 << 6));
	166	int offset = (op >> 22) & 0x7fff;
	167	int reg = (op >> 10) & 0x7;
	168	//int grm = op & 0x3;
	169	int ga = (op >> 3) & 0x7;
	170
	171	int greg = (bank << 3) | reg;
	172
	173	// sign extend offset
	174	if (s && (offset & 0x4000))
	175	offset |= 0xffffc000;
	176
	177	switch (le)
	178	{
	179	case 0: print("&%s%s = %s", TRANSFER_SIZE[size], format_address_mode(gmode, ga, s, offset), REG_NAMES[greg]); break;
	180	case 1: print("%s = %s", REG_NAMES[greg], format_address_mode(gmode, ga, s, offset)); break;
	181	case 2: print("%s = &%s%s", REG_NAMES[greg], TRANSFER_SIZE[size], format_address_mode(gmode, ga, s, offset)); break;
	182	case 3: print("%s = &%s%s", REG_NAMES[greg], TRANSFER_SIZE[size], format_address_mode(gmode, ga, s, offset)); break;
	183	}
94	184	}
95	185	break;
96	186	}
r24793	r24794
104	194
105	195	switch (mode)
106	196	{
107		case 0x00:
	197	case 0x00:                              // Format 2: Move || Local
108	198	{
109	199	print("move||local");
110	200	break;
111	201	}
112		case 0x01:
	202	case 0x01:                              // Format 3: Field Move || Local
113	203	{
114	204	print("field move||local");
115	205	break;
116	206	}
117		case 0x02: case 0x03:
	207	case 0x02: case 0x03:                     // Format 6: Non-D DU || Local
118	208	{
119	209	print("non-d du||local");
120	210	break;
121	211	}
122		case 0x10: case 0x11: case 0x12: case 0x13:
	212	case 0x10: case 0x11: case 0x12: case 0x13:      // Format 4: Local (Long Offset)
123	213	{
124	214	int d = (op >> 32) & 0x7;
125	215	int bank = (op >> 18) & 0xf;
r24793	r24794
142	232	offset = op & 0x7fff;
143	233	}
144	234
145		if (le == 0 && le == 1)
	235	switch (le)
146	236	{
147		print("%s = ", REG_NAMES[reg]);
	237	case 0: print("&%s%s = %s", TRANSFER_SIZE[size], format_address_mode(lmode, la, s, offset), REG_NAMES[reg]); break;
	238	case 1: print("%s = %s", REG_NAMES[reg], format_address_mode(lmode, la, s, offset)); break;
	239	case 2: print("%s = &%s%s", REG_NAMES[reg], TRANSFER_SIZE[size], format_address_mode(lmode, la, s, offset)); break;
	240	case 3: print("%s = &%s%s", REG_NAMES[reg], TRANSFER_SIZE[size], format_address_mode(lmode, la, s, offset)); break;
148	241	}
	242	break;
	243	}
	244	case 0x14: case 0x15: case 0x16: case 0x17:      // Format 1: Double Parallel
	245	case 0x18: case 0x19: case 0x1a: case 0x1b:
	246	case 0x1c: case 0x1d: case 0x1e: case 0x1f:
	247	{
	248	int la = (op >> 25) & 0x7;
	249	int ga = (op >> 3) & 0x7;
	250	int local_imx = op & 0x7;
	251	int global_imx = (op >> 22) & 0x7;
	252	int local_s = (op & (1 << 28));
	253	int global_s = (op & (1 << 6));
	254	int local_size = (op >> 29) & 0x3;
	255	int global_size = (op >> 7) & 0x3;
	256	int local_le = ((op >> 20) & 2) | ((op >> 31) & 1);
	257	int global_le = ((op >> 16) & 2) | ((op >> 9) & 1);
	258	int gbank = (op >> 18) & 0x7;
	259	int reg = (op >> 10) & 0x7;
	260	int d = (op >> 32) & 0x7;
149	261
150		switch (size)
	262	int greg = (gbank << 3) | reg;
	263	int lreg = (4 << 3) | d;
	264
	265	// local transfer
	266	switch (local_le)
151	267	{
152		case 0: print("b:"); break;
153		case 1: print("h:"); break;
	268	case 0: print("&%s%s = %s", TRANSFER_SIZE[local_size], format_address_mode(lmode, la, local_s, local_imx), REG_NAMES[lreg]); break;
	269	case 1: print("%s = %s", REG_NAMES[lreg], format_address_mode(lmode, la, local_s, local_imx)); break;
	270	case 2: print("%s = &%s%s", REG_NAMES[lreg], TRANSFER_SIZE[local_size], format_address_mode(lmode, la, local_s, local_imx)); break;
	271	case 3: print("%s = &%s%s", REG_NAMES[lreg], TRANSFER_SIZE[local_size], format_address_mode(lmode, la, local_s, local_imx)); break;
154	272	}
155	273
156		switch (lmode)
	274	print(", ");
	275
	276	// global transfer
	277	switch (global_le)
157	278	{
158		case 0x6: print("*(a%d++=0x%04X)", la, offset); break;
159		case 0x7: print("*(a%d--=0x%04X)", la, offset); break;
160		case 0xa: print("*(a%d+0x%04X)", la, offset); break;
161		case 0xb: print("*(a%d-0x%04X)", la, offset); break;
162		case 0xe: print("*(a%d+=0x%04X)", la, offset); break;
163		case 0xf: print("*(a%d-=0x%04X)", la, offset); break;
	279	case 0: print("&%s%s = %s", TRANSFER_SIZE[global_size], format_address_mode(gmode, ga, global_s, global_imx), REG_NAMES[greg]); break;
	280	case 1: print("%s = %s", REG_NAMES[greg], format_address_mode(gmode, ga, global_s, global_imx)); break;
	281	case 2: print("%s = &%s%s", REG_NAMES[greg], TRANSFER_SIZE[global_size], format_address_mode(gmode, ga, global_s, global_imx)); break;
	282	case 3: print("%s = &%s%s", REG_NAMES[greg], TRANSFER_SIZE[global_size], format_address_mode(gmode, ga, global_s, global_imx)); break;
164	283	}
165
166		if (le == 2)
167		print(" = %s", REG_NAMES[reg]);
168
169	284	break;
170	285	}
171		case 0x14: case 0x15: case 0x16: case 0x17:
172		case 0x18: case 0x19: case 0x1a: case 0x1b:
173		case 0x1c: case 0x1d: case 0x1e: case 0x1f:
174		{
175		print("double parallel");
176		break;
177		}
178	286	}
179	287	}
180	288	}
r24793	r24794
248	356	print("%s = %s & %s", dst_text, b_text, c_text);
249	357	break;
250	358
	359	case 0xea:      //  A &  B &  C | ~A &  B &  C |  A & ~B &  C |
	360	//  A &  B & ~C |  A & ~B & ~C                             = A | C
	361	print("%s = %s | %s", dst_text, a_text, c_text);
	362	break;
	363
	364	case 0xee:      //  A &  B &  C | ~A &  B &  C |  A & ~B &  C |
	365	//  A &  B & ~C | ~A &  B & ~C |  A & ~B & ~C              = A | B
	366	print("%s = %s | %s", dst_text, a_text, b_text);
	367	break;
	368
251	369	default:
252	370	print("%s = b%02X(%s, %s, %s)", dst_text, aluop, a_text, b_text, c_text);
253	371	break;
r24793	r24794
284	402	if ((op & U64(0xfaa8100000000000)) == U64(0x8800000000000000))
285	403	{
286	404	int operation = (op >> 39) & 0x1f;
287		UINT64 parallel_xfer = (op & U64(0x0000003fffffffff));
	405	UINT64 parallel_xfer = (op & U64(0x0000007fffffffff));
288	406
289	407	switch (operation)
290	408	{
r24793	r24794
308	426	case 0:
309	427	case 1:      // Base set ALU (5-bit immediate)
310	428	{
311		UINT64 parallel_xfer = (op & U64(0x0000003fffffffff));
	429	UINT64 parallel_xfer = (op & U64(0x0000007fffffffff));
312	430
313	431	int dst = (op >> 48) & 7;
314	432	int src1 = (op >> 45) & 7;
r24793	r24794
373	491
374	492	case 2:      // Base set ALU (reg src2)
375	493	{
376		UINT64 parallel_xfer = (op & U64(0x0000003fffffffff));
	494	UINT64 parallel_xfer = (op & U64(0x0000007fffffffff));
377	495
378	496	int dst = (op >> 48) & 7;
379	497	int src1 = (op >> 45) & 7;
r24793	r24794
391	509	switch (cl)
392	510	{
393	511	case 0:
394		sprintf(a_text, "%s", REG_NAMES[s1reg]);
	512	sprintf(a_text, "%s", REG_NAMES[s2reg]);
395	513	sprintf(b_text, "%s", REG_NAMES[s1reg]);
396	514	sprintf(c_text, "@mf");
397	515	break;
r24793	r24794
403	521	case 2:
404	522	sprintf(a_text, "%s", REG_NAMES[dstcreg]);
405	523	sprintf(b_text, "%s", REG_NAMES[s1reg]);
406		sprintf(c_text, "%%%s", REG_NAMES[s1reg]);
	524	sprintf(c_text, "%%%s", REG_NAMES[s2reg]);
407	525	break;
408	526	case 3:
409	527	sprintf(a_text, "%s", REG_NAMES[dstcreg]);
r24793	r24794
443	561	int src1 = (op >> 45) & 7;
444	562	int dstbank = (op >> 39) & 0xf;
445	563	int s1bank = (op >> 36) & 7;
446		//      int cond = (op >> 32) & 0xf;
	564	int cond = (op >> 32) & 0xf;
447	565	int cl = (op >> 60) & 7;
448	566	int aluop = (op >> 51) & 0xff;
449	567	int a = (op >> 59) & 1;
r24793	r24794
498	616	break;
499	617	}
500	618
	619	print("%s", CONDITION_CODES[cond]);
	620
501	621	format_alu_op(aluop, a, dst_text, a_text, b_text, c_text);
502	622	break;
503	623	}

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